1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright 2016 Freescale Semiconductor, Inc.
8 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 #include <linux/regmap.h>
12 #include <linux/sizes.h>
13 #include <linux/thermal.h>
15 #include "thermal_core.h"
16 #include "thermal_hwmon.h"
19 #define TMR_DISABLE 0x0
20 #define TMR_ME 0x80000000
21 #define TMR_ALPF 0x0c000000
22 #define TMR_ALPF_V2 0x03000000
23 #define TMTMIR_DEFAULT 0x0000000f
24 #define TIER_DISABLE 0x0
25 #define TEUMR0_V2 0x51009c00
29 #define REGS_TMR 0x000 /* Mode Register */
30 #define TMR_DISABLE 0x0
31 #define TMR_ME 0x80000000
32 #define TMR_ALPF 0x0c000000
33 #define TMR_MSITE_ALL GENMASK(15, 0)
35 #define REGS_TMTMIR 0x008 /* Temperature measurement interval Register */
36 #define TMTMIR_DEFAULT 0x0000000f
38 #define REGS_V2_TMSR 0x008 /* monitor site register */
40 #define REGS_V2_TMTMIR 0x00c /* Temperature measurement interval Register */
42 #define REGS_TIER 0x020 /* Interrupt Enable Register */
43 #define TIER_DISABLE 0x0
46 #define REGS_TTCFGR 0x080 /* Temperature Configuration Register */
47 #define REGS_TSCFGR 0x084 /* Sensor Configuration Register */
49 #define REGS_TRITSR(n) (0x100 + 16 * (n)) /* Immediate Temperature
52 #define TRITSR_V BIT(31)
53 #define REGS_TTRnCR(n) (0xf10 + 4 * (n)) /* Temperature Range n
56 #define REGS_IPBRR(n) (0xbf8 + 4 * (n)) /* IP Block Revision
59 #define REGS_V2_TEUMR(n) (0xf00 + 4 * (n))
68 struct qoriq_tmu_data
{
70 struct regmap
*regmap
;
72 struct qoriq_sensor sensor
[SITES_MAX
];
75 static struct qoriq_tmu_data
*qoriq_sensor_to_data(struct qoriq_sensor
*s
)
77 return container_of(s
, struct qoriq_tmu_data
, sensor
[s
->id
]);
80 static int tmu_get_temp(void *p
, int *temp
)
82 struct qoriq_sensor
*qsensor
= p
;
83 struct qoriq_tmu_data
*qdata
= qoriq_sensor_to_data(qsensor
);
86 * REGS_TRITSR(id) has the following layout:
88 * 31 ... 7 6 5 4 3 2 1 0
91 * Where V bit signifies if the measurement is ready and is
92 * within sensor range. TEMP is an 8 bit value representing
95 if (regmap_read_poll_timeout(qdata
->regmap
,
96 REGS_TRITSR(qsensor
->id
),
103 *temp
= (val
& 0xff) * 1000;
108 static const struct thermal_zone_of_device_ops tmu_tz_ops
= {
109 .get_temp
= tmu_get_temp
,
112 static int qoriq_tmu_register_tmu_zone(struct device
*dev
,
113 struct qoriq_tmu_data
*qdata
)
117 if (qdata
->ver
== TMU_VER1
) {
118 regmap_write(qdata
->regmap
, REGS_TMR
,
119 TMR_MSITE_ALL
| TMR_ME
| TMR_ALPF
);
121 regmap_write(qdata
->regmap
, REGS_V2_TMSR
, TMR_MSITE_ALL
);
122 regmap_write(qdata
->regmap
, REGS_TMR
, TMR_ME
| TMR_ALPF_V2
);
125 for (id
= 0; id
< SITES_MAX
; id
++) {
126 struct thermal_zone_device
*tzd
;
127 struct qoriq_sensor
*sensor
= &qdata
->sensor
[id
];
132 tzd
= devm_thermal_zone_of_sensor_register(dev
, id
,
135 ret
= PTR_ERR_OR_ZERO(tzd
);
140 regmap_write(qdata
->regmap
, REGS_TMR
, TMR_DISABLE
);
144 if (devm_thermal_add_hwmon_sysfs(tzd
))
146 "Failed to add hwmon sysfs attributes\n");
153 static int qoriq_tmu_calibration(struct device
*dev
,
154 struct qoriq_tmu_data
*data
)
158 const u32
*calibration
;
159 struct device_node
*np
= dev
->of_node
;
161 len
= of_property_count_u32_elems(np
, "fsl,tmu-range");
162 if (len
< 0 || len
> 4) {
163 dev_err(dev
, "invalid range data.\n");
167 val
= of_property_read_u32_array(np
, "fsl,tmu-range", range
, len
);
169 dev_err(dev
, "failed to read range data.\n");
173 /* Init temperature range registers */
174 for (i
= 0; i
< len
; i
++)
175 regmap_write(data
->regmap
, REGS_TTRnCR(i
), range
[i
]);
177 calibration
= of_get_property(np
, "fsl,tmu-calibration", &len
);
178 if (calibration
== NULL
|| len
% 8) {
179 dev_err(dev
, "invalid calibration data.\n");
183 for (i
= 0; i
< len
; i
+= 8, calibration
+= 2) {
184 val
= of_read_number(calibration
, 1);
185 regmap_write(data
->regmap
, REGS_TTCFGR
, val
);
186 val
= of_read_number(calibration
+ 1, 1);
187 regmap_write(data
->regmap
, REGS_TSCFGR
, val
);
193 static void qoriq_tmu_init_device(struct qoriq_tmu_data
*data
)
195 /* Disable interrupt, using polling instead */
196 regmap_write(data
->regmap
, REGS_TIER
, TIER_DISABLE
);
198 /* Set update_interval */
200 if (data
->ver
== TMU_VER1
) {
201 regmap_write(data
->regmap
, REGS_TMTMIR
, TMTMIR_DEFAULT
);
203 regmap_write(data
->regmap
, REGS_V2_TMTMIR
, TMTMIR_DEFAULT
);
204 regmap_write(data
->regmap
, REGS_V2_TEUMR(0), TEUMR0_V2
);
207 /* Disable monitoring */
208 regmap_write(data
->regmap
, REGS_TMR
, TMR_DISABLE
);
211 static const struct regmap_range qoriq_yes_ranges
[] = {
212 regmap_reg_range(REGS_TMR
, REGS_TSCFGR
),
213 regmap_reg_range(REGS_TTRnCR(0), REGS_TTRnCR(3)),
214 regmap_reg_range(REGS_V2_TEUMR(0), REGS_V2_TEUMR(2)),
215 regmap_reg_range(REGS_IPBRR(0), REGS_IPBRR(1)),
216 /* Read only registers below */
217 regmap_reg_range(REGS_TRITSR(0), REGS_TRITSR(15)),
220 static const struct regmap_access_table qoriq_wr_table
= {
221 .yes_ranges
= qoriq_yes_ranges
,
222 .n_yes_ranges
= ARRAY_SIZE(qoriq_yes_ranges
) - 1,
225 static const struct regmap_access_table qoriq_rd_table
= {
226 .yes_ranges
= qoriq_yes_ranges
,
227 .n_yes_ranges
= ARRAY_SIZE(qoriq_yes_ranges
),
230 static void qoriq_tmu_action(void *p
)
232 struct qoriq_tmu_data
*data
= p
;
234 regmap_write(data
->regmap
, REGS_TMR
, TMR_DISABLE
);
235 clk_disable_unprepare(data
->clk
);
238 static int qoriq_tmu_probe(struct platform_device
*pdev
)
242 struct qoriq_tmu_data
*data
;
243 struct device_node
*np
= pdev
->dev
.of_node
;
244 struct device
*dev
= &pdev
->dev
;
245 const bool little_endian
= of_property_read_bool(np
, "little-endian");
246 const enum regmap_endian format_endian
=
247 little_endian
? REGMAP_ENDIAN_LITTLE
: REGMAP_ENDIAN_BIG
;
248 const struct regmap_config regmap_config
= {
252 .rd_table
= &qoriq_rd_table
,
253 .wr_table
= &qoriq_wr_table
,
254 .val_format_endian
= format_endian
,
255 .max_register
= SZ_4K
,
259 data
= devm_kzalloc(dev
, sizeof(struct qoriq_tmu_data
),
264 base
= devm_platform_ioremap_resource(pdev
, 0);
265 ret
= PTR_ERR_OR_ZERO(base
);
267 dev_err(dev
, "Failed to get memory region\n");
271 data
->regmap
= devm_regmap_init_mmio(dev
, base
, ®map_config
);
272 ret
= PTR_ERR_OR_ZERO(data
->regmap
);
274 dev_err(dev
, "Failed to init regmap (%d)\n", ret
);
278 data
->clk
= devm_clk_get_optional(dev
, NULL
);
279 if (IS_ERR(data
->clk
))
280 return PTR_ERR(data
->clk
);
282 ret
= clk_prepare_enable(data
->clk
);
284 dev_err(dev
, "Failed to enable clock\n");
288 ret
= devm_add_action_or_reset(dev
, qoriq_tmu_action
, data
);
292 /* version register offset at: 0xbf8 on both v1 and v2 */
293 ret
= regmap_read(data
->regmap
, REGS_IPBRR(0), &ver
);
295 dev_err(&pdev
->dev
, "Failed to read IP block version\n");
298 data
->ver
= (ver
>> 8) & 0xff;
300 qoriq_tmu_init_device(data
); /* TMU initialization */
302 ret
= qoriq_tmu_calibration(dev
, data
); /* TMU calibration */
306 ret
= qoriq_tmu_register_tmu_zone(dev
, data
);
308 dev_err(dev
, "Failed to register sensors\n");
312 platform_set_drvdata(pdev
, data
);
317 static int __maybe_unused
qoriq_tmu_suspend(struct device
*dev
)
319 struct qoriq_tmu_data
*data
= dev_get_drvdata(dev
);
322 ret
= regmap_update_bits(data
->regmap
, REGS_TMR
, TMR_ME
, 0);
326 clk_disable_unprepare(data
->clk
);
331 static int __maybe_unused
qoriq_tmu_resume(struct device
*dev
)
334 struct qoriq_tmu_data
*data
= dev_get_drvdata(dev
);
336 ret
= clk_prepare_enable(data
->clk
);
340 /* Enable monitoring */
341 return regmap_update_bits(data
->regmap
, REGS_TMR
, TMR_ME
, TMR_ME
);
344 static SIMPLE_DEV_PM_OPS(qoriq_tmu_pm_ops
,
345 qoriq_tmu_suspend
, qoriq_tmu_resume
);
347 static const struct of_device_id qoriq_tmu_match
[] = {
348 { .compatible
= "fsl,qoriq-tmu", },
349 { .compatible
= "fsl,imx8mq-tmu", },
352 MODULE_DEVICE_TABLE(of
, qoriq_tmu_match
);
354 static struct platform_driver qoriq_tmu
= {
356 .name
= "qoriq_thermal",
357 .pm
= &qoriq_tmu_pm_ops
,
358 .of_match_table
= qoriq_tmu_match
,
360 .probe
= qoriq_tmu_probe
,
362 module_platform_driver(qoriq_tmu
);
364 MODULE_AUTHOR("Jia Hongtao <hongtao.jia@nxp.com>");
365 MODULE_DESCRIPTION("QorIQ Thermal Monitoring Unit driver");
366 MODULE_LICENSE("GPL v2");