drivers/thermal/samsung/exynos_tmu.h

   1 /*
   2  * exynos_tmu.h - Samsung EXYNOS TMU (Thermal Management Unit)
   3  *
   4  *  Copyright (C) 2011 Samsung Electronics
   5  *  Donggeun Kim <dg77.kim@samsung.com>
   6  *  Amit Daniel Kachhap <amit.daniel@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22
  23 #ifndef _EXYNOS_TMU_H
  24 #define _EXYNOS_TMU_H
  25 #include <linux/cpu_cooling.h>
  26
  27 #include "exynos_thermal_common.h"
  28
  29 enum calibration_type {
  30         TYPE_ONE_POINT_TRIMMING,
  31         TYPE_ONE_POINT_TRIMMING_25,
  32         TYPE_ONE_POINT_TRIMMING_85,
  33         TYPE_TWO_POINT_TRIMMING,
  34         TYPE_NONE,
  35 };
  36
  37 enum soc_type {
  38         SOC_ARCH_EXYNOS3250 = 1,
  39         SOC_ARCH_EXYNOS4210,
  40         SOC_ARCH_EXYNOS4412,
  41         SOC_ARCH_EXYNOS5250,
  42         SOC_ARCH_EXYNOS5260,
  43         SOC_ARCH_EXYNOS5420_TRIMINFO,
  44         SOC_ARCH_EXYNOS5440,
  45 };
  46
  47 /**
  48  * EXYNOS TMU supported features.
  49  * TMU_SUPPORT_EMULATION - This features is used to set user defined
  50  *                      temperature to the TMU controller.
  51  * TMU_SUPPORT_MULTI_INST - This features denotes that the soc
  52  *                      has many instances of TMU.
  53  * TMU_SUPPORT_TRIM_RELOAD - This features shows that trimming can
  54  *                      be reloaded.
  55  * TMU_SUPPORT_FALLING_TRIP - This features shows that interrupt can
  56  *                      be registered for falling trips also.
  57  * TMU_SUPPORT_READY_STATUS - This feature tells that the TMU current
  58  *                      state(active/idle) can be checked.
  59  * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
  60  *                      sample time.
  61  * TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
  62  *                      sensors shares some common registers.
  63  * TMU_SUPPORT - macro to compare the above features with the supplied.
  64  */
  65 #define TMU_SUPPORT_EMULATION                   BIT(0)
  66 #define TMU_SUPPORT_MULTI_INST                  BIT(1)
  67 #define TMU_SUPPORT_TRIM_RELOAD                 BIT(2)
  68 #define TMU_SUPPORT_FALLING_TRIP                BIT(3)
  69 #define TMU_SUPPORT_READY_STATUS                BIT(4)
  70 #define TMU_SUPPORT_EMUL_TIME                   BIT(5)
  71 #define TMU_SUPPORT_ADDRESS_MULTIPLE            BIT(6)
  72
  73 #define TMU_SUPPORTS(a, b)      (a->features & TMU_SUPPORT_ ## b)
  74
  75 /**
  76  * struct exynos_tmu_register - register descriptors to access registers and
  77  * bitfields. The register validity, offsets and bitfield values may vary
  78  * slightly across different exynos SOC's.
  79  * @triminfo_data: register containing 2 pont trimming data
  80  * @triminfo_ctrl: trim info controller register.
  81  * @triminfo_ctrl_count: the number of trim info controller register.
  82  * @tmu_ctrl: TMU main controller register.
  83  * @test_mux_addr_shift: shift bits of test mux address.
  84  * @therm_trip_mode_shift: shift bits of tripping mode in tmu_ctrl register.
  85  * @therm_trip_mode_mask: mask bits of tripping mode in tmu_ctrl register.
  86  * @therm_trip_en_shift: shift bits of tripping enable in tmu_ctrl register.
  87  * @tmu_status: register drescribing the TMU status.
  88  * @tmu_cur_temp: register containing the current temperature of the TMU.
  89  * @threshold_temp: register containing the base threshold level.
  90  * @threshold_th0: Register containing first set of rising levels.
  91  * @threshold_th1: Register containing second set of rising levels.
  92  * @threshold_th2: Register containing third set of rising levels.
  93  * @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
  94  * @tmu_inten: register containing the different threshold interrupt
  95         enable bits.
  96  * @inten_rise0_shift: shift bits of rising 0 interrupt bits.
  97  * @inten_rise1_shift: shift bits of rising 1 interrupt bits.
  98  * @inten_rise2_shift: shift bits of rising 2 interrupt bits.
  99  * @inten_rise3_shift: shift bits of rising 3 interrupt bits.
 100  * @inten_fall0_shift: shift bits of falling 0 interrupt bits.
 101  * @tmu_intstat: Register containing the interrupt status values.
 102  * @tmu_intclear: Register for clearing the raised interrupt status.
 103  * @emul_con: TMU emulation controller register.
 104  * @emul_temp_shift: shift bits of emulation temperature.
 105  * @emul_time_shift: shift bits of emulation time.
 106  * @tmu_irqstatus: register to find which TMU generated interrupts.
 107  * @tmu_pmin: register to get/set the Pmin value.
 108  */
 109 struct exynos_tmu_registers {
 110         u32     triminfo_data;
 111
 112         u32     triminfo_ctrl[MAX_TRIMINFO_CTRL_REG];
 113         u32     triminfo_ctrl_count;
 114
 115         u32     tmu_ctrl;
 116         u32     test_mux_addr_shift;
 117         u32     therm_trip_mode_shift;
 118         u32     therm_trip_mode_mask;
 119         u32     therm_trip_en_shift;
 120
 121         u32     tmu_status;
 122
 123         u32     tmu_cur_temp;
 124
 125         u32     threshold_temp;
 126
 127         u32     threshold_th0;
 128         u32     threshold_th1;
 129         u32     threshold_th2;
 130         u32     threshold_th3_l0_shift;
 131
 132         u32     tmu_inten;
 133         u32     inten_rise0_shift;
 134         u32     inten_rise1_shift;
 135         u32     inten_rise2_shift;
 136         u32     inten_rise3_shift;
 137         u32     inten_fall0_shift;
 138
 139         u32     tmu_intstat;
 140
 141         u32     tmu_intclear;
 142
 143         u32     emul_con;
 144         u32     emul_temp_shift;
 145         u32     emul_time_shift;
 146
 147         u32     tmu_irqstatus;
 148         u32     tmu_pmin;
 149 };
 150
 151 /**
 152  * struct exynos_tmu_platform_data
 153  * @threshold: basic temperature for generating interrupt
 154  *             25 <= threshold <= 125 [unit: degree Celsius]
 155  * @threshold_falling: differntial value for setting threshold
 156  *                     of temperature falling interrupt.
 157  * @trigger_levels: array for each interrupt levels
 158  *      [unit: degree Celsius]
 159  *      0: temperature for trigger_level0 interrupt
 160  *         condition for trigger_level0 interrupt:
 161  *              current temperature > threshold + trigger_levels[0]
 162  *      1: temperature for trigger_level1 interrupt
 163  *         condition for trigger_level1 interrupt:
 164  *              current temperature > threshold + trigger_levels[1]
 165  *      2: temperature for trigger_level2 interrupt
 166  *         condition for trigger_level2 interrupt:
 167  *              current temperature > threshold + trigger_levels[2]
 168  *      3: temperature for trigger_level3 interrupt
 169  *         condition for trigger_level3 interrupt:
 170  *              current temperature > threshold + trigger_levels[3]
 171  * @trigger_type: defines the type of trigger. Possible values are,
 172  *      THROTTLE_ACTIVE trigger type
 173  *      THROTTLE_PASSIVE trigger type
 174  *      SW_TRIP trigger type
 175  *      HW_TRIP
 176  * @trigger_enable[]: array to denote which trigger levels are enabled.
 177  *      1 = enable trigger_level[] interrupt,
 178  *      0 = disable trigger_level[] interrupt
 179  * @max_trigger_level: max trigger level supported by the TMU
 180  * @non_hw_trigger_levels: number of defined non-hardware trigger levels
 181  * @gain: gain of amplifier in the positive-TC generator block
 182  *      0 < gain <= 15
 183  * @reference_voltage: reference voltage of amplifier
 184  *      in the positive-TC generator block
 185  *      0 < reference_voltage <= 31
 186  * @noise_cancel_mode: noise cancellation mode
 187  *      000, 100, 101, 110 and 111 can be different modes
 188  * @type: determines the type of SOC
 189  * @efuse_value: platform defined fuse value
 190  * @min_efuse_value: minimum valid trimming data
 191  * @max_efuse_value: maximum valid trimming data
 192  * @first_point_trim: temp value of the first point trimming
 193  * @second_point_trim: temp value of the second point trimming
 194  * @default_temp_offset: default temperature offset in case of no trimming
 195  * @test_mux; information if SoC supports test MUX
 196  * @triminfo_reload: reload value to read TRIMINFO register
 197  * @cal_type: calibration type for temperature
 198  * @freq_clip_table: Table representing frequency reduction percentage.
 199  * @freq_tab_count: Count of the above table as frequency reduction may
 200  *      applicable to only some of the trigger levels.
 201  * @registers: Pointer to structure containing all the TMU controller registers
 202  *      and bitfields shifts and masks.
 203  * @features: a bitfield value indicating the features supported in SOC like
 204  *      emulation, multi instance etc
 205  *
 206  * This structure is required for configuration of exynos_tmu driver.
 207  */
 208 struct exynos_tmu_platform_data {
 209         u8 threshold;
 210         u8 threshold_falling;
 211         u8 trigger_levels[MAX_TRIP_COUNT];
 212         enum trigger_type trigger_type[MAX_TRIP_COUNT];
 213         bool trigger_enable[MAX_TRIP_COUNT];
 214         u8 max_trigger_level;
 215         u8 non_hw_trigger_levels;
 216         u8 gain;
 217         u8 reference_voltage;
 218         u8 noise_cancel_mode;
 219
 220         u32 efuse_value;
 221         u32 min_efuse_value;
 222         u32 max_efuse_value;
 223         u8 first_point_trim;
 224         u8 second_point_trim;
 225         u8 default_temp_offset;
 226         u8 test_mux;
 227         u8 triminfo_reload[MAX_TRIMINFO_CTRL_REG];
 228
 229         enum calibration_type cal_type;
 230         enum soc_type type;
 231         struct freq_clip_table freq_tab[4];
 232         unsigned int freq_tab_count;
 233         const struct exynos_tmu_registers *registers;
 234         unsigned int features;
 235 };
 236
 237 /**
 238  * struct exynos_tmu_init_data
 239  * @tmu_count: number of TMU instances.
 240  * @tmu_data: platform data of all TMU instances.
 241  * This structure is required to store data for multi-instance exynos tmu
 242  * driver.
 243  */
 244 struct exynos_tmu_init_data {
 245         int tmu_count;
 246         struct exynos_tmu_platform_data tmu_data[];
 247 };
 248
 249 #endif /* _EXYNOS_TMU_H */