drivers/thermal/samsung/exynos_tmu_data.c

   1 /*
   2  * exynos_tmu_data.c - Samsung EXYNOS tmu data file
   3  *
   4  *  Copyright (C) 2013 Samsung Electronics
   5  *  Amit Daniel Kachhap <amit.daniel@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  *
  21  */
  22
  23 #include "exynos_thermal_common.h"
  24 #include "exynos_tmu.h"
  25 #include "exynos_tmu_data.h"
  26
  27 #if defined(CONFIG_CPU_EXYNOS4210)
  28 static const struct exynos_tmu_registers exynos4210_tmu_registers = {
  29         .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
  30         .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
  31         .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
  32         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
  33         .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
  34         .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
  35         .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
  36         .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
  37         .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
  38         .tmu_status = EXYNOS_TMU_REG_STATUS,
  39         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
  40         .threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
  41         .threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
  42         .tmu_inten = EXYNOS_TMU_REG_INTEN,
  43         .inten_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
  44         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
  45         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
  46         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
  47         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
  48         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
  49 };
  50 struct exynos_tmu_platform_data const exynos4210_default_tmu_data = {
  51         .threshold = 80,
  52         .trigger_levels[0] = 5,
  53         .trigger_levels[1] = 20,
  54         .trigger_levels[2] = 30,
  55         .trigger_enable[0] = true,
  56         .trigger_enable[1] = true,
  57         .trigger_enable[2] = true,
  58         .trigger_enable[3] = false,
  59         .trigger_type[0] = THROTTLE_ACTIVE,
  60         .trigger_type[1] = THROTTLE_ACTIVE,
  61         .trigger_type[2] = SW_TRIP,
  62         .max_trigger_level = 4,
  63         .gain = 15,
  64         .reference_voltage = 7,
  65         .cal_type = TYPE_ONE_POINT_TRIMMING,
  66         .min_efuse_value = 40,
  67         .max_efuse_value = 100,
  68         .first_point_trim = 25,
  69         .second_point_trim = 85,
  70         .default_temp_offset = 50,
  71         .freq_tab[0] = {
  72                 .freq_clip_max = 800 * 1000,
  73                 .temp_level = 85,
  74         },
  75         .freq_tab[1] = {
  76                 .freq_clip_max = 200 * 1000,
  77                 .temp_level = 100,
  78         },
  79         .freq_tab_count = 2,
  80         .type = SOC_ARCH_EXYNOS4210,
  81         .registers = &exynos4210_tmu_registers,
  82 };
  83 #endif
  84
  85 #if defined(CONFIG_SOC_EXYNOS5250) || defined(CONFIG_SOC_EXYNOS4412)
  86 static const struct exynos_tmu_registers exynos5250_tmu_registers = {
  87         .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
  88         .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
  89         .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
  90         .triminfo_ctrl = EXYNOS_TMU_TRIMINFO_CON,
  91         .triminfo_reload_shift = EXYNOS_TRIMINFO_RELOAD_SHIFT,
  92         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
  93         .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
  94         .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
  95         .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
  96         .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
  97         .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
  98         .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
  99         .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
 100         .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
 101         .tmu_status = EXYNOS_TMU_REG_STATUS,
 102         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
 103         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
 104         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
 105         .tmu_inten = EXYNOS_TMU_REG_INTEN,
 106         .inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
 107         .inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
 108         .inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
 109         .inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
 110         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 111         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 112         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 113         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 114         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 115         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
 116         .emul_con = EXYNOS_EMUL_CON,
 117         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 118         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
 119         .emul_time_mask = EXYNOS_EMUL_TIME_MASK,
 120 };
 121 struct exynos_tmu_platform_data const exynos5250_default_tmu_data = {
 122         .threshold_falling = 10,
 123         .trigger_levels[0] = 85,
 124         .trigger_levels[1] = 103,
 125         .trigger_levels[2] = 110,
 126         .trigger_enable[0] = true,
 127         .trigger_enable[1] = true,
 128         .trigger_enable[2] = true,
 129         .trigger_enable[3] = false,
 130         .trigger_type[0] = THROTTLE_ACTIVE,
 131         .trigger_type[1] = THROTTLE_ACTIVE,
 132         .trigger_type[2] = SW_TRIP,
 133         .max_trigger_level = 4,
 134         .gain = 8,
 135         .reference_voltage = 16,
 136         .noise_cancel_mode = 4,
 137         .cal_type = TYPE_ONE_POINT_TRIMMING,
 138         .efuse_value = 55,
 139         .min_efuse_value = 40,
 140         .max_efuse_value = 100,
 141         .first_point_trim = 25,
 142         .second_point_trim = 85,
 143         .default_temp_offset = 50,
 144         .freq_tab[0] = {
 145                 .freq_clip_max = 800 * 1000,
 146                 .temp_level = 85,
 147         },
 148         .freq_tab[1] = {
 149                 .freq_clip_max = 200 * 1000,
 150                 .temp_level = 103,
 151         },
 152         .freq_tab_count = 2,
 153         .type = SOC_ARCH_EXYNOS,
 154         .registers = &exynos5250_tmu_registers,
 155 };
 156 #endif