2 * Thunderbolt Cactus Ridge driver - eeprom access
4 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
7 #include <linux/crc32.h>
8 #include <linux/property.h>
9 #include <linux/slab.h>
13 * tb_eeprom_ctl_write() - write control word
15 static int tb_eeprom_ctl_write(struct tb_switch
*sw
, struct tb_eeprom_ctl
*ctl
)
17 return tb_sw_write(sw
, ctl
, TB_CFG_SWITCH
, sw
->cap_plug_events
+ 4, 1);
21 * tb_eeprom_ctl_write() - read control word
23 static int tb_eeprom_ctl_read(struct tb_switch
*sw
, struct tb_eeprom_ctl
*ctl
)
25 return tb_sw_read(sw
, ctl
, TB_CFG_SWITCH
, sw
->cap_plug_events
+ 4, 1);
28 enum tb_eeprom_transfer
{
34 * tb_eeprom_active - enable rom access
36 * WARNING: Always disable access after usage. Otherwise the controller will
39 static int tb_eeprom_active(struct tb_switch
*sw
, bool enable
)
41 struct tb_eeprom_ctl ctl
;
42 int res
= tb_eeprom_ctl_read(sw
, &ctl
);
47 res
= tb_eeprom_ctl_write(sw
, &ctl
);
51 return tb_eeprom_ctl_write(sw
, &ctl
);
54 res
= tb_eeprom_ctl_write(sw
, &ctl
);
58 return tb_eeprom_ctl_write(sw
, &ctl
);
63 * tb_eeprom_transfer - transfer one bit
65 * If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->data_in.
66 * If TB_EEPROM_OUT is passed, then ctl->data_out will be written.
68 static int tb_eeprom_transfer(struct tb_switch
*sw
, struct tb_eeprom_ctl
*ctl
,
69 enum tb_eeprom_transfer direction
)
72 if (direction
== TB_EEPROM_OUT
) {
73 res
= tb_eeprom_ctl_write(sw
, ctl
);
78 res
= tb_eeprom_ctl_write(sw
, ctl
);
81 if (direction
== TB_EEPROM_IN
) {
82 res
= tb_eeprom_ctl_read(sw
, ctl
);
87 return tb_eeprom_ctl_write(sw
, ctl
);
91 * tb_eeprom_out - write one byte to the bus
93 static int tb_eeprom_out(struct tb_switch
*sw
, u8 val
)
95 struct tb_eeprom_ctl ctl
;
97 int res
= tb_eeprom_ctl_read(sw
, &ctl
);
100 for (i
= 0; i
< 8; i
++) {
101 ctl
.data_out
= val
& 0x80;
102 res
= tb_eeprom_transfer(sw
, &ctl
, TB_EEPROM_OUT
);
111 * tb_eeprom_in - read one byte from the bus
113 static int tb_eeprom_in(struct tb_switch
*sw
, u8
*val
)
115 struct tb_eeprom_ctl ctl
;
117 int res
= tb_eeprom_ctl_read(sw
, &ctl
);
121 for (i
= 0; i
< 8; i
++) {
123 res
= tb_eeprom_transfer(sw
, &ctl
, TB_EEPROM_IN
);
132 * tb_eeprom_read_n - read count bytes from offset into val
134 static int tb_eeprom_read_n(struct tb_switch
*sw
, u16 offset
, u8
*val
,
138 res
= tb_eeprom_active(sw
, true);
141 res
= tb_eeprom_out(sw
, 3);
144 res
= tb_eeprom_out(sw
, offset
>> 8);
147 res
= tb_eeprom_out(sw
, offset
);
150 for (i
= 0; i
< count
; i
++) {
151 res
= tb_eeprom_in(sw
, val
+ i
);
155 return tb_eeprom_active(sw
, false);
158 static u8
tb_crc8(u8
*data
, int len
)
162 for (i
= 0; i
< len
; i
++) {
164 for (j
= 0; j
< 8; j
++)
165 val
= (val
<< 1) ^ ((val
& 0x80) ? 7 : 0);
170 static u32
tb_crc32(void *data
, size_t len
)
172 return ~__crc32c_le(~0, data
, len
);
175 #define TB_DROM_DATA_START 13
176 struct tb_drom_header
{
178 u8 uid_crc8
; /* checksum for uid */
182 u32 data_crc32
; /* checksum for data_len bytes starting at byte 13 */
184 u8 device_rom_revision
; /* should be <= 1 */
194 enum tb_drom_entry_type
{
195 /* force unsigned to prevent "one-bit signed bitfield" warning */
196 TB_DROM_ENTRY_GENERIC
= 0U,
200 struct tb_drom_entry_header
{
203 bool port_disabled
:1; /* only valid if type is TB_DROM_ENTRY_PORT */
204 enum tb_drom_entry_type type
:1;
207 struct tb_drom_entry_port
{
209 struct tb_drom_entry_header header
;
211 u8 dual_link_port_rid
:4;
214 bool has_dual_link_port
:1;
217 u8 dual_link_port_nr
:6;
220 /* BYTES 4 - 5 TODO decode */
225 /* BYTES 6-7, TODO: verify (find hardware that has these set) */
228 bool has_peer_port
:1;
235 * tb_eeprom_get_drom_offset - get drom offset within eeprom
237 static int tb_eeprom_get_drom_offset(struct tb_switch
*sw
, u16
*offset
)
239 struct tb_cap_plug_events cap
;
241 if (!sw
->cap_plug_events
) {
242 tb_sw_warn(sw
, "no TB_CAP_PLUG_EVENTS, cannot read eeprom\n");
245 res
= tb_sw_read(sw
, &cap
, TB_CFG_SWITCH
, sw
->cap_plug_events
,
250 if (!cap
.eeprom_ctl
.present
|| cap
.eeprom_ctl
.not_present
) {
251 tb_sw_warn(sw
, "no NVM\n");
255 if (cap
.drom_offset
> 0xffff) {
256 tb_sw_warn(sw
, "drom offset is larger than 0xffff: %#x\n",
260 *offset
= cap
.drom_offset
;
265 * tb_drom_read_uid_only - read uid directly from drom
267 * Does not use the cached copy in sw->drom. Used during resume to check switch
270 int tb_drom_read_uid_only(struct tb_switch
*sw
, u64
*uid
)
275 int res
= tb_eeprom_get_drom_offset(sw
, &drom_offset
);
279 if (drom_offset
== 0)
283 res
= tb_eeprom_read_n(sw
, drom_offset
, data
, 9);
287 crc
= tb_crc8(data
+ 1, 8);
288 if (crc
!= data
[0]) {
289 tb_sw_warn(sw
, "uid crc8 missmatch (expected: %#x, got: %#x)\n",
294 *uid
= *(u64
*)(data
+1);
298 static void tb_drom_parse_port_entry(struct tb_port
*port
,
299 struct tb_drom_entry_port
*entry
)
301 port
->link_nr
= entry
->link_nr
;
302 if (entry
->has_dual_link_port
)
303 port
->dual_link_port
=
304 &port
->sw
->ports
[entry
->dual_link_port_nr
];
307 static int tb_drom_parse_entry(struct tb_switch
*sw
,
308 struct tb_drom_entry_header
*header
)
310 struct tb_port
*port
;
312 enum tb_port_type type
;
314 if (header
->type
!= TB_DROM_ENTRY_PORT
)
317 port
= &sw
->ports
[header
->index
];
318 port
->disabled
= header
->port_disabled
;
322 res
= tb_port_read(port
, &type
, TB_CFG_PORT
, 2, 1);
327 if (type
== TB_TYPE_PORT
) {
328 struct tb_drom_entry_port
*entry
= (void *) header
;
329 if (header
->len
!= sizeof(*entry
)) {
331 "port entry has size %#x (expected %#zx)\n",
332 header
->len
, sizeof(struct tb_drom_entry_port
));
335 tb_drom_parse_port_entry(port
, entry
);
341 * tb_drom_parse_entries - parse the linked list of drom entries
343 * Drom must have been copied to sw->drom.
345 static int tb_drom_parse_entries(struct tb_switch
*sw
)
347 struct tb_drom_header
*header
= (void *) sw
->drom
;
348 u16 pos
= sizeof(*header
);
349 u16 drom_size
= header
->data_len
+ TB_DROM_DATA_START
;
351 while (pos
< drom_size
) {
352 struct tb_drom_entry_header
*entry
= (void *) (sw
->drom
+ pos
);
353 if (pos
+ 1 == drom_size
|| pos
+ entry
->len
> drom_size
355 tb_sw_warn(sw
, "drom buffer overrun, aborting\n");
359 tb_drom_parse_entry(sw
, entry
);
367 * tb_drom_copy_efi - copy drom supplied by EFI to sw->drom if present
369 static int tb_drom_copy_efi(struct tb_switch
*sw
, u16
*size
)
371 struct device
*dev
= &sw
->tb
->nhi
->pdev
->dev
;
374 len
= device_property_read_u8_array(dev
, "ThunderboltDROM", NULL
, 0);
375 if (len
< 0 || len
< sizeof(struct tb_drom_header
))
378 sw
->drom
= kmalloc(len
, GFP_KERNEL
);
382 res
= device_property_read_u8_array(dev
, "ThunderboltDROM", sw
->drom
,
387 *size
= ((struct tb_drom_header
*)sw
->drom
)->data_len
+
401 * tb_drom_read - copy drom to sw->drom and parse it
403 int tb_drom_read(struct tb_switch
*sw
)
408 struct tb_drom_header
*header
;
413 if (tb_route(sw
) == 0) {
415 * Apple's NHI EFI driver supplies a DROM for the root switch
416 * in a device property. Use it if available.
418 if (tb_drom_copy_efi(sw
, &size
) == 0)
422 * The root switch contains only a dummy drom (header only,
423 * no entries). Hardcode the configuration here.
425 tb_drom_read_uid_only(sw
, &sw
->uid
);
427 sw
->ports
[1].link_nr
= 0;
428 sw
->ports
[2].link_nr
= 1;
429 sw
->ports
[1].dual_link_port
= &sw
->ports
[2];
430 sw
->ports
[2].dual_link_port
= &sw
->ports
[1];
432 sw
->ports
[3].link_nr
= 0;
433 sw
->ports
[4].link_nr
= 1;
434 sw
->ports
[3].dual_link_port
= &sw
->ports
[4];
435 sw
->ports
[4].dual_link_port
= &sw
->ports
[3];
437 /* Port 5 is inaccessible on this gen 1 controller */
438 if (sw
->config
.device_id
== PCI_DEVICE_ID_INTEL_LIGHT_RIDGE
)
439 sw
->ports
[5].disabled
= true;
444 res
= tb_eeprom_get_drom_offset(sw
, &drom_offset
);
448 res
= tb_eeprom_read_n(sw
, drom_offset
+ 14, (u8
*) &size
, 2);
452 size
+= TB_DROM_DATA_START
;
453 tb_sw_info(sw
, "reading drom (length: %#x)\n", size
);
454 if (size
< sizeof(*header
)) {
455 tb_sw_warn(sw
, "drom too small, aborting\n");
459 sw
->drom
= kzalloc(size
, GFP_KERNEL
);
462 res
= tb_eeprom_read_n(sw
, drom_offset
, sw
->drom
, size
);
467 header
= (void *) sw
->drom
;
469 if (header
->data_len
+ TB_DROM_DATA_START
!= size
) {
470 tb_sw_warn(sw
, "drom size mismatch, aborting\n");
474 crc
= tb_crc8((u8
*) &header
->uid
, 8);
475 if (crc
!= header
->uid_crc8
) {
477 "drom uid crc8 mismatch (expected: %#x, got: %#x), aborting\n",
478 header
->uid_crc8
, crc
);
481 sw
->uid
= header
->uid
;
482 sw
->vendor
= header
->vendor_id
;
483 sw
->device
= header
->model_id
;
485 crc
= tb_crc32(sw
->drom
+ TB_DROM_DATA_START
, header
->data_len
);
486 if (crc
!= header
->data_crc32
) {
488 "drom data crc32 mismatch (expected: %#x, got: %#x), continuing\n",
489 header
->data_crc32
, crc
);
492 if (header
->device_rom_revision
> 2)
493 tb_sw_warn(sw
, "drom device_rom_revision %#x unknown\n",
494 header
->device_rom_revision
);
496 return tb_drom_parse_entries(sw
);