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1 /*
2 * Thunderbolt Cactus Ridge driver - NHI driver
3 *
4 * The NHI (native host interface) is the pci device that allows us to send and
5 * receive frames from the thunderbolt bus.
6 *
7 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
8 */
9
10 #include <linux/pm_runtime.h>
11 #include <linux/slab.h>
12 #include <linux/errno.h>
13 #include <linux/pci.h>
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
16 #include <linux/delay.h>
17
18 #include "nhi.h"
19 #include "nhi_regs.h"
20 #include "tb.h"
21
22 #define RING_TYPE(ring) ((ring)->is_tx ? "TX ring" : "RX ring")
23
24 /*
25 * Used to enable end-to-end workaround for missing RX packets. Do not
26 * use this ring for anything else.
27 */
28 #define RING_E2E_UNUSED_HOPID 2
29 /* HopIDs 0-7 are reserved by the Thunderbolt protocol */
30 #define RING_FIRST_USABLE_HOPID 8
31
32 /*
33 * Minimal number of vectors when we use MSI-X. Two for control channel
34 * Rx/Tx and the rest four are for cross domain DMA paths.
35 */
36 #define MSIX_MIN_VECS 6
37 #define MSIX_MAX_VECS 16
38
39 #define NHI_MAILBOX_TIMEOUT 500 /* ms */
40
41 static int ring_interrupt_index(struct tb_ring *ring)
42 {
43 int bit = ring->hop;
44 if (!ring->is_tx)
45 bit += ring->nhi->hop_count;
46 return bit;
47 }
48
49 /**
50 * ring_interrupt_active() - activate/deactivate interrupts for a single ring
51 *
52 * ring->nhi->lock must be held.
53 */
54 static void ring_interrupt_active(struct tb_ring *ring, bool active)
55 {
56 int reg = REG_RING_INTERRUPT_BASE +
57 ring_interrupt_index(ring) / 32 * 4;
58 int bit = ring_interrupt_index(ring) & 31;
59 int mask = 1 << bit;
60 u32 old, new;
61
62 if (ring->irq > 0) {
63 u32 step, shift, ivr, misc;
64 void __iomem *ivr_base;
65 int index;
66
67 if (ring->is_tx)
68 index = ring->hop;
69 else
70 index = ring->hop + ring->nhi->hop_count;
71
72 /*
73 * Ask the hardware to clear interrupt status bits automatically
74 * since we already know which interrupt was triggered.
75 */
76 misc = ioread32(ring->nhi->iobase + REG_DMA_MISC);
77 if (!(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) {
78 misc |= REG_DMA_MISC_INT_AUTO_CLEAR;
79 iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC);
80 }
81
82 ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE;
83 step = index / REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
84 shift = index % REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
85 ivr = ioread32(ivr_base + step);
86 ivr &= ~(REG_INT_VEC_ALLOC_MASK << shift);
87 if (active)
88 ivr |= ring->vector << shift;
89 iowrite32(ivr, ivr_base + step);
90 }
91
92 old = ioread32(ring->nhi->iobase + reg);
93 if (active)
94 new = old | mask;
95 else
96 new = old & ~mask;
97
98 dev_info(&ring->nhi->pdev->dev,
99 "%s interrupt at register %#x bit %d (%#x -> %#x)\n",
100 active ? "enabling" : "disabling", reg, bit, old, new);
101
102 if (new == old)
103 dev_WARN(&ring->nhi->pdev->dev,
104 "interrupt for %s %d is already %s\n",
105 RING_TYPE(ring), ring->hop,
106 active ? "enabled" : "disabled");
107 iowrite32(new, ring->nhi->iobase + reg);
108 }
109
110 /**
111 * nhi_disable_interrupts() - disable interrupts for all rings
112 *
113 * Use only during init and shutdown.
114 */
115 static void nhi_disable_interrupts(struct tb_nhi *nhi)
116 {
117 int i = 0;
118 /* disable interrupts */
119 for (i = 0; i < RING_INTERRUPT_REG_COUNT(nhi); i++)
120 iowrite32(0, nhi->iobase + REG_RING_INTERRUPT_BASE + 4 * i);
121
122 /* clear interrupt status bits */
123 for (i = 0; i < RING_NOTIFY_REG_COUNT(nhi); i++)
124 ioread32(nhi->iobase + REG_RING_NOTIFY_BASE + 4 * i);
125 }
126
127 /* ring helper methods */
128
129 static void __iomem *ring_desc_base(struct tb_ring *ring)
130 {
131 void __iomem *io = ring->nhi->iobase;
132 io += ring->is_tx ? REG_TX_RING_BASE : REG_RX_RING_BASE;
133 io += ring->hop * 16;
134 return io;
135 }
136
137 static void __iomem *ring_options_base(struct tb_ring *ring)
138 {
139 void __iomem *io = ring->nhi->iobase;
140 io += ring->is_tx ? REG_TX_OPTIONS_BASE : REG_RX_OPTIONS_BASE;
141 io += ring->hop * 32;
142 return io;
143 }
144
145 static void ring_iowrite_cons(struct tb_ring *ring, u16 cons)
146 {
147 /*
148 * The other 16-bits in the register is read-only and writes to it
149 * are ignored by the hardware so we can save one ioread32() by
150 * filling the read-only bits with zeroes.
151 */
152 iowrite32(cons, ring_desc_base(ring) + 8);
153 }
154
155 static void ring_iowrite_prod(struct tb_ring *ring, u16 prod)
156 {
157 /* See ring_iowrite_cons() above for explanation */
158 iowrite32(prod << 16, ring_desc_base(ring) + 8);
159 }
160
161 static void ring_iowrite32desc(struct tb_ring *ring, u32 value, u32 offset)
162 {
163 iowrite32(value, ring_desc_base(ring) + offset);
164 }
165
166 static void ring_iowrite64desc(struct tb_ring *ring, u64 value, u32 offset)
167 {
168 iowrite32(value, ring_desc_base(ring) + offset);
169 iowrite32(value >> 32, ring_desc_base(ring) + offset + 4);
170 }
171
172 static void ring_iowrite32options(struct tb_ring *ring, u32 value, u32 offset)
173 {
174 iowrite32(value, ring_options_base(ring) + offset);
175 }
176
177 static bool ring_full(struct tb_ring *ring)
178 {
179 return ((ring->head + 1) % ring->size) == ring->tail;
180 }
181
182 static bool ring_empty(struct tb_ring *ring)
183 {
184 return ring->head == ring->tail;
185 }
186
187 /**
188 * ring_write_descriptors() - post frames from ring->queue to the controller
189 *
190 * ring->lock is held.
191 */
192 static void ring_write_descriptors(struct tb_ring *ring)
193 {
194 struct ring_frame *frame, *n;
195 struct ring_desc *descriptor;
196 list_for_each_entry_safe(frame, n, &ring->queue, list) {
197 if (ring_full(ring))
198 break;
199 list_move_tail(&frame->list, &ring->in_flight);
200 descriptor = &ring->descriptors[ring->head];
201 descriptor->phys = frame->buffer_phy;
202 descriptor->time = 0;
203 descriptor->flags = RING_DESC_POSTED | RING_DESC_INTERRUPT;
204 if (ring->is_tx) {
205 descriptor->length = frame->size;
206 descriptor->eof = frame->eof;
207 descriptor->sof = frame->sof;
208 }
209 ring->head = (ring->head + 1) % ring->size;
210 if (ring->is_tx)
211 ring_iowrite_prod(ring, ring->head);
212 else
213 ring_iowrite_cons(ring, ring->head);
214 }
215 }
216
217 /**
218 * ring_work() - progress completed frames
219 *
220 * If the ring is shutting down then all frames are marked as canceled and
221 * their callbacks are invoked.
222 *
223 * Otherwise we collect all completed frame from the ring buffer, write new
224 * frame to the ring buffer and invoke the callbacks for the completed frames.
225 */
226 static void ring_work(struct work_struct *work)
227 {
228 struct tb_ring *ring = container_of(work, typeof(*ring), work);
229 struct ring_frame *frame;
230 bool canceled = false;
231 unsigned long flags;
232 LIST_HEAD(done);
233
234 spin_lock_irqsave(&ring->lock, flags);
235
236 if (!ring->running) {
237 /* Move all frames to done and mark them as canceled. */
238 list_splice_tail_init(&ring->in_flight, &done);
239 list_splice_tail_init(&ring->queue, &done);
240 canceled = true;
241 goto invoke_callback;
242 }
243
244 while (!ring_empty(ring)) {
245 if (!(ring->descriptors[ring->tail].flags
246 & RING_DESC_COMPLETED))
247 break;
248 frame = list_first_entry(&ring->in_flight, typeof(*frame),
249 list);
250 list_move_tail(&frame->list, &done);
251 if (!ring->is_tx) {
252 frame->size = ring->descriptors[ring->tail].length;
253 frame->eof = ring->descriptors[ring->tail].eof;
254 frame->sof = ring->descriptors[ring->tail].sof;
255 frame->flags = ring->descriptors[ring->tail].flags;
256 }
257 ring->tail = (ring->tail + 1) % ring->size;
258 }
259 ring_write_descriptors(ring);
260
261 invoke_callback:
262 /* allow callbacks to schedule new work */
263 spin_unlock_irqrestore(&ring->lock, flags);
264 while (!list_empty(&done)) {
265 frame = list_first_entry(&done, typeof(*frame), list);
266 /*
267 * The callback may reenqueue or delete frame.
268 * Do not hold on to it.
269 */
270 list_del_init(&frame->list);
271 if (frame->callback)
272 frame->callback(ring, frame, canceled);
273 }
274 }
275
276 int __tb_ring_enqueue(struct tb_ring *ring, struct ring_frame *frame)
277 {
278 unsigned long flags;
279 int ret = 0;
280
281 spin_lock_irqsave(&ring->lock, flags);
282 if (ring->running) {
283 list_add_tail(&frame->list, &ring->queue);
284 ring_write_descriptors(ring);
285 } else {
286 ret = -ESHUTDOWN;
287 }
288 spin_unlock_irqrestore(&ring->lock, flags);
289 return ret;
290 }
291 EXPORT_SYMBOL_GPL(__tb_ring_enqueue);
292
293 /**
294 * tb_ring_poll() - Poll one completed frame from the ring
295 * @ring: Ring to poll
296 *
297 * This function can be called when @start_poll callback of the @ring
298 * has been called. It will read one completed frame from the ring and
299 * return it to the caller. Returns %NULL if there is no more completed
300 * frames.
301 */
302 struct ring_frame *tb_ring_poll(struct tb_ring *ring)
303 {
304 struct ring_frame *frame = NULL;
305 unsigned long flags;
306
307 spin_lock_irqsave(&ring->lock, flags);
308 if (!ring->running)
309 goto unlock;
310 if (ring_empty(ring))
311 goto unlock;
312
313 if (ring->descriptors[ring->tail].flags & RING_DESC_COMPLETED) {
314 frame = list_first_entry(&ring->in_flight, typeof(*frame),
315 list);
316 list_del_init(&frame->list);
317
318 if (!ring->is_tx) {
319 frame->size = ring->descriptors[ring->tail].length;
320 frame->eof = ring->descriptors[ring->tail].eof;
321 frame->sof = ring->descriptors[ring->tail].sof;
322 frame->flags = ring->descriptors[ring->tail].flags;
323 }
324
325 ring->tail = (ring->tail + 1) % ring->size;
326 }
327
328 unlock:
329 spin_unlock_irqrestore(&ring->lock, flags);
330 return frame;
331 }
332 EXPORT_SYMBOL_GPL(tb_ring_poll);
333
334 static void __ring_interrupt_mask(struct tb_ring *ring, bool mask)
335 {
336 int idx = ring_interrupt_index(ring);
337 int reg = REG_RING_INTERRUPT_BASE + idx / 32 * 4;
338 int bit = idx % 32;
339 u32 val;
340
341 val = ioread32(ring->nhi->iobase + reg);
342 if (mask)
343 val &= ~BIT(bit);
344 else
345 val |= BIT(bit);
346 iowrite32(val, ring->nhi->iobase + reg);
347 }
348
349 /* Both @nhi->lock and @ring->lock should be held */
350 static void __ring_interrupt(struct tb_ring *ring)
351 {
352 if (!ring->running)
353 return;
354
355 if (ring->start_poll) {
356 __ring_interrupt_mask(ring, true);
357 ring->start_poll(ring->poll_data);
358 } else {
359 schedule_work(&ring->work);
360 }
361 }
362
363 /**
364 * tb_ring_poll_complete() - Re-start interrupt for the ring
365 * @ring: Ring to re-start the interrupt
366 *
367 * This will re-start (unmask) the ring interrupt once the user is done
368 * with polling.
369 */
370 void tb_ring_poll_complete(struct tb_ring *ring)
371 {
372 unsigned long flags;
373
374 spin_lock_irqsave(&ring->nhi->lock, flags);
375 spin_lock(&ring->lock);
376 if (ring->start_poll)
377 __ring_interrupt_mask(ring, false);
378 spin_unlock(&ring->lock);
379 spin_unlock_irqrestore(&ring->nhi->lock, flags);
380 }
381 EXPORT_SYMBOL_GPL(tb_ring_poll_complete);
382
383 static irqreturn_t ring_msix(int irq, void *data)
384 {
385 struct tb_ring *ring = data;
386
387 spin_lock(&ring->nhi->lock);
388 spin_lock(&ring->lock);
389 __ring_interrupt(ring);
390 spin_unlock(&ring->lock);
391 spin_unlock(&ring->nhi->lock);
392
393 return IRQ_HANDLED;
394 }
395
396 static int ring_request_msix(struct tb_ring *ring, bool no_suspend)
397 {
398 struct tb_nhi *nhi = ring->nhi;
399 unsigned long irqflags;
400 int ret;
401
402 if (!nhi->pdev->msix_enabled)
403 return 0;
404
405 ret = ida_simple_get(&nhi->msix_ida, 0, MSIX_MAX_VECS, GFP_KERNEL);
406 if (ret < 0)
407 return ret;
408
409 ring->vector = ret;
410
411 ring->irq = pci_irq_vector(ring->nhi->pdev, ring->vector);
412 if (ring->irq < 0)
413 return ring->irq;
414
415 irqflags = no_suspend ? IRQF_NO_SUSPEND : 0;
416 return request_irq(ring->irq, ring_msix, irqflags, "thunderbolt", ring);
417 }
418
419 static void ring_release_msix(struct tb_ring *ring)
420 {
421 if (ring->irq <= 0)
422 return;
423
424 free_irq(ring->irq, ring);
425 ida_simple_remove(&ring->nhi->msix_ida, ring->vector);
426 ring->vector = 0;
427 ring->irq = 0;
428 }
429
430 static int nhi_alloc_hop(struct tb_nhi *nhi, struct tb_ring *ring)
431 {
432 int ret = 0;
433
434 spin_lock_irq(&nhi->lock);
435
436 if (ring->hop < 0) {
437 unsigned int i;
438
439 /*
440 * Automatically allocate HopID from the non-reserved
441 * range 8 .. hop_count - 1.
442 */
443 for (i = RING_FIRST_USABLE_HOPID; i < nhi->hop_count; i++) {
444 if (ring->is_tx) {
445 if (!nhi->tx_rings[i]) {
446 ring->hop = i;
447 break;
448 }
449 } else {
450 if (!nhi->rx_rings[i]) {
451 ring->hop = i;
452 break;
453 }
454 }
455 }
456 }
457
458 if (ring->hop < 0 || ring->hop >= nhi->hop_count) {
459 dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop);
460 ret = -EINVAL;
461 goto err_unlock;
462 }
463 if (ring->is_tx && nhi->tx_rings[ring->hop]) {
464 dev_warn(&nhi->pdev->dev, "TX hop %d already allocated\n",
465 ring->hop);
466 ret = -EBUSY;
467 goto err_unlock;
468 } else if (!ring->is_tx && nhi->rx_rings[ring->hop]) {
469 dev_warn(&nhi->pdev->dev, "RX hop %d already allocated\n",
470 ring->hop);
471 ret = -EBUSY;
472 goto err_unlock;
473 }
474
475 if (ring->is_tx)
476 nhi->tx_rings[ring->hop] = ring;
477 else
478 nhi->rx_rings[ring->hop] = ring;
479
480 err_unlock:
481 spin_unlock_irq(&nhi->lock);
482
483 return ret;
484 }
485
486 static struct tb_ring *tb_ring_alloc(struct tb_nhi *nhi, u32 hop, int size,
487 bool transmit, unsigned int flags,
488 u16 sof_mask, u16 eof_mask,
489 void (*start_poll)(void *),
490 void *poll_data)
491 {
492 struct tb_ring *ring = NULL;
493 dev_info(&nhi->pdev->dev, "allocating %s ring %d of size %d\n",
494 transmit ? "TX" : "RX", hop, size);
495
496 /* Tx Ring 2 is reserved for E2E workaround */
497 if (transmit && hop == RING_E2E_UNUSED_HOPID)
498 return NULL;
499
500 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
501 if (!ring)
502 return NULL;
503
504 spin_lock_init(&ring->lock);
505 INIT_LIST_HEAD(&ring->queue);
506 INIT_LIST_HEAD(&ring->in_flight);
507 INIT_WORK(&ring->work, ring_work);
508
509 ring->nhi = nhi;
510 ring->hop = hop;
511 ring->is_tx = transmit;
512 ring->size = size;
513 ring->flags = flags;
514 ring->sof_mask = sof_mask;
515 ring->eof_mask = eof_mask;
516 ring->head = 0;
517 ring->tail = 0;
518 ring->running = false;
519 ring->start_poll = start_poll;
520 ring->poll_data = poll_data;
521
522 ring->descriptors = dma_alloc_coherent(&ring->nhi->pdev->dev,
523 size * sizeof(*ring->descriptors),
524 &ring->descriptors_dma, GFP_KERNEL | __GFP_ZERO);
525 if (!ring->descriptors)
526 goto err_free_ring;
527
528 if (ring_request_msix(ring, flags & RING_FLAG_NO_SUSPEND))
529 goto err_free_descs;
530
531 if (nhi_alloc_hop(nhi, ring))
532 goto err_release_msix;
533
534 return ring;
535
536 err_release_msix:
537 ring_release_msix(ring);
538 err_free_descs:
539 dma_free_coherent(&ring->nhi->pdev->dev,
540 ring->size * sizeof(*ring->descriptors),
541 ring->descriptors, ring->descriptors_dma);
542 err_free_ring:
543 kfree(ring);
544
545 return NULL;
546 }
547
548 /**
549 * tb_ring_alloc_tx() - Allocate DMA ring for transmit
550 * @nhi: Pointer to the NHI the ring is to be allocated
551 * @hop: HopID (ring) to allocate
552 * @size: Number of entries in the ring
553 * @flags: Flags for the ring
554 */
555 struct tb_ring *tb_ring_alloc_tx(struct tb_nhi *nhi, int hop, int size,
556 unsigned int flags)
557 {
558 return tb_ring_alloc(nhi, hop, size, true, flags, 0, 0, NULL, NULL);
559 }
560 EXPORT_SYMBOL_GPL(tb_ring_alloc_tx);
561
562 /**
563 * tb_ring_alloc_rx() - Allocate DMA ring for receive
564 * @nhi: Pointer to the NHI the ring is to be allocated
565 * @hop: HopID (ring) to allocate. Pass %-1 for automatic allocation.
566 * @size: Number of entries in the ring
567 * @flags: Flags for the ring
568 * @sof_mask: Mask of PDF values that start a frame
569 * @eof_mask: Mask of PDF values that end a frame
570 * @start_poll: If not %NULL the ring will call this function when an
571 * interrupt is triggered and masked, instead of callback
572 * in each Rx frame.
573 * @poll_data: Optional data passed to @start_poll
574 */
575 struct tb_ring *tb_ring_alloc_rx(struct tb_nhi *nhi, int hop, int size,
576 unsigned int flags, u16 sof_mask, u16 eof_mask,
577 void (*start_poll)(void *), void *poll_data)
578 {
579 return tb_ring_alloc(nhi, hop, size, false, flags, sof_mask, eof_mask,
580 start_poll, poll_data);
581 }
582 EXPORT_SYMBOL_GPL(tb_ring_alloc_rx);
583
584 /**
585 * tb_ring_start() - enable a ring
586 *
587 * Must not be invoked in parallel with tb_ring_stop().
588 */
589 void tb_ring_start(struct tb_ring *ring)
590 {
591 u16 frame_size;
592 u32 flags;
593
594 spin_lock_irq(&ring->nhi->lock);
595 spin_lock(&ring->lock);
596 if (ring->nhi->going_away)
597 goto err;
598 if (ring->running) {
599 dev_WARN(&ring->nhi->pdev->dev, "ring already started\n");
600 goto err;
601 }
602 dev_info(&ring->nhi->pdev->dev, "starting %s %d\n",
603 RING_TYPE(ring), ring->hop);
604
605 if (ring->flags & RING_FLAG_FRAME) {
606 /* Means 4096 */
607 frame_size = 0;
608 flags = RING_FLAG_ENABLE;
609 } else {
610 frame_size = TB_FRAME_SIZE;
611 flags = RING_FLAG_ENABLE | RING_FLAG_RAW;
612 }
613
614 if (ring->flags & RING_FLAG_E2E && !ring->is_tx) {
615 u32 hop;
616
617 /*
618 * In order not to lose Rx packets we enable end-to-end
619 * workaround which transfers Rx credits to an unused Tx
620 * HopID.
621 */
622 hop = RING_E2E_UNUSED_HOPID << REG_RX_OPTIONS_E2E_HOP_SHIFT;
623 hop &= REG_RX_OPTIONS_E2E_HOP_MASK;
624 flags |= hop | RING_FLAG_E2E_FLOW_CONTROL;
625 }
626
627 ring_iowrite64desc(ring, ring->descriptors_dma, 0);
628 if (ring->is_tx) {
629 ring_iowrite32desc(ring, ring->size, 12);
630 ring_iowrite32options(ring, 0, 4); /* time releated ? */
631 ring_iowrite32options(ring, flags, 0);
632 } else {
633 u32 sof_eof_mask = ring->sof_mask << 16 | ring->eof_mask;
634
635 ring_iowrite32desc(ring, (frame_size << 16) | ring->size, 12);
636 ring_iowrite32options(ring, sof_eof_mask, 4);
637 ring_iowrite32options(ring, flags, 0);
638 }
639 ring_interrupt_active(ring, true);
640 ring->running = true;
641 err:
642 spin_unlock(&ring->lock);
643 spin_unlock_irq(&ring->nhi->lock);
644 }
645 EXPORT_SYMBOL_GPL(tb_ring_start);
646
647 /**
648 * tb_ring_stop() - shutdown a ring
649 *
650 * Must not be invoked from a callback.
651 *
652 * This method will disable the ring. Further calls to
653 * tb_ring_tx/tb_ring_rx will return -ESHUTDOWN until ring_stop has been
654 * called.
655 *
656 * All enqueued frames will be canceled and their callbacks will be executed
657 * with frame->canceled set to true (on the callback thread). This method
658 * returns only after all callback invocations have finished.
659 */
660 void tb_ring_stop(struct tb_ring *ring)
661 {
662 spin_lock_irq(&ring->nhi->lock);
663 spin_lock(&ring->lock);
664 dev_info(&ring->nhi->pdev->dev, "stopping %s %d\n",
665 RING_TYPE(ring), ring->hop);
666 if (ring->nhi->going_away)
667 goto err;
668 if (!ring->running) {
669 dev_WARN(&ring->nhi->pdev->dev, "%s %d already stopped\n",
670 RING_TYPE(ring), ring->hop);
671 goto err;
672 }
673 ring_interrupt_active(ring, false);
674
675 ring_iowrite32options(ring, 0, 0);
676 ring_iowrite64desc(ring, 0, 0);
677 ring_iowrite32desc(ring, 0, 8);
678 ring_iowrite32desc(ring, 0, 12);
679 ring->head = 0;
680 ring->tail = 0;
681 ring->running = false;
682
683 err:
684 spin_unlock(&ring->lock);
685 spin_unlock_irq(&ring->nhi->lock);
686
687 /*
688 * schedule ring->work to invoke callbacks on all remaining frames.
689 */
690 schedule_work(&ring->work);
691 flush_work(&ring->work);
692 }
693 EXPORT_SYMBOL_GPL(tb_ring_stop);
694
695 /*
696 * tb_ring_free() - free ring
697 *
698 * When this method returns all invocations of ring->callback will have
699 * finished.
700 *
701 * Ring must be stopped.
702 *
703 * Must NOT be called from ring_frame->callback!
704 */
705 void tb_ring_free(struct tb_ring *ring)
706 {
707 spin_lock_irq(&ring->nhi->lock);
708 /*
709 * Dissociate the ring from the NHI. This also ensures that
710 * nhi_interrupt_work cannot reschedule ring->work.
711 */
712 if (ring->is_tx)
713 ring->nhi->tx_rings[ring->hop] = NULL;
714 else
715 ring->nhi->rx_rings[ring->hop] = NULL;
716
717 if (ring->running) {
718 dev_WARN(&ring->nhi->pdev->dev, "%s %d still running\n",
719 RING_TYPE(ring), ring->hop);
720 }
721 spin_unlock_irq(&ring->nhi->lock);
722
723 ring_release_msix(ring);
724
725 dma_free_coherent(&ring->nhi->pdev->dev,
726 ring->size * sizeof(*ring->descriptors),
727 ring->descriptors, ring->descriptors_dma);
728
729 ring->descriptors = NULL;
730 ring->descriptors_dma = 0;
731
732
733 dev_info(&ring->nhi->pdev->dev,
734 "freeing %s %d\n",
735 RING_TYPE(ring),
736 ring->hop);
737
738 /**
739 * ring->work can no longer be scheduled (it is scheduled only
740 * by nhi_interrupt_work, ring_stop and ring_msix). Wait for it
741 * to finish before freeing the ring.
742 */
743 flush_work(&ring->work);
744 kfree(ring);
745 }
746 EXPORT_SYMBOL_GPL(tb_ring_free);
747
748 /**
749 * nhi_mailbox_cmd() - Send a command through NHI mailbox
750 * @nhi: Pointer to the NHI structure
751 * @cmd: Command to send
752 * @data: Data to be send with the command
753 *
754 * Sends mailbox command to the firmware running on NHI. Returns %0 in
755 * case of success and negative errno in case of failure.
756 */
757 int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data)
758 {
759 ktime_t timeout;
760 u32 val;
761
762 iowrite32(data, nhi->iobase + REG_INMAIL_DATA);
763
764 val = ioread32(nhi->iobase + REG_INMAIL_CMD);
765 val &= ~(REG_INMAIL_CMD_MASK | REG_INMAIL_ERROR);
766 val |= REG_INMAIL_OP_REQUEST | cmd;
767 iowrite32(val, nhi->iobase + REG_INMAIL_CMD);
768
769 timeout = ktime_add_ms(ktime_get(), NHI_MAILBOX_TIMEOUT);
770 do {
771 val = ioread32(nhi->iobase + REG_INMAIL_CMD);
772 if (!(val & REG_INMAIL_OP_REQUEST))
773 break;
774 usleep_range(10, 20);
775 } while (ktime_before(ktime_get(), timeout));
776
777 if (val & REG_INMAIL_OP_REQUEST)
778 return -ETIMEDOUT;
779 if (val & REG_INMAIL_ERROR)
780 return -EIO;
781
782 return 0;
783 }
784
785 /**
786 * nhi_mailbox_mode() - Return current firmware operation mode
787 * @nhi: Pointer to the NHI structure
788 *
789 * The function reads current firmware operation mode using NHI mailbox
790 * registers and returns it to the caller.
791 */
792 enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi)
793 {
794 u32 val;
795
796 val = ioread32(nhi->iobase + REG_OUTMAIL_CMD);
797 val &= REG_OUTMAIL_CMD_OPMODE_MASK;
798 val >>= REG_OUTMAIL_CMD_OPMODE_SHIFT;
799
800 return (enum nhi_fw_mode)val;
801 }
802
803 static void nhi_interrupt_work(struct work_struct *work)
804 {
805 struct tb_nhi *nhi = container_of(work, typeof(*nhi), interrupt_work);
806 int value = 0; /* Suppress uninitialized usage warning. */
807 int bit;
808 int hop = -1;
809 int type = 0; /* current interrupt type 0: TX, 1: RX, 2: RX overflow */
810 struct tb_ring *ring;
811
812 spin_lock_irq(&nhi->lock);
813
814 /*
815 * Starting at REG_RING_NOTIFY_BASE there are three status bitfields
816 * (TX, RX, RX overflow). We iterate over the bits and read a new
817 * dwords as required. The registers are cleared on read.
818 */
819 for (bit = 0; bit < 3 * nhi->hop_count; bit++) {
820 if (bit % 32 == 0)
821 value = ioread32(nhi->iobase
822 + REG_RING_NOTIFY_BASE
823 + 4 * (bit / 32));
824 if (++hop == nhi->hop_count) {
825 hop = 0;
826 type++;
827 }
828 if ((value & (1 << (bit % 32))) == 0)
829 continue;
830 if (type == 2) {
831 dev_warn(&nhi->pdev->dev,
832 "RX overflow for ring %d\n",
833 hop);
834 continue;
835 }
836 if (type == 0)
837 ring = nhi->tx_rings[hop];
838 else
839 ring = nhi->rx_rings[hop];
840 if (ring == NULL) {
841 dev_warn(&nhi->pdev->dev,
842 "got interrupt for inactive %s ring %d\n",
843 type ? "RX" : "TX",
844 hop);
845 continue;
846 }
847
848 spin_lock(&ring->lock);
849 __ring_interrupt(ring);
850 spin_unlock(&ring->lock);
851 }
852 spin_unlock_irq(&nhi->lock);
853 }
854
855 static irqreturn_t nhi_msi(int irq, void *data)
856 {
857 struct tb_nhi *nhi = data;
858 schedule_work(&nhi->interrupt_work);
859 return IRQ_HANDLED;
860 }
861
862 static int nhi_suspend_noirq(struct device *dev)
863 {
864 struct pci_dev *pdev = to_pci_dev(dev);
865 struct tb *tb = pci_get_drvdata(pdev);
866
867 return tb_domain_suspend_noirq(tb);
868 }
869
870 static void nhi_enable_int_throttling(struct tb_nhi *nhi)
871 {
872 /* Throttling is specified in 256ns increments */
873 u32 throttle = DIV_ROUND_UP(128 * NSEC_PER_USEC, 256);
874 unsigned int i;
875
876 /*
877 * Configure interrupt throttling for all vectors even if we
878 * only use few.
879 */
880 for (i = 0; i < MSIX_MAX_VECS; i++) {
881 u32 reg = REG_INT_THROTTLING_RATE + i * 4;
882 iowrite32(throttle, nhi->iobase + reg);
883 }
884 }
885
886 static int nhi_resume_noirq(struct device *dev)
887 {
888 struct pci_dev *pdev = to_pci_dev(dev);
889 struct tb *tb = pci_get_drvdata(pdev);
890
891 /*
892 * Check that the device is still there. It may be that the user
893 * unplugged last device which causes the host controller to go
894 * away on PCs.
895 */
896 if (!pci_device_is_present(pdev))
897 tb->nhi->going_away = true;
898 else
899 nhi_enable_int_throttling(tb->nhi);
900
901 return tb_domain_resume_noirq(tb);
902 }
903
904 static int nhi_suspend(struct device *dev)
905 {
906 struct pci_dev *pdev = to_pci_dev(dev);
907 struct tb *tb = pci_get_drvdata(pdev);
908
909 return tb_domain_suspend(tb);
910 }
911
912 static void nhi_complete(struct device *dev)
913 {
914 struct pci_dev *pdev = to_pci_dev(dev);
915 struct tb *tb = pci_get_drvdata(pdev);
916
917 /*
918 * If we were runtime suspended when system suspend started,
919 * schedule runtime resume now. It should bring the domain back
920 * to functional state.
921 */
922 if (pm_runtime_suspended(&pdev->dev))
923 pm_runtime_resume(&pdev->dev);
924 else
925 tb_domain_complete(tb);
926 }
927
928 static int nhi_runtime_suspend(struct device *dev)
929 {
930 struct pci_dev *pdev = to_pci_dev(dev);
931 struct tb *tb = pci_get_drvdata(pdev);
932
933 return tb_domain_runtime_suspend(tb);
934 }
935
936 static int nhi_runtime_resume(struct device *dev)
937 {
938 struct pci_dev *pdev = to_pci_dev(dev);
939 struct tb *tb = pci_get_drvdata(pdev);
940
941 nhi_enable_int_throttling(tb->nhi);
942 return tb_domain_runtime_resume(tb);
943 }
944
945 static void nhi_shutdown(struct tb_nhi *nhi)
946 {
947 int i;
948 dev_info(&nhi->pdev->dev, "shutdown\n");
949
950 for (i = 0; i < nhi->hop_count; i++) {
951 if (nhi->tx_rings[i])
952 dev_WARN(&nhi->pdev->dev,
953 "TX ring %d is still active\n", i);
954 if (nhi->rx_rings[i])
955 dev_WARN(&nhi->pdev->dev,
956 "RX ring %d is still active\n", i);
957 }
958 nhi_disable_interrupts(nhi);
959 /*
960 * We have to release the irq before calling flush_work. Otherwise an
961 * already executing IRQ handler could call schedule_work again.
962 */
963 if (!nhi->pdev->msix_enabled) {
964 devm_free_irq(&nhi->pdev->dev, nhi->pdev->irq, nhi);
965 flush_work(&nhi->interrupt_work);
966 }
967 ida_destroy(&nhi->msix_ida);
968 }
969
970 static int nhi_init_msi(struct tb_nhi *nhi)
971 {
972 struct pci_dev *pdev = nhi->pdev;
973 int res, irq, nvec;
974
975 /* In case someone left them on. */
976 nhi_disable_interrupts(nhi);
977
978 nhi_enable_int_throttling(nhi);
979
980 ida_init(&nhi->msix_ida);
981
982 /*
983 * The NHI has 16 MSI-X vectors or a single MSI. We first try to
984 * get all MSI-X vectors and if we succeed, each ring will have
985 * one MSI-X. If for some reason that does not work out, we
986 * fallback to a single MSI.
987 */
988 nvec = pci_alloc_irq_vectors(pdev, MSIX_MIN_VECS, MSIX_MAX_VECS,
989 PCI_IRQ_MSIX);
990 if (nvec < 0) {
991 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
992 if (nvec < 0)
993 return nvec;
994
995 INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work);
996
997 irq = pci_irq_vector(nhi->pdev, 0);
998 if (irq < 0)
999 return irq;
1000
1001 res = devm_request_irq(&pdev->dev, irq, nhi_msi,
1002 IRQF_NO_SUSPEND, "thunderbolt", nhi);
1003 if (res) {
1004 dev_err(&pdev->dev, "request_irq failed, aborting\n");
1005 return res;
1006 }
1007 }
1008
1009 return 0;
1010 }
1011
1012 static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1013 {
1014 struct tb_nhi *nhi;
1015 struct tb *tb;
1016 int res;
1017
1018 res = pcim_enable_device(pdev);
1019 if (res) {
1020 dev_err(&pdev->dev, "cannot enable PCI device, aborting\n");
1021 return res;
1022 }
1023
1024 res = pcim_iomap_regions(pdev, 1 << 0, "thunderbolt");
1025 if (res) {
1026 dev_err(&pdev->dev, "cannot obtain PCI resources, aborting\n");
1027 return res;
1028 }
1029
1030 nhi = devm_kzalloc(&pdev->dev, sizeof(*nhi), GFP_KERNEL);
1031 if (!nhi)
1032 return -ENOMEM;
1033
1034 nhi->pdev = pdev;
1035 /* cannot fail - table is allocated bin pcim_iomap_regions */
1036 nhi->iobase = pcim_iomap_table(pdev)[0];
1037 nhi->hop_count = ioread32(nhi->iobase + REG_HOP_COUNT) & 0x3ff;
1038 if (nhi->hop_count != 12 && nhi->hop_count != 32)
1039 dev_warn(&pdev->dev, "unexpected hop count: %d\n",
1040 nhi->hop_count);
1041
1042 nhi->tx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
1043 sizeof(*nhi->tx_rings), GFP_KERNEL);
1044 nhi->rx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
1045 sizeof(*nhi->rx_rings), GFP_KERNEL);
1046 if (!nhi->tx_rings || !nhi->rx_rings)
1047 return -ENOMEM;
1048
1049 res = nhi_init_msi(nhi);
1050 if (res) {
1051 dev_err(&pdev->dev, "cannot enable MSI, aborting\n");
1052 return res;
1053 }
1054
1055 spin_lock_init(&nhi->lock);
1056
1057 res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1058 if (res)
1059 res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1060 if (res) {
1061 dev_err(&pdev->dev, "failed to set DMA mask\n");
1062 return res;
1063 }
1064
1065 pci_set_master(pdev);
1066
1067 tb = icm_probe(nhi);
1068 if (!tb)
1069 tb = tb_probe(nhi);
1070 if (!tb) {
1071 dev_err(&nhi->pdev->dev,
1072 "failed to determine connection manager, aborting\n");
1073 return -ENODEV;
1074 }
1075
1076 dev_info(&nhi->pdev->dev, "NHI initialized, starting thunderbolt\n");
1077
1078 res = tb_domain_add(tb);
1079 if (res) {
1080 /*
1081 * At this point the RX/TX rings might already have been
1082 * activated. Do a proper shutdown.
1083 */
1084 tb_domain_put(tb);
1085 nhi_shutdown(nhi);
1086 return res;
1087 }
1088 pci_set_drvdata(pdev, tb);
1089
1090 pm_runtime_allow(&pdev->dev);
1091 pm_runtime_set_autosuspend_delay(&pdev->dev, TB_AUTOSUSPEND_DELAY);
1092 pm_runtime_use_autosuspend(&pdev->dev);
1093 pm_runtime_put_autosuspend(&pdev->dev);
1094
1095 return 0;
1096 }
1097
1098 static void nhi_remove(struct pci_dev *pdev)
1099 {
1100 struct tb *tb = pci_get_drvdata(pdev);
1101 struct tb_nhi *nhi = tb->nhi;
1102
1103 pm_runtime_get_sync(&pdev->dev);
1104 pm_runtime_dont_use_autosuspend(&pdev->dev);
1105 pm_runtime_forbid(&pdev->dev);
1106
1107 tb_domain_remove(tb);
1108 nhi_shutdown(nhi);
1109 }
1110
1111 /*
1112 * The tunneled pci bridges are siblings of us. Use resume_noirq to reenable
1113 * the tunnels asap. A corresponding pci quirk blocks the downstream bridges
1114 * resume_noirq until we are done.
1115 */
1116 static const struct dev_pm_ops nhi_pm_ops = {
1117 .suspend_noirq = nhi_suspend_noirq,
1118 .resume_noirq = nhi_resume_noirq,
1119 .freeze_noirq = nhi_suspend_noirq, /*
1120 * we just disable hotplug, the
1121 * pci-tunnels stay alive.
1122 */
1123 .thaw_noirq = nhi_resume_noirq,
1124 .restore_noirq = nhi_resume_noirq,
1125 .suspend = nhi_suspend,
1126 .freeze = nhi_suspend,
1127 .poweroff = nhi_suspend,
1128 .complete = nhi_complete,
1129 .runtime_suspend = nhi_runtime_suspend,
1130 .runtime_resume = nhi_runtime_resume,
1131 };
1132
1133 static struct pci_device_id nhi_ids[] = {
1134 /*
1135 * We have to specify class, the TB bridges use the same device and
1136 * vendor (sub)id on gen 1 and gen 2 controllers.
1137 */
1138 {
1139 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1140 .vendor = PCI_VENDOR_ID_INTEL,
1141 .device = PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
1142 .subvendor = 0x2222, .subdevice = 0x1111,
1143 },
1144 {
1145 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1146 .vendor = PCI_VENDOR_ID_INTEL,
1147 .device = PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
1148 .subvendor = 0x2222, .subdevice = 0x1111,
1149 },
1150 {
1151 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1152 .vendor = PCI_VENDOR_ID_INTEL,
1153 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI,
1154 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
1155 },
1156 {
1157 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1158 .vendor = PCI_VENDOR_ID_INTEL,
1159 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI,
1160 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
1161 },
1162
1163 /* Thunderbolt 3 */
1164 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI) },
1165 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI) },
1166 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI) },
1167 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI) },
1168 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI) },
1169 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI) },
1170 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI) },
1171 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI) },
1172 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI) },
1173 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI) },
1174
1175 { 0,}
1176 };
1177
1178 MODULE_DEVICE_TABLE(pci, nhi_ids);
1179 MODULE_LICENSE("GPL");
1180
1181 static struct pci_driver nhi_driver = {
1182 .name = "thunderbolt",
1183 .id_table = nhi_ids,
1184 .probe = nhi_probe,
1185 .remove = nhi_remove,
1186 .driver.pm = &nhi_pm_ops,
1187 };
1188
1189 static int __init nhi_init(void)
1190 {
1191 int ret;
1192
1193 ret = tb_domain_init();
1194 if (ret)
1195 return ret;
1196 ret = pci_register_driver(&nhi_driver);
1197 if (ret)
1198 tb_domain_exit();
1199 return ret;
1200 }
1201
1202 static void __exit nhi_unload(void)
1203 {
1204 pci_unregister_driver(&nhi_driver);
1205 tb_domain_exit();
1206 }
1207
1208 rootfs_initcall(nhi_init);
1209 module_exit(nhi_unload);