2 * Thunderbolt control channel messages
4 * Copyright (C) 2014 Andreas Noever <andreas.noever@gmail.com>
5 * Copyright (C) 2017, Intel Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
15 #include <linux/types.h>
16 #include <linux/uuid.h>
26 TB_CFG_ERROR_PORT_NOT_CONNECTED
= 0,
27 TB_CFG_ERROR_LINK_ERROR
= 1,
28 TB_CFG_ERROR_INVALID_CONFIG_SPACE
= 2,
29 TB_CFG_ERROR_NO_SUCH_PORT
= 4,
30 TB_CFG_ERROR_ACK_PLUG_EVENT
= 7, /* send as reply to TB_CFG_PKG_EVENT */
31 TB_CFG_ERROR_LOOP
= 8,
32 TB_CFG_ERROR_HEC_ERROR_DETECTED
= 12,
33 TB_CFG_ERROR_FLOW_CONTROL_ERROR
= 13,
37 struct tb_cfg_header
{
39 u32 unknown
:10; /* highest order bit is set on replies */
43 /* additional header for read/write packets */
44 struct tb_cfg_address
{
45 u32 offset
:13; /* in dwords */
46 u32 length
:6; /* in dwords */
48 enum tb_cfg_space space
:2;
49 u32 seq
:2; /* sequence number */
53 /* TB_CFG_PKG_READ, response for TB_CFG_PKG_WRITE */
55 struct tb_cfg_header header
;
56 struct tb_cfg_address addr
;
59 /* TB_CFG_PKG_WRITE, response for TB_CFG_PKG_READ */
60 struct cfg_write_pkg
{
61 struct tb_cfg_header header
;
62 struct tb_cfg_address addr
;
63 u32 data
[64]; /* maximum size, tb_cfg_address.length has 6 bits */
66 /* TB_CFG_PKG_ERROR */
67 struct cfg_error_pkg
{
68 struct tb_cfg_header header
;
69 enum tb_cfg_error error
:4;
72 u32 zero2
:2; /* Both should be zero, still they are different fields. */
76 /* TB_CFG_PKG_EVENT */
77 struct cfg_event_pkg
{
78 struct tb_cfg_header header
;
84 /* TB_CFG_PKG_RESET */
85 struct cfg_reset_pkg
{
86 struct tb_cfg_header header
;
89 /* TB_CFG_PKG_PREPARE_TO_SLEEP */
91 struct tb_cfg_header header
;
98 ICM_GET_TOPOLOGY
= 0x1,
99 ICM_DRIVER_READY
= 0x3,
100 ICM_APPROVE_DEVICE
= 0x4,
101 ICM_CHALLENGE_DEVICE
= 0x5,
102 ICM_ADD_DEVICE_KEY
= 0x6,
104 ICM_APPROVE_XDOMAIN
= 0x10,
105 ICM_PREBOOT_ACL
= 0x18,
108 enum icm_event_code
{
109 ICM_EVENT_DEVICE_CONNECTED
= 3,
110 ICM_EVENT_DEVICE_DISCONNECTED
= 4,
111 ICM_EVENT_XDOMAIN_CONNECTED
= 6,
112 ICM_EVENT_XDOMAIN_DISCONNECTED
= 7,
115 struct icm_pkg_header
{
122 #define ICM_FLAGS_ERROR BIT(0)
123 #define ICM_FLAGS_NO_KEY BIT(1)
124 #define ICM_FLAGS_SLEVEL_SHIFT 3
125 #define ICM_FLAGS_SLEVEL_MASK GENMASK(4, 3)
126 #define ICM_FLAGS_WRITE BIT(7)
128 struct icm_pkg_driver_ready
{
129 struct icm_pkg_header hdr
;
132 /* Falcon Ridge only messages */
134 struct icm_fr_pkg_driver_ready_response
{
135 struct icm_pkg_header hdr
;
141 #define ICM_FR_SLEVEL_MASK 0xf
143 /* Falcon Ridge & Alpine Ridge common messages */
145 struct icm_fr_pkg_get_topology
{
146 struct icm_pkg_header hdr
;
149 #define ICM_GET_TOPOLOGY_PACKETS 14
151 struct icm_fr_pkg_get_topology_response
{
152 struct icm_pkg_header hdr
;
157 u8 drom_i2c_address_index
;
161 u32 port_hop_info
[16];
164 #define ICM_SWITCH_USED BIT(0)
165 #define ICM_SWITCH_UPSTREAM_PORT_MASK GENMASK(7, 1)
166 #define ICM_SWITCH_UPSTREAM_PORT_SHIFT 1
168 #define ICM_PORT_TYPE_MASK GENMASK(23, 0)
169 #define ICM_PORT_INDEX_SHIFT 24
170 #define ICM_PORT_INDEX_MASK GENMASK(31, 24)
172 struct icm_fr_event_device_connected
{
173 struct icm_pkg_header hdr
;
181 #define ICM_LINK_INFO_LINK_MASK 0x7
182 #define ICM_LINK_INFO_DEPTH_SHIFT 4
183 #define ICM_LINK_INFO_DEPTH_MASK GENMASK(7, 4)
184 #define ICM_LINK_INFO_APPROVED BIT(8)
185 #define ICM_LINK_INFO_REJECTED BIT(9)
186 #define ICM_LINK_INFO_BOOT BIT(10)
188 struct icm_fr_pkg_approve_device
{
189 struct icm_pkg_header hdr
;
196 struct icm_fr_event_device_disconnected
{
197 struct icm_pkg_header hdr
;
202 struct icm_fr_event_xdomain_connected
{
203 struct icm_pkg_header hdr
;
214 struct icm_fr_event_xdomain_disconnected
{
215 struct icm_pkg_header hdr
;
221 struct icm_fr_pkg_add_device_key
{
222 struct icm_pkg_header hdr
;
230 struct icm_fr_pkg_add_device_key_response
{
231 struct icm_pkg_header hdr
;
238 struct icm_fr_pkg_challenge_device
{
239 struct icm_pkg_header hdr
;
247 struct icm_fr_pkg_challenge_device_response
{
248 struct icm_pkg_header hdr
;
257 struct icm_fr_pkg_approve_xdomain
{
258 struct icm_pkg_header hdr
;
268 struct icm_fr_pkg_approve_xdomain_response
{
269 struct icm_pkg_header hdr
;
279 /* Alpine Ridge only messages */
281 struct icm_ar_pkg_driver_ready_response
{
282 struct icm_pkg_header hdr
;
288 #define ICM_AR_INFO_SLEVEL_MASK GENMASK(3, 0)
289 #define ICM_AR_INFO_BOOT_ACL_SHIFT 7
290 #define ICM_AR_INFO_BOOT_ACL_MASK GENMASK(11, 7)
291 #define ICM_AR_INFO_BOOT_ACL_SUPPORTED BIT(13)
293 struct icm_ar_pkg_get_route
{
294 struct icm_pkg_header hdr
;
299 struct icm_ar_pkg_get_route_response
{
300 struct icm_pkg_header hdr
;
307 struct icm_ar_boot_acl_entry
{
312 #define ICM_AR_PREBOOT_ACL_ENTRIES 16
314 struct icm_ar_pkg_preboot_acl
{
315 struct icm_pkg_header hdr
;
316 struct icm_ar_boot_acl_entry acl
[ICM_AR_PREBOOT_ACL_ENTRIES
];
319 struct icm_ar_pkg_preboot_acl_response
{
320 struct icm_pkg_header hdr
;
321 struct icm_ar_boot_acl_entry acl
[ICM_AR_PREBOOT_ACL_ENTRIES
];
324 /* XDomain messages */
326 struct tb_xdomain_header
{
332 #define TB_XDOMAIN_LENGTH_MASK GENMASK(5, 0)
333 #define TB_XDOMAIN_SN_MASK GENMASK(28, 27)
334 #define TB_XDOMAIN_SN_SHIFT 27
337 UUID_REQUEST_OLD
= 1,
341 PROPERTIES_CHANGED_REQUEST
,
342 PROPERTIES_CHANGED_RESPONSE
,
347 struct tb_xdp_header
{
348 struct tb_xdomain_header xd_hdr
;
353 struct tb_xdp_properties
{
354 struct tb_xdp_header hdr
;
361 struct tb_xdp_properties_response
{
362 struct tb_xdp_header hdr
;
372 * Max length of data array single XDomain property response is allowed
375 #define TB_XDP_PROPERTIES_MAX_DATA_LENGTH \
376 (((256 - 4 - sizeof(struct tb_xdp_properties_response))) / 4)
378 /* Maximum size of the total property block in dwords we allow */
379 #define TB_XDP_PROPERTIES_MAX_LENGTH 500
381 struct tb_xdp_properties_changed
{
382 struct tb_xdp_header hdr
;
386 struct tb_xdp_properties_changed_response
{
387 struct tb_xdp_header hdr
;
392 ERROR_UNKNOWN_PACKET
,
393 ERROR_UNKNOWN_DOMAIN
,
398 struct tb_xdp_error_response
{
399 struct tb_xdp_header hdr
;