2 * Synopsys DesignWare 8250 driver.
4 * Copyright 2011 Picochip, Jamie Iles.
5 * Copyright 2013 Intel Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
13 * LCR is written whilst busy. If it is, then a busy detect interrupt is
14 * raised, the LCR needs to be rewritten and the uart status register read.
16 #include <linux/device.h>
18 #include <linux/module.h>
19 #include <linux/serial_8250.h>
20 #include <linux/serial_reg.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_platform.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/acpi.h>
27 #include <linux/clk.h>
28 #include <linux/reset.h>
29 #include <linux/pm_runtime.h>
31 #include <asm/byteorder.h>
35 /* Offsets for the DesignWare specific registers */
36 #define DW_UART_USR 0x1f /* UART Status Register */
37 #define DW_UART_CPR 0xf4 /* Component Parameter Register */
38 #define DW_UART_UCV 0xf8 /* UART Component Version */
40 /* Component Parameter Register bits */
41 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
42 #define DW_UART_CPR_AFCE_MODE (1 << 4)
43 #define DW_UART_CPR_THRE_MODE (1 << 5)
44 #define DW_UART_CPR_SIR_MODE (1 << 6)
45 #define DW_UART_CPR_SIR_LP_MODE (1 << 7)
46 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
47 #define DW_UART_CPR_FIFO_ACCESS (1 << 9)
48 #define DW_UART_CPR_FIFO_STAT (1 << 10)
49 #define DW_UART_CPR_SHADOW (1 << 11)
50 #define DW_UART_CPR_ENCODED_PARMS (1 << 12)
51 #define DW_UART_CPR_DMA_EXTRA (1 << 13)
52 #define DW_UART_CPR_FIFO_MODE (0xff << 16)
53 /* Helper for fifo size calculation */
54 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)
56 /* DesignWare specific register fields */
57 #define DW_UART_MCR_SIRE BIT(6)
66 struct reset_control
*rst
;
67 struct uart_8250_dma dma
;
69 unsigned int skip_autocfg
:1;
70 unsigned int uart_16550_compatible
:1;
73 static inline int dw8250_modify_msr(struct uart_port
*p
, int offset
, int value
)
75 struct dw8250_data
*d
= p
->private_data
;
77 /* Override any modem control signals if needed */
78 if (offset
== UART_MSR
) {
79 value
|= d
->msr_mask_on
;
80 value
&= ~d
->msr_mask_off
;
86 static void dw8250_force_idle(struct uart_port
*p
)
88 struct uart_8250_port
*up
= up_to_u8250p(p
);
90 serial8250_clear_and_reinit_fifos(up
);
91 (void)p
->serial_in(p
, UART_RX
);
94 static void dw8250_check_lcr(struct uart_port
*p
, int value
)
96 void __iomem
*offset
= p
->membase
+ (UART_LCR
<< p
->regshift
);
99 /* Make sure LCR write wasn't ignored */
101 unsigned int lcr
= p
->serial_in(p
, UART_LCR
);
103 if ((value
& ~UART_LCR_SPAR
) == (lcr
& ~UART_LCR_SPAR
))
106 dw8250_force_idle(p
);
109 if (p
->type
== PORT_OCTEON
)
110 __raw_writeq(value
& 0xff, offset
);
113 if (p
->iotype
== UPIO_MEM32
)
114 writel(value
, offset
);
115 else if (p
->iotype
== UPIO_MEM32BE
)
116 iowrite32be(value
, offset
);
118 writeb(value
, offset
);
121 * FIXME: this deadlocks if port->lock is already held
122 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
126 static void dw8250_serial_out(struct uart_port
*p
, int offset
, int value
)
128 struct dw8250_data
*d
= p
->private_data
;
130 writeb(value
, p
->membase
+ (offset
<< p
->regshift
));
132 if (offset
== UART_LCR
&& !d
->uart_16550_compatible
)
133 dw8250_check_lcr(p
, value
);
136 static unsigned int dw8250_serial_in(struct uart_port
*p
, int offset
)
138 unsigned int value
= readb(p
->membase
+ (offset
<< p
->regshift
));
140 return dw8250_modify_msr(p
, offset
, value
);
144 static unsigned int dw8250_serial_inq(struct uart_port
*p
, int offset
)
148 value
= (u8
)__raw_readq(p
->membase
+ (offset
<< p
->regshift
));
150 return dw8250_modify_msr(p
, offset
, value
);
153 static void dw8250_serial_outq(struct uart_port
*p
, int offset
, int value
)
155 struct dw8250_data
*d
= p
->private_data
;
158 __raw_writeq(value
, p
->membase
+ (offset
<< p
->regshift
));
159 /* Read back to ensure register write ordering. */
160 __raw_readq(p
->membase
+ (UART_LCR
<< p
->regshift
));
162 if (offset
== UART_LCR
&& !d
->uart_16550_compatible
)
163 dw8250_check_lcr(p
, value
);
165 #endif /* CONFIG_64BIT */
167 static void dw8250_serial_out32(struct uart_port
*p
, int offset
, int value
)
169 struct dw8250_data
*d
= p
->private_data
;
171 writel(value
, p
->membase
+ (offset
<< p
->regshift
));
173 if (offset
== UART_LCR
&& !d
->uart_16550_compatible
)
174 dw8250_check_lcr(p
, value
);
177 static unsigned int dw8250_serial_in32(struct uart_port
*p
, int offset
)
179 unsigned int value
= readl(p
->membase
+ (offset
<< p
->regshift
));
181 return dw8250_modify_msr(p
, offset
, value
);
184 static void dw8250_serial_out32be(struct uart_port
*p
, int offset
, int value
)
186 struct dw8250_data
*d
= p
->private_data
;
188 iowrite32be(value
, p
->membase
+ (offset
<< p
->regshift
));
190 if (offset
== UART_LCR
&& !d
->uart_16550_compatible
)
191 dw8250_check_lcr(p
, value
);
194 static unsigned int dw8250_serial_in32be(struct uart_port
*p
, int offset
)
196 unsigned int value
= ioread32be(p
->membase
+ (offset
<< p
->regshift
));
198 return dw8250_modify_msr(p
, offset
, value
);
202 static int dw8250_handle_irq(struct uart_port
*p
)
204 struct uart_8250_port
*up
= up_to_u8250p(p
);
205 struct dw8250_data
*d
= p
->private_data
;
206 unsigned int iir
= p
->serial_in(p
, UART_IIR
);
211 * There are ways to get Designware-based UARTs into a state where
212 * they are asserting UART_IIR_RX_TIMEOUT but there is no actual
213 * data available. If we see such a case then we'll do a bogus
214 * read. If we don't do this then the "RX TIMEOUT" interrupt will
217 * This problem has only been observed so far when not in DMA mode
218 * so we limit the workaround only to non-DMA mode.
220 if (!up
->dma
&& ((iir
& 0x3f) == UART_IIR_RX_TIMEOUT
)) {
221 spin_lock_irqsave(&p
->lock
, flags
);
222 status
= p
->serial_in(p
, UART_LSR
);
224 if (!(status
& (UART_LSR_DR
| UART_LSR_BI
)))
225 (void) p
->serial_in(p
, UART_RX
);
227 spin_unlock_irqrestore(&p
->lock
, flags
);
230 if (serial8250_handle_irq(p
, iir
))
233 if ((iir
& UART_IIR_BUSY
) == UART_IIR_BUSY
) {
235 (void)p
->serial_in(p
, d
->usr_reg
);
244 dw8250_do_pm(struct uart_port
*port
, unsigned int state
, unsigned int old
)
247 pm_runtime_get_sync(port
->dev
);
249 serial8250_do_pm(port
, state
, old
);
252 pm_runtime_put_sync_suspend(port
->dev
);
255 static void dw8250_set_termios(struct uart_port
*p
, struct ktermios
*termios
,
256 struct ktermios
*old
)
258 unsigned int baud
= tty_termios_baud_rate(termios
);
259 struct dw8250_data
*d
= p
->private_data
;
263 if (IS_ERR(d
->clk
) || !old
)
266 clk_disable_unprepare(d
->clk
);
267 rate
= clk_round_rate(d
->clk
, baud
* 16);
268 ret
= clk_set_rate(d
->clk
, rate
);
269 clk_prepare_enable(d
->clk
);
275 p
->status
&= ~UPSTAT_AUTOCTS
;
276 if (termios
->c_cflag
& CRTSCTS
)
277 p
->status
|= UPSTAT_AUTOCTS
;
279 serial8250_do_set_termios(p
, termios
, old
);
282 static void dw8250_set_ldisc(struct uart_port
*p
, struct ktermios
*termios
)
284 struct uart_8250_port
*up
= up_to_u8250p(p
);
285 unsigned int mcr
= p
->serial_in(p
, UART_MCR
);
287 if (up
->capabilities
& UART_CAP_IRDA
) {
288 if (termios
->c_line
== N_IRDA
)
289 mcr
|= DW_UART_MCR_SIRE
;
291 mcr
&= ~DW_UART_MCR_SIRE
;
293 p
->serial_out(p
, UART_MCR
, mcr
);
295 serial8250_do_set_ldisc(p
, termios
);
299 * dw8250_fallback_dma_filter will prevent the UART from getting just any free
300 * channel on platforms that have DMA engines, but don't have any channels
301 * assigned to the UART.
303 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the
304 * core problem is fixed, this function is no longer needed.
306 static bool dw8250_fallback_dma_filter(struct dma_chan
*chan
, void *param
)
311 static bool dw8250_idma_filter(struct dma_chan
*chan
, void *param
)
313 return param
== chan
->device
->dev
->parent
;
316 static void dw8250_quirks(struct uart_port
*p
, struct dw8250_data
*data
)
318 if (p
->dev
->of_node
) {
319 struct device_node
*np
= p
->dev
->of_node
;
322 /* get index of serial line, if found in DT aliases */
323 id
= of_alias_get_id(np
, "serial");
327 if (of_device_is_compatible(np
, "cavium,octeon-3860-uart")) {
328 p
->serial_in
= dw8250_serial_inq
;
329 p
->serial_out
= dw8250_serial_outq
;
330 p
->flags
= UPF_SKIP_TEST
| UPF_SHARE_IRQ
| UPF_FIXED_TYPE
;
331 p
->type
= PORT_OCTEON
;
332 data
->usr_reg
= 0x27;
333 data
->skip_autocfg
= true;
336 if (of_device_is_big_endian(p
->dev
->of_node
)) {
337 p
->iotype
= UPIO_MEM32BE
;
338 p
->serial_in
= dw8250_serial_in32be
;
339 p
->serial_out
= dw8250_serial_out32be
;
341 } else if (has_acpi_companion(p
->dev
)) {
342 const struct acpi_device_id
*id
;
344 id
= acpi_match_device(p
->dev
->driver
->acpi_match_table
,
346 if (id
&& !strcmp(id
->id
, "APMC0D08")) {
347 p
->iotype
= UPIO_MEM32
;
349 p
->serial_in
= dw8250_serial_in32
;
350 data
->uart_16550_compatible
= true;
354 /* Platforms with iDMA */
355 if (platform_get_resource_byname(to_platform_device(p
->dev
),
356 IORESOURCE_MEM
, "lpss_priv")) {
357 data
->dma
.rx_param
= p
->dev
->parent
;
358 data
->dma
.tx_param
= p
->dev
->parent
;
359 data
->dma
.fn
= dw8250_idma_filter
;
363 static void dw8250_setup_port(struct uart_port
*p
)
365 struct uart_8250_port
*up
= up_to_u8250p(p
);
369 * If the Component Version Register returns zero, we know that
370 * ADDITIONAL_FEATURES are not enabled. No need to go any further.
372 if (p
->iotype
== UPIO_MEM32BE
)
373 reg
= ioread32be(p
->membase
+ DW_UART_UCV
);
375 reg
= readl(p
->membase
+ DW_UART_UCV
);
379 dev_dbg(p
->dev
, "Designware UART version %c.%c%c\n",
380 (reg
>> 24) & 0xff, (reg
>> 16) & 0xff, (reg
>> 8) & 0xff);
382 if (p
->iotype
== UPIO_MEM32BE
)
383 reg
= ioread32be(p
->membase
+ DW_UART_CPR
);
385 reg
= readl(p
->membase
+ DW_UART_CPR
);
389 /* Select the type based on fifo */
390 if (reg
& DW_UART_CPR_FIFO_MODE
) {
391 p
->type
= PORT_16550A
;
392 p
->flags
|= UPF_FIXED_TYPE
;
393 p
->fifosize
= DW_UART_CPR_FIFO_SIZE(reg
);
394 up
->capabilities
= UART_CAP_FIFO
;
397 if (reg
& DW_UART_CPR_AFCE_MODE
)
398 up
->capabilities
|= UART_CAP_AFE
;
400 if (reg
& DW_UART_CPR_SIR_MODE
)
401 up
->capabilities
|= UART_CAP_IRDA
;
404 static int dw8250_probe(struct platform_device
*pdev
)
406 struct uart_8250_port uart
= {};
407 struct resource
*regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
408 int irq
= platform_get_irq(pdev
, 0);
409 struct uart_port
*p
= &uart
.port
;
410 struct device
*dev
= &pdev
->dev
;
411 struct dw8250_data
*data
;
416 dev_err(dev
, "no registers defined\n");
421 if (irq
!= -EPROBE_DEFER
)
422 dev_err(dev
, "cannot get irq\n");
426 spin_lock_init(&p
->lock
);
427 p
->mapbase
= regs
->start
;
429 p
->handle_irq
= dw8250_handle_irq
;
430 p
->pm
= dw8250_do_pm
;
432 p
->flags
= UPF_SHARE_IRQ
| UPF_FIXED_PORT
;
434 p
->iotype
= UPIO_MEM
;
435 p
->serial_in
= dw8250_serial_in
;
436 p
->serial_out
= dw8250_serial_out
;
437 p
->set_ldisc
= dw8250_set_ldisc
;
438 p
->set_termios
= dw8250_set_termios
;
440 p
->membase
= devm_ioremap(dev
, regs
->start
, resource_size(regs
));
444 data
= devm_kzalloc(dev
, sizeof(*data
), GFP_KERNEL
);
448 data
->dma
.fn
= dw8250_fallback_dma_filter
;
449 data
->usr_reg
= DW_UART_USR
;
450 p
->private_data
= data
;
452 data
->uart_16550_compatible
= device_property_read_bool(dev
,
453 "snps,uart-16550-compatible");
455 err
= device_property_read_u32(dev
, "reg-shift", &val
);
459 err
= device_property_read_u32(dev
, "reg-io-width", &val
);
460 if (!err
&& val
== 4) {
461 p
->iotype
= UPIO_MEM32
;
462 p
->serial_in
= dw8250_serial_in32
;
463 p
->serial_out
= dw8250_serial_out32
;
466 if (device_property_read_bool(dev
, "dcd-override")) {
467 /* Always report DCD as active */
468 data
->msr_mask_on
|= UART_MSR_DCD
;
469 data
->msr_mask_off
|= UART_MSR_DDCD
;
472 if (device_property_read_bool(dev
, "dsr-override")) {
473 /* Always report DSR as active */
474 data
->msr_mask_on
|= UART_MSR_DSR
;
475 data
->msr_mask_off
|= UART_MSR_DDSR
;
478 if (device_property_read_bool(dev
, "cts-override")) {
479 /* Always report CTS as active */
480 data
->msr_mask_on
|= UART_MSR_CTS
;
481 data
->msr_mask_off
|= UART_MSR_DCTS
;
484 if (device_property_read_bool(dev
, "ri-override")) {
485 /* Always report Ring indicator as inactive */
486 data
->msr_mask_off
|= UART_MSR_RI
;
487 data
->msr_mask_off
|= UART_MSR_TERI
;
490 /* Always ask for fixed clock rate from a property. */
491 device_property_read_u32(dev
, "clock-frequency", &p
->uartclk
);
493 /* If there is separate baudclk, get the rate from it. */
494 data
->clk
= devm_clk_get(dev
, "baudclk");
495 if (IS_ERR(data
->clk
) && PTR_ERR(data
->clk
) != -EPROBE_DEFER
)
496 data
->clk
= devm_clk_get(dev
, NULL
);
497 if (IS_ERR(data
->clk
) && PTR_ERR(data
->clk
) == -EPROBE_DEFER
)
498 return -EPROBE_DEFER
;
499 if (!IS_ERR_OR_NULL(data
->clk
)) {
500 err
= clk_prepare_enable(data
->clk
);
502 dev_warn(dev
, "could not enable optional baudclk: %d\n",
505 p
->uartclk
= clk_get_rate(data
->clk
);
508 /* If no clock rate is defined, fail. */
510 dev_err(dev
, "clock rate not defined\n");
514 data
->pclk
= devm_clk_get(dev
, "apb_pclk");
515 if (IS_ERR(data
->pclk
) && PTR_ERR(data
->pclk
) == -EPROBE_DEFER
) {
519 if (!IS_ERR(data
->pclk
)) {
520 err
= clk_prepare_enable(data
->pclk
);
522 dev_err(dev
, "could not enable apb_pclk\n");
527 data
->rst
= devm_reset_control_get_optional(dev
, NULL
);
528 if (IS_ERR(data
->rst
) && PTR_ERR(data
->rst
) == -EPROBE_DEFER
) {
532 if (!IS_ERR(data
->rst
))
533 reset_control_deassert(data
->rst
);
535 dw8250_quirks(p
, data
);
537 /* If the Busy Functionality is not implemented, don't handle it */
538 if (data
->uart_16550_compatible
)
539 p
->handle_irq
= NULL
;
541 if (!data
->skip_autocfg
)
542 dw8250_setup_port(p
);
544 /* If we have a valid fifosize, try hooking up DMA */
546 data
->dma
.rxconf
.src_maxburst
= p
->fifosize
/ 4;
547 data
->dma
.txconf
.dst_maxburst
= p
->fifosize
/ 4;
548 uart
.dma
= &data
->dma
;
551 data
->line
= serial8250_register_8250_port(&uart
);
552 if (data
->line
< 0) {
557 platform_set_drvdata(pdev
, data
);
559 pm_runtime_set_active(dev
);
560 pm_runtime_enable(dev
);
565 if (!IS_ERR(data
->rst
))
566 reset_control_assert(data
->rst
);
569 if (!IS_ERR(data
->pclk
))
570 clk_disable_unprepare(data
->pclk
);
573 if (!IS_ERR(data
->clk
))
574 clk_disable_unprepare(data
->clk
);
579 static int dw8250_remove(struct platform_device
*pdev
)
581 struct dw8250_data
*data
= platform_get_drvdata(pdev
);
583 pm_runtime_get_sync(&pdev
->dev
);
585 serial8250_unregister_port(data
->line
);
587 if (!IS_ERR(data
->rst
))
588 reset_control_assert(data
->rst
);
590 if (!IS_ERR(data
->pclk
))
591 clk_disable_unprepare(data
->pclk
);
593 if (!IS_ERR(data
->clk
))
594 clk_disable_unprepare(data
->clk
);
596 pm_runtime_disable(&pdev
->dev
);
597 pm_runtime_put_noidle(&pdev
->dev
);
602 #ifdef CONFIG_PM_SLEEP
603 static int dw8250_suspend(struct device
*dev
)
605 struct dw8250_data
*data
= dev_get_drvdata(dev
);
607 serial8250_suspend_port(data
->line
);
612 static int dw8250_resume(struct device
*dev
)
614 struct dw8250_data
*data
= dev_get_drvdata(dev
);
616 serial8250_resume_port(data
->line
);
620 #endif /* CONFIG_PM_SLEEP */
623 static int dw8250_runtime_suspend(struct device
*dev
)
625 struct dw8250_data
*data
= dev_get_drvdata(dev
);
627 if (!IS_ERR(data
->clk
))
628 clk_disable_unprepare(data
->clk
);
630 if (!IS_ERR(data
->pclk
))
631 clk_disable_unprepare(data
->pclk
);
636 static int dw8250_runtime_resume(struct device
*dev
)
638 struct dw8250_data
*data
= dev_get_drvdata(dev
);
640 if (!IS_ERR(data
->pclk
))
641 clk_prepare_enable(data
->pclk
);
643 if (!IS_ERR(data
->clk
))
644 clk_prepare_enable(data
->clk
);
650 static const struct dev_pm_ops dw8250_pm_ops
= {
651 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend
, dw8250_resume
)
652 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend
, dw8250_runtime_resume
, NULL
)
655 static const struct of_device_id dw8250_of_match
[] = {
656 { .compatible
= "snps,dw-apb-uart" },
657 { .compatible
= "cavium,octeon-3860-uart" },
660 MODULE_DEVICE_TABLE(of
, dw8250_of_match
);
662 static const struct acpi_device_id dw8250_acpi_match
[] = {
675 MODULE_DEVICE_TABLE(acpi
, dw8250_acpi_match
);
677 static struct platform_driver dw8250_platform_driver
= {
679 .name
= "dw-apb-uart",
680 .pm
= &dw8250_pm_ops
,
681 .of_match_table
= dw8250_of_match
,
682 .acpi_match_table
= ACPI_PTR(dw8250_acpi_match
),
684 .probe
= dw8250_probe
,
685 .remove
= dw8250_remove
,
688 module_platform_driver(dw8250_platform_driver
);
690 MODULE_AUTHOR("Jamie Iles");
691 MODULE_LICENSE("GPL");
692 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
693 MODULE_ALIAS("platform:dw-apb-uart");