drivers/tty/serial/8250/8250_of.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Serial Port driver for Open Firmware platform devices
   4  *
   5  *    Copyright (C) 2006 Arnd Bergmann <arnd@arndb.de>, IBM Corp.
   6  */
   7 #include <linux/console.h>
   8 #include <linux/module.h>
   9 #include <linux/slab.h>
  10 #include <linux/delay.h>
  11 #include <linux/serial_core.h>
  12 #include <linux/serial_reg.h>
  13 #include <linux/of_address.h>
  14 #include <linux/of_irq.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/clk.h>
  18 #include <linux/reset.h>
  19
  20 #include "8250.h"
  21
  22 struct of_serial_info {
  23         struct clk *clk;
  24         struct reset_control *rst;
  25         int type;
  26         int line;
  27 };
  28
  29 #ifdef CONFIG_ARCH_TEGRA
  30 static void tegra_serial_handle_break(struct uart_port *p)
  31 {
  32         unsigned int status, tmout = 10000;
  33
  34         do {
  35                 status = p->serial_in(p, UART_LSR);
  36                 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
  37                         status = p->serial_in(p, UART_RX);
  38                 else
  39                         break;
  40                 if (--tmout == 0)
  41                         break;
  42                 udelay(1);
  43         } while (1);
  44 }
  45 #else
  46 static inline void tegra_serial_handle_break(struct uart_port *port)
  47 {
  48 }
  49 #endif
  50
  51 /*
  52  * Fill a struct uart_port for a given device node
  53  */
  54 static int of_platform_serial_setup(struct platform_device *ofdev,
  55                         int type, struct uart_port *port,
  56                         struct of_serial_info *info)
  57 {
  58         struct resource resource;
  59         struct device_node *np = ofdev->dev.of_node;
  60         u32 clk, spd, prop;
  61         int ret;
  62
  63         memset(port, 0, sizeof *port);
  64
  65         pm_runtime_enable(&ofdev->dev);
  66         pm_runtime_get_sync(&ofdev->dev);
  67
  68         if (of_property_read_u32(np, "clock-frequency", &clk)) {
  69
  70                 /* Get clk rate through clk driver if present */
  71                 info->clk = devm_clk_get(&ofdev->dev, NULL);
  72                 if (IS_ERR(info->clk)) {
  73                         dev_warn(&ofdev->dev,
  74                                 "clk or clock-frequency not defined\n");
  75                         ret = PTR_ERR(info->clk);
  76                         goto err_pmruntime;
  77                 }
  78
  79                 ret = clk_prepare_enable(info->clk);
  80                 if (ret < 0)
  81                         goto err_pmruntime;
  82
  83                 clk = clk_get_rate(info->clk);
  84         }
  85         /* If current-speed was set, then try not to change it. */
  86         if (of_property_read_u32(np, "current-speed", &spd) == 0)
  87                 port->custom_divisor = clk / (16 * spd);
  88
  89         ret = of_address_to_resource(np, 0, &resource);
  90         if (ret) {
  91                 dev_warn(&ofdev->dev, "invalid address\n");
  92                 goto err_unprepare;
  93         }
  94
  95         spin_lock_init(&port->lock);
  96         port->mapbase = resource.start;
  97         port->mapsize = resource_size(&resource);
  98
  99         /* Check for shifted address mapping */
 100         if (of_property_read_u32(np, "reg-offset", &prop) == 0)
 101                 port->mapbase += prop;
 102
 103         /* Check for registers offset within the devices address range */
 104         if (of_property_read_u32(np, "reg-shift", &prop) == 0)
 105                 port->regshift = prop;
 106
 107         /* Check for fifo size */
 108         if (of_property_read_u32(np, "fifo-size", &prop) == 0)
 109                 port->fifosize = prop;
 110
 111         /* Check for a fixed line number */
 112         ret = of_alias_get_id(np, "serial");
 113         if (ret >= 0)
 114                 port->line = ret;
 115
 116         port->irq = irq_of_parse_and_map(np, 0);
 117         port->iotype = UPIO_MEM;
 118         if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
 119                 switch (prop) {
 120                 case 1:
 121                         port->iotype = UPIO_MEM;
 122                         break;
 123                 case 2:
 124                         port->iotype = UPIO_MEM16;
 125                         break;
 126                 case 4:
 127                         port->iotype = of_device_is_big_endian(np) ?
 128                                        UPIO_MEM32BE : UPIO_MEM32;
 129                         break;
 130                 default:
 131                         dev_warn(&ofdev->dev, "unsupported reg-io-width (%d)\n",
 132                                  prop);
 133                         ret = -EINVAL;
 134                         goto err_dispose;
 135                 }
 136         }
 137
 138         info->rst = devm_reset_control_get_optional_shared(&ofdev->dev, NULL);
 139         if (IS_ERR(info->rst)) {
 140                 ret = PTR_ERR(info->rst);
 141                 goto err_dispose;
 142         }
 143
 144         ret = reset_control_deassert(info->rst);
 145         if (ret)
 146                 goto err_dispose;
 147
 148         port->type = type;
 149         port->uartclk = clk;
 150         port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_IOREMAP
 151                 | UPF_FIXED_PORT | UPF_FIXED_TYPE;
 152
 153         if (of_property_read_bool(np, "no-loopback-test"))
 154                 port->flags |= UPF_SKIP_TEST;
 155
 156         port->dev = &ofdev->dev;
 157
 158         switch (type) {
 159         case PORT_TEGRA:
 160                 port->handle_break = tegra_serial_handle_break;
 161                 break;
 162
 163         case PORT_RT2880:
 164                 port->iotype = UPIO_AU;
 165                 break;
 166         }
 167
 168         if (IS_ENABLED(CONFIG_SERIAL_8250_FSL) &&
 169             (of_device_is_compatible(np, "fsl,ns16550") ||
 170              of_device_is_compatible(np, "fsl,16550-FIFO64")))
 171                 port->handle_irq = fsl8250_handle_irq;
 172
 173         return 0;
 174 err_dispose:
 175         irq_dispose_mapping(port->irq);
 176 err_unprepare:
 177         clk_disable_unprepare(info->clk);
 178 err_pmruntime:
 179         pm_runtime_put_sync(&ofdev->dev);
 180         pm_runtime_disable(&ofdev->dev);
 181         return ret;
 182 }
 183
 184 /*
 185  * Try to register a serial port
 186  */
 187 static const struct of_device_id of_platform_serial_table[];
 188 static int of_platform_serial_probe(struct platform_device *ofdev)
 189 {
 190         const struct of_device_id *match;
 191         struct of_serial_info *info;
 192         struct uart_8250_port port8250;
 193         u32 tx_threshold;
 194         int port_type;
 195         int ret;
 196
 197         match = of_match_device(of_platform_serial_table, &ofdev->dev);
 198         if (!match)
 199                 return -EINVAL;
 200
 201         if (of_property_read_bool(ofdev->dev.of_node, "used-by-rtas"))
 202                 return -EBUSY;
 203
 204         info = kzalloc(sizeof(*info), GFP_KERNEL);
 205         if (info == NULL)
 206                 return -ENOMEM;
 207
 208         port_type = (unsigned long)match->data;
 209         memset(&port8250, 0, sizeof(port8250));
 210         ret = of_platform_serial_setup(ofdev, port_type, &port8250.port, info);
 211         if (ret)
 212                 goto err_free;
 213
 214         if (port8250.port.fifosize)
 215                 port8250.capabilities = UART_CAP_FIFO;
 216
 217         /* Check for TX FIFO threshold & set tx_loadsz */
 218         if ((of_property_read_u32(ofdev->dev.of_node, "tx-threshold",
 219                                   &tx_threshold) == 0) &&
 220             (tx_threshold < port8250.port.fifosize))
 221                 port8250.tx_loadsz = port8250.port.fifosize - tx_threshold;
 222
 223         if (of_property_read_bool(ofdev->dev.of_node, "auto-flow-control"))
 224                 port8250.capabilities |= UART_CAP_AFE;
 225
 226         ret = serial8250_register_8250_port(&port8250);
 227         if (ret < 0)
 228                 goto err_dispose;
 229
 230         info->type = port_type;
 231         info->line = ret;
 232         platform_set_drvdata(ofdev, info);
 233         return 0;
 234 err_dispose:
 235         irq_dispose_mapping(port8250.port.irq);
 236         pm_runtime_put_sync(&ofdev->dev);
 237         pm_runtime_disable(&ofdev->dev);
 238         clk_disable_unprepare(info->clk);
 239 err_free:
 240         kfree(info);
 241         return ret;
 242 }
 243
 244 /*
 245  * Release a line
 246  */
 247 static int of_platform_serial_remove(struct platform_device *ofdev)
 248 {
 249         struct of_serial_info *info = platform_get_drvdata(ofdev);
 250
 251         serial8250_unregister_port(info->line);
 252
 253         reset_control_assert(info->rst);
 254         pm_runtime_put_sync(&ofdev->dev);
 255         pm_runtime_disable(&ofdev->dev);
 256         clk_disable_unprepare(info->clk);
 257         kfree(info);
 258         return 0;
 259 }
 260
 261 #ifdef CONFIG_PM_SLEEP
 262 static int of_serial_suspend(struct device *dev)
 263 {
 264         struct of_serial_info *info = dev_get_drvdata(dev);
 265         struct uart_8250_port *port8250 = serial8250_get_port(info->line);
 266         struct uart_port *port = &port8250->port;
 267
 268         serial8250_suspend_port(info->line);
 269
 270         if (!uart_console(port) || console_suspend_enabled) {
 271                 pm_runtime_put_sync(dev);
 272                 clk_disable_unprepare(info->clk);
 273         }
 274         return 0;
 275 }
 276
 277 static int of_serial_resume(struct device *dev)
 278 {
 279         struct of_serial_info *info = dev_get_drvdata(dev);
 280         struct uart_8250_port *port8250 = serial8250_get_port(info->line);
 281         struct uart_port *port = &port8250->port;
 282
 283         if (!uart_console(port) || console_suspend_enabled) {
 284                 pm_runtime_get_sync(dev);
 285                 clk_prepare_enable(info->clk);
 286         }
 287
 288         serial8250_resume_port(info->line);
 289
 290         return 0;
 291 }
 292 #endif
 293 static SIMPLE_DEV_PM_OPS(of_serial_pm_ops, of_serial_suspend, of_serial_resume);
 294
 295 /*
 296  * A few common types, add more as needed.
 297  */
 298 static const struct of_device_id of_platform_serial_table[] = {
 299         { .compatible = "ns8250",   .data = (void *)PORT_8250, },
 300         { .compatible = "ns16450",  .data = (void *)PORT_16450, },
 301         { .compatible = "ns16550a", .data = (void *)PORT_16550A, },
 302         { .compatible = "ns16550",  .data = (void *)PORT_16550, },
 303         { .compatible = "ns16750",  .data = (void *)PORT_16750, },
 304         { .compatible = "ns16850",  .data = (void *)PORT_16850, },
 305         { .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, },
 306         { .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, },
 307         { .compatible = "ralink,rt2880-uart", .data = (void *)PORT_RT2880, },
 308         { .compatible = "altr,16550-FIFO32",
 309                 .data = (void *)PORT_ALTR_16550_F32, },
 310         { .compatible = "altr,16550-FIFO64",
 311                 .data = (void *)PORT_ALTR_16550_F64, },
 312         { .compatible = "altr,16550-FIFO128",
 313                 .data = (void *)PORT_ALTR_16550_F128, },
 314         { .compatible = "mediatek,mtk-btif",
 315                 .data = (void *)PORT_MTK_BTIF, },
 316         { .compatible = "mrvl,mmp-uart",
 317                 .data = (void *)PORT_XSCALE, },
 318         { .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, },
 319         { .compatible = "nuvoton,npcm750-uart", .data = (void *)PORT_NPCM, },
 320         { /* end of list */ },
 321 };
 322 MODULE_DEVICE_TABLE(of, of_platform_serial_table);
 323
 324 static struct platform_driver of_platform_serial_driver = {
 325         .driver = {
 326                 .name = "of_serial",
 327                 .of_match_table = of_platform_serial_table,
 328                 .pm = &of_serial_pm_ops,
 329         },
 330         .probe = of_platform_serial_probe,
 331         .remove = of_platform_serial_remove,
 332 };
 333
 334 module_platform_driver(of_platform_serial_driver);
 335
 336 MODULE_AUTHOR("Arnd Bergmann <arnd@arndb.de>");
 337 MODULE_LICENSE("GPL");
 338 MODULE_DESCRIPTION("Serial Port driver for Open Firmware platform devices");