]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/tty/serial/8250/8250_pci.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ASoC: sti: fix missing clk_disable_unprepare() on error in uni_player_start()
[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / 8250 / 8250_pci.c
1 /*
2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 */
12 #undef DEBUG
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
24 #include <linux/rational.h>
25
26 #include <asm/byteorder.h>
27 #include <asm/io.h>
28
29 #include <linux/dmaengine.h>
30 #include <linux/platform_data/dma-dw.h>
31
32 #include "8250.h"
33
34 /*
35 * init function returns:
36 * > 0 - number of ports
37 * = 0 - use board->num_ports
38 * < 0 - error
39 */
40 struct pci_serial_quirk {
41 u32 vendor;
42 u32 device;
43 u32 subvendor;
44 u32 subdevice;
45 int (*probe)(struct pci_dev *dev);
46 int (*init)(struct pci_dev *dev);
47 int (*setup)(struct serial_private *,
48 const struct pciserial_board *,
49 struct uart_8250_port *, int);
50 void (*exit)(struct pci_dev *dev);
51 };
52
53 #define PCI_NUM_BAR_RESOURCES 6
54
55 struct serial_private {
56 struct pci_dev *dev;
57 unsigned int nr;
58 struct pci_serial_quirk *quirk;
59 int line[0];
60 };
61
62 static int pci_default_setup(struct serial_private*,
63 const struct pciserial_board*, struct uart_8250_port *, int);
64
65 static void moan_device(const char *str, struct pci_dev *dev)
66 {
67 dev_err(&dev->dev,
68 "%s: %s\n"
69 "Please send the output of lspci -vv, this\n"
70 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
71 "manufacturer and name of serial board or\n"
72 "modem board to <linux-serial@vger.kernel.org>.\n",
73 pci_name(dev), str, dev->vendor, dev->device,
74 dev->subsystem_vendor, dev->subsystem_device);
75 }
76
77 static int
78 setup_port(struct serial_private *priv, struct uart_8250_port *port,
79 int bar, int offset, int regshift)
80 {
81 struct pci_dev *dev = priv->dev;
82
83 if (bar >= PCI_NUM_BAR_RESOURCES)
84 return -EINVAL;
85
86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
87 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
88 return -ENOMEM;
89
90 port->port.iotype = UPIO_MEM;
91 port->port.iobase = 0;
92 port->port.mapbase = pci_resource_start(dev, bar) + offset;
93 port->port.membase = pcim_iomap_table(dev)[bar] + offset;
94 port->port.regshift = regshift;
95 } else {
96 port->port.iotype = UPIO_PORT;
97 port->port.iobase = pci_resource_start(dev, bar) + offset;
98 port->port.mapbase = 0;
99 port->port.membase = NULL;
100 port->port.regshift = 0;
101 }
102 return 0;
103 }
104
105 /*
106 * ADDI-DATA GmbH communication cards <info@addi-data.com>
107 */
108 static int addidata_apci7800_setup(struct serial_private *priv,
109 const struct pciserial_board *board,
110 struct uart_8250_port *port, int idx)
111 {
112 unsigned int bar = 0, offset = board->first_offset;
113 bar = FL_GET_BASE(board->flags);
114
115 if (idx < 2) {
116 offset += idx * board->uart_offset;
117 } else if ((idx >= 2) && (idx < 4)) {
118 bar += 1;
119 offset += ((idx - 2) * board->uart_offset);
120 } else if ((idx >= 4) && (idx < 6)) {
121 bar += 2;
122 offset += ((idx - 4) * board->uart_offset);
123 } else if (idx >= 6) {
124 bar += 3;
125 offset += ((idx - 6) * board->uart_offset);
126 }
127
128 return setup_port(priv, port, bar, offset, board->reg_shift);
129 }
130
131 /*
132 * AFAVLAB uses a different mixture of BARs and offsets
133 * Not that ugly ;) -- HW
134 */
135 static int
136 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
137 struct uart_8250_port *port, int idx)
138 {
139 unsigned int bar, offset = board->first_offset;
140
141 bar = FL_GET_BASE(board->flags);
142 if (idx < 4)
143 bar += idx;
144 else {
145 bar = 4;
146 offset += (idx - 4) * board->uart_offset;
147 }
148
149 return setup_port(priv, port, bar, offset, board->reg_shift);
150 }
151
152 /*
153 * HP's Remote Management Console. The Diva chip came in several
154 * different versions. N-class, L2000 and A500 have two Diva chips, each
155 * with 3 UARTs (the third UART on the second chip is unused). Superdome
156 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
157 * one Diva chip, but it has been expanded to 5 UARTs.
158 */
159 static int pci_hp_diva_init(struct pci_dev *dev)
160 {
161 int rc = 0;
162
163 switch (dev->subsystem_device) {
164 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
165 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
166 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
167 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
168 rc = 3;
169 break;
170 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
171 rc = 2;
172 break;
173 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
174 rc = 4;
175 break;
176 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
177 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
178 rc = 1;
179 break;
180 }
181
182 return rc;
183 }
184
185 /*
186 * HP's Diva chip puts the 4th/5th serial port further out, and
187 * some serial ports are supposed to be hidden on certain models.
188 */
189 static int
190 pci_hp_diva_setup(struct serial_private *priv,
191 const struct pciserial_board *board,
192 struct uart_8250_port *port, int idx)
193 {
194 unsigned int offset = board->first_offset;
195 unsigned int bar = FL_GET_BASE(board->flags);
196
197 switch (priv->dev->subsystem_device) {
198 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
199 if (idx == 3)
200 idx++;
201 break;
202 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
203 if (idx > 0)
204 idx++;
205 if (idx > 2)
206 idx++;
207 break;
208 }
209 if (idx > 2)
210 offset = 0x18;
211
212 offset += idx * board->uart_offset;
213
214 return setup_port(priv, port, bar, offset, board->reg_shift);
215 }
216
217 /*
218 * Added for EKF Intel i960 serial boards
219 */
220 static int pci_inteli960ni_init(struct pci_dev *dev)
221 {
222 u32 oldval;
223
224 if (!(dev->subsystem_device & 0x1000))
225 return -ENODEV;
226
227 /* is firmware started? */
228 pci_read_config_dword(dev, 0x44, &oldval);
229 if (oldval == 0x00001000L) { /* RESET value */
230 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
231 return -ENODEV;
232 }
233 return 0;
234 }
235
236 /*
237 * Some PCI serial cards using the PLX 9050 PCI interface chip require
238 * that the card interrupt be explicitly enabled or disabled. This
239 * seems to be mainly needed on card using the PLX which also use I/O
240 * mapped memory.
241 */
242 static int pci_plx9050_init(struct pci_dev *dev)
243 {
244 u8 irq_config;
245 void __iomem *p;
246
247 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
248 moan_device("no memory in bar 0", dev);
249 return 0;
250 }
251
252 irq_config = 0x41;
253 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
254 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
255 irq_config = 0x43;
256
257 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
258 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
259 /*
260 * As the megawolf cards have the int pins active
261 * high, and have 2 UART chips, both ints must be
262 * enabled on the 9050. Also, the UARTS are set in
263 * 16450 mode by default, so we have to enable the
264 * 16C950 'enhanced' mode so that we can use the
265 * deep FIFOs
266 */
267 irq_config = 0x5b;
268 /*
269 * enable/disable interrupts
270 */
271 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
272 if (p == NULL)
273 return -ENOMEM;
274 writel(irq_config, p + 0x4c);
275
276 /*
277 * Read the register back to ensure that it took effect.
278 */
279 readl(p + 0x4c);
280 iounmap(p);
281
282 return 0;
283 }
284
285 static void pci_plx9050_exit(struct pci_dev *dev)
286 {
287 u8 __iomem *p;
288
289 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
290 return;
291
292 /*
293 * disable interrupts
294 */
295 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
296 if (p != NULL) {
297 writel(0, p + 0x4c);
298
299 /*
300 * Read the register back to ensure that it took effect.
301 */
302 readl(p + 0x4c);
303 iounmap(p);
304 }
305 }
306
307 #define NI8420_INT_ENABLE_REG 0x38
308 #define NI8420_INT_ENABLE_BIT 0x2000
309
310 static void pci_ni8420_exit(struct pci_dev *dev)
311 {
312 void __iomem *p;
313 unsigned int bar = 0;
314
315 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
316 moan_device("no memory in bar", dev);
317 return;
318 }
319
320 p = pci_ioremap_bar(dev, bar);
321 if (p == NULL)
322 return;
323
324 /* Disable the CPU Interrupt */
325 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
326 p + NI8420_INT_ENABLE_REG);
327 iounmap(p);
328 }
329
330
331 /* MITE registers */
332 #define MITE_IOWBSR1 0xc4
333 #define MITE_IOWCR1 0xf4
334 #define MITE_LCIMR1 0x08
335 #define MITE_LCIMR2 0x10
336
337 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
338
339 static void pci_ni8430_exit(struct pci_dev *dev)
340 {
341 void __iomem *p;
342 unsigned int bar = 0;
343
344 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
345 moan_device("no memory in bar", dev);
346 return;
347 }
348
349 p = pci_ioremap_bar(dev, bar);
350 if (p == NULL)
351 return;
352
353 /* Disable the CPU Interrupt */
354 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
355 iounmap(p);
356 }
357
358 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
359 static int
360 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
361 struct uart_8250_port *port, int idx)
362 {
363 unsigned int bar, offset = board->first_offset;
364
365 bar = 0;
366
367 if (idx < 4) {
368 /* first four channels map to 0, 0x100, 0x200, 0x300 */
369 offset += idx * board->uart_offset;
370 } else if (idx < 8) {
371 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
372 offset += idx * board->uart_offset + 0xC00;
373 } else /* we have only 8 ports on PMC-OCTALPRO */
374 return 1;
375
376 return setup_port(priv, port, bar, offset, board->reg_shift);
377 }
378
379 /*
380 * This does initialization for PMC OCTALPRO cards:
381 * maps the device memory, resets the UARTs (needed, bc
382 * if the module is removed and inserted again, the card
383 * is in the sleep mode) and enables global interrupt.
384 */
385
386 /* global control register offset for SBS PMC-OctalPro */
387 #define OCT_REG_CR_OFF 0x500
388
389 static int sbs_init(struct pci_dev *dev)
390 {
391 u8 __iomem *p;
392
393 p = pci_ioremap_bar(dev, 0);
394
395 if (p == NULL)
396 return -ENOMEM;
397 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
398 writeb(0x10, p + OCT_REG_CR_OFF);
399 udelay(50);
400 writeb(0x0, p + OCT_REG_CR_OFF);
401
402 /* Set bit-2 (INTENABLE) of Control Register */
403 writeb(0x4, p + OCT_REG_CR_OFF);
404 iounmap(p);
405
406 return 0;
407 }
408
409 /*
410 * Disables the global interrupt of PMC-OctalPro
411 */
412
413 static void sbs_exit(struct pci_dev *dev)
414 {
415 u8 __iomem *p;
416
417 p = pci_ioremap_bar(dev, 0);
418 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
419 if (p != NULL)
420 writeb(0, p + OCT_REG_CR_OFF);
421 iounmap(p);
422 }
423
424 /*
425 * SIIG serial cards have an PCI interface chip which also controls
426 * the UART clocking frequency. Each UART can be clocked independently
427 * (except cards equipped with 4 UARTs) and initial clocking settings
428 * are stored in the EEPROM chip. It can cause problems because this
429 * version of serial driver doesn't support differently clocked UART's
430 * on single PCI card. To prevent this, initialization functions set
431 * high frequency clocking for all UART's on given card. It is safe (I
432 * hope) because it doesn't touch EEPROM settings to prevent conflicts
433 * with other OSes (like M$ DOS).
434 *
435 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
436 *
437 * There is two family of SIIG serial cards with different PCI
438 * interface chip and different configuration methods:
439 * - 10x cards have control registers in IO and/or memory space;
440 * - 20x cards have control registers in standard PCI configuration space.
441 *
442 * Note: all 10x cards have PCI device ids 0x10..
443 * all 20x cards have PCI device ids 0x20..
444 *
445 * There are also Quartet Serial cards which use Oxford Semiconductor
446 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
447 *
448 * Note: some SIIG cards are probed by the parport_serial object.
449 */
450
451 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
452 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
453
454 static int pci_siig10x_init(struct pci_dev *dev)
455 {
456 u16 data;
457 void __iomem *p;
458
459 switch (dev->device & 0xfff8) {
460 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
461 data = 0xffdf;
462 break;
463 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
464 data = 0xf7ff;
465 break;
466 default: /* 1S1P, 4S */
467 data = 0xfffb;
468 break;
469 }
470
471 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
472 if (p == NULL)
473 return -ENOMEM;
474
475 writew(readw(p + 0x28) & data, p + 0x28);
476 readw(p + 0x28);
477 iounmap(p);
478 return 0;
479 }
480
481 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
482 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
483
484 static int pci_siig20x_init(struct pci_dev *dev)
485 {
486 u8 data;
487
488 /* Change clock frequency for the first UART. */
489 pci_read_config_byte(dev, 0x6f, &data);
490 pci_write_config_byte(dev, 0x6f, data & 0xef);
491
492 /* If this card has 2 UART, we have to do the same with second UART. */
493 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
494 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
495 pci_read_config_byte(dev, 0x73, &data);
496 pci_write_config_byte(dev, 0x73, data & 0xef);
497 }
498 return 0;
499 }
500
501 static int pci_siig_init(struct pci_dev *dev)
502 {
503 unsigned int type = dev->device & 0xff00;
504
505 if (type == 0x1000)
506 return pci_siig10x_init(dev);
507 else if (type == 0x2000)
508 return pci_siig20x_init(dev);
509
510 moan_device("Unknown SIIG card", dev);
511 return -ENODEV;
512 }
513
514 static int pci_siig_setup(struct serial_private *priv,
515 const struct pciserial_board *board,
516 struct uart_8250_port *port, int idx)
517 {
518 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
519
520 if (idx > 3) {
521 bar = 4;
522 offset = (idx - 4) * 8;
523 }
524
525 return setup_port(priv, port, bar, offset, 0);
526 }
527
528 /*
529 * Timedia has an explosion of boards, and to avoid the PCI table from
530 * growing *huge*, we use this function to collapse some 70 entries
531 * in the PCI table into one, for sanity's and compactness's sake.
532 */
533 static const unsigned short timedia_single_port[] = {
534 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
535 };
536
537 static const unsigned short timedia_dual_port[] = {
538 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
539 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
540 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
541 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
542 0xD079, 0
543 };
544
545 static const unsigned short timedia_quad_port[] = {
546 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
547 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
548 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
549 0xB157, 0
550 };
551
552 static const unsigned short timedia_eight_port[] = {
553 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
554 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
555 };
556
557 static const struct timedia_struct {
558 int num;
559 const unsigned short *ids;
560 } timedia_data[] = {
561 { 1, timedia_single_port },
562 { 2, timedia_dual_port },
563 { 4, timedia_quad_port },
564 { 8, timedia_eight_port }
565 };
566
567 /*
568 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
569 * listing them individually, this driver merely grabs them all with
570 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
571 * and should be left free to be claimed by parport_serial instead.
572 */
573 static int pci_timedia_probe(struct pci_dev *dev)
574 {
575 /*
576 * Check the third digit of the subdevice ID
577 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
578 */
579 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
580 dev_info(&dev->dev,
581 "ignoring Timedia subdevice %04x for parport_serial\n",
582 dev->subsystem_device);
583 return -ENODEV;
584 }
585
586 return 0;
587 }
588
589 static int pci_timedia_init(struct pci_dev *dev)
590 {
591 const unsigned short *ids;
592 int i, j;
593
594 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
595 ids = timedia_data[i].ids;
596 for (j = 0; ids[j]; j++)
597 if (dev->subsystem_device == ids[j])
598 return timedia_data[i].num;
599 }
600 return 0;
601 }
602
603 /*
604 * Timedia/SUNIX uses a mixture of BARs and offsets
605 * Ugh, this is ugly as all hell --- TYT
606 */
607 static int
608 pci_timedia_setup(struct serial_private *priv,
609 const struct pciserial_board *board,
610 struct uart_8250_port *port, int idx)
611 {
612 unsigned int bar = 0, offset = board->first_offset;
613
614 switch (idx) {
615 case 0:
616 bar = 0;
617 break;
618 case 1:
619 offset = board->uart_offset;
620 bar = 0;
621 break;
622 case 2:
623 bar = 1;
624 break;
625 case 3:
626 offset = board->uart_offset;
627 /* FALLTHROUGH */
628 case 4: /* BAR 2 */
629 case 5: /* BAR 3 */
630 case 6: /* BAR 4 */
631 case 7: /* BAR 5 */
632 bar = idx - 2;
633 }
634
635 return setup_port(priv, port, bar, offset, board->reg_shift);
636 }
637
638 /*
639 * Some Titan cards are also a little weird
640 */
641 static int
642 titan_400l_800l_setup(struct serial_private *priv,
643 const struct pciserial_board *board,
644 struct uart_8250_port *port, int idx)
645 {
646 unsigned int bar, offset = board->first_offset;
647
648 switch (idx) {
649 case 0:
650 bar = 1;
651 break;
652 case 1:
653 bar = 2;
654 break;
655 default:
656 bar = 4;
657 offset = (idx - 2) * board->uart_offset;
658 }
659
660 return setup_port(priv, port, bar, offset, board->reg_shift);
661 }
662
663 static int pci_xircom_init(struct pci_dev *dev)
664 {
665 msleep(100);
666 return 0;
667 }
668
669 static int pci_ni8420_init(struct pci_dev *dev)
670 {
671 void __iomem *p;
672 unsigned int bar = 0;
673
674 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
675 moan_device("no memory in bar", dev);
676 return 0;
677 }
678
679 p = pci_ioremap_bar(dev, bar);
680 if (p == NULL)
681 return -ENOMEM;
682
683 /* Enable CPU Interrupt */
684 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
685 p + NI8420_INT_ENABLE_REG);
686
687 iounmap(p);
688 return 0;
689 }
690
691 #define MITE_IOWBSR1_WSIZE 0xa
692 #define MITE_IOWBSR1_WIN_OFFSET 0x800
693 #define MITE_IOWBSR1_WENAB (1 << 7)
694 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
695 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
696 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
697
698 static int pci_ni8430_init(struct pci_dev *dev)
699 {
700 void __iomem *p;
701 struct pci_bus_region region;
702 u32 device_window;
703 unsigned int bar = 0;
704
705 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
706 moan_device("no memory in bar", dev);
707 return 0;
708 }
709
710 p = pci_ioremap_bar(dev, bar);
711 if (p == NULL)
712 return -ENOMEM;
713
714 /*
715 * Set device window address and size in BAR0, while acknowledging that
716 * the resource structure may contain a translated address that differs
717 * from the address the device responds to.
718 */
719 pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
720 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
721 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
722 writel(device_window, p + MITE_IOWBSR1);
723
724 /* Set window access to go to RAMSEL IO address space */
725 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
726 p + MITE_IOWCR1);
727
728 /* Enable IO Bus Interrupt 0 */
729 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
730
731 /* Enable CPU Interrupt */
732 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
733
734 iounmap(p);
735 return 0;
736 }
737
738 /* UART Port Control Register */
739 #define NI8430_PORTCON 0x0f
740 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
741
742 static int
743 pci_ni8430_setup(struct serial_private *priv,
744 const struct pciserial_board *board,
745 struct uart_8250_port *port, int idx)
746 {
747 struct pci_dev *dev = priv->dev;
748 void __iomem *p;
749 unsigned int bar, offset = board->first_offset;
750
751 if (idx >= board->num_ports)
752 return 1;
753
754 bar = FL_GET_BASE(board->flags);
755 offset += idx * board->uart_offset;
756
757 p = pci_ioremap_bar(dev, bar);
758 if (!p)
759 return -ENOMEM;
760
761 /* enable the transceiver */
762 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
763 p + offset + NI8430_PORTCON);
764
765 iounmap(p);
766
767 return setup_port(priv, port, bar, offset, board->reg_shift);
768 }
769
770 static int pci_netmos_9900_setup(struct serial_private *priv,
771 const struct pciserial_board *board,
772 struct uart_8250_port *port, int idx)
773 {
774 unsigned int bar;
775
776 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
777 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
778 /* netmos apparently orders BARs by datasheet layout, so serial
779 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
780 */
781 bar = 3 * idx;
782
783 return setup_port(priv, port, bar, 0, board->reg_shift);
784 } else {
785 return pci_default_setup(priv, board, port, idx);
786 }
787 }
788
789 /* the 99xx series comes with a range of device IDs and a variety
790 * of capabilities:
791 *
792 * 9900 has varying capabilities and can cascade to sub-controllers
793 * (cascading should be purely internal)
794 * 9904 is hardwired with 4 serial ports
795 * 9912 and 9922 are hardwired with 2 serial ports
796 */
797 static int pci_netmos_9900_numports(struct pci_dev *dev)
798 {
799 unsigned int c = dev->class;
800 unsigned int pi;
801 unsigned short sub_serports;
802
803 pi = c & 0xff;
804
805 if (pi == 2)
806 return 1;
807
808 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
809 /* two possibilities: 0x30ps encodes number of parallel and
810 * serial ports, or 0x1000 indicates *something*. This is not
811 * immediately obvious, since the 2s1p+4s configuration seems
812 * to offer all functionality on functions 0..2, while still
813 * advertising the same function 3 as the 4s+2s1p config.
814 */
815 sub_serports = dev->subsystem_device & 0xf;
816 if (sub_serports > 0)
817 return sub_serports;
818
819 dev_err(&dev->dev,
820 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
821 return 0;
822 }
823
824 moan_device("unknown NetMos/Mostech program interface", dev);
825 return 0;
826 }
827
828 static int pci_netmos_init(struct pci_dev *dev)
829 {
830 /* subdevice 0x00PS means <P> parallel, <S> serial */
831 unsigned int num_serial = dev->subsystem_device & 0xf;
832
833 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
834 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
835 return 0;
836
837 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
838 dev->subsystem_device == 0x0299)
839 return 0;
840
841 switch (dev->device) { /* FALLTHROUGH on all */
842 case PCI_DEVICE_ID_NETMOS_9904:
843 case PCI_DEVICE_ID_NETMOS_9912:
844 case PCI_DEVICE_ID_NETMOS_9922:
845 case PCI_DEVICE_ID_NETMOS_9900:
846 num_serial = pci_netmos_9900_numports(dev);
847 break;
848
849 default:
850 break;
851 }
852
853 if (num_serial == 0) {
854 moan_device("unknown NetMos/Mostech device", dev);
855 return -ENODEV;
856 }
857
858 return num_serial;
859 }
860
861 /*
862 * These chips are available with optionally one parallel port and up to
863 * two serial ports. Unfortunately they all have the same product id.
864 *
865 * Basic configuration is done over a region of 32 I/O ports. The base
866 * ioport is called INTA or INTC, depending on docs/other drivers.
867 *
868 * The region of the 32 I/O ports is configured in POSIO0R...
869 */
870
871 /* registers */
872 #define ITE_887x_MISCR 0x9c
873 #define ITE_887x_INTCBAR 0x78
874 #define ITE_887x_UARTBAR 0x7c
875 #define ITE_887x_PS0BAR 0x10
876 #define ITE_887x_POSIO0 0x60
877
878 /* I/O space size */
879 #define ITE_887x_IOSIZE 32
880 /* I/O space size (bits 26-24; 8 bytes = 011b) */
881 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
882 /* I/O space size (bits 26-24; 32 bytes = 101b) */
883 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
884 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
885 #define ITE_887x_POSIO_SPEED (3 << 29)
886 /* enable IO_Space bit */
887 #define ITE_887x_POSIO_ENABLE (1 << 31)
888
889 static int pci_ite887x_init(struct pci_dev *dev)
890 {
891 /* inta_addr are the configuration addresses of the ITE */
892 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
893 0x200, 0x280, 0 };
894 int ret, i, type;
895 struct resource *iobase = NULL;
896 u32 miscr, uartbar, ioport;
897
898 /* search for the base-ioport */
899 i = 0;
900 while (inta_addr[i] && iobase == NULL) {
901 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
902 "ite887x");
903 if (iobase != NULL) {
904 /* write POSIO0R - speed | size | ioport */
905 pci_write_config_dword(dev, ITE_887x_POSIO0,
906 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
907 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
908 /* write INTCBAR - ioport */
909 pci_write_config_dword(dev, ITE_887x_INTCBAR,
910 inta_addr[i]);
911 ret = inb(inta_addr[i]);
912 if (ret != 0xff) {
913 /* ioport connected */
914 break;
915 }
916 release_region(iobase->start, ITE_887x_IOSIZE);
917 iobase = NULL;
918 }
919 i++;
920 }
921
922 if (!inta_addr[i]) {
923 dev_err(&dev->dev, "ite887x: could not find iobase\n");
924 return -ENODEV;
925 }
926
927 /* start of undocumented type checking (see parport_pc.c) */
928 type = inb(iobase->start + 0x18) & 0x0f;
929
930 switch (type) {
931 case 0x2: /* ITE8871 (1P) */
932 case 0xa: /* ITE8875 (1P) */
933 ret = 0;
934 break;
935 case 0xe: /* ITE8872 (2S1P) */
936 ret = 2;
937 break;
938 case 0x6: /* ITE8873 (1S) */
939 ret = 1;
940 break;
941 case 0x8: /* ITE8874 (2S) */
942 ret = 2;
943 break;
944 default:
945 moan_device("Unknown ITE887x", dev);
946 ret = -ENODEV;
947 }
948
949 /* configure all serial ports */
950 for (i = 0; i < ret; i++) {
951 /* read the I/O port from the device */
952 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
953 &ioport);
954 ioport &= 0x0000FF00; /* the actual base address */
955 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
956 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
957 ITE_887x_POSIO_IOSIZE_8 | ioport);
958
959 /* write the ioport to the UARTBAR */
960 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
961 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
962 uartbar |= (ioport << (16 * i)); /* set the ioport */
963 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
964
965 /* get current config */
966 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
967 /* disable interrupts (UARTx_Routing[3:0]) */
968 miscr &= ~(0xf << (12 - 4 * i));
969 /* activate the UART (UARTx_En) */
970 miscr |= 1 << (23 - i);
971 /* write new config with activated UART */
972 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
973 }
974
975 if (ret <= 0) {
976 /* the device has no UARTs if we get here */
977 release_region(iobase->start, ITE_887x_IOSIZE);
978 }
979
980 return ret;
981 }
982
983 static void pci_ite887x_exit(struct pci_dev *dev)
984 {
985 u32 ioport;
986 /* the ioport is bit 0-15 in POSIO0R */
987 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
988 ioport &= 0xffff;
989 release_region(ioport, ITE_887x_IOSIZE);
990 }
991
992 /*
993 * EndRun Technologies.
994 * Determine the number of ports available on the device.
995 */
996 #define PCI_VENDOR_ID_ENDRUN 0x7401
997 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
998
999 static int pci_endrun_init(struct pci_dev *dev)
1000 {
1001 u8 __iomem *p;
1002 unsigned long deviceID;
1003 unsigned int number_uarts = 0;
1004
1005 /* EndRun device is all 0xexxx */
1006 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1007 (dev->device & 0xf000) != 0xe000)
1008 return 0;
1009
1010 p = pci_iomap(dev, 0, 5);
1011 if (p == NULL)
1012 return -ENOMEM;
1013
1014 deviceID = ioread32(p);
1015 /* EndRun device */
1016 if (deviceID == 0x07000200) {
1017 number_uarts = ioread8(p + 4);
1018 dev_dbg(&dev->dev,
1019 "%d ports detected on EndRun PCI Express device\n",
1020 number_uarts);
1021 }
1022 pci_iounmap(dev, p);
1023 return number_uarts;
1024 }
1025
1026 /*
1027 * Oxford Semiconductor Inc.
1028 * Check that device is part of the Tornado range of devices, then determine
1029 * the number of ports available on the device.
1030 */
1031 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1032 {
1033 u8 __iomem *p;
1034 unsigned long deviceID;
1035 unsigned int number_uarts = 0;
1036
1037 /* OxSemi Tornado devices are all 0xCxxx */
1038 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1039 (dev->device & 0xF000) != 0xC000)
1040 return 0;
1041
1042 p = pci_iomap(dev, 0, 5);
1043 if (p == NULL)
1044 return -ENOMEM;
1045
1046 deviceID = ioread32(p);
1047 /* Tornado device */
1048 if (deviceID == 0x07000200) {
1049 number_uarts = ioread8(p + 4);
1050 dev_dbg(&dev->dev,
1051 "%d ports detected on Oxford PCI Express device\n",
1052 number_uarts);
1053 }
1054 pci_iounmap(dev, p);
1055 return number_uarts;
1056 }
1057
1058 static int pci_asix_setup(struct serial_private *priv,
1059 const struct pciserial_board *board,
1060 struct uart_8250_port *port, int idx)
1061 {
1062 port->bugs |= UART_BUG_PARITY;
1063 return pci_default_setup(priv, board, port, idx);
1064 }
1065
1066 /* Quatech devices have their own extra interface features */
1067
1068 struct quatech_feature {
1069 u16 devid;
1070 bool amcc;
1071 };
1072
1073 #define QPCR_TEST_FOR1 0x3F
1074 #define QPCR_TEST_GET1 0x00
1075 #define QPCR_TEST_FOR2 0x40
1076 #define QPCR_TEST_GET2 0x40
1077 #define QPCR_TEST_FOR3 0x80
1078 #define QPCR_TEST_GET3 0x40
1079 #define QPCR_TEST_FOR4 0xC0
1080 #define QPCR_TEST_GET4 0x80
1081
1082 #define QOPR_CLOCK_X1 0x0000
1083 #define QOPR_CLOCK_X2 0x0001
1084 #define QOPR_CLOCK_X4 0x0002
1085 #define QOPR_CLOCK_X8 0x0003
1086 #define QOPR_CLOCK_RATE_MASK 0x0003
1087
1088
1089 static struct quatech_feature quatech_cards[] = {
1090 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1091 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1092 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1093 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1094 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1095 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1096 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1097 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1098 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1099 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1100 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1101 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1102 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1103 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1104 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1105 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1106 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1107 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1108 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1109 { 0, }
1110 };
1111
1112 static int pci_quatech_amcc(u16 devid)
1113 {
1114 struct quatech_feature *qf = &quatech_cards[0];
1115 while (qf->devid) {
1116 if (qf->devid == devid)
1117 return qf->amcc;
1118 qf++;
1119 }
1120 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1121 return 0;
1122 };
1123
1124 static int pci_quatech_rqopr(struct uart_8250_port *port)
1125 {
1126 unsigned long base = port->port.iobase;
1127 u8 LCR, val;
1128
1129 LCR = inb(base + UART_LCR);
1130 outb(0xBF, base + UART_LCR);
1131 val = inb(base + UART_SCR);
1132 outb(LCR, base + UART_LCR);
1133 return val;
1134 }
1135
1136 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1137 {
1138 unsigned long base = port->port.iobase;
1139 u8 LCR;
1140
1141 LCR = inb(base + UART_LCR);
1142 outb(0xBF, base + UART_LCR);
1143 inb(base + UART_SCR);
1144 outb(qopr, base + UART_SCR);
1145 outb(LCR, base + UART_LCR);
1146 }
1147
1148 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1149 {
1150 unsigned long base = port->port.iobase;
1151 u8 LCR, val, qmcr;
1152
1153 LCR = inb(base + UART_LCR);
1154 outb(0xBF, base + UART_LCR);
1155 val = inb(base + UART_SCR);
1156 outb(val | 0x10, base + UART_SCR);
1157 qmcr = inb(base + UART_MCR);
1158 outb(val, base + UART_SCR);
1159 outb(LCR, base + UART_LCR);
1160
1161 return qmcr;
1162 }
1163
1164 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1165 {
1166 unsigned long base = port->port.iobase;
1167 u8 LCR, val;
1168
1169 LCR = inb(base + UART_LCR);
1170 outb(0xBF, base + UART_LCR);
1171 val = inb(base + UART_SCR);
1172 outb(val | 0x10, base + UART_SCR);
1173 outb(qmcr, base + UART_MCR);
1174 outb(val, base + UART_SCR);
1175 outb(LCR, base + UART_LCR);
1176 }
1177
1178 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1179 {
1180 unsigned long base = port->port.iobase;
1181 u8 LCR, val;
1182
1183 LCR = inb(base + UART_LCR);
1184 outb(0xBF, base + UART_LCR);
1185 val = inb(base + UART_SCR);
1186 if (val & 0x20) {
1187 outb(0x80, UART_LCR);
1188 if (!(inb(UART_SCR) & 0x20)) {
1189 outb(LCR, base + UART_LCR);
1190 return 1;
1191 }
1192 }
1193 return 0;
1194 }
1195
1196 static int pci_quatech_test(struct uart_8250_port *port)
1197 {
1198 u8 reg, qopr;
1199
1200 qopr = pci_quatech_rqopr(port);
1201 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1202 reg = pci_quatech_rqopr(port) & 0xC0;
1203 if (reg != QPCR_TEST_GET1)
1204 return -EINVAL;
1205 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1206 reg = pci_quatech_rqopr(port) & 0xC0;
1207 if (reg != QPCR_TEST_GET2)
1208 return -EINVAL;
1209 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1210 reg = pci_quatech_rqopr(port) & 0xC0;
1211 if (reg != QPCR_TEST_GET3)
1212 return -EINVAL;
1213 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1214 reg = pci_quatech_rqopr(port) & 0xC0;
1215 if (reg != QPCR_TEST_GET4)
1216 return -EINVAL;
1217
1218 pci_quatech_wqopr(port, qopr);
1219 return 0;
1220 }
1221
1222 static int pci_quatech_clock(struct uart_8250_port *port)
1223 {
1224 u8 qopr, reg, set;
1225 unsigned long clock;
1226
1227 if (pci_quatech_test(port) < 0)
1228 return 1843200;
1229
1230 qopr = pci_quatech_rqopr(port);
1231
1232 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1233 reg = pci_quatech_rqopr(port);
1234 if (reg & QOPR_CLOCK_X8) {
1235 clock = 1843200;
1236 goto out;
1237 }
1238 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1239 reg = pci_quatech_rqopr(port);
1240 if (!(reg & QOPR_CLOCK_X8)) {
1241 clock = 1843200;
1242 goto out;
1243 }
1244 reg &= QOPR_CLOCK_X8;
1245 if (reg == QOPR_CLOCK_X2) {
1246 clock = 3685400;
1247 set = QOPR_CLOCK_X2;
1248 } else if (reg == QOPR_CLOCK_X4) {
1249 clock = 7372800;
1250 set = QOPR_CLOCK_X4;
1251 } else if (reg == QOPR_CLOCK_X8) {
1252 clock = 14745600;
1253 set = QOPR_CLOCK_X8;
1254 } else {
1255 clock = 1843200;
1256 set = QOPR_CLOCK_X1;
1257 }
1258 qopr &= ~QOPR_CLOCK_RATE_MASK;
1259 qopr |= set;
1260
1261 out:
1262 pci_quatech_wqopr(port, qopr);
1263 return clock;
1264 }
1265
1266 static int pci_quatech_rs422(struct uart_8250_port *port)
1267 {
1268 u8 qmcr;
1269 int rs422 = 0;
1270
1271 if (!pci_quatech_has_qmcr(port))
1272 return 0;
1273 qmcr = pci_quatech_rqmcr(port);
1274 pci_quatech_wqmcr(port, 0xFF);
1275 if (pci_quatech_rqmcr(port))
1276 rs422 = 1;
1277 pci_quatech_wqmcr(port, qmcr);
1278 return rs422;
1279 }
1280
1281 static int pci_quatech_init(struct pci_dev *dev)
1282 {
1283 if (pci_quatech_amcc(dev->device)) {
1284 unsigned long base = pci_resource_start(dev, 0);
1285 if (base) {
1286 u32 tmp;
1287
1288 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1289 tmp = inl(base + 0x3c);
1290 outl(tmp | 0x01000000, base + 0x3c);
1291 outl(tmp &= ~0x01000000, base + 0x3c);
1292 }
1293 }
1294 return 0;
1295 }
1296
1297 static int pci_quatech_setup(struct serial_private *priv,
1298 const struct pciserial_board *board,
1299 struct uart_8250_port *port, int idx)
1300 {
1301 /* Needed by pci_quatech calls below */
1302 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1303 /* Set up the clocking */
1304 port->port.uartclk = pci_quatech_clock(port);
1305 /* For now just warn about RS422 */
1306 if (pci_quatech_rs422(port))
1307 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1308 return pci_default_setup(priv, board, port, idx);
1309 }
1310
1311 static void pci_quatech_exit(struct pci_dev *dev)
1312 {
1313 }
1314
1315 static int pci_default_setup(struct serial_private *priv,
1316 const struct pciserial_board *board,
1317 struct uart_8250_port *port, int idx)
1318 {
1319 unsigned int bar, offset = board->first_offset, maxnr;
1320
1321 bar = FL_GET_BASE(board->flags);
1322 if (board->flags & FL_BASE_BARS)
1323 bar += idx;
1324 else
1325 offset += idx * board->uart_offset;
1326
1327 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1328 (board->reg_shift + 3);
1329
1330 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1331 return 1;
1332
1333 return setup_port(priv, port, bar, offset, board->reg_shift);
1334 }
1335
1336 static int
1337 ce4100_serial_setup(struct serial_private *priv,
1338 const struct pciserial_board *board,
1339 struct uart_8250_port *port, int idx)
1340 {
1341 int ret;
1342
1343 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1344 port->port.iotype = UPIO_MEM32;
1345 port->port.type = PORT_XSCALE;
1346 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1347 port->port.regshift = 2;
1348
1349 return ret;
1350 }
1351
1352 #define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1353 #define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1354
1355 #define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a
1356 #define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c
1357
1358 #define PCI_DEVICE_ID_INTEL_BDW_UART1 0x9ce3
1359 #define PCI_DEVICE_ID_INTEL_BDW_UART2 0x9ce4
1360
1361 #define BYT_PRV_CLK 0x800
1362 #define BYT_PRV_CLK_EN (1 << 0)
1363 #define BYT_PRV_CLK_M_VAL_SHIFT 1
1364 #define BYT_PRV_CLK_N_VAL_SHIFT 16
1365 #define BYT_PRV_CLK_UPDATE (1 << 31)
1366
1367 #define BYT_TX_OVF_INT 0x820
1368 #define BYT_TX_OVF_INT_MASK (1 << 1)
1369
1370 static void
1371 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1372 struct ktermios *old)
1373 {
1374 unsigned int baud = tty_termios_baud_rate(termios);
1375 unsigned long fref = 100000000, fuart = baud * 16;
1376 unsigned long w = BIT(15) - 1;
1377 unsigned long m, n;
1378 u32 reg;
1379
1380 /* Gracefully handle the B0 case: fall back to B9600 */
1381 fuart = fuart ? fuart : 9600 * 16;
1382
1383 /* Get Fuart closer to Fref */
1384 fuart *= rounddown_pow_of_two(fref / fuart);
1385
1386 /*
1387 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1388 * dividers must be adjusted.
1389 *
1390 * uartclk = (m / n) * 100 MHz, where m <= n
1391 */
1392 rational_best_approximation(fuart, fref, w, w, &m, &n);
1393 p->uartclk = fuart;
1394
1395 /* Reset the clock */
1396 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1397 writel(reg, p->membase + BYT_PRV_CLK);
1398 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1399 writel(reg, p->membase + BYT_PRV_CLK);
1400
1401 p->status &= ~UPSTAT_AUTOCTS;
1402 if (termios->c_cflag & CRTSCTS)
1403 p->status |= UPSTAT_AUTOCTS;
1404
1405 serial8250_do_set_termios(p, termios, old);
1406 }
1407
1408 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1409 {
1410 struct dw_dma_slave *dws = param;
1411
1412 if (dws->dma_dev != chan->device->dev)
1413 return false;
1414
1415 chan->private = dws;
1416 return true;
1417 }
1418
1419 static unsigned int
1420 byt_get_mctrl(struct uart_port *port)
1421 {
1422 unsigned int ret = serial8250_do_get_mctrl(port);
1423
1424 /* Force DCD and DSR signals to permanently be reported as active. */
1425 ret |= TIOCM_CAR | TIOCM_DSR;
1426
1427 return ret;
1428 }
1429
1430 static int
1431 byt_serial_setup(struct serial_private *priv,
1432 const struct pciserial_board *board,
1433 struct uart_8250_port *port, int idx)
1434 {
1435 struct pci_dev *pdev = priv->dev;
1436 struct device *dev = port->port.dev;
1437 struct uart_8250_dma *dma;
1438 struct dw_dma_slave *tx_param, *rx_param;
1439 struct pci_dev *dma_dev;
1440 int ret;
1441
1442 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1443 if (!dma)
1444 return -ENOMEM;
1445
1446 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1447 if (!tx_param)
1448 return -ENOMEM;
1449
1450 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1451 if (!rx_param)
1452 return -ENOMEM;
1453
1454 switch (pdev->device) {
1455 case PCI_DEVICE_ID_INTEL_BYT_UART1:
1456 case PCI_DEVICE_ID_INTEL_BSW_UART1:
1457 case PCI_DEVICE_ID_INTEL_BDW_UART1:
1458 rx_param->src_id = 3;
1459 tx_param->dst_id = 2;
1460 break;
1461 case PCI_DEVICE_ID_INTEL_BYT_UART2:
1462 case PCI_DEVICE_ID_INTEL_BSW_UART2:
1463 case PCI_DEVICE_ID_INTEL_BDW_UART2:
1464 rx_param->src_id = 5;
1465 tx_param->dst_id = 4;
1466 break;
1467 default:
1468 return -EINVAL;
1469 }
1470
1471 rx_param->m_master = 0;
1472 rx_param->p_master = 1;
1473
1474 dma->rxconf.src_maxburst = 16;
1475
1476 tx_param->m_master = 0;
1477 tx_param->p_master = 1;
1478
1479 dma->txconf.dst_maxburst = 16;
1480
1481 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1482 rx_param->dma_dev = &dma_dev->dev;
1483 tx_param->dma_dev = &dma_dev->dev;
1484
1485 dma->fn = byt_dma_filter;
1486 dma->rx_param = rx_param;
1487 dma->tx_param = tx_param;
1488
1489 ret = pci_default_setup(priv, board, port, idx);
1490 port->port.iotype = UPIO_MEM;
1491 port->port.type = PORT_16550A;
1492 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1493 port->port.set_termios = byt_set_termios;
1494 port->port.get_mctrl = byt_get_mctrl;
1495 port->port.fifosize = 64;
1496 port->tx_loadsz = 64;
1497 port->dma = dma;
1498 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1499
1500 /* Disable Tx counter interrupts */
1501 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1502
1503 return ret;
1504 }
1505
1506 static int
1507 pci_omegapci_setup(struct serial_private *priv,
1508 const struct pciserial_board *board,
1509 struct uart_8250_port *port, int idx)
1510 {
1511 return setup_port(priv, port, 2, idx * 8, 0);
1512 }
1513
1514 static int
1515 pci_brcm_trumanage_setup(struct serial_private *priv,
1516 const struct pciserial_board *board,
1517 struct uart_8250_port *port, int idx)
1518 {
1519 int ret = pci_default_setup(priv, board, port, idx);
1520
1521 port->port.type = PORT_BRCM_TRUMANAGE;
1522 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1523 return ret;
1524 }
1525
1526 /* RTS will control by MCR if this bit is 0 */
1527 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1528 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1529 #define FINTEK_RTS_INVERT BIT(5)
1530
1531 /* We should do proper H/W transceiver setting before change to RS485 mode */
1532 static int pci_fintek_rs485_config(struct uart_port *port,
1533 struct serial_rs485 *rs485)
1534 {
1535 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1536 u8 setting;
1537 u8 *index = (u8 *) port->private_data;
1538
1539 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1540
1541 if (!rs485)
1542 rs485 = &port->rs485;
1543 else if (rs485->flags & SER_RS485_ENABLED)
1544 memset(rs485->padding, 0, sizeof(rs485->padding));
1545 else
1546 memset(rs485, 0, sizeof(*rs485));
1547
1548 /* F81504/508/512 not support RTS delay before or after send */
1549 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1550
1551 if (rs485->flags & SER_RS485_ENABLED) {
1552 /* Enable RTS H/W control mode */
1553 setting |= FINTEK_RTS_CONTROL_BY_HW;
1554
1555 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1556 /* RTS driving high on TX */
1557 setting &= ~FINTEK_RTS_INVERT;
1558 } else {
1559 /* RTS driving low on TX */
1560 setting |= FINTEK_RTS_INVERT;
1561 }
1562
1563 rs485->delay_rts_after_send = 0;
1564 rs485->delay_rts_before_send = 0;
1565 } else {
1566 /* Disable RTS H/W control mode */
1567 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1568 }
1569
1570 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1571
1572 if (rs485 != &port->rs485)
1573 port->rs485 = *rs485;
1574
1575 return 0;
1576 }
1577
1578 static int pci_fintek_setup(struct serial_private *priv,
1579 const struct pciserial_board *board,
1580 struct uart_8250_port *port, int idx)
1581 {
1582 struct pci_dev *pdev = priv->dev;
1583 u8 *data;
1584 u8 config_base;
1585 u16 iobase;
1586
1587 config_base = 0x40 + 0x08 * idx;
1588
1589 /* Get the io address from configuration space */
1590 pci_read_config_word(pdev, config_base + 4, &iobase);
1591
1592 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1593
1594 port->port.iotype = UPIO_PORT;
1595 port->port.iobase = iobase;
1596 port->port.rs485_config = pci_fintek_rs485_config;
1597
1598 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1599 if (!data)
1600 return -ENOMEM;
1601
1602 /* preserve index in PCI configuration space */
1603 *data = idx;
1604 port->port.private_data = data;
1605
1606 return 0;
1607 }
1608
1609 static int pci_fintek_init(struct pci_dev *dev)
1610 {
1611 unsigned long iobase;
1612 u32 max_port, i;
1613 u32 bar_data[3];
1614 u8 config_base;
1615 struct serial_private *priv = pci_get_drvdata(dev);
1616 struct uart_8250_port *port;
1617
1618 switch (dev->device) {
1619 case 0x1104: /* 4 ports */
1620 case 0x1108: /* 8 ports */
1621 max_port = dev->device & 0xff;
1622 break;
1623 case 0x1112: /* 12 ports */
1624 max_port = 12;
1625 break;
1626 default:
1627 return -EINVAL;
1628 }
1629
1630 /* Get the io address dispatch from the BIOS */
1631 pci_read_config_dword(dev, 0x24, &bar_data[0]);
1632 pci_read_config_dword(dev, 0x20, &bar_data[1]);
1633 pci_read_config_dword(dev, 0x1c, &bar_data[2]);
1634
1635 for (i = 0; i < max_port; ++i) {
1636 /* UART0 configuration offset start from 0x40 */
1637 config_base = 0x40 + 0x08 * i;
1638
1639 /* Calculate Real IO Port */
1640 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1641
1642 /* Enable UART I/O port */
1643 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1644
1645 /* Select 128-byte FIFO and 8x FIFO threshold */
1646 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1647
1648 /* LSB UART */
1649 pci_write_config_byte(dev, config_base + 0x04,
1650 (u8)(iobase & 0xff));
1651
1652 /* MSB UART */
1653 pci_write_config_byte(dev, config_base + 0x05,
1654 (u8)((iobase & 0xff00) >> 8));
1655
1656 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1657
1658 if (priv) {
1659 /* re-apply RS232/485 mode when
1660 * pciserial_resume_ports()
1661 */
1662 port = serial8250_get_port(priv->line[i]);
1663 pci_fintek_rs485_config(&port->port, NULL);
1664 } else {
1665 /* First init without port data
1666 * force init to RS232 Mode
1667 */
1668 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1669 }
1670 }
1671
1672 return max_port;
1673 }
1674
1675 static int skip_tx_en_setup(struct serial_private *priv,
1676 const struct pciserial_board *board,
1677 struct uart_8250_port *port, int idx)
1678 {
1679 port->port.flags |= UPF_NO_TXEN_TEST;
1680 dev_dbg(&priv->dev->dev,
1681 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1682 priv->dev->vendor, priv->dev->device,
1683 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1684
1685 return pci_default_setup(priv, board, port, idx);
1686 }
1687
1688 static void kt_handle_break(struct uart_port *p)
1689 {
1690 struct uart_8250_port *up = up_to_u8250p(p);
1691 /*
1692 * On receipt of a BI, serial device in Intel ME (Intel
1693 * management engine) needs to have its fifos cleared for sane
1694 * SOL (Serial Over Lan) output.
1695 */
1696 serial8250_clear_and_reinit_fifos(up);
1697 }
1698
1699 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1700 {
1701 struct uart_8250_port *up = up_to_u8250p(p);
1702 unsigned int val;
1703
1704 /*
1705 * When the Intel ME (management engine) gets reset its serial
1706 * port registers could return 0 momentarily. Functions like
1707 * serial8250_console_write, read and save the IER, perform
1708 * some operation and then restore it. In order to avoid
1709 * setting IER register inadvertently to 0, if the value read
1710 * is 0, double check with ier value in uart_8250_port and use
1711 * that instead. up->ier should be the same value as what is
1712 * currently configured.
1713 */
1714 val = inb(p->iobase + offset);
1715 if (offset == UART_IER) {
1716 if (val == 0)
1717 val = up->ier;
1718 }
1719 return val;
1720 }
1721
1722 static int kt_serial_setup(struct serial_private *priv,
1723 const struct pciserial_board *board,
1724 struct uart_8250_port *port, int idx)
1725 {
1726 port->port.flags |= UPF_BUG_THRE;
1727 port->port.serial_in = kt_serial_in;
1728 port->port.handle_break = kt_handle_break;
1729 return skip_tx_en_setup(priv, board, port, idx);
1730 }
1731
1732 static int pci_eg20t_init(struct pci_dev *dev)
1733 {
1734 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1735 return -ENODEV;
1736 #else
1737 return 0;
1738 #endif
1739 }
1740
1741 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
1742 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
1743
1744 static int
1745 pci_xr17c154_setup(struct serial_private *priv,
1746 const struct pciserial_board *board,
1747 struct uart_8250_port *port, int idx)
1748 {
1749 port->port.flags |= UPF_EXAR_EFR;
1750 return pci_default_setup(priv, board, port, idx);
1751 }
1752
1753 static inline int
1754 xr17v35x_has_slave(struct serial_private *priv)
1755 {
1756 const int dev_id = priv->dev->device;
1757
1758 return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) ||
1759 (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358));
1760 }
1761
1762 static int
1763 pci_xr17v35x_setup(struct serial_private *priv,
1764 const struct pciserial_board *board,
1765 struct uart_8250_port *port, int idx)
1766 {
1767 u8 __iomem *p;
1768
1769 p = pci_ioremap_bar(priv->dev, 0);
1770 if (p == NULL)
1771 return -ENOMEM;
1772
1773 port->port.flags |= UPF_EXAR_EFR;
1774
1775 /*
1776 * Setup the uart clock for the devices on expansion slot to
1777 * half the clock speed of the main chip (which is 125MHz)
1778 */
1779 if (xr17v35x_has_slave(priv) && idx >= 8)
1780 port->port.uartclk = (7812500 * 16 / 2);
1781
1782 /*
1783 * Setup Multipurpose Input/Output pins.
1784 */
1785 if (idx == 0) {
1786 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1787 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1788 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1789 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1790 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1791 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1792 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1793 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1794 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1795 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1796 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1797 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1798 }
1799 writeb(0x00, p + UART_EXAR_8XMODE);
1800 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1801 writeb(128, p + UART_EXAR_TXTRG);
1802 writeb(128, p + UART_EXAR_RXTRG);
1803 iounmap(p);
1804
1805 return pci_default_setup(priv, board, port, idx);
1806 }
1807
1808 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1809 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1810 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1811 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1812
1813 static int
1814 pci_fastcom335_setup(struct serial_private *priv,
1815 const struct pciserial_board *board,
1816 struct uart_8250_port *port, int idx)
1817 {
1818 u8 __iomem *p;
1819
1820 p = pci_ioremap_bar(priv->dev, 0);
1821 if (p == NULL)
1822 return -ENOMEM;
1823
1824 port->port.flags |= UPF_EXAR_EFR;
1825
1826 /*
1827 * Setup Multipurpose Input/Output pins.
1828 */
1829 if (idx == 0) {
1830 switch (priv->dev->device) {
1831 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1832 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1833 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1834 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1835 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1836 break;
1837 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1838 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1839 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1840 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1841 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1842 break;
1843 }
1844 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1845 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1846 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1847 }
1848 writeb(0x00, p + UART_EXAR_8XMODE);
1849 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1850 writeb(32, p + UART_EXAR_TXTRG);
1851 writeb(32, p + UART_EXAR_RXTRG);
1852 iounmap(p);
1853
1854 return pci_default_setup(priv, board, port, idx);
1855 }
1856
1857 static int
1858 pci_wch_ch353_setup(struct serial_private *priv,
1859 const struct pciserial_board *board,
1860 struct uart_8250_port *port, int idx)
1861 {
1862 port->port.flags |= UPF_FIXED_TYPE;
1863 port->port.type = PORT_16550A;
1864 return pci_default_setup(priv, board, port, idx);
1865 }
1866
1867 static int
1868 pci_wch_ch355_setup(struct serial_private *priv,
1869 const struct pciserial_board *board,
1870 struct uart_8250_port *port, int idx)
1871 {
1872 port->port.flags |= UPF_FIXED_TYPE;
1873 port->port.type = PORT_16550A;
1874 return pci_default_setup(priv, board, port, idx);
1875 }
1876
1877 static int
1878 pci_wch_ch38x_setup(struct serial_private *priv,
1879 const struct pciserial_board *board,
1880 struct uart_8250_port *port, int idx)
1881 {
1882 port->port.flags |= UPF_FIXED_TYPE;
1883 port->port.type = PORT_16850;
1884 return pci_default_setup(priv, board, port, idx);
1885 }
1886
1887 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1888 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1889 #define PCI_DEVICE_ID_OCTPRO 0x0001
1890 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1891 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1892 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1893 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1894 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1895 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1896 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1897 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1898 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1899 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1900 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1901 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1902 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1903 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1904 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1905 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1906 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1907 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1908 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1909 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1910 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1911 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1912 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1913 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1914 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1915 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1916 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1917 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1918 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1919 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1920 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1921 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1922 #define PCI_VENDOR_ID_WCH 0x4348
1923 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1924 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1925 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1926 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1927 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1928 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
1929 #define PCI_VENDOR_ID_AGESTAR 0x5372
1930 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1931 #define PCI_VENDOR_ID_ASIX 0x9710
1932 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1933 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1934 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1935 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1936 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1937 #define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936
1938
1939 #define PCI_VENDOR_ID_SUNIX 0x1fd4
1940 #define PCI_DEVICE_ID_SUNIX_1999 0x1999
1941
1942 #define PCIE_VENDOR_ID_WCH 0x1c00
1943 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1944 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1945 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1946
1947 #define PCI_VENDOR_ID_PERICOM 0x12D8
1948 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951
1949 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952
1950 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954
1951 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958
1952
1953 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1954 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1955 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1956
1957 /*
1958 * Master list of serial port init/setup/exit quirks.
1959 * This does not describe the general nature of the port.
1960 * (ie, baud base, number and location of ports, etc)
1961 *
1962 * This list is ordered alphabetically by vendor then device.
1963 * Specific entries must come before more generic entries.
1964 */
1965 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1966 /*
1967 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1968 */
1969 {
1970 .vendor = PCI_VENDOR_ID_AMCC,
1971 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1972 .subvendor = PCI_ANY_ID,
1973 .subdevice = PCI_ANY_ID,
1974 .setup = addidata_apci7800_setup,
1975 },
1976 /*
1977 * AFAVLAB cards - these may be called via parport_serial
1978 * It is not clear whether this applies to all products.
1979 */
1980 {
1981 .vendor = PCI_VENDOR_ID_AFAVLAB,
1982 .device = PCI_ANY_ID,
1983 .subvendor = PCI_ANY_ID,
1984 .subdevice = PCI_ANY_ID,
1985 .setup = afavlab_setup,
1986 },
1987 /*
1988 * HP Diva
1989 */
1990 {
1991 .vendor = PCI_VENDOR_ID_HP,
1992 .device = PCI_DEVICE_ID_HP_DIVA,
1993 .subvendor = PCI_ANY_ID,
1994 .subdevice = PCI_ANY_ID,
1995 .init = pci_hp_diva_init,
1996 .setup = pci_hp_diva_setup,
1997 },
1998 /*
1999 * Intel
2000 */
2001 {
2002 .vendor = PCI_VENDOR_ID_INTEL,
2003 .device = PCI_DEVICE_ID_INTEL_80960_RP,
2004 .subvendor = 0xe4bf,
2005 .subdevice = PCI_ANY_ID,
2006 .init = pci_inteli960ni_init,
2007 .setup = pci_default_setup,
2008 },
2009 {
2010 .vendor = PCI_VENDOR_ID_INTEL,
2011 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2012 .subvendor = PCI_ANY_ID,
2013 .subdevice = PCI_ANY_ID,
2014 .setup = skip_tx_en_setup,
2015 },
2016 {
2017 .vendor = PCI_VENDOR_ID_INTEL,
2018 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2019 .subvendor = PCI_ANY_ID,
2020 .subdevice = PCI_ANY_ID,
2021 .setup = skip_tx_en_setup,
2022 },
2023 {
2024 .vendor = PCI_VENDOR_ID_INTEL,
2025 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2026 .subvendor = PCI_ANY_ID,
2027 .subdevice = PCI_ANY_ID,
2028 .setup = skip_tx_en_setup,
2029 },
2030 {
2031 .vendor = PCI_VENDOR_ID_INTEL,
2032 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2033 .subvendor = PCI_ANY_ID,
2034 .subdevice = PCI_ANY_ID,
2035 .setup = ce4100_serial_setup,
2036 },
2037 {
2038 .vendor = PCI_VENDOR_ID_INTEL,
2039 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2040 .subvendor = PCI_ANY_ID,
2041 .subdevice = PCI_ANY_ID,
2042 .setup = kt_serial_setup,
2043 },
2044 {
2045 .vendor = PCI_VENDOR_ID_INTEL,
2046 .device = PCI_DEVICE_ID_INTEL_BYT_UART1,
2047 .subvendor = PCI_ANY_ID,
2048 .subdevice = PCI_ANY_ID,
2049 .setup = byt_serial_setup,
2050 },
2051 {
2052 .vendor = PCI_VENDOR_ID_INTEL,
2053 .device = PCI_DEVICE_ID_INTEL_BYT_UART2,
2054 .subvendor = PCI_ANY_ID,
2055 .subdevice = PCI_ANY_ID,
2056 .setup = byt_serial_setup,
2057 },
2058 {
2059 .vendor = PCI_VENDOR_ID_INTEL,
2060 .device = PCI_DEVICE_ID_INTEL_BSW_UART1,
2061 .subvendor = PCI_ANY_ID,
2062 .subdevice = PCI_ANY_ID,
2063 .setup = byt_serial_setup,
2064 },
2065 {
2066 .vendor = PCI_VENDOR_ID_INTEL,
2067 .device = PCI_DEVICE_ID_INTEL_BSW_UART2,
2068 .subvendor = PCI_ANY_ID,
2069 .subdevice = PCI_ANY_ID,
2070 .setup = byt_serial_setup,
2071 },
2072 {
2073 .vendor = PCI_VENDOR_ID_INTEL,
2074 .device = PCI_DEVICE_ID_INTEL_BDW_UART1,
2075 .subvendor = PCI_ANY_ID,
2076 .subdevice = PCI_ANY_ID,
2077 .setup = byt_serial_setup,
2078 },
2079 {
2080 .vendor = PCI_VENDOR_ID_INTEL,
2081 .device = PCI_DEVICE_ID_INTEL_BDW_UART2,
2082 .subvendor = PCI_ANY_ID,
2083 .subdevice = PCI_ANY_ID,
2084 .setup = byt_serial_setup,
2085 },
2086 /*
2087 * ITE
2088 */
2089 {
2090 .vendor = PCI_VENDOR_ID_ITE,
2091 .device = PCI_DEVICE_ID_ITE_8872,
2092 .subvendor = PCI_ANY_ID,
2093 .subdevice = PCI_ANY_ID,
2094 .init = pci_ite887x_init,
2095 .setup = pci_default_setup,
2096 .exit = pci_ite887x_exit,
2097 },
2098 /*
2099 * National Instruments
2100 */
2101 {
2102 .vendor = PCI_VENDOR_ID_NI,
2103 .device = PCI_DEVICE_ID_NI_PCI23216,
2104 .subvendor = PCI_ANY_ID,
2105 .subdevice = PCI_ANY_ID,
2106 .init = pci_ni8420_init,
2107 .setup = pci_default_setup,
2108 .exit = pci_ni8420_exit,
2109 },
2110 {
2111 .vendor = PCI_VENDOR_ID_NI,
2112 .device = PCI_DEVICE_ID_NI_PCI2328,
2113 .subvendor = PCI_ANY_ID,
2114 .subdevice = PCI_ANY_ID,
2115 .init = pci_ni8420_init,
2116 .setup = pci_default_setup,
2117 .exit = pci_ni8420_exit,
2118 },
2119 {
2120 .vendor = PCI_VENDOR_ID_NI,
2121 .device = PCI_DEVICE_ID_NI_PCI2324,
2122 .subvendor = PCI_ANY_ID,
2123 .subdevice = PCI_ANY_ID,
2124 .init = pci_ni8420_init,
2125 .setup = pci_default_setup,
2126 .exit = pci_ni8420_exit,
2127 },
2128 {
2129 .vendor = PCI_VENDOR_ID_NI,
2130 .device = PCI_DEVICE_ID_NI_PCI2322,
2131 .subvendor = PCI_ANY_ID,
2132 .subdevice = PCI_ANY_ID,
2133 .init = pci_ni8420_init,
2134 .setup = pci_default_setup,
2135 .exit = pci_ni8420_exit,
2136 },
2137 {
2138 .vendor = PCI_VENDOR_ID_NI,
2139 .device = PCI_DEVICE_ID_NI_PCI2324I,
2140 .subvendor = PCI_ANY_ID,
2141 .subdevice = PCI_ANY_ID,
2142 .init = pci_ni8420_init,
2143 .setup = pci_default_setup,
2144 .exit = pci_ni8420_exit,
2145 },
2146 {
2147 .vendor = PCI_VENDOR_ID_NI,
2148 .device = PCI_DEVICE_ID_NI_PCI2322I,
2149 .subvendor = PCI_ANY_ID,
2150 .subdevice = PCI_ANY_ID,
2151 .init = pci_ni8420_init,
2152 .setup = pci_default_setup,
2153 .exit = pci_ni8420_exit,
2154 },
2155 {
2156 .vendor = PCI_VENDOR_ID_NI,
2157 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2158 .subvendor = PCI_ANY_ID,
2159 .subdevice = PCI_ANY_ID,
2160 .init = pci_ni8420_init,
2161 .setup = pci_default_setup,
2162 .exit = pci_ni8420_exit,
2163 },
2164 {
2165 .vendor = PCI_VENDOR_ID_NI,
2166 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2167 .subvendor = PCI_ANY_ID,
2168 .subdevice = PCI_ANY_ID,
2169 .init = pci_ni8420_init,
2170 .setup = pci_default_setup,
2171 .exit = pci_ni8420_exit,
2172 },
2173 {
2174 .vendor = PCI_VENDOR_ID_NI,
2175 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2176 .subvendor = PCI_ANY_ID,
2177 .subdevice = PCI_ANY_ID,
2178 .init = pci_ni8420_init,
2179 .setup = pci_default_setup,
2180 .exit = pci_ni8420_exit,
2181 },
2182 {
2183 .vendor = PCI_VENDOR_ID_NI,
2184 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2185 .subvendor = PCI_ANY_ID,
2186 .subdevice = PCI_ANY_ID,
2187 .init = pci_ni8420_init,
2188 .setup = pci_default_setup,
2189 .exit = pci_ni8420_exit,
2190 },
2191 {
2192 .vendor = PCI_VENDOR_ID_NI,
2193 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2194 .subvendor = PCI_ANY_ID,
2195 .subdevice = PCI_ANY_ID,
2196 .init = pci_ni8420_init,
2197 .setup = pci_default_setup,
2198 .exit = pci_ni8420_exit,
2199 },
2200 {
2201 .vendor = PCI_VENDOR_ID_NI,
2202 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2203 .subvendor = PCI_ANY_ID,
2204 .subdevice = PCI_ANY_ID,
2205 .init = pci_ni8420_init,
2206 .setup = pci_default_setup,
2207 .exit = pci_ni8420_exit,
2208 },
2209 {
2210 .vendor = PCI_VENDOR_ID_NI,
2211 .device = PCI_ANY_ID,
2212 .subvendor = PCI_ANY_ID,
2213 .subdevice = PCI_ANY_ID,
2214 .init = pci_ni8430_init,
2215 .setup = pci_ni8430_setup,
2216 .exit = pci_ni8430_exit,
2217 },
2218 /* Quatech */
2219 {
2220 .vendor = PCI_VENDOR_ID_QUATECH,
2221 .device = PCI_ANY_ID,
2222 .subvendor = PCI_ANY_ID,
2223 .subdevice = PCI_ANY_ID,
2224 .init = pci_quatech_init,
2225 .setup = pci_quatech_setup,
2226 .exit = pci_quatech_exit,
2227 },
2228 /*
2229 * Panacom
2230 */
2231 {
2232 .vendor = PCI_VENDOR_ID_PANACOM,
2233 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2234 .subvendor = PCI_ANY_ID,
2235 .subdevice = PCI_ANY_ID,
2236 .init = pci_plx9050_init,
2237 .setup = pci_default_setup,
2238 .exit = pci_plx9050_exit,
2239 },
2240 {
2241 .vendor = PCI_VENDOR_ID_PANACOM,
2242 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2243 .subvendor = PCI_ANY_ID,
2244 .subdevice = PCI_ANY_ID,
2245 .init = pci_plx9050_init,
2246 .setup = pci_default_setup,
2247 .exit = pci_plx9050_exit,
2248 },
2249 /*
2250 * PLX
2251 */
2252 {
2253 .vendor = PCI_VENDOR_ID_PLX,
2254 .device = PCI_DEVICE_ID_PLX_9050,
2255 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2256 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2257 .init = pci_plx9050_init,
2258 .setup = pci_default_setup,
2259 .exit = pci_plx9050_exit,
2260 },
2261 {
2262 .vendor = PCI_VENDOR_ID_PLX,
2263 .device = PCI_DEVICE_ID_PLX_9050,
2264 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2265 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2266 .init = pci_plx9050_init,
2267 .setup = pci_default_setup,
2268 .exit = pci_plx9050_exit,
2269 },
2270 {
2271 .vendor = PCI_VENDOR_ID_PLX,
2272 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2273 .subvendor = PCI_VENDOR_ID_PLX,
2274 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2275 .init = pci_plx9050_init,
2276 .setup = pci_default_setup,
2277 .exit = pci_plx9050_exit,
2278 },
2279 /*
2280 * SBS Technologies, Inc., PMC-OCTALPRO 232
2281 */
2282 {
2283 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2284 .device = PCI_DEVICE_ID_OCTPRO,
2285 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2286 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2287 .init = sbs_init,
2288 .setup = sbs_setup,
2289 .exit = sbs_exit,
2290 },
2291 /*
2292 * SBS Technologies, Inc., PMC-OCTALPRO 422
2293 */
2294 {
2295 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2296 .device = PCI_DEVICE_ID_OCTPRO,
2297 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2298 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2299 .init = sbs_init,
2300 .setup = sbs_setup,
2301 .exit = sbs_exit,
2302 },
2303 /*
2304 * SBS Technologies, Inc., P-Octal 232
2305 */
2306 {
2307 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2308 .device = PCI_DEVICE_ID_OCTPRO,
2309 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2310 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2311 .init = sbs_init,
2312 .setup = sbs_setup,
2313 .exit = sbs_exit,
2314 },
2315 /*
2316 * SBS Technologies, Inc., P-Octal 422
2317 */
2318 {
2319 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2320 .device = PCI_DEVICE_ID_OCTPRO,
2321 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2322 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2323 .init = sbs_init,
2324 .setup = sbs_setup,
2325 .exit = sbs_exit,
2326 },
2327 /*
2328 * SIIG cards - these may be called via parport_serial
2329 */
2330 {
2331 .vendor = PCI_VENDOR_ID_SIIG,
2332 .device = PCI_ANY_ID,
2333 .subvendor = PCI_ANY_ID,
2334 .subdevice = PCI_ANY_ID,
2335 .init = pci_siig_init,
2336 .setup = pci_siig_setup,
2337 },
2338 /*
2339 * Titan cards
2340 */
2341 {
2342 .vendor = PCI_VENDOR_ID_TITAN,
2343 .device = PCI_DEVICE_ID_TITAN_400L,
2344 .subvendor = PCI_ANY_ID,
2345 .subdevice = PCI_ANY_ID,
2346 .setup = titan_400l_800l_setup,
2347 },
2348 {
2349 .vendor = PCI_VENDOR_ID_TITAN,
2350 .device = PCI_DEVICE_ID_TITAN_800L,
2351 .subvendor = PCI_ANY_ID,
2352 .subdevice = PCI_ANY_ID,
2353 .setup = titan_400l_800l_setup,
2354 },
2355 /*
2356 * Timedia cards
2357 */
2358 {
2359 .vendor = PCI_VENDOR_ID_TIMEDIA,
2360 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2361 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2362 .subdevice = PCI_ANY_ID,
2363 .probe = pci_timedia_probe,
2364 .init = pci_timedia_init,
2365 .setup = pci_timedia_setup,
2366 },
2367 {
2368 .vendor = PCI_VENDOR_ID_TIMEDIA,
2369 .device = PCI_ANY_ID,
2370 .subvendor = PCI_ANY_ID,
2371 .subdevice = PCI_ANY_ID,
2372 .setup = pci_timedia_setup,
2373 },
2374 /*
2375 * SUNIX (Timedia) cards
2376 * Do not "probe" for these cards as there is at least one combination
2377 * card that should be handled by parport_pc that doesn't match the
2378 * rule in pci_timedia_probe.
2379 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2380 * There are some boards with part number SER5037AL that report
2381 * subdevice ID 0x0002.
2382 */
2383 {
2384 .vendor = PCI_VENDOR_ID_SUNIX,
2385 .device = PCI_DEVICE_ID_SUNIX_1999,
2386 .subvendor = PCI_VENDOR_ID_SUNIX,
2387 .subdevice = PCI_ANY_ID,
2388 .init = pci_timedia_init,
2389 .setup = pci_timedia_setup,
2390 },
2391 /*
2392 * Exar cards
2393 */
2394 {
2395 .vendor = PCI_VENDOR_ID_EXAR,
2396 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2397 .subvendor = PCI_ANY_ID,
2398 .subdevice = PCI_ANY_ID,
2399 .setup = pci_xr17c154_setup,
2400 },
2401 {
2402 .vendor = PCI_VENDOR_ID_EXAR,
2403 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2404 .subvendor = PCI_ANY_ID,
2405 .subdevice = PCI_ANY_ID,
2406 .setup = pci_xr17c154_setup,
2407 },
2408 {
2409 .vendor = PCI_VENDOR_ID_EXAR,
2410 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2411 .subvendor = PCI_ANY_ID,
2412 .subdevice = PCI_ANY_ID,
2413 .setup = pci_xr17c154_setup,
2414 },
2415 {
2416 .vendor = PCI_VENDOR_ID_EXAR,
2417 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2418 .subvendor = PCI_ANY_ID,
2419 .subdevice = PCI_ANY_ID,
2420 .setup = pci_xr17v35x_setup,
2421 },
2422 {
2423 .vendor = PCI_VENDOR_ID_EXAR,
2424 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2425 .subvendor = PCI_ANY_ID,
2426 .subdevice = PCI_ANY_ID,
2427 .setup = pci_xr17v35x_setup,
2428 },
2429 {
2430 .vendor = PCI_VENDOR_ID_EXAR,
2431 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2432 .subvendor = PCI_ANY_ID,
2433 .subdevice = PCI_ANY_ID,
2434 .setup = pci_xr17v35x_setup,
2435 },
2436 {
2437 .vendor = PCI_VENDOR_ID_EXAR,
2438 .device = PCI_DEVICE_ID_EXAR_XR17V4358,
2439 .subvendor = PCI_ANY_ID,
2440 .subdevice = PCI_ANY_ID,
2441 .setup = pci_xr17v35x_setup,
2442 },
2443 {
2444 .vendor = PCI_VENDOR_ID_EXAR,
2445 .device = PCI_DEVICE_ID_EXAR_XR17V8358,
2446 .subvendor = PCI_ANY_ID,
2447 .subdevice = PCI_ANY_ID,
2448 .setup = pci_xr17v35x_setup,
2449 },
2450 /*
2451 * Xircom cards
2452 */
2453 {
2454 .vendor = PCI_VENDOR_ID_XIRCOM,
2455 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2456 .subvendor = PCI_ANY_ID,
2457 .subdevice = PCI_ANY_ID,
2458 .init = pci_xircom_init,
2459 .setup = pci_default_setup,
2460 },
2461 /*
2462 * Netmos cards - these may be called via parport_serial
2463 */
2464 {
2465 .vendor = PCI_VENDOR_ID_NETMOS,
2466 .device = PCI_ANY_ID,
2467 .subvendor = PCI_ANY_ID,
2468 .subdevice = PCI_ANY_ID,
2469 .init = pci_netmos_init,
2470 .setup = pci_netmos_9900_setup,
2471 },
2472 /*
2473 * EndRun Technologies
2474 */
2475 {
2476 .vendor = PCI_VENDOR_ID_ENDRUN,
2477 .device = PCI_ANY_ID,
2478 .subvendor = PCI_ANY_ID,
2479 .subdevice = PCI_ANY_ID,
2480 .init = pci_endrun_init,
2481 .setup = pci_default_setup,
2482 },
2483 /*
2484 * For Oxford Semiconductor Tornado based devices
2485 */
2486 {
2487 .vendor = PCI_VENDOR_ID_OXSEMI,
2488 .device = PCI_ANY_ID,
2489 .subvendor = PCI_ANY_ID,
2490 .subdevice = PCI_ANY_ID,
2491 .init = pci_oxsemi_tornado_init,
2492 .setup = pci_default_setup,
2493 },
2494 {
2495 .vendor = PCI_VENDOR_ID_MAINPINE,
2496 .device = PCI_ANY_ID,
2497 .subvendor = PCI_ANY_ID,
2498 .subdevice = PCI_ANY_ID,
2499 .init = pci_oxsemi_tornado_init,
2500 .setup = pci_default_setup,
2501 },
2502 {
2503 .vendor = PCI_VENDOR_ID_DIGI,
2504 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2505 .subvendor = PCI_SUBVENDOR_ID_IBM,
2506 .subdevice = PCI_ANY_ID,
2507 .init = pci_oxsemi_tornado_init,
2508 .setup = pci_default_setup,
2509 },
2510 {
2511 .vendor = PCI_VENDOR_ID_INTEL,
2512 .device = 0x8811,
2513 .subvendor = PCI_ANY_ID,
2514 .subdevice = PCI_ANY_ID,
2515 .init = pci_eg20t_init,
2516 .setup = pci_default_setup,
2517 },
2518 {
2519 .vendor = PCI_VENDOR_ID_INTEL,
2520 .device = 0x8812,
2521 .subvendor = PCI_ANY_ID,
2522 .subdevice = PCI_ANY_ID,
2523 .init = pci_eg20t_init,
2524 .setup = pci_default_setup,
2525 },
2526 {
2527 .vendor = PCI_VENDOR_ID_INTEL,
2528 .device = 0x8813,
2529 .subvendor = PCI_ANY_ID,
2530 .subdevice = PCI_ANY_ID,
2531 .init = pci_eg20t_init,
2532 .setup = pci_default_setup,
2533 },
2534 {
2535 .vendor = PCI_VENDOR_ID_INTEL,
2536 .device = 0x8814,
2537 .subvendor = PCI_ANY_ID,
2538 .subdevice = PCI_ANY_ID,
2539 .init = pci_eg20t_init,
2540 .setup = pci_default_setup,
2541 },
2542 {
2543 .vendor = 0x10DB,
2544 .device = 0x8027,
2545 .subvendor = PCI_ANY_ID,
2546 .subdevice = PCI_ANY_ID,
2547 .init = pci_eg20t_init,
2548 .setup = pci_default_setup,
2549 },
2550 {
2551 .vendor = 0x10DB,
2552 .device = 0x8028,
2553 .subvendor = PCI_ANY_ID,
2554 .subdevice = PCI_ANY_ID,
2555 .init = pci_eg20t_init,
2556 .setup = pci_default_setup,
2557 },
2558 {
2559 .vendor = 0x10DB,
2560 .device = 0x8029,
2561 .subvendor = PCI_ANY_ID,
2562 .subdevice = PCI_ANY_ID,
2563 .init = pci_eg20t_init,
2564 .setup = pci_default_setup,
2565 },
2566 {
2567 .vendor = 0x10DB,
2568 .device = 0x800C,
2569 .subvendor = PCI_ANY_ID,
2570 .subdevice = PCI_ANY_ID,
2571 .init = pci_eg20t_init,
2572 .setup = pci_default_setup,
2573 },
2574 {
2575 .vendor = 0x10DB,
2576 .device = 0x800D,
2577 .subvendor = PCI_ANY_ID,
2578 .subdevice = PCI_ANY_ID,
2579 .init = pci_eg20t_init,
2580 .setup = pci_default_setup,
2581 },
2582 /*
2583 * Cronyx Omega PCI (PLX-chip based)
2584 */
2585 {
2586 .vendor = PCI_VENDOR_ID_PLX,
2587 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2588 .subvendor = PCI_ANY_ID,
2589 .subdevice = PCI_ANY_ID,
2590 .setup = pci_omegapci_setup,
2591 },
2592 /* WCH CH353 1S1P card (16550 clone) */
2593 {
2594 .vendor = PCI_VENDOR_ID_WCH,
2595 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2596 .subvendor = PCI_ANY_ID,
2597 .subdevice = PCI_ANY_ID,
2598 .setup = pci_wch_ch353_setup,
2599 },
2600 /* WCH CH353 2S1P card (16550 clone) */
2601 {
2602 .vendor = PCI_VENDOR_ID_WCH,
2603 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2604 .subvendor = PCI_ANY_ID,
2605 .subdevice = PCI_ANY_ID,
2606 .setup = pci_wch_ch353_setup,
2607 },
2608 /* WCH CH353 4S card (16550 clone) */
2609 {
2610 .vendor = PCI_VENDOR_ID_WCH,
2611 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2612 .subvendor = PCI_ANY_ID,
2613 .subdevice = PCI_ANY_ID,
2614 .setup = pci_wch_ch353_setup,
2615 },
2616 /* WCH CH353 2S1PF card (16550 clone) */
2617 {
2618 .vendor = PCI_VENDOR_ID_WCH,
2619 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2620 .subvendor = PCI_ANY_ID,
2621 .subdevice = PCI_ANY_ID,
2622 .setup = pci_wch_ch353_setup,
2623 },
2624 /* WCH CH352 2S card (16550 clone) */
2625 {
2626 .vendor = PCI_VENDOR_ID_WCH,
2627 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2628 .subvendor = PCI_ANY_ID,
2629 .subdevice = PCI_ANY_ID,
2630 .setup = pci_wch_ch353_setup,
2631 },
2632 /* WCH CH355 4S card (16550 clone) */
2633 {
2634 .vendor = PCI_VENDOR_ID_WCH,
2635 .device = PCI_DEVICE_ID_WCH_CH355_4S,
2636 .subvendor = PCI_ANY_ID,
2637 .subdevice = PCI_ANY_ID,
2638 .setup = pci_wch_ch355_setup,
2639 },
2640 /* WCH CH382 2S card (16850 clone) */
2641 {
2642 .vendor = PCIE_VENDOR_ID_WCH,
2643 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2644 .subvendor = PCI_ANY_ID,
2645 .subdevice = PCI_ANY_ID,
2646 .setup = pci_wch_ch38x_setup,
2647 },
2648 /* WCH CH382 2S1P card (16850 clone) */
2649 {
2650 .vendor = PCIE_VENDOR_ID_WCH,
2651 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2652 .subvendor = PCI_ANY_ID,
2653 .subdevice = PCI_ANY_ID,
2654 .setup = pci_wch_ch38x_setup,
2655 },
2656 /* WCH CH384 4S card (16850 clone) */
2657 {
2658 .vendor = PCIE_VENDOR_ID_WCH,
2659 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2660 .subvendor = PCI_ANY_ID,
2661 .subdevice = PCI_ANY_ID,
2662 .setup = pci_wch_ch38x_setup,
2663 },
2664 /*
2665 * ASIX devices with FIFO bug
2666 */
2667 {
2668 .vendor = PCI_VENDOR_ID_ASIX,
2669 .device = PCI_ANY_ID,
2670 .subvendor = PCI_ANY_ID,
2671 .subdevice = PCI_ANY_ID,
2672 .setup = pci_asix_setup,
2673 },
2674 /*
2675 * Commtech, Inc. Fastcom adapters
2676 *
2677 */
2678 {
2679 .vendor = PCI_VENDOR_ID_COMMTECH,
2680 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2681 .subvendor = PCI_ANY_ID,
2682 .subdevice = PCI_ANY_ID,
2683 .setup = pci_fastcom335_setup,
2684 },
2685 {
2686 .vendor = PCI_VENDOR_ID_COMMTECH,
2687 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2688 .subvendor = PCI_ANY_ID,
2689 .subdevice = PCI_ANY_ID,
2690 .setup = pci_fastcom335_setup,
2691 },
2692 {
2693 .vendor = PCI_VENDOR_ID_COMMTECH,
2694 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2695 .subvendor = PCI_ANY_ID,
2696 .subdevice = PCI_ANY_ID,
2697 .setup = pci_fastcom335_setup,
2698 },
2699 {
2700 .vendor = PCI_VENDOR_ID_COMMTECH,
2701 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2702 .subvendor = PCI_ANY_ID,
2703 .subdevice = PCI_ANY_ID,
2704 .setup = pci_fastcom335_setup,
2705 },
2706 {
2707 .vendor = PCI_VENDOR_ID_COMMTECH,
2708 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2709 .subvendor = PCI_ANY_ID,
2710 .subdevice = PCI_ANY_ID,
2711 .setup = pci_xr17v35x_setup,
2712 },
2713 {
2714 .vendor = PCI_VENDOR_ID_COMMTECH,
2715 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2716 .subvendor = PCI_ANY_ID,
2717 .subdevice = PCI_ANY_ID,
2718 .setup = pci_xr17v35x_setup,
2719 },
2720 {
2721 .vendor = PCI_VENDOR_ID_COMMTECH,
2722 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2723 .subvendor = PCI_ANY_ID,
2724 .subdevice = PCI_ANY_ID,
2725 .setup = pci_xr17v35x_setup,
2726 },
2727 /*
2728 * Broadcom TruManage (NetXtreme)
2729 */
2730 {
2731 .vendor = PCI_VENDOR_ID_BROADCOM,
2732 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2733 .subvendor = PCI_ANY_ID,
2734 .subdevice = PCI_ANY_ID,
2735 .setup = pci_brcm_trumanage_setup,
2736 },
2737 {
2738 .vendor = 0x1c29,
2739 .device = 0x1104,
2740 .subvendor = PCI_ANY_ID,
2741 .subdevice = PCI_ANY_ID,
2742 .setup = pci_fintek_setup,
2743 .init = pci_fintek_init,
2744 },
2745 {
2746 .vendor = 0x1c29,
2747 .device = 0x1108,
2748 .subvendor = PCI_ANY_ID,
2749 .subdevice = PCI_ANY_ID,
2750 .setup = pci_fintek_setup,
2751 .init = pci_fintek_init,
2752 },
2753 {
2754 .vendor = 0x1c29,
2755 .device = 0x1112,
2756 .subvendor = PCI_ANY_ID,
2757 .subdevice = PCI_ANY_ID,
2758 .setup = pci_fintek_setup,
2759 .init = pci_fintek_init,
2760 },
2761
2762 /*
2763 * Default "match everything" terminator entry
2764 */
2765 {
2766 .vendor = PCI_ANY_ID,
2767 .device = PCI_ANY_ID,
2768 .subvendor = PCI_ANY_ID,
2769 .subdevice = PCI_ANY_ID,
2770 .setup = pci_default_setup,
2771 }
2772 };
2773
2774 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2775 {
2776 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2777 }
2778
2779 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2780 {
2781 struct pci_serial_quirk *quirk;
2782
2783 for (quirk = pci_serial_quirks; ; quirk++)
2784 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2785 quirk_id_matches(quirk->device, dev->device) &&
2786 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2787 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2788 break;
2789 return quirk;
2790 }
2791
2792 static inline int get_pci_irq(struct pci_dev *dev,
2793 const struct pciserial_board *board)
2794 {
2795 if (board->flags & FL_NOIRQ)
2796 return 0;
2797 else
2798 return dev->irq;
2799 }
2800
2801 /*
2802 * This is the configuration table for all of the PCI serial boards
2803 * which we support. It is directly indexed by the pci_board_num_t enum
2804 * value, which is encoded in the pci_device_id PCI probe table's
2805 * driver_data member.
2806 *
2807 * The makeup of these names are:
2808 * pbn_bn{_bt}_n_baud{_offsetinhex}
2809 *
2810 * bn = PCI BAR number
2811 * bt = Index using PCI BARs
2812 * n = number of serial ports
2813 * baud = baud rate
2814 * offsetinhex = offset for each sequential port (in hex)
2815 *
2816 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2817 *
2818 * Please note: in theory if n = 1, _bt infix should make no difference.
2819 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2820 */
2821 enum pci_board_num_t {
2822 pbn_default = 0,
2823
2824 pbn_b0_1_115200,
2825 pbn_b0_2_115200,
2826 pbn_b0_4_115200,
2827 pbn_b0_5_115200,
2828 pbn_b0_8_115200,
2829
2830 pbn_b0_1_921600,
2831 pbn_b0_2_921600,
2832 pbn_b0_4_921600,
2833
2834 pbn_b0_2_1130000,
2835
2836 pbn_b0_4_1152000,
2837
2838 pbn_b0_2_1152000_200,
2839 pbn_b0_4_1152000_200,
2840 pbn_b0_8_1152000_200,
2841
2842 pbn_b0_2_1843200,
2843 pbn_b0_4_1843200,
2844
2845 pbn_b0_2_1843200_200,
2846 pbn_b0_4_1843200_200,
2847 pbn_b0_8_1843200_200,
2848
2849 pbn_b0_1_4000000,
2850
2851 pbn_b0_bt_1_115200,
2852 pbn_b0_bt_2_115200,
2853 pbn_b0_bt_4_115200,
2854 pbn_b0_bt_8_115200,
2855
2856 pbn_b0_bt_1_460800,
2857 pbn_b0_bt_2_460800,
2858 pbn_b0_bt_4_460800,
2859
2860 pbn_b0_bt_1_921600,
2861 pbn_b0_bt_2_921600,
2862 pbn_b0_bt_4_921600,
2863 pbn_b0_bt_8_921600,
2864
2865 pbn_b1_1_115200,
2866 pbn_b1_2_115200,
2867 pbn_b1_4_115200,
2868 pbn_b1_8_115200,
2869 pbn_b1_16_115200,
2870
2871 pbn_b1_1_921600,
2872 pbn_b1_2_921600,
2873 pbn_b1_4_921600,
2874 pbn_b1_8_921600,
2875
2876 pbn_b1_2_1250000,
2877
2878 pbn_b1_bt_1_115200,
2879 pbn_b1_bt_2_115200,
2880 pbn_b1_bt_4_115200,
2881
2882 pbn_b1_bt_2_921600,
2883
2884 pbn_b1_1_1382400,
2885 pbn_b1_2_1382400,
2886 pbn_b1_4_1382400,
2887 pbn_b1_8_1382400,
2888
2889 pbn_b2_1_115200,
2890 pbn_b2_2_115200,
2891 pbn_b2_4_115200,
2892 pbn_b2_8_115200,
2893
2894 pbn_b2_1_460800,
2895 pbn_b2_4_460800,
2896 pbn_b2_8_460800,
2897 pbn_b2_16_460800,
2898
2899 pbn_b2_1_921600,
2900 pbn_b2_4_921600,
2901 pbn_b2_8_921600,
2902
2903 pbn_b2_8_1152000,
2904
2905 pbn_b2_bt_1_115200,
2906 pbn_b2_bt_2_115200,
2907 pbn_b2_bt_4_115200,
2908
2909 pbn_b2_bt_2_921600,
2910 pbn_b2_bt_4_921600,
2911
2912 pbn_b3_2_115200,
2913 pbn_b3_4_115200,
2914 pbn_b3_8_115200,
2915
2916 pbn_b4_bt_2_921600,
2917 pbn_b4_bt_4_921600,
2918 pbn_b4_bt_8_921600,
2919
2920 /*
2921 * Board-specific versions.
2922 */
2923 pbn_panacom,
2924 pbn_panacom2,
2925 pbn_panacom4,
2926 pbn_plx_romulus,
2927 pbn_endrun_2_4000000,
2928 pbn_oxsemi,
2929 pbn_oxsemi_1_4000000,
2930 pbn_oxsemi_2_4000000,
2931 pbn_oxsemi_4_4000000,
2932 pbn_oxsemi_8_4000000,
2933 pbn_intel_i960,
2934 pbn_sgi_ioc3,
2935 pbn_computone_4,
2936 pbn_computone_6,
2937 pbn_computone_8,
2938 pbn_sbsxrsio,
2939 pbn_exar_XR17C152,
2940 pbn_exar_XR17C154,
2941 pbn_exar_XR17C158,
2942 pbn_exar_XR17V352,
2943 pbn_exar_XR17V354,
2944 pbn_exar_XR17V358,
2945 pbn_exar_XR17V4358,
2946 pbn_exar_XR17V8358,
2947 pbn_exar_ibm_saturn,
2948 pbn_pasemi_1682M,
2949 pbn_ni8430_2,
2950 pbn_ni8430_4,
2951 pbn_ni8430_8,
2952 pbn_ni8430_16,
2953 pbn_ADDIDATA_PCIe_1_3906250,
2954 pbn_ADDIDATA_PCIe_2_3906250,
2955 pbn_ADDIDATA_PCIe_4_3906250,
2956 pbn_ADDIDATA_PCIe_8_3906250,
2957 pbn_ce4100_1_115200,
2958 pbn_byt,
2959 pbn_qrk,
2960 pbn_omegapci,
2961 pbn_NETMOS9900_2s_115200,
2962 pbn_brcm_trumanage,
2963 pbn_fintek_4,
2964 pbn_fintek_8,
2965 pbn_fintek_12,
2966 pbn_wch382_2,
2967 pbn_wch384_4,
2968 pbn_pericom_PI7C9X7951,
2969 pbn_pericom_PI7C9X7952,
2970 pbn_pericom_PI7C9X7954,
2971 pbn_pericom_PI7C9X7958,
2972 };
2973
2974 /*
2975 * uart_offset - the space between channels
2976 * reg_shift - describes how the UART registers are mapped
2977 * to PCI memory by the card.
2978 * For example IER register on SBS, Inc. PMC-OctPro is located at
2979 * offset 0x10 from the UART base, while UART_IER is defined as 1
2980 * in include/linux/serial_reg.h,
2981 * see first lines of serial_in() and serial_out() in 8250.c
2982 */
2983
2984 static struct pciserial_board pci_boards[] = {
2985 [pbn_default] = {
2986 .flags = FL_BASE0,
2987 .num_ports = 1,
2988 .base_baud = 115200,
2989 .uart_offset = 8,
2990 },
2991 [pbn_b0_1_115200] = {
2992 .flags = FL_BASE0,
2993 .num_ports = 1,
2994 .base_baud = 115200,
2995 .uart_offset = 8,
2996 },
2997 [pbn_b0_2_115200] = {
2998 .flags = FL_BASE0,
2999 .num_ports = 2,
3000 .base_baud = 115200,
3001 .uart_offset = 8,
3002 },
3003 [pbn_b0_4_115200] = {
3004 .flags = FL_BASE0,
3005 .num_ports = 4,
3006 .base_baud = 115200,
3007 .uart_offset = 8,
3008 },
3009 [pbn_b0_5_115200] = {
3010 .flags = FL_BASE0,
3011 .num_ports = 5,
3012 .base_baud = 115200,
3013 .uart_offset = 8,
3014 },
3015 [pbn_b0_8_115200] = {
3016 .flags = FL_BASE0,
3017 .num_ports = 8,
3018 .base_baud = 115200,
3019 .uart_offset = 8,
3020 },
3021 [pbn_b0_1_921600] = {
3022 .flags = FL_BASE0,
3023 .num_ports = 1,
3024 .base_baud = 921600,
3025 .uart_offset = 8,
3026 },
3027 [pbn_b0_2_921600] = {
3028 .flags = FL_BASE0,
3029 .num_ports = 2,
3030 .base_baud = 921600,
3031 .uart_offset = 8,
3032 },
3033 [pbn_b0_4_921600] = {
3034 .flags = FL_BASE0,
3035 .num_ports = 4,
3036 .base_baud = 921600,
3037 .uart_offset = 8,
3038 },
3039
3040 [pbn_b0_2_1130000] = {
3041 .flags = FL_BASE0,
3042 .num_ports = 2,
3043 .base_baud = 1130000,
3044 .uart_offset = 8,
3045 },
3046
3047 [pbn_b0_4_1152000] = {
3048 .flags = FL_BASE0,
3049 .num_ports = 4,
3050 .base_baud = 1152000,
3051 .uart_offset = 8,
3052 },
3053
3054 [pbn_b0_2_1152000_200] = {
3055 .flags = FL_BASE0,
3056 .num_ports = 2,
3057 .base_baud = 1152000,
3058 .uart_offset = 0x200,
3059 },
3060
3061 [pbn_b0_4_1152000_200] = {
3062 .flags = FL_BASE0,
3063 .num_ports = 4,
3064 .base_baud = 1152000,
3065 .uart_offset = 0x200,
3066 },
3067
3068 [pbn_b0_8_1152000_200] = {
3069 .flags = FL_BASE0,
3070 .num_ports = 8,
3071 .base_baud = 1152000,
3072 .uart_offset = 0x200,
3073 },
3074
3075 [pbn_b0_2_1843200] = {
3076 .flags = FL_BASE0,
3077 .num_ports = 2,
3078 .base_baud = 1843200,
3079 .uart_offset = 8,
3080 },
3081 [pbn_b0_4_1843200] = {
3082 .flags = FL_BASE0,
3083 .num_ports = 4,
3084 .base_baud = 1843200,
3085 .uart_offset = 8,
3086 },
3087
3088 [pbn_b0_2_1843200_200] = {
3089 .flags = FL_BASE0,
3090 .num_ports = 2,
3091 .base_baud = 1843200,
3092 .uart_offset = 0x200,
3093 },
3094 [pbn_b0_4_1843200_200] = {
3095 .flags = FL_BASE0,
3096 .num_ports = 4,
3097 .base_baud = 1843200,
3098 .uart_offset = 0x200,
3099 },
3100 [pbn_b0_8_1843200_200] = {
3101 .flags = FL_BASE0,
3102 .num_ports = 8,
3103 .base_baud = 1843200,
3104 .uart_offset = 0x200,
3105 },
3106 [pbn_b0_1_4000000] = {
3107 .flags = FL_BASE0,
3108 .num_ports = 1,
3109 .base_baud = 4000000,
3110 .uart_offset = 8,
3111 },
3112
3113 [pbn_b0_bt_1_115200] = {
3114 .flags = FL_BASE0|FL_BASE_BARS,
3115 .num_ports = 1,
3116 .base_baud = 115200,
3117 .uart_offset = 8,
3118 },
3119 [pbn_b0_bt_2_115200] = {
3120 .flags = FL_BASE0|FL_BASE_BARS,
3121 .num_ports = 2,
3122 .base_baud = 115200,
3123 .uart_offset = 8,
3124 },
3125 [pbn_b0_bt_4_115200] = {
3126 .flags = FL_BASE0|FL_BASE_BARS,
3127 .num_ports = 4,
3128 .base_baud = 115200,
3129 .uart_offset = 8,
3130 },
3131 [pbn_b0_bt_8_115200] = {
3132 .flags = FL_BASE0|FL_BASE_BARS,
3133 .num_ports = 8,
3134 .base_baud = 115200,
3135 .uart_offset = 8,
3136 },
3137
3138 [pbn_b0_bt_1_460800] = {
3139 .flags = FL_BASE0|FL_BASE_BARS,
3140 .num_ports = 1,
3141 .base_baud = 460800,
3142 .uart_offset = 8,
3143 },
3144 [pbn_b0_bt_2_460800] = {
3145 .flags = FL_BASE0|FL_BASE_BARS,
3146 .num_ports = 2,
3147 .base_baud = 460800,
3148 .uart_offset = 8,
3149 },
3150 [pbn_b0_bt_4_460800] = {
3151 .flags = FL_BASE0|FL_BASE_BARS,
3152 .num_ports = 4,
3153 .base_baud = 460800,
3154 .uart_offset = 8,
3155 },
3156
3157 [pbn_b0_bt_1_921600] = {
3158 .flags = FL_BASE0|FL_BASE_BARS,
3159 .num_ports = 1,
3160 .base_baud = 921600,
3161 .uart_offset = 8,
3162 },
3163 [pbn_b0_bt_2_921600] = {
3164 .flags = FL_BASE0|FL_BASE_BARS,
3165 .num_ports = 2,
3166 .base_baud = 921600,
3167 .uart_offset = 8,
3168 },
3169 [pbn_b0_bt_4_921600] = {
3170 .flags = FL_BASE0|FL_BASE_BARS,
3171 .num_ports = 4,
3172 .base_baud = 921600,
3173 .uart_offset = 8,
3174 },
3175 [pbn_b0_bt_8_921600] = {
3176 .flags = FL_BASE0|FL_BASE_BARS,
3177 .num_ports = 8,
3178 .base_baud = 921600,
3179 .uart_offset = 8,
3180 },
3181
3182 [pbn_b1_1_115200] = {
3183 .flags = FL_BASE1,
3184 .num_ports = 1,
3185 .base_baud = 115200,
3186 .uart_offset = 8,
3187 },
3188 [pbn_b1_2_115200] = {
3189 .flags = FL_BASE1,
3190 .num_ports = 2,
3191 .base_baud = 115200,
3192 .uart_offset = 8,
3193 },
3194 [pbn_b1_4_115200] = {
3195 .flags = FL_BASE1,
3196 .num_ports = 4,
3197 .base_baud = 115200,
3198 .uart_offset = 8,
3199 },
3200 [pbn_b1_8_115200] = {
3201 .flags = FL_BASE1,
3202 .num_ports = 8,
3203 .base_baud = 115200,
3204 .uart_offset = 8,
3205 },
3206 [pbn_b1_16_115200] = {
3207 .flags = FL_BASE1,
3208 .num_ports = 16,
3209 .base_baud = 115200,
3210 .uart_offset = 8,
3211 },
3212
3213 [pbn_b1_1_921600] = {
3214 .flags = FL_BASE1,
3215 .num_ports = 1,
3216 .base_baud = 921600,
3217 .uart_offset = 8,
3218 },
3219 [pbn_b1_2_921600] = {
3220 .flags = FL_BASE1,
3221 .num_ports = 2,
3222 .base_baud = 921600,
3223 .uart_offset = 8,
3224 },
3225 [pbn_b1_4_921600] = {
3226 .flags = FL_BASE1,
3227 .num_ports = 4,
3228 .base_baud = 921600,
3229 .uart_offset = 8,
3230 },
3231 [pbn_b1_8_921600] = {
3232 .flags = FL_BASE1,
3233 .num_ports = 8,
3234 .base_baud = 921600,
3235 .uart_offset = 8,
3236 },
3237 [pbn_b1_2_1250000] = {
3238 .flags = FL_BASE1,
3239 .num_ports = 2,
3240 .base_baud = 1250000,
3241 .uart_offset = 8,
3242 },
3243
3244 [pbn_b1_bt_1_115200] = {
3245 .flags = FL_BASE1|FL_BASE_BARS,
3246 .num_ports = 1,
3247 .base_baud = 115200,
3248 .uart_offset = 8,
3249 },
3250 [pbn_b1_bt_2_115200] = {
3251 .flags = FL_BASE1|FL_BASE_BARS,
3252 .num_ports = 2,
3253 .base_baud = 115200,
3254 .uart_offset = 8,
3255 },
3256 [pbn_b1_bt_4_115200] = {
3257 .flags = FL_BASE1|FL_BASE_BARS,
3258 .num_ports = 4,
3259 .base_baud = 115200,
3260 .uart_offset = 8,
3261 },
3262
3263 [pbn_b1_bt_2_921600] = {
3264 .flags = FL_BASE1|FL_BASE_BARS,
3265 .num_ports = 2,
3266 .base_baud = 921600,
3267 .uart_offset = 8,
3268 },
3269
3270 [pbn_b1_1_1382400] = {
3271 .flags = FL_BASE1,
3272 .num_ports = 1,
3273 .base_baud = 1382400,
3274 .uart_offset = 8,
3275 },
3276 [pbn_b1_2_1382400] = {
3277 .flags = FL_BASE1,
3278 .num_ports = 2,
3279 .base_baud = 1382400,
3280 .uart_offset = 8,
3281 },
3282 [pbn_b1_4_1382400] = {
3283 .flags = FL_BASE1,
3284 .num_ports = 4,
3285 .base_baud = 1382400,
3286 .uart_offset = 8,
3287 },
3288 [pbn_b1_8_1382400] = {
3289 .flags = FL_BASE1,
3290 .num_ports = 8,
3291 .base_baud = 1382400,
3292 .uart_offset = 8,
3293 },
3294
3295 [pbn_b2_1_115200] = {
3296 .flags = FL_BASE2,
3297 .num_ports = 1,
3298 .base_baud = 115200,
3299 .uart_offset = 8,
3300 },
3301 [pbn_b2_2_115200] = {
3302 .flags = FL_BASE2,
3303 .num_ports = 2,
3304 .base_baud = 115200,
3305 .uart_offset = 8,
3306 },
3307 [pbn_b2_4_115200] = {
3308 .flags = FL_BASE2,
3309 .num_ports = 4,
3310 .base_baud = 115200,
3311 .uart_offset = 8,
3312 },
3313 [pbn_b2_8_115200] = {
3314 .flags = FL_BASE2,
3315 .num_ports = 8,
3316 .base_baud = 115200,
3317 .uart_offset = 8,
3318 },
3319
3320 [pbn_b2_1_460800] = {
3321 .flags = FL_BASE2,
3322 .num_ports = 1,
3323 .base_baud = 460800,
3324 .uart_offset = 8,
3325 },
3326 [pbn_b2_4_460800] = {
3327 .flags = FL_BASE2,
3328 .num_ports = 4,
3329 .base_baud = 460800,
3330 .uart_offset = 8,
3331 },
3332 [pbn_b2_8_460800] = {
3333 .flags = FL_BASE2,
3334 .num_ports = 8,
3335 .base_baud = 460800,
3336 .uart_offset = 8,
3337 },
3338 [pbn_b2_16_460800] = {
3339 .flags = FL_BASE2,
3340 .num_ports = 16,
3341 .base_baud = 460800,
3342 .uart_offset = 8,
3343 },
3344
3345 [pbn_b2_1_921600] = {
3346 .flags = FL_BASE2,
3347 .num_ports = 1,
3348 .base_baud = 921600,
3349 .uart_offset = 8,
3350 },
3351 [pbn_b2_4_921600] = {
3352 .flags = FL_BASE2,
3353 .num_ports = 4,
3354 .base_baud = 921600,
3355 .uart_offset = 8,
3356 },
3357 [pbn_b2_8_921600] = {
3358 .flags = FL_BASE2,
3359 .num_ports = 8,
3360 .base_baud = 921600,
3361 .uart_offset = 8,
3362 },
3363
3364 [pbn_b2_8_1152000] = {
3365 .flags = FL_BASE2,
3366 .num_ports = 8,
3367 .base_baud = 1152000,
3368 .uart_offset = 8,
3369 },
3370
3371 [pbn_b2_bt_1_115200] = {
3372 .flags = FL_BASE2|FL_BASE_BARS,
3373 .num_ports = 1,
3374 .base_baud = 115200,
3375 .uart_offset = 8,
3376 },
3377 [pbn_b2_bt_2_115200] = {
3378 .flags = FL_BASE2|FL_BASE_BARS,
3379 .num_ports = 2,
3380 .base_baud = 115200,
3381 .uart_offset = 8,
3382 },
3383 [pbn_b2_bt_4_115200] = {
3384 .flags = FL_BASE2|FL_BASE_BARS,
3385 .num_ports = 4,
3386 .base_baud = 115200,
3387 .uart_offset = 8,
3388 },
3389
3390 [pbn_b2_bt_2_921600] = {
3391 .flags = FL_BASE2|FL_BASE_BARS,
3392 .num_ports = 2,
3393 .base_baud = 921600,
3394 .uart_offset = 8,
3395 },
3396 [pbn_b2_bt_4_921600] = {
3397 .flags = FL_BASE2|FL_BASE_BARS,
3398 .num_ports = 4,
3399 .base_baud = 921600,
3400 .uart_offset = 8,
3401 },
3402
3403 [pbn_b3_2_115200] = {
3404 .flags = FL_BASE3,
3405 .num_ports = 2,
3406 .base_baud = 115200,
3407 .uart_offset = 8,
3408 },
3409 [pbn_b3_4_115200] = {
3410 .flags = FL_BASE3,
3411 .num_ports = 4,
3412 .base_baud = 115200,
3413 .uart_offset = 8,
3414 },
3415 [pbn_b3_8_115200] = {
3416 .flags = FL_BASE3,
3417 .num_ports = 8,
3418 .base_baud = 115200,
3419 .uart_offset = 8,
3420 },
3421
3422 [pbn_b4_bt_2_921600] = {
3423 .flags = FL_BASE4,
3424 .num_ports = 2,
3425 .base_baud = 921600,
3426 .uart_offset = 8,
3427 },
3428 [pbn_b4_bt_4_921600] = {
3429 .flags = FL_BASE4,
3430 .num_ports = 4,
3431 .base_baud = 921600,
3432 .uart_offset = 8,
3433 },
3434 [pbn_b4_bt_8_921600] = {
3435 .flags = FL_BASE4,
3436 .num_ports = 8,
3437 .base_baud = 921600,
3438 .uart_offset = 8,
3439 },
3440
3441 /*
3442 * Entries following this are board-specific.
3443 */
3444
3445 /*
3446 * Panacom - IOMEM
3447 */
3448 [pbn_panacom] = {
3449 .flags = FL_BASE2,
3450 .num_ports = 2,
3451 .base_baud = 921600,
3452 .uart_offset = 0x400,
3453 .reg_shift = 7,
3454 },
3455 [pbn_panacom2] = {
3456 .flags = FL_BASE2|FL_BASE_BARS,
3457 .num_ports = 2,
3458 .base_baud = 921600,
3459 .uart_offset = 0x400,
3460 .reg_shift = 7,
3461 },
3462 [pbn_panacom4] = {
3463 .flags = FL_BASE2|FL_BASE_BARS,
3464 .num_ports = 4,
3465 .base_baud = 921600,
3466 .uart_offset = 0x400,
3467 .reg_shift = 7,
3468 },
3469
3470 /* I think this entry is broken - the first_offset looks wrong --rmk */
3471 [pbn_plx_romulus] = {
3472 .flags = FL_BASE2,
3473 .num_ports = 4,
3474 .base_baud = 921600,
3475 .uart_offset = 8 << 2,
3476 .reg_shift = 2,
3477 .first_offset = 0x03,
3478 },
3479
3480 /*
3481 * EndRun Technologies
3482 * Uses the size of PCI Base region 0 to
3483 * signal now many ports are available
3484 * 2 port 952 Uart support
3485 */
3486 [pbn_endrun_2_4000000] = {
3487 .flags = FL_BASE0,
3488 .num_ports = 2,
3489 .base_baud = 4000000,
3490 .uart_offset = 0x200,
3491 .first_offset = 0x1000,
3492 },
3493
3494 /*
3495 * This board uses the size of PCI Base region 0 to
3496 * signal now many ports are available
3497 */
3498 [pbn_oxsemi] = {
3499 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3500 .num_ports = 32,
3501 .base_baud = 115200,
3502 .uart_offset = 8,
3503 },
3504 [pbn_oxsemi_1_4000000] = {
3505 .flags = FL_BASE0,
3506 .num_ports = 1,
3507 .base_baud = 4000000,
3508 .uart_offset = 0x200,
3509 .first_offset = 0x1000,
3510 },
3511 [pbn_oxsemi_2_4000000] = {
3512 .flags = FL_BASE0,
3513 .num_ports = 2,
3514 .base_baud = 4000000,
3515 .uart_offset = 0x200,
3516 .first_offset = 0x1000,
3517 },
3518 [pbn_oxsemi_4_4000000] = {
3519 .flags = FL_BASE0,
3520 .num_ports = 4,
3521 .base_baud = 4000000,
3522 .uart_offset = 0x200,
3523 .first_offset = 0x1000,
3524 },
3525 [pbn_oxsemi_8_4000000] = {
3526 .flags = FL_BASE0,
3527 .num_ports = 8,
3528 .base_baud = 4000000,
3529 .uart_offset = 0x200,
3530 .first_offset = 0x1000,
3531 },
3532
3533
3534 /*
3535 * EKF addition for i960 Boards form EKF with serial port.
3536 * Max 256 ports.
3537 */
3538 [pbn_intel_i960] = {
3539 .flags = FL_BASE0,
3540 .num_ports = 32,
3541 .base_baud = 921600,
3542 .uart_offset = 8 << 2,
3543 .reg_shift = 2,
3544 .first_offset = 0x10000,
3545 },
3546 [pbn_sgi_ioc3] = {
3547 .flags = FL_BASE0|FL_NOIRQ,
3548 .num_ports = 1,
3549 .base_baud = 458333,
3550 .uart_offset = 8,
3551 .reg_shift = 0,
3552 .first_offset = 0x20178,
3553 },
3554
3555 /*
3556 * Computone - uses IOMEM.
3557 */
3558 [pbn_computone_4] = {
3559 .flags = FL_BASE0,
3560 .num_ports = 4,
3561 .base_baud = 921600,
3562 .uart_offset = 0x40,
3563 .reg_shift = 2,
3564 .first_offset = 0x200,
3565 },
3566 [pbn_computone_6] = {
3567 .flags = FL_BASE0,
3568 .num_ports = 6,
3569 .base_baud = 921600,
3570 .uart_offset = 0x40,
3571 .reg_shift = 2,
3572 .first_offset = 0x200,
3573 },
3574 [pbn_computone_8] = {
3575 .flags = FL_BASE0,
3576 .num_ports = 8,
3577 .base_baud = 921600,
3578 .uart_offset = 0x40,
3579 .reg_shift = 2,
3580 .first_offset = 0x200,
3581 },
3582 [pbn_sbsxrsio] = {
3583 .flags = FL_BASE0,
3584 .num_ports = 8,
3585 .base_baud = 460800,
3586 .uart_offset = 256,
3587 .reg_shift = 4,
3588 },
3589 /*
3590 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3591 * Only basic 16550A support.
3592 * XR17C15[24] are not tested, but they should work.
3593 */
3594 [pbn_exar_XR17C152] = {
3595 .flags = FL_BASE0,
3596 .num_ports = 2,
3597 .base_baud = 921600,
3598 .uart_offset = 0x200,
3599 },
3600 [pbn_exar_XR17C154] = {
3601 .flags = FL_BASE0,
3602 .num_ports = 4,
3603 .base_baud = 921600,
3604 .uart_offset = 0x200,
3605 },
3606 [pbn_exar_XR17C158] = {
3607 .flags = FL_BASE0,
3608 .num_ports = 8,
3609 .base_baud = 921600,
3610 .uart_offset = 0x200,
3611 },
3612 [pbn_exar_XR17V352] = {
3613 .flags = FL_BASE0,
3614 .num_ports = 2,
3615 .base_baud = 7812500,
3616 .uart_offset = 0x400,
3617 .reg_shift = 0,
3618 .first_offset = 0,
3619 },
3620 [pbn_exar_XR17V354] = {
3621 .flags = FL_BASE0,
3622 .num_ports = 4,
3623 .base_baud = 7812500,
3624 .uart_offset = 0x400,
3625 .reg_shift = 0,
3626 .first_offset = 0,
3627 },
3628 [pbn_exar_XR17V358] = {
3629 .flags = FL_BASE0,
3630 .num_ports = 8,
3631 .base_baud = 7812500,
3632 .uart_offset = 0x400,
3633 .reg_shift = 0,
3634 .first_offset = 0,
3635 },
3636 [pbn_exar_XR17V4358] = {
3637 .flags = FL_BASE0,
3638 .num_ports = 12,
3639 .base_baud = 7812500,
3640 .uart_offset = 0x400,
3641 .reg_shift = 0,
3642 .first_offset = 0,
3643 },
3644 [pbn_exar_XR17V8358] = {
3645 .flags = FL_BASE0,
3646 .num_ports = 16,
3647 .base_baud = 7812500,
3648 .uart_offset = 0x400,
3649 .reg_shift = 0,
3650 .first_offset = 0,
3651 },
3652 [pbn_exar_ibm_saturn] = {
3653 .flags = FL_BASE0,
3654 .num_ports = 1,
3655 .base_baud = 921600,
3656 .uart_offset = 0x200,
3657 },
3658
3659 /*
3660 * PA Semi PWRficient PA6T-1682M on-chip UART
3661 */
3662 [pbn_pasemi_1682M] = {
3663 .flags = FL_BASE0,
3664 .num_ports = 1,
3665 .base_baud = 8333333,
3666 },
3667 /*
3668 * National Instruments 843x
3669 */
3670 [pbn_ni8430_16] = {
3671 .flags = FL_BASE0,
3672 .num_ports = 16,
3673 .base_baud = 3686400,
3674 .uart_offset = 0x10,
3675 .first_offset = 0x800,
3676 },
3677 [pbn_ni8430_8] = {
3678 .flags = FL_BASE0,
3679 .num_ports = 8,
3680 .base_baud = 3686400,
3681 .uart_offset = 0x10,
3682 .first_offset = 0x800,
3683 },
3684 [pbn_ni8430_4] = {
3685 .flags = FL_BASE0,
3686 .num_ports = 4,
3687 .base_baud = 3686400,
3688 .uart_offset = 0x10,
3689 .first_offset = 0x800,
3690 },
3691 [pbn_ni8430_2] = {
3692 .flags = FL_BASE0,
3693 .num_ports = 2,
3694 .base_baud = 3686400,
3695 .uart_offset = 0x10,
3696 .first_offset = 0x800,
3697 },
3698 /*
3699 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3700 */
3701 [pbn_ADDIDATA_PCIe_1_3906250] = {
3702 .flags = FL_BASE0,
3703 .num_ports = 1,
3704 .base_baud = 3906250,
3705 .uart_offset = 0x200,
3706 .first_offset = 0x1000,
3707 },
3708 [pbn_ADDIDATA_PCIe_2_3906250] = {
3709 .flags = FL_BASE0,
3710 .num_ports = 2,
3711 .base_baud = 3906250,
3712 .uart_offset = 0x200,
3713 .first_offset = 0x1000,
3714 },
3715 [pbn_ADDIDATA_PCIe_4_3906250] = {
3716 .flags = FL_BASE0,
3717 .num_ports = 4,
3718 .base_baud = 3906250,
3719 .uart_offset = 0x200,
3720 .first_offset = 0x1000,
3721 },
3722 [pbn_ADDIDATA_PCIe_8_3906250] = {
3723 .flags = FL_BASE0,
3724 .num_ports = 8,
3725 .base_baud = 3906250,
3726 .uart_offset = 0x200,
3727 .first_offset = 0x1000,
3728 },
3729 [pbn_ce4100_1_115200] = {
3730 .flags = FL_BASE_BARS,
3731 .num_ports = 2,
3732 .base_baud = 921600,
3733 .reg_shift = 2,
3734 },
3735 [pbn_byt] = {
3736 .flags = FL_BASE0,
3737 .num_ports = 1,
3738 .base_baud = 2764800,
3739 .reg_shift = 2,
3740 },
3741 [pbn_qrk] = {
3742 .flags = FL_BASE0,
3743 .num_ports = 1,
3744 .base_baud = 2764800,
3745 .reg_shift = 2,
3746 },
3747 [pbn_omegapci] = {
3748 .flags = FL_BASE0,
3749 .num_ports = 8,
3750 .base_baud = 115200,
3751 .uart_offset = 0x200,
3752 },
3753 [pbn_NETMOS9900_2s_115200] = {
3754 .flags = FL_BASE0,
3755 .num_ports = 2,
3756 .base_baud = 115200,
3757 },
3758 [pbn_brcm_trumanage] = {
3759 .flags = FL_BASE0,
3760 .num_ports = 1,
3761 .reg_shift = 2,
3762 .base_baud = 115200,
3763 },
3764 [pbn_fintek_4] = {
3765 .num_ports = 4,
3766 .uart_offset = 8,
3767 .base_baud = 115200,
3768 .first_offset = 0x40,
3769 },
3770 [pbn_fintek_8] = {
3771 .num_ports = 8,
3772 .uart_offset = 8,
3773 .base_baud = 115200,
3774 .first_offset = 0x40,
3775 },
3776 [pbn_fintek_12] = {
3777 .num_ports = 12,
3778 .uart_offset = 8,
3779 .base_baud = 115200,
3780 .first_offset = 0x40,
3781 },
3782 [pbn_wch382_2] = {
3783 .flags = FL_BASE0,
3784 .num_ports = 2,
3785 .base_baud = 115200,
3786 .uart_offset = 8,
3787 .first_offset = 0xC0,
3788 },
3789 [pbn_wch384_4] = {
3790 .flags = FL_BASE0,
3791 .num_ports = 4,
3792 .base_baud = 115200,
3793 .uart_offset = 8,
3794 .first_offset = 0xC0,
3795 },
3796 /*
3797 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3798 */
3799 [pbn_pericom_PI7C9X7951] = {
3800 .flags = FL_BASE0,
3801 .num_ports = 1,
3802 .base_baud = 921600,
3803 .uart_offset = 0x8,
3804 },
3805 [pbn_pericom_PI7C9X7952] = {
3806 .flags = FL_BASE0,
3807 .num_ports = 2,
3808 .base_baud = 921600,
3809 .uart_offset = 0x8,
3810 },
3811 [pbn_pericom_PI7C9X7954] = {
3812 .flags = FL_BASE0,
3813 .num_ports = 4,
3814 .base_baud = 921600,
3815 .uart_offset = 0x8,
3816 },
3817 [pbn_pericom_PI7C9X7958] = {
3818 .flags = FL_BASE0,
3819 .num_ports = 8,
3820 .base_baud = 921600,
3821 .uart_offset = 0x8,
3822 },
3823 };
3824
3825 static const struct pci_device_id blacklist[] = {
3826 /* softmodems */
3827 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3828 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3829 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3830
3831 /* multi-io cards handled by parport_serial */
3832 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3833 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3834 { PCI_DEVICE(0x4348, 0x7173), }, /* WCH CH355 4S */
3835 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3836 { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
3837
3838 /* Moxa Smartio MUE boards handled by 8250_moxa */
3839 { PCI_VDEVICE(MOXA, 0x1024), },
3840 { PCI_VDEVICE(MOXA, 0x1025), },
3841 { PCI_VDEVICE(MOXA, 0x1045), },
3842 { PCI_VDEVICE(MOXA, 0x1144), },
3843 { PCI_VDEVICE(MOXA, 0x1160), },
3844 { PCI_VDEVICE(MOXA, 0x1161), },
3845 { PCI_VDEVICE(MOXA, 0x1182), },
3846 { PCI_VDEVICE(MOXA, 0x1183), },
3847 { PCI_VDEVICE(MOXA, 0x1322), },
3848 { PCI_VDEVICE(MOXA, 0x1342), },
3849 { PCI_VDEVICE(MOXA, 0x1381), },
3850 { PCI_VDEVICE(MOXA, 0x1683), },
3851
3852 /* Intel platforms with MID UART */
3853 { PCI_VDEVICE(INTEL, 0x081b), },
3854 { PCI_VDEVICE(INTEL, 0x081c), },
3855 { PCI_VDEVICE(INTEL, 0x081d), },
3856 { PCI_VDEVICE(INTEL, 0x1191), },
3857 { PCI_VDEVICE(INTEL, 0x19d8), },
3858 };
3859
3860 /*
3861 * Given a complete unknown PCI device, try to use some heuristics to
3862 * guess what the configuration might be, based on the pitiful PCI
3863 * serial specs. Returns 0 on success, 1 on failure.
3864 */
3865 static int
3866 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3867 {
3868 const struct pci_device_id *bldev;
3869 int num_iomem, num_port, first_port = -1, i;
3870
3871 /*
3872 * If it is not a communications device or the programming
3873 * interface is greater than 6, give up.
3874 *
3875 * (Should we try to make guesses for multiport serial devices
3876 * later?)
3877 */
3878 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3879 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3880 (dev->class & 0xff) > 6)
3881 return -ENODEV;
3882
3883 /*
3884 * Do not access blacklisted devices that are known not to
3885 * feature serial ports or are handled by other modules.
3886 */
3887 for (bldev = blacklist;
3888 bldev < blacklist + ARRAY_SIZE(blacklist);
3889 bldev++) {
3890 if (dev->vendor == bldev->vendor &&
3891 dev->device == bldev->device)
3892 return -ENODEV;
3893 }
3894
3895 num_iomem = num_port = 0;
3896 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3897 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3898 num_port++;
3899 if (first_port == -1)
3900 first_port = i;
3901 }
3902 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3903 num_iomem++;
3904 }
3905
3906 /*
3907 * If there is 1 or 0 iomem regions, and exactly one port,
3908 * use it. We guess the number of ports based on the IO
3909 * region size.
3910 */
3911 if (num_iomem <= 1 && num_port == 1) {
3912 board->flags = first_port;
3913 board->num_ports = pci_resource_len(dev, first_port) / 8;
3914 return 0;
3915 }
3916
3917 /*
3918 * Now guess if we've got a board which indexes by BARs.
3919 * Each IO BAR should be 8 bytes, and they should follow
3920 * consecutively.
3921 */
3922 first_port = -1;
3923 num_port = 0;
3924 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3925 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3926 pci_resource_len(dev, i) == 8 &&
3927 (first_port == -1 || (first_port + num_port) == i)) {
3928 num_port++;
3929 if (first_port == -1)
3930 first_port = i;
3931 }
3932 }
3933
3934 if (num_port > 1) {
3935 board->flags = first_port | FL_BASE_BARS;
3936 board->num_ports = num_port;
3937 return 0;
3938 }
3939
3940 return -ENODEV;
3941 }
3942
3943 static inline int
3944 serial_pci_matches(const struct pciserial_board *board,
3945 const struct pciserial_board *guessed)
3946 {
3947 return
3948 board->num_ports == guessed->num_ports &&
3949 board->base_baud == guessed->base_baud &&
3950 board->uart_offset == guessed->uart_offset &&
3951 board->reg_shift == guessed->reg_shift &&
3952 board->first_offset == guessed->first_offset;
3953 }
3954
3955 struct serial_private *
3956 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3957 {
3958 struct uart_8250_port uart;
3959 struct serial_private *priv;
3960 struct pci_serial_quirk *quirk;
3961 int rc, nr_ports, i;
3962
3963 nr_ports = board->num_ports;
3964
3965 /*
3966 * Find an init and setup quirks.
3967 */
3968 quirk = find_quirk(dev);
3969
3970 /*
3971 * Run the new-style initialization function.
3972 * The initialization function returns:
3973 * <0 - error
3974 * 0 - use board->num_ports
3975 * >0 - number of ports
3976 */
3977 if (quirk->init) {
3978 rc = quirk->init(dev);
3979 if (rc < 0) {
3980 priv = ERR_PTR(rc);
3981 goto err_out;
3982 }
3983 if (rc)
3984 nr_ports = rc;
3985 }
3986
3987 priv = kzalloc(sizeof(struct serial_private) +
3988 sizeof(unsigned int) * nr_ports,
3989 GFP_KERNEL);
3990 if (!priv) {
3991 priv = ERR_PTR(-ENOMEM);
3992 goto err_deinit;
3993 }
3994
3995 priv->dev = dev;
3996 priv->quirk = quirk;
3997
3998 memset(&uart, 0, sizeof(uart));
3999 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
4000 uart.port.uartclk = board->base_baud * 16;
4001 uart.port.irq = get_pci_irq(dev, board);
4002 uart.port.dev = &dev->dev;
4003
4004 for (i = 0; i < nr_ports; i++) {
4005 if (quirk->setup(priv, board, &uart, i))
4006 break;
4007
4008 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4009 uart.port.iobase, uart.port.irq, uart.port.iotype);
4010
4011 priv->line[i] = serial8250_register_8250_port(&uart);
4012 if (priv->line[i] < 0) {
4013 dev_err(&dev->dev,
4014 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4015 uart.port.iobase, uart.port.irq,
4016 uart.port.iotype, priv->line[i]);
4017 break;
4018 }
4019 }
4020 priv->nr = i;
4021 return priv;
4022
4023 err_deinit:
4024 if (quirk->exit)
4025 quirk->exit(dev);
4026 err_out:
4027 return priv;
4028 }
4029 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4030
4031 void pciserial_remove_ports(struct serial_private *priv)
4032 {
4033 struct pci_serial_quirk *quirk;
4034 int i;
4035
4036 for (i = 0; i < priv->nr; i++)
4037 serial8250_unregister_port(priv->line[i]);
4038
4039 /*
4040 * Find the exit quirks.
4041 */
4042 quirk = find_quirk(priv->dev);
4043 if (quirk->exit)
4044 quirk->exit(priv->dev);
4045
4046 kfree(priv);
4047 }
4048 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4049
4050 void pciserial_suspend_ports(struct serial_private *priv)
4051 {
4052 int i;
4053
4054 for (i = 0; i < priv->nr; i++)
4055 if (priv->line[i] >= 0)
4056 serial8250_suspend_port(priv->line[i]);
4057
4058 /*
4059 * Ensure that every init quirk is properly torn down
4060 */
4061 if (priv->quirk->exit)
4062 priv->quirk->exit(priv->dev);
4063 }
4064 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4065
4066 void pciserial_resume_ports(struct serial_private *priv)
4067 {
4068 int i;
4069
4070 /*
4071 * Ensure that the board is correctly configured.
4072 */
4073 if (priv->quirk->init)
4074 priv->quirk->init(priv->dev);
4075
4076 for (i = 0; i < priv->nr; i++)
4077 if (priv->line[i] >= 0)
4078 serial8250_resume_port(priv->line[i]);
4079 }
4080 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4081
4082 /*
4083 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4084 * to the arrangement of serial ports on a PCI card.
4085 */
4086 static int
4087 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4088 {
4089 struct pci_serial_quirk *quirk;
4090 struct serial_private *priv;
4091 const struct pciserial_board *board;
4092 struct pciserial_board tmp;
4093 int rc;
4094
4095 quirk = find_quirk(dev);
4096 if (quirk->probe) {
4097 rc = quirk->probe(dev);
4098 if (rc)
4099 return rc;
4100 }
4101
4102 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4103 dev_err(&dev->dev, "invalid driver_data: %ld\n",
4104 ent->driver_data);
4105 return -EINVAL;
4106 }
4107
4108 board = &pci_boards[ent->driver_data];
4109
4110 rc = pcim_enable_device(dev);
4111 pci_save_state(dev);
4112 if (rc)
4113 return rc;
4114
4115 if (ent->driver_data == pbn_default) {
4116 /*
4117 * Use a copy of the pci_board entry for this;
4118 * avoid changing entries in the table.
4119 */
4120 memcpy(&tmp, board, sizeof(struct pciserial_board));
4121 board = &tmp;
4122
4123 /*
4124 * We matched one of our class entries. Try to
4125 * determine the parameters of this board.
4126 */
4127 rc = serial_pci_guess_board(dev, &tmp);
4128 if (rc)
4129 return rc;
4130 } else {
4131 /*
4132 * We matched an explicit entry. If we are able to
4133 * detect this boards settings with our heuristic,
4134 * then we no longer need this entry.
4135 */
4136 memcpy(&tmp, &pci_boards[pbn_default],
4137 sizeof(struct pciserial_board));
4138 rc = serial_pci_guess_board(dev, &tmp);
4139 if (rc == 0 && serial_pci_matches(board, &tmp))
4140 moan_device("Redundant entry in serial pci_table.",
4141 dev);
4142 }
4143
4144 priv = pciserial_init_ports(dev, board);
4145 if (IS_ERR(priv))
4146 return PTR_ERR(priv);
4147
4148 pci_set_drvdata(dev, priv);
4149 return 0;
4150 }
4151
4152 static void pciserial_remove_one(struct pci_dev *dev)
4153 {
4154 struct serial_private *priv = pci_get_drvdata(dev);
4155
4156 pciserial_remove_ports(priv);
4157 }
4158
4159 #ifdef CONFIG_PM_SLEEP
4160 static int pciserial_suspend_one(struct device *dev)
4161 {
4162 struct pci_dev *pdev = to_pci_dev(dev);
4163 struct serial_private *priv = pci_get_drvdata(pdev);
4164
4165 if (priv)
4166 pciserial_suspend_ports(priv);
4167
4168 return 0;
4169 }
4170
4171 static int pciserial_resume_one(struct device *dev)
4172 {
4173 struct pci_dev *pdev = to_pci_dev(dev);
4174 struct serial_private *priv = pci_get_drvdata(pdev);
4175 int err;
4176
4177 if (priv) {
4178 /*
4179 * The device may have been disabled. Re-enable it.
4180 */
4181 err = pci_enable_device(pdev);
4182 /* FIXME: We cannot simply error out here */
4183 if (err)
4184 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4185 pciserial_resume_ports(priv);
4186 }
4187 return 0;
4188 }
4189 #endif
4190
4191 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4192 pciserial_resume_one);
4193
4194 static struct pci_device_id serial_pci_tbl[] = {
4195 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4196 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4197 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4198 pbn_b2_8_921600 },
4199 /* Advantech also use 0x3618 and 0xf618 */
4200 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4201 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4202 pbn_b0_4_921600 },
4203 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4204 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4205 pbn_b0_4_921600 },
4206 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4207 PCI_SUBVENDOR_ID_CONNECT_TECH,
4208 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4209 pbn_b1_8_1382400 },
4210 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4211 PCI_SUBVENDOR_ID_CONNECT_TECH,
4212 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4213 pbn_b1_4_1382400 },
4214 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4215 PCI_SUBVENDOR_ID_CONNECT_TECH,
4216 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4217 pbn_b1_2_1382400 },
4218 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4219 PCI_SUBVENDOR_ID_CONNECT_TECH,
4220 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4221 pbn_b1_8_1382400 },
4222 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4223 PCI_SUBVENDOR_ID_CONNECT_TECH,
4224 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4225 pbn_b1_4_1382400 },
4226 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4227 PCI_SUBVENDOR_ID_CONNECT_TECH,
4228 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4229 pbn_b1_2_1382400 },
4230 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4231 PCI_SUBVENDOR_ID_CONNECT_TECH,
4232 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4233 pbn_b1_8_921600 },
4234 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4235 PCI_SUBVENDOR_ID_CONNECT_TECH,
4236 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4237 pbn_b1_8_921600 },
4238 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4239 PCI_SUBVENDOR_ID_CONNECT_TECH,
4240 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4241 pbn_b1_4_921600 },
4242 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4243 PCI_SUBVENDOR_ID_CONNECT_TECH,
4244 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4245 pbn_b1_4_921600 },
4246 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4247 PCI_SUBVENDOR_ID_CONNECT_TECH,
4248 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4249 pbn_b1_2_921600 },
4250 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4251 PCI_SUBVENDOR_ID_CONNECT_TECH,
4252 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4253 pbn_b1_8_921600 },
4254 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4255 PCI_SUBVENDOR_ID_CONNECT_TECH,
4256 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4257 pbn_b1_8_921600 },
4258 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4259 PCI_SUBVENDOR_ID_CONNECT_TECH,
4260 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4261 pbn_b1_4_921600 },
4262 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4263 PCI_SUBVENDOR_ID_CONNECT_TECH,
4264 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4265 pbn_b1_2_1250000 },
4266 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4267 PCI_SUBVENDOR_ID_CONNECT_TECH,
4268 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4269 pbn_b0_2_1843200 },
4270 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4271 PCI_SUBVENDOR_ID_CONNECT_TECH,
4272 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4273 pbn_b0_4_1843200 },
4274 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4275 PCI_VENDOR_ID_AFAVLAB,
4276 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4277 pbn_b0_4_1152000 },
4278 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4279 PCI_SUBVENDOR_ID_CONNECT_TECH,
4280 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4281 pbn_b0_2_1843200_200 },
4282 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4283 PCI_SUBVENDOR_ID_CONNECT_TECH,
4284 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4285 pbn_b0_4_1843200_200 },
4286 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4287 PCI_SUBVENDOR_ID_CONNECT_TECH,
4288 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4289 pbn_b0_8_1843200_200 },
4290 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4291 PCI_SUBVENDOR_ID_CONNECT_TECH,
4292 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4293 pbn_b0_2_1843200_200 },
4294 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4295 PCI_SUBVENDOR_ID_CONNECT_TECH,
4296 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4297 pbn_b0_4_1843200_200 },
4298 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4299 PCI_SUBVENDOR_ID_CONNECT_TECH,
4300 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4301 pbn_b0_8_1843200_200 },
4302 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4303 PCI_SUBVENDOR_ID_CONNECT_TECH,
4304 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4305 pbn_b0_2_1843200_200 },
4306 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4307 PCI_SUBVENDOR_ID_CONNECT_TECH,
4308 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4309 pbn_b0_4_1843200_200 },
4310 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4311 PCI_SUBVENDOR_ID_CONNECT_TECH,
4312 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4313 pbn_b0_8_1843200_200 },
4314 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4315 PCI_SUBVENDOR_ID_CONNECT_TECH,
4316 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4317 pbn_b0_2_1843200_200 },
4318 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4319 PCI_SUBVENDOR_ID_CONNECT_TECH,
4320 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4321 pbn_b0_4_1843200_200 },
4322 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4323 PCI_SUBVENDOR_ID_CONNECT_TECH,
4324 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4325 pbn_b0_8_1843200_200 },
4326 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4327 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4328 0, 0, pbn_exar_ibm_saturn },
4329
4330 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4331 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4332 pbn_b2_bt_1_115200 },
4333 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4334 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4335 pbn_b2_bt_2_115200 },
4336 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4337 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4338 pbn_b2_bt_4_115200 },
4339 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4340 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4341 pbn_b2_bt_2_115200 },
4342 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4343 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4344 pbn_b2_bt_4_115200 },
4345 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4346 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4347 pbn_b2_8_115200 },
4348 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4349 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4350 pbn_b2_8_460800 },
4351 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4352 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4353 pbn_b2_8_115200 },
4354
4355 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4356 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4357 pbn_b2_bt_2_115200 },
4358 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4359 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4360 pbn_b2_bt_2_921600 },
4361 /*
4362 * VScom SPCOM800, from sl@s.pl
4363 */
4364 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4365 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4366 pbn_b2_8_921600 },
4367 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4368 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4369 pbn_b2_4_921600 },
4370 /* Unknown card - subdevice 0x1584 */
4371 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4372 PCI_VENDOR_ID_PLX,
4373 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4374 pbn_b2_4_115200 },
4375 /* Unknown card - subdevice 0x1588 */
4376 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4377 PCI_VENDOR_ID_PLX,
4378 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4379 pbn_b2_8_115200 },
4380 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4381 PCI_SUBVENDOR_ID_KEYSPAN,
4382 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4383 pbn_panacom },
4384 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4385 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4386 pbn_panacom4 },
4387 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4388 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4389 pbn_panacom2 },
4390 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4391 PCI_VENDOR_ID_ESDGMBH,
4392 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4393 pbn_b2_4_115200 },
4394 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4395 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4396 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4397 pbn_b2_4_460800 },
4398 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4399 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4400 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4401 pbn_b2_8_460800 },
4402 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4403 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4404 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4405 pbn_b2_16_460800 },
4406 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4407 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4408 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4409 pbn_b2_16_460800 },
4410 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4411 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4412 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4413 pbn_b2_4_460800 },
4414 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4415 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4416 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4417 pbn_b2_8_460800 },
4418 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4419 PCI_SUBVENDOR_ID_EXSYS,
4420 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4421 pbn_b2_4_115200 },
4422 /*
4423 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4424 * (Exoray@isys.ca)
4425 */
4426 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4427 0x10b5, 0x106a, 0, 0,
4428 pbn_plx_romulus },
4429 /*
4430 * EndRun Technologies. PCI express device range.
4431 * EndRun PTP/1588 has 2 Native UARTs.
4432 */
4433 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4434 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4435 pbn_endrun_2_4000000 },
4436 /*
4437 * Quatech cards. These actually have configurable clocks but for
4438 * now we just use the default.
4439 *
4440 * 100 series are RS232, 200 series RS422,
4441 */
4442 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4444 pbn_b1_4_115200 },
4445 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4446 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4447 pbn_b1_2_115200 },
4448 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4449 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4450 pbn_b2_2_115200 },
4451 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4452 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4453 pbn_b1_2_115200 },
4454 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4455 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4456 pbn_b2_2_115200 },
4457 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4458 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4459 pbn_b1_4_115200 },
4460 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4461 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4462 pbn_b1_8_115200 },
4463 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4464 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4465 pbn_b1_8_115200 },
4466 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4467 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4468 pbn_b1_4_115200 },
4469 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4470 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4471 pbn_b1_2_115200 },
4472 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4473 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4474 pbn_b1_4_115200 },
4475 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4476 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4477 pbn_b1_2_115200 },
4478 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4479 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4480 pbn_b2_4_115200 },
4481 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4482 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4483 pbn_b2_2_115200 },
4484 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4485 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4486 pbn_b2_1_115200 },
4487 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4488 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4489 pbn_b2_4_115200 },
4490 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4491 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4492 pbn_b2_2_115200 },
4493 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4494 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4495 pbn_b2_1_115200 },
4496 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4497 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4498 pbn_b0_8_115200 },
4499
4500 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4501 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4502 0, 0,
4503 pbn_b0_4_921600 },
4504 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4505 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4506 0, 0,
4507 pbn_b0_4_1152000 },
4508 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4510 pbn_b0_bt_2_921600 },
4511
4512 /*
4513 * The below card is a little controversial since it is the
4514 * subject of a PCI vendor/device ID clash. (See
4515 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4516 * For now just used the hex ID 0x950a.
4517 */
4518 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4519 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4520 0, 0, pbn_b0_2_115200 },
4521 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4522 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4523 0, 0, pbn_b0_2_115200 },
4524 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4525 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4526 pbn_b0_2_1130000 },
4527 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4528 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4529 pbn_b0_1_921600 },
4530 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4531 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4532 pbn_b0_4_115200 },
4533 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4534 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4535 pbn_b0_bt_2_921600 },
4536 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4537 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4538 pbn_b2_8_1152000 },
4539
4540 /*
4541 * Oxford Semiconductor Inc. Tornado PCI express device range.
4542 */
4543 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4544 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4545 pbn_b0_1_4000000 },
4546 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4547 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4548 pbn_b0_1_4000000 },
4549 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4550 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4551 pbn_oxsemi_1_4000000 },
4552 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4553 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4554 pbn_oxsemi_1_4000000 },
4555 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4556 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4557 pbn_b0_1_4000000 },
4558 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4559 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4560 pbn_b0_1_4000000 },
4561 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4562 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4563 pbn_oxsemi_1_4000000 },
4564 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4565 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4566 pbn_oxsemi_1_4000000 },
4567 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4568 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4569 pbn_b0_1_4000000 },
4570 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4571 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4572 pbn_b0_1_4000000 },
4573 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4574 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4575 pbn_b0_1_4000000 },
4576 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4577 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4578 pbn_b0_1_4000000 },
4579 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4580 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4581 pbn_oxsemi_2_4000000 },
4582 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4583 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4584 pbn_oxsemi_2_4000000 },
4585 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4586 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4587 pbn_oxsemi_4_4000000 },
4588 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4589 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4590 pbn_oxsemi_4_4000000 },
4591 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593 pbn_oxsemi_8_4000000 },
4594 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596 pbn_oxsemi_8_4000000 },
4597 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599 pbn_oxsemi_1_4000000 },
4600 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602 pbn_oxsemi_1_4000000 },
4603 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 pbn_oxsemi_1_4000000 },
4606 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608 pbn_oxsemi_1_4000000 },
4609 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611 pbn_oxsemi_1_4000000 },
4612 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614 pbn_oxsemi_1_4000000 },
4615 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617 pbn_oxsemi_1_4000000 },
4618 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4619 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4620 pbn_oxsemi_1_4000000 },
4621 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623 pbn_oxsemi_1_4000000 },
4624 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4625 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4626 pbn_oxsemi_1_4000000 },
4627 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4628 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629 pbn_oxsemi_1_4000000 },
4630 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4631 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4632 pbn_oxsemi_1_4000000 },
4633 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4634 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4635 pbn_oxsemi_1_4000000 },
4636 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4637 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4638 pbn_oxsemi_1_4000000 },
4639 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4640 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4641 pbn_oxsemi_1_4000000 },
4642 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4643 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4644 pbn_oxsemi_1_4000000 },
4645 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4646 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4647 pbn_oxsemi_1_4000000 },
4648 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4649 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4650 pbn_oxsemi_1_4000000 },
4651 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4652 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4653 pbn_oxsemi_1_4000000 },
4654 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4655 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4656 pbn_oxsemi_1_4000000 },
4657 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4658 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4659 pbn_oxsemi_1_4000000 },
4660 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4661 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4662 pbn_oxsemi_1_4000000 },
4663 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4664 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4665 pbn_oxsemi_1_4000000 },
4666 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4667 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4668 pbn_oxsemi_1_4000000 },
4669 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4670 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4671 pbn_oxsemi_1_4000000 },
4672 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4673 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4674 pbn_oxsemi_1_4000000 },
4675 /*
4676 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4677 */
4678 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4679 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4680 pbn_oxsemi_1_4000000 },
4681 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4682 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4683 pbn_oxsemi_2_4000000 },
4684 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4685 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4686 pbn_oxsemi_4_4000000 },
4687 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4688 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4689 pbn_oxsemi_8_4000000 },
4690
4691 /*
4692 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4693 */
4694 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4695 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4696 pbn_oxsemi_2_4000000 },
4697
4698 /*
4699 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4700 * from skokodyn@yahoo.com
4701 */
4702 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4703 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4704 pbn_sbsxrsio },
4705 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4706 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4707 pbn_sbsxrsio },
4708 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4709 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4710 pbn_sbsxrsio },
4711 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4712 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4713 pbn_sbsxrsio },
4714
4715 /*
4716 * Digitan DS560-558, from jimd@esoft.com
4717 */
4718 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4719 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4720 pbn_b1_1_115200 },
4721
4722 /*
4723 * Titan Electronic cards
4724 * The 400L and 800L have a custom setup quirk.
4725 */
4726 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4727 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4728 pbn_b0_1_921600 },
4729 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4730 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4731 pbn_b0_2_921600 },
4732 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4733 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4734 pbn_b0_4_921600 },
4735 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4736 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4737 pbn_b0_4_921600 },
4738 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4739 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4740 pbn_b1_1_921600 },
4741 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4742 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4743 pbn_b1_bt_2_921600 },
4744 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4745 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4746 pbn_b0_bt_4_921600 },
4747 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4748 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4749 pbn_b0_bt_8_921600 },
4750 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4751 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4752 pbn_b4_bt_2_921600 },
4753 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4754 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4755 pbn_b4_bt_4_921600 },
4756 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4757 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4758 pbn_b4_bt_8_921600 },
4759 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4760 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4761 pbn_b0_4_921600 },
4762 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4763 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4764 pbn_b0_4_921600 },
4765 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4766 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4767 pbn_b0_4_921600 },
4768 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4769 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4770 pbn_oxsemi_1_4000000 },
4771 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4772 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4773 pbn_oxsemi_2_4000000 },
4774 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4775 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4776 pbn_oxsemi_4_4000000 },
4777 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4778 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4779 pbn_oxsemi_8_4000000 },
4780 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4781 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4782 pbn_oxsemi_2_4000000 },
4783 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4784 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4785 pbn_oxsemi_2_4000000 },
4786 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4787 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4788 pbn_b0_bt_2_921600 },
4789 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4790 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4791 pbn_b0_4_921600 },
4792 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4793 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4794 pbn_b0_4_921600 },
4795 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4796 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4797 pbn_b0_4_921600 },
4798 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4799 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4800 pbn_b0_4_921600 },
4801
4802 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4803 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4804 pbn_b2_1_460800 },
4805 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4806 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4807 pbn_b2_1_460800 },
4808 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4809 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4810 pbn_b2_1_460800 },
4811 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4812 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4813 pbn_b2_bt_2_921600 },
4814 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4815 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4816 pbn_b2_bt_2_921600 },
4817 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4818 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4819 pbn_b2_bt_2_921600 },
4820 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4821 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4822 pbn_b2_bt_4_921600 },
4823 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4824 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4825 pbn_b2_bt_4_921600 },
4826 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4827 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4828 pbn_b2_bt_4_921600 },
4829 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4830 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4831 pbn_b0_1_921600 },
4832 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4833 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4834 pbn_b0_1_921600 },
4835 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4836 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4837 pbn_b0_1_921600 },
4838 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4839 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4840 pbn_b0_bt_2_921600 },
4841 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4842 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4843 pbn_b0_bt_2_921600 },
4844 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4845 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4846 pbn_b0_bt_2_921600 },
4847 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4848 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4849 pbn_b0_bt_4_921600 },
4850 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4851 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4852 pbn_b0_bt_4_921600 },
4853 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4854 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4855 pbn_b0_bt_4_921600 },
4856 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4857 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4858 pbn_b0_bt_8_921600 },
4859 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4860 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4861 pbn_b0_bt_8_921600 },
4862 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4863 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4864 pbn_b0_bt_8_921600 },
4865
4866 /*
4867 * Computone devices submitted by Doug McNash dmcnash@computone.com
4868 */
4869 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4870 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4871 0, 0, pbn_computone_4 },
4872 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4873 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4874 0, 0, pbn_computone_8 },
4875 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4876 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4877 0, 0, pbn_computone_6 },
4878
4879 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4880 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4881 pbn_oxsemi },
4882 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4883 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4884 pbn_b0_bt_1_921600 },
4885
4886 /*
4887 * SUNIX (TIMEDIA)
4888 */
4889 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4890 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4891 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4892 pbn_b0_bt_1_921600 },
4893
4894 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4895 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4896 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4897 pbn_b0_bt_1_921600 },
4898
4899 /*
4900 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4901 */
4902 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4904 pbn_b0_bt_8_115200 },
4905 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4906 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4907 pbn_b0_bt_8_115200 },
4908
4909 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4910 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4911 pbn_b0_bt_2_115200 },
4912 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4913 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4914 pbn_b0_bt_2_115200 },
4915 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4916 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4917 pbn_b0_bt_2_115200 },
4918 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4919 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4920 pbn_b0_bt_2_115200 },
4921 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4922 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4923 pbn_b0_bt_2_115200 },
4924 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4925 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4926 pbn_b0_bt_4_460800 },
4927 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4928 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4929 pbn_b0_bt_4_460800 },
4930 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4931 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4932 pbn_b0_bt_2_460800 },
4933 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4934 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4935 pbn_b0_bt_2_460800 },
4936 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4937 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4938 pbn_b0_bt_2_460800 },
4939 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4940 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4941 pbn_b0_bt_1_115200 },
4942 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4944 pbn_b0_bt_1_460800 },
4945
4946 /*
4947 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4948 * Cards are identified by their subsystem vendor IDs, which
4949 * (in hex) match the model number.
4950 *
4951 * Note that JC140x are RS422/485 cards which require ox950
4952 * ACR = 0x10, and as such are not currently fully supported.
4953 */
4954 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4955 0x1204, 0x0004, 0, 0,
4956 pbn_b0_4_921600 },
4957 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4958 0x1208, 0x0004, 0, 0,
4959 pbn_b0_4_921600 },
4960 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4961 0x1402, 0x0002, 0, 0,
4962 pbn_b0_2_921600 }, */
4963 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4964 0x1404, 0x0004, 0, 0,
4965 pbn_b0_4_921600 }, */
4966 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4967 0x1208, 0x0004, 0, 0,
4968 pbn_b0_4_921600 },
4969
4970 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4971 0x1204, 0x0004, 0, 0,
4972 pbn_b0_4_921600 },
4973 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4974 0x1208, 0x0004, 0, 0,
4975 pbn_b0_4_921600 },
4976 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4977 0x1208, 0x0004, 0, 0,
4978 pbn_b0_4_921600 },
4979 /*
4980 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4981 */
4982 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4983 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4984 pbn_b1_1_1382400 },
4985
4986 /*
4987 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4988 */
4989 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4990 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4991 pbn_b1_1_1382400 },
4992
4993 /*
4994 * RAStel 2 port modem, gerg@moreton.com.au
4995 */
4996 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4997 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4998 pbn_b2_bt_2_115200 },
4999
5000 /*
5001 * EKF addition for i960 Boards form EKF with serial port
5002 */
5003 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5004 0xE4BF, PCI_ANY_ID, 0, 0,
5005 pbn_intel_i960 },
5006
5007 /*
5008 * Xircom Cardbus/Ethernet combos
5009 */
5010 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5011 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5012 pbn_b0_1_115200 },
5013 /*
5014 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5015 */
5016 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5017 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5018 pbn_b0_1_115200 },
5019
5020 /*
5021 * Untested PCI modems, sent in from various folks...
5022 */
5023
5024 /*
5025 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5026 */
5027 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5028 0x1048, 0x1500, 0, 0,
5029 pbn_b1_1_115200 },
5030
5031 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5032 0xFF00, 0, 0, 0,
5033 pbn_sgi_ioc3 },
5034
5035 /*
5036 * HP Diva card
5037 */
5038 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5039 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5040 pbn_b1_1_115200 },
5041 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5042 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5043 pbn_b0_5_115200 },
5044 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5045 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5046 pbn_b2_1_115200 },
5047
5048 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5049 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5050 pbn_b3_2_115200 },
5051 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5052 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5053 pbn_b3_4_115200 },
5054 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5055 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5056 pbn_b3_8_115200 },
5057
5058 /*
5059 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
5060 */
5061 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
5062 PCI_ANY_ID, PCI_ANY_ID,
5063 0,
5064 0, pbn_exar_XR17C152 },
5065 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
5066 PCI_ANY_ID, PCI_ANY_ID,
5067 0,
5068 0, pbn_exar_XR17C154 },
5069 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
5070 PCI_ANY_ID, PCI_ANY_ID,
5071 0,
5072 0, pbn_exar_XR17C158 },
5073 /*
5074 * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
5075 */
5076 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
5077 PCI_ANY_ID, PCI_ANY_ID,
5078 0,
5079 0, pbn_exar_XR17V352 },
5080 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
5081 PCI_ANY_ID, PCI_ANY_ID,
5082 0,
5083 0, pbn_exar_XR17V354 },
5084 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
5085 PCI_ANY_ID, PCI_ANY_ID,
5086 0,
5087 0, pbn_exar_XR17V358 },
5088 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358,
5089 PCI_ANY_ID, PCI_ANY_ID,
5090 0,
5091 0, pbn_exar_XR17V4358 },
5092 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
5093 PCI_ANY_ID, PCI_ANY_ID,
5094 0,
5095 0, pbn_exar_XR17V8358 },
5096 /*
5097 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
5098 */
5099 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
5100 PCI_ANY_ID, PCI_ANY_ID,
5101 0,
5102 0, pbn_pericom_PI7C9X7951 },
5103 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
5104 PCI_ANY_ID, PCI_ANY_ID,
5105 0,
5106 0, pbn_pericom_PI7C9X7952 },
5107 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
5108 PCI_ANY_ID, PCI_ANY_ID,
5109 0,
5110 0, pbn_pericom_PI7C9X7954 },
5111 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
5112 PCI_ANY_ID, PCI_ANY_ID,
5113 0,
5114 0, pbn_pericom_PI7C9X7958 },
5115 /*
5116 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5117 */
5118 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5119 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5120 pbn_b0_1_115200 },
5121 /*
5122 * ITE
5123 */
5124 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5125 PCI_ANY_ID, PCI_ANY_ID,
5126 0, 0,
5127 pbn_b1_bt_1_115200 },
5128
5129 /*
5130 * IntaShield IS-200
5131 */
5132 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
5134 pbn_b2_2_115200 },
5135 /*
5136 * IntaShield IS-400
5137 */
5138 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5140 pbn_b2_4_115200 },
5141 /*
5142 * Perle PCI-RAS cards
5143 */
5144 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5145 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5146 0, 0, pbn_b2_4_921600 },
5147 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5148 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5149 0, 0, pbn_b2_8_921600 },
5150
5151 /*
5152 * Mainpine series cards: Fairly standard layout but fools
5153 * parts of the autodetect in some cases and uses otherwise
5154 * unmatched communications subclasses in the PCI Express case
5155 */
5156
5157 { /* RockForceDUO */
5158 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5159 PCI_VENDOR_ID_MAINPINE, 0x0200,
5160 0, 0, pbn_b0_2_115200 },
5161 { /* RockForceQUATRO */
5162 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5163 PCI_VENDOR_ID_MAINPINE, 0x0300,
5164 0, 0, pbn_b0_4_115200 },
5165 { /* RockForceDUO+ */
5166 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5167 PCI_VENDOR_ID_MAINPINE, 0x0400,
5168 0, 0, pbn_b0_2_115200 },
5169 { /* RockForceQUATRO+ */
5170 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5171 PCI_VENDOR_ID_MAINPINE, 0x0500,
5172 0, 0, pbn_b0_4_115200 },
5173 { /* RockForce+ */
5174 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5175 PCI_VENDOR_ID_MAINPINE, 0x0600,
5176 0, 0, pbn_b0_2_115200 },
5177 { /* RockForce+ */
5178 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5179 PCI_VENDOR_ID_MAINPINE, 0x0700,
5180 0, 0, pbn_b0_4_115200 },
5181 { /* RockForceOCTO+ */
5182 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5183 PCI_VENDOR_ID_MAINPINE, 0x0800,
5184 0, 0, pbn_b0_8_115200 },
5185 { /* RockForceDUO+ */
5186 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5187 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5188 0, 0, pbn_b0_2_115200 },
5189 { /* RockForceQUARTRO+ */
5190 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5191 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5192 0, 0, pbn_b0_4_115200 },
5193 { /* RockForceOCTO+ */
5194 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5195 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5196 0, 0, pbn_b0_8_115200 },
5197 { /* RockForceD1 */
5198 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5199 PCI_VENDOR_ID_MAINPINE, 0x2000,
5200 0, 0, pbn_b0_1_115200 },
5201 { /* RockForceF1 */
5202 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5203 PCI_VENDOR_ID_MAINPINE, 0x2100,
5204 0, 0, pbn_b0_1_115200 },
5205 { /* RockForceD2 */
5206 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5207 PCI_VENDOR_ID_MAINPINE, 0x2200,
5208 0, 0, pbn_b0_2_115200 },
5209 { /* RockForceF2 */
5210 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5211 PCI_VENDOR_ID_MAINPINE, 0x2300,
5212 0, 0, pbn_b0_2_115200 },
5213 { /* RockForceD4 */
5214 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5215 PCI_VENDOR_ID_MAINPINE, 0x2400,
5216 0, 0, pbn_b0_4_115200 },
5217 { /* RockForceF4 */
5218 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5219 PCI_VENDOR_ID_MAINPINE, 0x2500,
5220 0, 0, pbn_b0_4_115200 },
5221 { /* RockForceD8 */
5222 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5223 PCI_VENDOR_ID_MAINPINE, 0x2600,
5224 0, 0, pbn_b0_8_115200 },
5225 { /* RockForceF8 */
5226 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5227 PCI_VENDOR_ID_MAINPINE, 0x2700,
5228 0, 0, pbn_b0_8_115200 },
5229 { /* IQ Express D1 */
5230 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5231 PCI_VENDOR_ID_MAINPINE, 0x3000,
5232 0, 0, pbn_b0_1_115200 },
5233 { /* IQ Express F1 */
5234 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5235 PCI_VENDOR_ID_MAINPINE, 0x3100,
5236 0, 0, pbn_b0_1_115200 },
5237 { /* IQ Express D2 */
5238 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5239 PCI_VENDOR_ID_MAINPINE, 0x3200,
5240 0, 0, pbn_b0_2_115200 },
5241 { /* IQ Express F2 */
5242 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5243 PCI_VENDOR_ID_MAINPINE, 0x3300,
5244 0, 0, pbn_b0_2_115200 },
5245 { /* IQ Express D4 */
5246 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5247 PCI_VENDOR_ID_MAINPINE, 0x3400,
5248 0, 0, pbn_b0_4_115200 },
5249 { /* IQ Express F4 */
5250 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5251 PCI_VENDOR_ID_MAINPINE, 0x3500,
5252 0, 0, pbn_b0_4_115200 },
5253 { /* IQ Express D8 */
5254 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5255 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5256 0, 0, pbn_b0_8_115200 },
5257 { /* IQ Express F8 */
5258 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5259 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5260 0, 0, pbn_b0_8_115200 },
5261
5262
5263 /*
5264 * PA Semi PA6T-1682M on-chip UART
5265 */
5266 { PCI_VENDOR_ID_PASEMI, 0xa004,
5267 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5268 pbn_pasemi_1682M },
5269
5270 /*
5271 * National Instruments
5272 */
5273 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5274 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5275 pbn_b1_16_115200 },
5276 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5278 pbn_b1_8_115200 },
5279 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5280 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5281 pbn_b1_bt_4_115200 },
5282 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5283 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5284 pbn_b1_bt_2_115200 },
5285 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5286 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5287 pbn_b1_bt_4_115200 },
5288 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5289 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5290 pbn_b1_bt_2_115200 },
5291 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5292 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5293 pbn_b1_16_115200 },
5294 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5295 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5296 pbn_b1_8_115200 },
5297 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5298 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5299 pbn_b1_bt_4_115200 },
5300 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5301 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5302 pbn_b1_bt_2_115200 },
5303 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5304 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5305 pbn_b1_bt_4_115200 },
5306 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5307 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5308 pbn_b1_bt_2_115200 },
5309 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5310 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5311 pbn_ni8430_2 },
5312 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5313 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5314 pbn_ni8430_2 },
5315 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5316 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5317 pbn_ni8430_4 },
5318 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5319 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5320 pbn_ni8430_4 },
5321 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5322 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5323 pbn_ni8430_8 },
5324 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5325 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5326 pbn_ni8430_8 },
5327 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5328 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5329 pbn_ni8430_16 },
5330 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5331 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5332 pbn_ni8430_16 },
5333 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5334 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5335 pbn_ni8430_2 },
5336 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5337 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5338 pbn_ni8430_2 },
5339 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5340 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5341 pbn_ni8430_4 },
5342 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5343 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5344 pbn_ni8430_4 },
5345
5346 /*
5347 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5348 */
5349 { PCI_VENDOR_ID_ADDIDATA,
5350 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5351 PCI_ANY_ID,
5352 PCI_ANY_ID,
5353 0,
5354 0,
5355 pbn_b0_4_115200 },
5356
5357 { PCI_VENDOR_ID_ADDIDATA,
5358 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5359 PCI_ANY_ID,
5360 PCI_ANY_ID,
5361 0,
5362 0,
5363 pbn_b0_2_115200 },
5364
5365 { PCI_VENDOR_ID_ADDIDATA,
5366 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5367 PCI_ANY_ID,
5368 PCI_ANY_ID,
5369 0,
5370 0,
5371 pbn_b0_1_115200 },
5372
5373 { PCI_VENDOR_ID_AMCC,
5374 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5375 PCI_ANY_ID,
5376 PCI_ANY_ID,
5377 0,
5378 0,
5379 pbn_b1_8_115200 },
5380
5381 { PCI_VENDOR_ID_ADDIDATA,
5382 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5383 PCI_ANY_ID,
5384 PCI_ANY_ID,
5385 0,
5386 0,
5387 pbn_b0_4_115200 },
5388
5389 { PCI_VENDOR_ID_ADDIDATA,
5390 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5391 PCI_ANY_ID,
5392 PCI_ANY_ID,
5393 0,
5394 0,
5395 pbn_b0_2_115200 },
5396
5397 { PCI_VENDOR_ID_ADDIDATA,
5398 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5399 PCI_ANY_ID,
5400 PCI_ANY_ID,
5401 0,
5402 0,
5403 pbn_b0_1_115200 },
5404
5405 { PCI_VENDOR_ID_ADDIDATA,
5406 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5407 PCI_ANY_ID,
5408 PCI_ANY_ID,
5409 0,
5410 0,
5411 pbn_b0_4_115200 },
5412
5413 { PCI_VENDOR_ID_ADDIDATA,
5414 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5415 PCI_ANY_ID,
5416 PCI_ANY_ID,
5417 0,
5418 0,
5419 pbn_b0_2_115200 },
5420
5421 { PCI_VENDOR_ID_ADDIDATA,
5422 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5423 PCI_ANY_ID,
5424 PCI_ANY_ID,
5425 0,
5426 0,
5427 pbn_b0_1_115200 },
5428
5429 { PCI_VENDOR_ID_ADDIDATA,
5430 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5431 PCI_ANY_ID,
5432 PCI_ANY_ID,
5433 0,
5434 0,
5435 pbn_b0_8_115200 },
5436
5437 { PCI_VENDOR_ID_ADDIDATA,
5438 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5439 PCI_ANY_ID,
5440 PCI_ANY_ID,
5441 0,
5442 0,
5443 pbn_ADDIDATA_PCIe_4_3906250 },
5444
5445 { PCI_VENDOR_ID_ADDIDATA,
5446 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5447 PCI_ANY_ID,
5448 PCI_ANY_ID,
5449 0,
5450 0,
5451 pbn_ADDIDATA_PCIe_2_3906250 },
5452
5453 { PCI_VENDOR_ID_ADDIDATA,
5454 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5455 PCI_ANY_ID,
5456 PCI_ANY_ID,
5457 0,
5458 0,
5459 pbn_ADDIDATA_PCIe_1_3906250 },
5460
5461 { PCI_VENDOR_ID_ADDIDATA,
5462 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5463 PCI_ANY_ID,
5464 PCI_ANY_ID,
5465 0,
5466 0,
5467 pbn_ADDIDATA_PCIe_8_3906250 },
5468
5469 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5470 PCI_VENDOR_ID_IBM, 0x0299,
5471 0, 0, pbn_b0_bt_2_115200 },
5472
5473 /*
5474 * other NetMos 9835 devices are most likely handled by the
5475 * parport_serial driver, check drivers/parport/parport_serial.c
5476 * before adding them here.
5477 */
5478
5479 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5480 0xA000, 0x1000,
5481 0, 0, pbn_b0_1_115200 },
5482
5483 /* the 9901 is a rebranded 9912 */
5484 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5485 0xA000, 0x1000,
5486 0, 0, pbn_b0_1_115200 },
5487
5488 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5489 0xA000, 0x1000,
5490 0, 0, pbn_b0_1_115200 },
5491
5492 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5493 0xA000, 0x1000,
5494 0, 0, pbn_b0_1_115200 },
5495
5496 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5497 0xA000, 0x1000,
5498 0, 0, pbn_b0_1_115200 },
5499
5500 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5501 0xA000, 0x3002,
5502 0, 0, pbn_NETMOS9900_2s_115200 },
5503
5504 /*
5505 * Best Connectivity and Rosewill PCI Multi I/O cards
5506 */
5507
5508 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5509 0xA000, 0x1000,
5510 0, 0, pbn_b0_1_115200 },
5511
5512 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5513 0xA000, 0x3002,
5514 0, 0, pbn_b0_bt_2_115200 },
5515
5516 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5517 0xA000, 0x3004,
5518 0, 0, pbn_b0_bt_4_115200 },
5519 /* Intel CE4100 */
5520 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5521 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5522 pbn_ce4100_1_115200 },
5523 /* Intel BayTrail */
5524 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5525 PCI_ANY_ID, PCI_ANY_ID,
5526 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5527 pbn_byt },
5528 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5529 PCI_ANY_ID, PCI_ANY_ID,
5530 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5531 pbn_byt },
5532 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5533 PCI_ANY_ID, PCI_ANY_ID,
5534 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5535 pbn_byt },
5536 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5537 PCI_ANY_ID, PCI_ANY_ID,
5538 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5539 pbn_byt },
5540
5541 /* Intel Broadwell */
5542 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART1,
5543 PCI_ANY_ID, PCI_ANY_ID,
5544 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5545 pbn_byt },
5546 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART2,
5547 PCI_ANY_ID, PCI_ANY_ID,
5548 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5549 pbn_byt },
5550
5551 /*
5552 * Intel Quark x1000
5553 */
5554 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5555 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5556 pbn_qrk },
5557 /*
5558 * Cronyx Omega PCI
5559 */
5560 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5561 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5562 pbn_omegapci },
5563
5564 /*
5565 * Broadcom TruManage
5566 */
5567 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5568 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5569 pbn_brcm_trumanage },
5570
5571 /*
5572 * AgeStar as-prs2-009
5573 */
5574 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5575 PCI_ANY_ID, PCI_ANY_ID,
5576 0, 0, pbn_b0_bt_2_115200 },
5577
5578 /*
5579 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5580 * so not listed here.
5581 */
5582 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5583 PCI_ANY_ID, PCI_ANY_ID,
5584 0, 0, pbn_b0_bt_4_115200 },
5585
5586 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5587 PCI_ANY_ID, PCI_ANY_ID,
5588 0, 0, pbn_b0_bt_2_115200 },
5589
5590 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5591 PCI_ANY_ID, PCI_ANY_ID,
5592 0, 0, pbn_b0_bt_4_115200 },
5593
5594 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5595 PCI_ANY_ID, PCI_ANY_ID,
5596 0, 0, pbn_wch382_2 },
5597
5598 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5599 PCI_ANY_ID, PCI_ANY_ID,
5600 0, 0, pbn_wch384_4 },
5601
5602 /*
5603 * Commtech, Inc. Fastcom adapters
5604 */
5605 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5606 PCI_ANY_ID, PCI_ANY_ID,
5607 0,
5608 0, pbn_b0_2_1152000_200 },
5609 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5610 PCI_ANY_ID, PCI_ANY_ID,
5611 0,
5612 0, pbn_b0_4_1152000_200 },
5613 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5614 PCI_ANY_ID, PCI_ANY_ID,
5615 0,
5616 0, pbn_b0_4_1152000_200 },
5617 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5618 PCI_ANY_ID, PCI_ANY_ID,
5619 0,
5620 0, pbn_b0_8_1152000_200 },
5621 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5622 PCI_ANY_ID, PCI_ANY_ID,
5623 0,
5624 0, pbn_exar_XR17V352 },
5625 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5626 PCI_ANY_ID, PCI_ANY_ID,
5627 0,
5628 0, pbn_exar_XR17V354 },
5629 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5630 PCI_ANY_ID, PCI_ANY_ID,
5631 0,
5632 0, pbn_exar_XR17V358 },
5633
5634 /* Fintek PCI serial cards */
5635 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5636 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5637 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5638
5639 /*
5640 * These entries match devices with class COMMUNICATION_SERIAL,
5641 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5642 */
5643 { PCI_ANY_ID, PCI_ANY_ID,
5644 PCI_ANY_ID, PCI_ANY_ID,
5645 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5646 0xffff00, pbn_default },
5647 { PCI_ANY_ID, PCI_ANY_ID,
5648 PCI_ANY_ID, PCI_ANY_ID,
5649 PCI_CLASS_COMMUNICATION_MODEM << 8,
5650 0xffff00, pbn_default },
5651 { PCI_ANY_ID, PCI_ANY_ID,
5652 PCI_ANY_ID, PCI_ANY_ID,
5653 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5654 0xffff00, pbn_default },
5655 { 0, }
5656 };
5657
5658 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5659 pci_channel_state_t state)
5660 {
5661 struct serial_private *priv = pci_get_drvdata(dev);
5662
5663 if (state == pci_channel_io_perm_failure)
5664 return PCI_ERS_RESULT_DISCONNECT;
5665
5666 if (priv)
5667 pciserial_suspend_ports(priv);
5668
5669 pci_disable_device(dev);
5670
5671 return PCI_ERS_RESULT_NEED_RESET;
5672 }
5673
5674 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5675 {
5676 int rc;
5677
5678 rc = pci_enable_device(dev);
5679
5680 if (rc)
5681 return PCI_ERS_RESULT_DISCONNECT;
5682
5683 pci_restore_state(dev);
5684 pci_save_state(dev);
5685
5686 return PCI_ERS_RESULT_RECOVERED;
5687 }
5688
5689 static void serial8250_io_resume(struct pci_dev *dev)
5690 {
5691 struct serial_private *priv = pci_get_drvdata(dev);
5692
5693 if (priv)
5694 pciserial_resume_ports(priv);
5695 }
5696
5697 static const struct pci_error_handlers serial8250_err_handler = {
5698 .error_detected = serial8250_io_error_detected,
5699 .slot_reset = serial8250_io_slot_reset,
5700 .resume = serial8250_io_resume,
5701 };
5702
5703 static struct pci_driver serial_pci_driver = {
5704 .name = "serial",
5705 .probe = pciserial_init_one,
5706 .remove = pciserial_remove_one,
5707 .driver = {
5708 .pm = &pciserial_pm_ops,
5709 },
5710 .id_table = serial_pci_tbl,
5711 .err_handler = &serial8250_err_handler,
5712 };
5713
5714 module_pci_driver(serial_pci_driver);
5715
5716 MODULE_LICENSE("GPL");
5717 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5718 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
ubuntu-bionic-kernel mirror