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[mirror_ubuntu-jammy-kernel.git] / drivers / tty / serial / 8250 / 8250_pci.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type PCI serial ports.
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 */
9 #undef DEBUG
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/string.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/delay.h>
16 #include <linux/tty.h>
17 #include <linux/serial_reg.h>
18 #include <linux/serial_core.h>
19 #include <linux/8250_pci.h>
20 #include <linux/bitops.h>
21
22 #include <asm/byteorder.h>
23 #include <asm/io.h>
24
25 #include "8250.h"
26
27 /*
28 * init function returns:
29 * > 0 - number of ports
30 * = 0 - use board->num_ports
31 * < 0 - error
32 */
33 struct pci_serial_quirk {
34 u32 vendor;
35 u32 device;
36 u32 subvendor;
37 u32 subdevice;
38 int (*probe)(struct pci_dev *dev);
39 int (*init)(struct pci_dev *dev);
40 int (*setup)(struct serial_private *,
41 const struct pciserial_board *,
42 struct uart_8250_port *, int);
43 void (*exit)(struct pci_dev *dev);
44 };
45
46 struct f815xxa_data {
47 spinlock_t lock;
48 int idx;
49 };
50
51 struct serial_private {
52 struct pci_dev *dev;
53 unsigned int nr;
54 struct pci_serial_quirk *quirk;
55 const struct pciserial_board *board;
56 int line[];
57 };
58
59 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e
60
61 static const struct pci_device_id pci_use_msi[] = {
62 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
63 0xA000, 0x1000) },
64 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
65 0xA000, 0x1000) },
66 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
67 0xA000, 0x1000) },
68 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
69 PCI_ANY_ID, PCI_ANY_ID) },
70 { }
71 };
72
73 static int pci_default_setup(struct serial_private*,
74 const struct pciserial_board*, struct uart_8250_port *, int);
75
76 static void moan_device(const char *str, struct pci_dev *dev)
77 {
78 dev_err(&dev->dev,
79 "%s: %s\n"
80 "Please send the output of lspci -vv, this\n"
81 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
82 "manufacturer and name of serial board or\n"
83 "modem board to <linux-serial@vger.kernel.org>.\n",
84 pci_name(dev), str, dev->vendor, dev->device,
85 dev->subsystem_vendor, dev->subsystem_device);
86 }
87
88 static int
89 setup_port(struct serial_private *priv, struct uart_8250_port *port,
90 u8 bar, unsigned int offset, int regshift)
91 {
92 struct pci_dev *dev = priv->dev;
93
94 if (bar >= PCI_STD_NUM_BARS)
95 return -EINVAL;
96
97 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
98 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
99 return -ENOMEM;
100
101 port->port.iotype = UPIO_MEM;
102 port->port.iobase = 0;
103 port->port.mapbase = pci_resource_start(dev, bar) + offset;
104 port->port.membase = pcim_iomap_table(dev)[bar] + offset;
105 port->port.regshift = regshift;
106 } else {
107 port->port.iotype = UPIO_PORT;
108 port->port.iobase = pci_resource_start(dev, bar) + offset;
109 port->port.mapbase = 0;
110 port->port.membase = NULL;
111 port->port.regshift = 0;
112 }
113 return 0;
114 }
115
116 /*
117 * ADDI-DATA GmbH communication cards <info@addi-data.com>
118 */
119 static int addidata_apci7800_setup(struct serial_private *priv,
120 const struct pciserial_board *board,
121 struct uart_8250_port *port, int idx)
122 {
123 unsigned int bar = 0, offset = board->first_offset;
124 bar = FL_GET_BASE(board->flags);
125
126 if (idx < 2) {
127 offset += idx * board->uart_offset;
128 } else if ((idx >= 2) && (idx < 4)) {
129 bar += 1;
130 offset += ((idx - 2) * board->uart_offset);
131 } else if ((idx >= 4) && (idx < 6)) {
132 bar += 2;
133 offset += ((idx - 4) * board->uart_offset);
134 } else if (idx >= 6) {
135 bar += 3;
136 offset += ((idx - 6) * board->uart_offset);
137 }
138
139 return setup_port(priv, port, bar, offset, board->reg_shift);
140 }
141
142 /*
143 * AFAVLAB uses a different mixture of BARs and offsets
144 * Not that ugly ;) -- HW
145 */
146 static int
147 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
148 struct uart_8250_port *port, int idx)
149 {
150 unsigned int bar, offset = board->first_offset;
151
152 bar = FL_GET_BASE(board->flags);
153 if (idx < 4)
154 bar += idx;
155 else {
156 bar = 4;
157 offset += (idx - 4) * board->uart_offset;
158 }
159
160 return setup_port(priv, port, bar, offset, board->reg_shift);
161 }
162
163 /*
164 * HP's Remote Management Console. The Diva chip came in several
165 * different versions. N-class, L2000 and A500 have two Diva chips, each
166 * with 3 UARTs (the third UART on the second chip is unused). Superdome
167 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
168 * one Diva chip, but it has been expanded to 5 UARTs.
169 */
170 static int pci_hp_diva_init(struct pci_dev *dev)
171 {
172 int rc = 0;
173
174 switch (dev->subsystem_device) {
175 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
176 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
177 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
178 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
179 rc = 3;
180 break;
181 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
182 rc = 2;
183 break;
184 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
185 rc = 4;
186 break;
187 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
188 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
189 rc = 1;
190 break;
191 }
192
193 return rc;
194 }
195
196 /*
197 * HP's Diva chip puts the 4th/5th serial port further out, and
198 * some serial ports are supposed to be hidden on certain models.
199 */
200 static int
201 pci_hp_diva_setup(struct serial_private *priv,
202 const struct pciserial_board *board,
203 struct uart_8250_port *port, int idx)
204 {
205 unsigned int offset = board->first_offset;
206 unsigned int bar = FL_GET_BASE(board->flags);
207
208 switch (priv->dev->subsystem_device) {
209 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
210 if (idx == 3)
211 idx++;
212 break;
213 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
214 if (idx > 0)
215 idx++;
216 if (idx > 2)
217 idx++;
218 break;
219 }
220 if (idx > 2)
221 offset = 0x18;
222
223 offset += idx * board->uart_offset;
224
225 return setup_port(priv, port, bar, offset, board->reg_shift);
226 }
227
228 /*
229 * Added for EKF Intel i960 serial boards
230 */
231 static int pci_inteli960ni_init(struct pci_dev *dev)
232 {
233 u32 oldval;
234
235 if (!(dev->subsystem_device & 0x1000))
236 return -ENODEV;
237
238 /* is firmware started? */
239 pci_read_config_dword(dev, 0x44, &oldval);
240 if (oldval == 0x00001000L) { /* RESET value */
241 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
242 return -ENODEV;
243 }
244 return 0;
245 }
246
247 /*
248 * Some PCI serial cards using the PLX 9050 PCI interface chip require
249 * that the card interrupt be explicitly enabled or disabled. This
250 * seems to be mainly needed on card using the PLX which also use I/O
251 * mapped memory.
252 */
253 static int pci_plx9050_init(struct pci_dev *dev)
254 {
255 u8 irq_config;
256 void __iomem *p;
257
258 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
259 moan_device("no memory in bar 0", dev);
260 return 0;
261 }
262
263 irq_config = 0x41;
264 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
265 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
266 irq_config = 0x43;
267
268 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
269 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
270 /*
271 * As the megawolf cards have the int pins active
272 * high, and have 2 UART chips, both ints must be
273 * enabled on the 9050. Also, the UARTS are set in
274 * 16450 mode by default, so we have to enable the
275 * 16C950 'enhanced' mode so that we can use the
276 * deep FIFOs
277 */
278 irq_config = 0x5b;
279 /*
280 * enable/disable interrupts
281 */
282 p = ioremap(pci_resource_start(dev, 0), 0x80);
283 if (p == NULL)
284 return -ENOMEM;
285 writel(irq_config, p + 0x4c);
286
287 /*
288 * Read the register back to ensure that it took effect.
289 */
290 readl(p + 0x4c);
291 iounmap(p);
292
293 return 0;
294 }
295
296 static void pci_plx9050_exit(struct pci_dev *dev)
297 {
298 u8 __iomem *p;
299
300 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
301 return;
302
303 /*
304 * disable interrupts
305 */
306 p = ioremap(pci_resource_start(dev, 0), 0x80);
307 if (p != NULL) {
308 writel(0, p + 0x4c);
309
310 /*
311 * Read the register back to ensure that it took effect.
312 */
313 readl(p + 0x4c);
314 iounmap(p);
315 }
316 }
317
318 #define NI8420_INT_ENABLE_REG 0x38
319 #define NI8420_INT_ENABLE_BIT 0x2000
320
321 static void pci_ni8420_exit(struct pci_dev *dev)
322 {
323 void __iomem *p;
324 unsigned int bar = 0;
325
326 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
327 moan_device("no memory in bar", dev);
328 return;
329 }
330
331 p = pci_ioremap_bar(dev, bar);
332 if (p == NULL)
333 return;
334
335 /* Disable the CPU Interrupt */
336 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
337 p + NI8420_INT_ENABLE_REG);
338 iounmap(p);
339 }
340
341
342 /* MITE registers */
343 #define MITE_IOWBSR1 0xc4
344 #define MITE_IOWCR1 0xf4
345 #define MITE_LCIMR1 0x08
346 #define MITE_LCIMR2 0x10
347
348 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
349
350 static void pci_ni8430_exit(struct pci_dev *dev)
351 {
352 void __iomem *p;
353 unsigned int bar = 0;
354
355 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
356 moan_device("no memory in bar", dev);
357 return;
358 }
359
360 p = pci_ioremap_bar(dev, bar);
361 if (p == NULL)
362 return;
363
364 /* Disable the CPU Interrupt */
365 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
366 iounmap(p);
367 }
368
369 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
370 static int
371 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
372 struct uart_8250_port *port, int idx)
373 {
374 unsigned int bar, offset = board->first_offset;
375
376 bar = 0;
377
378 if (idx < 4) {
379 /* first four channels map to 0, 0x100, 0x200, 0x300 */
380 offset += idx * board->uart_offset;
381 } else if (idx < 8) {
382 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
383 offset += idx * board->uart_offset + 0xC00;
384 } else /* we have only 8 ports on PMC-OCTALPRO */
385 return 1;
386
387 return setup_port(priv, port, bar, offset, board->reg_shift);
388 }
389
390 /*
391 * This does initialization for PMC OCTALPRO cards:
392 * maps the device memory, resets the UARTs (needed, bc
393 * if the module is removed and inserted again, the card
394 * is in the sleep mode) and enables global interrupt.
395 */
396
397 /* global control register offset for SBS PMC-OctalPro */
398 #define OCT_REG_CR_OFF 0x500
399
400 static int sbs_init(struct pci_dev *dev)
401 {
402 u8 __iomem *p;
403
404 p = pci_ioremap_bar(dev, 0);
405
406 if (p == NULL)
407 return -ENOMEM;
408 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
409 writeb(0x10, p + OCT_REG_CR_OFF);
410 udelay(50);
411 writeb(0x0, p + OCT_REG_CR_OFF);
412
413 /* Set bit-2 (INTENABLE) of Control Register */
414 writeb(0x4, p + OCT_REG_CR_OFF);
415 iounmap(p);
416
417 return 0;
418 }
419
420 /*
421 * Disables the global interrupt of PMC-OctalPro
422 */
423
424 static void sbs_exit(struct pci_dev *dev)
425 {
426 u8 __iomem *p;
427
428 p = pci_ioremap_bar(dev, 0);
429 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
430 if (p != NULL)
431 writeb(0, p + OCT_REG_CR_OFF);
432 iounmap(p);
433 }
434
435 /*
436 * SIIG serial cards have an PCI interface chip which also controls
437 * the UART clocking frequency. Each UART can be clocked independently
438 * (except cards equipped with 4 UARTs) and initial clocking settings
439 * are stored in the EEPROM chip. It can cause problems because this
440 * version of serial driver doesn't support differently clocked UART's
441 * on single PCI card. To prevent this, initialization functions set
442 * high frequency clocking for all UART's on given card. It is safe (I
443 * hope) because it doesn't touch EEPROM settings to prevent conflicts
444 * with other OSes (like M$ DOS).
445 *
446 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
447 *
448 * There is two family of SIIG serial cards with different PCI
449 * interface chip and different configuration methods:
450 * - 10x cards have control registers in IO and/or memory space;
451 * - 20x cards have control registers in standard PCI configuration space.
452 *
453 * Note: all 10x cards have PCI device ids 0x10..
454 * all 20x cards have PCI device ids 0x20..
455 *
456 * There are also Quartet Serial cards which use Oxford Semiconductor
457 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
458 *
459 * Note: some SIIG cards are probed by the parport_serial object.
460 */
461
462 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
463 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
464
465 static int pci_siig10x_init(struct pci_dev *dev)
466 {
467 u16 data;
468 void __iomem *p;
469
470 switch (dev->device & 0xfff8) {
471 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
472 data = 0xffdf;
473 break;
474 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
475 data = 0xf7ff;
476 break;
477 default: /* 1S1P, 4S */
478 data = 0xfffb;
479 break;
480 }
481
482 p = ioremap(pci_resource_start(dev, 0), 0x80);
483 if (p == NULL)
484 return -ENOMEM;
485
486 writew(readw(p + 0x28) & data, p + 0x28);
487 readw(p + 0x28);
488 iounmap(p);
489 return 0;
490 }
491
492 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
493 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
494
495 static int pci_siig20x_init(struct pci_dev *dev)
496 {
497 u8 data;
498
499 /* Change clock frequency for the first UART. */
500 pci_read_config_byte(dev, 0x6f, &data);
501 pci_write_config_byte(dev, 0x6f, data & 0xef);
502
503 /* If this card has 2 UART, we have to do the same with second UART. */
504 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
505 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
506 pci_read_config_byte(dev, 0x73, &data);
507 pci_write_config_byte(dev, 0x73, data & 0xef);
508 }
509 return 0;
510 }
511
512 static int pci_siig_init(struct pci_dev *dev)
513 {
514 unsigned int type = dev->device & 0xff00;
515
516 if (type == 0x1000)
517 return pci_siig10x_init(dev);
518 else if (type == 0x2000)
519 return pci_siig20x_init(dev);
520
521 moan_device("Unknown SIIG card", dev);
522 return -ENODEV;
523 }
524
525 static int pci_siig_setup(struct serial_private *priv,
526 const struct pciserial_board *board,
527 struct uart_8250_port *port, int idx)
528 {
529 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
530
531 if (idx > 3) {
532 bar = 4;
533 offset = (idx - 4) * 8;
534 }
535
536 return setup_port(priv, port, bar, offset, 0);
537 }
538
539 /*
540 * Timedia has an explosion of boards, and to avoid the PCI table from
541 * growing *huge*, we use this function to collapse some 70 entries
542 * in the PCI table into one, for sanity's and compactness's sake.
543 */
544 static const unsigned short timedia_single_port[] = {
545 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
546 };
547
548 static const unsigned short timedia_dual_port[] = {
549 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
550 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
551 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
552 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
553 0xD079, 0
554 };
555
556 static const unsigned short timedia_quad_port[] = {
557 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
558 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
559 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
560 0xB157, 0
561 };
562
563 static const unsigned short timedia_eight_port[] = {
564 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
565 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
566 };
567
568 static const struct timedia_struct {
569 int num;
570 const unsigned short *ids;
571 } timedia_data[] = {
572 { 1, timedia_single_port },
573 { 2, timedia_dual_port },
574 { 4, timedia_quad_port },
575 { 8, timedia_eight_port }
576 };
577
578 /*
579 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
580 * listing them individually, this driver merely grabs them all with
581 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
582 * and should be left free to be claimed by parport_serial instead.
583 */
584 static int pci_timedia_probe(struct pci_dev *dev)
585 {
586 /*
587 * Check the third digit of the subdevice ID
588 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
589 */
590 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
591 dev_info(&dev->dev,
592 "ignoring Timedia subdevice %04x for parport_serial\n",
593 dev->subsystem_device);
594 return -ENODEV;
595 }
596
597 return 0;
598 }
599
600 static int pci_timedia_init(struct pci_dev *dev)
601 {
602 const unsigned short *ids;
603 int i, j;
604
605 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
606 ids = timedia_data[i].ids;
607 for (j = 0; ids[j]; j++)
608 if (dev->subsystem_device == ids[j])
609 return timedia_data[i].num;
610 }
611 return 0;
612 }
613
614 /*
615 * Timedia/SUNIX uses a mixture of BARs and offsets
616 * Ugh, this is ugly as all hell --- TYT
617 */
618 static int
619 pci_timedia_setup(struct serial_private *priv,
620 const struct pciserial_board *board,
621 struct uart_8250_port *port, int idx)
622 {
623 unsigned int bar = 0, offset = board->first_offset;
624
625 switch (idx) {
626 case 0:
627 bar = 0;
628 break;
629 case 1:
630 offset = board->uart_offset;
631 bar = 0;
632 break;
633 case 2:
634 bar = 1;
635 break;
636 case 3:
637 offset = board->uart_offset;
638 fallthrough;
639 case 4: /* BAR 2 */
640 case 5: /* BAR 3 */
641 case 6: /* BAR 4 */
642 case 7: /* BAR 5 */
643 bar = idx - 2;
644 }
645
646 return setup_port(priv, port, bar, offset, board->reg_shift);
647 }
648
649 /*
650 * Some Titan cards are also a little weird
651 */
652 static int
653 titan_400l_800l_setup(struct serial_private *priv,
654 const struct pciserial_board *board,
655 struct uart_8250_port *port, int idx)
656 {
657 unsigned int bar, offset = board->first_offset;
658
659 switch (idx) {
660 case 0:
661 bar = 1;
662 break;
663 case 1:
664 bar = 2;
665 break;
666 default:
667 bar = 4;
668 offset = (idx - 2) * board->uart_offset;
669 }
670
671 return setup_port(priv, port, bar, offset, board->reg_shift);
672 }
673
674 static int pci_xircom_init(struct pci_dev *dev)
675 {
676 msleep(100);
677 return 0;
678 }
679
680 static int pci_ni8420_init(struct pci_dev *dev)
681 {
682 void __iomem *p;
683 unsigned int bar = 0;
684
685 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
686 moan_device("no memory in bar", dev);
687 return 0;
688 }
689
690 p = pci_ioremap_bar(dev, bar);
691 if (p == NULL)
692 return -ENOMEM;
693
694 /* Enable CPU Interrupt */
695 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
696 p + NI8420_INT_ENABLE_REG);
697
698 iounmap(p);
699 return 0;
700 }
701
702 #define MITE_IOWBSR1_WSIZE 0xa
703 #define MITE_IOWBSR1_WIN_OFFSET 0x800
704 #define MITE_IOWBSR1_WENAB (1 << 7)
705 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
706 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
707 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
708
709 static int pci_ni8430_init(struct pci_dev *dev)
710 {
711 void __iomem *p;
712 struct pci_bus_region region;
713 u32 device_window;
714 unsigned int bar = 0;
715
716 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
717 moan_device("no memory in bar", dev);
718 return 0;
719 }
720
721 p = pci_ioremap_bar(dev, bar);
722 if (p == NULL)
723 return -ENOMEM;
724
725 /*
726 * Set device window address and size in BAR0, while acknowledging that
727 * the resource structure may contain a translated address that differs
728 * from the address the device responds to.
729 */
730 pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
731 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
732 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
733 writel(device_window, p + MITE_IOWBSR1);
734
735 /* Set window access to go to RAMSEL IO address space */
736 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
737 p + MITE_IOWCR1);
738
739 /* Enable IO Bus Interrupt 0 */
740 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
741
742 /* Enable CPU Interrupt */
743 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
744
745 iounmap(p);
746 return 0;
747 }
748
749 /* UART Port Control Register */
750 #define NI8430_PORTCON 0x0f
751 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
752
753 static int
754 pci_ni8430_setup(struct serial_private *priv,
755 const struct pciserial_board *board,
756 struct uart_8250_port *port, int idx)
757 {
758 struct pci_dev *dev = priv->dev;
759 void __iomem *p;
760 unsigned int bar, offset = board->first_offset;
761
762 if (idx >= board->num_ports)
763 return 1;
764
765 bar = FL_GET_BASE(board->flags);
766 offset += idx * board->uart_offset;
767
768 p = pci_ioremap_bar(dev, bar);
769 if (!p)
770 return -ENOMEM;
771
772 /* enable the transceiver */
773 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
774 p + offset + NI8430_PORTCON);
775
776 iounmap(p);
777
778 return setup_port(priv, port, bar, offset, board->reg_shift);
779 }
780
781 static int pci_netmos_9900_setup(struct serial_private *priv,
782 const struct pciserial_board *board,
783 struct uart_8250_port *port, int idx)
784 {
785 unsigned int bar;
786
787 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
788 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
789 /* netmos apparently orders BARs by datasheet layout, so serial
790 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
791 */
792 bar = 3 * idx;
793
794 return setup_port(priv, port, bar, 0, board->reg_shift);
795 } else {
796 return pci_default_setup(priv, board, port, idx);
797 }
798 }
799
800 /* the 99xx series comes with a range of device IDs and a variety
801 * of capabilities:
802 *
803 * 9900 has varying capabilities and can cascade to sub-controllers
804 * (cascading should be purely internal)
805 * 9904 is hardwired with 4 serial ports
806 * 9912 and 9922 are hardwired with 2 serial ports
807 */
808 static int pci_netmos_9900_numports(struct pci_dev *dev)
809 {
810 unsigned int c = dev->class;
811 unsigned int pi;
812 unsigned short sub_serports;
813
814 pi = c & 0xff;
815
816 if (pi == 2)
817 return 1;
818
819 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
820 /* two possibilities: 0x30ps encodes number of parallel and
821 * serial ports, or 0x1000 indicates *something*. This is not
822 * immediately obvious, since the 2s1p+4s configuration seems
823 * to offer all functionality on functions 0..2, while still
824 * advertising the same function 3 as the 4s+2s1p config.
825 */
826 sub_serports = dev->subsystem_device & 0xf;
827 if (sub_serports > 0)
828 return sub_serports;
829
830 dev_err(&dev->dev,
831 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
832 return 0;
833 }
834
835 moan_device("unknown NetMos/Mostech program interface", dev);
836 return 0;
837 }
838
839 static int pci_netmos_init(struct pci_dev *dev)
840 {
841 /* subdevice 0x00PS means <P> parallel, <S> serial */
842 unsigned int num_serial = dev->subsystem_device & 0xf;
843
844 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
845 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
846 return 0;
847
848 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
849 dev->subsystem_device == 0x0299)
850 return 0;
851
852 switch (dev->device) { /* FALLTHROUGH on all */
853 case PCI_DEVICE_ID_NETMOS_9904:
854 case PCI_DEVICE_ID_NETMOS_9912:
855 case PCI_DEVICE_ID_NETMOS_9922:
856 case PCI_DEVICE_ID_NETMOS_9900:
857 num_serial = pci_netmos_9900_numports(dev);
858 break;
859
860 default:
861 break;
862 }
863
864 if (num_serial == 0) {
865 moan_device("unknown NetMos/Mostech device", dev);
866 return -ENODEV;
867 }
868
869 return num_serial;
870 }
871
872 /*
873 * These chips are available with optionally one parallel port and up to
874 * two serial ports. Unfortunately they all have the same product id.
875 *
876 * Basic configuration is done over a region of 32 I/O ports. The base
877 * ioport is called INTA or INTC, depending on docs/other drivers.
878 *
879 * The region of the 32 I/O ports is configured in POSIO0R...
880 */
881
882 /* registers */
883 #define ITE_887x_MISCR 0x9c
884 #define ITE_887x_INTCBAR 0x78
885 #define ITE_887x_UARTBAR 0x7c
886 #define ITE_887x_PS0BAR 0x10
887 #define ITE_887x_POSIO0 0x60
888
889 /* I/O space size */
890 #define ITE_887x_IOSIZE 32
891 /* I/O space size (bits 26-24; 8 bytes = 011b) */
892 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
893 /* I/O space size (bits 26-24; 32 bytes = 101b) */
894 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
895 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
896 #define ITE_887x_POSIO_SPEED (3 << 29)
897 /* enable IO_Space bit */
898 #define ITE_887x_POSIO_ENABLE (1 << 31)
899
900 static int pci_ite887x_init(struct pci_dev *dev)
901 {
902 /* inta_addr are the configuration addresses of the ITE */
903 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
904 0x200, 0x280, 0 };
905 int ret, i, type;
906 struct resource *iobase = NULL;
907 u32 miscr, uartbar, ioport;
908
909 /* search for the base-ioport */
910 i = 0;
911 while (inta_addr[i] && iobase == NULL) {
912 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
913 "ite887x");
914 if (iobase != NULL) {
915 /* write POSIO0R - speed | size | ioport */
916 pci_write_config_dword(dev, ITE_887x_POSIO0,
917 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
918 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
919 /* write INTCBAR - ioport */
920 pci_write_config_dword(dev, ITE_887x_INTCBAR,
921 inta_addr[i]);
922 ret = inb(inta_addr[i]);
923 if (ret != 0xff) {
924 /* ioport connected */
925 break;
926 }
927 release_region(iobase->start, ITE_887x_IOSIZE);
928 iobase = NULL;
929 }
930 i++;
931 }
932
933 if (!inta_addr[i]) {
934 dev_err(&dev->dev, "ite887x: could not find iobase\n");
935 return -ENODEV;
936 }
937
938 /* start of undocumented type checking (see parport_pc.c) */
939 type = inb(iobase->start + 0x18) & 0x0f;
940
941 switch (type) {
942 case 0x2: /* ITE8871 (1P) */
943 case 0xa: /* ITE8875 (1P) */
944 ret = 0;
945 break;
946 case 0xe: /* ITE8872 (2S1P) */
947 ret = 2;
948 break;
949 case 0x6: /* ITE8873 (1S) */
950 ret = 1;
951 break;
952 case 0x8: /* ITE8874 (2S) */
953 ret = 2;
954 break;
955 default:
956 moan_device("Unknown ITE887x", dev);
957 ret = -ENODEV;
958 }
959
960 /* configure all serial ports */
961 for (i = 0; i < ret; i++) {
962 /* read the I/O port from the device */
963 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
964 &ioport);
965 ioport &= 0x0000FF00; /* the actual base address */
966 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
967 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
968 ITE_887x_POSIO_IOSIZE_8 | ioport);
969
970 /* write the ioport to the UARTBAR */
971 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
972 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
973 uartbar |= (ioport << (16 * i)); /* set the ioport */
974 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
975
976 /* get current config */
977 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
978 /* disable interrupts (UARTx_Routing[3:0]) */
979 miscr &= ~(0xf << (12 - 4 * i));
980 /* activate the UART (UARTx_En) */
981 miscr |= 1 << (23 - i);
982 /* write new config with activated UART */
983 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
984 }
985
986 if (ret <= 0) {
987 /* the device has no UARTs if we get here */
988 release_region(iobase->start, ITE_887x_IOSIZE);
989 }
990
991 return ret;
992 }
993
994 static void pci_ite887x_exit(struct pci_dev *dev)
995 {
996 u32 ioport;
997 /* the ioport is bit 0-15 in POSIO0R */
998 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
999 ioport &= 0xffff;
1000 release_region(ioport, ITE_887x_IOSIZE);
1001 }
1002
1003 /*
1004 * EndRun Technologies.
1005 * Determine the number of ports available on the device.
1006 */
1007 #define PCI_VENDOR_ID_ENDRUN 0x7401
1008 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1009
1010 static int pci_endrun_init(struct pci_dev *dev)
1011 {
1012 u8 __iomem *p;
1013 unsigned long deviceID;
1014 unsigned int number_uarts = 0;
1015
1016 /* EndRun device is all 0xexxx */
1017 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1018 (dev->device & 0xf000) != 0xe000)
1019 return 0;
1020
1021 p = pci_iomap(dev, 0, 5);
1022 if (p == NULL)
1023 return -ENOMEM;
1024
1025 deviceID = ioread32(p);
1026 /* EndRun device */
1027 if (deviceID == 0x07000200) {
1028 number_uarts = ioread8(p + 4);
1029 dev_dbg(&dev->dev,
1030 "%d ports detected on EndRun PCI Express device\n",
1031 number_uarts);
1032 }
1033 pci_iounmap(dev, p);
1034 return number_uarts;
1035 }
1036
1037 /*
1038 * Oxford Semiconductor Inc.
1039 * Check that device is part of the Tornado range of devices, then determine
1040 * the number of ports available on the device.
1041 */
1042 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1043 {
1044 u8 __iomem *p;
1045 unsigned long deviceID;
1046 unsigned int number_uarts = 0;
1047
1048 /* OxSemi Tornado devices are all 0xCxxx */
1049 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1050 (dev->device & 0xF000) != 0xC000)
1051 return 0;
1052
1053 p = pci_iomap(dev, 0, 5);
1054 if (p == NULL)
1055 return -ENOMEM;
1056
1057 deviceID = ioread32(p);
1058 /* Tornado device */
1059 if (deviceID == 0x07000200) {
1060 number_uarts = ioread8(p + 4);
1061 dev_dbg(&dev->dev,
1062 "%d ports detected on Oxford PCI Express device\n",
1063 number_uarts);
1064 }
1065 pci_iounmap(dev, p);
1066 return number_uarts;
1067 }
1068
1069 static int pci_asix_setup(struct serial_private *priv,
1070 const struct pciserial_board *board,
1071 struct uart_8250_port *port, int idx)
1072 {
1073 port->bugs |= UART_BUG_PARITY;
1074 return pci_default_setup(priv, board, port, idx);
1075 }
1076
1077 /* Quatech devices have their own extra interface features */
1078
1079 struct quatech_feature {
1080 u16 devid;
1081 bool amcc;
1082 };
1083
1084 #define QPCR_TEST_FOR1 0x3F
1085 #define QPCR_TEST_GET1 0x00
1086 #define QPCR_TEST_FOR2 0x40
1087 #define QPCR_TEST_GET2 0x40
1088 #define QPCR_TEST_FOR3 0x80
1089 #define QPCR_TEST_GET3 0x40
1090 #define QPCR_TEST_FOR4 0xC0
1091 #define QPCR_TEST_GET4 0x80
1092
1093 #define QOPR_CLOCK_X1 0x0000
1094 #define QOPR_CLOCK_X2 0x0001
1095 #define QOPR_CLOCK_X4 0x0002
1096 #define QOPR_CLOCK_X8 0x0003
1097 #define QOPR_CLOCK_RATE_MASK 0x0003
1098
1099
1100 static struct quatech_feature quatech_cards[] = {
1101 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1102 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1103 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1104 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1105 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1106 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1107 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1108 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1109 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1110 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1111 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1112 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1113 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1114 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1115 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1116 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1117 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1118 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1119 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1120 { 0, }
1121 };
1122
1123 static int pci_quatech_amcc(u16 devid)
1124 {
1125 struct quatech_feature *qf = &quatech_cards[0];
1126 while (qf->devid) {
1127 if (qf->devid == devid)
1128 return qf->amcc;
1129 qf++;
1130 }
1131 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1132 return 0;
1133 };
1134
1135 static int pci_quatech_rqopr(struct uart_8250_port *port)
1136 {
1137 unsigned long base = port->port.iobase;
1138 u8 LCR, val;
1139
1140 LCR = inb(base + UART_LCR);
1141 outb(0xBF, base + UART_LCR);
1142 val = inb(base + UART_SCR);
1143 outb(LCR, base + UART_LCR);
1144 return val;
1145 }
1146
1147 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1148 {
1149 unsigned long base = port->port.iobase;
1150 u8 LCR;
1151
1152 LCR = inb(base + UART_LCR);
1153 outb(0xBF, base + UART_LCR);
1154 inb(base + UART_SCR);
1155 outb(qopr, base + UART_SCR);
1156 outb(LCR, base + UART_LCR);
1157 }
1158
1159 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1160 {
1161 unsigned long base = port->port.iobase;
1162 u8 LCR, val, qmcr;
1163
1164 LCR = inb(base + UART_LCR);
1165 outb(0xBF, base + UART_LCR);
1166 val = inb(base + UART_SCR);
1167 outb(val | 0x10, base + UART_SCR);
1168 qmcr = inb(base + UART_MCR);
1169 outb(val, base + UART_SCR);
1170 outb(LCR, base + UART_LCR);
1171
1172 return qmcr;
1173 }
1174
1175 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1176 {
1177 unsigned long base = port->port.iobase;
1178 u8 LCR, val;
1179
1180 LCR = inb(base + UART_LCR);
1181 outb(0xBF, base + UART_LCR);
1182 val = inb(base + UART_SCR);
1183 outb(val | 0x10, base + UART_SCR);
1184 outb(qmcr, base + UART_MCR);
1185 outb(val, base + UART_SCR);
1186 outb(LCR, base + UART_LCR);
1187 }
1188
1189 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1190 {
1191 unsigned long base = port->port.iobase;
1192 u8 LCR, val;
1193
1194 LCR = inb(base + UART_LCR);
1195 outb(0xBF, base + UART_LCR);
1196 val = inb(base + UART_SCR);
1197 if (val & 0x20) {
1198 outb(0x80, UART_LCR);
1199 if (!(inb(UART_SCR) & 0x20)) {
1200 outb(LCR, base + UART_LCR);
1201 return 1;
1202 }
1203 }
1204 return 0;
1205 }
1206
1207 static int pci_quatech_test(struct uart_8250_port *port)
1208 {
1209 u8 reg, qopr;
1210
1211 qopr = pci_quatech_rqopr(port);
1212 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1213 reg = pci_quatech_rqopr(port) & 0xC0;
1214 if (reg != QPCR_TEST_GET1)
1215 return -EINVAL;
1216 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1217 reg = pci_quatech_rqopr(port) & 0xC0;
1218 if (reg != QPCR_TEST_GET2)
1219 return -EINVAL;
1220 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1221 reg = pci_quatech_rqopr(port) & 0xC0;
1222 if (reg != QPCR_TEST_GET3)
1223 return -EINVAL;
1224 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1225 reg = pci_quatech_rqopr(port) & 0xC0;
1226 if (reg != QPCR_TEST_GET4)
1227 return -EINVAL;
1228
1229 pci_quatech_wqopr(port, qopr);
1230 return 0;
1231 }
1232
1233 static int pci_quatech_clock(struct uart_8250_port *port)
1234 {
1235 u8 qopr, reg, set;
1236 unsigned long clock;
1237
1238 if (pci_quatech_test(port) < 0)
1239 return 1843200;
1240
1241 qopr = pci_quatech_rqopr(port);
1242
1243 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1244 reg = pci_quatech_rqopr(port);
1245 if (reg & QOPR_CLOCK_X8) {
1246 clock = 1843200;
1247 goto out;
1248 }
1249 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1250 reg = pci_quatech_rqopr(port);
1251 if (!(reg & QOPR_CLOCK_X8)) {
1252 clock = 1843200;
1253 goto out;
1254 }
1255 reg &= QOPR_CLOCK_X8;
1256 if (reg == QOPR_CLOCK_X2) {
1257 clock = 3685400;
1258 set = QOPR_CLOCK_X2;
1259 } else if (reg == QOPR_CLOCK_X4) {
1260 clock = 7372800;
1261 set = QOPR_CLOCK_X4;
1262 } else if (reg == QOPR_CLOCK_X8) {
1263 clock = 14745600;
1264 set = QOPR_CLOCK_X8;
1265 } else {
1266 clock = 1843200;
1267 set = QOPR_CLOCK_X1;
1268 }
1269 qopr &= ~QOPR_CLOCK_RATE_MASK;
1270 qopr |= set;
1271
1272 out:
1273 pci_quatech_wqopr(port, qopr);
1274 return clock;
1275 }
1276
1277 static int pci_quatech_rs422(struct uart_8250_port *port)
1278 {
1279 u8 qmcr;
1280 int rs422 = 0;
1281
1282 if (!pci_quatech_has_qmcr(port))
1283 return 0;
1284 qmcr = pci_quatech_rqmcr(port);
1285 pci_quatech_wqmcr(port, 0xFF);
1286 if (pci_quatech_rqmcr(port))
1287 rs422 = 1;
1288 pci_quatech_wqmcr(port, qmcr);
1289 return rs422;
1290 }
1291
1292 static int pci_quatech_init(struct pci_dev *dev)
1293 {
1294 if (pci_quatech_amcc(dev->device)) {
1295 unsigned long base = pci_resource_start(dev, 0);
1296 if (base) {
1297 u32 tmp;
1298
1299 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1300 tmp = inl(base + 0x3c);
1301 outl(tmp | 0x01000000, base + 0x3c);
1302 outl(tmp &= ~0x01000000, base + 0x3c);
1303 }
1304 }
1305 return 0;
1306 }
1307
1308 static int pci_quatech_setup(struct serial_private *priv,
1309 const struct pciserial_board *board,
1310 struct uart_8250_port *port, int idx)
1311 {
1312 /* Needed by pci_quatech calls below */
1313 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1314 /* Set up the clocking */
1315 port->port.uartclk = pci_quatech_clock(port);
1316 /* For now just warn about RS422 */
1317 if (pci_quatech_rs422(port))
1318 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1319 return pci_default_setup(priv, board, port, idx);
1320 }
1321
1322 static void pci_quatech_exit(struct pci_dev *dev)
1323 {
1324 }
1325
1326 static int pci_default_setup(struct serial_private *priv,
1327 const struct pciserial_board *board,
1328 struct uart_8250_port *port, int idx)
1329 {
1330 unsigned int bar, offset = board->first_offset, maxnr;
1331
1332 bar = FL_GET_BASE(board->flags);
1333 if (board->flags & FL_BASE_BARS)
1334 bar += idx;
1335 else
1336 offset += idx * board->uart_offset;
1337
1338 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1339 (board->reg_shift + 3);
1340
1341 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1342 return 1;
1343
1344 return setup_port(priv, port, bar, offset, board->reg_shift);
1345 }
1346 static void
1347 pericom_do_set_divisor(struct uart_port *port, unsigned int baud,
1348 unsigned int quot, unsigned int quot_frac)
1349 {
1350 int scr;
1351 int lcr;
1352 int actual_baud;
1353 int tolerance;
1354
1355 for (scr = 5 ; scr <= 15 ; scr++) {
1356 actual_baud = 921600 * 16 / scr;
1357 tolerance = actual_baud / 50;
1358
1359 if ((baud < actual_baud + tolerance) &&
1360 (baud > actual_baud - tolerance)) {
1361
1362 lcr = serial_port_in(port, UART_LCR);
1363 serial_port_out(port, UART_LCR, lcr | 0x80);
1364
1365 serial_port_out(port, UART_DLL, 1);
1366 serial_port_out(port, UART_DLM, 0);
1367 serial_port_out(port, 2, 16 - scr);
1368 serial_port_out(port, UART_LCR, lcr);
1369 return;
1370 } else if (baud > actual_baud) {
1371 break;
1372 }
1373 }
1374 serial8250_do_set_divisor(port, baud, quot, quot_frac);
1375 }
1376 static int pci_pericom_setup(struct serial_private *priv,
1377 const struct pciserial_board *board,
1378 struct uart_8250_port *port, int idx)
1379 {
1380 unsigned int bar, offset = board->first_offset, maxnr;
1381
1382 bar = FL_GET_BASE(board->flags);
1383 if (board->flags & FL_BASE_BARS)
1384 bar += idx;
1385 else
1386 offset += idx * board->uart_offset;
1387
1388
1389 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1390 (board->reg_shift + 3);
1391
1392 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1393 return 1;
1394
1395 port->port.set_divisor = pericom_do_set_divisor;
1396
1397 return setup_port(priv, port, bar, offset, board->reg_shift);
1398 }
1399
1400 static int pci_pericom_setup_four_at_eight(struct serial_private *priv,
1401 const struct pciserial_board *board,
1402 struct uart_8250_port *port, int idx)
1403 {
1404 unsigned int bar, offset = board->first_offset, maxnr;
1405
1406 bar = FL_GET_BASE(board->flags);
1407 if (board->flags & FL_BASE_BARS)
1408 bar += idx;
1409 else
1410 offset += idx * board->uart_offset;
1411
1412 if (idx==3)
1413 offset = 0x38;
1414
1415 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1416 (board->reg_shift + 3);
1417
1418 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1419 return 1;
1420
1421 port->port.set_divisor = pericom_do_set_divisor;
1422
1423 return setup_port(priv, port, bar, offset, board->reg_shift);
1424 }
1425
1426 static int
1427 ce4100_serial_setup(struct serial_private *priv,
1428 const struct pciserial_board *board,
1429 struct uart_8250_port *port, int idx)
1430 {
1431 int ret;
1432
1433 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1434 port->port.iotype = UPIO_MEM32;
1435 port->port.type = PORT_XSCALE;
1436 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1437 port->port.regshift = 2;
1438
1439 return ret;
1440 }
1441
1442 static int
1443 pci_omegapci_setup(struct serial_private *priv,
1444 const struct pciserial_board *board,
1445 struct uart_8250_port *port, int idx)
1446 {
1447 return setup_port(priv, port, 2, idx * 8, 0);
1448 }
1449
1450 static int
1451 pci_brcm_trumanage_setup(struct serial_private *priv,
1452 const struct pciserial_board *board,
1453 struct uart_8250_port *port, int idx)
1454 {
1455 int ret = pci_default_setup(priv, board, port, idx);
1456
1457 port->port.type = PORT_BRCM_TRUMANAGE;
1458 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1459 return ret;
1460 }
1461
1462 /* RTS will control by MCR if this bit is 0 */
1463 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1464 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1465 #define FINTEK_RTS_INVERT BIT(5)
1466
1467 /* We should do proper H/W transceiver setting before change to RS485 mode */
1468 static int pci_fintek_rs485_config(struct uart_port *port,
1469 struct serial_rs485 *rs485)
1470 {
1471 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1472 u8 setting;
1473 u8 *index = (u8 *) port->private_data;
1474
1475 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1476
1477 if (!rs485)
1478 rs485 = &port->rs485;
1479 else if (rs485->flags & SER_RS485_ENABLED)
1480 memset(rs485->padding, 0, sizeof(rs485->padding));
1481 else
1482 memset(rs485, 0, sizeof(*rs485));
1483
1484 /* F81504/508/512 not support RTS delay before or after send */
1485 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1486
1487 if (rs485->flags & SER_RS485_ENABLED) {
1488 /* Enable RTS H/W control mode */
1489 setting |= FINTEK_RTS_CONTROL_BY_HW;
1490
1491 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1492 /* RTS driving high on TX */
1493 setting &= ~FINTEK_RTS_INVERT;
1494 } else {
1495 /* RTS driving low on TX */
1496 setting |= FINTEK_RTS_INVERT;
1497 }
1498
1499 rs485->delay_rts_after_send = 0;
1500 rs485->delay_rts_before_send = 0;
1501 } else {
1502 /* Disable RTS H/W control mode */
1503 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1504 }
1505
1506 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1507
1508 if (rs485 != &port->rs485)
1509 port->rs485 = *rs485;
1510
1511 return 0;
1512 }
1513
1514 static int pci_fintek_setup(struct serial_private *priv,
1515 const struct pciserial_board *board,
1516 struct uart_8250_port *port, int idx)
1517 {
1518 struct pci_dev *pdev = priv->dev;
1519 u8 *data;
1520 u8 config_base;
1521 u16 iobase;
1522
1523 config_base = 0x40 + 0x08 * idx;
1524
1525 /* Get the io address from configuration space */
1526 pci_read_config_word(pdev, config_base + 4, &iobase);
1527
1528 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1529
1530 port->port.iotype = UPIO_PORT;
1531 port->port.iobase = iobase;
1532 port->port.rs485_config = pci_fintek_rs485_config;
1533
1534 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1535 if (!data)
1536 return -ENOMEM;
1537
1538 /* preserve index in PCI configuration space */
1539 *data = idx;
1540 port->port.private_data = data;
1541
1542 return 0;
1543 }
1544
1545 static int pci_fintek_init(struct pci_dev *dev)
1546 {
1547 unsigned long iobase;
1548 u32 max_port, i;
1549 resource_size_t bar_data[3];
1550 u8 config_base;
1551 struct serial_private *priv = pci_get_drvdata(dev);
1552 struct uart_8250_port *port;
1553
1554 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1555 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1556 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1557 return -ENODEV;
1558
1559 switch (dev->device) {
1560 case 0x1104: /* 4 ports */
1561 case 0x1108: /* 8 ports */
1562 max_port = dev->device & 0xff;
1563 break;
1564 case 0x1112: /* 12 ports */
1565 max_port = 12;
1566 break;
1567 default:
1568 return -EINVAL;
1569 }
1570
1571 /* Get the io address dispatch from the BIOS */
1572 bar_data[0] = pci_resource_start(dev, 5);
1573 bar_data[1] = pci_resource_start(dev, 4);
1574 bar_data[2] = pci_resource_start(dev, 3);
1575
1576 for (i = 0; i < max_port; ++i) {
1577 /* UART0 configuration offset start from 0x40 */
1578 config_base = 0x40 + 0x08 * i;
1579
1580 /* Calculate Real IO Port */
1581 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1582
1583 /* Enable UART I/O port */
1584 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1585
1586 /* Select 128-byte FIFO and 8x FIFO threshold */
1587 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1588
1589 /* LSB UART */
1590 pci_write_config_byte(dev, config_base + 0x04,
1591 (u8)(iobase & 0xff));
1592
1593 /* MSB UART */
1594 pci_write_config_byte(dev, config_base + 0x05,
1595 (u8)((iobase & 0xff00) >> 8));
1596
1597 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1598
1599 if (priv) {
1600 /* re-apply RS232/485 mode when
1601 * pciserial_resume_ports()
1602 */
1603 port = serial8250_get_port(priv->line[i]);
1604 pci_fintek_rs485_config(&port->port, NULL);
1605 } else {
1606 /* First init without port data
1607 * force init to RS232 Mode
1608 */
1609 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1610 }
1611 }
1612
1613 return max_port;
1614 }
1615
1616 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value)
1617 {
1618 struct f815xxa_data *data = p->private_data;
1619 unsigned long flags;
1620
1621 spin_lock_irqsave(&data->lock, flags);
1622 writeb(value, p->membase + offset);
1623 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
1624 spin_unlock_irqrestore(&data->lock, flags);
1625 }
1626
1627 static int pci_fintek_f815xxa_setup(struct serial_private *priv,
1628 const struct pciserial_board *board,
1629 struct uart_8250_port *port, int idx)
1630 {
1631 struct pci_dev *pdev = priv->dev;
1632 struct f815xxa_data *data;
1633
1634 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
1635 if (!data)
1636 return -ENOMEM;
1637
1638 data->idx = idx;
1639 spin_lock_init(&data->lock);
1640
1641 port->port.private_data = data;
1642 port->port.iotype = UPIO_MEM;
1643 port->port.flags |= UPF_IOREMAP;
1644 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
1645 port->port.serial_out = f815xxa_mem_serial_out;
1646
1647 return 0;
1648 }
1649
1650 static int pci_fintek_f815xxa_init(struct pci_dev *dev)
1651 {
1652 u32 max_port, i;
1653 int config_base;
1654
1655 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM))
1656 return -ENODEV;
1657
1658 switch (dev->device) {
1659 case 0x1204: /* 4 ports */
1660 case 0x1208: /* 8 ports */
1661 max_port = dev->device & 0xff;
1662 break;
1663 case 0x1212: /* 12 ports */
1664 max_port = 12;
1665 break;
1666 default:
1667 return -EINVAL;
1668 }
1669
1670 /* Set to mmio decode */
1671 pci_write_config_byte(dev, 0x209, 0x40);
1672
1673 for (i = 0; i < max_port; ++i) {
1674 /* UART0 configuration offset start from 0x2A0 */
1675 config_base = 0x2A0 + 0x08 * i;
1676
1677 /* Select 128-byte FIFO and 8x FIFO threshold */
1678 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1679
1680 /* Enable UART I/O port */
1681 pci_write_config_byte(dev, config_base + 0, 0x01);
1682 }
1683
1684 return max_port;
1685 }
1686
1687 static int skip_tx_en_setup(struct serial_private *priv,
1688 const struct pciserial_board *board,
1689 struct uart_8250_port *port, int idx)
1690 {
1691 port->port.quirks |= UPQ_NO_TXEN_TEST;
1692 dev_dbg(&priv->dev->dev,
1693 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1694 priv->dev->vendor, priv->dev->device,
1695 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1696
1697 return pci_default_setup(priv, board, port, idx);
1698 }
1699
1700 static void kt_handle_break(struct uart_port *p)
1701 {
1702 struct uart_8250_port *up = up_to_u8250p(p);
1703 /*
1704 * On receipt of a BI, serial device in Intel ME (Intel
1705 * management engine) needs to have its fifos cleared for sane
1706 * SOL (Serial Over Lan) output.
1707 */
1708 serial8250_clear_and_reinit_fifos(up);
1709 }
1710
1711 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1712 {
1713 struct uart_8250_port *up = up_to_u8250p(p);
1714 unsigned int val;
1715
1716 /*
1717 * When the Intel ME (management engine) gets reset its serial
1718 * port registers could return 0 momentarily. Functions like
1719 * serial8250_console_write, read and save the IER, perform
1720 * some operation and then restore it. In order to avoid
1721 * setting IER register inadvertently to 0, if the value read
1722 * is 0, double check with ier value in uart_8250_port and use
1723 * that instead. up->ier should be the same value as what is
1724 * currently configured.
1725 */
1726 val = inb(p->iobase + offset);
1727 if (offset == UART_IER) {
1728 if (val == 0)
1729 val = up->ier;
1730 }
1731 return val;
1732 }
1733
1734 static int kt_serial_setup(struct serial_private *priv,
1735 const struct pciserial_board *board,
1736 struct uart_8250_port *port, int idx)
1737 {
1738 port->port.flags |= UPF_BUG_THRE;
1739 port->port.serial_in = kt_serial_in;
1740 port->port.handle_break = kt_handle_break;
1741 return skip_tx_en_setup(priv, board, port, idx);
1742 }
1743
1744 static int pci_eg20t_init(struct pci_dev *dev)
1745 {
1746 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1747 return -ENODEV;
1748 #else
1749 return 0;
1750 #endif
1751 }
1752
1753 static int
1754 pci_wch_ch353_setup(struct serial_private *priv,
1755 const struct pciserial_board *board,
1756 struct uart_8250_port *port, int idx)
1757 {
1758 port->port.flags |= UPF_FIXED_TYPE;
1759 port->port.type = PORT_16550A;
1760 return pci_default_setup(priv, board, port, idx);
1761 }
1762
1763 static int
1764 pci_wch_ch355_setup(struct serial_private *priv,
1765 const struct pciserial_board *board,
1766 struct uart_8250_port *port, int idx)
1767 {
1768 port->port.flags |= UPF_FIXED_TYPE;
1769 port->port.type = PORT_16550A;
1770 return pci_default_setup(priv, board, port, idx);
1771 }
1772
1773 static int
1774 pci_wch_ch38x_setup(struct serial_private *priv,
1775 const struct pciserial_board *board,
1776 struct uart_8250_port *port, int idx)
1777 {
1778 port->port.flags |= UPF_FIXED_TYPE;
1779 port->port.type = PORT_16850;
1780 return pci_default_setup(priv, board, port, idx);
1781 }
1782
1783
1784 #define CH384_XINT_ENABLE_REG 0xEB
1785 #define CH384_XINT_ENABLE_BIT 0x02
1786
1787 static int pci_wch_ch38x_init(struct pci_dev *dev)
1788 {
1789 int max_port;
1790 unsigned long iobase;
1791
1792
1793 switch (dev->device) {
1794 case 0x3853: /* 8 ports */
1795 max_port = 8;
1796 break;
1797 default:
1798 return -EINVAL;
1799 }
1800
1801 iobase = pci_resource_start(dev, 0);
1802 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG);
1803
1804 return max_port;
1805 }
1806
1807 static void pci_wch_ch38x_exit(struct pci_dev *dev)
1808 {
1809 unsigned long iobase;
1810
1811 iobase = pci_resource_start(dev, 0);
1812 outb(0x0, iobase + CH384_XINT_ENABLE_REG);
1813 }
1814
1815
1816 static int
1817 pci_sunix_setup(struct serial_private *priv,
1818 const struct pciserial_board *board,
1819 struct uart_8250_port *port, int idx)
1820 {
1821 int bar;
1822 int offset;
1823
1824 port->port.flags |= UPF_FIXED_TYPE;
1825 port->port.type = PORT_SUNIX;
1826
1827 if (idx < 4) {
1828 bar = 0;
1829 offset = idx * board->uart_offset;
1830 } else {
1831 bar = 1;
1832 idx -= 4;
1833 idx = div_s64_rem(idx, 4, &offset);
1834 offset = idx * 64 + offset * board->uart_offset;
1835 }
1836
1837 return setup_port(priv, port, bar, offset, 0);
1838 }
1839
1840 static int
1841 pci_moxa_setup(struct serial_private *priv,
1842 const struct pciserial_board *board,
1843 struct uart_8250_port *port, int idx)
1844 {
1845 unsigned int bar = FL_GET_BASE(board->flags);
1846 int offset;
1847
1848 if (board->num_ports == 4 && idx == 3)
1849 offset = 7 * board->uart_offset;
1850 else
1851 offset = idx * board->uart_offset;
1852
1853 return setup_port(priv, port, bar, offset, 0);
1854 }
1855
1856 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1857 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1858 #define PCI_DEVICE_ID_OCTPRO 0x0001
1859 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1860 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1861 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1862 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1863 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1864 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1865 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1866 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1867 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1868 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1869 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1870 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1871 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1872 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1873 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1874 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1875 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1876 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1877 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1878 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1879 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1880 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1881 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1882 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1883 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1884 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1885 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1886 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1887 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1888 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1889 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1890 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1891 #define PCI_VENDOR_ID_WCH 0x4348
1892 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1893 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1894 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1895 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1896 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1897 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
1898 #define PCI_VENDOR_ID_AGESTAR 0x5372
1899 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1900 #define PCI_VENDOR_ID_ASIX 0x9710
1901 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1902 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1903
1904 #define PCIE_VENDOR_ID_WCH 0x1c00
1905 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1906 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1907 #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853
1908 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1909
1910 #define PCI_VENDOR_ID_ACCESIO 0x494f
1911 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051
1912 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053
1913 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C
1914 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E
1915 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091
1916 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093
1917 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099
1918 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B
1919 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1
1920 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3
1921 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA
1922 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC
1923 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108
1924 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110
1925 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111
1926 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118
1927 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119
1928 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152
1929 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A
1930 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190
1931 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191
1932 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198
1933 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199
1934 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0
1935 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A
1936 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B
1937 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A
1938 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B
1939 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098
1940 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9
1941 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9
1942 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9
1943 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8
1944
1945
1946 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024
1947 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
1948 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
1949 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
1950 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
1951 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
1952 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
1953 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
1954 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
1955 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
1956 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
1957 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
1958
1959 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1960 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1961 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1962
1963 /*
1964 * Master list of serial port init/setup/exit quirks.
1965 * This does not describe the general nature of the port.
1966 * (ie, baud base, number and location of ports, etc)
1967 *
1968 * This list is ordered alphabetically by vendor then device.
1969 * Specific entries must come before more generic entries.
1970 */
1971 static struct pci_serial_quirk pci_serial_quirks[] = {
1972 /*
1973 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1974 */
1975 {
1976 .vendor = PCI_VENDOR_ID_AMCC,
1977 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1978 .subvendor = PCI_ANY_ID,
1979 .subdevice = PCI_ANY_ID,
1980 .setup = addidata_apci7800_setup,
1981 },
1982 /*
1983 * AFAVLAB cards - these may be called via parport_serial
1984 * It is not clear whether this applies to all products.
1985 */
1986 {
1987 .vendor = PCI_VENDOR_ID_AFAVLAB,
1988 .device = PCI_ANY_ID,
1989 .subvendor = PCI_ANY_ID,
1990 .subdevice = PCI_ANY_ID,
1991 .setup = afavlab_setup,
1992 },
1993 /*
1994 * HP Diva
1995 */
1996 {
1997 .vendor = PCI_VENDOR_ID_HP,
1998 .device = PCI_DEVICE_ID_HP_DIVA,
1999 .subvendor = PCI_ANY_ID,
2000 .subdevice = PCI_ANY_ID,
2001 .init = pci_hp_diva_init,
2002 .setup = pci_hp_diva_setup,
2003 },
2004 /*
2005 * HPE PCI serial device
2006 */
2007 {
2008 .vendor = PCI_VENDOR_ID_HP_3PAR,
2009 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL,
2010 .subvendor = PCI_ANY_ID,
2011 .subdevice = PCI_ANY_ID,
2012 .setup = pci_hp_diva_setup,
2013 },
2014 /*
2015 * Intel
2016 */
2017 {
2018 .vendor = PCI_VENDOR_ID_INTEL,
2019 .device = PCI_DEVICE_ID_INTEL_80960_RP,
2020 .subvendor = 0xe4bf,
2021 .subdevice = PCI_ANY_ID,
2022 .init = pci_inteli960ni_init,
2023 .setup = pci_default_setup,
2024 },
2025 {
2026 .vendor = PCI_VENDOR_ID_INTEL,
2027 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2028 .subvendor = PCI_ANY_ID,
2029 .subdevice = PCI_ANY_ID,
2030 .setup = skip_tx_en_setup,
2031 },
2032 {
2033 .vendor = PCI_VENDOR_ID_INTEL,
2034 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2035 .subvendor = PCI_ANY_ID,
2036 .subdevice = PCI_ANY_ID,
2037 .setup = skip_tx_en_setup,
2038 },
2039 {
2040 .vendor = PCI_VENDOR_ID_INTEL,
2041 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2042 .subvendor = PCI_ANY_ID,
2043 .subdevice = PCI_ANY_ID,
2044 .setup = skip_tx_en_setup,
2045 },
2046 {
2047 .vendor = PCI_VENDOR_ID_INTEL,
2048 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2049 .subvendor = PCI_ANY_ID,
2050 .subdevice = PCI_ANY_ID,
2051 .setup = ce4100_serial_setup,
2052 },
2053 {
2054 .vendor = PCI_VENDOR_ID_INTEL,
2055 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2056 .subvendor = PCI_ANY_ID,
2057 .subdevice = PCI_ANY_ID,
2058 .setup = kt_serial_setup,
2059 },
2060 /*
2061 * ITE
2062 */
2063 {
2064 .vendor = PCI_VENDOR_ID_ITE,
2065 .device = PCI_DEVICE_ID_ITE_8872,
2066 .subvendor = PCI_ANY_ID,
2067 .subdevice = PCI_ANY_ID,
2068 .init = pci_ite887x_init,
2069 .setup = pci_default_setup,
2070 .exit = pci_ite887x_exit,
2071 },
2072 /*
2073 * National Instruments
2074 */
2075 {
2076 .vendor = PCI_VENDOR_ID_NI,
2077 .device = PCI_DEVICE_ID_NI_PCI23216,
2078 .subvendor = PCI_ANY_ID,
2079 .subdevice = PCI_ANY_ID,
2080 .init = pci_ni8420_init,
2081 .setup = pci_default_setup,
2082 .exit = pci_ni8420_exit,
2083 },
2084 {
2085 .vendor = PCI_VENDOR_ID_NI,
2086 .device = PCI_DEVICE_ID_NI_PCI2328,
2087 .subvendor = PCI_ANY_ID,
2088 .subdevice = PCI_ANY_ID,
2089 .init = pci_ni8420_init,
2090 .setup = pci_default_setup,
2091 .exit = pci_ni8420_exit,
2092 },
2093 {
2094 .vendor = PCI_VENDOR_ID_NI,
2095 .device = PCI_DEVICE_ID_NI_PCI2324,
2096 .subvendor = PCI_ANY_ID,
2097 .subdevice = PCI_ANY_ID,
2098 .init = pci_ni8420_init,
2099 .setup = pci_default_setup,
2100 .exit = pci_ni8420_exit,
2101 },
2102 {
2103 .vendor = PCI_VENDOR_ID_NI,
2104 .device = PCI_DEVICE_ID_NI_PCI2322,
2105 .subvendor = PCI_ANY_ID,
2106 .subdevice = PCI_ANY_ID,
2107 .init = pci_ni8420_init,
2108 .setup = pci_default_setup,
2109 .exit = pci_ni8420_exit,
2110 },
2111 {
2112 .vendor = PCI_VENDOR_ID_NI,
2113 .device = PCI_DEVICE_ID_NI_PCI2324I,
2114 .subvendor = PCI_ANY_ID,
2115 .subdevice = PCI_ANY_ID,
2116 .init = pci_ni8420_init,
2117 .setup = pci_default_setup,
2118 .exit = pci_ni8420_exit,
2119 },
2120 {
2121 .vendor = PCI_VENDOR_ID_NI,
2122 .device = PCI_DEVICE_ID_NI_PCI2322I,
2123 .subvendor = PCI_ANY_ID,
2124 .subdevice = PCI_ANY_ID,
2125 .init = pci_ni8420_init,
2126 .setup = pci_default_setup,
2127 .exit = pci_ni8420_exit,
2128 },
2129 {
2130 .vendor = PCI_VENDOR_ID_NI,
2131 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2132 .subvendor = PCI_ANY_ID,
2133 .subdevice = PCI_ANY_ID,
2134 .init = pci_ni8420_init,
2135 .setup = pci_default_setup,
2136 .exit = pci_ni8420_exit,
2137 },
2138 {
2139 .vendor = PCI_VENDOR_ID_NI,
2140 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2141 .subvendor = PCI_ANY_ID,
2142 .subdevice = PCI_ANY_ID,
2143 .init = pci_ni8420_init,
2144 .setup = pci_default_setup,
2145 .exit = pci_ni8420_exit,
2146 },
2147 {
2148 .vendor = PCI_VENDOR_ID_NI,
2149 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2150 .subvendor = PCI_ANY_ID,
2151 .subdevice = PCI_ANY_ID,
2152 .init = pci_ni8420_init,
2153 .setup = pci_default_setup,
2154 .exit = pci_ni8420_exit,
2155 },
2156 {
2157 .vendor = PCI_VENDOR_ID_NI,
2158 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2159 .subvendor = PCI_ANY_ID,
2160 .subdevice = PCI_ANY_ID,
2161 .init = pci_ni8420_init,
2162 .setup = pci_default_setup,
2163 .exit = pci_ni8420_exit,
2164 },
2165 {
2166 .vendor = PCI_VENDOR_ID_NI,
2167 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2168 .subvendor = PCI_ANY_ID,
2169 .subdevice = PCI_ANY_ID,
2170 .init = pci_ni8420_init,
2171 .setup = pci_default_setup,
2172 .exit = pci_ni8420_exit,
2173 },
2174 {
2175 .vendor = PCI_VENDOR_ID_NI,
2176 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2177 .subvendor = PCI_ANY_ID,
2178 .subdevice = PCI_ANY_ID,
2179 .init = pci_ni8420_init,
2180 .setup = pci_default_setup,
2181 .exit = pci_ni8420_exit,
2182 },
2183 {
2184 .vendor = PCI_VENDOR_ID_NI,
2185 .device = PCI_ANY_ID,
2186 .subvendor = PCI_ANY_ID,
2187 .subdevice = PCI_ANY_ID,
2188 .init = pci_ni8430_init,
2189 .setup = pci_ni8430_setup,
2190 .exit = pci_ni8430_exit,
2191 },
2192 /* Quatech */
2193 {
2194 .vendor = PCI_VENDOR_ID_QUATECH,
2195 .device = PCI_ANY_ID,
2196 .subvendor = PCI_ANY_ID,
2197 .subdevice = PCI_ANY_ID,
2198 .init = pci_quatech_init,
2199 .setup = pci_quatech_setup,
2200 .exit = pci_quatech_exit,
2201 },
2202 /*
2203 * Panacom
2204 */
2205 {
2206 .vendor = PCI_VENDOR_ID_PANACOM,
2207 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2208 .subvendor = PCI_ANY_ID,
2209 .subdevice = PCI_ANY_ID,
2210 .init = pci_plx9050_init,
2211 .setup = pci_default_setup,
2212 .exit = pci_plx9050_exit,
2213 },
2214 {
2215 .vendor = PCI_VENDOR_ID_PANACOM,
2216 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2217 .subvendor = PCI_ANY_ID,
2218 .subdevice = PCI_ANY_ID,
2219 .init = pci_plx9050_init,
2220 .setup = pci_default_setup,
2221 .exit = pci_plx9050_exit,
2222 },
2223 /*
2224 * Pericom (Only 7954 - It have a offset jump for port 4)
2225 */
2226 {
2227 .vendor = PCI_VENDOR_ID_PERICOM,
2228 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954,
2229 .subvendor = PCI_ANY_ID,
2230 .subdevice = PCI_ANY_ID,
2231 .setup = pci_pericom_setup_four_at_eight,
2232 },
2233 /*
2234 * PLX
2235 */
2236 {
2237 .vendor = PCI_VENDOR_ID_PLX,
2238 .device = PCI_DEVICE_ID_PLX_9050,
2239 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2240 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2241 .init = pci_plx9050_init,
2242 .setup = pci_default_setup,
2243 .exit = pci_plx9050_exit,
2244 },
2245 {
2246 .vendor = PCI_VENDOR_ID_PLX,
2247 .device = PCI_DEVICE_ID_PLX_9050,
2248 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2249 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2250 .init = pci_plx9050_init,
2251 .setup = pci_default_setup,
2252 .exit = pci_plx9050_exit,
2253 },
2254 {
2255 .vendor = PCI_VENDOR_ID_PLX,
2256 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2257 .subvendor = PCI_VENDOR_ID_PLX,
2258 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2259 .init = pci_plx9050_init,
2260 .setup = pci_default_setup,
2261 .exit = pci_plx9050_exit,
2262 },
2263 {
2264 .vendor = PCI_VENDOR_ID_ACCESIO,
2265 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
2266 .subvendor = PCI_ANY_ID,
2267 .subdevice = PCI_ANY_ID,
2268 .setup = pci_pericom_setup_four_at_eight,
2269 },
2270 {
2271 .vendor = PCI_VENDOR_ID_ACCESIO,
2272 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
2273 .subvendor = PCI_ANY_ID,
2274 .subdevice = PCI_ANY_ID,
2275 .setup = pci_pericom_setup_four_at_eight,
2276 },
2277 {
2278 .vendor = PCI_VENDOR_ID_ACCESIO,
2279 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
2280 .subvendor = PCI_ANY_ID,
2281 .subdevice = PCI_ANY_ID,
2282 .setup = pci_pericom_setup_four_at_eight,
2283 },
2284 {
2285 .vendor = PCI_VENDOR_ID_ACCESIO,
2286 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
2287 .subvendor = PCI_ANY_ID,
2288 .subdevice = PCI_ANY_ID,
2289 .setup = pci_pericom_setup_four_at_eight,
2290 },
2291 {
2292 .vendor = PCI_VENDOR_ID_ACCESIO,
2293 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
2294 .subvendor = PCI_ANY_ID,
2295 .subdevice = PCI_ANY_ID,
2296 .setup = pci_pericom_setup_four_at_eight,
2297 },
2298 {
2299 .vendor = PCI_VENDOR_ID_ACCESIO,
2300 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
2301 .subvendor = PCI_ANY_ID,
2302 .subdevice = PCI_ANY_ID,
2303 .setup = pci_pericom_setup_four_at_eight,
2304 },
2305 {
2306 .vendor = PCI_VENDOR_ID_ACCESIO,
2307 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
2308 .subvendor = PCI_ANY_ID,
2309 .subdevice = PCI_ANY_ID,
2310 .setup = pci_pericom_setup_four_at_eight,
2311 },
2312 {
2313 .vendor = PCI_VENDOR_ID_ACCESIO,
2314 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
2315 .subvendor = PCI_ANY_ID,
2316 .subdevice = PCI_ANY_ID,
2317 .setup = pci_pericom_setup_four_at_eight,
2318 },
2319 {
2320 .vendor = PCI_VENDOR_ID_ACCESIO,
2321 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
2322 .subvendor = PCI_ANY_ID,
2323 .subdevice = PCI_ANY_ID,
2324 .setup = pci_pericom_setup_four_at_eight,
2325 },
2326 {
2327 .vendor = PCI_VENDOR_ID_ACCESIO,
2328 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
2329 .subvendor = PCI_ANY_ID,
2330 .subdevice = PCI_ANY_ID,
2331 .setup = pci_pericom_setup_four_at_eight,
2332 },
2333 {
2334 .vendor = PCI_VENDOR_ID_ACCESIO,
2335 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
2336 .subvendor = PCI_ANY_ID,
2337 .subdevice = PCI_ANY_ID,
2338 .setup = pci_pericom_setup_four_at_eight,
2339 },
2340 {
2341 .vendor = PCI_VENDOR_ID_ACCESIO,
2342 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
2343 .subvendor = PCI_ANY_ID,
2344 .subdevice = PCI_ANY_ID,
2345 .setup = pci_pericom_setup_four_at_eight,
2346 },
2347 {
2348 .vendor = PCI_VENDOR_ID_ACCESIO,
2349 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
2350 .subvendor = PCI_ANY_ID,
2351 .subdevice = PCI_ANY_ID,
2352 .setup = pci_pericom_setup_four_at_eight,
2353 },
2354 {
2355 .vendor = PCI_VENDOR_ID_ACCESIO,
2356 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
2357 .subvendor = PCI_ANY_ID,
2358 .subdevice = PCI_ANY_ID,
2359 .setup = pci_pericom_setup_four_at_eight,
2360 },
2361 {
2362 .vendor = PCI_VENDOR_ID_ACCESIO,
2363 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
2364 .subvendor = PCI_ANY_ID,
2365 .subdevice = PCI_ANY_ID,
2366 .setup = pci_pericom_setup_four_at_eight,
2367 },
2368 {
2369 .vendor = PCI_VENDOR_ID_ACCESIO,
2370 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
2371 .subvendor = PCI_ANY_ID,
2372 .subdevice = PCI_ANY_ID,
2373 .setup = pci_pericom_setup_four_at_eight,
2374 },
2375 {
2376 .vendor = PCI_VENDOR_ID_ACCESIO,
2377 .device = PCI_ANY_ID,
2378 .subvendor = PCI_ANY_ID,
2379 .subdevice = PCI_ANY_ID,
2380 .setup = pci_pericom_setup,
2381 }, /*
2382 * SBS Technologies, Inc., PMC-OCTALPRO 232
2383 */
2384 {
2385 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2386 .device = PCI_DEVICE_ID_OCTPRO,
2387 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2388 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2389 .init = sbs_init,
2390 .setup = sbs_setup,
2391 .exit = sbs_exit,
2392 },
2393 /*
2394 * SBS Technologies, Inc., PMC-OCTALPRO 422
2395 */
2396 {
2397 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2398 .device = PCI_DEVICE_ID_OCTPRO,
2399 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2400 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2401 .init = sbs_init,
2402 .setup = sbs_setup,
2403 .exit = sbs_exit,
2404 },
2405 /*
2406 * SBS Technologies, Inc., P-Octal 232
2407 */
2408 {
2409 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2410 .device = PCI_DEVICE_ID_OCTPRO,
2411 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2412 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2413 .init = sbs_init,
2414 .setup = sbs_setup,
2415 .exit = sbs_exit,
2416 },
2417 /*
2418 * SBS Technologies, Inc., P-Octal 422
2419 */
2420 {
2421 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2422 .device = PCI_DEVICE_ID_OCTPRO,
2423 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2424 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2425 .init = sbs_init,
2426 .setup = sbs_setup,
2427 .exit = sbs_exit,
2428 },
2429 /*
2430 * SIIG cards - these may be called via parport_serial
2431 */
2432 {
2433 .vendor = PCI_VENDOR_ID_SIIG,
2434 .device = PCI_ANY_ID,
2435 .subvendor = PCI_ANY_ID,
2436 .subdevice = PCI_ANY_ID,
2437 .init = pci_siig_init,
2438 .setup = pci_siig_setup,
2439 },
2440 /*
2441 * Titan cards
2442 */
2443 {
2444 .vendor = PCI_VENDOR_ID_TITAN,
2445 .device = PCI_DEVICE_ID_TITAN_400L,
2446 .subvendor = PCI_ANY_ID,
2447 .subdevice = PCI_ANY_ID,
2448 .setup = titan_400l_800l_setup,
2449 },
2450 {
2451 .vendor = PCI_VENDOR_ID_TITAN,
2452 .device = PCI_DEVICE_ID_TITAN_800L,
2453 .subvendor = PCI_ANY_ID,
2454 .subdevice = PCI_ANY_ID,
2455 .setup = titan_400l_800l_setup,
2456 },
2457 /*
2458 * Timedia cards
2459 */
2460 {
2461 .vendor = PCI_VENDOR_ID_TIMEDIA,
2462 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2463 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2464 .subdevice = PCI_ANY_ID,
2465 .probe = pci_timedia_probe,
2466 .init = pci_timedia_init,
2467 .setup = pci_timedia_setup,
2468 },
2469 {
2470 .vendor = PCI_VENDOR_ID_TIMEDIA,
2471 .device = PCI_ANY_ID,
2472 .subvendor = PCI_ANY_ID,
2473 .subdevice = PCI_ANY_ID,
2474 .setup = pci_timedia_setup,
2475 },
2476 /*
2477 * Sunix PCI serial boards
2478 */
2479 {
2480 .vendor = PCI_VENDOR_ID_SUNIX,
2481 .device = PCI_DEVICE_ID_SUNIX_1999,
2482 .subvendor = PCI_VENDOR_ID_SUNIX,
2483 .subdevice = PCI_ANY_ID,
2484 .setup = pci_sunix_setup,
2485 },
2486 /*
2487 * Xircom cards
2488 */
2489 {
2490 .vendor = PCI_VENDOR_ID_XIRCOM,
2491 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2492 .subvendor = PCI_ANY_ID,
2493 .subdevice = PCI_ANY_ID,
2494 .init = pci_xircom_init,
2495 .setup = pci_default_setup,
2496 },
2497 /*
2498 * Netmos cards - these may be called via parport_serial
2499 */
2500 {
2501 .vendor = PCI_VENDOR_ID_NETMOS,
2502 .device = PCI_ANY_ID,
2503 .subvendor = PCI_ANY_ID,
2504 .subdevice = PCI_ANY_ID,
2505 .init = pci_netmos_init,
2506 .setup = pci_netmos_9900_setup,
2507 },
2508 /*
2509 * EndRun Technologies
2510 */
2511 {
2512 .vendor = PCI_VENDOR_ID_ENDRUN,
2513 .device = PCI_ANY_ID,
2514 .subvendor = PCI_ANY_ID,
2515 .subdevice = PCI_ANY_ID,
2516 .init = pci_endrun_init,
2517 .setup = pci_default_setup,
2518 },
2519 /*
2520 * For Oxford Semiconductor Tornado based devices
2521 */
2522 {
2523 .vendor = PCI_VENDOR_ID_OXSEMI,
2524 .device = PCI_ANY_ID,
2525 .subvendor = PCI_ANY_ID,
2526 .subdevice = PCI_ANY_ID,
2527 .init = pci_oxsemi_tornado_init,
2528 .setup = pci_default_setup,
2529 },
2530 {
2531 .vendor = PCI_VENDOR_ID_MAINPINE,
2532 .device = PCI_ANY_ID,
2533 .subvendor = PCI_ANY_ID,
2534 .subdevice = PCI_ANY_ID,
2535 .init = pci_oxsemi_tornado_init,
2536 .setup = pci_default_setup,
2537 },
2538 {
2539 .vendor = PCI_VENDOR_ID_DIGI,
2540 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2541 .subvendor = PCI_SUBVENDOR_ID_IBM,
2542 .subdevice = PCI_ANY_ID,
2543 .init = pci_oxsemi_tornado_init,
2544 .setup = pci_default_setup,
2545 },
2546 {
2547 .vendor = PCI_VENDOR_ID_INTEL,
2548 .device = 0x8811,
2549 .subvendor = PCI_ANY_ID,
2550 .subdevice = PCI_ANY_ID,
2551 .init = pci_eg20t_init,
2552 .setup = pci_default_setup,
2553 },
2554 {
2555 .vendor = PCI_VENDOR_ID_INTEL,
2556 .device = 0x8812,
2557 .subvendor = PCI_ANY_ID,
2558 .subdevice = PCI_ANY_ID,
2559 .init = pci_eg20t_init,
2560 .setup = pci_default_setup,
2561 },
2562 {
2563 .vendor = PCI_VENDOR_ID_INTEL,
2564 .device = 0x8813,
2565 .subvendor = PCI_ANY_ID,
2566 .subdevice = PCI_ANY_ID,
2567 .init = pci_eg20t_init,
2568 .setup = pci_default_setup,
2569 },
2570 {
2571 .vendor = PCI_VENDOR_ID_INTEL,
2572 .device = 0x8814,
2573 .subvendor = PCI_ANY_ID,
2574 .subdevice = PCI_ANY_ID,
2575 .init = pci_eg20t_init,
2576 .setup = pci_default_setup,
2577 },
2578 {
2579 .vendor = 0x10DB,
2580 .device = 0x8027,
2581 .subvendor = PCI_ANY_ID,
2582 .subdevice = PCI_ANY_ID,
2583 .init = pci_eg20t_init,
2584 .setup = pci_default_setup,
2585 },
2586 {
2587 .vendor = 0x10DB,
2588 .device = 0x8028,
2589 .subvendor = PCI_ANY_ID,
2590 .subdevice = PCI_ANY_ID,
2591 .init = pci_eg20t_init,
2592 .setup = pci_default_setup,
2593 },
2594 {
2595 .vendor = 0x10DB,
2596 .device = 0x8029,
2597 .subvendor = PCI_ANY_ID,
2598 .subdevice = PCI_ANY_ID,
2599 .init = pci_eg20t_init,
2600 .setup = pci_default_setup,
2601 },
2602 {
2603 .vendor = 0x10DB,
2604 .device = 0x800C,
2605 .subvendor = PCI_ANY_ID,
2606 .subdevice = PCI_ANY_ID,
2607 .init = pci_eg20t_init,
2608 .setup = pci_default_setup,
2609 },
2610 {
2611 .vendor = 0x10DB,
2612 .device = 0x800D,
2613 .subvendor = PCI_ANY_ID,
2614 .subdevice = PCI_ANY_ID,
2615 .init = pci_eg20t_init,
2616 .setup = pci_default_setup,
2617 },
2618 /*
2619 * Cronyx Omega PCI (PLX-chip based)
2620 */
2621 {
2622 .vendor = PCI_VENDOR_ID_PLX,
2623 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2624 .subvendor = PCI_ANY_ID,
2625 .subdevice = PCI_ANY_ID,
2626 .setup = pci_omegapci_setup,
2627 },
2628 /* WCH CH353 1S1P card (16550 clone) */
2629 {
2630 .vendor = PCI_VENDOR_ID_WCH,
2631 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2632 .subvendor = PCI_ANY_ID,
2633 .subdevice = PCI_ANY_ID,
2634 .setup = pci_wch_ch353_setup,
2635 },
2636 /* WCH CH353 2S1P card (16550 clone) */
2637 {
2638 .vendor = PCI_VENDOR_ID_WCH,
2639 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2640 .subvendor = PCI_ANY_ID,
2641 .subdevice = PCI_ANY_ID,
2642 .setup = pci_wch_ch353_setup,
2643 },
2644 /* WCH CH353 4S card (16550 clone) */
2645 {
2646 .vendor = PCI_VENDOR_ID_WCH,
2647 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2648 .subvendor = PCI_ANY_ID,
2649 .subdevice = PCI_ANY_ID,
2650 .setup = pci_wch_ch353_setup,
2651 },
2652 /* WCH CH353 2S1PF card (16550 clone) */
2653 {
2654 .vendor = PCI_VENDOR_ID_WCH,
2655 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2656 .subvendor = PCI_ANY_ID,
2657 .subdevice = PCI_ANY_ID,
2658 .setup = pci_wch_ch353_setup,
2659 },
2660 /* WCH CH352 2S card (16550 clone) */
2661 {
2662 .vendor = PCI_VENDOR_ID_WCH,
2663 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2664 .subvendor = PCI_ANY_ID,
2665 .subdevice = PCI_ANY_ID,
2666 .setup = pci_wch_ch353_setup,
2667 },
2668 /* WCH CH355 4S card (16550 clone) */
2669 {
2670 .vendor = PCI_VENDOR_ID_WCH,
2671 .device = PCI_DEVICE_ID_WCH_CH355_4S,
2672 .subvendor = PCI_ANY_ID,
2673 .subdevice = PCI_ANY_ID,
2674 .setup = pci_wch_ch355_setup,
2675 },
2676 /* WCH CH382 2S card (16850 clone) */
2677 {
2678 .vendor = PCIE_VENDOR_ID_WCH,
2679 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2680 .subvendor = PCI_ANY_ID,
2681 .subdevice = PCI_ANY_ID,
2682 .setup = pci_wch_ch38x_setup,
2683 },
2684 /* WCH CH382 2S1P card (16850 clone) */
2685 {
2686 .vendor = PCIE_VENDOR_ID_WCH,
2687 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2688 .subvendor = PCI_ANY_ID,
2689 .subdevice = PCI_ANY_ID,
2690 .setup = pci_wch_ch38x_setup,
2691 },
2692 /* WCH CH384 4S card (16850 clone) */
2693 {
2694 .vendor = PCIE_VENDOR_ID_WCH,
2695 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2696 .subvendor = PCI_ANY_ID,
2697 .subdevice = PCI_ANY_ID,
2698 .setup = pci_wch_ch38x_setup,
2699 },
2700 /* WCH CH384 8S card (16850 clone) */
2701 {
2702 .vendor = PCIE_VENDOR_ID_WCH,
2703 .device = PCIE_DEVICE_ID_WCH_CH384_8S,
2704 .subvendor = PCI_ANY_ID,
2705 .subdevice = PCI_ANY_ID,
2706 .init = pci_wch_ch38x_init,
2707 .exit = pci_wch_ch38x_exit,
2708 .setup = pci_wch_ch38x_setup,
2709 },
2710 /*
2711 * ASIX devices with FIFO bug
2712 */
2713 {
2714 .vendor = PCI_VENDOR_ID_ASIX,
2715 .device = PCI_ANY_ID,
2716 .subvendor = PCI_ANY_ID,
2717 .subdevice = PCI_ANY_ID,
2718 .setup = pci_asix_setup,
2719 },
2720 /*
2721 * Broadcom TruManage (NetXtreme)
2722 */
2723 {
2724 .vendor = PCI_VENDOR_ID_BROADCOM,
2725 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2726 .subvendor = PCI_ANY_ID,
2727 .subdevice = PCI_ANY_ID,
2728 .setup = pci_brcm_trumanage_setup,
2729 },
2730 {
2731 .vendor = 0x1c29,
2732 .device = 0x1104,
2733 .subvendor = PCI_ANY_ID,
2734 .subdevice = PCI_ANY_ID,
2735 .setup = pci_fintek_setup,
2736 .init = pci_fintek_init,
2737 },
2738 {
2739 .vendor = 0x1c29,
2740 .device = 0x1108,
2741 .subvendor = PCI_ANY_ID,
2742 .subdevice = PCI_ANY_ID,
2743 .setup = pci_fintek_setup,
2744 .init = pci_fintek_init,
2745 },
2746 {
2747 .vendor = 0x1c29,
2748 .device = 0x1112,
2749 .subvendor = PCI_ANY_ID,
2750 .subdevice = PCI_ANY_ID,
2751 .setup = pci_fintek_setup,
2752 .init = pci_fintek_init,
2753 },
2754 /*
2755 * MOXA
2756 */
2757 {
2758 .vendor = PCI_VENDOR_ID_MOXA,
2759 .device = PCI_ANY_ID,
2760 .subvendor = PCI_ANY_ID,
2761 .subdevice = PCI_ANY_ID,
2762 .setup = pci_moxa_setup,
2763 },
2764 {
2765 .vendor = 0x1c29,
2766 .device = 0x1204,
2767 .subvendor = PCI_ANY_ID,
2768 .subdevice = PCI_ANY_ID,
2769 .setup = pci_fintek_f815xxa_setup,
2770 .init = pci_fintek_f815xxa_init,
2771 },
2772 {
2773 .vendor = 0x1c29,
2774 .device = 0x1208,
2775 .subvendor = PCI_ANY_ID,
2776 .subdevice = PCI_ANY_ID,
2777 .setup = pci_fintek_f815xxa_setup,
2778 .init = pci_fintek_f815xxa_init,
2779 },
2780 {
2781 .vendor = 0x1c29,
2782 .device = 0x1212,
2783 .subvendor = PCI_ANY_ID,
2784 .subdevice = PCI_ANY_ID,
2785 .setup = pci_fintek_f815xxa_setup,
2786 .init = pci_fintek_f815xxa_init,
2787 },
2788
2789 /*
2790 * Default "match everything" terminator entry
2791 */
2792 {
2793 .vendor = PCI_ANY_ID,
2794 .device = PCI_ANY_ID,
2795 .subvendor = PCI_ANY_ID,
2796 .subdevice = PCI_ANY_ID,
2797 .setup = pci_default_setup,
2798 }
2799 };
2800
2801 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2802 {
2803 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2804 }
2805
2806 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2807 {
2808 struct pci_serial_quirk *quirk;
2809
2810 for (quirk = pci_serial_quirks; ; quirk++)
2811 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2812 quirk_id_matches(quirk->device, dev->device) &&
2813 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2814 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2815 break;
2816 return quirk;
2817 }
2818
2819 /*
2820 * This is the configuration table for all of the PCI serial boards
2821 * which we support. It is directly indexed by the pci_board_num_t enum
2822 * value, which is encoded in the pci_device_id PCI probe table's
2823 * driver_data member.
2824 *
2825 * The makeup of these names are:
2826 * pbn_bn{_bt}_n_baud{_offsetinhex}
2827 *
2828 * bn = PCI BAR number
2829 * bt = Index using PCI BARs
2830 * n = number of serial ports
2831 * baud = baud rate
2832 * offsetinhex = offset for each sequential port (in hex)
2833 *
2834 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2835 *
2836 * Please note: in theory if n = 1, _bt infix should make no difference.
2837 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2838 */
2839 enum pci_board_num_t {
2840 pbn_default = 0,
2841
2842 pbn_b0_1_115200,
2843 pbn_b0_2_115200,
2844 pbn_b0_4_115200,
2845 pbn_b0_5_115200,
2846 pbn_b0_8_115200,
2847
2848 pbn_b0_1_921600,
2849 pbn_b0_2_921600,
2850 pbn_b0_4_921600,
2851
2852 pbn_b0_2_1130000,
2853
2854 pbn_b0_4_1152000,
2855
2856 pbn_b0_4_1250000,
2857
2858 pbn_b0_2_1843200,
2859 pbn_b0_4_1843200,
2860
2861 pbn_b0_1_3906250,
2862
2863 pbn_b0_bt_1_115200,
2864 pbn_b0_bt_2_115200,
2865 pbn_b0_bt_4_115200,
2866 pbn_b0_bt_8_115200,
2867
2868 pbn_b0_bt_1_460800,
2869 pbn_b0_bt_2_460800,
2870 pbn_b0_bt_4_460800,
2871
2872 pbn_b0_bt_1_921600,
2873 pbn_b0_bt_2_921600,
2874 pbn_b0_bt_4_921600,
2875 pbn_b0_bt_8_921600,
2876
2877 pbn_b1_1_115200,
2878 pbn_b1_2_115200,
2879 pbn_b1_4_115200,
2880 pbn_b1_8_115200,
2881 pbn_b1_16_115200,
2882
2883 pbn_b1_1_921600,
2884 pbn_b1_2_921600,
2885 pbn_b1_4_921600,
2886 pbn_b1_8_921600,
2887
2888 pbn_b1_2_1250000,
2889
2890 pbn_b1_bt_1_115200,
2891 pbn_b1_bt_2_115200,
2892 pbn_b1_bt_4_115200,
2893
2894 pbn_b1_bt_2_921600,
2895
2896 pbn_b1_1_1382400,
2897 pbn_b1_2_1382400,
2898 pbn_b1_4_1382400,
2899 pbn_b1_8_1382400,
2900
2901 pbn_b2_1_115200,
2902 pbn_b2_2_115200,
2903 pbn_b2_4_115200,
2904 pbn_b2_8_115200,
2905
2906 pbn_b2_1_460800,
2907 pbn_b2_4_460800,
2908 pbn_b2_8_460800,
2909 pbn_b2_16_460800,
2910
2911 pbn_b2_1_921600,
2912 pbn_b2_4_921600,
2913 pbn_b2_8_921600,
2914
2915 pbn_b2_8_1152000,
2916
2917 pbn_b2_bt_1_115200,
2918 pbn_b2_bt_2_115200,
2919 pbn_b2_bt_4_115200,
2920
2921 pbn_b2_bt_2_921600,
2922 pbn_b2_bt_4_921600,
2923
2924 pbn_b3_2_115200,
2925 pbn_b3_4_115200,
2926 pbn_b3_8_115200,
2927
2928 pbn_b4_bt_2_921600,
2929 pbn_b4_bt_4_921600,
2930 pbn_b4_bt_8_921600,
2931
2932 /*
2933 * Board-specific versions.
2934 */
2935 pbn_panacom,
2936 pbn_panacom2,
2937 pbn_panacom4,
2938 pbn_plx_romulus,
2939 pbn_endrun_2_4000000,
2940 pbn_oxsemi,
2941 pbn_oxsemi_1_3906250,
2942 pbn_oxsemi_2_3906250,
2943 pbn_oxsemi_4_3906250,
2944 pbn_oxsemi_8_3906250,
2945 pbn_intel_i960,
2946 pbn_sgi_ioc3,
2947 pbn_computone_4,
2948 pbn_computone_6,
2949 pbn_computone_8,
2950 pbn_sbsxrsio,
2951 pbn_pasemi_1682M,
2952 pbn_ni8430_2,
2953 pbn_ni8430_4,
2954 pbn_ni8430_8,
2955 pbn_ni8430_16,
2956 pbn_ADDIDATA_PCIe_1_3906250,
2957 pbn_ADDIDATA_PCIe_2_3906250,
2958 pbn_ADDIDATA_PCIe_4_3906250,
2959 pbn_ADDIDATA_PCIe_8_3906250,
2960 pbn_ce4100_1_115200,
2961 pbn_omegapci,
2962 pbn_NETMOS9900_2s_115200,
2963 pbn_brcm_trumanage,
2964 pbn_fintek_4,
2965 pbn_fintek_8,
2966 pbn_fintek_12,
2967 pbn_fintek_F81504A,
2968 pbn_fintek_F81508A,
2969 pbn_fintek_F81512A,
2970 pbn_wch382_2,
2971 pbn_wch384_4,
2972 pbn_wch384_8,
2973 pbn_pericom_PI7C9X7951,
2974 pbn_pericom_PI7C9X7952,
2975 pbn_pericom_PI7C9X7954,
2976 pbn_pericom_PI7C9X7958,
2977 pbn_sunix_pci_1s,
2978 pbn_sunix_pci_2s,
2979 pbn_sunix_pci_4s,
2980 pbn_sunix_pci_8s,
2981 pbn_sunix_pci_16s,
2982 pbn_titan_1_4000000,
2983 pbn_titan_2_4000000,
2984 pbn_titan_4_4000000,
2985 pbn_titan_8_4000000,
2986 pbn_moxa8250_2p,
2987 pbn_moxa8250_4p,
2988 pbn_moxa8250_8p,
2989 };
2990
2991 /*
2992 * uart_offset - the space between channels
2993 * reg_shift - describes how the UART registers are mapped
2994 * to PCI memory by the card.
2995 * For example IER register on SBS, Inc. PMC-OctPro is located at
2996 * offset 0x10 from the UART base, while UART_IER is defined as 1
2997 * in include/linux/serial_reg.h,
2998 * see first lines of serial_in() and serial_out() in 8250.c
2999 */
3000
3001 static struct pciserial_board pci_boards[] = {
3002 [pbn_default] = {
3003 .flags = FL_BASE0,
3004 .num_ports = 1,
3005 .base_baud = 115200,
3006 .uart_offset = 8,
3007 },
3008 [pbn_b0_1_115200] = {
3009 .flags = FL_BASE0,
3010 .num_ports = 1,
3011 .base_baud = 115200,
3012 .uart_offset = 8,
3013 },
3014 [pbn_b0_2_115200] = {
3015 .flags = FL_BASE0,
3016 .num_ports = 2,
3017 .base_baud = 115200,
3018 .uart_offset = 8,
3019 },
3020 [pbn_b0_4_115200] = {
3021 .flags = FL_BASE0,
3022 .num_ports = 4,
3023 .base_baud = 115200,
3024 .uart_offset = 8,
3025 },
3026 [pbn_b0_5_115200] = {
3027 .flags = FL_BASE0,
3028 .num_ports = 5,
3029 .base_baud = 115200,
3030 .uart_offset = 8,
3031 },
3032 [pbn_b0_8_115200] = {
3033 .flags = FL_BASE0,
3034 .num_ports = 8,
3035 .base_baud = 115200,
3036 .uart_offset = 8,
3037 },
3038 [pbn_b0_1_921600] = {
3039 .flags = FL_BASE0,
3040 .num_ports = 1,
3041 .base_baud = 921600,
3042 .uart_offset = 8,
3043 },
3044 [pbn_b0_2_921600] = {
3045 .flags = FL_BASE0,
3046 .num_ports = 2,
3047 .base_baud = 921600,
3048 .uart_offset = 8,
3049 },
3050 [pbn_b0_4_921600] = {
3051 .flags = FL_BASE0,
3052 .num_ports = 4,
3053 .base_baud = 921600,
3054 .uart_offset = 8,
3055 },
3056
3057 [pbn_b0_2_1130000] = {
3058 .flags = FL_BASE0,
3059 .num_ports = 2,
3060 .base_baud = 1130000,
3061 .uart_offset = 8,
3062 },
3063
3064 [pbn_b0_4_1152000] = {
3065 .flags = FL_BASE0,
3066 .num_ports = 4,
3067 .base_baud = 1152000,
3068 .uart_offset = 8,
3069 },
3070
3071 [pbn_b0_4_1250000] = {
3072 .flags = FL_BASE0,
3073 .num_ports = 4,
3074 .base_baud = 1250000,
3075 .uart_offset = 8,
3076 },
3077
3078 [pbn_b0_2_1843200] = {
3079 .flags = FL_BASE0,
3080 .num_ports = 2,
3081 .base_baud = 1843200,
3082 .uart_offset = 8,
3083 },
3084 [pbn_b0_4_1843200] = {
3085 .flags = FL_BASE0,
3086 .num_ports = 4,
3087 .base_baud = 1843200,
3088 .uart_offset = 8,
3089 },
3090
3091 [pbn_b0_1_3906250] = {
3092 .flags = FL_BASE0,
3093 .num_ports = 1,
3094 .base_baud = 3906250,
3095 .uart_offset = 8,
3096 },
3097
3098 [pbn_b0_bt_1_115200] = {
3099 .flags = FL_BASE0|FL_BASE_BARS,
3100 .num_ports = 1,
3101 .base_baud = 115200,
3102 .uart_offset = 8,
3103 },
3104 [pbn_b0_bt_2_115200] = {
3105 .flags = FL_BASE0|FL_BASE_BARS,
3106 .num_ports = 2,
3107 .base_baud = 115200,
3108 .uart_offset = 8,
3109 },
3110 [pbn_b0_bt_4_115200] = {
3111 .flags = FL_BASE0|FL_BASE_BARS,
3112 .num_ports = 4,
3113 .base_baud = 115200,
3114 .uart_offset = 8,
3115 },
3116 [pbn_b0_bt_8_115200] = {
3117 .flags = FL_BASE0|FL_BASE_BARS,
3118 .num_ports = 8,
3119 .base_baud = 115200,
3120 .uart_offset = 8,
3121 },
3122
3123 [pbn_b0_bt_1_460800] = {
3124 .flags = FL_BASE0|FL_BASE_BARS,
3125 .num_ports = 1,
3126 .base_baud = 460800,
3127 .uart_offset = 8,
3128 },
3129 [pbn_b0_bt_2_460800] = {
3130 .flags = FL_BASE0|FL_BASE_BARS,
3131 .num_ports = 2,
3132 .base_baud = 460800,
3133 .uart_offset = 8,
3134 },
3135 [pbn_b0_bt_4_460800] = {
3136 .flags = FL_BASE0|FL_BASE_BARS,
3137 .num_ports = 4,
3138 .base_baud = 460800,
3139 .uart_offset = 8,
3140 },
3141
3142 [pbn_b0_bt_1_921600] = {
3143 .flags = FL_BASE0|FL_BASE_BARS,
3144 .num_ports = 1,
3145 .base_baud = 921600,
3146 .uart_offset = 8,
3147 },
3148 [pbn_b0_bt_2_921600] = {
3149 .flags = FL_BASE0|FL_BASE_BARS,
3150 .num_ports = 2,
3151 .base_baud = 921600,
3152 .uart_offset = 8,
3153 },
3154 [pbn_b0_bt_4_921600] = {
3155 .flags = FL_BASE0|FL_BASE_BARS,
3156 .num_ports = 4,
3157 .base_baud = 921600,
3158 .uart_offset = 8,
3159 },
3160 [pbn_b0_bt_8_921600] = {
3161 .flags = FL_BASE0|FL_BASE_BARS,
3162 .num_ports = 8,
3163 .base_baud = 921600,
3164 .uart_offset = 8,
3165 },
3166
3167 [pbn_b1_1_115200] = {
3168 .flags = FL_BASE1,
3169 .num_ports = 1,
3170 .base_baud = 115200,
3171 .uart_offset = 8,
3172 },
3173 [pbn_b1_2_115200] = {
3174 .flags = FL_BASE1,
3175 .num_ports = 2,
3176 .base_baud = 115200,
3177 .uart_offset = 8,
3178 },
3179 [pbn_b1_4_115200] = {
3180 .flags = FL_BASE1,
3181 .num_ports = 4,
3182 .base_baud = 115200,
3183 .uart_offset = 8,
3184 },
3185 [pbn_b1_8_115200] = {
3186 .flags = FL_BASE1,
3187 .num_ports = 8,
3188 .base_baud = 115200,
3189 .uart_offset = 8,
3190 },
3191 [pbn_b1_16_115200] = {
3192 .flags = FL_BASE1,
3193 .num_ports = 16,
3194 .base_baud = 115200,
3195 .uart_offset = 8,
3196 },
3197
3198 [pbn_b1_1_921600] = {
3199 .flags = FL_BASE1,
3200 .num_ports = 1,
3201 .base_baud = 921600,
3202 .uart_offset = 8,
3203 },
3204 [pbn_b1_2_921600] = {
3205 .flags = FL_BASE1,
3206 .num_ports = 2,
3207 .base_baud = 921600,
3208 .uart_offset = 8,
3209 },
3210 [pbn_b1_4_921600] = {
3211 .flags = FL_BASE1,
3212 .num_ports = 4,
3213 .base_baud = 921600,
3214 .uart_offset = 8,
3215 },
3216 [pbn_b1_8_921600] = {
3217 .flags = FL_BASE1,
3218 .num_ports = 8,
3219 .base_baud = 921600,
3220 .uart_offset = 8,
3221 },
3222 [pbn_b1_2_1250000] = {
3223 .flags = FL_BASE1,
3224 .num_ports = 2,
3225 .base_baud = 1250000,
3226 .uart_offset = 8,
3227 },
3228
3229 [pbn_b1_bt_1_115200] = {
3230 .flags = FL_BASE1|FL_BASE_BARS,
3231 .num_ports = 1,
3232 .base_baud = 115200,
3233 .uart_offset = 8,
3234 },
3235 [pbn_b1_bt_2_115200] = {
3236 .flags = FL_BASE1|FL_BASE_BARS,
3237 .num_ports = 2,
3238 .base_baud = 115200,
3239 .uart_offset = 8,
3240 },
3241 [pbn_b1_bt_4_115200] = {
3242 .flags = FL_BASE1|FL_BASE_BARS,
3243 .num_ports = 4,
3244 .base_baud = 115200,
3245 .uart_offset = 8,
3246 },
3247
3248 [pbn_b1_bt_2_921600] = {
3249 .flags = FL_BASE1|FL_BASE_BARS,
3250 .num_ports = 2,
3251 .base_baud = 921600,
3252 .uart_offset = 8,
3253 },
3254
3255 [pbn_b1_1_1382400] = {
3256 .flags = FL_BASE1,
3257 .num_ports = 1,
3258 .base_baud = 1382400,
3259 .uart_offset = 8,
3260 },
3261 [pbn_b1_2_1382400] = {
3262 .flags = FL_BASE1,
3263 .num_ports = 2,
3264 .base_baud = 1382400,
3265 .uart_offset = 8,
3266 },
3267 [pbn_b1_4_1382400] = {
3268 .flags = FL_BASE1,
3269 .num_ports = 4,
3270 .base_baud = 1382400,
3271 .uart_offset = 8,
3272 },
3273 [pbn_b1_8_1382400] = {
3274 .flags = FL_BASE1,
3275 .num_ports = 8,
3276 .base_baud = 1382400,
3277 .uart_offset = 8,
3278 },
3279
3280 [pbn_b2_1_115200] = {
3281 .flags = FL_BASE2,
3282 .num_ports = 1,
3283 .base_baud = 115200,
3284 .uart_offset = 8,
3285 },
3286 [pbn_b2_2_115200] = {
3287 .flags = FL_BASE2,
3288 .num_ports = 2,
3289 .base_baud = 115200,
3290 .uart_offset = 8,
3291 },
3292 [pbn_b2_4_115200] = {
3293 .flags = FL_BASE2,
3294 .num_ports = 4,
3295 .base_baud = 115200,
3296 .uart_offset = 8,
3297 },
3298 [pbn_b2_8_115200] = {
3299 .flags = FL_BASE2,
3300 .num_ports = 8,
3301 .base_baud = 115200,
3302 .uart_offset = 8,
3303 },
3304
3305 [pbn_b2_1_460800] = {
3306 .flags = FL_BASE2,
3307 .num_ports = 1,
3308 .base_baud = 460800,
3309 .uart_offset = 8,
3310 },
3311 [pbn_b2_4_460800] = {
3312 .flags = FL_BASE2,
3313 .num_ports = 4,
3314 .base_baud = 460800,
3315 .uart_offset = 8,
3316 },
3317 [pbn_b2_8_460800] = {
3318 .flags = FL_BASE2,
3319 .num_ports = 8,
3320 .base_baud = 460800,
3321 .uart_offset = 8,
3322 },
3323 [pbn_b2_16_460800] = {
3324 .flags = FL_BASE2,
3325 .num_ports = 16,
3326 .base_baud = 460800,
3327 .uart_offset = 8,
3328 },
3329
3330 [pbn_b2_1_921600] = {
3331 .flags = FL_BASE2,
3332 .num_ports = 1,
3333 .base_baud = 921600,
3334 .uart_offset = 8,
3335 },
3336 [pbn_b2_4_921600] = {
3337 .flags = FL_BASE2,
3338 .num_ports = 4,
3339 .base_baud = 921600,
3340 .uart_offset = 8,
3341 },
3342 [pbn_b2_8_921600] = {
3343 .flags = FL_BASE2,
3344 .num_ports = 8,
3345 .base_baud = 921600,
3346 .uart_offset = 8,
3347 },
3348
3349 [pbn_b2_8_1152000] = {
3350 .flags = FL_BASE2,
3351 .num_ports = 8,
3352 .base_baud = 1152000,
3353 .uart_offset = 8,
3354 },
3355
3356 [pbn_b2_bt_1_115200] = {
3357 .flags = FL_BASE2|FL_BASE_BARS,
3358 .num_ports = 1,
3359 .base_baud = 115200,
3360 .uart_offset = 8,
3361 },
3362 [pbn_b2_bt_2_115200] = {
3363 .flags = FL_BASE2|FL_BASE_BARS,
3364 .num_ports = 2,
3365 .base_baud = 115200,
3366 .uart_offset = 8,
3367 },
3368 [pbn_b2_bt_4_115200] = {
3369 .flags = FL_BASE2|FL_BASE_BARS,
3370 .num_ports = 4,
3371 .base_baud = 115200,
3372 .uart_offset = 8,
3373 },
3374
3375 [pbn_b2_bt_2_921600] = {
3376 .flags = FL_BASE2|FL_BASE_BARS,
3377 .num_ports = 2,
3378 .base_baud = 921600,
3379 .uart_offset = 8,
3380 },
3381 [pbn_b2_bt_4_921600] = {
3382 .flags = FL_BASE2|FL_BASE_BARS,
3383 .num_ports = 4,
3384 .base_baud = 921600,
3385 .uart_offset = 8,
3386 },
3387
3388 [pbn_b3_2_115200] = {
3389 .flags = FL_BASE3,
3390 .num_ports = 2,
3391 .base_baud = 115200,
3392 .uart_offset = 8,
3393 },
3394 [pbn_b3_4_115200] = {
3395 .flags = FL_BASE3,
3396 .num_ports = 4,
3397 .base_baud = 115200,
3398 .uart_offset = 8,
3399 },
3400 [pbn_b3_8_115200] = {
3401 .flags = FL_BASE3,
3402 .num_ports = 8,
3403 .base_baud = 115200,
3404 .uart_offset = 8,
3405 },
3406
3407 [pbn_b4_bt_2_921600] = {
3408 .flags = FL_BASE4,
3409 .num_ports = 2,
3410 .base_baud = 921600,
3411 .uart_offset = 8,
3412 },
3413 [pbn_b4_bt_4_921600] = {
3414 .flags = FL_BASE4,
3415 .num_ports = 4,
3416 .base_baud = 921600,
3417 .uart_offset = 8,
3418 },
3419 [pbn_b4_bt_8_921600] = {
3420 .flags = FL_BASE4,
3421 .num_ports = 8,
3422 .base_baud = 921600,
3423 .uart_offset = 8,
3424 },
3425
3426 /*
3427 * Entries following this are board-specific.
3428 */
3429
3430 /*
3431 * Panacom - IOMEM
3432 */
3433 [pbn_panacom] = {
3434 .flags = FL_BASE2,
3435 .num_ports = 2,
3436 .base_baud = 921600,
3437 .uart_offset = 0x400,
3438 .reg_shift = 7,
3439 },
3440 [pbn_panacom2] = {
3441 .flags = FL_BASE2|FL_BASE_BARS,
3442 .num_ports = 2,
3443 .base_baud = 921600,
3444 .uart_offset = 0x400,
3445 .reg_shift = 7,
3446 },
3447 [pbn_panacom4] = {
3448 .flags = FL_BASE2|FL_BASE_BARS,
3449 .num_ports = 4,
3450 .base_baud = 921600,
3451 .uart_offset = 0x400,
3452 .reg_shift = 7,
3453 },
3454
3455 /* I think this entry is broken - the first_offset looks wrong --rmk */
3456 [pbn_plx_romulus] = {
3457 .flags = FL_BASE2,
3458 .num_ports = 4,
3459 .base_baud = 921600,
3460 .uart_offset = 8 << 2,
3461 .reg_shift = 2,
3462 .first_offset = 0x03,
3463 },
3464
3465 /*
3466 * EndRun Technologies
3467 * Uses the size of PCI Base region 0 to
3468 * signal now many ports are available
3469 * 2 port 952 Uart support
3470 */
3471 [pbn_endrun_2_4000000] = {
3472 .flags = FL_BASE0,
3473 .num_ports = 2,
3474 .base_baud = 4000000,
3475 .uart_offset = 0x200,
3476 .first_offset = 0x1000,
3477 },
3478
3479 /*
3480 * This board uses the size of PCI Base region 0 to
3481 * signal now many ports are available
3482 */
3483 [pbn_oxsemi] = {
3484 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3485 .num_ports = 32,
3486 .base_baud = 115200,
3487 .uart_offset = 8,
3488 },
3489 [pbn_oxsemi_1_3906250] = {
3490 .flags = FL_BASE0,
3491 .num_ports = 1,
3492 .base_baud = 3906250,
3493 .uart_offset = 0x200,
3494 .first_offset = 0x1000,
3495 },
3496 [pbn_oxsemi_2_3906250] = {
3497 .flags = FL_BASE0,
3498 .num_ports = 2,
3499 .base_baud = 3906250,
3500 .uart_offset = 0x200,
3501 .first_offset = 0x1000,
3502 },
3503 [pbn_oxsemi_4_3906250] = {
3504 .flags = FL_BASE0,
3505 .num_ports = 4,
3506 .base_baud = 3906250,
3507 .uart_offset = 0x200,
3508 .first_offset = 0x1000,
3509 },
3510 [pbn_oxsemi_8_3906250] = {
3511 .flags = FL_BASE0,
3512 .num_ports = 8,
3513 .base_baud = 3906250,
3514 .uart_offset = 0x200,
3515 .first_offset = 0x1000,
3516 },
3517
3518
3519 /*
3520 * EKF addition for i960 Boards form EKF with serial port.
3521 * Max 256 ports.
3522 */
3523 [pbn_intel_i960] = {
3524 .flags = FL_BASE0,
3525 .num_ports = 32,
3526 .base_baud = 921600,
3527 .uart_offset = 8 << 2,
3528 .reg_shift = 2,
3529 .first_offset = 0x10000,
3530 },
3531 [pbn_sgi_ioc3] = {
3532 .flags = FL_BASE0|FL_NOIRQ,
3533 .num_ports = 1,
3534 .base_baud = 458333,
3535 .uart_offset = 8,
3536 .reg_shift = 0,
3537 .first_offset = 0x20178,
3538 },
3539
3540 /*
3541 * Computone - uses IOMEM.
3542 */
3543 [pbn_computone_4] = {
3544 .flags = FL_BASE0,
3545 .num_ports = 4,
3546 .base_baud = 921600,
3547 .uart_offset = 0x40,
3548 .reg_shift = 2,
3549 .first_offset = 0x200,
3550 },
3551 [pbn_computone_6] = {
3552 .flags = FL_BASE0,
3553 .num_ports = 6,
3554 .base_baud = 921600,
3555 .uart_offset = 0x40,
3556 .reg_shift = 2,
3557 .first_offset = 0x200,
3558 },
3559 [pbn_computone_8] = {
3560 .flags = FL_BASE0,
3561 .num_ports = 8,
3562 .base_baud = 921600,
3563 .uart_offset = 0x40,
3564 .reg_shift = 2,
3565 .first_offset = 0x200,
3566 },
3567 [pbn_sbsxrsio] = {
3568 .flags = FL_BASE0,
3569 .num_ports = 8,
3570 .base_baud = 460800,
3571 .uart_offset = 256,
3572 .reg_shift = 4,
3573 },
3574 /*
3575 * PA Semi PWRficient PA6T-1682M on-chip UART
3576 */
3577 [pbn_pasemi_1682M] = {
3578 .flags = FL_BASE0,
3579 .num_ports = 1,
3580 .base_baud = 8333333,
3581 },
3582 /*
3583 * National Instruments 843x
3584 */
3585 [pbn_ni8430_16] = {
3586 .flags = FL_BASE0,
3587 .num_ports = 16,
3588 .base_baud = 3686400,
3589 .uart_offset = 0x10,
3590 .first_offset = 0x800,
3591 },
3592 [pbn_ni8430_8] = {
3593 .flags = FL_BASE0,
3594 .num_ports = 8,
3595 .base_baud = 3686400,
3596 .uart_offset = 0x10,
3597 .first_offset = 0x800,
3598 },
3599 [pbn_ni8430_4] = {
3600 .flags = FL_BASE0,
3601 .num_ports = 4,
3602 .base_baud = 3686400,
3603 .uart_offset = 0x10,
3604 .first_offset = 0x800,
3605 },
3606 [pbn_ni8430_2] = {
3607 .flags = FL_BASE0,
3608 .num_ports = 2,
3609 .base_baud = 3686400,
3610 .uart_offset = 0x10,
3611 .first_offset = 0x800,
3612 },
3613 /*
3614 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3615 */
3616 [pbn_ADDIDATA_PCIe_1_3906250] = {
3617 .flags = FL_BASE0,
3618 .num_ports = 1,
3619 .base_baud = 3906250,
3620 .uart_offset = 0x200,
3621 .first_offset = 0x1000,
3622 },
3623 [pbn_ADDIDATA_PCIe_2_3906250] = {
3624 .flags = FL_BASE0,
3625 .num_ports = 2,
3626 .base_baud = 3906250,
3627 .uart_offset = 0x200,
3628 .first_offset = 0x1000,
3629 },
3630 [pbn_ADDIDATA_PCIe_4_3906250] = {
3631 .flags = FL_BASE0,
3632 .num_ports = 4,
3633 .base_baud = 3906250,
3634 .uart_offset = 0x200,
3635 .first_offset = 0x1000,
3636 },
3637 [pbn_ADDIDATA_PCIe_8_3906250] = {
3638 .flags = FL_BASE0,
3639 .num_ports = 8,
3640 .base_baud = 3906250,
3641 .uart_offset = 0x200,
3642 .first_offset = 0x1000,
3643 },
3644 [pbn_ce4100_1_115200] = {
3645 .flags = FL_BASE_BARS,
3646 .num_ports = 2,
3647 .base_baud = 921600,
3648 .reg_shift = 2,
3649 },
3650 [pbn_omegapci] = {
3651 .flags = FL_BASE0,
3652 .num_ports = 8,
3653 .base_baud = 115200,
3654 .uart_offset = 0x200,
3655 },
3656 [pbn_NETMOS9900_2s_115200] = {
3657 .flags = FL_BASE0,
3658 .num_ports = 2,
3659 .base_baud = 115200,
3660 },
3661 [pbn_brcm_trumanage] = {
3662 .flags = FL_BASE0,
3663 .num_ports = 1,
3664 .reg_shift = 2,
3665 .base_baud = 115200,
3666 },
3667 [pbn_fintek_4] = {
3668 .num_ports = 4,
3669 .uart_offset = 8,
3670 .base_baud = 115200,
3671 .first_offset = 0x40,
3672 },
3673 [pbn_fintek_8] = {
3674 .num_ports = 8,
3675 .uart_offset = 8,
3676 .base_baud = 115200,
3677 .first_offset = 0x40,
3678 },
3679 [pbn_fintek_12] = {
3680 .num_ports = 12,
3681 .uart_offset = 8,
3682 .base_baud = 115200,
3683 .first_offset = 0x40,
3684 },
3685 [pbn_fintek_F81504A] = {
3686 .num_ports = 4,
3687 .uart_offset = 8,
3688 .base_baud = 115200,
3689 },
3690 [pbn_fintek_F81508A] = {
3691 .num_ports = 8,
3692 .uart_offset = 8,
3693 .base_baud = 115200,
3694 },
3695 [pbn_fintek_F81512A] = {
3696 .num_ports = 12,
3697 .uart_offset = 8,
3698 .base_baud = 115200,
3699 },
3700 [pbn_wch382_2] = {
3701 .flags = FL_BASE0,
3702 .num_ports = 2,
3703 .base_baud = 115200,
3704 .uart_offset = 8,
3705 .first_offset = 0xC0,
3706 },
3707 [pbn_wch384_4] = {
3708 .flags = FL_BASE0,
3709 .num_ports = 4,
3710 .base_baud = 115200,
3711 .uart_offset = 8,
3712 .first_offset = 0xC0,
3713 },
3714 [pbn_wch384_8] = {
3715 .flags = FL_BASE0,
3716 .num_ports = 8,
3717 .base_baud = 115200,
3718 .uart_offset = 8,
3719 .first_offset = 0x00,
3720 },
3721 /*
3722 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3723 */
3724 [pbn_pericom_PI7C9X7951] = {
3725 .flags = FL_BASE0,
3726 .num_ports = 1,
3727 .base_baud = 921600,
3728 .uart_offset = 0x8,
3729 },
3730 [pbn_pericom_PI7C9X7952] = {
3731 .flags = FL_BASE0,
3732 .num_ports = 2,
3733 .base_baud = 921600,
3734 .uart_offset = 0x8,
3735 },
3736 [pbn_pericom_PI7C9X7954] = {
3737 .flags = FL_BASE0,
3738 .num_ports = 4,
3739 .base_baud = 921600,
3740 .uart_offset = 0x8,
3741 },
3742 [pbn_pericom_PI7C9X7958] = {
3743 .flags = FL_BASE0,
3744 .num_ports = 8,
3745 .base_baud = 921600,
3746 .uart_offset = 0x8,
3747 },
3748 [pbn_sunix_pci_1s] = {
3749 .num_ports = 1,
3750 .base_baud = 921600,
3751 .uart_offset = 0x8,
3752 },
3753 [pbn_sunix_pci_2s] = {
3754 .num_ports = 2,
3755 .base_baud = 921600,
3756 .uart_offset = 0x8,
3757 },
3758 [pbn_sunix_pci_4s] = {
3759 .num_ports = 4,
3760 .base_baud = 921600,
3761 .uart_offset = 0x8,
3762 },
3763 [pbn_sunix_pci_8s] = {
3764 .num_ports = 8,
3765 .base_baud = 921600,
3766 .uart_offset = 0x8,
3767 },
3768 [pbn_sunix_pci_16s] = {
3769 .num_ports = 16,
3770 .base_baud = 921600,
3771 .uart_offset = 0x8,
3772 },
3773 [pbn_titan_1_4000000] = {
3774 .flags = FL_BASE0,
3775 .num_ports = 1,
3776 .base_baud = 4000000,
3777 .uart_offset = 0x200,
3778 .first_offset = 0x1000,
3779 },
3780 [pbn_titan_2_4000000] = {
3781 .flags = FL_BASE0,
3782 .num_ports = 2,
3783 .base_baud = 4000000,
3784 .uart_offset = 0x200,
3785 .first_offset = 0x1000,
3786 },
3787 [pbn_titan_4_4000000] = {
3788 .flags = FL_BASE0,
3789 .num_ports = 4,
3790 .base_baud = 4000000,
3791 .uart_offset = 0x200,
3792 .first_offset = 0x1000,
3793 },
3794 [pbn_titan_8_4000000] = {
3795 .flags = FL_BASE0,
3796 .num_ports = 8,
3797 .base_baud = 4000000,
3798 .uart_offset = 0x200,
3799 .first_offset = 0x1000,
3800 },
3801 [pbn_moxa8250_2p] = {
3802 .flags = FL_BASE1,
3803 .num_ports = 2,
3804 .base_baud = 921600,
3805 .uart_offset = 0x200,
3806 },
3807 [pbn_moxa8250_4p] = {
3808 .flags = FL_BASE1,
3809 .num_ports = 4,
3810 .base_baud = 921600,
3811 .uart_offset = 0x200,
3812 },
3813 [pbn_moxa8250_8p] = {
3814 .flags = FL_BASE1,
3815 .num_ports = 8,
3816 .base_baud = 921600,
3817 .uart_offset = 0x200,
3818 },
3819 };
3820
3821 static const struct pci_device_id blacklist[] = {
3822 /* softmodems */
3823 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3824 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3825 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3826
3827 /* multi-io cards handled by parport_serial */
3828 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3829 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3830 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3831
3832 /* Intel platforms with MID UART */
3833 { PCI_VDEVICE(INTEL, 0x081b), },
3834 { PCI_VDEVICE(INTEL, 0x081c), },
3835 { PCI_VDEVICE(INTEL, 0x081d), },
3836 { PCI_VDEVICE(INTEL, 0x1191), },
3837 { PCI_VDEVICE(INTEL, 0x18d8), },
3838 { PCI_VDEVICE(INTEL, 0x19d8), },
3839
3840 /* Intel platforms with DesignWare UART */
3841 { PCI_VDEVICE(INTEL, 0x0936), },
3842 { PCI_VDEVICE(INTEL, 0x0f0a), },
3843 { PCI_VDEVICE(INTEL, 0x0f0c), },
3844 { PCI_VDEVICE(INTEL, 0x228a), },
3845 { PCI_VDEVICE(INTEL, 0x228c), },
3846 { PCI_VDEVICE(INTEL, 0x4b96), },
3847 { PCI_VDEVICE(INTEL, 0x4b97), },
3848 { PCI_VDEVICE(INTEL, 0x4b98), },
3849 { PCI_VDEVICE(INTEL, 0x4b99), },
3850 { PCI_VDEVICE(INTEL, 0x4b9a), },
3851 { PCI_VDEVICE(INTEL, 0x4b9b), },
3852 { PCI_VDEVICE(INTEL, 0x9ce3), },
3853 { PCI_VDEVICE(INTEL, 0x9ce4), },
3854
3855 /* Exar devices */
3856 { PCI_VDEVICE(EXAR, PCI_ANY_ID), },
3857 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), },
3858
3859 /* End of the black list */
3860 { }
3861 };
3862
3863 static int serial_pci_is_class_communication(struct pci_dev *dev)
3864 {
3865 /*
3866 * If it is not a communications device or the programming
3867 * interface is greater than 6, give up.
3868 */
3869 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3870 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
3871 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3872 (dev->class & 0xff) > 6)
3873 return -ENODEV;
3874
3875 return 0;
3876 }
3877
3878 /*
3879 * Given a complete unknown PCI device, try to use some heuristics to
3880 * guess what the configuration might be, based on the pitiful PCI
3881 * serial specs. Returns 0 on success, -ENODEV on failure.
3882 */
3883 static int
3884 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3885 {
3886 int num_iomem, num_port, first_port = -1, i;
3887 int rc;
3888
3889 rc = serial_pci_is_class_communication(dev);
3890 if (rc)
3891 return rc;
3892
3893 /*
3894 * Should we try to make guesses for multiport serial devices later?
3895 */
3896 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
3897 return -ENODEV;
3898
3899 num_iomem = num_port = 0;
3900 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
3901 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3902 num_port++;
3903 if (first_port == -1)
3904 first_port = i;
3905 }
3906 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3907 num_iomem++;
3908 }
3909
3910 /*
3911 * If there is 1 or 0 iomem regions, and exactly one port,
3912 * use it. We guess the number of ports based on the IO
3913 * region size.
3914 */
3915 if (num_iomem <= 1 && num_port == 1) {
3916 board->flags = first_port;
3917 board->num_ports = pci_resource_len(dev, first_port) / 8;
3918 return 0;
3919 }
3920
3921 /*
3922 * Now guess if we've got a board which indexes by BARs.
3923 * Each IO BAR should be 8 bytes, and they should follow
3924 * consecutively.
3925 */
3926 first_port = -1;
3927 num_port = 0;
3928 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
3929 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3930 pci_resource_len(dev, i) == 8 &&
3931 (first_port == -1 || (first_port + num_port) == i)) {
3932 num_port++;
3933 if (first_port == -1)
3934 first_port = i;
3935 }
3936 }
3937
3938 if (num_port > 1) {
3939 board->flags = first_port | FL_BASE_BARS;
3940 board->num_ports = num_port;
3941 return 0;
3942 }
3943
3944 return -ENODEV;
3945 }
3946
3947 static inline int
3948 serial_pci_matches(const struct pciserial_board *board,
3949 const struct pciserial_board *guessed)
3950 {
3951 return
3952 board->num_ports == guessed->num_ports &&
3953 board->base_baud == guessed->base_baud &&
3954 board->uart_offset == guessed->uart_offset &&
3955 board->reg_shift == guessed->reg_shift &&
3956 board->first_offset == guessed->first_offset;
3957 }
3958
3959 struct serial_private *
3960 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3961 {
3962 struct uart_8250_port uart;
3963 struct serial_private *priv;
3964 struct pci_serial_quirk *quirk;
3965 int rc, nr_ports, i;
3966
3967 nr_ports = board->num_ports;
3968
3969 /*
3970 * Find an init and setup quirks.
3971 */
3972 quirk = find_quirk(dev);
3973
3974 /*
3975 * Run the new-style initialization function.
3976 * The initialization function returns:
3977 * <0 - error
3978 * 0 - use board->num_ports
3979 * >0 - number of ports
3980 */
3981 if (quirk->init) {
3982 rc = quirk->init(dev);
3983 if (rc < 0) {
3984 priv = ERR_PTR(rc);
3985 goto err_out;
3986 }
3987 if (rc)
3988 nr_ports = rc;
3989 }
3990
3991 priv = kzalloc(sizeof(struct serial_private) +
3992 sizeof(unsigned int) * nr_ports,
3993 GFP_KERNEL);
3994 if (!priv) {
3995 priv = ERR_PTR(-ENOMEM);
3996 goto err_deinit;
3997 }
3998
3999 priv->dev = dev;
4000 priv->quirk = quirk;
4001
4002 memset(&uart, 0, sizeof(uart));
4003 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
4004 uart.port.uartclk = board->base_baud * 16;
4005
4006 if (board->flags & FL_NOIRQ) {
4007 uart.port.irq = 0;
4008 } else {
4009 if (pci_match_id(pci_use_msi, dev)) {
4010 dev_dbg(&dev->dev, "Using MSI(-X) interrupts\n");
4011 pci_set_master(dev);
4012 uart.port.flags &= ~UPF_SHARE_IRQ;
4013 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
4014 } else {
4015 dev_dbg(&dev->dev, "Using legacy interrupts\n");
4016 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY);
4017 }
4018 if (rc < 0) {
4019 kfree(priv);
4020 priv = ERR_PTR(rc);
4021 goto err_deinit;
4022 }
4023
4024 uart.port.irq = pci_irq_vector(dev, 0);
4025 }
4026
4027 uart.port.dev = &dev->dev;
4028
4029 for (i = 0; i < nr_ports; i++) {
4030 if (quirk->setup(priv, board, &uart, i))
4031 break;
4032
4033 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4034 uart.port.iobase, uart.port.irq, uart.port.iotype);
4035
4036 priv->line[i] = serial8250_register_8250_port(&uart);
4037 if (priv->line[i] < 0) {
4038 dev_err(&dev->dev,
4039 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4040 uart.port.iobase, uart.port.irq,
4041 uart.port.iotype, priv->line[i]);
4042 break;
4043 }
4044 }
4045 priv->nr = i;
4046 priv->board = board;
4047 return priv;
4048
4049 err_deinit:
4050 if (quirk->exit)
4051 quirk->exit(dev);
4052 err_out:
4053 return priv;
4054 }
4055 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4056
4057 static void pciserial_detach_ports(struct serial_private *priv)
4058 {
4059 struct pci_serial_quirk *quirk;
4060 int i;
4061
4062 for (i = 0; i < priv->nr; i++)
4063 serial8250_unregister_port(priv->line[i]);
4064
4065 /*
4066 * Find the exit quirks.
4067 */
4068 quirk = find_quirk(priv->dev);
4069 if (quirk->exit)
4070 quirk->exit(priv->dev);
4071 }
4072
4073 void pciserial_remove_ports(struct serial_private *priv)
4074 {
4075 pciserial_detach_ports(priv);
4076 kfree(priv);
4077 }
4078 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4079
4080 void pciserial_suspend_ports(struct serial_private *priv)
4081 {
4082 int i;
4083
4084 for (i = 0; i < priv->nr; i++)
4085 if (priv->line[i] >= 0)
4086 serial8250_suspend_port(priv->line[i]);
4087
4088 /*
4089 * Ensure that every init quirk is properly torn down
4090 */
4091 if (priv->quirk->exit)
4092 priv->quirk->exit(priv->dev);
4093 }
4094 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4095
4096 void pciserial_resume_ports(struct serial_private *priv)
4097 {
4098 int i;
4099
4100 /*
4101 * Ensure that the board is correctly configured.
4102 */
4103 if (priv->quirk->init)
4104 priv->quirk->init(priv->dev);
4105
4106 for (i = 0; i < priv->nr; i++)
4107 if (priv->line[i] >= 0)
4108 serial8250_resume_port(priv->line[i]);
4109 }
4110 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4111
4112 /*
4113 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4114 * to the arrangement of serial ports on a PCI card.
4115 */
4116 static int
4117 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4118 {
4119 struct pci_serial_quirk *quirk;
4120 struct serial_private *priv;
4121 const struct pciserial_board *board;
4122 const struct pci_device_id *exclude;
4123 struct pciserial_board tmp;
4124 int rc;
4125
4126 quirk = find_quirk(dev);
4127 if (quirk->probe) {
4128 rc = quirk->probe(dev);
4129 if (rc)
4130 return rc;
4131 }
4132
4133 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4134 dev_err(&dev->dev, "invalid driver_data: %ld\n",
4135 ent->driver_data);
4136 return -EINVAL;
4137 }
4138
4139 board = &pci_boards[ent->driver_data];
4140
4141 exclude = pci_match_id(blacklist, dev);
4142 if (exclude)
4143 return -ENODEV;
4144
4145 rc = pcim_enable_device(dev);
4146 pci_save_state(dev);
4147 if (rc)
4148 return rc;
4149
4150 if (ent->driver_data == pbn_default) {
4151 /*
4152 * Use a copy of the pci_board entry for this;
4153 * avoid changing entries in the table.
4154 */
4155 memcpy(&tmp, board, sizeof(struct pciserial_board));
4156 board = &tmp;
4157
4158 /*
4159 * We matched one of our class entries. Try to
4160 * determine the parameters of this board.
4161 */
4162 rc = serial_pci_guess_board(dev, &tmp);
4163 if (rc)
4164 return rc;
4165 } else {
4166 /*
4167 * We matched an explicit entry. If we are able to
4168 * detect this boards settings with our heuristic,
4169 * then we no longer need this entry.
4170 */
4171 memcpy(&tmp, &pci_boards[pbn_default],
4172 sizeof(struct pciserial_board));
4173 rc = serial_pci_guess_board(dev, &tmp);
4174 if (rc == 0 && serial_pci_matches(board, &tmp))
4175 moan_device("Redundant entry in serial pci_table.",
4176 dev);
4177 }
4178
4179 priv = pciserial_init_ports(dev, board);
4180 if (IS_ERR(priv))
4181 return PTR_ERR(priv);
4182
4183 pci_set_drvdata(dev, priv);
4184 return 0;
4185 }
4186
4187 static void pciserial_remove_one(struct pci_dev *dev)
4188 {
4189 struct serial_private *priv = pci_get_drvdata(dev);
4190
4191 pciserial_remove_ports(priv);
4192 }
4193
4194 #ifdef CONFIG_PM_SLEEP
4195 static int pciserial_suspend_one(struct device *dev)
4196 {
4197 struct serial_private *priv = dev_get_drvdata(dev);
4198
4199 if (priv)
4200 pciserial_suspend_ports(priv);
4201
4202 return 0;
4203 }
4204
4205 static int pciserial_resume_one(struct device *dev)
4206 {
4207 struct pci_dev *pdev = to_pci_dev(dev);
4208 struct serial_private *priv = pci_get_drvdata(pdev);
4209 int err;
4210
4211 if (priv) {
4212 /*
4213 * The device may have been disabled. Re-enable it.
4214 */
4215 err = pci_enable_device(pdev);
4216 /* FIXME: We cannot simply error out here */
4217 if (err)
4218 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4219 pciserial_resume_ports(priv);
4220 }
4221 return 0;
4222 }
4223 #endif
4224
4225 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4226 pciserial_resume_one);
4227
4228 static const struct pci_device_id serial_pci_tbl[] = {
4229 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4230 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4231 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4232 pbn_b2_8_921600 },
4233 /* Advantech also use 0x3618 and 0xf618 */
4234 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4235 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4236 pbn_b0_4_921600 },
4237 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4238 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4239 pbn_b0_4_921600 },
4240 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4241 PCI_SUBVENDOR_ID_CONNECT_TECH,
4242 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4243 pbn_b1_8_1382400 },
4244 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4245 PCI_SUBVENDOR_ID_CONNECT_TECH,
4246 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4247 pbn_b1_4_1382400 },
4248 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4249 PCI_SUBVENDOR_ID_CONNECT_TECH,
4250 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4251 pbn_b1_2_1382400 },
4252 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4253 PCI_SUBVENDOR_ID_CONNECT_TECH,
4254 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4255 pbn_b1_8_1382400 },
4256 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4257 PCI_SUBVENDOR_ID_CONNECT_TECH,
4258 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4259 pbn_b1_4_1382400 },
4260 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4261 PCI_SUBVENDOR_ID_CONNECT_TECH,
4262 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4263 pbn_b1_2_1382400 },
4264 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4265 PCI_SUBVENDOR_ID_CONNECT_TECH,
4266 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4267 pbn_b1_8_921600 },
4268 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4269 PCI_SUBVENDOR_ID_CONNECT_TECH,
4270 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4271 pbn_b1_8_921600 },
4272 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4273 PCI_SUBVENDOR_ID_CONNECT_TECH,
4274 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4275 pbn_b1_4_921600 },
4276 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4277 PCI_SUBVENDOR_ID_CONNECT_TECH,
4278 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4279 pbn_b1_4_921600 },
4280 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4281 PCI_SUBVENDOR_ID_CONNECT_TECH,
4282 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4283 pbn_b1_2_921600 },
4284 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4285 PCI_SUBVENDOR_ID_CONNECT_TECH,
4286 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4287 pbn_b1_8_921600 },
4288 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4289 PCI_SUBVENDOR_ID_CONNECT_TECH,
4290 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4291 pbn_b1_8_921600 },
4292 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4293 PCI_SUBVENDOR_ID_CONNECT_TECH,
4294 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4295 pbn_b1_4_921600 },
4296 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4297 PCI_SUBVENDOR_ID_CONNECT_TECH,
4298 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4299 pbn_b1_2_1250000 },
4300 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4301 PCI_SUBVENDOR_ID_CONNECT_TECH,
4302 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4303 pbn_b0_2_1843200 },
4304 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4305 PCI_SUBVENDOR_ID_CONNECT_TECH,
4306 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4307 pbn_b0_4_1843200 },
4308 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4309 PCI_VENDOR_ID_AFAVLAB,
4310 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4311 pbn_b0_4_1152000 },
4312 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4313 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4314 pbn_b2_bt_1_115200 },
4315 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4316 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4317 pbn_b2_bt_2_115200 },
4318 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4319 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4320 pbn_b2_bt_4_115200 },
4321 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4322 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4323 pbn_b2_bt_2_115200 },
4324 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4325 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4326 pbn_b2_bt_4_115200 },
4327 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4328 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4329 pbn_b2_8_115200 },
4330 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4331 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4332 pbn_b2_8_460800 },
4333 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4334 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4335 pbn_b2_8_115200 },
4336
4337 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4338 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4339 pbn_b2_bt_2_115200 },
4340 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4341 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342 pbn_b2_bt_2_921600 },
4343 /*
4344 * VScom SPCOM800, from sl@s.pl
4345 */
4346 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4347 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4348 pbn_b2_8_921600 },
4349 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4350 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4351 pbn_b2_4_921600 },
4352 /* Unknown card - subdevice 0x1584 */
4353 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4354 PCI_VENDOR_ID_PLX,
4355 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4356 pbn_b2_4_115200 },
4357 /* Unknown card - subdevice 0x1588 */
4358 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4359 PCI_VENDOR_ID_PLX,
4360 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4361 pbn_b2_8_115200 },
4362 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4363 PCI_SUBVENDOR_ID_KEYSPAN,
4364 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4365 pbn_panacom },
4366 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4367 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4368 pbn_panacom4 },
4369 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4370 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4371 pbn_panacom2 },
4372 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4373 PCI_VENDOR_ID_ESDGMBH,
4374 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4375 pbn_b2_4_115200 },
4376 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4377 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4378 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4379 pbn_b2_4_460800 },
4380 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4381 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4382 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4383 pbn_b2_8_460800 },
4384 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4385 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4386 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4387 pbn_b2_16_460800 },
4388 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4389 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4390 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4391 pbn_b2_16_460800 },
4392 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4393 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4394 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4395 pbn_b2_4_460800 },
4396 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4397 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4398 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4399 pbn_b2_8_460800 },
4400 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4401 PCI_SUBVENDOR_ID_EXSYS,
4402 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4403 pbn_b2_4_115200 },
4404 /*
4405 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4406 * (Exoray@isys.ca)
4407 */
4408 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4409 0x10b5, 0x106a, 0, 0,
4410 pbn_plx_romulus },
4411 /*
4412 * EndRun Technologies. PCI express device range.
4413 * EndRun PTP/1588 has 2 Native UARTs.
4414 */
4415 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4416 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4417 pbn_endrun_2_4000000 },
4418 /*
4419 * Quatech cards. These actually have configurable clocks but for
4420 * now we just use the default.
4421 *
4422 * 100 series are RS232, 200 series RS422,
4423 */
4424 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4425 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4426 pbn_b1_4_115200 },
4427 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4428 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4429 pbn_b1_2_115200 },
4430 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4431 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4432 pbn_b2_2_115200 },
4433 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4434 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4435 pbn_b1_2_115200 },
4436 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4437 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4438 pbn_b2_2_115200 },
4439 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4440 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4441 pbn_b1_4_115200 },
4442 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4444 pbn_b1_8_115200 },
4445 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4446 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4447 pbn_b1_8_115200 },
4448 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4449 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4450 pbn_b1_4_115200 },
4451 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4452 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4453 pbn_b1_2_115200 },
4454 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4455 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4456 pbn_b1_4_115200 },
4457 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4458 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4459 pbn_b1_2_115200 },
4460 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4461 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4462 pbn_b2_4_115200 },
4463 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4464 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4465 pbn_b2_2_115200 },
4466 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4467 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4468 pbn_b2_1_115200 },
4469 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4470 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4471 pbn_b2_4_115200 },
4472 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4473 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4474 pbn_b2_2_115200 },
4475 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4476 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4477 pbn_b2_1_115200 },
4478 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4479 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4480 pbn_b0_8_115200 },
4481
4482 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4483 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4484 0, 0,
4485 pbn_b0_4_921600 },
4486 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4487 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4488 0, 0,
4489 pbn_b0_4_1152000 },
4490 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4491 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4492 pbn_b0_bt_2_921600 },
4493
4494 /*
4495 * The below card is a little controversial since it is the
4496 * subject of a PCI vendor/device ID clash. (See
4497 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4498 * For now just used the hex ID 0x950a.
4499 */
4500 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4501 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4502 0, 0, pbn_b0_2_115200 },
4503 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4504 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4505 0, 0, pbn_b0_2_115200 },
4506 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4507 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4508 pbn_b0_2_1130000 },
4509 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4510 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4511 pbn_b0_1_921600 },
4512 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4513 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4514 pbn_b0_4_115200 },
4515 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4516 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4517 pbn_b0_bt_2_921600 },
4518 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4519 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4520 pbn_b2_8_1152000 },
4521
4522 /*
4523 * Oxford Semiconductor Inc. Tornado PCI express device range.
4524 */
4525 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4526 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4527 pbn_b0_1_3906250 },
4528 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4529 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4530 pbn_b0_1_3906250 },
4531 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4532 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4533 pbn_oxsemi_1_3906250 },
4534 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4535 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4536 pbn_oxsemi_1_3906250 },
4537 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4538 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4539 pbn_b0_1_3906250 },
4540 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4541 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4542 pbn_b0_1_3906250 },
4543 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4544 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4545 pbn_oxsemi_1_3906250 },
4546 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4547 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4548 pbn_oxsemi_1_3906250 },
4549 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4550 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4551 pbn_b0_1_3906250 },
4552 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4553 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4554 pbn_b0_1_3906250 },
4555 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4556 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4557 pbn_b0_1_3906250 },
4558 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4559 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4560 pbn_b0_1_3906250 },
4561 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4562 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4563 pbn_oxsemi_2_3906250 },
4564 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4565 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4566 pbn_oxsemi_2_3906250 },
4567 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4568 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4569 pbn_oxsemi_4_3906250 },
4570 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4571 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4572 pbn_oxsemi_4_3906250 },
4573 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4574 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4575 pbn_oxsemi_8_3906250 },
4576 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4577 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4578 pbn_oxsemi_8_3906250 },
4579 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4580 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4581 pbn_oxsemi_1_3906250 },
4582 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4583 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4584 pbn_oxsemi_1_3906250 },
4585 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4586 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4587 pbn_oxsemi_1_3906250 },
4588 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4589 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4590 pbn_oxsemi_1_3906250 },
4591 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593 pbn_oxsemi_1_3906250 },
4594 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596 pbn_oxsemi_1_3906250 },
4597 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599 pbn_oxsemi_1_3906250 },
4600 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602 pbn_oxsemi_1_3906250 },
4603 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 pbn_oxsemi_1_3906250 },
4606 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608 pbn_oxsemi_1_3906250 },
4609 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611 pbn_oxsemi_1_3906250 },
4612 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614 pbn_oxsemi_1_3906250 },
4615 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617 pbn_oxsemi_1_3906250 },
4618 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4619 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4620 pbn_oxsemi_1_3906250 },
4621 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623 pbn_oxsemi_1_3906250 },
4624 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4625 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4626 pbn_oxsemi_1_3906250 },
4627 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4628 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629 pbn_oxsemi_1_3906250 },
4630 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4631 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4632 pbn_oxsemi_1_3906250 },
4633 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4634 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4635 pbn_oxsemi_1_3906250 },
4636 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4637 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4638 pbn_oxsemi_1_3906250 },
4639 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4640 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4641 pbn_oxsemi_1_3906250 },
4642 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4643 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4644 pbn_oxsemi_1_3906250 },
4645 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4646 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4647 pbn_oxsemi_1_3906250 },
4648 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4649 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4650 pbn_oxsemi_1_3906250 },
4651 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4652 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4653 pbn_oxsemi_1_3906250 },
4654 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4655 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4656 pbn_oxsemi_1_3906250 },
4657 /*
4658 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4659 */
4660 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4661 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4662 pbn_oxsemi_1_3906250 },
4663 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4664 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4665 pbn_oxsemi_2_3906250 },
4666 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4667 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4668 pbn_oxsemi_4_3906250 },
4669 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4670 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4671 pbn_oxsemi_8_3906250 },
4672
4673 /*
4674 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4675 */
4676 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4677 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4678 pbn_oxsemi_2_3906250 },
4679
4680 /*
4681 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4682 * from skokodyn@yahoo.com
4683 */
4684 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4685 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4686 pbn_sbsxrsio },
4687 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4688 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4689 pbn_sbsxrsio },
4690 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4691 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4692 pbn_sbsxrsio },
4693 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4694 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4695 pbn_sbsxrsio },
4696
4697 /*
4698 * Digitan DS560-558, from jimd@esoft.com
4699 */
4700 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4701 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4702 pbn_b1_1_115200 },
4703
4704 /*
4705 * Titan Electronic cards
4706 * The 400L and 800L have a custom setup quirk.
4707 */
4708 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4709 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4710 pbn_b0_1_921600 },
4711 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4712 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4713 pbn_b0_2_921600 },
4714 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4715 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4716 pbn_b0_4_921600 },
4717 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4718 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4719 pbn_b0_4_921600 },
4720 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4721 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4722 pbn_b1_1_921600 },
4723 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4724 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4725 pbn_b1_bt_2_921600 },
4726 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4727 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4728 pbn_b0_bt_4_921600 },
4729 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4730 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4731 pbn_b0_bt_8_921600 },
4732 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4733 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4734 pbn_b4_bt_2_921600 },
4735 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4736 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4737 pbn_b4_bt_4_921600 },
4738 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4739 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4740 pbn_b4_bt_8_921600 },
4741 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4742 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4743 pbn_b0_4_921600 },
4744 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4745 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4746 pbn_b0_4_921600 },
4747 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4748 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4749 pbn_b0_4_921600 },
4750 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4751 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4752 pbn_titan_1_4000000 },
4753 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4754 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4755 pbn_titan_2_4000000 },
4756 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4757 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4758 pbn_titan_4_4000000 },
4759 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4760 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4761 pbn_titan_8_4000000 },
4762 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4763 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4764 pbn_titan_2_4000000 },
4765 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4766 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4767 pbn_titan_2_4000000 },
4768 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4769 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4770 pbn_b0_bt_2_921600 },
4771 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4772 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4773 pbn_b0_4_921600 },
4774 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4775 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4776 pbn_b0_4_921600 },
4777 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4778 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4779 pbn_b0_4_921600 },
4780 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4781 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4782 pbn_b0_4_921600 },
4783
4784 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4785 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4786 pbn_b2_1_460800 },
4787 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4788 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4789 pbn_b2_1_460800 },
4790 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4791 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4792 pbn_b2_1_460800 },
4793 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4794 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4795 pbn_b2_bt_2_921600 },
4796 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4797 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4798 pbn_b2_bt_2_921600 },
4799 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4800 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4801 pbn_b2_bt_2_921600 },
4802 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4803 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4804 pbn_b2_bt_4_921600 },
4805 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4806 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4807 pbn_b2_bt_4_921600 },
4808 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4809 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4810 pbn_b2_bt_4_921600 },
4811 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4812 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4813 pbn_b0_1_921600 },
4814 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4815 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4816 pbn_b0_1_921600 },
4817 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4818 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4819 pbn_b0_1_921600 },
4820 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4821 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4822 pbn_b0_bt_2_921600 },
4823 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4824 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4825 pbn_b0_bt_2_921600 },
4826 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4827 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4828 pbn_b0_bt_2_921600 },
4829 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4830 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4831 pbn_b0_bt_4_921600 },
4832 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4833 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4834 pbn_b0_bt_4_921600 },
4835 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4836 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4837 pbn_b0_bt_4_921600 },
4838 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4839 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4840 pbn_b0_bt_8_921600 },
4841 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4842 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4843 pbn_b0_bt_8_921600 },
4844 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4845 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4846 pbn_b0_bt_8_921600 },
4847
4848 /*
4849 * Computone devices submitted by Doug McNash dmcnash@computone.com
4850 */
4851 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4852 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4853 0, 0, pbn_computone_4 },
4854 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4855 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4856 0, 0, pbn_computone_8 },
4857 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4858 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4859 0, 0, pbn_computone_6 },
4860
4861 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4862 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4863 pbn_oxsemi },
4864 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4865 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4866 pbn_b0_bt_1_921600 },
4867
4868 /*
4869 * Sunix PCI serial boards
4870 */
4871 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4872 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
4873 pbn_sunix_pci_1s },
4874 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4875 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
4876 pbn_sunix_pci_2s },
4877 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4878 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
4879 pbn_sunix_pci_4s },
4880 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4881 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
4882 pbn_sunix_pci_4s },
4883 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4884 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
4885 pbn_sunix_pci_8s },
4886 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4887 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
4888 pbn_sunix_pci_8s },
4889 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4890 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
4891 pbn_sunix_pci_16s },
4892
4893 /*
4894 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4895 */
4896 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4897 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4898 pbn_b0_bt_8_115200 },
4899 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4900 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4901 pbn_b0_bt_8_115200 },
4902
4903 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4904 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4905 pbn_b0_bt_2_115200 },
4906 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4907 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4908 pbn_b0_bt_2_115200 },
4909 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4910 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4911 pbn_b0_bt_2_115200 },
4912 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4913 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4914 pbn_b0_bt_2_115200 },
4915 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4916 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4917 pbn_b0_bt_2_115200 },
4918 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4919 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4920 pbn_b0_bt_4_460800 },
4921 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4922 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4923 pbn_b0_bt_4_460800 },
4924 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4925 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4926 pbn_b0_bt_2_460800 },
4927 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4928 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4929 pbn_b0_bt_2_460800 },
4930 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4931 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4932 pbn_b0_bt_2_460800 },
4933 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4934 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4935 pbn_b0_bt_1_115200 },
4936 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4937 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4938 pbn_b0_bt_1_460800 },
4939
4940 /*
4941 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4942 * Cards are identified by their subsystem vendor IDs, which
4943 * (in hex) match the model number.
4944 *
4945 * Note that JC140x are RS422/485 cards which require ox950
4946 * ACR = 0x10, and as such are not currently fully supported.
4947 */
4948 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4949 0x1204, 0x0004, 0, 0,
4950 pbn_b0_4_921600 },
4951 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4952 0x1208, 0x0004, 0, 0,
4953 pbn_b0_4_921600 },
4954 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4955 0x1402, 0x0002, 0, 0,
4956 pbn_b0_2_921600 }, */
4957 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4958 0x1404, 0x0004, 0, 0,
4959 pbn_b0_4_921600 }, */
4960 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4961 0x1208, 0x0004, 0, 0,
4962 pbn_b0_4_921600 },
4963
4964 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4965 0x1204, 0x0004, 0, 0,
4966 pbn_b0_4_921600 },
4967 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4968 0x1208, 0x0004, 0, 0,
4969 pbn_b0_4_921600 },
4970 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4971 0x1208, 0x0004, 0, 0,
4972 pbn_b0_4_921600 },
4973 /*
4974 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4975 */
4976 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4977 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4978 pbn_b1_1_1382400 },
4979
4980 /*
4981 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4982 */
4983 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4984 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4985 pbn_b1_1_1382400 },
4986
4987 /*
4988 * RAStel 2 port modem, gerg@moreton.com.au
4989 */
4990 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4991 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4992 pbn_b2_bt_2_115200 },
4993
4994 /*
4995 * EKF addition for i960 Boards form EKF with serial port
4996 */
4997 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4998 0xE4BF, PCI_ANY_ID, 0, 0,
4999 pbn_intel_i960 },
5000
5001 /*
5002 * Xircom Cardbus/Ethernet combos
5003 */
5004 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5005 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5006 pbn_b0_1_115200 },
5007 /*
5008 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5009 */
5010 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5011 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5012 pbn_b0_1_115200 },
5013
5014 /*
5015 * Untested PCI modems, sent in from various folks...
5016 */
5017
5018 /*
5019 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5020 */
5021 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5022 0x1048, 0x1500, 0, 0,
5023 pbn_b1_1_115200 },
5024
5025 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5026 0xFF00, 0, 0, 0,
5027 pbn_sgi_ioc3 },
5028
5029 /*
5030 * HP Diva card
5031 */
5032 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5033 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5034 pbn_b1_1_115200 },
5035 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5036 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5037 pbn_b0_5_115200 },
5038 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5039 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5040 pbn_b2_1_115200 },
5041 /* HPE PCI serial device */
5042 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
5043 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5044 pbn_b1_1_115200 },
5045
5046 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5047 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5048 pbn_b3_2_115200 },
5049 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5050 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5051 pbn_b3_4_115200 },
5052 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5053 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5054 pbn_b3_8_115200 },
5055 /*
5056 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
5057 */
5058 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
5059 PCI_ANY_ID, PCI_ANY_ID,
5060 0,
5061 0, pbn_pericom_PI7C9X7951 },
5062 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
5063 PCI_ANY_ID, PCI_ANY_ID,
5064 0,
5065 0, pbn_pericom_PI7C9X7952 },
5066 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
5067 PCI_ANY_ID, PCI_ANY_ID,
5068 0,
5069 0, pbn_pericom_PI7C9X7954 },
5070 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
5071 PCI_ANY_ID, PCI_ANY_ID,
5072 0,
5073 0, pbn_pericom_PI7C9X7958 },
5074 /*
5075 * ACCES I/O Products quad
5076 */
5077 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
5078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5079 pbn_pericom_PI7C9X7952 },
5080 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
5081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5082 pbn_pericom_PI7C9X7952 },
5083 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
5084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5085 pbn_pericom_PI7C9X7954 },
5086 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
5087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5088 pbn_pericom_PI7C9X7954 },
5089 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
5090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5091 pbn_pericom_PI7C9X7952 },
5092 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
5093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5094 pbn_pericom_PI7C9X7952 },
5095 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
5096 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5097 pbn_pericom_PI7C9X7954 },
5098 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
5099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5100 pbn_pericom_PI7C9X7954 },
5101 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
5102 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5103 pbn_pericom_PI7C9X7952 },
5104 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
5105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5106 pbn_pericom_PI7C9X7952 },
5107 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
5108 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5109 pbn_pericom_PI7C9X7954 },
5110 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
5111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5112 pbn_pericom_PI7C9X7954 },
5113 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
5114 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5115 pbn_pericom_PI7C9X7951 },
5116 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
5117 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5118 pbn_pericom_PI7C9X7952 },
5119 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
5120 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5121 pbn_pericom_PI7C9X7952 },
5122 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
5123 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5124 pbn_pericom_PI7C9X7954 },
5125 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
5126 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5127 pbn_pericom_PI7C9X7954 },
5128 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
5129 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5130 pbn_pericom_PI7C9X7952 },
5131 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
5132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5133 pbn_pericom_PI7C9X7954 },
5134 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
5135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5136 pbn_pericom_PI7C9X7952 },
5137 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
5138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5139 pbn_pericom_PI7C9X7952 },
5140 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
5141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5142 pbn_pericom_PI7C9X7954 },
5143 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
5144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5145 pbn_pericom_PI7C9X7954 },
5146 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
5147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5148 pbn_pericom_PI7C9X7952 },
5149 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
5150 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5151 pbn_pericom_PI7C9X7954 },
5152 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
5153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5154 pbn_pericom_PI7C9X7954 },
5155 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
5156 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5157 pbn_pericom_PI7C9X7958 },
5158 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
5159 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5160 pbn_pericom_PI7C9X7958 },
5161 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
5162 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5163 pbn_pericom_PI7C9X7954 },
5164 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
5165 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5166 pbn_pericom_PI7C9X7958 },
5167 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
5168 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5169 pbn_pericom_PI7C9X7954 },
5170 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
5171 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5172 pbn_pericom_PI7C9X7958 },
5173 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
5174 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5175 pbn_pericom_PI7C9X7954 },
5176 /*
5177 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5178 */
5179 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5180 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5181 pbn_b0_1_115200 },
5182 /*
5183 * ITE
5184 */
5185 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5186 PCI_ANY_ID, PCI_ANY_ID,
5187 0, 0,
5188 pbn_b1_bt_1_115200 },
5189
5190 /*
5191 * IntaShield IS-200
5192 */
5193 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
5195 pbn_b2_2_115200 },
5196 /*
5197 * IntaShield IS-400
5198 */
5199 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5201 pbn_b2_4_115200 },
5202 /*
5203 * BrainBoxes UC-260
5204 */
5205 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5206 PCI_ANY_ID, PCI_ANY_ID,
5207 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5208 pbn_b2_4_115200 },
5209 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5210 PCI_ANY_ID, PCI_ANY_ID,
5211 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5212 pbn_b2_4_115200 },
5213 /*
5214 * Perle PCI-RAS cards
5215 */
5216 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5217 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5218 0, 0, pbn_b2_4_921600 },
5219 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5220 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5221 0, 0, pbn_b2_8_921600 },
5222
5223 /*
5224 * Mainpine series cards: Fairly standard layout but fools
5225 * parts of the autodetect in some cases and uses otherwise
5226 * unmatched communications subclasses in the PCI Express case
5227 */
5228
5229 { /* RockForceDUO */
5230 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5231 PCI_VENDOR_ID_MAINPINE, 0x0200,
5232 0, 0, pbn_b0_2_115200 },
5233 { /* RockForceQUATRO */
5234 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5235 PCI_VENDOR_ID_MAINPINE, 0x0300,
5236 0, 0, pbn_b0_4_115200 },
5237 { /* RockForceDUO+ */
5238 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5239 PCI_VENDOR_ID_MAINPINE, 0x0400,
5240 0, 0, pbn_b0_2_115200 },
5241 { /* RockForceQUATRO+ */
5242 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5243 PCI_VENDOR_ID_MAINPINE, 0x0500,
5244 0, 0, pbn_b0_4_115200 },
5245 { /* RockForce+ */
5246 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5247 PCI_VENDOR_ID_MAINPINE, 0x0600,
5248 0, 0, pbn_b0_2_115200 },
5249 { /* RockForce+ */
5250 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5251 PCI_VENDOR_ID_MAINPINE, 0x0700,
5252 0, 0, pbn_b0_4_115200 },
5253 { /* RockForceOCTO+ */
5254 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5255 PCI_VENDOR_ID_MAINPINE, 0x0800,
5256 0, 0, pbn_b0_8_115200 },
5257 { /* RockForceDUO+ */
5258 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5259 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5260 0, 0, pbn_b0_2_115200 },
5261 { /* RockForceQUARTRO+ */
5262 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5263 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5264 0, 0, pbn_b0_4_115200 },
5265 { /* RockForceOCTO+ */
5266 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5267 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5268 0, 0, pbn_b0_8_115200 },
5269 { /* RockForceD1 */
5270 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5271 PCI_VENDOR_ID_MAINPINE, 0x2000,
5272 0, 0, pbn_b0_1_115200 },
5273 { /* RockForceF1 */
5274 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5275 PCI_VENDOR_ID_MAINPINE, 0x2100,
5276 0, 0, pbn_b0_1_115200 },
5277 { /* RockForceD2 */
5278 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5279 PCI_VENDOR_ID_MAINPINE, 0x2200,
5280 0, 0, pbn_b0_2_115200 },
5281 { /* RockForceF2 */
5282 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5283 PCI_VENDOR_ID_MAINPINE, 0x2300,
5284 0, 0, pbn_b0_2_115200 },
5285 { /* RockForceD4 */
5286 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5287 PCI_VENDOR_ID_MAINPINE, 0x2400,
5288 0, 0, pbn_b0_4_115200 },
5289 { /* RockForceF4 */
5290 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5291 PCI_VENDOR_ID_MAINPINE, 0x2500,
5292 0, 0, pbn_b0_4_115200 },
5293 { /* RockForceD8 */
5294 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5295 PCI_VENDOR_ID_MAINPINE, 0x2600,
5296 0, 0, pbn_b0_8_115200 },
5297 { /* RockForceF8 */
5298 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5299 PCI_VENDOR_ID_MAINPINE, 0x2700,
5300 0, 0, pbn_b0_8_115200 },
5301 { /* IQ Express D1 */
5302 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5303 PCI_VENDOR_ID_MAINPINE, 0x3000,
5304 0, 0, pbn_b0_1_115200 },
5305 { /* IQ Express F1 */
5306 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5307 PCI_VENDOR_ID_MAINPINE, 0x3100,
5308 0, 0, pbn_b0_1_115200 },
5309 { /* IQ Express D2 */
5310 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5311 PCI_VENDOR_ID_MAINPINE, 0x3200,
5312 0, 0, pbn_b0_2_115200 },
5313 { /* IQ Express F2 */
5314 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5315 PCI_VENDOR_ID_MAINPINE, 0x3300,
5316 0, 0, pbn_b0_2_115200 },
5317 { /* IQ Express D4 */
5318 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5319 PCI_VENDOR_ID_MAINPINE, 0x3400,
5320 0, 0, pbn_b0_4_115200 },
5321 { /* IQ Express F4 */
5322 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5323 PCI_VENDOR_ID_MAINPINE, 0x3500,
5324 0, 0, pbn_b0_4_115200 },
5325 { /* IQ Express D8 */
5326 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5327 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5328 0, 0, pbn_b0_8_115200 },
5329 { /* IQ Express F8 */
5330 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5331 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5332 0, 0, pbn_b0_8_115200 },
5333
5334
5335 /*
5336 * PA Semi PA6T-1682M on-chip UART
5337 */
5338 { PCI_VENDOR_ID_PASEMI, 0xa004,
5339 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5340 pbn_pasemi_1682M },
5341
5342 /*
5343 * National Instruments
5344 */
5345 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5346 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5347 pbn_b1_16_115200 },
5348 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5349 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5350 pbn_b1_8_115200 },
5351 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5352 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5353 pbn_b1_bt_4_115200 },
5354 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5355 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5356 pbn_b1_bt_2_115200 },
5357 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5358 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5359 pbn_b1_bt_4_115200 },
5360 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5361 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5362 pbn_b1_bt_2_115200 },
5363 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5364 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5365 pbn_b1_16_115200 },
5366 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5367 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5368 pbn_b1_8_115200 },
5369 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5370 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5371 pbn_b1_bt_4_115200 },
5372 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5373 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5374 pbn_b1_bt_2_115200 },
5375 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5376 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5377 pbn_b1_bt_4_115200 },
5378 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5379 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5380 pbn_b1_bt_2_115200 },
5381 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5382 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5383 pbn_ni8430_2 },
5384 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5385 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5386 pbn_ni8430_2 },
5387 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5388 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5389 pbn_ni8430_4 },
5390 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5391 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5392 pbn_ni8430_4 },
5393 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5394 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5395 pbn_ni8430_8 },
5396 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5397 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5398 pbn_ni8430_8 },
5399 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5400 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5401 pbn_ni8430_16 },
5402 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5403 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5404 pbn_ni8430_16 },
5405 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5406 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5407 pbn_ni8430_2 },
5408 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5409 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5410 pbn_ni8430_2 },
5411 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5412 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5413 pbn_ni8430_4 },
5414 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5415 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5416 pbn_ni8430_4 },
5417
5418 /*
5419 * MOXA
5420 */
5421 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E,
5422 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5423 pbn_moxa8250_2p },
5424 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL,
5425 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5426 pbn_moxa8250_2p },
5427 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A,
5428 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5429 pbn_moxa8250_4p },
5430 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL,
5431 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5432 pbn_moxa8250_4p },
5433 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A,
5434 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5435 pbn_moxa8250_8p },
5436 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B,
5437 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5438 pbn_moxa8250_8p },
5439 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A,
5440 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5441 pbn_moxa8250_8p },
5442 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I,
5443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5444 pbn_moxa8250_8p },
5445 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL,
5446 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5447 pbn_moxa8250_2p },
5448 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A,
5449 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5450 pbn_moxa8250_4p },
5451 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A,
5452 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5453 pbn_moxa8250_8p },
5454 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A,
5455 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5456 pbn_moxa8250_8p },
5457
5458 /*
5459 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5460 */
5461 { PCI_VENDOR_ID_ADDIDATA,
5462 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5463 PCI_ANY_ID,
5464 PCI_ANY_ID,
5465 0,
5466 0,
5467 pbn_b0_4_115200 },
5468
5469 { PCI_VENDOR_ID_ADDIDATA,
5470 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5471 PCI_ANY_ID,
5472 PCI_ANY_ID,
5473 0,
5474 0,
5475 pbn_b0_2_115200 },
5476
5477 { PCI_VENDOR_ID_ADDIDATA,
5478 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5479 PCI_ANY_ID,
5480 PCI_ANY_ID,
5481 0,
5482 0,
5483 pbn_b0_1_115200 },
5484
5485 { PCI_VENDOR_ID_AMCC,
5486 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5487 PCI_ANY_ID,
5488 PCI_ANY_ID,
5489 0,
5490 0,
5491 pbn_b1_8_115200 },
5492
5493 { PCI_VENDOR_ID_ADDIDATA,
5494 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5495 PCI_ANY_ID,
5496 PCI_ANY_ID,
5497 0,
5498 0,
5499 pbn_b0_4_115200 },
5500
5501 { PCI_VENDOR_ID_ADDIDATA,
5502 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5503 PCI_ANY_ID,
5504 PCI_ANY_ID,
5505 0,
5506 0,
5507 pbn_b0_2_115200 },
5508
5509 { PCI_VENDOR_ID_ADDIDATA,
5510 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5511 PCI_ANY_ID,
5512 PCI_ANY_ID,
5513 0,
5514 0,
5515 pbn_b0_1_115200 },
5516
5517 { PCI_VENDOR_ID_ADDIDATA,
5518 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5519 PCI_ANY_ID,
5520 PCI_ANY_ID,
5521 0,
5522 0,
5523 pbn_b0_4_115200 },
5524
5525 { PCI_VENDOR_ID_ADDIDATA,
5526 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5527 PCI_ANY_ID,
5528 PCI_ANY_ID,
5529 0,
5530 0,
5531 pbn_b0_2_115200 },
5532
5533 { PCI_VENDOR_ID_ADDIDATA,
5534 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5535 PCI_ANY_ID,
5536 PCI_ANY_ID,
5537 0,
5538 0,
5539 pbn_b0_1_115200 },
5540
5541 { PCI_VENDOR_ID_ADDIDATA,
5542 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5543 PCI_ANY_ID,
5544 PCI_ANY_ID,
5545 0,
5546 0,
5547 pbn_b0_8_115200 },
5548
5549 { PCI_VENDOR_ID_ADDIDATA,
5550 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5551 PCI_ANY_ID,
5552 PCI_ANY_ID,
5553 0,
5554 0,
5555 pbn_ADDIDATA_PCIe_4_3906250 },
5556
5557 { PCI_VENDOR_ID_ADDIDATA,
5558 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5559 PCI_ANY_ID,
5560 PCI_ANY_ID,
5561 0,
5562 0,
5563 pbn_ADDIDATA_PCIe_2_3906250 },
5564
5565 { PCI_VENDOR_ID_ADDIDATA,
5566 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5567 PCI_ANY_ID,
5568 PCI_ANY_ID,
5569 0,
5570 0,
5571 pbn_ADDIDATA_PCIe_1_3906250 },
5572
5573 { PCI_VENDOR_ID_ADDIDATA,
5574 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5575 PCI_ANY_ID,
5576 PCI_ANY_ID,
5577 0,
5578 0,
5579 pbn_ADDIDATA_PCIe_8_3906250 },
5580
5581 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5582 PCI_VENDOR_ID_IBM, 0x0299,
5583 0, 0, pbn_b0_bt_2_115200 },
5584
5585 /*
5586 * other NetMos 9835 devices are most likely handled by the
5587 * parport_serial driver, check drivers/parport/parport_serial.c
5588 * before adding them here.
5589 */
5590
5591 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5592 0xA000, 0x1000,
5593 0, 0, pbn_b0_1_115200 },
5594
5595 /* the 9901 is a rebranded 9912 */
5596 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5597 0xA000, 0x1000,
5598 0, 0, pbn_b0_1_115200 },
5599
5600 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5601 0xA000, 0x1000,
5602 0, 0, pbn_b0_1_115200 },
5603
5604 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5605 0xA000, 0x1000,
5606 0, 0, pbn_b0_1_115200 },
5607
5608 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5609 0xA000, 0x1000,
5610 0, 0, pbn_b0_1_115200 },
5611
5612 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5613 0xA000, 0x3002,
5614 0, 0, pbn_NETMOS9900_2s_115200 },
5615
5616 /*
5617 * Best Connectivity and Rosewill PCI Multi I/O cards
5618 */
5619
5620 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5621 0xA000, 0x1000,
5622 0, 0, pbn_b0_1_115200 },
5623
5624 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5625 0xA000, 0x3002,
5626 0, 0, pbn_b0_bt_2_115200 },
5627
5628 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5629 0xA000, 0x3004,
5630 0, 0, pbn_b0_bt_4_115200 },
5631 /* Intel CE4100 */
5632 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5633 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5634 pbn_ce4100_1_115200 },
5635
5636 /*
5637 * Cronyx Omega PCI
5638 */
5639 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5640 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5641 pbn_omegapci },
5642
5643 /*
5644 * Broadcom TruManage
5645 */
5646 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5647 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5648 pbn_brcm_trumanage },
5649
5650 /*
5651 * AgeStar as-prs2-009
5652 */
5653 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5654 PCI_ANY_ID, PCI_ANY_ID,
5655 0, 0, pbn_b0_bt_2_115200 },
5656
5657 /*
5658 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5659 * so not listed here.
5660 */
5661 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5662 PCI_ANY_ID, PCI_ANY_ID,
5663 0, 0, pbn_b0_bt_4_115200 },
5664
5665 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5666 PCI_ANY_ID, PCI_ANY_ID,
5667 0, 0, pbn_b0_bt_2_115200 },
5668
5669 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5670 PCI_ANY_ID, PCI_ANY_ID,
5671 0, 0, pbn_b0_bt_4_115200 },
5672
5673 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5674 PCI_ANY_ID, PCI_ANY_ID,
5675 0, 0, pbn_wch382_2 },
5676
5677 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5678 PCI_ANY_ID, PCI_ANY_ID,
5679 0, 0, pbn_wch384_4 },
5680
5681 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S,
5682 PCI_ANY_ID, PCI_ANY_ID,
5683 0, 0, pbn_wch384_8 },
5684 /*
5685 * Realtek RealManage
5686 */
5687 { PCI_VENDOR_ID_REALTEK, 0x816a,
5688 PCI_ANY_ID, PCI_ANY_ID,
5689 0, 0, pbn_b0_1_115200 },
5690
5691 { PCI_VENDOR_ID_REALTEK, 0x816b,
5692 PCI_ANY_ID, PCI_ANY_ID,
5693 0, 0, pbn_b0_1_115200 },
5694
5695 /* Fintek PCI serial cards */
5696 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5697 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5698 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5699 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
5700 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
5701 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
5702
5703 /* MKS Tenta SCOM-080x serial cards */
5704 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5705 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5706
5707 /* Amazon PCI serial device */
5708 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
5709
5710 /*
5711 * These entries match devices with class COMMUNICATION_SERIAL,
5712 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5713 */
5714 { PCI_ANY_ID, PCI_ANY_ID,
5715 PCI_ANY_ID, PCI_ANY_ID,
5716 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5717 0xffff00, pbn_default },
5718 { PCI_ANY_ID, PCI_ANY_ID,
5719 PCI_ANY_ID, PCI_ANY_ID,
5720 PCI_CLASS_COMMUNICATION_MODEM << 8,
5721 0xffff00, pbn_default },
5722 { PCI_ANY_ID, PCI_ANY_ID,
5723 PCI_ANY_ID, PCI_ANY_ID,
5724 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5725 0xffff00, pbn_default },
5726 { 0, }
5727 };
5728
5729 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5730 pci_channel_state_t state)
5731 {
5732 struct serial_private *priv = pci_get_drvdata(dev);
5733
5734 if (state == pci_channel_io_perm_failure)
5735 return PCI_ERS_RESULT_DISCONNECT;
5736
5737 if (priv)
5738 pciserial_detach_ports(priv);
5739
5740 pci_disable_device(dev);
5741
5742 return PCI_ERS_RESULT_NEED_RESET;
5743 }
5744
5745 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5746 {
5747 int rc;
5748
5749 rc = pci_enable_device(dev);
5750
5751 if (rc)
5752 return PCI_ERS_RESULT_DISCONNECT;
5753
5754 pci_restore_state(dev);
5755 pci_save_state(dev);
5756
5757 return PCI_ERS_RESULT_RECOVERED;
5758 }
5759
5760 static void serial8250_io_resume(struct pci_dev *dev)
5761 {
5762 struct serial_private *priv = pci_get_drvdata(dev);
5763 struct serial_private *new;
5764
5765 if (!priv)
5766 return;
5767
5768 new = pciserial_init_ports(dev, priv->board);
5769 if (!IS_ERR(new)) {
5770 pci_set_drvdata(dev, new);
5771 kfree(priv);
5772 }
5773 }
5774
5775 static const struct pci_error_handlers serial8250_err_handler = {
5776 .error_detected = serial8250_io_error_detected,
5777 .slot_reset = serial8250_io_slot_reset,
5778 .resume = serial8250_io_resume,
5779 };
5780
5781 static struct pci_driver serial_pci_driver = {
5782 .name = "serial",
5783 .probe = pciserial_init_one,
5784 .remove = pciserial_remove_one,
5785 .driver = {
5786 .pm = &pciserial_pm_ops,
5787 },
5788 .id_table = serial_pci_tbl,
5789 .err_handler = &serial8250_err_handler,
5790 };
5791
5792 module_pci_driver(serial_pci_driver);
5793
5794 MODULE_LICENSE("GPL");
5795 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5796 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
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