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[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / 8250 / 8250_pci.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type PCI serial ports.
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 */
9 #undef DEBUG
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/string.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/delay.h>
16 #include <linux/tty.h>
17 #include <linux/serial_reg.h>
18 #include <linux/serial_core.h>
19 #include <linux/8250_pci.h>
20 #include <linux/bitops.h>
21
22 #include <asm/byteorder.h>
23 #include <asm/io.h>
24
25 #include "8250.h"
26
27 /*
28 * init function returns:
29 * > 0 - number of ports
30 * = 0 - use board->num_ports
31 * < 0 - error
32 */
33 struct pci_serial_quirk {
34 u32 vendor;
35 u32 device;
36 u32 subvendor;
37 u32 subdevice;
38 int (*probe)(struct pci_dev *dev);
39 int (*init)(struct pci_dev *dev);
40 int (*setup)(struct serial_private *,
41 const struct pciserial_board *,
42 struct uart_8250_port *, int);
43 void (*exit)(struct pci_dev *dev);
44 };
45
46 #define PCI_NUM_BAR_RESOURCES 6
47
48 struct serial_private {
49 struct pci_dev *dev;
50 unsigned int nr;
51 struct pci_serial_quirk *quirk;
52 const struct pciserial_board *board;
53 int line[0];
54 };
55
56 static int pci_default_setup(struct serial_private*,
57 const struct pciserial_board*, struct uart_8250_port *, int);
58
59 static void moan_device(const char *str, struct pci_dev *dev)
60 {
61 dev_err(&dev->dev,
62 "%s: %s\n"
63 "Please send the output of lspci -vv, this\n"
64 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
65 "manufacturer and name of serial board or\n"
66 "modem board to <linux-serial@vger.kernel.org>.\n",
67 pci_name(dev), str, dev->vendor, dev->device,
68 dev->subsystem_vendor, dev->subsystem_device);
69 }
70
71 static int
72 setup_port(struct serial_private *priv, struct uart_8250_port *port,
73 int bar, int offset, int regshift)
74 {
75 struct pci_dev *dev = priv->dev;
76
77 if (bar >= PCI_NUM_BAR_RESOURCES)
78 return -EINVAL;
79
80 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
81 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
82 return -ENOMEM;
83
84 port->port.iotype = UPIO_MEM;
85 port->port.iobase = 0;
86 port->port.mapbase = pci_resource_start(dev, bar) + offset;
87 port->port.membase = pcim_iomap_table(dev)[bar] + offset;
88 port->port.regshift = regshift;
89 } else {
90 port->port.iotype = UPIO_PORT;
91 port->port.iobase = pci_resource_start(dev, bar) + offset;
92 port->port.mapbase = 0;
93 port->port.membase = NULL;
94 port->port.regshift = 0;
95 }
96 return 0;
97 }
98
99 /*
100 * ADDI-DATA GmbH communication cards <info@addi-data.com>
101 */
102 static int addidata_apci7800_setup(struct serial_private *priv,
103 const struct pciserial_board *board,
104 struct uart_8250_port *port, int idx)
105 {
106 unsigned int bar = 0, offset = board->first_offset;
107 bar = FL_GET_BASE(board->flags);
108
109 if (idx < 2) {
110 offset += idx * board->uart_offset;
111 } else if ((idx >= 2) && (idx < 4)) {
112 bar += 1;
113 offset += ((idx - 2) * board->uart_offset);
114 } else if ((idx >= 4) && (idx < 6)) {
115 bar += 2;
116 offset += ((idx - 4) * board->uart_offset);
117 } else if (idx >= 6) {
118 bar += 3;
119 offset += ((idx - 6) * board->uart_offset);
120 }
121
122 return setup_port(priv, port, bar, offset, board->reg_shift);
123 }
124
125 /*
126 * AFAVLAB uses a different mixture of BARs and offsets
127 * Not that ugly ;) -- HW
128 */
129 static int
130 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
131 struct uart_8250_port *port, int idx)
132 {
133 unsigned int bar, offset = board->first_offset;
134
135 bar = FL_GET_BASE(board->flags);
136 if (idx < 4)
137 bar += idx;
138 else {
139 bar = 4;
140 offset += (idx - 4) * board->uart_offset;
141 }
142
143 return setup_port(priv, port, bar, offset, board->reg_shift);
144 }
145
146 /*
147 * HP's Remote Management Console. The Diva chip came in several
148 * different versions. N-class, L2000 and A500 have two Diva chips, each
149 * with 3 UARTs (the third UART on the second chip is unused). Superdome
150 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
151 * one Diva chip, but it has been expanded to 5 UARTs.
152 */
153 static int pci_hp_diva_init(struct pci_dev *dev)
154 {
155 int rc = 0;
156
157 switch (dev->subsystem_device) {
158 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
159 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
160 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
161 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
162 rc = 3;
163 break;
164 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
165 rc = 2;
166 break;
167 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
168 rc = 4;
169 break;
170 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
171 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
172 rc = 1;
173 break;
174 }
175
176 return rc;
177 }
178
179 /*
180 * HP's Diva chip puts the 4th/5th serial port further out, and
181 * some serial ports are supposed to be hidden on certain models.
182 */
183 static int
184 pci_hp_diva_setup(struct serial_private *priv,
185 const struct pciserial_board *board,
186 struct uart_8250_port *port, int idx)
187 {
188 unsigned int offset = board->first_offset;
189 unsigned int bar = FL_GET_BASE(board->flags);
190
191 switch (priv->dev->subsystem_device) {
192 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
193 if (idx == 3)
194 idx++;
195 break;
196 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
197 if (idx > 0)
198 idx++;
199 if (idx > 2)
200 idx++;
201 break;
202 }
203 if (idx > 2)
204 offset = 0x18;
205
206 offset += idx * board->uart_offset;
207
208 return setup_port(priv, port, bar, offset, board->reg_shift);
209 }
210
211 /*
212 * Added for EKF Intel i960 serial boards
213 */
214 static int pci_inteli960ni_init(struct pci_dev *dev)
215 {
216 u32 oldval;
217
218 if (!(dev->subsystem_device & 0x1000))
219 return -ENODEV;
220
221 /* is firmware started? */
222 pci_read_config_dword(dev, 0x44, &oldval);
223 if (oldval == 0x00001000L) { /* RESET value */
224 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
225 return -ENODEV;
226 }
227 return 0;
228 }
229
230 /*
231 * Some PCI serial cards using the PLX 9050 PCI interface chip require
232 * that the card interrupt be explicitly enabled or disabled. This
233 * seems to be mainly needed on card using the PLX which also use I/O
234 * mapped memory.
235 */
236 static int pci_plx9050_init(struct pci_dev *dev)
237 {
238 u8 irq_config;
239 void __iomem *p;
240
241 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
242 moan_device("no memory in bar 0", dev);
243 return 0;
244 }
245
246 irq_config = 0x41;
247 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
248 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
249 irq_config = 0x43;
250
251 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
252 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
253 /*
254 * As the megawolf cards have the int pins active
255 * high, and have 2 UART chips, both ints must be
256 * enabled on the 9050. Also, the UARTS are set in
257 * 16450 mode by default, so we have to enable the
258 * 16C950 'enhanced' mode so that we can use the
259 * deep FIFOs
260 */
261 irq_config = 0x5b;
262 /*
263 * enable/disable interrupts
264 */
265 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
266 if (p == NULL)
267 return -ENOMEM;
268 writel(irq_config, p + 0x4c);
269
270 /*
271 * Read the register back to ensure that it took effect.
272 */
273 readl(p + 0x4c);
274 iounmap(p);
275
276 return 0;
277 }
278
279 static void pci_plx9050_exit(struct pci_dev *dev)
280 {
281 u8 __iomem *p;
282
283 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
284 return;
285
286 /*
287 * disable interrupts
288 */
289 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
290 if (p != NULL) {
291 writel(0, p + 0x4c);
292
293 /*
294 * Read the register back to ensure that it took effect.
295 */
296 readl(p + 0x4c);
297 iounmap(p);
298 }
299 }
300
301 #define NI8420_INT_ENABLE_REG 0x38
302 #define NI8420_INT_ENABLE_BIT 0x2000
303
304 static void pci_ni8420_exit(struct pci_dev *dev)
305 {
306 void __iomem *p;
307 unsigned int bar = 0;
308
309 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
310 moan_device("no memory in bar", dev);
311 return;
312 }
313
314 p = pci_ioremap_bar(dev, bar);
315 if (p == NULL)
316 return;
317
318 /* Disable the CPU Interrupt */
319 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
320 p + NI8420_INT_ENABLE_REG);
321 iounmap(p);
322 }
323
324
325 /* MITE registers */
326 #define MITE_IOWBSR1 0xc4
327 #define MITE_IOWCR1 0xf4
328 #define MITE_LCIMR1 0x08
329 #define MITE_LCIMR2 0x10
330
331 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
332
333 static void pci_ni8430_exit(struct pci_dev *dev)
334 {
335 void __iomem *p;
336 unsigned int bar = 0;
337
338 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
339 moan_device("no memory in bar", dev);
340 return;
341 }
342
343 p = pci_ioremap_bar(dev, bar);
344 if (p == NULL)
345 return;
346
347 /* Disable the CPU Interrupt */
348 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
349 iounmap(p);
350 }
351
352 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
353 static int
354 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
355 struct uart_8250_port *port, int idx)
356 {
357 unsigned int bar, offset = board->first_offset;
358
359 bar = 0;
360
361 if (idx < 4) {
362 /* first four channels map to 0, 0x100, 0x200, 0x300 */
363 offset += idx * board->uart_offset;
364 } else if (idx < 8) {
365 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
366 offset += idx * board->uart_offset + 0xC00;
367 } else /* we have only 8 ports on PMC-OCTALPRO */
368 return 1;
369
370 return setup_port(priv, port, bar, offset, board->reg_shift);
371 }
372
373 /*
374 * This does initialization for PMC OCTALPRO cards:
375 * maps the device memory, resets the UARTs (needed, bc
376 * if the module is removed and inserted again, the card
377 * is in the sleep mode) and enables global interrupt.
378 */
379
380 /* global control register offset for SBS PMC-OctalPro */
381 #define OCT_REG_CR_OFF 0x500
382
383 static int sbs_init(struct pci_dev *dev)
384 {
385 u8 __iomem *p;
386
387 p = pci_ioremap_bar(dev, 0);
388
389 if (p == NULL)
390 return -ENOMEM;
391 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
392 writeb(0x10, p + OCT_REG_CR_OFF);
393 udelay(50);
394 writeb(0x0, p + OCT_REG_CR_OFF);
395
396 /* Set bit-2 (INTENABLE) of Control Register */
397 writeb(0x4, p + OCT_REG_CR_OFF);
398 iounmap(p);
399
400 return 0;
401 }
402
403 /*
404 * Disables the global interrupt of PMC-OctalPro
405 */
406
407 static void sbs_exit(struct pci_dev *dev)
408 {
409 u8 __iomem *p;
410
411 p = pci_ioremap_bar(dev, 0);
412 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
413 if (p != NULL)
414 writeb(0, p + OCT_REG_CR_OFF);
415 iounmap(p);
416 }
417
418 /*
419 * SIIG serial cards have an PCI interface chip which also controls
420 * the UART clocking frequency. Each UART can be clocked independently
421 * (except cards equipped with 4 UARTs) and initial clocking settings
422 * are stored in the EEPROM chip. It can cause problems because this
423 * version of serial driver doesn't support differently clocked UART's
424 * on single PCI card. To prevent this, initialization functions set
425 * high frequency clocking for all UART's on given card. It is safe (I
426 * hope) because it doesn't touch EEPROM settings to prevent conflicts
427 * with other OSes (like M$ DOS).
428 *
429 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
430 *
431 * There is two family of SIIG serial cards with different PCI
432 * interface chip and different configuration methods:
433 * - 10x cards have control registers in IO and/or memory space;
434 * - 20x cards have control registers in standard PCI configuration space.
435 *
436 * Note: all 10x cards have PCI device ids 0x10..
437 * all 20x cards have PCI device ids 0x20..
438 *
439 * There are also Quartet Serial cards which use Oxford Semiconductor
440 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
441 *
442 * Note: some SIIG cards are probed by the parport_serial object.
443 */
444
445 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
446 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
447
448 static int pci_siig10x_init(struct pci_dev *dev)
449 {
450 u16 data;
451 void __iomem *p;
452
453 switch (dev->device & 0xfff8) {
454 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
455 data = 0xffdf;
456 break;
457 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
458 data = 0xf7ff;
459 break;
460 default: /* 1S1P, 4S */
461 data = 0xfffb;
462 break;
463 }
464
465 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
466 if (p == NULL)
467 return -ENOMEM;
468
469 writew(readw(p + 0x28) & data, p + 0x28);
470 readw(p + 0x28);
471 iounmap(p);
472 return 0;
473 }
474
475 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
476 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
477
478 static int pci_siig20x_init(struct pci_dev *dev)
479 {
480 u8 data;
481
482 /* Change clock frequency for the first UART. */
483 pci_read_config_byte(dev, 0x6f, &data);
484 pci_write_config_byte(dev, 0x6f, data & 0xef);
485
486 /* If this card has 2 UART, we have to do the same with second UART. */
487 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
488 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
489 pci_read_config_byte(dev, 0x73, &data);
490 pci_write_config_byte(dev, 0x73, data & 0xef);
491 }
492 return 0;
493 }
494
495 static int pci_siig_init(struct pci_dev *dev)
496 {
497 unsigned int type = dev->device & 0xff00;
498
499 if (type == 0x1000)
500 return pci_siig10x_init(dev);
501 else if (type == 0x2000)
502 return pci_siig20x_init(dev);
503
504 moan_device("Unknown SIIG card", dev);
505 return -ENODEV;
506 }
507
508 static int pci_siig_setup(struct serial_private *priv,
509 const struct pciserial_board *board,
510 struct uart_8250_port *port, int idx)
511 {
512 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
513
514 if (idx > 3) {
515 bar = 4;
516 offset = (idx - 4) * 8;
517 }
518
519 return setup_port(priv, port, bar, offset, 0);
520 }
521
522 /*
523 * Timedia has an explosion of boards, and to avoid the PCI table from
524 * growing *huge*, we use this function to collapse some 70 entries
525 * in the PCI table into one, for sanity's and compactness's sake.
526 */
527 static const unsigned short timedia_single_port[] = {
528 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
529 };
530
531 static const unsigned short timedia_dual_port[] = {
532 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
533 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
534 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
535 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
536 0xD079, 0
537 };
538
539 static const unsigned short timedia_quad_port[] = {
540 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
541 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
542 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
543 0xB157, 0
544 };
545
546 static const unsigned short timedia_eight_port[] = {
547 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
548 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
549 };
550
551 static const struct timedia_struct {
552 int num;
553 const unsigned short *ids;
554 } timedia_data[] = {
555 { 1, timedia_single_port },
556 { 2, timedia_dual_port },
557 { 4, timedia_quad_port },
558 { 8, timedia_eight_port }
559 };
560
561 /*
562 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
563 * listing them individually, this driver merely grabs them all with
564 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
565 * and should be left free to be claimed by parport_serial instead.
566 */
567 static int pci_timedia_probe(struct pci_dev *dev)
568 {
569 /*
570 * Check the third digit of the subdevice ID
571 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
572 */
573 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
574 dev_info(&dev->dev,
575 "ignoring Timedia subdevice %04x for parport_serial\n",
576 dev->subsystem_device);
577 return -ENODEV;
578 }
579
580 return 0;
581 }
582
583 static int pci_timedia_init(struct pci_dev *dev)
584 {
585 const unsigned short *ids;
586 int i, j;
587
588 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
589 ids = timedia_data[i].ids;
590 for (j = 0; ids[j]; j++)
591 if (dev->subsystem_device == ids[j])
592 return timedia_data[i].num;
593 }
594 return 0;
595 }
596
597 /*
598 * Timedia/SUNIX uses a mixture of BARs and offsets
599 * Ugh, this is ugly as all hell --- TYT
600 */
601 static int
602 pci_timedia_setup(struct serial_private *priv,
603 const struct pciserial_board *board,
604 struct uart_8250_port *port, int idx)
605 {
606 unsigned int bar = 0, offset = board->first_offset;
607
608 switch (idx) {
609 case 0:
610 bar = 0;
611 break;
612 case 1:
613 offset = board->uart_offset;
614 bar = 0;
615 break;
616 case 2:
617 bar = 1;
618 break;
619 case 3:
620 offset = board->uart_offset;
621 /* FALLTHROUGH */
622 case 4: /* BAR 2 */
623 case 5: /* BAR 3 */
624 case 6: /* BAR 4 */
625 case 7: /* BAR 5 */
626 bar = idx - 2;
627 }
628
629 return setup_port(priv, port, bar, offset, board->reg_shift);
630 }
631
632 /*
633 * Some Titan cards are also a little weird
634 */
635 static int
636 titan_400l_800l_setup(struct serial_private *priv,
637 const struct pciserial_board *board,
638 struct uart_8250_port *port, int idx)
639 {
640 unsigned int bar, offset = board->first_offset;
641
642 switch (idx) {
643 case 0:
644 bar = 1;
645 break;
646 case 1:
647 bar = 2;
648 break;
649 default:
650 bar = 4;
651 offset = (idx - 2) * board->uart_offset;
652 }
653
654 return setup_port(priv, port, bar, offset, board->reg_shift);
655 }
656
657 static int pci_xircom_init(struct pci_dev *dev)
658 {
659 msleep(100);
660 return 0;
661 }
662
663 static int pci_ni8420_init(struct pci_dev *dev)
664 {
665 void __iomem *p;
666 unsigned int bar = 0;
667
668 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
669 moan_device("no memory in bar", dev);
670 return 0;
671 }
672
673 p = pci_ioremap_bar(dev, bar);
674 if (p == NULL)
675 return -ENOMEM;
676
677 /* Enable CPU Interrupt */
678 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
679 p + NI8420_INT_ENABLE_REG);
680
681 iounmap(p);
682 return 0;
683 }
684
685 #define MITE_IOWBSR1_WSIZE 0xa
686 #define MITE_IOWBSR1_WIN_OFFSET 0x800
687 #define MITE_IOWBSR1_WENAB (1 << 7)
688 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
689 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
690 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
691
692 static int pci_ni8430_init(struct pci_dev *dev)
693 {
694 void __iomem *p;
695 struct pci_bus_region region;
696 u32 device_window;
697 unsigned int bar = 0;
698
699 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
700 moan_device("no memory in bar", dev);
701 return 0;
702 }
703
704 p = pci_ioremap_bar(dev, bar);
705 if (p == NULL)
706 return -ENOMEM;
707
708 /*
709 * Set device window address and size in BAR0, while acknowledging that
710 * the resource structure may contain a translated address that differs
711 * from the address the device responds to.
712 */
713 pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
714 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
715 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
716 writel(device_window, p + MITE_IOWBSR1);
717
718 /* Set window access to go to RAMSEL IO address space */
719 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
720 p + MITE_IOWCR1);
721
722 /* Enable IO Bus Interrupt 0 */
723 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
724
725 /* Enable CPU Interrupt */
726 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
727
728 iounmap(p);
729 return 0;
730 }
731
732 /* UART Port Control Register */
733 #define NI8430_PORTCON 0x0f
734 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
735
736 static int
737 pci_ni8430_setup(struct serial_private *priv,
738 const struct pciserial_board *board,
739 struct uart_8250_port *port, int idx)
740 {
741 struct pci_dev *dev = priv->dev;
742 void __iomem *p;
743 unsigned int bar, offset = board->first_offset;
744
745 if (idx >= board->num_ports)
746 return 1;
747
748 bar = FL_GET_BASE(board->flags);
749 offset += idx * board->uart_offset;
750
751 p = pci_ioremap_bar(dev, bar);
752 if (!p)
753 return -ENOMEM;
754
755 /* enable the transceiver */
756 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
757 p + offset + NI8430_PORTCON);
758
759 iounmap(p);
760
761 return setup_port(priv, port, bar, offset, board->reg_shift);
762 }
763
764 static int pci_netmos_9900_setup(struct serial_private *priv,
765 const struct pciserial_board *board,
766 struct uart_8250_port *port, int idx)
767 {
768 unsigned int bar;
769
770 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
771 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
772 /* netmos apparently orders BARs by datasheet layout, so serial
773 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
774 */
775 bar = 3 * idx;
776
777 return setup_port(priv, port, bar, 0, board->reg_shift);
778 } else {
779 return pci_default_setup(priv, board, port, idx);
780 }
781 }
782
783 /* the 99xx series comes with a range of device IDs and a variety
784 * of capabilities:
785 *
786 * 9900 has varying capabilities and can cascade to sub-controllers
787 * (cascading should be purely internal)
788 * 9904 is hardwired with 4 serial ports
789 * 9912 and 9922 are hardwired with 2 serial ports
790 */
791 static int pci_netmos_9900_numports(struct pci_dev *dev)
792 {
793 unsigned int c = dev->class;
794 unsigned int pi;
795 unsigned short sub_serports;
796
797 pi = c & 0xff;
798
799 if (pi == 2)
800 return 1;
801
802 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
803 /* two possibilities: 0x30ps encodes number of parallel and
804 * serial ports, or 0x1000 indicates *something*. This is not
805 * immediately obvious, since the 2s1p+4s configuration seems
806 * to offer all functionality on functions 0..2, while still
807 * advertising the same function 3 as the 4s+2s1p config.
808 */
809 sub_serports = dev->subsystem_device & 0xf;
810 if (sub_serports > 0)
811 return sub_serports;
812
813 dev_err(&dev->dev,
814 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
815 return 0;
816 }
817
818 moan_device("unknown NetMos/Mostech program interface", dev);
819 return 0;
820 }
821
822 static int pci_netmos_init(struct pci_dev *dev)
823 {
824 /* subdevice 0x00PS means <P> parallel, <S> serial */
825 unsigned int num_serial = dev->subsystem_device & 0xf;
826
827 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
828 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
829 return 0;
830
831 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
832 dev->subsystem_device == 0x0299)
833 return 0;
834
835 switch (dev->device) { /* FALLTHROUGH on all */
836 case PCI_DEVICE_ID_NETMOS_9904:
837 case PCI_DEVICE_ID_NETMOS_9912:
838 case PCI_DEVICE_ID_NETMOS_9922:
839 case PCI_DEVICE_ID_NETMOS_9900:
840 num_serial = pci_netmos_9900_numports(dev);
841 break;
842
843 default:
844 break;
845 }
846
847 if (num_serial == 0) {
848 moan_device("unknown NetMos/Mostech device", dev);
849 return -ENODEV;
850 }
851
852 return num_serial;
853 }
854
855 /*
856 * These chips are available with optionally one parallel port and up to
857 * two serial ports. Unfortunately they all have the same product id.
858 *
859 * Basic configuration is done over a region of 32 I/O ports. The base
860 * ioport is called INTA or INTC, depending on docs/other drivers.
861 *
862 * The region of the 32 I/O ports is configured in POSIO0R...
863 */
864
865 /* registers */
866 #define ITE_887x_MISCR 0x9c
867 #define ITE_887x_INTCBAR 0x78
868 #define ITE_887x_UARTBAR 0x7c
869 #define ITE_887x_PS0BAR 0x10
870 #define ITE_887x_POSIO0 0x60
871
872 /* I/O space size */
873 #define ITE_887x_IOSIZE 32
874 /* I/O space size (bits 26-24; 8 bytes = 011b) */
875 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
876 /* I/O space size (bits 26-24; 32 bytes = 101b) */
877 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
878 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
879 #define ITE_887x_POSIO_SPEED (3 << 29)
880 /* enable IO_Space bit */
881 #define ITE_887x_POSIO_ENABLE (1 << 31)
882
883 static int pci_ite887x_init(struct pci_dev *dev)
884 {
885 /* inta_addr are the configuration addresses of the ITE */
886 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
887 0x200, 0x280, 0 };
888 int ret, i, type;
889 struct resource *iobase = NULL;
890 u32 miscr, uartbar, ioport;
891
892 /* search for the base-ioport */
893 i = 0;
894 while (inta_addr[i] && iobase == NULL) {
895 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
896 "ite887x");
897 if (iobase != NULL) {
898 /* write POSIO0R - speed | size | ioport */
899 pci_write_config_dword(dev, ITE_887x_POSIO0,
900 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
901 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
902 /* write INTCBAR - ioport */
903 pci_write_config_dword(dev, ITE_887x_INTCBAR,
904 inta_addr[i]);
905 ret = inb(inta_addr[i]);
906 if (ret != 0xff) {
907 /* ioport connected */
908 break;
909 }
910 release_region(iobase->start, ITE_887x_IOSIZE);
911 iobase = NULL;
912 }
913 i++;
914 }
915
916 if (!inta_addr[i]) {
917 dev_err(&dev->dev, "ite887x: could not find iobase\n");
918 return -ENODEV;
919 }
920
921 /* start of undocumented type checking (see parport_pc.c) */
922 type = inb(iobase->start + 0x18) & 0x0f;
923
924 switch (type) {
925 case 0x2: /* ITE8871 (1P) */
926 case 0xa: /* ITE8875 (1P) */
927 ret = 0;
928 break;
929 case 0xe: /* ITE8872 (2S1P) */
930 ret = 2;
931 break;
932 case 0x6: /* ITE8873 (1S) */
933 ret = 1;
934 break;
935 case 0x8: /* ITE8874 (2S) */
936 ret = 2;
937 break;
938 default:
939 moan_device("Unknown ITE887x", dev);
940 ret = -ENODEV;
941 }
942
943 /* configure all serial ports */
944 for (i = 0; i < ret; i++) {
945 /* read the I/O port from the device */
946 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
947 &ioport);
948 ioport &= 0x0000FF00; /* the actual base address */
949 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
950 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
951 ITE_887x_POSIO_IOSIZE_8 | ioport);
952
953 /* write the ioport to the UARTBAR */
954 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
955 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
956 uartbar |= (ioport << (16 * i)); /* set the ioport */
957 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
958
959 /* get current config */
960 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
961 /* disable interrupts (UARTx_Routing[3:0]) */
962 miscr &= ~(0xf << (12 - 4 * i));
963 /* activate the UART (UARTx_En) */
964 miscr |= 1 << (23 - i);
965 /* write new config with activated UART */
966 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
967 }
968
969 if (ret <= 0) {
970 /* the device has no UARTs if we get here */
971 release_region(iobase->start, ITE_887x_IOSIZE);
972 }
973
974 return ret;
975 }
976
977 static void pci_ite887x_exit(struct pci_dev *dev)
978 {
979 u32 ioport;
980 /* the ioport is bit 0-15 in POSIO0R */
981 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
982 ioport &= 0xffff;
983 release_region(ioport, ITE_887x_IOSIZE);
984 }
985
986 /*
987 * EndRun Technologies.
988 * Determine the number of ports available on the device.
989 */
990 #define PCI_VENDOR_ID_ENDRUN 0x7401
991 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
992
993 static int pci_endrun_init(struct pci_dev *dev)
994 {
995 u8 __iomem *p;
996 unsigned long deviceID;
997 unsigned int number_uarts = 0;
998
999 /* EndRun device is all 0xexxx */
1000 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1001 (dev->device & 0xf000) != 0xe000)
1002 return 0;
1003
1004 p = pci_iomap(dev, 0, 5);
1005 if (p == NULL)
1006 return -ENOMEM;
1007
1008 deviceID = ioread32(p);
1009 /* EndRun device */
1010 if (deviceID == 0x07000200) {
1011 number_uarts = ioread8(p + 4);
1012 dev_dbg(&dev->dev,
1013 "%d ports detected on EndRun PCI Express device\n",
1014 number_uarts);
1015 }
1016 pci_iounmap(dev, p);
1017 return number_uarts;
1018 }
1019
1020 /*
1021 * Oxford Semiconductor Inc.
1022 * Check that device is part of the Tornado range of devices, then determine
1023 * the number of ports available on the device.
1024 */
1025 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1026 {
1027 u8 __iomem *p;
1028 unsigned long deviceID;
1029 unsigned int number_uarts = 0;
1030
1031 /* OxSemi Tornado devices are all 0xCxxx */
1032 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1033 (dev->device & 0xF000) != 0xC000)
1034 return 0;
1035
1036 p = pci_iomap(dev, 0, 5);
1037 if (p == NULL)
1038 return -ENOMEM;
1039
1040 deviceID = ioread32(p);
1041 /* Tornado device */
1042 if (deviceID == 0x07000200) {
1043 number_uarts = ioread8(p + 4);
1044 dev_dbg(&dev->dev,
1045 "%d ports detected on Oxford PCI Express device\n",
1046 number_uarts);
1047 }
1048 pci_iounmap(dev, p);
1049 return number_uarts;
1050 }
1051
1052 static int pci_asix_setup(struct serial_private *priv,
1053 const struct pciserial_board *board,
1054 struct uart_8250_port *port, int idx)
1055 {
1056 port->bugs |= UART_BUG_PARITY;
1057 return pci_default_setup(priv, board, port, idx);
1058 }
1059
1060 /* Quatech devices have their own extra interface features */
1061
1062 struct quatech_feature {
1063 u16 devid;
1064 bool amcc;
1065 };
1066
1067 #define QPCR_TEST_FOR1 0x3F
1068 #define QPCR_TEST_GET1 0x00
1069 #define QPCR_TEST_FOR2 0x40
1070 #define QPCR_TEST_GET2 0x40
1071 #define QPCR_TEST_FOR3 0x80
1072 #define QPCR_TEST_GET3 0x40
1073 #define QPCR_TEST_FOR4 0xC0
1074 #define QPCR_TEST_GET4 0x80
1075
1076 #define QOPR_CLOCK_X1 0x0000
1077 #define QOPR_CLOCK_X2 0x0001
1078 #define QOPR_CLOCK_X4 0x0002
1079 #define QOPR_CLOCK_X8 0x0003
1080 #define QOPR_CLOCK_RATE_MASK 0x0003
1081
1082
1083 static struct quatech_feature quatech_cards[] = {
1084 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1085 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1086 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1087 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1088 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1089 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1090 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1091 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1092 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1093 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1094 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1095 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1096 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1097 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1098 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1099 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1100 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1101 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1102 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1103 { 0, }
1104 };
1105
1106 static int pci_quatech_amcc(u16 devid)
1107 {
1108 struct quatech_feature *qf = &quatech_cards[0];
1109 while (qf->devid) {
1110 if (qf->devid == devid)
1111 return qf->amcc;
1112 qf++;
1113 }
1114 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1115 return 0;
1116 };
1117
1118 static int pci_quatech_rqopr(struct uart_8250_port *port)
1119 {
1120 unsigned long base = port->port.iobase;
1121 u8 LCR, val;
1122
1123 LCR = inb(base + UART_LCR);
1124 outb(0xBF, base + UART_LCR);
1125 val = inb(base + UART_SCR);
1126 outb(LCR, base + UART_LCR);
1127 return val;
1128 }
1129
1130 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1131 {
1132 unsigned long base = port->port.iobase;
1133 u8 LCR;
1134
1135 LCR = inb(base + UART_LCR);
1136 outb(0xBF, base + UART_LCR);
1137 inb(base + UART_SCR);
1138 outb(qopr, base + UART_SCR);
1139 outb(LCR, base + UART_LCR);
1140 }
1141
1142 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1143 {
1144 unsigned long base = port->port.iobase;
1145 u8 LCR, val, qmcr;
1146
1147 LCR = inb(base + UART_LCR);
1148 outb(0xBF, base + UART_LCR);
1149 val = inb(base + UART_SCR);
1150 outb(val | 0x10, base + UART_SCR);
1151 qmcr = inb(base + UART_MCR);
1152 outb(val, base + UART_SCR);
1153 outb(LCR, base + UART_LCR);
1154
1155 return qmcr;
1156 }
1157
1158 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1159 {
1160 unsigned long base = port->port.iobase;
1161 u8 LCR, val;
1162
1163 LCR = inb(base + UART_LCR);
1164 outb(0xBF, base + UART_LCR);
1165 val = inb(base + UART_SCR);
1166 outb(val | 0x10, base + UART_SCR);
1167 outb(qmcr, base + UART_MCR);
1168 outb(val, base + UART_SCR);
1169 outb(LCR, base + UART_LCR);
1170 }
1171
1172 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1173 {
1174 unsigned long base = port->port.iobase;
1175 u8 LCR, val;
1176
1177 LCR = inb(base + UART_LCR);
1178 outb(0xBF, base + UART_LCR);
1179 val = inb(base + UART_SCR);
1180 if (val & 0x20) {
1181 outb(0x80, UART_LCR);
1182 if (!(inb(UART_SCR) & 0x20)) {
1183 outb(LCR, base + UART_LCR);
1184 return 1;
1185 }
1186 }
1187 return 0;
1188 }
1189
1190 static int pci_quatech_test(struct uart_8250_port *port)
1191 {
1192 u8 reg, qopr;
1193
1194 qopr = pci_quatech_rqopr(port);
1195 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1196 reg = pci_quatech_rqopr(port) & 0xC0;
1197 if (reg != QPCR_TEST_GET1)
1198 return -EINVAL;
1199 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1200 reg = pci_quatech_rqopr(port) & 0xC0;
1201 if (reg != QPCR_TEST_GET2)
1202 return -EINVAL;
1203 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1204 reg = pci_quatech_rqopr(port) & 0xC0;
1205 if (reg != QPCR_TEST_GET3)
1206 return -EINVAL;
1207 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1208 reg = pci_quatech_rqopr(port) & 0xC0;
1209 if (reg != QPCR_TEST_GET4)
1210 return -EINVAL;
1211
1212 pci_quatech_wqopr(port, qopr);
1213 return 0;
1214 }
1215
1216 static int pci_quatech_clock(struct uart_8250_port *port)
1217 {
1218 u8 qopr, reg, set;
1219 unsigned long clock;
1220
1221 if (pci_quatech_test(port) < 0)
1222 return 1843200;
1223
1224 qopr = pci_quatech_rqopr(port);
1225
1226 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1227 reg = pci_quatech_rqopr(port);
1228 if (reg & QOPR_CLOCK_X8) {
1229 clock = 1843200;
1230 goto out;
1231 }
1232 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1233 reg = pci_quatech_rqopr(port);
1234 if (!(reg & QOPR_CLOCK_X8)) {
1235 clock = 1843200;
1236 goto out;
1237 }
1238 reg &= QOPR_CLOCK_X8;
1239 if (reg == QOPR_CLOCK_X2) {
1240 clock = 3685400;
1241 set = QOPR_CLOCK_X2;
1242 } else if (reg == QOPR_CLOCK_X4) {
1243 clock = 7372800;
1244 set = QOPR_CLOCK_X4;
1245 } else if (reg == QOPR_CLOCK_X8) {
1246 clock = 14745600;
1247 set = QOPR_CLOCK_X8;
1248 } else {
1249 clock = 1843200;
1250 set = QOPR_CLOCK_X1;
1251 }
1252 qopr &= ~QOPR_CLOCK_RATE_MASK;
1253 qopr |= set;
1254
1255 out:
1256 pci_quatech_wqopr(port, qopr);
1257 return clock;
1258 }
1259
1260 static int pci_quatech_rs422(struct uart_8250_port *port)
1261 {
1262 u8 qmcr;
1263 int rs422 = 0;
1264
1265 if (!pci_quatech_has_qmcr(port))
1266 return 0;
1267 qmcr = pci_quatech_rqmcr(port);
1268 pci_quatech_wqmcr(port, 0xFF);
1269 if (pci_quatech_rqmcr(port))
1270 rs422 = 1;
1271 pci_quatech_wqmcr(port, qmcr);
1272 return rs422;
1273 }
1274
1275 static int pci_quatech_init(struct pci_dev *dev)
1276 {
1277 if (pci_quatech_amcc(dev->device)) {
1278 unsigned long base = pci_resource_start(dev, 0);
1279 if (base) {
1280 u32 tmp;
1281
1282 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1283 tmp = inl(base + 0x3c);
1284 outl(tmp | 0x01000000, base + 0x3c);
1285 outl(tmp &= ~0x01000000, base + 0x3c);
1286 }
1287 }
1288 return 0;
1289 }
1290
1291 static int pci_quatech_setup(struct serial_private *priv,
1292 const struct pciserial_board *board,
1293 struct uart_8250_port *port, int idx)
1294 {
1295 /* Needed by pci_quatech calls below */
1296 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1297 /* Set up the clocking */
1298 port->port.uartclk = pci_quatech_clock(port);
1299 /* For now just warn about RS422 */
1300 if (pci_quatech_rs422(port))
1301 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1302 return pci_default_setup(priv, board, port, idx);
1303 }
1304
1305 static void pci_quatech_exit(struct pci_dev *dev)
1306 {
1307 }
1308
1309 static int pci_default_setup(struct serial_private *priv,
1310 const struct pciserial_board *board,
1311 struct uart_8250_port *port, int idx)
1312 {
1313 unsigned int bar, offset = board->first_offset, maxnr;
1314
1315 bar = FL_GET_BASE(board->flags);
1316 if (board->flags & FL_BASE_BARS)
1317 bar += idx;
1318 else
1319 offset += idx * board->uart_offset;
1320
1321 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1322 (board->reg_shift + 3);
1323
1324 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1325 return 1;
1326
1327 return setup_port(priv, port, bar, offset, board->reg_shift);
1328 }
1329
1330 static int pci_pericom_setup(struct serial_private *priv,
1331 const struct pciserial_board *board,
1332 struct uart_8250_port *port, int idx)
1333 {
1334 unsigned int bar, offset = board->first_offset, maxnr;
1335
1336 bar = FL_GET_BASE(board->flags);
1337 if (board->flags & FL_BASE_BARS)
1338 bar += idx;
1339 else
1340 offset += idx * board->uart_offset;
1341
1342 if (idx==3)
1343 offset = 0x38;
1344
1345 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1346 (board->reg_shift + 3);
1347
1348 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1349 return 1;
1350
1351 return setup_port(priv, port, bar, offset, board->reg_shift);
1352 }
1353
1354 static int
1355 ce4100_serial_setup(struct serial_private *priv,
1356 const struct pciserial_board *board,
1357 struct uart_8250_port *port, int idx)
1358 {
1359 int ret;
1360
1361 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1362 port->port.iotype = UPIO_MEM32;
1363 port->port.type = PORT_XSCALE;
1364 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1365 port->port.regshift = 2;
1366
1367 return ret;
1368 }
1369
1370 static int
1371 pci_omegapci_setup(struct serial_private *priv,
1372 const struct pciserial_board *board,
1373 struct uart_8250_port *port, int idx)
1374 {
1375 return setup_port(priv, port, 2, idx * 8, 0);
1376 }
1377
1378 static int
1379 pci_brcm_trumanage_setup(struct serial_private *priv,
1380 const struct pciserial_board *board,
1381 struct uart_8250_port *port, int idx)
1382 {
1383 int ret = pci_default_setup(priv, board, port, idx);
1384
1385 port->port.type = PORT_BRCM_TRUMANAGE;
1386 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1387 return ret;
1388 }
1389
1390 /* RTS will control by MCR if this bit is 0 */
1391 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1392 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1393 #define FINTEK_RTS_INVERT BIT(5)
1394
1395 /* We should do proper H/W transceiver setting before change to RS485 mode */
1396 static int pci_fintek_rs485_config(struct uart_port *port,
1397 struct serial_rs485 *rs485)
1398 {
1399 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1400 u8 setting;
1401 u8 *index = (u8 *) port->private_data;
1402
1403 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1404
1405 if (!rs485)
1406 rs485 = &port->rs485;
1407 else if (rs485->flags & SER_RS485_ENABLED)
1408 memset(rs485->padding, 0, sizeof(rs485->padding));
1409 else
1410 memset(rs485, 0, sizeof(*rs485));
1411
1412 /* F81504/508/512 not support RTS delay before or after send */
1413 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1414
1415 if (rs485->flags & SER_RS485_ENABLED) {
1416 /* Enable RTS H/W control mode */
1417 setting |= FINTEK_RTS_CONTROL_BY_HW;
1418
1419 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1420 /* RTS driving high on TX */
1421 setting &= ~FINTEK_RTS_INVERT;
1422 } else {
1423 /* RTS driving low on TX */
1424 setting |= FINTEK_RTS_INVERT;
1425 }
1426
1427 rs485->delay_rts_after_send = 0;
1428 rs485->delay_rts_before_send = 0;
1429 } else {
1430 /* Disable RTS H/W control mode */
1431 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1432 }
1433
1434 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1435
1436 if (rs485 != &port->rs485)
1437 port->rs485 = *rs485;
1438
1439 return 0;
1440 }
1441
1442 static int pci_fintek_setup(struct serial_private *priv,
1443 const struct pciserial_board *board,
1444 struct uart_8250_port *port, int idx)
1445 {
1446 struct pci_dev *pdev = priv->dev;
1447 u8 *data;
1448 u8 config_base;
1449 u16 iobase;
1450
1451 config_base = 0x40 + 0x08 * idx;
1452
1453 /* Get the io address from configuration space */
1454 pci_read_config_word(pdev, config_base + 4, &iobase);
1455
1456 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1457
1458 port->port.iotype = UPIO_PORT;
1459 port->port.iobase = iobase;
1460 port->port.rs485_config = pci_fintek_rs485_config;
1461
1462 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1463 if (!data)
1464 return -ENOMEM;
1465
1466 /* preserve index in PCI configuration space */
1467 *data = idx;
1468 port->port.private_data = data;
1469
1470 return 0;
1471 }
1472
1473 static int pci_fintek_init(struct pci_dev *dev)
1474 {
1475 unsigned long iobase;
1476 u32 max_port, i;
1477 resource_size_t bar_data[3];
1478 u8 config_base;
1479 struct serial_private *priv = pci_get_drvdata(dev);
1480 struct uart_8250_port *port;
1481
1482 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1483 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1484 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1485 return -ENODEV;
1486
1487 switch (dev->device) {
1488 case 0x1104: /* 4 ports */
1489 case 0x1108: /* 8 ports */
1490 max_port = dev->device & 0xff;
1491 break;
1492 case 0x1112: /* 12 ports */
1493 max_port = 12;
1494 break;
1495 default:
1496 return -EINVAL;
1497 }
1498
1499 /* Get the io address dispatch from the BIOS */
1500 bar_data[0] = pci_resource_start(dev, 5);
1501 bar_data[1] = pci_resource_start(dev, 4);
1502 bar_data[2] = pci_resource_start(dev, 3);
1503
1504 for (i = 0; i < max_port; ++i) {
1505 /* UART0 configuration offset start from 0x40 */
1506 config_base = 0x40 + 0x08 * i;
1507
1508 /* Calculate Real IO Port */
1509 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1510
1511 /* Enable UART I/O port */
1512 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1513
1514 /* Select 128-byte FIFO and 8x FIFO threshold */
1515 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1516
1517 /* LSB UART */
1518 pci_write_config_byte(dev, config_base + 0x04,
1519 (u8)(iobase & 0xff));
1520
1521 /* MSB UART */
1522 pci_write_config_byte(dev, config_base + 0x05,
1523 (u8)((iobase & 0xff00) >> 8));
1524
1525 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1526
1527 if (priv) {
1528 /* re-apply RS232/485 mode when
1529 * pciserial_resume_ports()
1530 */
1531 port = serial8250_get_port(priv->line[i]);
1532 pci_fintek_rs485_config(&port->port, NULL);
1533 } else {
1534 /* First init without port data
1535 * force init to RS232 Mode
1536 */
1537 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1538 }
1539 }
1540
1541 return max_port;
1542 }
1543
1544 static int skip_tx_en_setup(struct serial_private *priv,
1545 const struct pciserial_board *board,
1546 struct uart_8250_port *port, int idx)
1547 {
1548 port->port.quirks |= UPQ_NO_TXEN_TEST;
1549 dev_dbg(&priv->dev->dev,
1550 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1551 priv->dev->vendor, priv->dev->device,
1552 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1553
1554 return pci_default_setup(priv, board, port, idx);
1555 }
1556
1557 static void kt_handle_break(struct uart_port *p)
1558 {
1559 struct uart_8250_port *up = up_to_u8250p(p);
1560 /*
1561 * On receipt of a BI, serial device in Intel ME (Intel
1562 * management engine) needs to have its fifos cleared for sane
1563 * SOL (Serial Over Lan) output.
1564 */
1565 serial8250_clear_and_reinit_fifos(up);
1566 }
1567
1568 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1569 {
1570 struct uart_8250_port *up = up_to_u8250p(p);
1571 unsigned int val;
1572
1573 /*
1574 * When the Intel ME (management engine) gets reset its serial
1575 * port registers could return 0 momentarily. Functions like
1576 * serial8250_console_write, read and save the IER, perform
1577 * some operation and then restore it. In order to avoid
1578 * setting IER register inadvertently to 0, if the value read
1579 * is 0, double check with ier value in uart_8250_port and use
1580 * that instead. up->ier should be the same value as what is
1581 * currently configured.
1582 */
1583 val = inb(p->iobase + offset);
1584 if (offset == UART_IER) {
1585 if (val == 0)
1586 val = up->ier;
1587 }
1588 return val;
1589 }
1590
1591 static int kt_serial_setup(struct serial_private *priv,
1592 const struct pciserial_board *board,
1593 struct uart_8250_port *port, int idx)
1594 {
1595 port->port.flags |= UPF_BUG_THRE;
1596 port->port.serial_in = kt_serial_in;
1597 port->port.handle_break = kt_handle_break;
1598 return skip_tx_en_setup(priv, board, port, idx);
1599 }
1600
1601 static int pci_eg20t_init(struct pci_dev *dev)
1602 {
1603 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1604 return -ENODEV;
1605 #else
1606 return 0;
1607 #endif
1608 }
1609
1610 static int
1611 pci_wch_ch353_setup(struct serial_private *priv,
1612 const struct pciserial_board *board,
1613 struct uart_8250_port *port, int idx)
1614 {
1615 port->port.flags |= UPF_FIXED_TYPE;
1616 port->port.type = PORT_16550A;
1617 return pci_default_setup(priv, board, port, idx);
1618 }
1619
1620 static int
1621 pci_wch_ch355_setup(struct serial_private *priv,
1622 const struct pciserial_board *board,
1623 struct uart_8250_port *port, int idx)
1624 {
1625 port->port.flags |= UPF_FIXED_TYPE;
1626 port->port.type = PORT_16550A;
1627 return pci_default_setup(priv, board, port, idx);
1628 }
1629
1630 static int
1631 pci_wch_ch38x_setup(struct serial_private *priv,
1632 const struct pciserial_board *board,
1633 struct uart_8250_port *port, int idx)
1634 {
1635 port->port.flags |= UPF_FIXED_TYPE;
1636 port->port.type = PORT_16850;
1637 return pci_default_setup(priv, board, port, idx);
1638 }
1639
1640 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1641 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1642 #define PCI_DEVICE_ID_OCTPRO 0x0001
1643 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1644 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1645 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1646 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1647 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1648 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1649 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1650 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1651 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1652 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1653 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1654 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1655 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1656 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1657 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1658 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1659 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1660 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1661 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1662 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1663 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1664 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1665 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1666 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1667 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1668 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1669 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1670 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1671 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1672 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1673 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1674 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1675 #define PCI_VENDOR_ID_WCH 0x4348
1676 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1677 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1678 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1679 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1680 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1681 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
1682 #define PCI_VENDOR_ID_AGESTAR 0x5372
1683 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1684 #define PCI_VENDOR_ID_ASIX 0x9710
1685 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1686 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1687
1688 #define PCI_VENDOR_ID_SUNIX 0x1fd4
1689 #define PCI_DEVICE_ID_SUNIX_1999 0x1999
1690
1691 #define PCIE_VENDOR_ID_WCH 0x1c00
1692 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1693 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1694 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1695
1696 #define PCI_VENDOR_ID_PERICOM 0x12D8
1697 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951
1698 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952
1699 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954
1700 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958
1701
1702 #define PCI_VENDOR_ID_ACCESIO 0x494f
1703 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051
1704 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053
1705 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C
1706 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E
1707 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091
1708 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093
1709 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099
1710 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B
1711 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1
1712 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3
1713 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA
1714 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC
1715 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108
1716 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110
1717 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111
1718 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118
1719 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119
1720 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152
1721 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A
1722 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190
1723 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191
1724 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198
1725 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199
1726 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0
1727 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A
1728 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B
1729 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A
1730 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B
1731 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098
1732 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9
1733 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9
1734 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9
1735 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8
1736
1737
1738
1739 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1740 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1741 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1742
1743 /*
1744 * Master list of serial port init/setup/exit quirks.
1745 * This does not describe the general nature of the port.
1746 * (ie, baud base, number and location of ports, etc)
1747 *
1748 * This list is ordered alphabetically by vendor then device.
1749 * Specific entries must come before more generic entries.
1750 */
1751 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1752 /*
1753 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1754 */
1755 {
1756 .vendor = PCI_VENDOR_ID_AMCC,
1757 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1758 .subvendor = PCI_ANY_ID,
1759 .subdevice = PCI_ANY_ID,
1760 .setup = addidata_apci7800_setup,
1761 },
1762 /*
1763 * AFAVLAB cards - these may be called via parport_serial
1764 * It is not clear whether this applies to all products.
1765 */
1766 {
1767 .vendor = PCI_VENDOR_ID_AFAVLAB,
1768 .device = PCI_ANY_ID,
1769 .subvendor = PCI_ANY_ID,
1770 .subdevice = PCI_ANY_ID,
1771 .setup = afavlab_setup,
1772 },
1773 /*
1774 * HP Diva
1775 */
1776 {
1777 .vendor = PCI_VENDOR_ID_HP,
1778 .device = PCI_DEVICE_ID_HP_DIVA,
1779 .subvendor = PCI_ANY_ID,
1780 .subdevice = PCI_ANY_ID,
1781 .init = pci_hp_diva_init,
1782 .setup = pci_hp_diva_setup,
1783 },
1784 /*
1785 * Intel
1786 */
1787 {
1788 .vendor = PCI_VENDOR_ID_INTEL,
1789 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1790 .subvendor = 0xe4bf,
1791 .subdevice = PCI_ANY_ID,
1792 .init = pci_inteli960ni_init,
1793 .setup = pci_default_setup,
1794 },
1795 {
1796 .vendor = PCI_VENDOR_ID_INTEL,
1797 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1798 .subvendor = PCI_ANY_ID,
1799 .subdevice = PCI_ANY_ID,
1800 .setup = skip_tx_en_setup,
1801 },
1802 {
1803 .vendor = PCI_VENDOR_ID_INTEL,
1804 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1805 .subvendor = PCI_ANY_ID,
1806 .subdevice = PCI_ANY_ID,
1807 .setup = skip_tx_en_setup,
1808 },
1809 {
1810 .vendor = PCI_VENDOR_ID_INTEL,
1811 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1812 .subvendor = PCI_ANY_ID,
1813 .subdevice = PCI_ANY_ID,
1814 .setup = skip_tx_en_setup,
1815 },
1816 {
1817 .vendor = PCI_VENDOR_ID_INTEL,
1818 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1819 .subvendor = PCI_ANY_ID,
1820 .subdevice = PCI_ANY_ID,
1821 .setup = ce4100_serial_setup,
1822 },
1823 {
1824 .vendor = PCI_VENDOR_ID_INTEL,
1825 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1826 .subvendor = PCI_ANY_ID,
1827 .subdevice = PCI_ANY_ID,
1828 .setup = kt_serial_setup,
1829 },
1830 /*
1831 * ITE
1832 */
1833 {
1834 .vendor = PCI_VENDOR_ID_ITE,
1835 .device = PCI_DEVICE_ID_ITE_8872,
1836 .subvendor = PCI_ANY_ID,
1837 .subdevice = PCI_ANY_ID,
1838 .init = pci_ite887x_init,
1839 .setup = pci_default_setup,
1840 .exit = pci_ite887x_exit,
1841 },
1842 /*
1843 * National Instruments
1844 */
1845 {
1846 .vendor = PCI_VENDOR_ID_NI,
1847 .device = PCI_DEVICE_ID_NI_PCI23216,
1848 .subvendor = PCI_ANY_ID,
1849 .subdevice = PCI_ANY_ID,
1850 .init = pci_ni8420_init,
1851 .setup = pci_default_setup,
1852 .exit = pci_ni8420_exit,
1853 },
1854 {
1855 .vendor = PCI_VENDOR_ID_NI,
1856 .device = PCI_DEVICE_ID_NI_PCI2328,
1857 .subvendor = PCI_ANY_ID,
1858 .subdevice = PCI_ANY_ID,
1859 .init = pci_ni8420_init,
1860 .setup = pci_default_setup,
1861 .exit = pci_ni8420_exit,
1862 },
1863 {
1864 .vendor = PCI_VENDOR_ID_NI,
1865 .device = PCI_DEVICE_ID_NI_PCI2324,
1866 .subvendor = PCI_ANY_ID,
1867 .subdevice = PCI_ANY_ID,
1868 .init = pci_ni8420_init,
1869 .setup = pci_default_setup,
1870 .exit = pci_ni8420_exit,
1871 },
1872 {
1873 .vendor = PCI_VENDOR_ID_NI,
1874 .device = PCI_DEVICE_ID_NI_PCI2322,
1875 .subvendor = PCI_ANY_ID,
1876 .subdevice = PCI_ANY_ID,
1877 .init = pci_ni8420_init,
1878 .setup = pci_default_setup,
1879 .exit = pci_ni8420_exit,
1880 },
1881 {
1882 .vendor = PCI_VENDOR_ID_NI,
1883 .device = PCI_DEVICE_ID_NI_PCI2324I,
1884 .subvendor = PCI_ANY_ID,
1885 .subdevice = PCI_ANY_ID,
1886 .init = pci_ni8420_init,
1887 .setup = pci_default_setup,
1888 .exit = pci_ni8420_exit,
1889 },
1890 {
1891 .vendor = PCI_VENDOR_ID_NI,
1892 .device = PCI_DEVICE_ID_NI_PCI2322I,
1893 .subvendor = PCI_ANY_ID,
1894 .subdevice = PCI_ANY_ID,
1895 .init = pci_ni8420_init,
1896 .setup = pci_default_setup,
1897 .exit = pci_ni8420_exit,
1898 },
1899 {
1900 .vendor = PCI_VENDOR_ID_NI,
1901 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1902 .subvendor = PCI_ANY_ID,
1903 .subdevice = PCI_ANY_ID,
1904 .init = pci_ni8420_init,
1905 .setup = pci_default_setup,
1906 .exit = pci_ni8420_exit,
1907 },
1908 {
1909 .vendor = PCI_VENDOR_ID_NI,
1910 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1911 .subvendor = PCI_ANY_ID,
1912 .subdevice = PCI_ANY_ID,
1913 .init = pci_ni8420_init,
1914 .setup = pci_default_setup,
1915 .exit = pci_ni8420_exit,
1916 },
1917 {
1918 .vendor = PCI_VENDOR_ID_NI,
1919 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1920 .subvendor = PCI_ANY_ID,
1921 .subdevice = PCI_ANY_ID,
1922 .init = pci_ni8420_init,
1923 .setup = pci_default_setup,
1924 .exit = pci_ni8420_exit,
1925 },
1926 {
1927 .vendor = PCI_VENDOR_ID_NI,
1928 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1929 .subvendor = PCI_ANY_ID,
1930 .subdevice = PCI_ANY_ID,
1931 .init = pci_ni8420_init,
1932 .setup = pci_default_setup,
1933 .exit = pci_ni8420_exit,
1934 },
1935 {
1936 .vendor = PCI_VENDOR_ID_NI,
1937 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1938 .subvendor = PCI_ANY_ID,
1939 .subdevice = PCI_ANY_ID,
1940 .init = pci_ni8420_init,
1941 .setup = pci_default_setup,
1942 .exit = pci_ni8420_exit,
1943 },
1944 {
1945 .vendor = PCI_VENDOR_ID_NI,
1946 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1947 .subvendor = PCI_ANY_ID,
1948 .subdevice = PCI_ANY_ID,
1949 .init = pci_ni8420_init,
1950 .setup = pci_default_setup,
1951 .exit = pci_ni8420_exit,
1952 },
1953 {
1954 .vendor = PCI_VENDOR_ID_NI,
1955 .device = PCI_ANY_ID,
1956 .subvendor = PCI_ANY_ID,
1957 .subdevice = PCI_ANY_ID,
1958 .init = pci_ni8430_init,
1959 .setup = pci_ni8430_setup,
1960 .exit = pci_ni8430_exit,
1961 },
1962 /* Quatech */
1963 {
1964 .vendor = PCI_VENDOR_ID_QUATECH,
1965 .device = PCI_ANY_ID,
1966 .subvendor = PCI_ANY_ID,
1967 .subdevice = PCI_ANY_ID,
1968 .init = pci_quatech_init,
1969 .setup = pci_quatech_setup,
1970 .exit = pci_quatech_exit,
1971 },
1972 /*
1973 * Panacom
1974 */
1975 {
1976 .vendor = PCI_VENDOR_ID_PANACOM,
1977 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1978 .subvendor = PCI_ANY_ID,
1979 .subdevice = PCI_ANY_ID,
1980 .init = pci_plx9050_init,
1981 .setup = pci_default_setup,
1982 .exit = pci_plx9050_exit,
1983 },
1984 {
1985 .vendor = PCI_VENDOR_ID_PANACOM,
1986 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1987 .subvendor = PCI_ANY_ID,
1988 .subdevice = PCI_ANY_ID,
1989 .init = pci_plx9050_init,
1990 .setup = pci_default_setup,
1991 .exit = pci_plx9050_exit,
1992 },
1993 /*
1994 * Pericom (Only 7954 - It have a offset jump for port 4)
1995 */
1996 {
1997 .vendor = PCI_VENDOR_ID_PERICOM,
1998 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954,
1999 .subvendor = PCI_ANY_ID,
2000 .subdevice = PCI_ANY_ID,
2001 .setup = pci_pericom_setup,
2002 },
2003 /*
2004 * PLX
2005 */
2006 {
2007 .vendor = PCI_VENDOR_ID_PLX,
2008 .device = PCI_DEVICE_ID_PLX_9050,
2009 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2010 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2011 .init = pci_plx9050_init,
2012 .setup = pci_default_setup,
2013 .exit = pci_plx9050_exit,
2014 },
2015 {
2016 .vendor = PCI_VENDOR_ID_PLX,
2017 .device = PCI_DEVICE_ID_PLX_9050,
2018 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2019 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2020 .init = pci_plx9050_init,
2021 .setup = pci_default_setup,
2022 .exit = pci_plx9050_exit,
2023 },
2024 {
2025 .vendor = PCI_VENDOR_ID_PLX,
2026 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2027 .subvendor = PCI_VENDOR_ID_PLX,
2028 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2029 .init = pci_plx9050_init,
2030 .setup = pci_default_setup,
2031 .exit = pci_plx9050_exit,
2032 },
2033 {
2034 .vendor = PCI_VENDOR_ID_ACCESIO,
2035 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
2036 .subvendor = PCI_ANY_ID,
2037 .subdevice = PCI_ANY_ID,
2038 .setup = pci_pericom_setup,
2039 },
2040 {
2041 .vendor = PCI_VENDOR_ID_ACCESIO,
2042 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
2043 .subvendor = PCI_ANY_ID,
2044 .subdevice = PCI_ANY_ID,
2045 .setup = pci_pericom_setup,
2046 },
2047 {
2048 .vendor = PCI_VENDOR_ID_ACCESIO,
2049 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
2050 .subvendor = PCI_ANY_ID,
2051 .subdevice = PCI_ANY_ID,
2052 .setup = pci_pericom_setup,
2053 },
2054 {
2055 .vendor = PCI_VENDOR_ID_ACCESIO,
2056 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
2057 .subvendor = PCI_ANY_ID,
2058 .subdevice = PCI_ANY_ID,
2059 .setup = pci_pericom_setup,
2060 },
2061 {
2062 .vendor = PCI_VENDOR_ID_ACCESIO,
2063 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
2064 .subvendor = PCI_ANY_ID,
2065 .subdevice = PCI_ANY_ID,
2066 .setup = pci_pericom_setup,
2067 },
2068 {
2069 .vendor = PCI_VENDOR_ID_ACCESIO,
2070 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
2071 .subvendor = PCI_ANY_ID,
2072 .subdevice = PCI_ANY_ID,
2073 .setup = pci_pericom_setup,
2074 },
2075 {
2076 .vendor = PCI_VENDOR_ID_ACCESIO,
2077 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
2078 .subvendor = PCI_ANY_ID,
2079 .subdevice = PCI_ANY_ID,
2080 .setup = pci_pericom_setup,
2081 },
2082 {
2083 .vendor = PCI_VENDOR_ID_ACCESIO,
2084 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
2085 .subvendor = PCI_ANY_ID,
2086 .subdevice = PCI_ANY_ID,
2087 .setup = pci_pericom_setup,
2088 },
2089 {
2090 .vendor = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
2091 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
2092 .subvendor = PCI_ANY_ID,
2093 .subdevice = PCI_ANY_ID,
2094 .setup = pci_pericom_setup,
2095 },
2096 {
2097 .vendor = PCI_VENDOR_ID_ACCESIO,
2098 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
2099 .subvendor = PCI_ANY_ID,
2100 .subdevice = PCI_ANY_ID,
2101 .setup = pci_pericom_setup,
2102 },
2103 {
2104 .vendor = PCI_VENDOR_ID_ACCESIO,
2105 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
2106 .subvendor = PCI_ANY_ID,
2107 .subdevice = PCI_ANY_ID,
2108 .setup = pci_pericom_setup,
2109 },
2110 {
2111 .vendor = PCI_VENDOR_ID_ACCESIO,
2112 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
2113 .subvendor = PCI_ANY_ID,
2114 .subdevice = PCI_ANY_ID,
2115 .setup = pci_pericom_setup,
2116 },
2117 {
2118 .vendor = PCI_VENDOR_ID_ACCESIO,
2119 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
2120 .subvendor = PCI_ANY_ID,
2121 .subdevice = PCI_ANY_ID,
2122 .setup = pci_pericom_setup,
2123 },
2124 {
2125 .vendor = PCI_VENDOR_ID_ACCESIO,
2126 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
2127 .subvendor = PCI_ANY_ID,
2128 .subdevice = PCI_ANY_ID,
2129 .setup = pci_pericom_setup,
2130 },
2131 {
2132 .vendor = PCI_VENDOR_ID_ACCESIO,
2133 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
2134 .subvendor = PCI_ANY_ID,
2135 .subdevice = PCI_ANY_ID,
2136 .setup = pci_pericom_setup,
2137 },
2138 /*
2139 * SBS Technologies, Inc., PMC-OCTALPRO 232
2140 */
2141 {
2142 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2143 .device = PCI_DEVICE_ID_OCTPRO,
2144 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2145 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2146 .init = sbs_init,
2147 .setup = sbs_setup,
2148 .exit = sbs_exit,
2149 },
2150 /*
2151 * SBS Technologies, Inc., PMC-OCTALPRO 422
2152 */
2153 {
2154 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2155 .device = PCI_DEVICE_ID_OCTPRO,
2156 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2157 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2158 .init = sbs_init,
2159 .setup = sbs_setup,
2160 .exit = sbs_exit,
2161 },
2162 /*
2163 * SBS Technologies, Inc., P-Octal 232
2164 */
2165 {
2166 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2167 .device = PCI_DEVICE_ID_OCTPRO,
2168 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2169 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2170 .init = sbs_init,
2171 .setup = sbs_setup,
2172 .exit = sbs_exit,
2173 },
2174 /*
2175 * SBS Technologies, Inc., P-Octal 422
2176 */
2177 {
2178 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2179 .device = PCI_DEVICE_ID_OCTPRO,
2180 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2181 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2182 .init = sbs_init,
2183 .setup = sbs_setup,
2184 .exit = sbs_exit,
2185 },
2186 /*
2187 * SIIG cards - these may be called via parport_serial
2188 */
2189 {
2190 .vendor = PCI_VENDOR_ID_SIIG,
2191 .device = PCI_ANY_ID,
2192 .subvendor = PCI_ANY_ID,
2193 .subdevice = PCI_ANY_ID,
2194 .init = pci_siig_init,
2195 .setup = pci_siig_setup,
2196 },
2197 /*
2198 * Titan cards
2199 */
2200 {
2201 .vendor = PCI_VENDOR_ID_TITAN,
2202 .device = PCI_DEVICE_ID_TITAN_400L,
2203 .subvendor = PCI_ANY_ID,
2204 .subdevice = PCI_ANY_ID,
2205 .setup = titan_400l_800l_setup,
2206 },
2207 {
2208 .vendor = PCI_VENDOR_ID_TITAN,
2209 .device = PCI_DEVICE_ID_TITAN_800L,
2210 .subvendor = PCI_ANY_ID,
2211 .subdevice = PCI_ANY_ID,
2212 .setup = titan_400l_800l_setup,
2213 },
2214 /*
2215 * Timedia cards
2216 */
2217 {
2218 .vendor = PCI_VENDOR_ID_TIMEDIA,
2219 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2220 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2221 .subdevice = PCI_ANY_ID,
2222 .probe = pci_timedia_probe,
2223 .init = pci_timedia_init,
2224 .setup = pci_timedia_setup,
2225 },
2226 {
2227 .vendor = PCI_VENDOR_ID_TIMEDIA,
2228 .device = PCI_ANY_ID,
2229 .subvendor = PCI_ANY_ID,
2230 .subdevice = PCI_ANY_ID,
2231 .setup = pci_timedia_setup,
2232 },
2233 /*
2234 * SUNIX (Timedia) cards
2235 * Do not "probe" for these cards as there is at least one combination
2236 * card that should be handled by parport_pc that doesn't match the
2237 * rule in pci_timedia_probe.
2238 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2239 * There are some boards with part number SER5037AL that report
2240 * subdevice ID 0x0002.
2241 */
2242 {
2243 .vendor = PCI_VENDOR_ID_SUNIX,
2244 .device = PCI_DEVICE_ID_SUNIX_1999,
2245 .subvendor = PCI_VENDOR_ID_SUNIX,
2246 .subdevice = PCI_ANY_ID,
2247 .init = pci_timedia_init,
2248 .setup = pci_timedia_setup,
2249 },
2250 /*
2251 * Xircom cards
2252 */
2253 {
2254 .vendor = PCI_VENDOR_ID_XIRCOM,
2255 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2256 .subvendor = PCI_ANY_ID,
2257 .subdevice = PCI_ANY_ID,
2258 .init = pci_xircom_init,
2259 .setup = pci_default_setup,
2260 },
2261 /*
2262 * Netmos cards - these may be called via parport_serial
2263 */
2264 {
2265 .vendor = PCI_VENDOR_ID_NETMOS,
2266 .device = PCI_ANY_ID,
2267 .subvendor = PCI_ANY_ID,
2268 .subdevice = PCI_ANY_ID,
2269 .init = pci_netmos_init,
2270 .setup = pci_netmos_9900_setup,
2271 },
2272 /*
2273 * EndRun Technologies
2274 */
2275 {
2276 .vendor = PCI_VENDOR_ID_ENDRUN,
2277 .device = PCI_ANY_ID,
2278 .subvendor = PCI_ANY_ID,
2279 .subdevice = PCI_ANY_ID,
2280 .init = pci_endrun_init,
2281 .setup = pci_default_setup,
2282 },
2283 /*
2284 * For Oxford Semiconductor Tornado based devices
2285 */
2286 {
2287 .vendor = PCI_VENDOR_ID_OXSEMI,
2288 .device = PCI_ANY_ID,
2289 .subvendor = PCI_ANY_ID,
2290 .subdevice = PCI_ANY_ID,
2291 .init = pci_oxsemi_tornado_init,
2292 .setup = pci_default_setup,
2293 },
2294 {
2295 .vendor = PCI_VENDOR_ID_MAINPINE,
2296 .device = PCI_ANY_ID,
2297 .subvendor = PCI_ANY_ID,
2298 .subdevice = PCI_ANY_ID,
2299 .init = pci_oxsemi_tornado_init,
2300 .setup = pci_default_setup,
2301 },
2302 {
2303 .vendor = PCI_VENDOR_ID_DIGI,
2304 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2305 .subvendor = PCI_SUBVENDOR_ID_IBM,
2306 .subdevice = PCI_ANY_ID,
2307 .init = pci_oxsemi_tornado_init,
2308 .setup = pci_default_setup,
2309 },
2310 {
2311 .vendor = PCI_VENDOR_ID_INTEL,
2312 .device = 0x8811,
2313 .subvendor = PCI_ANY_ID,
2314 .subdevice = PCI_ANY_ID,
2315 .init = pci_eg20t_init,
2316 .setup = pci_default_setup,
2317 },
2318 {
2319 .vendor = PCI_VENDOR_ID_INTEL,
2320 .device = 0x8812,
2321 .subvendor = PCI_ANY_ID,
2322 .subdevice = PCI_ANY_ID,
2323 .init = pci_eg20t_init,
2324 .setup = pci_default_setup,
2325 },
2326 {
2327 .vendor = PCI_VENDOR_ID_INTEL,
2328 .device = 0x8813,
2329 .subvendor = PCI_ANY_ID,
2330 .subdevice = PCI_ANY_ID,
2331 .init = pci_eg20t_init,
2332 .setup = pci_default_setup,
2333 },
2334 {
2335 .vendor = PCI_VENDOR_ID_INTEL,
2336 .device = 0x8814,
2337 .subvendor = PCI_ANY_ID,
2338 .subdevice = PCI_ANY_ID,
2339 .init = pci_eg20t_init,
2340 .setup = pci_default_setup,
2341 },
2342 {
2343 .vendor = 0x10DB,
2344 .device = 0x8027,
2345 .subvendor = PCI_ANY_ID,
2346 .subdevice = PCI_ANY_ID,
2347 .init = pci_eg20t_init,
2348 .setup = pci_default_setup,
2349 },
2350 {
2351 .vendor = 0x10DB,
2352 .device = 0x8028,
2353 .subvendor = PCI_ANY_ID,
2354 .subdevice = PCI_ANY_ID,
2355 .init = pci_eg20t_init,
2356 .setup = pci_default_setup,
2357 },
2358 {
2359 .vendor = 0x10DB,
2360 .device = 0x8029,
2361 .subvendor = PCI_ANY_ID,
2362 .subdevice = PCI_ANY_ID,
2363 .init = pci_eg20t_init,
2364 .setup = pci_default_setup,
2365 },
2366 {
2367 .vendor = 0x10DB,
2368 .device = 0x800C,
2369 .subvendor = PCI_ANY_ID,
2370 .subdevice = PCI_ANY_ID,
2371 .init = pci_eg20t_init,
2372 .setup = pci_default_setup,
2373 },
2374 {
2375 .vendor = 0x10DB,
2376 .device = 0x800D,
2377 .subvendor = PCI_ANY_ID,
2378 .subdevice = PCI_ANY_ID,
2379 .init = pci_eg20t_init,
2380 .setup = pci_default_setup,
2381 },
2382 /*
2383 * Cronyx Omega PCI (PLX-chip based)
2384 */
2385 {
2386 .vendor = PCI_VENDOR_ID_PLX,
2387 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2388 .subvendor = PCI_ANY_ID,
2389 .subdevice = PCI_ANY_ID,
2390 .setup = pci_omegapci_setup,
2391 },
2392 /* WCH CH353 1S1P card (16550 clone) */
2393 {
2394 .vendor = PCI_VENDOR_ID_WCH,
2395 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2396 .subvendor = PCI_ANY_ID,
2397 .subdevice = PCI_ANY_ID,
2398 .setup = pci_wch_ch353_setup,
2399 },
2400 /* WCH CH353 2S1P card (16550 clone) */
2401 {
2402 .vendor = PCI_VENDOR_ID_WCH,
2403 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2404 .subvendor = PCI_ANY_ID,
2405 .subdevice = PCI_ANY_ID,
2406 .setup = pci_wch_ch353_setup,
2407 },
2408 /* WCH CH353 4S card (16550 clone) */
2409 {
2410 .vendor = PCI_VENDOR_ID_WCH,
2411 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2412 .subvendor = PCI_ANY_ID,
2413 .subdevice = PCI_ANY_ID,
2414 .setup = pci_wch_ch353_setup,
2415 },
2416 /* WCH CH353 2S1PF card (16550 clone) */
2417 {
2418 .vendor = PCI_VENDOR_ID_WCH,
2419 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2420 .subvendor = PCI_ANY_ID,
2421 .subdevice = PCI_ANY_ID,
2422 .setup = pci_wch_ch353_setup,
2423 },
2424 /* WCH CH352 2S card (16550 clone) */
2425 {
2426 .vendor = PCI_VENDOR_ID_WCH,
2427 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2428 .subvendor = PCI_ANY_ID,
2429 .subdevice = PCI_ANY_ID,
2430 .setup = pci_wch_ch353_setup,
2431 },
2432 /* WCH CH355 4S card (16550 clone) */
2433 {
2434 .vendor = PCI_VENDOR_ID_WCH,
2435 .device = PCI_DEVICE_ID_WCH_CH355_4S,
2436 .subvendor = PCI_ANY_ID,
2437 .subdevice = PCI_ANY_ID,
2438 .setup = pci_wch_ch355_setup,
2439 },
2440 /* WCH CH382 2S card (16850 clone) */
2441 {
2442 .vendor = PCIE_VENDOR_ID_WCH,
2443 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2444 .subvendor = PCI_ANY_ID,
2445 .subdevice = PCI_ANY_ID,
2446 .setup = pci_wch_ch38x_setup,
2447 },
2448 /* WCH CH382 2S1P card (16850 clone) */
2449 {
2450 .vendor = PCIE_VENDOR_ID_WCH,
2451 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2452 .subvendor = PCI_ANY_ID,
2453 .subdevice = PCI_ANY_ID,
2454 .setup = pci_wch_ch38x_setup,
2455 },
2456 /* WCH CH384 4S card (16850 clone) */
2457 {
2458 .vendor = PCIE_VENDOR_ID_WCH,
2459 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2460 .subvendor = PCI_ANY_ID,
2461 .subdevice = PCI_ANY_ID,
2462 .setup = pci_wch_ch38x_setup,
2463 },
2464 /*
2465 * ASIX devices with FIFO bug
2466 */
2467 {
2468 .vendor = PCI_VENDOR_ID_ASIX,
2469 .device = PCI_ANY_ID,
2470 .subvendor = PCI_ANY_ID,
2471 .subdevice = PCI_ANY_ID,
2472 .setup = pci_asix_setup,
2473 },
2474 /*
2475 * Broadcom TruManage (NetXtreme)
2476 */
2477 {
2478 .vendor = PCI_VENDOR_ID_BROADCOM,
2479 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2480 .subvendor = PCI_ANY_ID,
2481 .subdevice = PCI_ANY_ID,
2482 .setup = pci_brcm_trumanage_setup,
2483 },
2484 {
2485 .vendor = 0x1c29,
2486 .device = 0x1104,
2487 .subvendor = PCI_ANY_ID,
2488 .subdevice = PCI_ANY_ID,
2489 .setup = pci_fintek_setup,
2490 .init = pci_fintek_init,
2491 },
2492 {
2493 .vendor = 0x1c29,
2494 .device = 0x1108,
2495 .subvendor = PCI_ANY_ID,
2496 .subdevice = PCI_ANY_ID,
2497 .setup = pci_fintek_setup,
2498 .init = pci_fintek_init,
2499 },
2500 {
2501 .vendor = 0x1c29,
2502 .device = 0x1112,
2503 .subvendor = PCI_ANY_ID,
2504 .subdevice = PCI_ANY_ID,
2505 .setup = pci_fintek_setup,
2506 .init = pci_fintek_init,
2507 },
2508
2509 /*
2510 * Default "match everything" terminator entry
2511 */
2512 {
2513 .vendor = PCI_ANY_ID,
2514 .device = PCI_ANY_ID,
2515 .subvendor = PCI_ANY_ID,
2516 .subdevice = PCI_ANY_ID,
2517 .setup = pci_default_setup,
2518 }
2519 };
2520
2521 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2522 {
2523 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2524 }
2525
2526 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2527 {
2528 struct pci_serial_quirk *quirk;
2529
2530 for (quirk = pci_serial_quirks; ; quirk++)
2531 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2532 quirk_id_matches(quirk->device, dev->device) &&
2533 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2534 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2535 break;
2536 return quirk;
2537 }
2538
2539 static inline int get_pci_irq(struct pci_dev *dev,
2540 const struct pciserial_board *board)
2541 {
2542 if (board->flags & FL_NOIRQ)
2543 return 0;
2544 else
2545 return dev->irq;
2546 }
2547
2548 /*
2549 * This is the configuration table for all of the PCI serial boards
2550 * which we support. It is directly indexed by the pci_board_num_t enum
2551 * value, which is encoded in the pci_device_id PCI probe table's
2552 * driver_data member.
2553 *
2554 * The makeup of these names are:
2555 * pbn_bn{_bt}_n_baud{_offsetinhex}
2556 *
2557 * bn = PCI BAR number
2558 * bt = Index using PCI BARs
2559 * n = number of serial ports
2560 * baud = baud rate
2561 * offsetinhex = offset for each sequential port (in hex)
2562 *
2563 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2564 *
2565 * Please note: in theory if n = 1, _bt infix should make no difference.
2566 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2567 */
2568 enum pci_board_num_t {
2569 pbn_default = 0,
2570
2571 pbn_b0_1_115200,
2572 pbn_b0_2_115200,
2573 pbn_b0_4_115200,
2574 pbn_b0_5_115200,
2575 pbn_b0_8_115200,
2576
2577 pbn_b0_1_921600,
2578 pbn_b0_2_921600,
2579 pbn_b0_4_921600,
2580
2581 pbn_b0_2_1130000,
2582
2583 pbn_b0_4_1152000,
2584
2585 pbn_b0_4_1250000,
2586
2587 pbn_b0_2_1843200,
2588 pbn_b0_4_1843200,
2589
2590 pbn_b0_1_4000000,
2591
2592 pbn_b0_bt_1_115200,
2593 pbn_b0_bt_2_115200,
2594 pbn_b0_bt_4_115200,
2595 pbn_b0_bt_8_115200,
2596
2597 pbn_b0_bt_1_460800,
2598 pbn_b0_bt_2_460800,
2599 pbn_b0_bt_4_460800,
2600
2601 pbn_b0_bt_1_921600,
2602 pbn_b0_bt_2_921600,
2603 pbn_b0_bt_4_921600,
2604 pbn_b0_bt_8_921600,
2605
2606 pbn_b1_1_115200,
2607 pbn_b1_2_115200,
2608 pbn_b1_4_115200,
2609 pbn_b1_8_115200,
2610 pbn_b1_16_115200,
2611
2612 pbn_b1_1_921600,
2613 pbn_b1_2_921600,
2614 pbn_b1_4_921600,
2615 pbn_b1_8_921600,
2616
2617 pbn_b1_2_1250000,
2618
2619 pbn_b1_bt_1_115200,
2620 pbn_b1_bt_2_115200,
2621 pbn_b1_bt_4_115200,
2622
2623 pbn_b1_bt_2_921600,
2624
2625 pbn_b1_1_1382400,
2626 pbn_b1_2_1382400,
2627 pbn_b1_4_1382400,
2628 pbn_b1_8_1382400,
2629
2630 pbn_b2_1_115200,
2631 pbn_b2_2_115200,
2632 pbn_b2_4_115200,
2633 pbn_b2_8_115200,
2634
2635 pbn_b2_1_460800,
2636 pbn_b2_4_460800,
2637 pbn_b2_8_460800,
2638 pbn_b2_16_460800,
2639
2640 pbn_b2_1_921600,
2641 pbn_b2_4_921600,
2642 pbn_b2_8_921600,
2643
2644 pbn_b2_8_1152000,
2645
2646 pbn_b2_bt_1_115200,
2647 pbn_b2_bt_2_115200,
2648 pbn_b2_bt_4_115200,
2649
2650 pbn_b2_bt_2_921600,
2651 pbn_b2_bt_4_921600,
2652
2653 pbn_b3_2_115200,
2654 pbn_b3_4_115200,
2655 pbn_b3_8_115200,
2656
2657 pbn_b4_bt_2_921600,
2658 pbn_b4_bt_4_921600,
2659 pbn_b4_bt_8_921600,
2660
2661 /*
2662 * Board-specific versions.
2663 */
2664 pbn_panacom,
2665 pbn_panacom2,
2666 pbn_panacom4,
2667 pbn_plx_romulus,
2668 pbn_endrun_2_4000000,
2669 pbn_oxsemi,
2670 pbn_oxsemi_1_4000000,
2671 pbn_oxsemi_2_4000000,
2672 pbn_oxsemi_4_4000000,
2673 pbn_oxsemi_8_4000000,
2674 pbn_intel_i960,
2675 pbn_sgi_ioc3,
2676 pbn_computone_4,
2677 pbn_computone_6,
2678 pbn_computone_8,
2679 pbn_sbsxrsio,
2680 pbn_pasemi_1682M,
2681 pbn_ni8430_2,
2682 pbn_ni8430_4,
2683 pbn_ni8430_8,
2684 pbn_ni8430_16,
2685 pbn_ADDIDATA_PCIe_1_3906250,
2686 pbn_ADDIDATA_PCIe_2_3906250,
2687 pbn_ADDIDATA_PCIe_4_3906250,
2688 pbn_ADDIDATA_PCIe_8_3906250,
2689 pbn_ce4100_1_115200,
2690 pbn_omegapci,
2691 pbn_NETMOS9900_2s_115200,
2692 pbn_brcm_trumanage,
2693 pbn_fintek_4,
2694 pbn_fintek_8,
2695 pbn_fintek_12,
2696 pbn_wch382_2,
2697 pbn_wch384_4,
2698 pbn_pericom_PI7C9X7951,
2699 pbn_pericom_PI7C9X7952,
2700 pbn_pericom_PI7C9X7954,
2701 pbn_pericom_PI7C9X7958,
2702 };
2703
2704 /*
2705 * uart_offset - the space between channels
2706 * reg_shift - describes how the UART registers are mapped
2707 * to PCI memory by the card.
2708 * For example IER register on SBS, Inc. PMC-OctPro is located at
2709 * offset 0x10 from the UART base, while UART_IER is defined as 1
2710 * in include/linux/serial_reg.h,
2711 * see first lines of serial_in() and serial_out() in 8250.c
2712 */
2713
2714 static struct pciserial_board pci_boards[] = {
2715 [pbn_default] = {
2716 .flags = FL_BASE0,
2717 .num_ports = 1,
2718 .base_baud = 115200,
2719 .uart_offset = 8,
2720 },
2721 [pbn_b0_1_115200] = {
2722 .flags = FL_BASE0,
2723 .num_ports = 1,
2724 .base_baud = 115200,
2725 .uart_offset = 8,
2726 },
2727 [pbn_b0_2_115200] = {
2728 .flags = FL_BASE0,
2729 .num_ports = 2,
2730 .base_baud = 115200,
2731 .uart_offset = 8,
2732 },
2733 [pbn_b0_4_115200] = {
2734 .flags = FL_BASE0,
2735 .num_ports = 4,
2736 .base_baud = 115200,
2737 .uart_offset = 8,
2738 },
2739 [pbn_b0_5_115200] = {
2740 .flags = FL_BASE0,
2741 .num_ports = 5,
2742 .base_baud = 115200,
2743 .uart_offset = 8,
2744 },
2745 [pbn_b0_8_115200] = {
2746 .flags = FL_BASE0,
2747 .num_ports = 8,
2748 .base_baud = 115200,
2749 .uart_offset = 8,
2750 },
2751 [pbn_b0_1_921600] = {
2752 .flags = FL_BASE0,
2753 .num_ports = 1,
2754 .base_baud = 921600,
2755 .uart_offset = 8,
2756 },
2757 [pbn_b0_2_921600] = {
2758 .flags = FL_BASE0,
2759 .num_ports = 2,
2760 .base_baud = 921600,
2761 .uart_offset = 8,
2762 },
2763 [pbn_b0_4_921600] = {
2764 .flags = FL_BASE0,
2765 .num_ports = 4,
2766 .base_baud = 921600,
2767 .uart_offset = 8,
2768 },
2769
2770 [pbn_b0_2_1130000] = {
2771 .flags = FL_BASE0,
2772 .num_ports = 2,
2773 .base_baud = 1130000,
2774 .uart_offset = 8,
2775 },
2776
2777 [pbn_b0_4_1152000] = {
2778 .flags = FL_BASE0,
2779 .num_ports = 4,
2780 .base_baud = 1152000,
2781 .uart_offset = 8,
2782 },
2783
2784 [pbn_b0_4_1250000] = {
2785 .flags = FL_BASE0,
2786 .num_ports = 4,
2787 .base_baud = 1250000,
2788 .uart_offset = 8,
2789 },
2790
2791 [pbn_b0_2_1843200] = {
2792 .flags = FL_BASE0,
2793 .num_ports = 2,
2794 .base_baud = 1843200,
2795 .uart_offset = 8,
2796 },
2797 [pbn_b0_4_1843200] = {
2798 .flags = FL_BASE0,
2799 .num_ports = 4,
2800 .base_baud = 1843200,
2801 .uart_offset = 8,
2802 },
2803
2804 [pbn_b0_1_4000000] = {
2805 .flags = FL_BASE0,
2806 .num_ports = 1,
2807 .base_baud = 4000000,
2808 .uart_offset = 8,
2809 },
2810
2811 [pbn_b0_bt_1_115200] = {
2812 .flags = FL_BASE0|FL_BASE_BARS,
2813 .num_ports = 1,
2814 .base_baud = 115200,
2815 .uart_offset = 8,
2816 },
2817 [pbn_b0_bt_2_115200] = {
2818 .flags = FL_BASE0|FL_BASE_BARS,
2819 .num_ports = 2,
2820 .base_baud = 115200,
2821 .uart_offset = 8,
2822 },
2823 [pbn_b0_bt_4_115200] = {
2824 .flags = FL_BASE0|FL_BASE_BARS,
2825 .num_ports = 4,
2826 .base_baud = 115200,
2827 .uart_offset = 8,
2828 },
2829 [pbn_b0_bt_8_115200] = {
2830 .flags = FL_BASE0|FL_BASE_BARS,
2831 .num_ports = 8,
2832 .base_baud = 115200,
2833 .uart_offset = 8,
2834 },
2835
2836 [pbn_b0_bt_1_460800] = {
2837 .flags = FL_BASE0|FL_BASE_BARS,
2838 .num_ports = 1,
2839 .base_baud = 460800,
2840 .uart_offset = 8,
2841 },
2842 [pbn_b0_bt_2_460800] = {
2843 .flags = FL_BASE0|FL_BASE_BARS,
2844 .num_ports = 2,
2845 .base_baud = 460800,
2846 .uart_offset = 8,
2847 },
2848 [pbn_b0_bt_4_460800] = {
2849 .flags = FL_BASE0|FL_BASE_BARS,
2850 .num_ports = 4,
2851 .base_baud = 460800,
2852 .uart_offset = 8,
2853 },
2854
2855 [pbn_b0_bt_1_921600] = {
2856 .flags = FL_BASE0|FL_BASE_BARS,
2857 .num_ports = 1,
2858 .base_baud = 921600,
2859 .uart_offset = 8,
2860 },
2861 [pbn_b0_bt_2_921600] = {
2862 .flags = FL_BASE0|FL_BASE_BARS,
2863 .num_ports = 2,
2864 .base_baud = 921600,
2865 .uart_offset = 8,
2866 },
2867 [pbn_b0_bt_4_921600] = {
2868 .flags = FL_BASE0|FL_BASE_BARS,
2869 .num_ports = 4,
2870 .base_baud = 921600,
2871 .uart_offset = 8,
2872 },
2873 [pbn_b0_bt_8_921600] = {
2874 .flags = FL_BASE0|FL_BASE_BARS,
2875 .num_ports = 8,
2876 .base_baud = 921600,
2877 .uart_offset = 8,
2878 },
2879
2880 [pbn_b1_1_115200] = {
2881 .flags = FL_BASE1,
2882 .num_ports = 1,
2883 .base_baud = 115200,
2884 .uart_offset = 8,
2885 },
2886 [pbn_b1_2_115200] = {
2887 .flags = FL_BASE1,
2888 .num_ports = 2,
2889 .base_baud = 115200,
2890 .uart_offset = 8,
2891 },
2892 [pbn_b1_4_115200] = {
2893 .flags = FL_BASE1,
2894 .num_ports = 4,
2895 .base_baud = 115200,
2896 .uart_offset = 8,
2897 },
2898 [pbn_b1_8_115200] = {
2899 .flags = FL_BASE1,
2900 .num_ports = 8,
2901 .base_baud = 115200,
2902 .uart_offset = 8,
2903 },
2904 [pbn_b1_16_115200] = {
2905 .flags = FL_BASE1,
2906 .num_ports = 16,
2907 .base_baud = 115200,
2908 .uart_offset = 8,
2909 },
2910
2911 [pbn_b1_1_921600] = {
2912 .flags = FL_BASE1,
2913 .num_ports = 1,
2914 .base_baud = 921600,
2915 .uart_offset = 8,
2916 },
2917 [pbn_b1_2_921600] = {
2918 .flags = FL_BASE1,
2919 .num_ports = 2,
2920 .base_baud = 921600,
2921 .uart_offset = 8,
2922 },
2923 [pbn_b1_4_921600] = {
2924 .flags = FL_BASE1,
2925 .num_ports = 4,
2926 .base_baud = 921600,
2927 .uart_offset = 8,
2928 },
2929 [pbn_b1_8_921600] = {
2930 .flags = FL_BASE1,
2931 .num_ports = 8,
2932 .base_baud = 921600,
2933 .uart_offset = 8,
2934 },
2935 [pbn_b1_2_1250000] = {
2936 .flags = FL_BASE1,
2937 .num_ports = 2,
2938 .base_baud = 1250000,
2939 .uart_offset = 8,
2940 },
2941
2942 [pbn_b1_bt_1_115200] = {
2943 .flags = FL_BASE1|FL_BASE_BARS,
2944 .num_ports = 1,
2945 .base_baud = 115200,
2946 .uart_offset = 8,
2947 },
2948 [pbn_b1_bt_2_115200] = {
2949 .flags = FL_BASE1|FL_BASE_BARS,
2950 .num_ports = 2,
2951 .base_baud = 115200,
2952 .uart_offset = 8,
2953 },
2954 [pbn_b1_bt_4_115200] = {
2955 .flags = FL_BASE1|FL_BASE_BARS,
2956 .num_ports = 4,
2957 .base_baud = 115200,
2958 .uart_offset = 8,
2959 },
2960
2961 [pbn_b1_bt_2_921600] = {
2962 .flags = FL_BASE1|FL_BASE_BARS,
2963 .num_ports = 2,
2964 .base_baud = 921600,
2965 .uart_offset = 8,
2966 },
2967
2968 [pbn_b1_1_1382400] = {
2969 .flags = FL_BASE1,
2970 .num_ports = 1,
2971 .base_baud = 1382400,
2972 .uart_offset = 8,
2973 },
2974 [pbn_b1_2_1382400] = {
2975 .flags = FL_BASE1,
2976 .num_ports = 2,
2977 .base_baud = 1382400,
2978 .uart_offset = 8,
2979 },
2980 [pbn_b1_4_1382400] = {
2981 .flags = FL_BASE1,
2982 .num_ports = 4,
2983 .base_baud = 1382400,
2984 .uart_offset = 8,
2985 },
2986 [pbn_b1_8_1382400] = {
2987 .flags = FL_BASE1,
2988 .num_ports = 8,
2989 .base_baud = 1382400,
2990 .uart_offset = 8,
2991 },
2992
2993 [pbn_b2_1_115200] = {
2994 .flags = FL_BASE2,
2995 .num_ports = 1,
2996 .base_baud = 115200,
2997 .uart_offset = 8,
2998 },
2999 [pbn_b2_2_115200] = {
3000 .flags = FL_BASE2,
3001 .num_ports = 2,
3002 .base_baud = 115200,
3003 .uart_offset = 8,
3004 },
3005 [pbn_b2_4_115200] = {
3006 .flags = FL_BASE2,
3007 .num_ports = 4,
3008 .base_baud = 115200,
3009 .uart_offset = 8,
3010 },
3011 [pbn_b2_8_115200] = {
3012 .flags = FL_BASE2,
3013 .num_ports = 8,
3014 .base_baud = 115200,
3015 .uart_offset = 8,
3016 },
3017
3018 [pbn_b2_1_460800] = {
3019 .flags = FL_BASE2,
3020 .num_ports = 1,
3021 .base_baud = 460800,
3022 .uart_offset = 8,
3023 },
3024 [pbn_b2_4_460800] = {
3025 .flags = FL_BASE2,
3026 .num_ports = 4,
3027 .base_baud = 460800,
3028 .uart_offset = 8,
3029 },
3030 [pbn_b2_8_460800] = {
3031 .flags = FL_BASE2,
3032 .num_ports = 8,
3033 .base_baud = 460800,
3034 .uart_offset = 8,
3035 },
3036 [pbn_b2_16_460800] = {
3037 .flags = FL_BASE2,
3038 .num_ports = 16,
3039 .base_baud = 460800,
3040 .uart_offset = 8,
3041 },
3042
3043 [pbn_b2_1_921600] = {
3044 .flags = FL_BASE2,
3045 .num_ports = 1,
3046 .base_baud = 921600,
3047 .uart_offset = 8,
3048 },
3049 [pbn_b2_4_921600] = {
3050 .flags = FL_BASE2,
3051 .num_ports = 4,
3052 .base_baud = 921600,
3053 .uart_offset = 8,
3054 },
3055 [pbn_b2_8_921600] = {
3056 .flags = FL_BASE2,
3057 .num_ports = 8,
3058 .base_baud = 921600,
3059 .uart_offset = 8,
3060 },
3061
3062 [pbn_b2_8_1152000] = {
3063 .flags = FL_BASE2,
3064 .num_ports = 8,
3065 .base_baud = 1152000,
3066 .uart_offset = 8,
3067 },
3068
3069 [pbn_b2_bt_1_115200] = {
3070 .flags = FL_BASE2|FL_BASE_BARS,
3071 .num_ports = 1,
3072 .base_baud = 115200,
3073 .uart_offset = 8,
3074 },
3075 [pbn_b2_bt_2_115200] = {
3076 .flags = FL_BASE2|FL_BASE_BARS,
3077 .num_ports = 2,
3078 .base_baud = 115200,
3079 .uart_offset = 8,
3080 },
3081 [pbn_b2_bt_4_115200] = {
3082 .flags = FL_BASE2|FL_BASE_BARS,
3083 .num_ports = 4,
3084 .base_baud = 115200,
3085 .uart_offset = 8,
3086 },
3087
3088 [pbn_b2_bt_2_921600] = {
3089 .flags = FL_BASE2|FL_BASE_BARS,
3090 .num_ports = 2,
3091 .base_baud = 921600,
3092 .uart_offset = 8,
3093 },
3094 [pbn_b2_bt_4_921600] = {
3095 .flags = FL_BASE2|FL_BASE_BARS,
3096 .num_ports = 4,
3097 .base_baud = 921600,
3098 .uart_offset = 8,
3099 },
3100
3101 [pbn_b3_2_115200] = {
3102 .flags = FL_BASE3,
3103 .num_ports = 2,
3104 .base_baud = 115200,
3105 .uart_offset = 8,
3106 },
3107 [pbn_b3_4_115200] = {
3108 .flags = FL_BASE3,
3109 .num_ports = 4,
3110 .base_baud = 115200,
3111 .uart_offset = 8,
3112 },
3113 [pbn_b3_8_115200] = {
3114 .flags = FL_BASE3,
3115 .num_ports = 8,
3116 .base_baud = 115200,
3117 .uart_offset = 8,
3118 },
3119
3120 [pbn_b4_bt_2_921600] = {
3121 .flags = FL_BASE4,
3122 .num_ports = 2,
3123 .base_baud = 921600,
3124 .uart_offset = 8,
3125 },
3126 [pbn_b4_bt_4_921600] = {
3127 .flags = FL_BASE4,
3128 .num_ports = 4,
3129 .base_baud = 921600,
3130 .uart_offset = 8,
3131 },
3132 [pbn_b4_bt_8_921600] = {
3133 .flags = FL_BASE4,
3134 .num_ports = 8,
3135 .base_baud = 921600,
3136 .uart_offset = 8,
3137 },
3138
3139 /*
3140 * Entries following this are board-specific.
3141 */
3142
3143 /*
3144 * Panacom - IOMEM
3145 */
3146 [pbn_panacom] = {
3147 .flags = FL_BASE2,
3148 .num_ports = 2,
3149 .base_baud = 921600,
3150 .uart_offset = 0x400,
3151 .reg_shift = 7,
3152 },
3153 [pbn_panacom2] = {
3154 .flags = FL_BASE2|FL_BASE_BARS,
3155 .num_ports = 2,
3156 .base_baud = 921600,
3157 .uart_offset = 0x400,
3158 .reg_shift = 7,
3159 },
3160 [pbn_panacom4] = {
3161 .flags = FL_BASE2|FL_BASE_BARS,
3162 .num_ports = 4,
3163 .base_baud = 921600,
3164 .uart_offset = 0x400,
3165 .reg_shift = 7,
3166 },
3167
3168 /* I think this entry is broken - the first_offset looks wrong --rmk */
3169 [pbn_plx_romulus] = {
3170 .flags = FL_BASE2,
3171 .num_ports = 4,
3172 .base_baud = 921600,
3173 .uart_offset = 8 << 2,
3174 .reg_shift = 2,
3175 .first_offset = 0x03,
3176 },
3177
3178 /*
3179 * EndRun Technologies
3180 * Uses the size of PCI Base region 0 to
3181 * signal now many ports are available
3182 * 2 port 952 Uart support
3183 */
3184 [pbn_endrun_2_4000000] = {
3185 .flags = FL_BASE0,
3186 .num_ports = 2,
3187 .base_baud = 4000000,
3188 .uart_offset = 0x200,
3189 .first_offset = 0x1000,
3190 },
3191
3192 /*
3193 * This board uses the size of PCI Base region 0 to
3194 * signal now many ports are available
3195 */
3196 [pbn_oxsemi] = {
3197 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3198 .num_ports = 32,
3199 .base_baud = 115200,
3200 .uart_offset = 8,
3201 },
3202 [pbn_oxsemi_1_4000000] = {
3203 .flags = FL_BASE0,
3204 .num_ports = 1,
3205 .base_baud = 4000000,
3206 .uart_offset = 0x200,
3207 .first_offset = 0x1000,
3208 },
3209 [pbn_oxsemi_2_4000000] = {
3210 .flags = FL_BASE0,
3211 .num_ports = 2,
3212 .base_baud = 4000000,
3213 .uart_offset = 0x200,
3214 .first_offset = 0x1000,
3215 },
3216 [pbn_oxsemi_4_4000000] = {
3217 .flags = FL_BASE0,
3218 .num_ports = 4,
3219 .base_baud = 4000000,
3220 .uart_offset = 0x200,
3221 .first_offset = 0x1000,
3222 },
3223 [pbn_oxsemi_8_4000000] = {
3224 .flags = FL_BASE0,
3225 .num_ports = 8,
3226 .base_baud = 4000000,
3227 .uart_offset = 0x200,
3228 .first_offset = 0x1000,
3229 },
3230
3231
3232 /*
3233 * EKF addition for i960 Boards form EKF with serial port.
3234 * Max 256 ports.
3235 */
3236 [pbn_intel_i960] = {
3237 .flags = FL_BASE0,
3238 .num_ports = 32,
3239 .base_baud = 921600,
3240 .uart_offset = 8 << 2,
3241 .reg_shift = 2,
3242 .first_offset = 0x10000,
3243 },
3244 [pbn_sgi_ioc3] = {
3245 .flags = FL_BASE0|FL_NOIRQ,
3246 .num_ports = 1,
3247 .base_baud = 458333,
3248 .uart_offset = 8,
3249 .reg_shift = 0,
3250 .first_offset = 0x20178,
3251 },
3252
3253 /*
3254 * Computone - uses IOMEM.
3255 */
3256 [pbn_computone_4] = {
3257 .flags = FL_BASE0,
3258 .num_ports = 4,
3259 .base_baud = 921600,
3260 .uart_offset = 0x40,
3261 .reg_shift = 2,
3262 .first_offset = 0x200,
3263 },
3264 [pbn_computone_6] = {
3265 .flags = FL_BASE0,
3266 .num_ports = 6,
3267 .base_baud = 921600,
3268 .uart_offset = 0x40,
3269 .reg_shift = 2,
3270 .first_offset = 0x200,
3271 },
3272 [pbn_computone_8] = {
3273 .flags = FL_BASE0,
3274 .num_ports = 8,
3275 .base_baud = 921600,
3276 .uart_offset = 0x40,
3277 .reg_shift = 2,
3278 .first_offset = 0x200,
3279 },
3280 [pbn_sbsxrsio] = {
3281 .flags = FL_BASE0,
3282 .num_ports = 8,
3283 .base_baud = 460800,
3284 .uart_offset = 256,
3285 .reg_shift = 4,
3286 },
3287 /*
3288 * PA Semi PWRficient PA6T-1682M on-chip UART
3289 */
3290 [pbn_pasemi_1682M] = {
3291 .flags = FL_BASE0,
3292 .num_ports = 1,
3293 .base_baud = 8333333,
3294 },
3295 /*
3296 * National Instruments 843x
3297 */
3298 [pbn_ni8430_16] = {
3299 .flags = FL_BASE0,
3300 .num_ports = 16,
3301 .base_baud = 3686400,
3302 .uart_offset = 0x10,
3303 .first_offset = 0x800,
3304 },
3305 [pbn_ni8430_8] = {
3306 .flags = FL_BASE0,
3307 .num_ports = 8,
3308 .base_baud = 3686400,
3309 .uart_offset = 0x10,
3310 .first_offset = 0x800,
3311 },
3312 [pbn_ni8430_4] = {
3313 .flags = FL_BASE0,
3314 .num_ports = 4,
3315 .base_baud = 3686400,
3316 .uart_offset = 0x10,
3317 .first_offset = 0x800,
3318 },
3319 [pbn_ni8430_2] = {
3320 .flags = FL_BASE0,
3321 .num_ports = 2,
3322 .base_baud = 3686400,
3323 .uart_offset = 0x10,
3324 .first_offset = 0x800,
3325 },
3326 /*
3327 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3328 */
3329 [pbn_ADDIDATA_PCIe_1_3906250] = {
3330 .flags = FL_BASE0,
3331 .num_ports = 1,
3332 .base_baud = 3906250,
3333 .uart_offset = 0x200,
3334 .first_offset = 0x1000,
3335 },
3336 [pbn_ADDIDATA_PCIe_2_3906250] = {
3337 .flags = FL_BASE0,
3338 .num_ports = 2,
3339 .base_baud = 3906250,
3340 .uart_offset = 0x200,
3341 .first_offset = 0x1000,
3342 },
3343 [pbn_ADDIDATA_PCIe_4_3906250] = {
3344 .flags = FL_BASE0,
3345 .num_ports = 4,
3346 .base_baud = 3906250,
3347 .uart_offset = 0x200,
3348 .first_offset = 0x1000,
3349 },
3350 [pbn_ADDIDATA_PCIe_8_3906250] = {
3351 .flags = FL_BASE0,
3352 .num_ports = 8,
3353 .base_baud = 3906250,
3354 .uart_offset = 0x200,
3355 .first_offset = 0x1000,
3356 },
3357 [pbn_ce4100_1_115200] = {
3358 .flags = FL_BASE_BARS,
3359 .num_ports = 2,
3360 .base_baud = 921600,
3361 .reg_shift = 2,
3362 },
3363 [pbn_omegapci] = {
3364 .flags = FL_BASE0,
3365 .num_ports = 8,
3366 .base_baud = 115200,
3367 .uart_offset = 0x200,
3368 },
3369 [pbn_NETMOS9900_2s_115200] = {
3370 .flags = FL_BASE0,
3371 .num_ports = 2,
3372 .base_baud = 115200,
3373 },
3374 [pbn_brcm_trumanage] = {
3375 .flags = FL_BASE0,
3376 .num_ports = 1,
3377 .reg_shift = 2,
3378 .base_baud = 115200,
3379 },
3380 [pbn_fintek_4] = {
3381 .num_ports = 4,
3382 .uart_offset = 8,
3383 .base_baud = 115200,
3384 .first_offset = 0x40,
3385 },
3386 [pbn_fintek_8] = {
3387 .num_ports = 8,
3388 .uart_offset = 8,
3389 .base_baud = 115200,
3390 .first_offset = 0x40,
3391 },
3392 [pbn_fintek_12] = {
3393 .num_ports = 12,
3394 .uart_offset = 8,
3395 .base_baud = 115200,
3396 .first_offset = 0x40,
3397 },
3398 [pbn_wch382_2] = {
3399 .flags = FL_BASE0,
3400 .num_ports = 2,
3401 .base_baud = 115200,
3402 .uart_offset = 8,
3403 .first_offset = 0xC0,
3404 },
3405 [pbn_wch384_4] = {
3406 .flags = FL_BASE0,
3407 .num_ports = 4,
3408 .base_baud = 115200,
3409 .uart_offset = 8,
3410 .first_offset = 0xC0,
3411 },
3412 /*
3413 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3414 */
3415 [pbn_pericom_PI7C9X7951] = {
3416 .flags = FL_BASE0,
3417 .num_ports = 1,
3418 .base_baud = 921600,
3419 .uart_offset = 0x8,
3420 },
3421 [pbn_pericom_PI7C9X7952] = {
3422 .flags = FL_BASE0,
3423 .num_ports = 2,
3424 .base_baud = 921600,
3425 .uart_offset = 0x8,
3426 },
3427 [pbn_pericom_PI7C9X7954] = {
3428 .flags = FL_BASE0,
3429 .num_ports = 4,
3430 .base_baud = 921600,
3431 .uart_offset = 0x8,
3432 },
3433 [pbn_pericom_PI7C9X7958] = {
3434 .flags = FL_BASE0,
3435 .num_ports = 8,
3436 .base_baud = 921600,
3437 .uart_offset = 0x8,
3438 },
3439 };
3440
3441 static const struct pci_device_id blacklist[] = {
3442 /* softmodems */
3443 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3444 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3445 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3446
3447 /* multi-io cards handled by parport_serial */
3448 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3449 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3450 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3451
3452 /* Moxa Smartio MUE boards handled by 8250_moxa */
3453 { PCI_VDEVICE(MOXA, 0x1024), },
3454 { PCI_VDEVICE(MOXA, 0x1025), },
3455 { PCI_VDEVICE(MOXA, 0x1045), },
3456 { PCI_VDEVICE(MOXA, 0x1144), },
3457 { PCI_VDEVICE(MOXA, 0x1160), },
3458 { PCI_VDEVICE(MOXA, 0x1161), },
3459 { PCI_VDEVICE(MOXA, 0x1182), },
3460 { PCI_VDEVICE(MOXA, 0x1183), },
3461 { PCI_VDEVICE(MOXA, 0x1322), },
3462 { PCI_VDEVICE(MOXA, 0x1342), },
3463 { PCI_VDEVICE(MOXA, 0x1381), },
3464 { PCI_VDEVICE(MOXA, 0x1683), },
3465
3466 /* Intel platforms with MID UART */
3467 { PCI_VDEVICE(INTEL, 0x081b), },
3468 { PCI_VDEVICE(INTEL, 0x081c), },
3469 { PCI_VDEVICE(INTEL, 0x081d), },
3470 { PCI_VDEVICE(INTEL, 0x1191), },
3471 { PCI_VDEVICE(INTEL, 0x18d8), },
3472 { PCI_VDEVICE(INTEL, 0x19d8), },
3473
3474 /* Intel platforms with DesignWare UART */
3475 { PCI_VDEVICE(INTEL, 0x0936), },
3476 { PCI_VDEVICE(INTEL, 0x0f0a), },
3477 { PCI_VDEVICE(INTEL, 0x0f0c), },
3478 { PCI_VDEVICE(INTEL, 0x228a), },
3479 { PCI_VDEVICE(INTEL, 0x228c), },
3480 { PCI_VDEVICE(INTEL, 0x9ce3), },
3481 { PCI_VDEVICE(INTEL, 0x9ce4), },
3482
3483 /* Exar devices */
3484 { PCI_VDEVICE(EXAR, PCI_ANY_ID), },
3485 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), },
3486 };
3487
3488 static int serial_pci_is_class_communication(struct pci_dev *dev)
3489 {
3490 /*
3491 * If it is not a communications device or the programming
3492 * interface is greater than 6, give up.
3493 */
3494 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3495 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
3496 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3497 (dev->class & 0xff) > 6)
3498 return -ENODEV;
3499
3500 return 0;
3501 }
3502
3503 static int serial_pci_is_blacklisted(struct pci_dev *dev)
3504 {
3505 const struct pci_device_id *bldev;
3506
3507 /*
3508 * Do not access blacklisted devices that are known not to
3509 * feature serial ports or are handled by other modules.
3510 */
3511 for (bldev = blacklist;
3512 bldev < blacklist + ARRAY_SIZE(blacklist);
3513 bldev++) {
3514 if (dev->vendor == bldev->vendor &&
3515 dev->device == bldev->device)
3516 return -ENODEV;
3517 }
3518
3519 return 0;
3520 }
3521
3522 /*
3523 * Given a complete unknown PCI device, try to use some heuristics to
3524 * guess what the configuration might be, based on the pitiful PCI
3525 * serial specs. Returns 0 on success, -ENODEV on failure.
3526 */
3527 static int
3528 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3529 {
3530 int num_iomem, num_port, first_port = -1, i;
3531 int rc;
3532
3533 rc = serial_pci_is_class_communication(dev);
3534 if (rc)
3535 return rc;
3536
3537 /*
3538 * Should we try to make guesses for multiport serial devices later?
3539 */
3540 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
3541 return -ENODEV;
3542
3543 num_iomem = num_port = 0;
3544 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3545 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3546 num_port++;
3547 if (first_port == -1)
3548 first_port = i;
3549 }
3550 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3551 num_iomem++;
3552 }
3553
3554 /*
3555 * If there is 1 or 0 iomem regions, and exactly one port,
3556 * use it. We guess the number of ports based on the IO
3557 * region size.
3558 */
3559 if (num_iomem <= 1 && num_port == 1) {
3560 board->flags = first_port;
3561 board->num_ports = pci_resource_len(dev, first_port) / 8;
3562 return 0;
3563 }
3564
3565 /*
3566 * Now guess if we've got a board which indexes by BARs.
3567 * Each IO BAR should be 8 bytes, and they should follow
3568 * consecutively.
3569 */
3570 first_port = -1;
3571 num_port = 0;
3572 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3573 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3574 pci_resource_len(dev, i) == 8 &&
3575 (first_port == -1 || (first_port + num_port) == i)) {
3576 num_port++;
3577 if (first_port == -1)
3578 first_port = i;
3579 }
3580 }
3581
3582 if (num_port > 1) {
3583 board->flags = first_port | FL_BASE_BARS;
3584 board->num_ports = num_port;
3585 return 0;
3586 }
3587
3588 return -ENODEV;
3589 }
3590
3591 static inline int
3592 serial_pci_matches(const struct pciserial_board *board,
3593 const struct pciserial_board *guessed)
3594 {
3595 return
3596 board->num_ports == guessed->num_ports &&
3597 board->base_baud == guessed->base_baud &&
3598 board->uart_offset == guessed->uart_offset &&
3599 board->reg_shift == guessed->reg_shift &&
3600 board->first_offset == guessed->first_offset;
3601 }
3602
3603 struct serial_private *
3604 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3605 {
3606 struct uart_8250_port uart;
3607 struct serial_private *priv;
3608 struct pci_serial_quirk *quirk;
3609 int rc, nr_ports, i;
3610
3611 nr_ports = board->num_ports;
3612
3613 /*
3614 * Find an init and setup quirks.
3615 */
3616 quirk = find_quirk(dev);
3617
3618 /*
3619 * Run the new-style initialization function.
3620 * The initialization function returns:
3621 * <0 - error
3622 * 0 - use board->num_ports
3623 * >0 - number of ports
3624 */
3625 if (quirk->init) {
3626 rc = quirk->init(dev);
3627 if (rc < 0) {
3628 priv = ERR_PTR(rc);
3629 goto err_out;
3630 }
3631 if (rc)
3632 nr_ports = rc;
3633 }
3634
3635 priv = kzalloc(sizeof(struct serial_private) +
3636 sizeof(unsigned int) * nr_ports,
3637 GFP_KERNEL);
3638 if (!priv) {
3639 priv = ERR_PTR(-ENOMEM);
3640 goto err_deinit;
3641 }
3642
3643 priv->dev = dev;
3644 priv->quirk = quirk;
3645
3646 memset(&uart, 0, sizeof(uart));
3647 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3648 uart.port.uartclk = board->base_baud * 16;
3649 uart.port.irq = get_pci_irq(dev, board);
3650 uart.port.dev = &dev->dev;
3651
3652 for (i = 0; i < nr_ports; i++) {
3653 if (quirk->setup(priv, board, &uart, i))
3654 break;
3655
3656 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3657 uart.port.iobase, uart.port.irq, uart.port.iotype);
3658
3659 priv->line[i] = serial8250_register_8250_port(&uart);
3660 if (priv->line[i] < 0) {
3661 dev_err(&dev->dev,
3662 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3663 uart.port.iobase, uart.port.irq,
3664 uart.port.iotype, priv->line[i]);
3665 break;
3666 }
3667 }
3668 priv->nr = i;
3669 priv->board = board;
3670 return priv;
3671
3672 err_deinit:
3673 if (quirk->exit)
3674 quirk->exit(dev);
3675 err_out:
3676 return priv;
3677 }
3678 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3679
3680 static void pciserial_detach_ports(struct serial_private *priv)
3681 {
3682 struct pci_serial_quirk *quirk;
3683 int i;
3684
3685 for (i = 0; i < priv->nr; i++)
3686 serial8250_unregister_port(priv->line[i]);
3687
3688 /*
3689 * Find the exit quirks.
3690 */
3691 quirk = find_quirk(priv->dev);
3692 if (quirk->exit)
3693 quirk->exit(priv->dev);
3694 }
3695
3696 void pciserial_remove_ports(struct serial_private *priv)
3697 {
3698 pciserial_detach_ports(priv);
3699 kfree(priv);
3700 }
3701 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3702
3703 void pciserial_suspend_ports(struct serial_private *priv)
3704 {
3705 int i;
3706
3707 for (i = 0; i < priv->nr; i++)
3708 if (priv->line[i] >= 0)
3709 serial8250_suspend_port(priv->line[i]);
3710
3711 /*
3712 * Ensure that every init quirk is properly torn down
3713 */
3714 if (priv->quirk->exit)
3715 priv->quirk->exit(priv->dev);
3716 }
3717 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3718
3719 void pciserial_resume_ports(struct serial_private *priv)
3720 {
3721 int i;
3722
3723 /*
3724 * Ensure that the board is correctly configured.
3725 */
3726 if (priv->quirk->init)
3727 priv->quirk->init(priv->dev);
3728
3729 for (i = 0; i < priv->nr; i++)
3730 if (priv->line[i] >= 0)
3731 serial8250_resume_port(priv->line[i]);
3732 }
3733 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3734
3735 /*
3736 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3737 * to the arrangement of serial ports on a PCI card.
3738 */
3739 static int
3740 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3741 {
3742 struct pci_serial_quirk *quirk;
3743 struct serial_private *priv;
3744 const struct pciserial_board *board;
3745 struct pciserial_board tmp;
3746 int rc;
3747
3748 quirk = find_quirk(dev);
3749 if (quirk->probe) {
3750 rc = quirk->probe(dev);
3751 if (rc)
3752 return rc;
3753 }
3754
3755 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3756 dev_err(&dev->dev, "invalid driver_data: %ld\n",
3757 ent->driver_data);
3758 return -EINVAL;
3759 }
3760
3761 board = &pci_boards[ent->driver_data];
3762
3763 rc = serial_pci_is_blacklisted(dev);
3764 if (rc)
3765 return rc;
3766
3767 rc = pcim_enable_device(dev);
3768 pci_save_state(dev);
3769 if (rc)
3770 return rc;
3771
3772 if (ent->driver_data == pbn_default) {
3773 /*
3774 * Use a copy of the pci_board entry for this;
3775 * avoid changing entries in the table.
3776 */
3777 memcpy(&tmp, board, sizeof(struct pciserial_board));
3778 board = &tmp;
3779
3780 /*
3781 * We matched one of our class entries. Try to
3782 * determine the parameters of this board.
3783 */
3784 rc = serial_pci_guess_board(dev, &tmp);
3785 if (rc)
3786 return rc;
3787 } else {
3788 /*
3789 * We matched an explicit entry. If we are able to
3790 * detect this boards settings with our heuristic,
3791 * then we no longer need this entry.
3792 */
3793 memcpy(&tmp, &pci_boards[pbn_default],
3794 sizeof(struct pciserial_board));
3795 rc = serial_pci_guess_board(dev, &tmp);
3796 if (rc == 0 && serial_pci_matches(board, &tmp))
3797 moan_device("Redundant entry in serial pci_table.",
3798 dev);
3799 }
3800
3801 priv = pciserial_init_ports(dev, board);
3802 if (IS_ERR(priv))
3803 return PTR_ERR(priv);
3804
3805 pci_set_drvdata(dev, priv);
3806 return 0;
3807 }
3808
3809 static void pciserial_remove_one(struct pci_dev *dev)
3810 {
3811 struct serial_private *priv = pci_get_drvdata(dev);
3812
3813 pciserial_remove_ports(priv);
3814 }
3815
3816 #ifdef CONFIG_PM_SLEEP
3817 static int pciserial_suspend_one(struct device *dev)
3818 {
3819 struct pci_dev *pdev = to_pci_dev(dev);
3820 struct serial_private *priv = pci_get_drvdata(pdev);
3821
3822 if (priv)
3823 pciserial_suspend_ports(priv);
3824
3825 return 0;
3826 }
3827
3828 static int pciserial_resume_one(struct device *dev)
3829 {
3830 struct pci_dev *pdev = to_pci_dev(dev);
3831 struct serial_private *priv = pci_get_drvdata(pdev);
3832 int err;
3833
3834 if (priv) {
3835 /*
3836 * The device may have been disabled. Re-enable it.
3837 */
3838 err = pci_enable_device(pdev);
3839 /* FIXME: We cannot simply error out here */
3840 if (err)
3841 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
3842 pciserial_resume_ports(priv);
3843 }
3844 return 0;
3845 }
3846 #endif
3847
3848 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
3849 pciserial_resume_one);
3850
3851 static const struct pci_device_id serial_pci_tbl[] = {
3852 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3853 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3854 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3855 pbn_b2_8_921600 },
3856 /* Advantech also use 0x3618 and 0xf618 */
3857 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
3858 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3859 pbn_b0_4_921600 },
3860 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
3861 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3862 pbn_b0_4_921600 },
3863 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3864 PCI_SUBVENDOR_ID_CONNECT_TECH,
3865 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3866 pbn_b1_8_1382400 },
3867 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3868 PCI_SUBVENDOR_ID_CONNECT_TECH,
3869 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3870 pbn_b1_4_1382400 },
3871 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3872 PCI_SUBVENDOR_ID_CONNECT_TECH,
3873 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3874 pbn_b1_2_1382400 },
3875 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3876 PCI_SUBVENDOR_ID_CONNECT_TECH,
3877 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3878 pbn_b1_8_1382400 },
3879 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3880 PCI_SUBVENDOR_ID_CONNECT_TECH,
3881 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3882 pbn_b1_4_1382400 },
3883 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3884 PCI_SUBVENDOR_ID_CONNECT_TECH,
3885 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3886 pbn_b1_2_1382400 },
3887 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3888 PCI_SUBVENDOR_ID_CONNECT_TECH,
3889 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3890 pbn_b1_8_921600 },
3891 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3892 PCI_SUBVENDOR_ID_CONNECT_TECH,
3893 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3894 pbn_b1_8_921600 },
3895 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3896 PCI_SUBVENDOR_ID_CONNECT_TECH,
3897 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3898 pbn_b1_4_921600 },
3899 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3900 PCI_SUBVENDOR_ID_CONNECT_TECH,
3901 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3902 pbn_b1_4_921600 },
3903 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3904 PCI_SUBVENDOR_ID_CONNECT_TECH,
3905 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3906 pbn_b1_2_921600 },
3907 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3908 PCI_SUBVENDOR_ID_CONNECT_TECH,
3909 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3910 pbn_b1_8_921600 },
3911 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3912 PCI_SUBVENDOR_ID_CONNECT_TECH,
3913 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3914 pbn_b1_8_921600 },
3915 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3916 PCI_SUBVENDOR_ID_CONNECT_TECH,
3917 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3918 pbn_b1_4_921600 },
3919 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3920 PCI_SUBVENDOR_ID_CONNECT_TECH,
3921 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3922 pbn_b1_2_1250000 },
3923 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3924 PCI_SUBVENDOR_ID_CONNECT_TECH,
3925 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3926 pbn_b0_2_1843200 },
3927 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3928 PCI_SUBVENDOR_ID_CONNECT_TECH,
3929 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3930 pbn_b0_4_1843200 },
3931 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3932 PCI_VENDOR_ID_AFAVLAB,
3933 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3934 pbn_b0_4_1152000 },
3935 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3936 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3937 pbn_b2_bt_1_115200 },
3938 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3939 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3940 pbn_b2_bt_2_115200 },
3941 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3942 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3943 pbn_b2_bt_4_115200 },
3944 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3945 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3946 pbn_b2_bt_2_115200 },
3947 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3948 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3949 pbn_b2_bt_4_115200 },
3950 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3951 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3952 pbn_b2_8_115200 },
3953 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3954 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3955 pbn_b2_8_460800 },
3956 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3957 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3958 pbn_b2_8_115200 },
3959
3960 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3961 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3962 pbn_b2_bt_2_115200 },
3963 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3964 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3965 pbn_b2_bt_2_921600 },
3966 /*
3967 * VScom SPCOM800, from sl@s.pl
3968 */
3969 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3971 pbn_b2_8_921600 },
3972 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3973 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3974 pbn_b2_4_921600 },
3975 /* Unknown card - subdevice 0x1584 */
3976 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3977 PCI_VENDOR_ID_PLX,
3978 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3979 pbn_b2_4_115200 },
3980 /* Unknown card - subdevice 0x1588 */
3981 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3982 PCI_VENDOR_ID_PLX,
3983 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
3984 pbn_b2_8_115200 },
3985 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3986 PCI_SUBVENDOR_ID_KEYSPAN,
3987 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3988 pbn_panacom },
3989 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3990 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3991 pbn_panacom4 },
3992 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3993 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3994 pbn_panacom2 },
3995 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3996 PCI_VENDOR_ID_ESDGMBH,
3997 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3998 pbn_b2_4_115200 },
3999 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4000 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4001 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4002 pbn_b2_4_460800 },
4003 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4004 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4005 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4006 pbn_b2_8_460800 },
4007 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4008 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4009 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4010 pbn_b2_16_460800 },
4011 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4012 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4013 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4014 pbn_b2_16_460800 },
4015 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4016 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4017 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4018 pbn_b2_4_460800 },
4019 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4020 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4021 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4022 pbn_b2_8_460800 },
4023 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4024 PCI_SUBVENDOR_ID_EXSYS,
4025 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4026 pbn_b2_4_115200 },
4027 /*
4028 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4029 * (Exoray@isys.ca)
4030 */
4031 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4032 0x10b5, 0x106a, 0, 0,
4033 pbn_plx_romulus },
4034 /*
4035 * EndRun Technologies. PCI express device range.
4036 * EndRun PTP/1588 has 2 Native UARTs.
4037 */
4038 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4039 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4040 pbn_endrun_2_4000000 },
4041 /*
4042 * Quatech cards. These actually have configurable clocks but for
4043 * now we just use the default.
4044 *
4045 * 100 series are RS232, 200 series RS422,
4046 */
4047 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4048 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4049 pbn_b1_4_115200 },
4050 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4051 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4052 pbn_b1_2_115200 },
4053 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4054 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4055 pbn_b2_2_115200 },
4056 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4057 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4058 pbn_b1_2_115200 },
4059 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4060 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4061 pbn_b2_2_115200 },
4062 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4063 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4064 pbn_b1_4_115200 },
4065 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4066 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4067 pbn_b1_8_115200 },
4068 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4070 pbn_b1_8_115200 },
4071 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4072 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4073 pbn_b1_4_115200 },
4074 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4076 pbn_b1_2_115200 },
4077 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4079 pbn_b1_4_115200 },
4080 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4082 pbn_b1_2_115200 },
4083 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4085 pbn_b2_4_115200 },
4086 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4088 pbn_b2_2_115200 },
4089 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4091 pbn_b2_1_115200 },
4092 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4094 pbn_b2_4_115200 },
4095 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4096 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4097 pbn_b2_2_115200 },
4098 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4100 pbn_b2_1_115200 },
4101 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4102 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4103 pbn_b0_8_115200 },
4104
4105 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4106 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4107 0, 0,
4108 pbn_b0_4_921600 },
4109 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4110 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4111 0, 0,
4112 pbn_b0_4_1152000 },
4113 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4114 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4115 pbn_b0_bt_2_921600 },
4116
4117 /*
4118 * The below card is a little controversial since it is the
4119 * subject of a PCI vendor/device ID clash. (See
4120 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4121 * For now just used the hex ID 0x950a.
4122 */
4123 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4124 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4125 0, 0, pbn_b0_2_115200 },
4126 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4127 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4128 0, 0, pbn_b0_2_115200 },
4129 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4131 pbn_b0_2_1130000 },
4132 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4133 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4134 pbn_b0_1_921600 },
4135 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4136 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4137 pbn_b0_4_115200 },
4138 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4139 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4140 pbn_b0_bt_2_921600 },
4141 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4142 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4143 pbn_b2_8_1152000 },
4144
4145 /*
4146 * Oxford Semiconductor Inc. Tornado PCI express device range.
4147 */
4148 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4149 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4150 pbn_b0_1_4000000 },
4151 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4152 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4153 pbn_b0_1_4000000 },
4154 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4155 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4156 pbn_oxsemi_1_4000000 },
4157 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4158 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4159 pbn_oxsemi_1_4000000 },
4160 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4161 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4162 pbn_b0_1_4000000 },
4163 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4164 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4165 pbn_b0_1_4000000 },
4166 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4167 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4168 pbn_oxsemi_1_4000000 },
4169 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4170 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4171 pbn_oxsemi_1_4000000 },
4172 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4173 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4174 pbn_b0_1_4000000 },
4175 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4176 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4177 pbn_b0_1_4000000 },
4178 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4179 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4180 pbn_b0_1_4000000 },
4181 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4182 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4183 pbn_b0_1_4000000 },
4184 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4185 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4186 pbn_oxsemi_2_4000000 },
4187 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4188 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4189 pbn_oxsemi_2_4000000 },
4190 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4191 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4192 pbn_oxsemi_4_4000000 },
4193 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4194 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4195 pbn_oxsemi_4_4000000 },
4196 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4197 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4198 pbn_oxsemi_8_4000000 },
4199 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4200 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4201 pbn_oxsemi_8_4000000 },
4202 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4203 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4204 pbn_oxsemi_1_4000000 },
4205 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4206 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4207 pbn_oxsemi_1_4000000 },
4208 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4209 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4210 pbn_oxsemi_1_4000000 },
4211 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4212 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4213 pbn_oxsemi_1_4000000 },
4214 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4215 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4216 pbn_oxsemi_1_4000000 },
4217 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4218 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4219 pbn_oxsemi_1_4000000 },
4220 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4221 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4222 pbn_oxsemi_1_4000000 },
4223 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4224 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4225 pbn_oxsemi_1_4000000 },
4226 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4227 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4228 pbn_oxsemi_1_4000000 },
4229 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4230 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4231 pbn_oxsemi_1_4000000 },
4232 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4233 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4234 pbn_oxsemi_1_4000000 },
4235 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4236 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4237 pbn_oxsemi_1_4000000 },
4238 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4239 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4240 pbn_oxsemi_1_4000000 },
4241 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4242 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4243 pbn_oxsemi_1_4000000 },
4244 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4245 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4246 pbn_oxsemi_1_4000000 },
4247 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4248 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4249 pbn_oxsemi_1_4000000 },
4250 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4251 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4252 pbn_oxsemi_1_4000000 },
4253 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4254 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4255 pbn_oxsemi_1_4000000 },
4256 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4257 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4258 pbn_oxsemi_1_4000000 },
4259 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4260 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4261 pbn_oxsemi_1_4000000 },
4262 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4263 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4264 pbn_oxsemi_1_4000000 },
4265 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4266 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4267 pbn_oxsemi_1_4000000 },
4268 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4270 pbn_oxsemi_1_4000000 },
4271 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4273 pbn_oxsemi_1_4000000 },
4274 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4275 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4276 pbn_oxsemi_1_4000000 },
4277 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4278 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4279 pbn_oxsemi_1_4000000 },
4280 /*
4281 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4282 */
4283 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4284 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4285 pbn_oxsemi_1_4000000 },
4286 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4287 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4288 pbn_oxsemi_2_4000000 },
4289 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4290 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4291 pbn_oxsemi_4_4000000 },
4292 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4293 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4294 pbn_oxsemi_8_4000000 },
4295
4296 /*
4297 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4298 */
4299 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4300 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4301 pbn_oxsemi_2_4000000 },
4302
4303 /*
4304 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4305 * from skokodyn@yahoo.com
4306 */
4307 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4308 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4309 pbn_sbsxrsio },
4310 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4311 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4312 pbn_sbsxrsio },
4313 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4314 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4315 pbn_sbsxrsio },
4316 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4317 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4318 pbn_sbsxrsio },
4319
4320 /*
4321 * Digitan DS560-558, from jimd@esoft.com
4322 */
4323 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4324 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4325 pbn_b1_1_115200 },
4326
4327 /*
4328 * Titan Electronic cards
4329 * The 400L and 800L have a custom setup quirk.
4330 */
4331 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4332 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4333 pbn_b0_1_921600 },
4334 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4335 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4336 pbn_b0_2_921600 },
4337 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4338 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4339 pbn_b0_4_921600 },
4340 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4341 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342 pbn_b0_4_921600 },
4343 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4344 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4345 pbn_b1_1_921600 },
4346 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4347 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4348 pbn_b1_bt_2_921600 },
4349 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4350 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4351 pbn_b0_bt_4_921600 },
4352 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4353 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4354 pbn_b0_bt_8_921600 },
4355 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4356 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4357 pbn_b4_bt_2_921600 },
4358 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4359 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4360 pbn_b4_bt_4_921600 },
4361 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4362 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4363 pbn_b4_bt_8_921600 },
4364 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4365 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4366 pbn_b0_4_921600 },
4367 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4368 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4369 pbn_b0_4_921600 },
4370 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4371 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4372 pbn_b0_4_921600 },
4373 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4374 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4375 pbn_oxsemi_1_4000000 },
4376 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4377 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4378 pbn_oxsemi_2_4000000 },
4379 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4380 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4381 pbn_oxsemi_4_4000000 },
4382 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4383 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4384 pbn_oxsemi_8_4000000 },
4385 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4386 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4387 pbn_oxsemi_2_4000000 },
4388 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4389 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4390 pbn_oxsemi_2_4000000 },
4391 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4392 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4393 pbn_b0_bt_2_921600 },
4394 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4395 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4396 pbn_b0_4_921600 },
4397 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4398 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4399 pbn_b0_4_921600 },
4400 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4401 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4402 pbn_b0_4_921600 },
4403 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4404 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4405 pbn_b0_4_921600 },
4406
4407 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4408 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4409 pbn_b2_1_460800 },
4410 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4411 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4412 pbn_b2_1_460800 },
4413 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4414 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4415 pbn_b2_1_460800 },
4416 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4417 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4418 pbn_b2_bt_2_921600 },
4419 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4420 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4421 pbn_b2_bt_2_921600 },
4422 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4423 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4424 pbn_b2_bt_2_921600 },
4425 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4426 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4427 pbn_b2_bt_4_921600 },
4428 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4429 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4430 pbn_b2_bt_4_921600 },
4431 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4433 pbn_b2_bt_4_921600 },
4434 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4436 pbn_b0_1_921600 },
4437 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4438 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4439 pbn_b0_1_921600 },
4440 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4442 pbn_b0_1_921600 },
4443 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4444 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4445 pbn_b0_bt_2_921600 },
4446 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4447 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4448 pbn_b0_bt_2_921600 },
4449 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4451 pbn_b0_bt_2_921600 },
4452 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4454 pbn_b0_bt_4_921600 },
4455 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4457 pbn_b0_bt_4_921600 },
4458 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4460 pbn_b0_bt_4_921600 },
4461 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4462 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4463 pbn_b0_bt_8_921600 },
4464 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4466 pbn_b0_bt_8_921600 },
4467 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4469 pbn_b0_bt_8_921600 },
4470
4471 /*
4472 * Computone devices submitted by Doug McNash dmcnash@computone.com
4473 */
4474 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4475 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4476 0, 0, pbn_computone_4 },
4477 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4478 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4479 0, 0, pbn_computone_8 },
4480 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4481 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4482 0, 0, pbn_computone_6 },
4483
4484 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4485 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4486 pbn_oxsemi },
4487 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4488 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4489 pbn_b0_bt_1_921600 },
4490
4491 /*
4492 * SUNIX (TIMEDIA)
4493 */
4494 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4495 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4496 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4497 pbn_b0_bt_1_921600 },
4498
4499 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4500 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4501 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4502 pbn_b0_bt_1_921600 },
4503
4504 /*
4505 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4506 */
4507 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4508 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4509 pbn_b0_bt_8_115200 },
4510 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4511 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4512 pbn_b0_bt_8_115200 },
4513
4514 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4515 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4516 pbn_b0_bt_2_115200 },
4517 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4518 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4519 pbn_b0_bt_2_115200 },
4520 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4521 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4522 pbn_b0_bt_2_115200 },
4523 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4524 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4525 pbn_b0_bt_2_115200 },
4526 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4527 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4528 pbn_b0_bt_2_115200 },
4529 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4530 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4531 pbn_b0_bt_4_460800 },
4532 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4533 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4534 pbn_b0_bt_4_460800 },
4535 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4536 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4537 pbn_b0_bt_2_460800 },
4538 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4539 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4540 pbn_b0_bt_2_460800 },
4541 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4542 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4543 pbn_b0_bt_2_460800 },
4544 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4545 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4546 pbn_b0_bt_1_115200 },
4547 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4548 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4549 pbn_b0_bt_1_460800 },
4550
4551 /*
4552 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4553 * Cards are identified by their subsystem vendor IDs, which
4554 * (in hex) match the model number.
4555 *
4556 * Note that JC140x are RS422/485 cards which require ox950
4557 * ACR = 0x10, and as such are not currently fully supported.
4558 */
4559 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4560 0x1204, 0x0004, 0, 0,
4561 pbn_b0_4_921600 },
4562 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4563 0x1208, 0x0004, 0, 0,
4564 pbn_b0_4_921600 },
4565 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4566 0x1402, 0x0002, 0, 0,
4567 pbn_b0_2_921600 }, */
4568 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4569 0x1404, 0x0004, 0, 0,
4570 pbn_b0_4_921600 }, */
4571 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4572 0x1208, 0x0004, 0, 0,
4573 pbn_b0_4_921600 },
4574
4575 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4576 0x1204, 0x0004, 0, 0,
4577 pbn_b0_4_921600 },
4578 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4579 0x1208, 0x0004, 0, 0,
4580 pbn_b0_4_921600 },
4581 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4582 0x1208, 0x0004, 0, 0,
4583 pbn_b0_4_921600 },
4584 /*
4585 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4586 */
4587 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4589 pbn_b1_1_1382400 },
4590
4591 /*
4592 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4593 */
4594 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596 pbn_b1_1_1382400 },
4597
4598 /*
4599 * RAStel 2 port modem, gerg@moreton.com.au
4600 */
4601 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4602 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4603 pbn_b2_bt_2_115200 },
4604
4605 /*
4606 * EKF addition for i960 Boards form EKF with serial port
4607 */
4608 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4609 0xE4BF, PCI_ANY_ID, 0, 0,
4610 pbn_intel_i960 },
4611
4612 /*
4613 * Xircom Cardbus/Ethernet combos
4614 */
4615 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617 pbn_b0_1_115200 },
4618 /*
4619 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4620 */
4621 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623 pbn_b0_1_115200 },
4624
4625 /*
4626 * Untested PCI modems, sent in from various folks...
4627 */
4628
4629 /*
4630 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4631 */
4632 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4633 0x1048, 0x1500, 0, 0,
4634 pbn_b1_1_115200 },
4635
4636 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4637 0xFF00, 0, 0, 0,
4638 pbn_sgi_ioc3 },
4639
4640 /*
4641 * HP Diva card
4642 */
4643 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4644 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4645 pbn_b1_1_115200 },
4646 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4647 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4648 pbn_b0_5_115200 },
4649 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4650 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4651 pbn_b2_1_115200 },
4652
4653 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4654 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4655 pbn_b3_2_115200 },
4656 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4657 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4658 pbn_b3_4_115200 },
4659 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4660 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4661 pbn_b3_8_115200 },
4662 /*
4663 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
4664 */
4665 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
4666 PCI_ANY_ID, PCI_ANY_ID,
4667 0,
4668 0, pbn_pericom_PI7C9X7951 },
4669 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
4670 PCI_ANY_ID, PCI_ANY_ID,
4671 0,
4672 0, pbn_pericom_PI7C9X7952 },
4673 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
4674 PCI_ANY_ID, PCI_ANY_ID,
4675 0,
4676 0, pbn_pericom_PI7C9X7954 },
4677 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
4678 PCI_ANY_ID, PCI_ANY_ID,
4679 0,
4680 0, pbn_pericom_PI7C9X7958 },
4681 /*
4682 * ACCES I/O Products quad
4683 */
4684 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
4685 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4686 pbn_pericom_PI7C9X7952 },
4687 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
4688 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4689 pbn_pericom_PI7C9X7952 },
4690 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
4691 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4692 pbn_pericom_PI7C9X7954 },
4693 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
4694 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4695 pbn_pericom_PI7C9X7954 },
4696 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
4697 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4698 pbn_pericom_PI7C9X7952 },
4699 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
4700 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4701 pbn_pericom_PI7C9X7952 },
4702 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
4703 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4704 pbn_pericom_PI7C9X7954 },
4705 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4707 pbn_pericom_PI7C9X7954 },
4708 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
4709 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4710 pbn_pericom_PI7C9X7952 },
4711 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
4712 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4713 pbn_pericom_PI7C9X7952 },
4714 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
4715 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4716 pbn_pericom_PI7C9X7954 },
4717 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
4718 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4719 pbn_pericom_PI7C9X7954 },
4720 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
4721 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4722 pbn_pericom_PI7C9X7951 },
4723 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
4724 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4725 pbn_pericom_PI7C9X7952 },
4726 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
4727 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4728 pbn_pericom_PI7C9X7952 },
4729 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
4730 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4731 pbn_pericom_PI7C9X7954 },
4732 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
4733 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4734 pbn_pericom_PI7C9X7954 },
4735 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
4736 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4737 pbn_pericom_PI7C9X7952 },
4738 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
4739 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4740 pbn_pericom_PI7C9X7954 },
4741 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
4742 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4743 pbn_pericom_PI7C9X7952 },
4744 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
4745 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4746 pbn_pericom_PI7C9X7952 },
4747 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
4748 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4749 pbn_pericom_PI7C9X7954 },
4750 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
4751 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4752 pbn_pericom_PI7C9X7954 },
4753 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
4754 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4755 pbn_pericom_PI7C9X7952 },
4756 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
4757 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4758 pbn_pericom_PI7C9X7954 },
4759 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
4760 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4761 pbn_pericom_PI7C9X7954 },
4762 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
4763 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4764 pbn_pericom_PI7C9X7958 },
4765 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
4766 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4767 pbn_pericom_PI7C9X7958 },
4768 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
4769 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4770 pbn_pericom_PI7C9X7954 },
4771 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
4772 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4773 pbn_pericom_PI7C9X7958 },
4774 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
4775 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4776 pbn_pericom_PI7C9X7954 },
4777 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
4778 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4779 pbn_pericom_PI7C9X7958 },
4780 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
4781 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4782 pbn_pericom_PI7C9X7954 },
4783 /*
4784 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4785 */
4786 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4787 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4788 pbn_b0_1_115200 },
4789 /*
4790 * ITE
4791 */
4792 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4793 PCI_ANY_ID, PCI_ANY_ID,
4794 0, 0,
4795 pbn_b1_bt_1_115200 },
4796
4797 /*
4798 * IntaShield IS-200
4799 */
4800 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4801 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4802 pbn_b2_2_115200 },
4803 /*
4804 * IntaShield IS-400
4805 */
4806 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4807 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4808 pbn_b2_4_115200 },
4809 /*
4810 * BrainBoxes UC-260
4811 */
4812 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
4813 PCI_ANY_ID, PCI_ANY_ID,
4814 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4815 pbn_b2_4_115200 },
4816 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
4817 PCI_ANY_ID, PCI_ANY_ID,
4818 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4819 pbn_b2_4_115200 },
4820 /*
4821 * Perle PCI-RAS cards
4822 */
4823 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4824 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4825 0, 0, pbn_b2_4_921600 },
4826 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4827 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4828 0, 0, pbn_b2_8_921600 },
4829
4830 /*
4831 * Mainpine series cards: Fairly standard layout but fools
4832 * parts of the autodetect in some cases and uses otherwise
4833 * unmatched communications subclasses in the PCI Express case
4834 */
4835
4836 { /* RockForceDUO */
4837 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4838 PCI_VENDOR_ID_MAINPINE, 0x0200,
4839 0, 0, pbn_b0_2_115200 },
4840 { /* RockForceQUATRO */
4841 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4842 PCI_VENDOR_ID_MAINPINE, 0x0300,
4843 0, 0, pbn_b0_4_115200 },
4844 { /* RockForceDUO+ */
4845 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4846 PCI_VENDOR_ID_MAINPINE, 0x0400,
4847 0, 0, pbn_b0_2_115200 },
4848 { /* RockForceQUATRO+ */
4849 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4850 PCI_VENDOR_ID_MAINPINE, 0x0500,
4851 0, 0, pbn_b0_4_115200 },
4852 { /* RockForce+ */
4853 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4854 PCI_VENDOR_ID_MAINPINE, 0x0600,
4855 0, 0, pbn_b0_2_115200 },
4856 { /* RockForce+ */
4857 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4858 PCI_VENDOR_ID_MAINPINE, 0x0700,
4859 0, 0, pbn_b0_4_115200 },
4860 { /* RockForceOCTO+ */
4861 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4862 PCI_VENDOR_ID_MAINPINE, 0x0800,
4863 0, 0, pbn_b0_8_115200 },
4864 { /* RockForceDUO+ */
4865 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4866 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4867 0, 0, pbn_b0_2_115200 },
4868 { /* RockForceQUARTRO+ */
4869 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4870 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4871 0, 0, pbn_b0_4_115200 },
4872 { /* RockForceOCTO+ */
4873 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4874 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4875 0, 0, pbn_b0_8_115200 },
4876 { /* RockForceD1 */
4877 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4878 PCI_VENDOR_ID_MAINPINE, 0x2000,
4879 0, 0, pbn_b0_1_115200 },
4880 { /* RockForceF1 */
4881 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4882 PCI_VENDOR_ID_MAINPINE, 0x2100,
4883 0, 0, pbn_b0_1_115200 },
4884 { /* RockForceD2 */
4885 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4886 PCI_VENDOR_ID_MAINPINE, 0x2200,
4887 0, 0, pbn_b0_2_115200 },
4888 { /* RockForceF2 */
4889 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4890 PCI_VENDOR_ID_MAINPINE, 0x2300,
4891 0, 0, pbn_b0_2_115200 },
4892 { /* RockForceD4 */
4893 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4894 PCI_VENDOR_ID_MAINPINE, 0x2400,
4895 0, 0, pbn_b0_4_115200 },
4896 { /* RockForceF4 */
4897 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4898 PCI_VENDOR_ID_MAINPINE, 0x2500,
4899 0, 0, pbn_b0_4_115200 },
4900 { /* RockForceD8 */
4901 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4902 PCI_VENDOR_ID_MAINPINE, 0x2600,
4903 0, 0, pbn_b0_8_115200 },
4904 { /* RockForceF8 */
4905 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4906 PCI_VENDOR_ID_MAINPINE, 0x2700,
4907 0, 0, pbn_b0_8_115200 },
4908 { /* IQ Express D1 */
4909 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4910 PCI_VENDOR_ID_MAINPINE, 0x3000,
4911 0, 0, pbn_b0_1_115200 },
4912 { /* IQ Express F1 */
4913 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4914 PCI_VENDOR_ID_MAINPINE, 0x3100,
4915 0, 0, pbn_b0_1_115200 },
4916 { /* IQ Express D2 */
4917 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4918 PCI_VENDOR_ID_MAINPINE, 0x3200,
4919 0, 0, pbn_b0_2_115200 },
4920 { /* IQ Express F2 */
4921 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4922 PCI_VENDOR_ID_MAINPINE, 0x3300,
4923 0, 0, pbn_b0_2_115200 },
4924 { /* IQ Express D4 */
4925 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4926 PCI_VENDOR_ID_MAINPINE, 0x3400,
4927 0, 0, pbn_b0_4_115200 },
4928 { /* IQ Express F4 */
4929 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4930 PCI_VENDOR_ID_MAINPINE, 0x3500,
4931 0, 0, pbn_b0_4_115200 },
4932 { /* IQ Express D8 */
4933 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4934 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4935 0, 0, pbn_b0_8_115200 },
4936 { /* IQ Express F8 */
4937 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4938 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4939 0, 0, pbn_b0_8_115200 },
4940
4941
4942 /*
4943 * PA Semi PA6T-1682M on-chip UART
4944 */
4945 { PCI_VENDOR_ID_PASEMI, 0xa004,
4946 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4947 pbn_pasemi_1682M },
4948
4949 /*
4950 * National Instruments
4951 */
4952 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4953 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4954 pbn_b1_16_115200 },
4955 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4956 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4957 pbn_b1_8_115200 },
4958 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4959 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4960 pbn_b1_bt_4_115200 },
4961 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4962 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4963 pbn_b1_bt_2_115200 },
4964 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4965 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4966 pbn_b1_bt_4_115200 },
4967 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4968 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4969 pbn_b1_bt_2_115200 },
4970 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4971 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4972 pbn_b1_16_115200 },
4973 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4974 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4975 pbn_b1_8_115200 },
4976 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4977 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4978 pbn_b1_bt_4_115200 },
4979 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4980 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4981 pbn_b1_bt_2_115200 },
4982 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4983 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4984 pbn_b1_bt_4_115200 },
4985 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4986 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4987 pbn_b1_bt_2_115200 },
4988 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4989 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4990 pbn_ni8430_2 },
4991 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4992 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4993 pbn_ni8430_2 },
4994 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4995 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4996 pbn_ni8430_4 },
4997 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4998 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4999 pbn_ni8430_4 },
5000 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5001 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5002 pbn_ni8430_8 },
5003 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5004 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5005 pbn_ni8430_8 },
5006 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5007 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5008 pbn_ni8430_16 },
5009 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5010 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5011 pbn_ni8430_16 },
5012 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5013 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5014 pbn_ni8430_2 },
5015 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5016 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5017 pbn_ni8430_2 },
5018 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5019 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5020 pbn_ni8430_4 },
5021 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5022 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5023 pbn_ni8430_4 },
5024
5025 /*
5026 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5027 */
5028 { PCI_VENDOR_ID_ADDIDATA,
5029 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5030 PCI_ANY_ID,
5031 PCI_ANY_ID,
5032 0,
5033 0,
5034 pbn_b0_4_115200 },
5035
5036 { PCI_VENDOR_ID_ADDIDATA,
5037 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5038 PCI_ANY_ID,
5039 PCI_ANY_ID,
5040 0,
5041 0,
5042 pbn_b0_2_115200 },
5043
5044 { PCI_VENDOR_ID_ADDIDATA,
5045 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5046 PCI_ANY_ID,
5047 PCI_ANY_ID,
5048 0,
5049 0,
5050 pbn_b0_1_115200 },
5051
5052 { PCI_VENDOR_ID_AMCC,
5053 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5054 PCI_ANY_ID,
5055 PCI_ANY_ID,
5056 0,
5057 0,
5058 pbn_b1_8_115200 },
5059
5060 { PCI_VENDOR_ID_ADDIDATA,
5061 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5062 PCI_ANY_ID,
5063 PCI_ANY_ID,
5064 0,
5065 0,
5066 pbn_b0_4_115200 },
5067
5068 { PCI_VENDOR_ID_ADDIDATA,
5069 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5070 PCI_ANY_ID,
5071 PCI_ANY_ID,
5072 0,
5073 0,
5074 pbn_b0_2_115200 },
5075
5076 { PCI_VENDOR_ID_ADDIDATA,
5077 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5078 PCI_ANY_ID,
5079 PCI_ANY_ID,
5080 0,
5081 0,
5082 pbn_b0_1_115200 },
5083
5084 { PCI_VENDOR_ID_ADDIDATA,
5085 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5086 PCI_ANY_ID,
5087 PCI_ANY_ID,
5088 0,
5089 0,
5090 pbn_b0_4_115200 },
5091
5092 { PCI_VENDOR_ID_ADDIDATA,
5093 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5094 PCI_ANY_ID,
5095 PCI_ANY_ID,
5096 0,
5097 0,
5098 pbn_b0_2_115200 },
5099
5100 { PCI_VENDOR_ID_ADDIDATA,
5101 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5102 PCI_ANY_ID,
5103 PCI_ANY_ID,
5104 0,
5105 0,
5106 pbn_b0_1_115200 },
5107
5108 { PCI_VENDOR_ID_ADDIDATA,
5109 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5110 PCI_ANY_ID,
5111 PCI_ANY_ID,
5112 0,
5113 0,
5114 pbn_b0_8_115200 },
5115
5116 { PCI_VENDOR_ID_ADDIDATA,
5117 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5118 PCI_ANY_ID,
5119 PCI_ANY_ID,
5120 0,
5121 0,
5122 pbn_ADDIDATA_PCIe_4_3906250 },
5123
5124 { PCI_VENDOR_ID_ADDIDATA,
5125 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5126 PCI_ANY_ID,
5127 PCI_ANY_ID,
5128 0,
5129 0,
5130 pbn_ADDIDATA_PCIe_2_3906250 },
5131
5132 { PCI_VENDOR_ID_ADDIDATA,
5133 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5134 PCI_ANY_ID,
5135 PCI_ANY_ID,
5136 0,
5137 0,
5138 pbn_ADDIDATA_PCIe_1_3906250 },
5139
5140 { PCI_VENDOR_ID_ADDIDATA,
5141 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5142 PCI_ANY_ID,
5143 PCI_ANY_ID,
5144 0,
5145 0,
5146 pbn_ADDIDATA_PCIe_8_3906250 },
5147
5148 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5149 PCI_VENDOR_ID_IBM, 0x0299,
5150 0, 0, pbn_b0_bt_2_115200 },
5151
5152 /*
5153 * other NetMos 9835 devices are most likely handled by the
5154 * parport_serial driver, check drivers/parport/parport_serial.c
5155 * before adding them here.
5156 */
5157
5158 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5159 0xA000, 0x1000,
5160 0, 0, pbn_b0_1_115200 },
5161
5162 /* the 9901 is a rebranded 9912 */
5163 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5164 0xA000, 0x1000,
5165 0, 0, pbn_b0_1_115200 },
5166
5167 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5168 0xA000, 0x1000,
5169 0, 0, pbn_b0_1_115200 },
5170
5171 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5172 0xA000, 0x1000,
5173 0, 0, pbn_b0_1_115200 },
5174
5175 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5176 0xA000, 0x1000,
5177 0, 0, pbn_b0_1_115200 },
5178
5179 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5180 0xA000, 0x3002,
5181 0, 0, pbn_NETMOS9900_2s_115200 },
5182
5183 /*
5184 * Best Connectivity and Rosewill PCI Multi I/O cards
5185 */
5186
5187 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5188 0xA000, 0x1000,
5189 0, 0, pbn_b0_1_115200 },
5190
5191 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5192 0xA000, 0x3002,
5193 0, 0, pbn_b0_bt_2_115200 },
5194
5195 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5196 0xA000, 0x3004,
5197 0, 0, pbn_b0_bt_4_115200 },
5198 /* Intel CE4100 */
5199 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5200 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5201 pbn_ce4100_1_115200 },
5202
5203 /*
5204 * Cronyx Omega PCI
5205 */
5206 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5207 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5208 pbn_omegapci },
5209
5210 /*
5211 * Broadcom TruManage
5212 */
5213 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5214 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5215 pbn_brcm_trumanage },
5216
5217 /*
5218 * AgeStar as-prs2-009
5219 */
5220 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5221 PCI_ANY_ID, PCI_ANY_ID,
5222 0, 0, pbn_b0_bt_2_115200 },
5223
5224 /*
5225 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5226 * so not listed here.
5227 */
5228 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5229 PCI_ANY_ID, PCI_ANY_ID,
5230 0, 0, pbn_b0_bt_4_115200 },
5231
5232 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5233 PCI_ANY_ID, PCI_ANY_ID,
5234 0, 0, pbn_b0_bt_2_115200 },
5235
5236 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5237 PCI_ANY_ID, PCI_ANY_ID,
5238 0, 0, pbn_b0_bt_4_115200 },
5239
5240 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5241 PCI_ANY_ID, PCI_ANY_ID,
5242 0, 0, pbn_wch382_2 },
5243
5244 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5245 PCI_ANY_ID, PCI_ANY_ID,
5246 0, 0, pbn_wch384_4 },
5247
5248 /* Fintek PCI serial cards */
5249 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5250 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5251 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5252
5253 /* MKS Tenta SCOM-080x serial cards */
5254 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5255 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5256
5257 /* Amazon PCI serial device */
5258 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
5259
5260 /*
5261 * These entries match devices with class COMMUNICATION_SERIAL,
5262 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5263 */
5264 { PCI_ANY_ID, PCI_ANY_ID,
5265 PCI_ANY_ID, PCI_ANY_ID,
5266 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5267 0xffff00, pbn_default },
5268 { PCI_ANY_ID, PCI_ANY_ID,
5269 PCI_ANY_ID, PCI_ANY_ID,
5270 PCI_CLASS_COMMUNICATION_MODEM << 8,
5271 0xffff00, pbn_default },
5272 { PCI_ANY_ID, PCI_ANY_ID,
5273 PCI_ANY_ID, PCI_ANY_ID,
5274 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5275 0xffff00, pbn_default },
5276 { 0, }
5277 };
5278
5279 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5280 pci_channel_state_t state)
5281 {
5282 struct serial_private *priv = pci_get_drvdata(dev);
5283
5284 if (state == pci_channel_io_perm_failure)
5285 return PCI_ERS_RESULT_DISCONNECT;
5286
5287 if (priv)
5288 pciserial_detach_ports(priv);
5289
5290 pci_disable_device(dev);
5291
5292 return PCI_ERS_RESULT_NEED_RESET;
5293 }
5294
5295 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5296 {
5297 int rc;
5298
5299 rc = pci_enable_device(dev);
5300
5301 if (rc)
5302 return PCI_ERS_RESULT_DISCONNECT;
5303
5304 pci_restore_state(dev);
5305 pci_save_state(dev);
5306
5307 return PCI_ERS_RESULT_RECOVERED;
5308 }
5309
5310 static void serial8250_io_resume(struct pci_dev *dev)
5311 {
5312 struct serial_private *priv = pci_get_drvdata(dev);
5313 struct serial_private *new;
5314
5315 if (!priv)
5316 return;
5317
5318 new = pciserial_init_ports(dev, priv->board);
5319 if (!IS_ERR(new)) {
5320 pci_set_drvdata(dev, new);
5321 kfree(priv);
5322 }
5323 }
5324
5325 static const struct pci_error_handlers serial8250_err_handler = {
5326 .error_detected = serial8250_io_error_detected,
5327 .slot_reset = serial8250_io_slot_reset,
5328 .resume = serial8250_io_resume,
5329 };
5330
5331 static struct pci_driver serial_pci_driver = {
5332 .name = "serial",
5333 .probe = pciserial_init_one,
5334 .remove = pciserial_remove_one,
5335 .driver = {
5336 .pm = &pciserial_pm_ops,
5337 },
5338 .id_table = serial_pci_tbl,
5339 .err_handler = &serial8250_err_handler,
5340 };
5341
5342 module_pci_driver(serial_pci_driver);
5343
5344 MODULE_LICENSE("GPL");
5345 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5346 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
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