2 * Probe module for 8250/16550-type PCI serial ports.
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
24 #include <linux/rational.h>
26 #include <asm/byteorder.h>
29 #include <linux/dmaengine.h>
30 #include <linux/platform_data/dma-dw.h>
35 * init function returns:
36 * > 0 - number of ports
37 * = 0 - use board->num_ports
40 struct pci_serial_quirk
{
45 int (*probe
)(struct pci_dev
*dev
);
46 int (*init
)(struct pci_dev
*dev
);
47 int (*setup
)(struct serial_private
*,
48 const struct pciserial_board
*,
49 struct uart_8250_port
*, int);
50 void (*exit
)(struct pci_dev
*dev
);
53 #define PCI_NUM_BAR_RESOURCES 6
55 struct serial_private
{
58 struct pci_serial_quirk
*quirk
;
62 static int pci_default_setup(struct serial_private
*,
63 const struct pciserial_board
*, struct uart_8250_port
*, int);
65 static void moan_device(const char *str
, struct pci_dev
*dev
)
69 "Please send the output of lspci -vv, this\n"
70 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
71 "manufacturer and name of serial board or\n"
72 "modem board to <linux-serial@vger.kernel.org>.\n",
73 pci_name(dev
), str
, dev
->vendor
, dev
->device
,
74 dev
->subsystem_vendor
, dev
->subsystem_device
);
78 setup_port(struct serial_private
*priv
, struct uart_8250_port
*port
,
79 int bar
, int offset
, int regshift
)
81 struct pci_dev
*dev
= priv
->dev
;
83 if (bar
>= PCI_NUM_BAR_RESOURCES
)
86 if (pci_resource_flags(dev
, bar
) & IORESOURCE_MEM
) {
87 if (!pcim_iomap(dev
, bar
, 0) && !pcim_iomap_table(dev
))
90 port
->port
.iotype
= UPIO_MEM
;
91 port
->port
.iobase
= 0;
92 port
->port
.mapbase
= pci_resource_start(dev
, bar
) + offset
;
93 port
->port
.membase
= pcim_iomap_table(dev
)[bar
] + offset
;
94 port
->port
.regshift
= regshift
;
96 port
->port
.iotype
= UPIO_PORT
;
97 port
->port
.iobase
= pci_resource_start(dev
, bar
) + offset
;
98 port
->port
.mapbase
= 0;
99 port
->port
.membase
= NULL
;
100 port
->port
.regshift
= 0;
106 * ADDI-DATA GmbH communication cards <info@addi-data.com>
108 static int addidata_apci7800_setup(struct serial_private
*priv
,
109 const struct pciserial_board
*board
,
110 struct uart_8250_port
*port
, int idx
)
112 unsigned int bar
= 0, offset
= board
->first_offset
;
113 bar
= FL_GET_BASE(board
->flags
);
116 offset
+= idx
* board
->uart_offset
;
117 } else if ((idx
>= 2) && (idx
< 4)) {
119 offset
+= ((idx
- 2) * board
->uart_offset
);
120 } else if ((idx
>= 4) && (idx
< 6)) {
122 offset
+= ((idx
- 4) * board
->uart_offset
);
123 } else if (idx
>= 6) {
125 offset
+= ((idx
- 6) * board
->uart_offset
);
128 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
132 * AFAVLAB uses a different mixture of BARs and offsets
133 * Not that ugly ;) -- HW
136 afavlab_setup(struct serial_private
*priv
, const struct pciserial_board
*board
,
137 struct uart_8250_port
*port
, int idx
)
139 unsigned int bar
, offset
= board
->first_offset
;
141 bar
= FL_GET_BASE(board
->flags
);
146 offset
+= (idx
- 4) * board
->uart_offset
;
149 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
153 * HP's Remote Management Console. The Diva chip came in several
154 * different versions. N-class, L2000 and A500 have two Diva chips, each
155 * with 3 UARTs (the third UART on the second chip is unused). Superdome
156 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
157 * one Diva chip, but it has been expanded to 5 UARTs.
159 static int pci_hp_diva_init(struct pci_dev
*dev
)
163 switch (dev
->subsystem_device
) {
164 case PCI_DEVICE_ID_HP_DIVA_TOSCA1
:
165 case PCI_DEVICE_ID_HP_DIVA_HALFDOME
:
166 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE
:
167 case PCI_DEVICE_ID_HP_DIVA_EVEREST
:
170 case PCI_DEVICE_ID_HP_DIVA_TOSCA2
:
173 case PCI_DEVICE_ID_HP_DIVA_MAESTRO
:
176 case PCI_DEVICE_ID_HP_DIVA_POWERBAR
:
177 case PCI_DEVICE_ID_HP_DIVA_HURRICANE
:
186 * HP's Diva chip puts the 4th/5th serial port further out, and
187 * some serial ports are supposed to be hidden on certain models.
190 pci_hp_diva_setup(struct serial_private
*priv
,
191 const struct pciserial_board
*board
,
192 struct uart_8250_port
*port
, int idx
)
194 unsigned int offset
= board
->first_offset
;
195 unsigned int bar
= FL_GET_BASE(board
->flags
);
197 switch (priv
->dev
->subsystem_device
) {
198 case PCI_DEVICE_ID_HP_DIVA_MAESTRO
:
202 case PCI_DEVICE_ID_HP_DIVA_EVEREST
:
212 offset
+= idx
* board
->uart_offset
;
214 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
218 * Added for EKF Intel i960 serial boards
220 static int pci_inteli960ni_init(struct pci_dev
*dev
)
224 if (!(dev
->subsystem_device
& 0x1000))
227 /* is firmware started? */
228 pci_read_config_dword(dev
, 0x44, &oldval
);
229 if (oldval
== 0x00001000L
) { /* RESET value */
230 dev_dbg(&dev
->dev
, "Local i960 firmware missing\n");
237 * Some PCI serial cards using the PLX 9050 PCI interface chip require
238 * that the card interrupt be explicitly enabled or disabled. This
239 * seems to be mainly needed on card using the PLX which also use I/O
242 static int pci_plx9050_init(struct pci_dev
*dev
)
247 if ((pci_resource_flags(dev
, 0) & IORESOURCE_MEM
) == 0) {
248 moan_device("no memory in bar 0", dev
);
253 if (dev
->vendor
== PCI_VENDOR_ID_PANACOM
||
254 dev
->subsystem_vendor
== PCI_SUBVENDOR_ID_EXSYS
)
257 if ((dev
->vendor
== PCI_VENDOR_ID_PLX
) &&
258 (dev
->device
== PCI_DEVICE_ID_PLX_ROMULUS
))
260 * As the megawolf cards have the int pins active
261 * high, and have 2 UART chips, both ints must be
262 * enabled on the 9050. Also, the UARTS are set in
263 * 16450 mode by default, so we have to enable the
264 * 16C950 'enhanced' mode so that we can use the
269 * enable/disable interrupts
271 p
= ioremap_nocache(pci_resource_start(dev
, 0), 0x80);
274 writel(irq_config
, p
+ 0x4c);
277 * Read the register back to ensure that it took effect.
285 static void pci_plx9050_exit(struct pci_dev
*dev
)
289 if ((pci_resource_flags(dev
, 0) & IORESOURCE_MEM
) == 0)
295 p
= ioremap_nocache(pci_resource_start(dev
, 0), 0x80);
300 * Read the register back to ensure that it took effect.
307 #define NI8420_INT_ENABLE_REG 0x38
308 #define NI8420_INT_ENABLE_BIT 0x2000
310 static void pci_ni8420_exit(struct pci_dev
*dev
)
313 unsigned int bar
= 0;
315 if ((pci_resource_flags(dev
, bar
) & IORESOURCE_MEM
) == 0) {
316 moan_device("no memory in bar", dev
);
320 p
= pci_ioremap_bar(dev
, bar
);
324 /* Disable the CPU Interrupt */
325 writel(readl(p
+ NI8420_INT_ENABLE_REG
) & ~(NI8420_INT_ENABLE_BIT
),
326 p
+ NI8420_INT_ENABLE_REG
);
332 #define MITE_IOWBSR1 0xc4
333 #define MITE_IOWCR1 0xf4
334 #define MITE_LCIMR1 0x08
335 #define MITE_LCIMR2 0x10
337 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
339 static void pci_ni8430_exit(struct pci_dev
*dev
)
342 unsigned int bar
= 0;
344 if ((pci_resource_flags(dev
, bar
) & IORESOURCE_MEM
) == 0) {
345 moan_device("no memory in bar", dev
);
349 p
= pci_ioremap_bar(dev
, bar
);
353 /* Disable the CPU Interrupt */
354 writel(MITE_LCIMR2_CLR_CPU_IE
, p
+ MITE_LCIMR2
);
358 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
360 sbs_setup(struct serial_private
*priv
, const struct pciserial_board
*board
,
361 struct uart_8250_port
*port
, int idx
)
363 unsigned int bar
, offset
= board
->first_offset
;
368 /* first four channels map to 0, 0x100, 0x200, 0x300 */
369 offset
+= idx
* board
->uart_offset
;
370 } else if (idx
< 8) {
371 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
372 offset
+= idx
* board
->uart_offset
+ 0xC00;
373 } else /* we have only 8 ports on PMC-OCTALPRO */
376 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
380 * This does initialization for PMC OCTALPRO cards:
381 * maps the device memory, resets the UARTs (needed, bc
382 * if the module is removed and inserted again, the card
383 * is in the sleep mode) and enables global interrupt.
386 /* global control register offset for SBS PMC-OctalPro */
387 #define OCT_REG_CR_OFF 0x500
389 static int sbs_init(struct pci_dev
*dev
)
393 p
= pci_ioremap_bar(dev
, 0);
397 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
398 writeb(0x10, p
+ OCT_REG_CR_OFF
);
400 writeb(0x0, p
+ OCT_REG_CR_OFF
);
402 /* Set bit-2 (INTENABLE) of Control Register */
403 writeb(0x4, p
+ OCT_REG_CR_OFF
);
410 * Disables the global interrupt of PMC-OctalPro
413 static void sbs_exit(struct pci_dev
*dev
)
417 p
= pci_ioremap_bar(dev
, 0);
418 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
420 writeb(0, p
+ OCT_REG_CR_OFF
);
425 * SIIG serial cards have an PCI interface chip which also controls
426 * the UART clocking frequency. Each UART can be clocked independently
427 * (except cards equipped with 4 UARTs) and initial clocking settings
428 * are stored in the EEPROM chip. It can cause problems because this
429 * version of serial driver doesn't support differently clocked UART's
430 * on single PCI card. To prevent this, initialization functions set
431 * high frequency clocking for all UART's on given card. It is safe (I
432 * hope) because it doesn't touch EEPROM settings to prevent conflicts
433 * with other OSes (like M$ DOS).
435 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
437 * There is two family of SIIG serial cards with different PCI
438 * interface chip and different configuration methods:
439 * - 10x cards have control registers in IO and/or memory space;
440 * - 20x cards have control registers in standard PCI configuration space.
442 * Note: all 10x cards have PCI device ids 0x10..
443 * all 20x cards have PCI device ids 0x20..
445 * There are also Quartet Serial cards which use Oxford Semiconductor
446 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
448 * Note: some SIIG cards are probed by the parport_serial object.
451 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
452 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
454 static int pci_siig10x_init(struct pci_dev
*dev
)
459 switch (dev
->device
& 0xfff8) {
460 case PCI_DEVICE_ID_SIIG_1S_10x
: /* 1S */
463 case PCI_DEVICE_ID_SIIG_2S_10x
: /* 2S, 2S1P */
466 default: /* 1S1P, 4S */
471 p
= ioremap_nocache(pci_resource_start(dev
, 0), 0x80);
475 writew(readw(p
+ 0x28) & data
, p
+ 0x28);
481 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
482 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
484 static int pci_siig20x_init(struct pci_dev
*dev
)
488 /* Change clock frequency for the first UART. */
489 pci_read_config_byte(dev
, 0x6f, &data
);
490 pci_write_config_byte(dev
, 0x6f, data
& 0xef);
492 /* If this card has 2 UART, we have to do the same with second UART. */
493 if (((dev
->device
& 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x
) ||
494 ((dev
->device
& 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x
)) {
495 pci_read_config_byte(dev
, 0x73, &data
);
496 pci_write_config_byte(dev
, 0x73, data
& 0xef);
501 static int pci_siig_init(struct pci_dev
*dev
)
503 unsigned int type
= dev
->device
& 0xff00;
506 return pci_siig10x_init(dev
);
507 else if (type
== 0x2000)
508 return pci_siig20x_init(dev
);
510 moan_device("Unknown SIIG card", dev
);
514 static int pci_siig_setup(struct serial_private
*priv
,
515 const struct pciserial_board
*board
,
516 struct uart_8250_port
*port
, int idx
)
518 unsigned int bar
= FL_GET_BASE(board
->flags
) + idx
, offset
= 0;
522 offset
= (idx
- 4) * 8;
525 return setup_port(priv
, port
, bar
, offset
, 0);
529 * Timedia has an explosion of boards, and to avoid the PCI table from
530 * growing *huge*, we use this function to collapse some 70 entries
531 * in the PCI table into one, for sanity's and compactness's sake.
533 static const unsigned short timedia_single_port
[] = {
534 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
537 static const unsigned short timedia_dual_port
[] = {
538 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
539 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
540 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
541 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
545 static const unsigned short timedia_quad_port
[] = {
546 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
547 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
548 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
552 static const unsigned short timedia_eight_port
[] = {
553 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
554 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
557 static const struct timedia_struct
{
559 const unsigned short *ids
;
561 { 1, timedia_single_port
},
562 { 2, timedia_dual_port
},
563 { 4, timedia_quad_port
},
564 { 8, timedia_eight_port
}
568 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
569 * listing them individually, this driver merely grabs them all with
570 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
571 * and should be left free to be claimed by parport_serial instead.
573 static int pci_timedia_probe(struct pci_dev
*dev
)
576 * Check the third digit of the subdevice ID
577 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
579 if ((dev
->subsystem_device
& 0x00f0) >= 0x70) {
581 "ignoring Timedia subdevice %04x for parport_serial\n",
582 dev
->subsystem_device
);
589 static int pci_timedia_init(struct pci_dev
*dev
)
591 const unsigned short *ids
;
594 for (i
= 0; i
< ARRAY_SIZE(timedia_data
); i
++) {
595 ids
= timedia_data
[i
].ids
;
596 for (j
= 0; ids
[j
]; j
++)
597 if (dev
->subsystem_device
== ids
[j
])
598 return timedia_data
[i
].num
;
604 * Timedia/SUNIX uses a mixture of BARs and offsets
605 * Ugh, this is ugly as all hell --- TYT
608 pci_timedia_setup(struct serial_private
*priv
,
609 const struct pciserial_board
*board
,
610 struct uart_8250_port
*port
, int idx
)
612 unsigned int bar
= 0, offset
= board
->first_offset
;
619 offset
= board
->uart_offset
;
626 offset
= board
->uart_offset
;
635 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
639 * Some Titan cards are also a little weird
642 titan_400l_800l_setup(struct serial_private
*priv
,
643 const struct pciserial_board
*board
,
644 struct uart_8250_port
*port
, int idx
)
646 unsigned int bar
, offset
= board
->first_offset
;
657 offset
= (idx
- 2) * board
->uart_offset
;
660 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
663 static int pci_xircom_init(struct pci_dev
*dev
)
669 static int pci_ni8420_init(struct pci_dev
*dev
)
672 unsigned int bar
= 0;
674 if ((pci_resource_flags(dev
, bar
) & IORESOURCE_MEM
) == 0) {
675 moan_device("no memory in bar", dev
);
679 p
= pci_ioremap_bar(dev
, bar
);
683 /* Enable CPU Interrupt */
684 writel(readl(p
+ NI8420_INT_ENABLE_REG
) | NI8420_INT_ENABLE_BIT
,
685 p
+ NI8420_INT_ENABLE_REG
);
691 #define MITE_IOWBSR1_WSIZE 0xa
692 #define MITE_IOWBSR1_WIN_OFFSET 0x800
693 #define MITE_IOWBSR1_WENAB (1 << 7)
694 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
695 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
696 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
698 static int pci_ni8430_init(struct pci_dev
*dev
)
701 struct pci_bus_region region
;
703 unsigned int bar
= 0;
705 if ((pci_resource_flags(dev
, bar
) & IORESOURCE_MEM
) == 0) {
706 moan_device("no memory in bar", dev
);
710 p
= pci_ioremap_bar(dev
, bar
);
715 * Set device window address and size in BAR0, while acknowledging that
716 * the resource structure may contain a translated address that differs
717 * from the address the device responds to.
719 pcibios_resource_to_bus(dev
->bus
, ®ion
, &dev
->resource
[bar
]);
720 device_window
= ((region
.start
+ MITE_IOWBSR1_WIN_OFFSET
) & 0xffffff00)
721 | MITE_IOWBSR1_WENAB
| MITE_IOWBSR1_WSIZE
;
722 writel(device_window
, p
+ MITE_IOWBSR1
);
724 /* Set window access to go to RAMSEL IO address space */
725 writel((readl(p
+ MITE_IOWCR1
) & MITE_IOWCR1_RAMSEL_MASK
),
728 /* Enable IO Bus Interrupt 0 */
729 writel(MITE_LCIMR1_IO_IE_0
, p
+ MITE_LCIMR1
);
731 /* Enable CPU Interrupt */
732 writel(MITE_LCIMR2_SET_CPU_IE
, p
+ MITE_LCIMR2
);
738 /* UART Port Control Register */
739 #define NI8430_PORTCON 0x0f
740 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
743 pci_ni8430_setup(struct serial_private
*priv
,
744 const struct pciserial_board
*board
,
745 struct uart_8250_port
*port
, int idx
)
747 struct pci_dev
*dev
= priv
->dev
;
749 unsigned int bar
, offset
= board
->first_offset
;
751 if (idx
>= board
->num_ports
)
754 bar
= FL_GET_BASE(board
->flags
);
755 offset
+= idx
* board
->uart_offset
;
757 p
= pci_ioremap_bar(dev
, bar
);
761 /* enable the transceiver */
762 writeb(readb(p
+ offset
+ NI8430_PORTCON
) | NI8430_PORTCON_TXVR_ENABLE
,
763 p
+ offset
+ NI8430_PORTCON
);
767 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
770 static int pci_netmos_9900_setup(struct serial_private
*priv
,
771 const struct pciserial_board
*board
,
772 struct uart_8250_port
*port
, int idx
)
776 if ((priv
->dev
->device
!= PCI_DEVICE_ID_NETMOS_9865
) &&
777 (priv
->dev
->subsystem_device
& 0xff00) == 0x3000) {
778 /* netmos apparently orders BARs by datasheet layout, so serial
779 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
783 return setup_port(priv
, port
, bar
, 0, board
->reg_shift
);
785 return pci_default_setup(priv
, board
, port
, idx
);
789 /* the 99xx series comes with a range of device IDs and a variety
792 * 9900 has varying capabilities and can cascade to sub-controllers
793 * (cascading should be purely internal)
794 * 9904 is hardwired with 4 serial ports
795 * 9912 and 9922 are hardwired with 2 serial ports
797 static int pci_netmos_9900_numports(struct pci_dev
*dev
)
799 unsigned int c
= dev
->class;
801 unsigned short sub_serports
;
808 if ((pi
== 0) && (dev
->device
== PCI_DEVICE_ID_NETMOS_9900
)) {
809 /* two possibilities: 0x30ps encodes number of parallel and
810 * serial ports, or 0x1000 indicates *something*. This is not
811 * immediately obvious, since the 2s1p+4s configuration seems
812 * to offer all functionality on functions 0..2, while still
813 * advertising the same function 3 as the 4s+2s1p config.
815 sub_serports
= dev
->subsystem_device
& 0xf;
816 if (sub_serports
> 0)
820 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
824 moan_device("unknown NetMos/Mostech program interface", dev
);
828 static int pci_netmos_init(struct pci_dev
*dev
)
830 /* subdevice 0x00PS means <P> parallel, <S> serial */
831 unsigned int num_serial
= dev
->subsystem_device
& 0xf;
833 if ((dev
->device
== PCI_DEVICE_ID_NETMOS_9901
) ||
834 (dev
->device
== PCI_DEVICE_ID_NETMOS_9865
))
837 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_IBM
&&
838 dev
->subsystem_device
== 0x0299)
841 switch (dev
->device
) { /* FALLTHROUGH on all */
842 case PCI_DEVICE_ID_NETMOS_9904
:
843 case PCI_DEVICE_ID_NETMOS_9912
:
844 case PCI_DEVICE_ID_NETMOS_9922
:
845 case PCI_DEVICE_ID_NETMOS_9900
:
846 num_serial
= pci_netmos_9900_numports(dev
);
853 if (num_serial
== 0) {
854 moan_device("unknown NetMos/Mostech device", dev
);
862 * These chips are available with optionally one parallel port and up to
863 * two serial ports. Unfortunately they all have the same product id.
865 * Basic configuration is done over a region of 32 I/O ports. The base
866 * ioport is called INTA or INTC, depending on docs/other drivers.
868 * The region of the 32 I/O ports is configured in POSIO0R...
872 #define ITE_887x_MISCR 0x9c
873 #define ITE_887x_INTCBAR 0x78
874 #define ITE_887x_UARTBAR 0x7c
875 #define ITE_887x_PS0BAR 0x10
876 #define ITE_887x_POSIO0 0x60
879 #define ITE_887x_IOSIZE 32
880 /* I/O space size (bits 26-24; 8 bytes = 011b) */
881 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
882 /* I/O space size (bits 26-24; 32 bytes = 101b) */
883 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
884 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
885 #define ITE_887x_POSIO_SPEED (3 << 29)
886 /* enable IO_Space bit */
887 #define ITE_887x_POSIO_ENABLE (1 << 31)
889 static int pci_ite887x_init(struct pci_dev
*dev
)
891 /* inta_addr are the configuration addresses of the ITE */
892 static const short inta_addr
[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
895 struct resource
*iobase
= NULL
;
896 u32 miscr
, uartbar
, ioport
;
898 /* search for the base-ioport */
900 while (inta_addr
[i
] && iobase
== NULL
) {
901 iobase
= request_region(inta_addr
[i
], ITE_887x_IOSIZE
,
903 if (iobase
!= NULL
) {
904 /* write POSIO0R - speed | size | ioport */
905 pci_write_config_dword(dev
, ITE_887x_POSIO0
,
906 ITE_887x_POSIO_ENABLE
| ITE_887x_POSIO_SPEED
|
907 ITE_887x_POSIO_IOSIZE_32
| inta_addr
[i
]);
908 /* write INTCBAR - ioport */
909 pci_write_config_dword(dev
, ITE_887x_INTCBAR
,
911 ret
= inb(inta_addr
[i
]);
913 /* ioport connected */
916 release_region(iobase
->start
, ITE_887x_IOSIZE
);
923 dev_err(&dev
->dev
, "ite887x: could not find iobase\n");
927 /* start of undocumented type checking (see parport_pc.c) */
928 type
= inb(iobase
->start
+ 0x18) & 0x0f;
931 case 0x2: /* ITE8871 (1P) */
932 case 0xa: /* ITE8875 (1P) */
935 case 0xe: /* ITE8872 (2S1P) */
938 case 0x6: /* ITE8873 (1S) */
941 case 0x8: /* ITE8874 (2S) */
945 moan_device("Unknown ITE887x", dev
);
949 /* configure all serial ports */
950 for (i
= 0; i
< ret
; i
++) {
951 /* read the I/O port from the device */
952 pci_read_config_dword(dev
, ITE_887x_PS0BAR
+ (0x4 * (i
+ 1)),
954 ioport
&= 0x0000FF00; /* the actual base address */
955 pci_write_config_dword(dev
, ITE_887x_POSIO0
+ (0x4 * (i
+ 1)),
956 ITE_887x_POSIO_ENABLE
| ITE_887x_POSIO_SPEED
|
957 ITE_887x_POSIO_IOSIZE_8
| ioport
);
959 /* write the ioport to the UARTBAR */
960 pci_read_config_dword(dev
, ITE_887x_UARTBAR
, &uartbar
);
961 uartbar
&= ~(0xffff << (16 * i
)); /* clear half the reg */
962 uartbar
|= (ioport
<< (16 * i
)); /* set the ioport */
963 pci_write_config_dword(dev
, ITE_887x_UARTBAR
, uartbar
);
965 /* get current config */
966 pci_read_config_dword(dev
, ITE_887x_MISCR
, &miscr
);
967 /* disable interrupts (UARTx_Routing[3:0]) */
968 miscr
&= ~(0xf << (12 - 4 * i
));
969 /* activate the UART (UARTx_En) */
970 miscr
|= 1 << (23 - i
);
971 /* write new config with activated UART */
972 pci_write_config_dword(dev
, ITE_887x_MISCR
, miscr
);
976 /* the device has no UARTs if we get here */
977 release_region(iobase
->start
, ITE_887x_IOSIZE
);
983 static void pci_ite887x_exit(struct pci_dev
*dev
)
986 /* the ioport is bit 0-15 in POSIO0R */
987 pci_read_config_dword(dev
, ITE_887x_POSIO0
, &ioport
);
989 release_region(ioport
, ITE_887x_IOSIZE
);
993 * EndRun Technologies.
994 * Determine the number of ports available on the device.
996 #define PCI_VENDOR_ID_ENDRUN 0x7401
997 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
999 static int pci_endrun_init(struct pci_dev
*dev
)
1002 unsigned long deviceID
;
1003 unsigned int number_uarts
= 0;
1005 /* EndRun device is all 0xexxx */
1006 if (dev
->vendor
== PCI_VENDOR_ID_ENDRUN
&&
1007 (dev
->device
& 0xf000) != 0xe000)
1010 p
= pci_iomap(dev
, 0, 5);
1014 deviceID
= ioread32(p
);
1016 if (deviceID
== 0x07000200) {
1017 number_uarts
= ioread8(p
+ 4);
1019 "%d ports detected on EndRun PCI Express device\n",
1022 pci_iounmap(dev
, p
);
1023 return number_uarts
;
1027 * Oxford Semiconductor Inc.
1028 * Check that device is part of the Tornado range of devices, then determine
1029 * the number of ports available on the device.
1031 static int pci_oxsemi_tornado_init(struct pci_dev
*dev
)
1034 unsigned long deviceID
;
1035 unsigned int number_uarts
= 0;
1037 /* OxSemi Tornado devices are all 0xCxxx */
1038 if (dev
->vendor
== PCI_VENDOR_ID_OXSEMI
&&
1039 (dev
->device
& 0xF000) != 0xC000)
1042 p
= pci_iomap(dev
, 0, 5);
1046 deviceID
= ioread32(p
);
1047 /* Tornado device */
1048 if (deviceID
== 0x07000200) {
1049 number_uarts
= ioread8(p
+ 4);
1051 "%d ports detected on Oxford PCI Express device\n",
1054 pci_iounmap(dev
, p
);
1055 return number_uarts
;
1058 static int pci_asix_setup(struct serial_private
*priv
,
1059 const struct pciserial_board
*board
,
1060 struct uart_8250_port
*port
, int idx
)
1062 port
->bugs
|= UART_BUG_PARITY
;
1063 return pci_default_setup(priv
, board
, port
, idx
);
1066 /* Quatech devices have their own extra interface features */
1068 struct quatech_feature
{
1073 #define QPCR_TEST_FOR1 0x3F
1074 #define QPCR_TEST_GET1 0x00
1075 #define QPCR_TEST_FOR2 0x40
1076 #define QPCR_TEST_GET2 0x40
1077 #define QPCR_TEST_FOR3 0x80
1078 #define QPCR_TEST_GET3 0x40
1079 #define QPCR_TEST_FOR4 0xC0
1080 #define QPCR_TEST_GET4 0x80
1082 #define QOPR_CLOCK_X1 0x0000
1083 #define QOPR_CLOCK_X2 0x0001
1084 #define QOPR_CLOCK_X4 0x0002
1085 #define QOPR_CLOCK_X8 0x0003
1086 #define QOPR_CLOCK_RATE_MASK 0x0003
1089 static struct quatech_feature quatech_cards
[] = {
1090 { PCI_DEVICE_ID_QUATECH_QSC100
, 1 },
1091 { PCI_DEVICE_ID_QUATECH_DSC100
, 1 },
1092 { PCI_DEVICE_ID_QUATECH_DSC100E
, 0 },
1093 { PCI_DEVICE_ID_QUATECH_DSC200
, 1 },
1094 { PCI_DEVICE_ID_QUATECH_DSC200E
, 0 },
1095 { PCI_DEVICE_ID_QUATECH_ESC100D
, 1 },
1096 { PCI_DEVICE_ID_QUATECH_ESC100M
, 1 },
1097 { PCI_DEVICE_ID_QUATECH_QSCP100
, 1 },
1098 { PCI_DEVICE_ID_QUATECH_DSCP100
, 1 },
1099 { PCI_DEVICE_ID_QUATECH_QSCP200
, 1 },
1100 { PCI_DEVICE_ID_QUATECH_DSCP200
, 1 },
1101 { PCI_DEVICE_ID_QUATECH_ESCLP100
, 0 },
1102 { PCI_DEVICE_ID_QUATECH_QSCLP100
, 0 },
1103 { PCI_DEVICE_ID_QUATECH_DSCLP100
, 0 },
1104 { PCI_DEVICE_ID_QUATECH_SSCLP100
, 0 },
1105 { PCI_DEVICE_ID_QUATECH_QSCLP200
, 0 },
1106 { PCI_DEVICE_ID_QUATECH_DSCLP200
, 0 },
1107 { PCI_DEVICE_ID_QUATECH_SSCLP200
, 0 },
1108 { PCI_DEVICE_ID_QUATECH_SPPXP_100
, 0 },
1112 static int pci_quatech_amcc(u16 devid
)
1114 struct quatech_feature
*qf
= &quatech_cards
[0];
1116 if (qf
->devid
== devid
)
1120 pr_err("quatech: unknown port type '0x%04X'.\n", devid
);
1124 static int pci_quatech_rqopr(struct uart_8250_port
*port
)
1126 unsigned long base
= port
->port
.iobase
;
1129 LCR
= inb(base
+ UART_LCR
);
1130 outb(0xBF, base
+ UART_LCR
);
1131 val
= inb(base
+ UART_SCR
);
1132 outb(LCR
, base
+ UART_LCR
);
1136 static void pci_quatech_wqopr(struct uart_8250_port
*port
, u8 qopr
)
1138 unsigned long base
= port
->port
.iobase
;
1141 LCR
= inb(base
+ UART_LCR
);
1142 outb(0xBF, base
+ UART_LCR
);
1143 inb(base
+ UART_SCR
);
1144 outb(qopr
, base
+ UART_SCR
);
1145 outb(LCR
, base
+ UART_LCR
);
1148 static int pci_quatech_rqmcr(struct uart_8250_port
*port
)
1150 unsigned long base
= port
->port
.iobase
;
1153 LCR
= inb(base
+ UART_LCR
);
1154 outb(0xBF, base
+ UART_LCR
);
1155 val
= inb(base
+ UART_SCR
);
1156 outb(val
| 0x10, base
+ UART_SCR
);
1157 qmcr
= inb(base
+ UART_MCR
);
1158 outb(val
, base
+ UART_SCR
);
1159 outb(LCR
, base
+ UART_LCR
);
1164 static void pci_quatech_wqmcr(struct uart_8250_port
*port
, u8 qmcr
)
1166 unsigned long base
= port
->port
.iobase
;
1169 LCR
= inb(base
+ UART_LCR
);
1170 outb(0xBF, base
+ UART_LCR
);
1171 val
= inb(base
+ UART_SCR
);
1172 outb(val
| 0x10, base
+ UART_SCR
);
1173 outb(qmcr
, base
+ UART_MCR
);
1174 outb(val
, base
+ UART_SCR
);
1175 outb(LCR
, base
+ UART_LCR
);
1178 static int pci_quatech_has_qmcr(struct uart_8250_port
*port
)
1180 unsigned long base
= port
->port
.iobase
;
1183 LCR
= inb(base
+ UART_LCR
);
1184 outb(0xBF, base
+ UART_LCR
);
1185 val
= inb(base
+ UART_SCR
);
1187 outb(0x80, UART_LCR
);
1188 if (!(inb(UART_SCR
) & 0x20)) {
1189 outb(LCR
, base
+ UART_LCR
);
1196 static int pci_quatech_test(struct uart_8250_port
*port
)
1200 qopr
= pci_quatech_rqopr(port
);
1201 pci_quatech_wqopr(port
, qopr
& QPCR_TEST_FOR1
);
1202 reg
= pci_quatech_rqopr(port
) & 0xC0;
1203 if (reg
!= QPCR_TEST_GET1
)
1205 pci_quatech_wqopr(port
, (qopr
& QPCR_TEST_FOR1
)|QPCR_TEST_FOR2
);
1206 reg
= pci_quatech_rqopr(port
) & 0xC0;
1207 if (reg
!= QPCR_TEST_GET2
)
1209 pci_quatech_wqopr(port
, (qopr
& QPCR_TEST_FOR1
)|QPCR_TEST_FOR3
);
1210 reg
= pci_quatech_rqopr(port
) & 0xC0;
1211 if (reg
!= QPCR_TEST_GET3
)
1213 pci_quatech_wqopr(port
, (qopr
& QPCR_TEST_FOR1
)|QPCR_TEST_FOR4
);
1214 reg
= pci_quatech_rqopr(port
) & 0xC0;
1215 if (reg
!= QPCR_TEST_GET4
)
1218 pci_quatech_wqopr(port
, qopr
);
1222 static int pci_quatech_clock(struct uart_8250_port
*port
)
1225 unsigned long clock
;
1227 if (pci_quatech_test(port
) < 0)
1230 qopr
= pci_quatech_rqopr(port
);
1232 pci_quatech_wqopr(port
, qopr
& ~QOPR_CLOCK_X8
);
1233 reg
= pci_quatech_rqopr(port
);
1234 if (reg
& QOPR_CLOCK_X8
) {
1238 pci_quatech_wqopr(port
, qopr
| QOPR_CLOCK_X8
);
1239 reg
= pci_quatech_rqopr(port
);
1240 if (!(reg
& QOPR_CLOCK_X8
)) {
1244 reg
&= QOPR_CLOCK_X8
;
1245 if (reg
== QOPR_CLOCK_X2
) {
1247 set
= QOPR_CLOCK_X2
;
1248 } else if (reg
== QOPR_CLOCK_X4
) {
1250 set
= QOPR_CLOCK_X4
;
1251 } else if (reg
== QOPR_CLOCK_X8
) {
1253 set
= QOPR_CLOCK_X8
;
1256 set
= QOPR_CLOCK_X1
;
1258 qopr
&= ~QOPR_CLOCK_RATE_MASK
;
1262 pci_quatech_wqopr(port
, qopr
);
1266 static int pci_quatech_rs422(struct uart_8250_port
*port
)
1271 if (!pci_quatech_has_qmcr(port
))
1273 qmcr
= pci_quatech_rqmcr(port
);
1274 pci_quatech_wqmcr(port
, 0xFF);
1275 if (pci_quatech_rqmcr(port
))
1277 pci_quatech_wqmcr(port
, qmcr
);
1281 static int pci_quatech_init(struct pci_dev
*dev
)
1283 if (pci_quatech_amcc(dev
->device
)) {
1284 unsigned long base
= pci_resource_start(dev
, 0);
1288 outl(inl(base
+ 0x38) | 0x00002000, base
+ 0x38);
1289 tmp
= inl(base
+ 0x3c);
1290 outl(tmp
| 0x01000000, base
+ 0x3c);
1291 outl(tmp
&= ~0x01000000, base
+ 0x3c);
1297 static int pci_quatech_setup(struct serial_private
*priv
,
1298 const struct pciserial_board
*board
,
1299 struct uart_8250_port
*port
, int idx
)
1301 /* Needed by pci_quatech calls below */
1302 port
->port
.iobase
= pci_resource_start(priv
->dev
, FL_GET_BASE(board
->flags
));
1303 /* Set up the clocking */
1304 port
->port
.uartclk
= pci_quatech_clock(port
);
1305 /* For now just warn about RS422 */
1306 if (pci_quatech_rs422(port
))
1307 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1308 return pci_default_setup(priv
, board
, port
, idx
);
1311 static void pci_quatech_exit(struct pci_dev
*dev
)
1315 static int pci_default_setup(struct serial_private
*priv
,
1316 const struct pciserial_board
*board
,
1317 struct uart_8250_port
*port
, int idx
)
1319 unsigned int bar
, offset
= board
->first_offset
, maxnr
;
1321 bar
= FL_GET_BASE(board
->flags
);
1322 if (board
->flags
& FL_BASE_BARS
)
1325 offset
+= idx
* board
->uart_offset
;
1327 maxnr
= (pci_resource_len(priv
->dev
, bar
) - board
->first_offset
) >>
1328 (board
->reg_shift
+ 3);
1330 if (board
->flags
& FL_REGION_SZ_CAP
&& idx
>= maxnr
)
1333 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
1337 ce4100_serial_setup(struct serial_private
*priv
,
1338 const struct pciserial_board
*board
,
1339 struct uart_8250_port
*port
, int idx
)
1343 ret
= setup_port(priv
, port
, idx
, 0, board
->reg_shift
);
1344 port
->port
.iotype
= UPIO_MEM32
;
1345 port
->port
.type
= PORT_XSCALE
;
1346 port
->port
.flags
= (port
->port
.flags
| UPF_FIXED_PORT
| UPF_FIXED_TYPE
);
1347 port
->port
.regshift
= 2;
1352 #define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1353 #define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1355 #define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a
1356 #define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c
1358 #define PCI_DEVICE_ID_INTEL_BDW_UART1 0x9ce3
1359 #define PCI_DEVICE_ID_INTEL_BDW_UART2 0x9ce4
1361 #define BYT_PRV_CLK 0x800
1362 #define BYT_PRV_CLK_EN (1 << 0)
1363 #define BYT_PRV_CLK_M_VAL_SHIFT 1
1364 #define BYT_PRV_CLK_N_VAL_SHIFT 16
1365 #define BYT_PRV_CLK_UPDATE (1 << 31)
1367 #define BYT_TX_OVF_INT 0x820
1368 #define BYT_TX_OVF_INT_MASK (1 << 1)
1371 byt_set_termios(struct uart_port
*p
, struct ktermios
*termios
,
1372 struct ktermios
*old
)
1374 unsigned int baud
= tty_termios_baud_rate(termios
);
1375 unsigned long fref
= 100000000, fuart
= baud
* 16;
1376 unsigned long w
= BIT(15) - 1;
1380 /* Gracefully handle the B0 case: fall back to B9600 */
1381 fuart
= fuart
? fuart
: 9600 * 16;
1383 /* Get Fuart closer to Fref */
1384 fuart
*= rounddown_pow_of_two(fref
/ fuart
);
1387 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1388 * dividers must be adjusted.
1390 * uartclk = (m / n) * 100 MHz, where m <= n
1392 rational_best_approximation(fuart
, fref
, w
, w
, &m
, &n
);
1395 /* Reset the clock */
1396 reg
= (m
<< BYT_PRV_CLK_M_VAL_SHIFT
) | (n
<< BYT_PRV_CLK_N_VAL_SHIFT
);
1397 writel(reg
, p
->membase
+ BYT_PRV_CLK
);
1398 reg
|= BYT_PRV_CLK_EN
| BYT_PRV_CLK_UPDATE
;
1399 writel(reg
, p
->membase
+ BYT_PRV_CLK
);
1401 p
->status
&= ~UPSTAT_AUTOCTS
;
1402 if (termios
->c_cflag
& CRTSCTS
)
1403 p
->status
|= UPSTAT_AUTOCTS
;
1405 serial8250_do_set_termios(p
, termios
, old
);
1408 static bool byt_dma_filter(struct dma_chan
*chan
, void *param
)
1410 struct dw_dma_slave
*dws
= param
;
1412 if (dws
->dma_dev
!= chan
->device
->dev
)
1415 chan
->private = dws
;
1420 byt_get_mctrl(struct uart_port
*port
)
1422 unsigned int ret
= serial8250_do_get_mctrl(port
);
1424 /* Force DCD and DSR signals to permanently be reported as active. */
1425 ret
|= TIOCM_CAR
| TIOCM_DSR
;
1431 byt_serial_setup(struct serial_private
*priv
,
1432 const struct pciserial_board
*board
,
1433 struct uart_8250_port
*port
, int idx
)
1435 struct pci_dev
*pdev
= priv
->dev
;
1436 struct device
*dev
= port
->port
.dev
;
1437 struct uart_8250_dma
*dma
;
1438 struct dw_dma_slave
*tx_param
, *rx_param
;
1439 struct pci_dev
*dma_dev
;
1442 dma
= devm_kzalloc(dev
, sizeof(*dma
), GFP_KERNEL
);
1446 tx_param
= devm_kzalloc(dev
, sizeof(*tx_param
), GFP_KERNEL
);
1450 rx_param
= devm_kzalloc(dev
, sizeof(*rx_param
), GFP_KERNEL
);
1454 switch (pdev
->device
) {
1455 case PCI_DEVICE_ID_INTEL_BYT_UART1
:
1456 case PCI_DEVICE_ID_INTEL_BSW_UART1
:
1457 case PCI_DEVICE_ID_INTEL_BDW_UART1
:
1458 rx_param
->src_id
= 3;
1459 tx_param
->dst_id
= 2;
1461 case PCI_DEVICE_ID_INTEL_BYT_UART2
:
1462 case PCI_DEVICE_ID_INTEL_BSW_UART2
:
1463 case PCI_DEVICE_ID_INTEL_BDW_UART2
:
1464 rx_param
->src_id
= 5;
1465 tx_param
->dst_id
= 4;
1471 rx_param
->m_master
= 0;
1472 rx_param
->p_master
= 1;
1474 dma
->rxconf
.src_maxburst
= 16;
1476 tx_param
->m_master
= 0;
1477 tx_param
->p_master
= 1;
1479 dma
->txconf
.dst_maxburst
= 16;
1481 dma_dev
= pci_get_slot(pdev
->bus
, PCI_DEVFN(PCI_SLOT(pdev
->devfn
), 0));
1482 rx_param
->dma_dev
= &dma_dev
->dev
;
1483 tx_param
->dma_dev
= &dma_dev
->dev
;
1485 dma
->fn
= byt_dma_filter
;
1486 dma
->rx_param
= rx_param
;
1487 dma
->tx_param
= tx_param
;
1489 ret
= pci_default_setup(priv
, board
, port
, idx
);
1490 port
->port
.iotype
= UPIO_MEM
;
1491 port
->port
.type
= PORT_16550A
;
1492 port
->port
.flags
= (port
->port
.flags
| UPF_FIXED_PORT
| UPF_FIXED_TYPE
);
1493 port
->port
.set_termios
= byt_set_termios
;
1494 port
->port
.get_mctrl
= byt_get_mctrl
;
1495 port
->port
.fifosize
= 64;
1496 port
->tx_loadsz
= 64;
1498 port
->capabilities
= UART_CAP_FIFO
| UART_CAP_AFE
;
1500 /* Disable Tx counter interrupts */
1501 writel(BYT_TX_OVF_INT_MASK
, port
->port
.membase
+ BYT_TX_OVF_INT
);
1507 pci_omegapci_setup(struct serial_private
*priv
,
1508 const struct pciserial_board
*board
,
1509 struct uart_8250_port
*port
, int idx
)
1511 return setup_port(priv
, port
, 2, idx
* 8, 0);
1515 pci_brcm_trumanage_setup(struct serial_private
*priv
,
1516 const struct pciserial_board
*board
,
1517 struct uart_8250_port
*port
, int idx
)
1519 int ret
= pci_default_setup(priv
, board
, port
, idx
);
1521 port
->port
.type
= PORT_BRCM_TRUMANAGE
;
1522 port
->port
.flags
= (port
->port
.flags
| UPF_FIXED_PORT
| UPF_FIXED_TYPE
);
1526 /* RTS will control by MCR if this bit is 0 */
1527 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1528 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1529 #define FINTEK_RTS_INVERT BIT(5)
1531 /* We should do proper H/W transceiver setting before change to RS485 mode */
1532 static int pci_fintek_rs485_config(struct uart_port
*port
,
1533 struct serial_rs485
*rs485
)
1535 struct pci_dev
*pci_dev
= to_pci_dev(port
->dev
);
1537 u8
*index
= (u8
*) port
->private_data
;
1539 pci_read_config_byte(pci_dev
, 0x40 + 8 * *index
+ 7, &setting
);
1542 rs485
= &port
->rs485
;
1543 else if (rs485
->flags
& SER_RS485_ENABLED
)
1544 memset(rs485
->padding
, 0, sizeof(rs485
->padding
));
1546 memset(rs485
, 0, sizeof(*rs485
));
1548 /* F81504/508/512 not support RTS delay before or after send */
1549 rs485
->flags
&= SER_RS485_ENABLED
| SER_RS485_RTS_ON_SEND
;
1551 if (rs485
->flags
& SER_RS485_ENABLED
) {
1552 /* Enable RTS H/W control mode */
1553 setting
|= FINTEK_RTS_CONTROL_BY_HW
;
1555 if (rs485
->flags
& SER_RS485_RTS_ON_SEND
) {
1556 /* RTS driving high on TX */
1557 setting
&= ~FINTEK_RTS_INVERT
;
1559 /* RTS driving low on TX */
1560 setting
|= FINTEK_RTS_INVERT
;
1563 rs485
->delay_rts_after_send
= 0;
1564 rs485
->delay_rts_before_send
= 0;
1566 /* Disable RTS H/W control mode */
1567 setting
&= ~(FINTEK_RTS_CONTROL_BY_HW
| FINTEK_RTS_INVERT
);
1570 pci_write_config_byte(pci_dev
, 0x40 + 8 * *index
+ 7, setting
);
1572 if (rs485
!= &port
->rs485
)
1573 port
->rs485
= *rs485
;
1578 static int pci_fintek_setup(struct serial_private
*priv
,
1579 const struct pciserial_board
*board
,
1580 struct uart_8250_port
*port
, int idx
)
1582 struct pci_dev
*pdev
= priv
->dev
;
1587 config_base
= 0x40 + 0x08 * idx
;
1589 /* Get the io address from configuration space */
1590 pci_read_config_word(pdev
, config_base
+ 4, &iobase
);
1592 dev_dbg(&pdev
->dev
, "%s: idx=%d iobase=0x%x", __func__
, idx
, iobase
);
1594 port
->port
.iotype
= UPIO_PORT
;
1595 port
->port
.iobase
= iobase
;
1596 port
->port
.rs485_config
= pci_fintek_rs485_config
;
1598 data
= devm_kzalloc(&pdev
->dev
, sizeof(u8
), GFP_KERNEL
);
1602 /* preserve index in PCI configuration space */
1604 port
->port
.private_data
= data
;
1609 static int pci_fintek_init(struct pci_dev
*dev
)
1611 unsigned long iobase
;
1615 struct serial_private
*priv
= pci_get_drvdata(dev
);
1616 struct uart_8250_port
*port
;
1618 switch (dev
->device
) {
1619 case 0x1104: /* 4 ports */
1620 case 0x1108: /* 8 ports */
1621 max_port
= dev
->device
& 0xff;
1623 case 0x1112: /* 12 ports */
1630 /* Get the io address dispatch from the BIOS */
1631 pci_read_config_dword(dev
, 0x24, &bar_data
[0]);
1632 pci_read_config_dword(dev
, 0x20, &bar_data
[1]);
1633 pci_read_config_dword(dev
, 0x1c, &bar_data
[2]);
1635 for (i
= 0; i
< max_port
; ++i
) {
1636 /* UART0 configuration offset start from 0x40 */
1637 config_base
= 0x40 + 0x08 * i
;
1639 /* Calculate Real IO Port */
1640 iobase
= (bar_data
[i
/ 4] & 0xffffffe0) + (i
% 4) * 8;
1642 /* Enable UART I/O port */
1643 pci_write_config_byte(dev
, config_base
+ 0x00, 0x01);
1645 /* Select 128-byte FIFO and 8x FIFO threshold */
1646 pci_write_config_byte(dev
, config_base
+ 0x01, 0x33);
1649 pci_write_config_byte(dev
, config_base
+ 0x04,
1650 (u8
)(iobase
& 0xff));
1653 pci_write_config_byte(dev
, config_base
+ 0x05,
1654 (u8
)((iobase
& 0xff00) >> 8));
1656 pci_write_config_byte(dev
, config_base
+ 0x06, dev
->irq
);
1659 /* re-apply RS232/485 mode when
1660 * pciserial_resume_ports()
1662 port
= serial8250_get_port(priv
->line
[i
]);
1663 pci_fintek_rs485_config(&port
->port
, NULL
);
1665 /* First init without port data
1666 * force init to RS232 Mode
1668 pci_write_config_byte(dev
, config_base
+ 0x07, 0x01);
1675 static int skip_tx_en_setup(struct serial_private
*priv
,
1676 const struct pciserial_board
*board
,
1677 struct uart_8250_port
*port
, int idx
)
1679 port
->port
.flags
|= UPF_NO_TXEN_TEST
;
1680 dev_dbg(&priv
->dev
->dev
,
1681 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1682 priv
->dev
->vendor
, priv
->dev
->device
,
1683 priv
->dev
->subsystem_vendor
, priv
->dev
->subsystem_device
);
1685 return pci_default_setup(priv
, board
, port
, idx
);
1688 static void kt_handle_break(struct uart_port
*p
)
1690 struct uart_8250_port
*up
= up_to_u8250p(p
);
1692 * On receipt of a BI, serial device in Intel ME (Intel
1693 * management engine) needs to have its fifos cleared for sane
1694 * SOL (Serial Over Lan) output.
1696 serial8250_clear_and_reinit_fifos(up
);
1699 static unsigned int kt_serial_in(struct uart_port
*p
, int offset
)
1701 struct uart_8250_port
*up
= up_to_u8250p(p
);
1705 * When the Intel ME (management engine) gets reset its serial
1706 * port registers could return 0 momentarily. Functions like
1707 * serial8250_console_write, read and save the IER, perform
1708 * some operation and then restore it. In order to avoid
1709 * setting IER register inadvertently to 0, if the value read
1710 * is 0, double check with ier value in uart_8250_port and use
1711 * that instead. up->ier should be the same value as what is
1712 * currently configured.
1714 val
= inb(p
->iobase
+ offset
);
1715 if (offset
== UART_IER
) {
1722 static int kt_serial_setup(struct serial_private
*priv
,
1723 const struct pciserial_board
*board
,
1724 struct uart_8250_port
*port
, int idx
)
1726 port
->port
.flags
|= UPF_BUG_THRE
;
1727 port
->port
.serial_in
= kt_serial_in
;
1728 port
->port
.handle_break
= kt_handle_break
;
1729 return skip_tx_en_setup(priv
, board
, port
, idx
);
1732 static int pci_eg20t_init(struct pci_dev
*dev
)
1734 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1741 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
1742 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
1745 pci_xr17c154_setup(struct serial_private
*priv
,
1746 const struct pciserial_board
*board
,
1747 struct uart_8250_port
*port
, int idx
)
1749 port
->port
.flags
|= UPF_EXAR_EFR
;
1750 return pci_default_setup(priv
, board
, port
, idx
);
1754 xr17v35x_has_slave(struct serial_private
*priv
)
1756 const int dev_id
= priv
->dev
->device
;
1758 return ((dev_id
== PCI_DEVICE_ID_EXAR_XR17V4358
) ||
1759 (dev_id
== PCI_DEVICE_ID_EXAR_XR17V8358
));
1763 pci_xr17v35x_setup(struct serial_private
*priv
,
1764 const struct pciserial_board
*board
,
1765 struct uart_8250_port
*port
, int idx
)
1769 p
= pci_ioremap_bar(priv
->dev
, 0);
1773 port
->port
.flags
|= UPF_EXAR_EFR
;
1776 * Setup the uart clock for the devices on expansion slot to
1777 * half the clock speed of the main chip (which is 125MHz)
1779 if (xr17v35x_has_slave(priv
) && idx
>= 8)
1780 port
->port
.uartclk
= (7812500 * 16 / 2);
1783 * Setup Multipurpose Input/Output pins.
1786 writeb(0x00, p
+ 0x8f); /*MPIOINT[7:0]*/
1787 writeb(0x00, p
+ 0x90); /*MPIOLVL[7:0]*/
1788 writeb(0x00, p
+ 0x91); /*MPIO3T[7:0]*/
1789 writeb(0x00, p
+ 0x92); /*MPIOINV[7:0]*/
1790 writeb(0x00, p
+ 0x93); /*MPIOSEL[7:0]*/
1791 writeb(0x00, p
+ 0x94); /*MPIOOD[7:0]*/
1792 writeb(0x00, p
+ 0x95); /*MPIOINT[15:8]*/
1793 writeb(0x00, p
+ 0x96); /*MPIOLVL[15:8]*/
1794 writeb(0x00, p
+ 0x97); /*MPIO3T[15:8]*/
1795 writeb(0x00, p
+ 0x98); /*MPIOINV[15:8]*/
1796 writeb(0x00, p
+ 0x99); /*MPIOSEL[15:8]*/
1797 writeb(0x00, p
+ 0x9a); /*MPIOOD[15:8]*/
1799 writeb(0x00, p
+ UART_EXAR_8XMODE
);
1800 writeb(UART_FCTR_EXAR_TRGD
, p
+ UART_EXAR_FCTR
);
1801 writeb(128, p
+ UART_EXAR_TXTRG
);
1802 writeb(128, p
+ UART_EXAR_RXTRG
);
1805 return pci_default_setup(priv
, board
, port
, idx
);
1808 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1809 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1810 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1811 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1814 pci_fastcom335_setup(struct serial_private
*priv
,
1815 const struct pciserial_board
*board
,
1816 struct uart_8250_port
*port
, int idx
)
1820 p
= pci_ioremap_bar(priv
->dev
, 0);
1824 port
->port
.flags
|= UPF_EXAR_EFR
;
1827 * Setup Multipurpose Input/Output pins.
1830 switch (priv
->dev
->device
) {
1831 case PCI_DEVICE_ID_COMMTECH_4222PCI335
:
1832 case PCI_DEVICE_ID_COMMTECH_4224PCI335
:
1833 writeb(0x78, p
+ 0x90); /* MPIOLVL[7:0] */
1834 writeb(0x00, p
+ 0x92); /* MPIOINV[7:0] */
1835 writeb(0x00, p
+ 0x93); /* MPIOSEL[7:0] */
1837 case PCI_DEVICE_ID_COMMTECH_2324PCI335
:
1838 case PCI_DEVICE_ID_COMMTECH_2328PCI335
:
1839 writeb(0x00, p
+ 0x90); /* MPIOLVL[7:0] */
1840 writeb(0xc0, p
+ 0x92); /* MPIOINV[7:0] */
1841 writeb(0xc0, p
+ 0x93); /* MPIOSEL[7:0] */
1844 writeb(0x00, p
+ 0x8f); /* MPIOINT[7:0] */
1845 writeb(0x00, p
+ 0x91); /* MPIO3T[7:0] */
1846 writeb(0x00, p
+ 0x94); /* MPIOOD[7:0] */
1848 writeb(0x00, p
+ UART_EXAR_8XMODE
);
1849 writeb(UART_FCTR_EXAR_TRGD
, p
+ UART_EXAR_FCTR
);
1850 writeb(32, p
+ UART_EXAR_TXTRG
);
1851 writeb(32, p
+ UART_EXAR_RXTRG
);
1854 return pci_default_setup(priv
, board
, port
, idx
);
1858 pci_wch_ch353_setup(struct serial_private
*priv
,
1859 const struct pciserial_board
*board
,
1860 struct uart_8250_port
*port
, int idx
)
1862 port
->port
.flags
|= UPF_FIXED_TYPE
;
1863 port
->port
.type
= PORT_16550A
;
1864 return pci_default_setup(priv
, board
, port
, idx
);
1868 pci_wch_ch355_setup(struct serial_private
*priv
,
1869 const struct pciserial_board
*board
,
1870 struct uart_8250_port
*port
, int idx
)
1872 port
->port
.flags
|= UPF_FIXED_TYPE
;
1873 port
->port
.type
= PORT_16550A
;
1874 return pci_default_setup(priv
, board
, port
, idx
);
1878 pci_wch_ch38x_setup(struct serial_private
*priv
,
1879 const struct pciserial_board
*board
,
1880 struct uart_8250_port
*port
, int idx
)
1882 port
->port
.flags
|= UPF_FIXED_TYPE
;
1883 port
->port
.type
= PORT_16850
;
1884 return pci_default_setup(priv
, board
, port
, idx
);
1887 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1888 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1889 #define PCI_DEVICE_ID_OCTPRO 0x0001
1890 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1891 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1892 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1893 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1894 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1895 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1896 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1897 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1898 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1899 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1900 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1901 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1902 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1903 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1904 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1905 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1906 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1907 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1908 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1909 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1910 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1911 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1912 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1913 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1914 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1915 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1916 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1917 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1918 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1919 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1920 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1921 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1922 #define PCI_VENDOR_ID_WCH 0x4348
1923 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1924 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1925 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1926 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1927 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1928 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
1929 #define PCI_VENDOR_ID_AGESTAR 0x5372
1930 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1931 #define PCI_VENDOR_ID_ASIX 0x9710
1932 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1933 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1934 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1935 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1936 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1937 #define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936
1939 #define PCI_VENDOR_ID_SUNIX 0x1fd4
1940 #define PCI_DEVICE_ID_SUNIX_1999 0x1999
1942 #define PCIE_VENDOR_ID_WCH 0x1c00
1943 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1944 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1945 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1947 #define PCI_VENDOR_ID_PERICOM 0x12D8
1948 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951
1949 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952
1950 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954
1951 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958
1953 #define PCI_VENDOR_ID_ACCESIO 0x494f
1954 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051
1955 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053
1956 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C
1957 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E
1958 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091
1959 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093
1960 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099
1961 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B
1962 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1
1963 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3
1964 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA
1965 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC
1966 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108
1967 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110
1968 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111
1969 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118
1970 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119
1971 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152
1972 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A
1973 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190
1974 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191
1975 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198
1976 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199
1977 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0
1978 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A
1979 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B
1980 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A
1981 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B
1982 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098
1983 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9
1984 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9
1985 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9
1986 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8
1990 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1991 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1992 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1995 * Master list of serial port init/setup/exit quirks.
1996 * This does not describe the general nature of the port.
1997 * (ie, baud base, number and location of ports, etc)
1999 * This list is ordered alphabetically by vendor then device.
2000 * Specific entries must come before more generic entries.
2002 static struct pci_serial_quirk pci_serial_quirks
[] __refdata
= {
2004 * ADDI-DATA GmbH communication cards <info@addi-data.com>
2007 .vendor
= PCI_VENDOR_ID_AMCC
,
2008 .device
= PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800
,
2009 .subvendor
= PCI_ANY_ID
,
2010 .subdevice
= PCI_ANY_ID
,
2011 .setup
= addidata_apci7800_setup
,
2014 * AFAVLAB cards - these may be called via parport_serial
2015 * It is not clear whether this applies to all products.
2018 .vendor
= PCI_VENDOR_ID_AFAVLAB
,
2019 .device
= PCI_ANY_ID
,
2020 .subvendor
= PCI_ANY_ID
,
2021 .subdevice
= PCI_ANY_ID
,
2022 .setup
= afavlab_setup
,
2028 .vendor
= PCI_VENDOR_ID_HP
,
2029 .device
= PCI_DEVICE_ID_HP_DIVA
,
2030 .subvendor
= PCI_ANY_ID
,
2031 .subdevice
= PCI_ANY_ID
,
2032 .init
= pci_hp_diva_init
,
2033 .setup
= pci_hp_diva_setup
,
2039 .vendor
= PCI_VENDOR_ID_INTEL
,
2040 .device
= PCI_DEVICE_ID_INTEL_80960_RP
,
2041 .subvendor
= 0xe4bf,
2042 .subdevice
= PCI_ANY_ID
,
2043 .init
= pci_inteli960ni_init
,
2044 .setup
= pci_default_setup
,
2047 .vendor
= PCI_VENDOR_ID_INTEL
,
2048 .device
= PCI_DEVICE_ID_INTEL_8257X_SOL
,
2049 .subvendor
= PCI_ANY_ID
,
2050 .subdevice
= PCI_ANY_ID
,
2051 .setup
= skip_tx_en_setup
,
2054 .vendor
= PCI_VENDOR_ID_INTEL
,
2055 .device
= PCI_DEVICE_ID_INTEL_82573L_SOL
,
2056 .subvendor
= PCI_ANY_ID
,
2057 .subdevice
= PCI_ANY_ID
,
2058 .setup
= skip_tx_en_setup
,
2061 .vendor
= PCI_VENDOR_ID_INTEL
,
2062 .device
= PCI_DEVICE_ID_INTEL_82573E_SOL
,
2063 .subvendor
= PCI_ANY_ID
,
2064 .subdevice
= PCI_ANY_ID
,
2065 .setup
= skip_tx_en_setup
,
2068 .vendor
= PCI_VENDOR_ID_INTEL
,
2069 .device
= PCI_DEVICE_ID_INTEL_CE4100_UART
,
2070 .subvendor
= PCI_ANY_ID
,
2071 .subdevice
= PCI_ANY_ID
,
2072 .setup
= ce4100_serial_setup
,
2075 .vendor
= PCI_VENDOR_ID_INTEL
,
2076 .device
= PCI_DEVICE_ID_INTEL_PATSBURG_KT
,
2077 .subvendor
= PCI_ANY_ID
,
2078 .subdevice
= PCI_ANY_ID
,
2079 .setup
= kt_serial_setup
,
2082 .vendor
= PCI_VENDOR_ID_INTEL
,
2083 .device
= PCI_DEVICE_ID_INTEL_BYT_UART1
,
2084 .subvendor
= PCI_ANY_ID
,
2085 .subdevice
= PCI_ANY_ID
,
2086 .setup
= byt_serial_setup
,
2089 .vendor
= PCI_VENDOR_ID_INTEL
,
2090 .device
= PCI_DEVICE_ID_INTEL_BYT_UART2
,
2091 .subvendor
= PCI_ANY_ID
,
2092 .subdevice
= PCI_ANY_ID
,
2093 .setup
= byt_serial_setup
,
2096 .vendor
= PCI_VENDOR_ID_INTEL
,
2097 .device
= PCI_DEVICE_ID_INTEL_BSW_UART1
,
2098 .subvendor
= PCI_ANY_ID
,
2099 .subdevice
= PCI_ANY_ID
,
2100 .setup
= byt_serial_setup
,
2103 .vendor
= PCI_VENDOR_ID_INTEL
,
2104 .device
= PCI_DEVICE_ID_INTEL_BSW_UART2
,
2105 .subvendor
= PCI_ANY_ID
,
2106 .subdevice
= PCI_ANY_ID
,
2107 .setup
= byt_serial_setup
,
2110 .vendor
= PCI_VENDOR_ID_INTEL
,
2111 .device
= PCI_DEVICE_ID_INTEL_BDW_UART1
,
2112 .subvendor
= PCI_ANY_ID
,
2113 .subdevice
= PCI_ANY_ID
,
2114 .setup
= byt_serial_setup
,
2117 .vendor
= PCI_VENDOR_ID_INTEL
,
2118 .device
= PCI_DEVICE_ID_INTEL_BDW_UART2
,
2119 .subvendor
= PCI_ANY_ID
,
2120 .subdevice
= PCI_ANY_ID
,
2121 .setup
= byt_serial_setup
,
2127 .vendor
= PCI_VENDOR_ID_ITE
,
2128 .device
= PCI_DEVICE_ID_ITE_8872
,
2129 .subvendor
= PCI_ANY_ID
,
2130 .subdevice
= PCI_ANY_ID
,
2131 .init
= pci_ite887x_init
,
2132 .setup
= pci_default_setup
,
2133 .exit
= pci_ite887x_exit
,
2136 * National Instruments
2139 .vendor
= PCI_VENDOR_ID_NI
,
2140 .device
= PCI_DEVICE_ID_NI_PCI23216
,
2141 .subvendor
= PCI_ANY_ID
,
2142 .subdevice
= PCI_ANY_ID
,
2143 .init
= pci_ni8420_init
,
2144 .setup
= pci_default_setup
,
2145 .exit
= pci_ni8420_exit
,
2148 .vendor
= PCI_VENDOR_ID_NI
,
2149 .device
= PCI_DEVICE_ID_NI_PCI2328
,
2150 .subvendor
= PCI_ANY_ID
,
2151 .subdevice
= PCI_ANY_ID
,
2152 .init
= pci_ni8420_init
,
2153 .setup
= pci_default_setup
,
2154 .exit
= pci_ni8420_exit
,
2157 .vendor
= PCI_VENDOR_ID_NI
,
2158 .device
= PCI_DEVICE_ID_NI_PCI2324
,
2159 .subvendor
= PCI_ANY_ID
,
2160 .subdevice
= PCI_ANY_ID
,
2161 .init
= pci_ni8420_init
,
2162 .setup
= pci_default_setup
,
2163 .exit
= pci_ni8420_exit
,
2166 .vendor
= PCI_VENDOR_ID_NI
,
2167 .device
= PCI_DEVICE_ID_NI_PCI2322
,
2168 .subvendor
= PCI_ANY_ID
,
2169 .subdevice
= PCI_ANY_ID
,
2170 .init
= pci_ni8420_init
,
2171 .setup
= pci_default_setup
,
2172 .exit
= pci_ni8420_exit
,
2175 .vendor
= PCI_VENDOR_ID_NI
,
2176 .device
= PCI_DEVICE_ID_NI_PCI2324I
,
2177 .subvendor
= PCI_ANY_ID
,
2178 .subdevice
= PCI_ANY_ID
,
2179 .init
= pci_ni8420_init
,
2180 .setup
= pci_default_setup
,
2181 .exit
= pci_ni8420_exit
,
2184 .vendor
= PCI_VENDOR_ID_NI
,
2185 .device
= PCI_DEVICE_ID_NI_PCI2322I
,
2186 .subvendor
= PCI_ANY_ID
,
2187 .subdevice
= PCI_ANY_ID
,
2188 .init
= pci_ni8420_init
,
2189 .setup
= pci_default_setup
,
2190 .exit
= pci_ni8420_exit
,
2193 .vendor
= PCI_VENDOR_ID_NI
,
2194 .device
= PCI_DEVICE_ID_NI_PXI8420_23216
,
2195 .subvendor
= PCI_ANY_ID
,
2196 .subdevice
= PCI_ANY_ID
,
2197 .init
= pci_ni8420_init
,
2198 .setup
= pci_default_setup
,
2199 .exit
= pci_ni8420_exit
,
2202 .vendor
= PCI_VENDOR_ID_NI
,
2203 .device
= PCI_DEVICE_ID_NI_PXI8420_2328
,
2204 .subvendor
= PCI_ANY_ID
,
2205 .subdevice
= PCI_ANY_ID
,
2206 .init
= pci_ni8420_init
,
2207 .setup
= pci_default_setup
,
2208 .exit
= pci_ni8420_exit
,
2211 .vendor
= PCI_VENDOR_ID_NI
,
2212 .device
= PCI_DEVICE_ID_NI_PXI8420_2324
,
2213 .subvendor
= PCI_ANY_ID
,
2214 .subdevice
= PCI_ANY_ID
,
2215 .init
= pci_ni8420_init
,
2216 .setup
= pci_default_setup
,
2217 .exit
= pci_ni8420_exit
,
2220 .vendor
= PCI_VENDOR_ID_NI
,
2221 .device
= PCI_DEVICE_ID_NI_PXI8420_2322
,
2222 .subvendor
= PCI_ANY_ID
,
2223 .subdevice
= PCI_ANY_ID
,
2224 .init
= pci_ni8420_init
,
2225 .setup
= pci_default_setup
,
2226 .exit
= pci_ni8420_exit
,
2229 .vendor
= PCI_VENDOR_ID_NI
,
2230 .device
= PCI_DEVICE_ID_NI_PXI8422_2324
,
2231 .subvendor
= PCI_ANY_ID
,
2232 .subdevice
= PCI_ANY_ID
,
2233 .init
= pci_ni8420_init
,
2234 .setup
= pci_default_setup
,
2235 .exit
= pci_ni8420_exit
,
2238 .vendor
= PCI_VENDOR_ID_NI
,
2239 .device
= PCI_DEVICE_ID_NI_PXI8422_2322
,
2240 .subvendor
= PCI_ANY_ID
,
2241 .subdevice
= PCI_ANY_ID
,
2242 .init
= pci_ni8420_init
,
2243 .setup
= pci_default_setup
,
2244 .exit
= pci_ni8420_exit
,
2247 .vendor
= PCI_VENDOR_ID_NI
,
2248 .device
= PCI_ANY_ID
,
2249 .subvendor
= PCI_ANY_ID
,
2250 .subdevice
= PCI_ANY_ID
,
2251 .init
= pci_ni8430_init
,
2252 .setup
= pci_ni8430_setup
,
2253 .exit
= pci_ni8430_exit
,
2257 .vendor
= PCI_VENDOR_ID_QUATECH
,
2258 .device
= PCI_ANY_ID
,
2259 .subvendor
= PCI_ANY_ID
,
2260 .subdevice
= PCI_ANY_ID
,
2261 .init
= pci_quatech_init
,
2262 .setup
= pci_quatech_setup
,
2263 .exit
= pci_quatech_exit
,
2269 .vendor
= PCI_VENDOR_ID_PANACOM
,
2270 .device
= PCI_DEVICE_ID_PANACOM_QUADMODEM
,
2271 .subvendor
= PCI_ANY_ID
,
2272 .subdevice
= PCI_ANY_ID
,
2273 .init
= pci_plx9050_init
,
2274 .setup
= pci_default_setup
,
2275 .exit
= pci_plx9050_exit
,
2278 .vendor
= PCI_VENDOR_ID_PANACOM
,
2279 .device
= PCI_DEVICE_ID_PANACOM_DUALMODEM
,
2280 .subvendor
= PCI_ANY_ID
,
2281 .subdevice
= PCI_ANY_ID
,
2282 .init
= pci_plx9050_init
,
2283 .setup
= pci_default_setup
,
2284 .exit
= pci_plx9050_exit
,
2290 .vendor
= PCI_VENDOR_ID_PLX
,
2291 .device
= PCI_DEVICE_ID_PLX_9050
,
2292 .subvendor
= PCI_SUBVENDOR_ID_EXSYS
,
2293 .subdevice
= PCI_SUBDEVICE_ID_EXSYS_4055
,
2294 .init
= pci_plx9050_init
,
2295 .setup
= pci_default_setup
,
2296 .exit
= pci_plx9050_exit
,
2299 .vendor
= PCI_VENDOR_ID_PLX
,
2300 .device
= PCI_DEVICE_ID_PLX_9050
,
2301 .subvendor
= PCI_SUBVENDOR_ID_KEYSPAN
,
2302 .subdevice
= PCI_SUBDEVICE_ID_KEYSPAN_SX2
,
2303 .init
= pci_plx9050_init
,
2304 .setup
= pci_default_setup
,
2305 .exit
= pci_plx9050_exit
,
2308 .vendor
= PCI_VENDOR_ID_PLX
,
2309 .device
= PCI_DEVICE_ID_PLX_ROMULUS
,
2310 .subvendor
= PCI_VENDOR_ID_PLX
,
2311 .subdevice
= PCI_DEVICE_ID_PLX_ROMULUS
,
2312 .init
= pci_plx9050_init
,
2313 .setup
= pci_default_setup
,
2314 .exit
= pci_plx9050_exit
,
2317 * SBS Technologies, Inc., PMC-OCTALPRO 232
2320 .vendor
= PCI_VENDOR_ID_SBSMODULARIO
,
2321 .device
= PCI_DEVICE_ID_OCTPRO
,
2322 .subvendor
= PCI_SUBVENDOR_ID_SBSMODULARIO
,
2323 .subdevice
= PCI_SUBDEVICE_ID_OCTPRO232
,
2329 * SBS Technologies, Inc., PMC-OCTALPRO 422
2332 .vendor
= PCI_VENDOR_ID_SBSMODULARIO
,
2333 .device
= PCI_DEVICE_ID_OCTPRO
,
2334 .subvendor
= PCI_SUBVENDOR_ID_SBSMODULARIO
,
2335 .subdevice
= PCI_SUBDEVICE_ID_OCTPRO422
,
2341 * SBS Technologies, Inc., P-Octal 232
2344 .vendor
= PCI_VENDOR_ID_SBSMODULARIO
,
2345 .device
= PCI_DEVICE_ID_OCTPRO
,
2346 .subvendor
= PCI_SUBVENDOR_ID_SBSMODULARIO
,
2347 .subdevice
= PCI_SUBDEVICE_ID_POCTAL232
,
2353 * SBS Technologies, Inc., P-Octal 422
2356 .vendor
= PCI_VENDOR_ID_SBSMODULARIO
,
2357 .device
= PCI_DEVICE_ID_OCTPRO
,
2358 .subvendor
= PCI_SUBVENDOR_ID_SBSMODULARIO
,
2359 .subdevice
= PCI_SUBDEVICE_ID_POCTAL422
,
2365 * SIIG cards - these may be called via parport_serial
2368 .vendor
= PCI_VENDOR_ID_SIIG
,
2369 .device
= PCI_ANY_ID
,
2370 .subvendor
= PCI_ANY_ID
,
2371 .subdevice
= PCI_ANY_ID
,
2372 .init
= pci_siig_init
,
2373 .setup
= pci_siig_setup
,
2379 .vendor
= PCI_VENDOR_ID_TITAN
,
2380 .device
= PCI_DEVICE_ID_TITAN_400L
,
2381 .subvendor
= PCI_ANY_ID
,
2382 .subdevice
= PCI_ANY_ID
,
2383 .setup
= titan_400l_800l_setup
,
2386 .vendor
= PCI_VENDOR_ID_TITAN
,
2387 .device
= PCI_DEVICE_ID_TITAN_800L
,
2388 .subvendor
= PCI_ANY_ID
,
2389 .subdevice
= PCI_ANY_ID
,
2390 .setup
= titan_400l_800l_setup
,
2396 .vendor
= PCI_VENDOR_ID_TIMEDIA
,
2397 .device
= PCI_DEVICE_ID_TIMEDIA_1889
,
2398 .subvendor
= PCI_VENDOR_ID_TIMEDIA
,
2399 .subdevice
= PCI_ANY_ID
,
2400 .probe
= pci_timedia_probe
,
2401 .init
= pci_timedia_init
,
2402 .setup
= pci_timedia_setup
,
2405 .vendor
= PCI_VENDOR_ID_TIMEDIA
,
2406 .device
= PCI_ANY_ID
,
2407 .subvendor
= PCI_ANY_ID
,
2408 .subdevice
= PCI_ANY_ID
,
2409 .setup
= pci_timedia_setup
,
2412 * SUNIX (Timedia) cards
2413 * Do not "probe" for these cards as there is at least one combination
2414 * card that should be handled by parport_pc that doesn't match the
2415 * rule in pci_timedia_probe.
2416 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2417 * There are some boards with part number SER5037AL that report
2418 * subdevice ID 0x0002.
2421 .vendor
= PCI_VENDOR_ID_SUNIX
,
2422 .device
= PCI_DEVICE_ID_SUNIX_1999
,
2423 .subvendor
= PCI_VENDOR_ID_SUNIX
,
2424 .subdevice
= PCI_ANY_ID
,
2425 .init
= pci_timedia_init
,
2426 .setup
= pci_timedia_setup
,
2432 .vendor
= PCI_VENDOR_ID_EXAR
,
2433 .device
= PCI_DEVICE_ID_EXAR_XR17C152
,
2434 .subvendor
= PCI_ANY_ID
,
2435 .subdevice
= PCI_ANY_ID
,
2436 .setup
= pci_xr17c154_setup
,
2439 .vendor
= PCI_VENDOR_ID_EXAR
,
2440 .device
= PCI_DEVICE_ID_EXAR_XR17C154
,
2441 .subvendor
= PCI_ANY_ID
,
2442 .subdevice
= PCI_ANY_ID
,
2443 .setup
= pci_xr17c154_setup
,
2446 .vendor
= PCI_VENDOR_ID_EXAR
,
2447 .device
= PCI_DEVICE_ID_EXAR_XR17C158
,
2448 .subvendor
= PCI_ANY_ID
,
2449 .subdevice
= PCI_ANY_ID
,
2450 .setup
= pci_xr17c154_setup
,
2453 .vendor
= PCI_VENDOR_ID_EXAR
,
2454 .device
= PCI_DEVICE_ID_EXAR_XR17V352
,
2455 .subvendor
= PCI_ANY_ID
,
2456 .subdevice
= PCI_ANY_ID
,
2457 .setup
= pci_xr17v35x_setup
,
2460 .vendor
= PCI_VENDOR_ID_EXAR
,
2461 .device
= PCI_DEVICE_ID_EXAR_XR17V354
,
2462 .subvendor
= PCI_ANY_ID
,
2463 .subdevice
= PCI_ANY_ID
,
2464 .setup
= pci_xr17v35x_setup
,
2467 .vendor
= PCI_VENDOR_ID_EXAR
,
2468 .device
= PCI_DEVICE_ID_EXAR_XR17V358
,
2469 .subvendor
= PCI_ANY_ID
,
2470 .subdevice
= PCI_ANY_ID
,
2471 .setup
= pci_xr17v35x_setup
,
2474 .vendor
= PCI_VENDOR_ID_EXAR
,
2475 .device
= PCI_DEVICE_ID_EXAR_XR17V4358
,
2476 .subvendor
= PCI_ANY_ID
,
2477 .subdevice
= PCI_ANY_ID
,
2478 .setup
= pci_xr17v35x_setup
,
2481 .vendor
= PCI_VENDOR_ID_EXAR
,
2482 .device
= PCI_DEVICE_ID_EXAR_XR17V8358
,
2483 .subvendor
= PCI_ANY_ID
,
2484 .subdevice
= PCI_ANY_ID
,
2485 .setup
= pci_xr17v35x_setup
,
2491 .vendor
= PCI_VENDOR_ID_XIRCOM
,
2492 .device
= PCI_DEVICE_ID_XIRCOM_X3201_MDM
,
2493 .subvendor
= PCI_ANY_ID
,
2494 .subdevice
= PCI_ANY_ID
,
2495 .init
= pci_xircom_init
,
2496 .setup
= pci_default_setup
,
2499 * Netmos cards - these may be called via parport_serial
2502 .vendor
= PCI_VENDOR_ID_NETMOS
,
2503 .device
= PCI_ANY_ID
,
2504 .subvendor
= PCI_ANY_ID
,
2505 .subdevice
= PCI_ANY_ID
,
2506 .init
= pci_netmos_init
,
2507 .setup
= pci_netmos_9900_setup
,
2510 * EndRun Technologies
2513 .vendor
= PCI_VENDOR_ID_ENDRUN
,
2514 .device
= PCI_ANY_ID
,
2515 .subvendor
= PCI_ANY_ID
,
2516 .subdevice
= PCI_ANY_ID
,
2517 .init
= pci_endrun_init
,
2518 .setup
= pci_default_setup
,
2521 * For Oxford Semiconductor Tornado based devices
2524 .vendor
= PCI_VENDOR_ID_OXSEMI
,
2525 .device
= PCI_ANY_ID
,
2526 .subvendor
= PCI_ANY_ID
,
2527 .subdevice
= PCI_ANY_ID
,
2528 .init
= pci_oxsemi_tornado_init
,
2529 .setup
= pci_default_setup
,
2532 .vendor
= PCI_VENDOR_ID_MAINPINE
,
2533 .device
= PCI_ANY_ID
,
2534 .subvendor
= PCI_ANY_ID
,
2535 .subdevice
= PCI_ANY_ID
,
2536 .init
= pci_oxsemi_tornado_init
,
2537 .setup
= pci_default_setup
,
2540 .vendor
= PCI_VENDOR_ID_DIGI
,
2541 .device
= PCIE_DEVICE_ID_NEO_2_OX_IBM
,
2542 .subvendor
= PCI_SUBVENDOR_ID_IBM
,
2543 .subdevice
= PCI_ANY_ID
,
2544 .init
= pci_oxsemi_tornado_init
,
2545 .setup
= pci_default_setup
,
2548 .vendor
= PCI_VENDOR_ID_INTEL
,
2550 .subvendor
= PCI_ANY_ID
,
2551 .subdevice
= PCI_ANY_ID
,
2552 .init
= pci_eg20t_init
,
2553 .setup
= pci_default_setup
,
2556 .vendor
= PCI_VENDOR_ID_INTEL
,
2558 .subvendor
= PCI_ANY_ID
,
2559 .subdevice
= PCI_ANY_ID
,
2560 .init
= pci_eg20t_init
,
2561 .setup
= pci_default_setup
,
2564 .vendor
= PCI_VENDOR_ID_INTEL
,
2566 .subvendor
= PCI_ANY_ID
,
2567 .subdevice
= PCI_ANY_ID
,
2568 .init
= pci_eg20t_init
,
2569 .setup
= pci_default_setup
,
2572 .vendor
= PCI_VENDOR_ID_INTEL
,
2574 .subvendor
= PCI_ANY_ID
,
2575 .subdevice
= PCI_ANY_ID
,
2576 .init
= pci_eg20t_init
,
2577 .setup
= pci_default_setup
,
2582 .subvendor
= PCI_ANY_ID
,
2583 .subdevice
= PCI_ANY_ID
,
2584 .init
= pci_eg20t_init
,
2585 .setup
= pci_default_setup
,
2590 .subvendor
= PCI_ANY_ID
,
2591 .subdevice
= PCI_ANY_ID
,
2592 .init
= pci_eg20t_init
,
2593 .setup
= pci_default_setup
,
2598 .subvendor
= PCI_ANY_ID
,
2599 .subdevice
= PCI_ANY_ID
,
2600 .init
= pci_eg20t_init
,
2601 .setup
= pci_default_setup
,
2606 .subvendor
= PCI_ANY_ID
,
2607 .subdevice
= PCI_ANY_ID
,
2608 .init
= pci_eg20t_init
,
2609 .setup
= pci_default_setup
,
2614 .subvendor
= PCI_ANY_ID
,
2615 .subdevice
= PCI_ANY_ID
,
2616 .init
= pci_eg20t_init
,
2617 .setup
= pci_default_setup
,
2620 * Cronyx Omega PCI (PLX-chip based)
2623 .vendor
= PCI_VENDOR_ID_PLX
,
2624 .device
= PCI_DEVICE_ID_PLX_CRONYX_OMEGA
,
2625 .subvendor
= PCI_ANY_ID
,
2626 .subdevice
= PCI_ANY_ID
,
2627 .setup
= pci_omegapci_setup
,
2629 /* WCH CH353 1S1P card (16550 clone) */
2631 .vendor
= PCI_VENDOR_ID_WCH
,
2632 .device
= PCI_DEVICE_ID_WCH_CH353_1S1P
,
2633 .subvendor
= PCI_ANY_ID
,
2634 .subdevice
= PCI_ANY_ID
,
2635 .setup
= pci_wch_ch353_setup
,
2637 /* WCH CH353 2S1P card (16550 clone) */
2639 .vendor
= PCI_VENDOR_ID_WCH
,
2640 .device
= PCI_DEVICE_ID_WCH_CH353_2S1P
,
2641 .subvendor
= PCI_ANY_ID
,
2642 .subdevice
= PCI_ANY_ID
,
2643 .setup
= pci_wch_ch353_setup
,
2645 /* WCH CH353 4S card (16550 clone) */
2647 .vendor
= PCI_VENDOR_ID_WCH
,
2648 .device
= PCI_DEVICE_ID_WCH_CH353_4S
,
2649 .subvendor
= PCI_ANY_ID
,
2650 .subdevice
= PCI_ANY_ID
,
2651 .setup
= pci_wch_ch353_setup
,
2653 /* WCH CH353 2S1PF card (16550 clone) */
2655 .vendor
= PCI_VENDOR_ID_WCH
,
2656 .device
= PCI_DEVICE_ID_WCH_CH353_2S1PF
,
2657 .subvendor
= PCI_ANY_ID
,
2658 .subdevice
= PCI_ANY_ID
,
2659 .setup
= pci_wch_ch353_setup
,
2661 /* WCH CH352 2S card (16550 clone) */
2663 .vendor
= PCI_VENDOR_ID_WCH
,
2664 .device
= PCI_DEVICE_ID_WCH_CH352_2S
,
2665 .subvendor
= PCI_ANY_ID
,
2666 .subdevice
= PCI_ANY_ID
,
2667 .setup
= pci_wch_ch353_setup
,
2669 /* WCH CH355 4S card (16550 clone) */
2671 .vendor
= PCI_VENDOR_ID_WCH
,
2672 .device
= PCI_DEVICE_ID_WCH_CH355_4S
,
2673 .subvendor
= PCI_ANY_ID
,
2674 .subdevice
= PCI_ANY_ID
,
2675 .setup
= pci_wch_ch355_setup
,
2677 /* WCH CH382 2S card (16850 clone) */
2679 .vendor
= PCIE_VENDOR_ID_WCH
,
2680 .device
= PCIE_DEVICE_ID_WCH_CH382_2S
,
2681 .subvendor
= PCI_ANY_ID
,
2682 .subdevice
= PCI_ANY_ID
,
2683 .setup
= pci_wch_ch38x_setup
,
2685 /* WCH CH382 2S1P card (16850 clone) */
2687 .vendor
= PCIE_VENDOR_ID_WCH
,
2688 .device
= PCIE_DEVICE_ID_WCH_CH382_2S1P
,
2689 .subvendor
= PCI_ANY_ID
,
2690 .subdevice
= PCI_ANY_ID
,
2691 .setup
= pci_wch_ch38x_setup
,
2693 /* WCH CH384 4S card (16850 clone) */
2695 .vendor
= PCIE_VENDOR_ID_WCH
,
2696 .device
= PCIE_DEVICE_ID_WCH_CH384_4S
,
2697 .subvendor
= PCI_ANY_ID
,
2698 .subdevice
= PCI_ANY_ID
,
2699 .setup
= pci_wch_ch38x_setup
,
2702 * ASIX devices with FIFO bug
2705 .vendor
= PCI_VENDOR_ID_ASIX
,
2706 .device
= PCI_ANY_ID
,
2707 .subvendor
= PCI_ANY_ID
,
2708 .subdevice
= PCI_ANY_ID
,
2709 .setup
= pci_asix_setup
,
2712 * Commtech, Inc. Fastcom adapters
2716 .vendor
= PCI_VENDOR_ID_COMMTECH
,
2717 .device
= PCI_DEVICE_ID_COMMTECH_4222PCI335
,
2718 .subvendor
= PCI_ANY_ID
,
2719 .subdevice
= PCI_ANY_ID
,
2720 .setup
= pci_fastcom335_setup
,
2723 .vendor
= PCI_VENDOR_ID_COMMTECH
,
2724 .device
= PCI_DEVICE_ID_COMMTECH_4224PCI335
,
2725 .subvendor
= PCI_ANY_ID
,
2726 .subdevice
= PCI_ANY_ID
,
2727 .setup
= pci_fastcom335_setup
,
2730 .vendor
= PCI_VENDOR_ID_COMMTECH
,
2731 .device
= PCI_DEVICE_ID_COMMTECH_2324PCI335
,
2732 .subvendor
= PCI_ANY_ID
,
2733 .subdevice
= PCI_ANY_ID
,
2734 .setup
= pci_fastcom335_setup
,
2737 .vendor
= PCI_VENDOR_ID_COMMTECH
,
2738 .device
= PCI_DEVICE_ID_COMMTECH_2328PCI335
,
2739 .subvendor
= PCI_ANY_ID
,
2740 .subdevice
= PCI_ANY_ID
,
2741 .setup
= pci_fastcom335_setup
,
2744 .vendor
= PCI_VENDOR_ID_COMMTECH
,
2745 .device
= PCI_DEVICE_ID_COMMTECH_4222PCIE
,
2746 .subvendor
= PCI_ANY_ID
,
2747 .subdevice
= PCI_ANY_ID
,
2748 .setup
= pci_xr17v35x_setup
,
2751 .vendor
= PCI_VENDOR_ID_COMMTECH
,
2752 .device
= PCI_DEVICE_ID_COMMTECH_4224PCIE
,
2753 .subvendor
= PCI_ANY_ID
,
2754 .subdevice
= PCI_ANY_ID
,
2755 .setup
= pci_xr17v35x_setup
,
2758 .vendor
= PCI_VENDOR_ID_COMMTECH
,
2759 .device
= PCI_DEVICE_ID_COMMTECH_4228PCIE
,
2760 .subvendor
= PCI_ANY_ID
,
2761 .subdevice
= PCI_ANY_ID
,
2762 .setup
= pci_xr17v35x_setup
,
2765 * Broadcom TruManage (NetXtreme)
2768 .vendor
= PCI_VENDOR_ID_BROADCOM
,
2769 .device
= PCI_DEVICE_ID_BROADCOM_TRUMANAGE
,
2770 .subvendor
= PCI_ANY_ID
,
2771 .subdevice
= PCI_ANY_ID
,
2772 .setup
= pci_brcm_trumanage_setup
,
2777 .subvendor
= PCI_ANY_ID
,
2778 .subdevice
= PCI_ANY_ID
,
2779 .setup
= pci_fintek_setup
,
2780 .init
= pci_fintek_init
,
2785 .subvendor
= PCI_ANY_ID
,
2786 .subdevice
= PCI_ANY_ID
,
2787 .setup
= pci_fintek_setup
,
2788 .init
= pci_fintek_init
,
2793 .subvendor
= PCI_ANY_ID
,
2794 .subdevice
= PCI_ANY_ID
,
2795 .setup
= pci_fintek_setup
,
2796 .init
= pci_fintek_init
,
2800 * Default "match everything" terminator entry
2803 .vendor
= PCI_ANY_ID
,
2804 .device
= PCI_ANY_ID
,
2805 .subvendor
= PCI_ANY_ID
,
2806 .subdevice
= PCI_ANY_ID
,
2807 .setup
= pci_default_setup
,
2811 static inline int quirk_id_matches(u32 quirk_id
, u32 dev_id
)
2813 return quirk_id
== PCI_ANY_ID
|| quirk_id
== dev_id
;
2816 static struct pci_serial_quirk
*find_quirk(struct pci_dev
*dev
)
2818 struct pci_serial_quirk
*quirk
;
2820 for (quirk
= pci_serial_quirks
; ; quirk
++)
2821 if (quirk_id_matches(quirk
->vendor
, dev
->vendor
) &&
2822 quirk_id_matches(quirk
->device
, dev
->device
) &&
2823 quirk_id_matches(quirk
->subvendor
, dev
->subsystem_vendor
) &&
2824 quirk_id_matches(quirk
->subdevice
, dev
->subsystem_device
))
2829 static inline int get_pci_irq(struct pci_dev
*dev
,
2830 const struct pciserial_board
*board
)
2832 if (board
->flags
& FL_NOIRQ
)
2839 * This is the configuration table for all of the PCI serial boards
2840 * which we support. It is directly indexed by the pci_board_num_t enum
2841 * value, which is encoded in the pci_device_id PCI probe table's
2842 * driver_data member.
2844 * The makeup of these names are:
2845 * pbn_bn{_bt}_n_baud{_offsetinhex}
2847 * bn = PCI BAR number
2848 * bt = Index using PCI BARs
2849 * n = number of serial ports
2851 * offsetinhex = offset for each sequential port (in hex)
2853 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2855 * Please note: in theory if n = 1, _bt infix should make no difference.
2856 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2858 enum pci_board_num_t
{
2875 pbn_b0_2_1152000_200
,
2876 pbn_b0_4_1152000_200
,
2877 pbn_b0_8_1152000_200
,
2882 pbn_b0_2_1843200_200
,
2883 pbn_b0_4_1843200_200
,
2884 pbn_b0_8_1843200_200
,
2958 * Board-specific versions.
2964 pbn_endrun_2_4000000
,
2966 pbn_oxsemi_1_4000000
,
2967 pbn_oxsemi_2_4000000
,
2968 pbn_oxsemi_4_4000000
,
2969 pbn_oxsemi_8_4000000
,
2984 pbn_exar_ibm_saturn
,
2990 pbn_ADDIDATA_PCIe_1_3906250
,
2991 pbn_ADDIDATA_PCIe_2_3906250
,
2992 pbn_ADDIDATA_PCIe_4_3906250
,
2993 pbn_ADDIDATA_PCIe_8_3906250
,
2994 pbn_ce4100_1_115200
,
2998 pbn_NETMOS9900_2s_115200
,
3005 pbn_pericom_PI7C9X7951
,
3006 pbn_pericom_PI7C9X7952
,
3007 pbn_pericom_PI7C9X7954
,
3008 pbn_pericom_PI7C9X7958
,
3012 * uart_offset - the space between channels
3013 * reg_shift - describes how the UART registers are mapped
3014 * to PCI memory by the card.
3015 * For example IER register on SBS, Inc. PMC-OctPro is located at
3016 * offset 0x10 from the UART base, while UART_IER is defined as 1
3017 * in include/linux/serial_reg.h,
3018 * see first lines of serial_in() and serial_out() in 8250.c
3021 static struct pciserial_board pci_boards
[] = {
3025 .base_baud
= 115200,
3028 [pbn_b0_1_115200
] = {
3031 .base_baud
= 115200,
3034 [pbn_b0_2_115200
] = {
3037 .base_baud
= 115200,
3040 [pbn_b0_4_115200
] = {
3043 .base_baud
= 115200,
3046 [pbn_b0_5_115200
] = {
3049 .base_baud
= 115200,
3052 [pbn_b0_8_115200
] = {
3055 .base_baud
= 115200,
3058 [pbn_b0_1_921600
] = {
3061 .base_baud
= 921600,
3064 [pbn_b0_2_921600
] = {
3067 .base_baud
= 921600,
3070 [pbn_b0_4_921600
] = {
3073 .base_baud
= 921600,
3077 [pbn_b0_2_1130000
] = {
3080 .base_baud
= 1130000,
3084 [pbn_b0_4_1152000
] = {
3087 .base_baud
= 1152000,
3091 [pbn_b0_2_1152000_200
] = {
3094 .base_baud
= 1152000,
3095 .uart_offset
= 0x200,
3098 [pbn_b0_4_1152000_200
] = {
3101 .base_baud
= 1152000,
3102 .uart_offset
= 0x200,
3105 [pbn_b0_8_1152000_200
] = {
3108 .base_baud
= 1152000,
3109 .uart_offset
= 0x200,
3112 [pbn_b0_2_1843200
] = {
3115 .base_baud
= 1843200,
3118 [pbn_b0_4_1843200
] = {
3121 .base_baud
= 1843200,
3125 [pbn_b0_2_1843200_200
] = {
3128 .base_baud
= 1843200,
3129 .uart_offset
= 0x200,
3131 [pbn_b0_4_1843200_200
] = {
3134 .base_baud
= 1843200,
3135 .uart_offset
= 0x200,
3137 [pbn_b0_8_1843200_200
] = {
3140 .base_baud
= 1843200,
3141 .uart_offset
= 0x200,
3143 [pbn_b0_1_4000000
] = {
3146 .base_baud
= 4000000,
3150 [pbn_b0_bt_1_115200
] = {
3151 .flags
= FL_BASE0
|FL_BASE_BARS
,
3153 .base_baud
= 115200,
3156 [pbn_b0_bt_2_115200
] = {
3157 .flags
= FL_BASE0
|FL_BASE_BARS
,
3159 .base_baud
= 115200,
3162 [pbn_b0_bt_4_115200
] = {
3163 .flags
= FL_BASE0
|FL_BASE_BARS
,
3165 .base_baud
= 115200,
3168 [pbn_b0_bt_8_115200
] = {
3169 .flags
= FL_BASE0
|FL_BASE_BARS
,
3171 .base_baud
= 115200,
3175 [pbn_b0_bt_1_460800
] = {
3176 .flags
= FL_BASE0
|FL_BASE_BARS
,
3178 .base_baud
= 460800,
3181 [pbn_b0_bt_2_460800
] = {
3182 .flags
= FL_BASE0
|FL_BASE_BARS
,
3184 .base_baud
= 460800,
3187 [pbn_b0_bt_4_460800
] = {
3188 .flags
= FL_BASE0
|FL_BASE_BARS
,
3190 .base_baud
= 460800,
3194 [pbn_b0_bt_1_921600
] = {
3195 .flags
= FL_BASE0
|FL_BASE_BARS
,
3197 .base_baud
= 921600,
3200 [pbn_b0_bt_2_921600
] = {
3201 .flags
= FL_BASE0
|FL_BASE_BARS
,
3203 .base_baud
= 921600,
3206 [pbn_b0_bt_4_921600
] = {
3207 .flags
= FL_BASE0
|FL_BASE_BARS
,
3209 .base_baud
= 921600,
3212 [pbn_b0_bt_8_921600
] = {
3213 .flags
= FL_BASE0
|FL_BASE_BARS
,
3215 .base_baud
= 921600,
3219 [pbn_b1_1_115200
] = {
3222 .base_baud
= 115200,
3225 [pbn_b1_2_115200
] = {
3228 .base_baud
= 115200,
3231 [pbn_b1_4_115200
] = {
3234 .base_baud
= 115200,
3237 [pbn_b1_8_115200
] = {
3240 .base_baud
= 115200,
3243 [pbn_b1_16_115200
] = {
3246 .base_baud
= 115200,
3250 [pbn_b1_1_921600
] = {
3253 .base_baud
= 921600,
3256 [pbn_b1_2_921600
] = {
3259 .base_baud
= 921600,
3262 [pbn_b1_4_921600
] = {
3265 .base_baud
= 921600,
3268 [pbn_b1_8_921600
] = {
3271 .base_baud
= 921600,
3274 [pbn_b1_2_1250000
] = {
3277 .base_baud
= 1250000,
3281 [pbn_b1_bt_1_115200
] = {
3282 .flags
= FL_BASE1
|FL_BASE_BARS
,
3284 .base_baud
= 115200,
3287 [pbn_b1_bt_2_115200
] = {
3288 .flags
= FL_BASE1
|FL_BASE_BARS
,
3290 .base_baud
= 115200,
3293 [pbn_b1_bt_4_115200
] = {
3294 .flags
= FL_BASE1
|FL_BASE_BARS
,
3296 .base_baud
= 115200,
3300 [pbn_b1_bt_2_921600
] = {
3301 .flags
= FL_BASE1
|FL_BASE_BARS
,
3303 .base_baud
= 921600,
3307 [pbn_b1_1_1382400
] = {
3310 .base_baud
= 1382400,
3313 [pbn_b1_2_1382400
] = {
3316 .base_baud
= 1382400,
3319 [pbn_b1_4_1382400
] = {
3322 .base_baud
= 1382400,
3325 [pbn_b1_8_1382400
] = {
3328 .base_baud
= 1382400,
3332 [pbn_b2_1_115200
] = {
3335 .base_baud
= 115200,
3338 [pbn_b2_2_115200
] = {
3341 .base_baud
= 115200,
3344 [pbn_b2_4_115200
] = {
3347 .base_baud
= 115200,
3350 [pbn_b2_8_115200
] = {
3353 .base_baud
= 115200,
3357 [pbn_b2_1_460800
] = {
3360 .base_baud
= 460800,
3363 [pbn_b2_4_460800
] = {
3366 .base_baud
= 460800,
3369 [pbn_b2_8_460800
] = {
3372 .base_baud
= 460800,
3375 [pbn_b2_16_460800
] = {
3378 .base_baud
= 460800,
3382 [pbn_b2_1_921600
] = {
3385 .base_baud
= 921600,
3388 [pbn_b2_4_921600
] = {
3391 .base_baud
= 921600,
3394 [pbn_b2_8_921600
] = {
3397 .base_baud
= 921600,
3401 [pbn_b2_8_1152000
] = {
3404 .base_baud
= 1152000,
3408 [pbn_b2_bt_1_115200
] = {
3409 .flags
= FL_BASE2
|FL_BASE_BARS
,
3411 .base_baud
= 115200,
3414 [pbn_b2_bt_2_115200
] = {
3415 .flags
= FL_BASE2
|FL_BASE_BARS
,
3417 .base_baud
= 115200,
3420 [pbn_b2_bt_4_115200
] = {
3421 .flags
= FL_BASE2
|FL_BASE_BARS
,
3423 .base_baud
= 115200,
3427 [pbn_b2_bt_2_921600
] = {
3428 .flags
= FL_BASE2
|FL_BASE_BARS
,
3430 .base_baud
= 921600,
3433 [pbn_b2_bt_4_921600
] = {
3434 .flags
= FL_BASE2
|FL_BASE_BARS
,
3436 .base_baud
= 921600,
3440 [pbn_b3_2_115200
] = {
3443 .base_baud
= 115200,
3446 [pbn_b3_4_115200
] = {
3449 .base_baud
= 115200,
3452 [pbn_b3_8_115200
] = {
3455 .base_baud
= 115200,
3459 [pbn_b4_bt_2_921600
] = {
3462 .base_baud
= 921600,
3465 [pbn_b4_bt_4_921600
] = {
3468 .base_baud
= 921600,
3471 [pbn_b4_bt_8_921600
] = {
3474 .base_baud
= 921600,
3479 * Entries following this are board-specific.
3488 .base_baud
= 921600,
3489 .uart_offset
= 0x400,
3493 .flags
= FL_BASE2
|FL_BASE_BARS
,
3495 .base_baud
= 921600,
3496 .uart_offset
= 0x400,
3500 .flags
= FL_BASE2
|FL_BASE_BARS
,
3502 .base_baud
= 921600,
3503 .uart_offset
= 0x400,
3507 /* I think this entry is broken - the first_offset looks wrong --rmk */
3508 [pbn_plx_romulus
] = {
3511 .base_baud
= 921600,
3512 .uart_offset
= 8 << 2,
3514 .first_offset
= 0x03,
3518 * EndRun Technologies
3519 * Uses the size of PCI Base region 0 to
3520 * signal now many ports are available
3521 * 2 port 952 Uart support
3523 [pbn_endrun_2_4000000
] = {
3526 .base_baud
= 4000000,
3527 .uart_offset
= 0x200,
3528 .first_offset
= 0x1000,
3532 * This board uses the size of PCI Base region 0 to
3533 * signal now many ports are available
3536 .flags
= FL_BASE0
|FL_REGION_SZ_CAP
,
3538 .base_baud
= 115200,
3541 [pbn_oxsemi_1_4000000
] = {
3544 .base_baud
= 4000000,
3545 .uart_offset
= 0x200,
3546 .first_offset
= 0x1000,
3548 [pbn_oxsemi_2_4000000
] = {
3551 .base_baud
= 4000000,
3552 .uart_offset
= 0x200,
3553 .first_offset
= 0x1000,
3555 [pbn_oxsemi_4_4000000
] = {
3558 .base_baud
= 4000000,
3559 .uart_offset
= 0x200,
3560 .first_offset
= 0x1000,
3562 [pbn_oxsemi_8_4000000
] = {
3565 .base_baud
= 4000000,
3566 .uart_offset
= 0x200,
3567 .first_offset
= 0x1000,
3572 * EKF addition for i960 Boards form EKF with serial port.
3575 [pbn_intel_i960
] = {
3578 .base_baud
= 921600,
3579 .uart_offset
= 8 << 2,
3581 .first_offset
= 0x10000,
3584 .flags
= FL_BASE0
|FL_NOIRQ
,
3586 .base_baud
= 458333,
3589 .first_offset
= 0x20178,
3593 * Computone - uses IOMEM.
3595 [pbn_computone_4
] = {
3598 .base_baud
= 921600,
3599 .uart_offset
= 0x40,
3601 .first_offset
= 0x200,
3603 [pbn_computone_6
] = {
3606 .base_baud
= 921600,
3607 .uart_offset
= 0x40,
3609 .first_offset
= 0x200,
3611 [pbn_computone_8
] = {
3614 .base_baud
= 921600,
3615 .uart_offset
= 0x40,
3617 .first_offset
= 0x200,
3622 .base_baud
= 460800,
3627 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3628 * Only basic 16550A support.
3629 * XR17C15[24] are not tested, but they should work.
3631 [pbn_exar_XR17C152
] = {
3634 .base_baud
= 921600,
3635 .uart_offset
= 0x200,
3637 [pbn_exar_XR17C154
] = {
3640 .base_baud
= 921600,
3641 .uart_offset
= 0x200,
3643 [pbn_exar_XR17C158
] = {
3646 .base_baud
= 921600,
3647 .uart_offset
= 0x200,
3649 [pbn_exar_XR17V352
] = {
3652 .base_baud
= 7812500,
3653 .uart_offset
= 0x400,
3657 [pbn_exar_XR17V354
] = {
3660 .base_baud
= 7812500,
3661 .uart_offset
= 0x400,
3665 [pbn_exar_XR17V358
] = {
3668 .base_baud
= 7812500,
3669 .uart_offset
= 0x400,
3673 [pbn_exar_XR17V4358
] = {
3676 .base_baud
= 7812500,
3677 .uart_offset
= 0x400,
3681 [pbn_exar_XR17V8358
] = {
3684 .base_baud
= 7812500,
3685 .uart_offset
= 0x400,
3689 [pbn_exar_ibm_saturn
] = {
3692 .base_baud
= 921600,
3693 .uart_offset
= 0x200,
3697 * PA Semi PWRficient PA6T-1682M on-chip UART
3699 [pbn_pasemi_1682M
] = {
3702 .base_baud
= 8333333,
3705 * National Instruments 843x
3710 .base_baud
= 3686400,
3711 .uart_offset
= 0x10,
3712 .first_offset
= 0x800,
3717 .base_baud
= 3686400,
3718 .uart_offset
= 0x10,
3719 .first_offset
= 0x800,
3724 .base_baud
= 3686400,
3725 .uart_offset
= 0x10,
3726 .first_offset
= 0x800,
3731 .base_baud
= 3686400,
3732 .uart_offset
= 0x10,
3733 .first_offset
= 0x800,
3736 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3738 [pbn_ADDIDATA_PCIe_1_3906250
] = {
3741 .base_baud
= 3906250,
3742 .uart_offset
= 0x200,
3743 .first_offset
= 0x1000,
3745 [pbn_ADDIDATA_PCIe_2_3906250
] = {
3748 .base_baud
= 3906250,
3749 .uart_offset
= 0x200,
3750 .first_offset
= 0x1000,
3752 [pbn_ADDIDATA_PCIe_4_3906250
] = {
3755 .base_baud
= 3906250,
3756 .uart_offset
= 0x200,
3757 .first_offset
= 0x1000,
3759 [pbn_ADDIDATA_PCIe_8_3906250
] = {
3762 .base_baud
= 3906250,
3763 .uart_offset
= 0x200,
3764 .first_offset
= 0x1000,
3766 [pbn_ce4100_1_115200
] = {
3767 .flags
= FL_BASE_BARS
,
3769 .base_baud
= 921600,
3775 .base_baud
= 2764800,
3781 .base_baud
= 2764800,
3787 .base_baud
= 115200,
3788 .uart_offset
= 0x200,
3790 [pbn_NETMOS9900_2s_115200
] = {
3793 .base_baud
= 115200,
3795 [pbn_brcm_trumanage
] = {
3799 .base_baud
= 115200,
3804 .base_baud
= 115200,
3805 .first_offset
= 0x40,
3810 .base_baud
= 115200,
3811 .first_offset
= 0x40,
3816 .base_baud
= 115200,
3817 .first_offset
= 0x40,
3822 .base_baud
= 115200,
3824 .first_offset
= 0xC0,
3829 .base_baud
= 115200,
3831 .first_offset
= 0xC0,
3834 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3836 [pbn_pericom_PI7C9X7951
] = {
3839 .base_baud
= 921600,
3842 [pbn_pericom_PI7C9X7952
] = {
3845 .base_baud
= 921600,
3848 [pbn_pericom_PI7C9X7954
] = {
3851 .base_baud
= 921600,
3854 [pbn_pericom_PI7C9X7958
] = {
3857 .base_baud
= 921600,
3862 static const struct pci_device_id blacklist
[] = {
3864 { PCI_VDEVICE(AL
, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3865 { PCI_VDEVICE(MOTOROLA
, 0x3052), }, /* Motorola Si3052-based modem */
3866 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3868 /* multi-io cards handled by parport_serial */
3869 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3870 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3871 { PCI_DEVICE(0x4348, 0x7173), }, /* WCH CH355 4S */
3872 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3873 { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
3875 /* Moxa Smartio MUE boards handled by 8250_moxa */
3876 { PCI_VDEVICE(MOXA
, 0x1024), },
3877 { PCI_VDEVICE(MOXA
, 0x1025), },
3878 { PCI_VDEVICE(MOXA
, 0x1045), },
3879 { PCI_VDEVICE(MOXA
, 0x1144), },
3880 { PCI_VDEVICE(MOXA
, 0x1160), },
3881 { PCI_VDEVICE(MOXA
, 0x1161), },
3882 { PCI_VDEVICE(MOXA
, 0x1182), },
3883 { PCI_VDEVICE(MOXA
, 0x1183), },
3884 { PCI_VDEVICE(MOXA
, 0x1322), },
3885 { PCI_VDEVICE(MOXA
, 0x1342), },
3886 { PCI_VDEVICE(MOXA
, 0x1381), },
3887 { PCI_VDEVICE(MOXA
, 0x1683), },
3889 /* Intel platforms with MID UART */
3890 { PCI_VDEVICE(INTEL
, 0x081b), },
3891 { PCI_VDEVICE(INTEL
, 0x081c), },
3892 { PCI_VDEVICE(INTEL
, 0x081d), },
3893 { PCI_VDEVICE(INTEL
, 0x1191), },
3894 { PCI_VDEVICE(INTEL
, 0x19d8), },
3898 * Given a complete unknown PCI device, try to use some heuristics to
3899 * guess what the configuration might be, based on the pitiful PCI
3900 * serial specs. Returns 0 on success, 1 on failure.
3903 serial_pci_guess_board(struct pci_dev
*dev
, struct pciserial_board
*board
)
3905 const struct pci_device_id
*bldev
;
3906 int num_iomem
, num_port
, first_port
= -1, i
;
3909 * If it is not a communications device or the programming
3910 * interface is greater than 6, give up.
3912 * (Should we try to make guesses for multiport serial devices
3915 if ((((dev
->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL
) &&
3916 ((dev
->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM
)) ||
3917 (dev
->class & 0xff) > 6)
3921 * Do not access blacklisted devices that are known not to
3922 * feature serial ports or are handled by other modules.
3924 for (bldev
= blacklist
;
3925 bldev
< blacklist
+ ARRAY_SIZE(blacklist
);
3927 if (dev
->vendor
== bldev
->vendor
&&
3928 dev
->device
== bldev
->device
)
3932 num_iomem
= num_port
= 0;
3933 for (i
= 0; i
< PCI_NUM_BAR_RESOURCES
; i
++) {
3934 if (pci_resource_flags(dev
, i
) & IORESOURCE_IO
) {
3936 if (first_port
== -1)
3939 if (pci_resource_flags(dev
, i
) & IORESOURCE_MEM
)
3944 * If there is 1 or 0 iomem regions, and exactly one port,
3945 * use it. We guess the number of ports based on the IO
3948 if (num_iomem
<= 1 && num_port
== 1) {
3949 board
->flags
= first_port
;
3950 board
->num_ports
= pci_resource_len(dev
, first_port
) / 8;
3955 * Now guess if we've got a board which indexes by BARs.
3956 * Each IO BAR should be 8 bytes, and they should follow
3961 for (i
= 0; i
< PCI_NUM_BAR_RESOURCES
; i
++) {
3962 if (pci_resource_flags(dev
, i
) & IORESOURCE_IO
&&
3963 pci_resource_len(dev
, i
) == 8 &&
3964 (first_port
== -1 || (first_port
+ num_port
) == i
)) {
3966 if (first_port
== -1)
3972 board
->flags
= first_port
| FL_BASE_BARS
;
3973 board
->num_ports
= num_port
;
3981 serial_pci_matches(const struct pciserial_board
*board
,
3982 const struct pciserial_board
*guessed
)
3985 board
->num_ports
== guessed
->num_ports
&&
3986 board
->base_baud
== guessed
->base_baud
&&
3987 board
->uart_offset
== guessed
->uart_offset
&&
3988 board
->reg_shift
== guessed
->reg_shift
&&
3989 board
->first_offset
== guessed
->first_offset
;
3992 struct serial_private
*
3993 pciserial_init_ports(struct pci_dev
*dev
, const struct pciserial_board
*board
)
3995 struct uart_8250_port uart
;
3996 struct serial_private
*priv
;
3997 struct pci_serial_quirk
*quirk
;
3998 int rc
, nr_ports
, i
;
4000 nr_ports
= board
->num_ports
;
4003 * Find an init and setup quirks.
4005 quirk
= find_quirk(dev
);
4008 * Run the new-style initialization function.
4009 * The initialization function returns:
4011 * 0 - use board->num_ports
4012 * >0 - number of ports
4015 rc
= quirk
->init(dev
);
4024 priv
= kzalloc(sizeof(struct serial_private
) +
4025 sizeof(unsigned int) * nr_ports
,
4028 priv
= ERR_PTR(-ENOMEM
);
4033 priv
->quirk
= quirk
;
4035 memset(&uart
, 0, sizeof(uart
));
4036 uart
.port
.flags
= UPF_SKIP_TEST
| UPF_BOOT_AUTOCONF
| UPF_SHARE_IRQ
;
4037 uart
.port
.uartclk
= board
->base_baud
* 16;
4038 uart
.port
.irq
= get_pci_irq(dev
, board
);
4039 uart
.port
.dev
= &dev
->dev
;
4041 for (i
= 0; i
< nr_ports
; i
++) {
4042 if (quirk
->setup(priv
, board
, &uart
, i
))
4045 dev_dbg(&dev
->dev
, "Setup PCI port: port %lx, irq %d, type %d\n",
4046 uart
.port
.iobase
, uart
.port
.irq
, uart
.port
.iotype
);
4048 priv
->line
[i
] = serial8250_register_8250_port(&uart
);
4049 if (priv
->line
[i
] < 0) {
4051 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4052 uart
.port
.iobase
, uart
.port
.irq
,
4053 uart
.port
.iotype
, priv
->line
[i
]);
4066 EXPORT_SYMBOL_GPL(pciserial_init_ports
);
4068 void pciserial_remove_ports(struct serial_private
*priv
)
4070 struct pci_serial_quirk
*quirk
;
4073 for (i
= 0; i
< priv
->nr
; i
++)
4074 serial8250_unregister_port(priv
->line
[i
]);
4077 * Find the exit quirks.
4079 quirk
= find_quirk(priv
->dev
);
4081 quirk
->exit(priv
->dev
);
4085 EXPORT_SYMBOL_GPL(pciserial_remove_ports
);
4087 void pciserial_suspend_ports(struct serial_private
*priv
)
4091 for (i
= 0; i
< priv
->nr
; i
++)
4092 if (priv
->line
[i
] >= 0)
4093 serial8250_suspend_port(priv
->line
[i
]);
4096 * Ensure that every init quirk is properly torn down
4098 if (priv
->quirk
->exit
)
4099 priv
->quirk
->exit(priv
->dev
);
4101 EXPORT_SYMBOL_GPL(pciserial_suspend_ports
);
4103 void pciserial_resume_ports(struct serial_private
*priv
)
4108 * Ensure that the board is correctly configured.
4110 if (priv
->quirk
->init
)
4111 priv
->quirk
->init(priv
->dev
);
4113 for (i
= 0; i
< priv
->nr
; i
++)
4114 if (priv
->line
[i
] >= 0)
4115 serial8250_resume_port(priv
->line
[i
]);
4117 EXPORT_SYMBOL_GPL(pciserial_resume_ports
);
4120 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4121 * to the arrangement of serial ports on a PCI card.
4124 pciserial_init_one(struct pci_dev
*dev
, const struct pci_device_id
*ent
)
4126 struct pci_serial_quirk
*quirk
;
4127 struct serial_private
*priv
;
4128 const struct pciserial_board
*board
;
4129 struct pciserial_board tmp
;
4132 quirk
= find_quirk(dev
);
4134 rc
= quirk
->probe(dev
);
4139 if (ent
->driver_data
>= ARRAY_SIZE(pci_boards
)) {
4140 dev_err(&dev
->dev
, "invalid driver_data: %ld\n",
4145 board
= &pci_boards
[ent
->driver_data
];
4147 rc
= pcim_enable_device(dev
);
4148 pci_save_state(dev
);
4152 if (ent
->driver_data
== pbn_default
) {
4154 * Use a copy of the pci_board entry for this;
4155 * avoid changing entries in the table.
4157 memcpy(&tmp
, board
, sizeof(struct pciserial_board
));
4161 * We matched one of our class entries. Try to
4162 * determine the parameters of this board.
4164 rc
= serial_pci_guess_board(dev
, &tmp
);
4169 * We matched an explicit entry. If we are able to
4170 * detect this boards settings with our heuristic,
4171 * then we no longer need this entry.
4173 memcpy(&tmp
, &pci_boards
[pbn_default
],
4174 sizeof(struct pciserial_board
));
4175 rc
= serial_pci_guess_board(dev
, &tmp
);
4176 if (rc
== 0 && serial_pci_matches(board
, &tmp
))
4177 moan_device("Redundant entry in serial pci_table.",
4181 priv
= pciserial_init_ports(dev
, board
);
4183 return PTR_ERR(priv
);
4185 pci_set_drvdata(dev
, priv
);
4189 static void pciserial_remove_one(struct pci_dev
*dev
)
4191 struct serial_private
*priv
= pci_get_drvdata(dev
);
4193 pciserial_remove_ports(priv
);
4196 #ifdef CONFIG_PM_SLEEP
4197 static int pciserial_suspend_one(struct device
*dev
)
4199 struct pci_dev
*pdev
= to_pci_dev(dev
);
4200 struct serial_private
*priv
= pci_get_drvdata(pdev
);
4203 pciserial_suspend_ports(priv
);
4208 static int pciserial_resume_one(struct device
*dev
)
4210 struct pci_dev
*pdev
= to_pci_dev(dev
);
4211 struct serial_private
*priv
= pci_get_drvdata(pdev
);
4216 * The device may have been disabled. Re-enable it.
4218 err
= pci_enable_device(pdev
);
4219 /* FIXME: We cannot simply error out here */
4221 dev_err(dev
, "Unable to re-enable ports, trying to continue.\n");
4222 pciserial_resume_ports(priv
);
4228 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops
, pciserial_suspend_one
,
4229 pciserial_resume_one
);
4231 static struct pci_device_id serial_pci_tbl
[] = {
4232 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4233 { PCI_VENDOR_ID_ADVANTECH
, PCI_DEVICE_ID_ADVANTECH_PCI3620
,
4234 PCI_DEVICE_ID_ADVANTECH_PCI3620
, 0x0001, 0, 0,
4236 /* Advantech also use 0x3618 and 0xf618 */
4237 { PCI_VENDOR_ID_ADVANTECH
, PCI_DEVICE_ID_ADVANTECH_PCI3618
,
4238 PCI_DEVICE_ID_ADVANTECH_PCI3618
, PCI_ANY_ID
, 0, 0,
4240 { PCI_VENDOR_ID_ADVANTECH
, PCI_DEVICE_ID_ADVANTECH_PCIf618
,
4241 PCI_DEVICE_ID_ADVANTECH_PCI3618
, PCI_ANY_ID
, 0, 0,
4243 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V960
,
4244 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4245 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232
, 0, 0,
4247 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V960
,
4248 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4249 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232
, 0, 0,
4251 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V960
,
4252 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4253 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232
, 0, 0,
4255 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
4256 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4257 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232
, 0, 0,
4259 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
4260 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4261 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232
, 0, 0,
4263 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
4264 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4265 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232
, 0, 0,
4267 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
4268 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4269 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485
, 0, 0,
4271 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
4272 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4273 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4
, 0, 0,
4275 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
4276 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4277 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485
, 0, 0,
4279 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
4280 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4281 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2
, 0, 0,
4283 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
4284 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4285 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485
, 0, 0,
4287 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
4288 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4289 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6
, 0, 0,
4291 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
4292 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4293 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1
, 0, 0,
4295 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
4296 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4297 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1
, 0, 0,
4299 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
4300 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4301 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ
, 0, 0,
4303 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI954
,
4304 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4305 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2
, 0, 0,
4307 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI954
,
4308 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4309 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4
, 0, 0,
4311 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI954
,
4312 PCI_VENDOR_ID_AFAVLAB
,
4313 PCI_SUBDEVICE_ID_AFAVLAB_P061
, 0, 0,
4315 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C152
,
4316 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4317 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232
, 0, 0,
4318 pbn_b0_2_1843200_200
},
4319 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C154
,
4320 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4321 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232
, 0, 0,
4322 pbn_b0_4_1843200_200
},
4323 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C158
,
4324 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4325 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232
, 0, 0,
4326 pbn_b0_8_1843200_200
},
4327 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C152
,
4328 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4329 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1
, 0, 0,
4330 pbn_b0_2_1843200_200
},
4331 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C154
,
4332 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4333 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2
, 0, 0,
4334 pbn_b0_4_1843200_200
},
4335 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C158
,
4336 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4337 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4
, 0, 0,
4338 pbn_b0_8_1843200_200
},
4339 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C152
,
4340 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4341 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2
, 0, 0,
4342 pbn_b0_2_1843200_200
},
4343 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C154
,
4344 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4345 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4
, 0, 0,
4346 pbn_b0_4_1843200_200
},
4347 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C158
,
4348 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4349 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8
, 0, 0,
4350 pbn_b0_8_1843200_200
},
4351 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C152
,
4352 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4353 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485
, 0, 0,
4354 pbn_b0_2_1843200_200
},
4355 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C154
,
4356 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4357 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485
, 0, 0,
4358 pbn_b0_4_1843200_200
},
4359 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C158
,
4360 PCI_SUBVENDOR_ID_CONNECT_TECH
,
4361 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485
, 0, 0,
4362 pbn_b0_8_1843200_200
},
4363 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C152
,
4364 PCI_VENDOR_ID_IBM
, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT
,
4365 0, 0, pbn_exar_ibm_saturn
},
4367 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_U530
,
4368 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4369 pbn_b2_bt_1_115200
},
4370 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_UCOMM2
,
4371 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4372 pbn_b2_bt_2_115200
},
4373 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_UCOMM422
,
4374 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4375 pbn_b2_bt_4_115200
},
4376 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_UCOMM232
,
4377 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4378 pbn_b2_bt_2_115200
},
4379 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_COMM4
,
4380 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4381 pbn_b2_bt_4_115200
},
4382 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_COMM8
,
4383 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4385 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_7803
,
4386 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4388 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_UCOMM8
,
4389 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4392 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_GTEK_SERIAL2
,
4393 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4394 pbn_b2_bt_2_115200
},
4395 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_SPCOM200
,
4396 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4397 pbn_b2_bt_2_921600
},
4399 * VScom SPCOM800, from sl@s.pl
4401 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_SPCOM800
,
4402 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4404 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_1077
,
4405 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4407 /* Unknown card - subdevice 0x1584 */
4408 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
4410 PCI_SUBDEVICE_ID_UNKNOWN_0x1584
, 0, 0,
4412 /* Unknown card - subdevice 0x1588 */
4413 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
4415 PCI_SUBDEVICE_ID_UNKNOWN_0x1588
, 0, 0,
4417 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
4418 PCI_SUBVENDOR_ID_KEYSPAN
,
4419 PCI_SUBDEVICE_ID_KEYSPAN_SX2
, 0, 0,
4421 { PCI_VENDOR_ID_PANACOM
, PCI_DEVICE_ID_PANACOM_QUADMODEM
,
4422 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4424 { PCI_VENDOR_ID_PANACOM
, PCI_DEVICE_ID_PANACOM_DUALMODEM
,
4425 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4427 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9030
,
4428 PCI_VENDOR_ID_ESDGMBH
,
4429 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4
, 0, 0,
4431 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
4432 PCI_SUBVENDOR_ID_CHASE_PCIFAST
,
4433 PCI_SUBDEVICE_ID_CHASE_PCIFAST4
, 0, 0,
4435 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
4436 PCI_SUBVENDOR_ID_CHASE_PCIFAST
,
4437 PCI_SUBDEVICE_ID_CHASE_PCIFAST8
, 0, 0,
4439 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
4440 PCI_SUBVENDOR_ID_CHASE_PCIFAST
,
4441 PCI_SUBDEVICE_ID_CHASE_PCIFAST16
, 0, 0,
4443 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
4444 PCI_SUBVENDOR_ID_CHASE_PCIFAST
,
4445 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC
, 0, 0,
4447 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
4448 PCI_SUBVENDOR_ID_CHASE_PCIRAS
,
4449 PCI_SUBDEVICE_ID_CHASE_PCIRAS4
, 0, 0,
4451 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
4452 PCI_SUBVENDOR_ID_CHASE_PCIRAS
,
4453 PCI_SUBDEVICE_ID_CHASE_PCIRAS8
, 0, 0,
4455 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
4456 PCI_SUBVENDOR_ID_EXSYS
,
4457 PCI_SUBDEVICE_ID_EXSYS_4055
, 0, 0,
4460 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4463 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_ROMULUS
,
4464 0x10b5, 0x106a, 0, 0,
4467 * EndRun Technologies. PCI express device range.
4468 * EndRun PTP/1588 has 2 Native UARTs.
4470 { PCI_VENDOR_ID_ENDRUN
, PCI_DEVICE_ID_ENDRUN_1588
,
4471 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4472 pbn_endrun_2_4000000
},
4474 * Quatech cards. These actually have configurable clocks but for
4475 * now we just use the default.
4477 * 100 series are RS232, 200 series RS422,
4479 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_QSC100
,
4480 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4482 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_DSC100
,
4483 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4485 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_DSC100E
,
4486 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4488 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_DSC200
,
4489 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4491 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_DSC200E
,
4492 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4494 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_QSC200
,
4495 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4497 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_ESC100D
,
4498 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4500 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_ESC100M
,
4501 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4503 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_QSCP100
,
4504 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4506 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_DSCP100
,
4507 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4509 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_QSCP200
,
4510 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4512 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_DSCP200
,
4513 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4515 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_QSCLP100
,
4516 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4518 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_DSCLP100
,
4519 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4521 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_SSCLP100
,
4522 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4524 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_QSCLP200
,
4525 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4527 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_DSCLP200
,
4528 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4530 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_SSCLP200
,
4531 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4533 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_ESCLP100
,
4534 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4537 { PCI_VENDOR_ID_SPECIALIX
, PCI_DEVICE_ID_OXSEMI_16PCI954
,
4538 PCI_VENDOR_ID_SPECIALIX
, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4
,
4541 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI954
,
4542 PCI_SUBVENDOR_ID_SIIG
, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL
,
4545 { PCI_VENDOR_ID_OXSEMI
, 0x9505,
4546 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4547 pbn_b0_bt_2_921600
},
4550 * The below card is a little controversial since it is the
4551 * subject of a PCI vendor/device ID clash. (See
4552 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4553 * For now just used the hex ID 0x950a.
4555 { PCI_VENDOR_ID_OXSEMI
, 0x950a,
4556 PCI_SUBVENDOR_ID_SIIG
, PCI_SUBDEVICE_ID_SIIG_DUAL_00
,
4557 0, 0, pbn_b0_2_115200
},
4558 { PCI_VENDOR_ID_OXSEMI
, 0x950a,
4559 PCI_SUBVENDOR_ID_SIIG
, PCI_SUBDEVICE_ID_SIIG_DUAL_30
,
4560 0, 0, pbn_b0_2_115200
},
4561 { PCI_VENDOR_ID_OXSEMI
, 0x950a,
4562 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4564 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_C950
,
4565 PCI_VENDOR_ID_OXSEMI
, PCI_SUBDEVICE_ID_OXSEMI_C950
, 0, 0,
4567 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI954
,
4568 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4570 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI952
,
4571 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4572 pbn_b0_bt_2_921600
},
4573 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI958
,
4574 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4578 * Oxford Semiconductor Inc. Tornado PCI express device range.
4580 { PCI_VENDOR_ID_OXSEMI
, 0xc101, /* OXPCIe952 1 Legacy UART */
4581 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4583 { PCI_VENDOR_ID_OXSEMI
, 0xc105, /* OXPCIe952 1 Legacy UART */
4584 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4586 { PCI_VENDOR_ID_OXSEMI
, 0xc11b, /* OXPCIe952 1 Native UART */
4587 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4588 pbn_oxsemi_1_4000000
},
4589 { PCI_VENDOR_ID_OXSEMI
, 0xc11f, /* OXPCIe952 1 Native UART */
4590 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4591 pbn_oxsemi_1_4000000
},
4592 { PCI_VENDOR_ID_OXSEMI
, 0xc120, /* OXPCIe952 1 Legacy UART */
4593 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4595 { PCI_VENDOR_ID_OXSEMI
, 0xc124, /* OXPCIe952 1 Legacy UART */
4596 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4598 { PCI_VENDOR_ID_OXSEMI
, 0xc138, /* OXPCIe952 1 Native UART */
4599 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4600 pbn_oxsemi_1_4000000
},
4601 { PCI_VENDOR_ID_OXSEMI
, 0xc13d, /* OXPCIe952 1 Native UART */
4602 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4603 pbn_oxsemi_1_4000000
},
4604 { PCI_VENDOR_ID_OXSEMI
, 0xc140, /* OXPCIe952 1 Legacy UART */
4605 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4607 { PCI_VENDOR_ID_OXSEMI
, 0xc141, /* OXPCIe952 1 Legacy UART */
4608 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4610 { PCI_VENDOR_ID_OXSEMI
, 0xc144, /* OXPCIe952 1 Legacy UART */
4611 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4613 { PCI_VENDOR_ID_OXSEMI
, 0xc145, /* OXPCIe952 1 Legacy UART */
4614 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4616 { PCI_VENDOR_ID_OXSEMI
, 0xc158, /* OXPCIe952 2 Native UART */
4617 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4618 pbn_oxsemi_2_4000000
},
4619 { PCI_VENDOR_ID_OXSEMI
, 0xc15d, /* OXPCIe952 2 Native UART */
4620 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4621 pbn_oxsemi_2_4000000
},
4622 { PCI_VENDOR_ID_OXSEMI
, 0xc208, /* OXPCIe954 4 Native UART */
4623 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4624 pbn_oxsemi_4_4000000
},
4625 { PCI_VENDOR_ID_OXSEMI
, 0xc20d, /* OXPCIe954 4 Native UART */
4626 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4627 pbn_oxsemi_4_4000000
},
4628 { PCI_VENDOR_ID_OXSEMI
, 0xc308, /* OXPCIe958 8 Native UART */
4629 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4630 pbn_oxsemi_8_4000000
},
4631 { PCI_VENDOR_ID_OXSEMI
, 0xc30d, /* OXPCIe958 8 Native UART */
4632 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4633 pbn_oxsemi_8_4000000
},
4634 { PCI_VENDOR_ID_OXSEMI
, 0xc40b, /* OXPCIe200 1 Native UART */
4635 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4636 pbn_oxsemi_1_4000000
},
4637 { PCI_VENDOR_ID_OXSEMI
, 0xc40f, /* OXPCIe200 1 Native UART */
4638 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4639 pbn_oxsemi_1_4000000
},
4640 { PCI_VENDOR_ID_OXSEMI
, 0xc41b, /* OXPCIe200 1 Native UART */
4641 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4642 pbn_oxsemi_1_4000000
},
4643 { PCI_VENDOR_ID_OXSEMI
, 0xc41f, /* OXPCIe200 1 Native UART */
4644 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4645 pbn_oxsemi_1_4000000
},
4646 { PCI_VENDOR_ID_OXSEMI
, 0xc42b, /* OXPCIe200 1 Native UART */
4647 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4648 pbn_oxsemi_1_4000000
},
4649 { PCI_VENDOR_ID_OXSEMI
, 0xc42f, /* OXPCIe200 1 Native UART */
4650 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4651 pbn_oxsemi_1_4000000
},
4652 { PCI_VENDOR_ID_OXSEMI
, 0xc43b, /* OXPCIe200 1 Native UART */
4653 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4654 pbn_oxsemi_1_4000000
},
4655 { PCI_VENDOR_ID_OXSEMI
, 0xc43f, /* OXPCIe200 1 Native UART */
4656 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4657 pbn_oxsemi_1_4000000
},
4658 { PCI_VENDOR_ID_OXSEMI
, 0xc44b, /* OXPCIe200 1 Native UART */
4659 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4660 pbn_oxsemi_1_4000000
},
4661 { PCI_VENDOR_ID_OXSEMI
, 0xc44f, /* OXPCIe200 1 Native UART */
4662 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4663 pbn_oxsemi_1_4000000
},
4664 { PCI_VENDOR_ID_OXSEMI
, 0xc45b, /* OXPCIe200 1 Native UART */
4665 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4666 pbn_oxsemi_1_4000000
},
4667 { PCI_VENDOR_ID_OXSEMI
, 0xc45f, /* OXPCIe200 1 Native UART */
4668 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4669 pbn_oxsemi_1_4000000
},
4670 { PCI_VENDOR_ID_OXSEMI
, 0xc46b, /* OXPCIe200 1 Native UART */
4671 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4672 pbn_oxsemi_1_4000000
},
4673 { PCI_VENDOR_ID_OXSEMI
, 0xc46f, /* OXPCIe200 1 Native UART */
4674 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4675 pbn_oxsemi_1_4000000
},
4676 { PCI_VENDOR_ID_OXSEMI
, 0xc47b, /* OXPCIe200 1 Native UART */
4677 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4678 pbn_oxsemi_1_4000000
},
4679 { PCI_VENDOR_ID_OXSEMI
, 0xc47f, /* OXPCIe200 1 Native UART */
4680 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4681 pbn_oxsemi_1_4000000
},
4682 { PCI_VENDOR_ID_OXSEMI
, 0xc48b, /* OXPCIe200 1 Native UART */
4683 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4684 pbn_oxsemi_1_4000000
},
4685 { PCI_VENDOR_ID_OXSEMI
, 0xc48f, /* OXPCIe200 1 Native UART */
4686 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4687 pbn_oxsemi_1_4000000
},
4688 { PCI_VENDOR_ID_OXSEMI
, 0xc49b, /* OXPCIe200 1 Native UART */
4689 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4690 pbn_oxsemi_1_4000000
},
4691 { PCI_VENDOR_ID_OXSEMI
, 0xc49f, /* OXPCIe200 1 Native UART */
4692 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4693 pbn_oxsemi_1_4000000
},
4694 { PCI_VENDOR_ID_OXSEMI
, 0xc4ab, /* OXPCIe200 1 Native UART */
4695 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4696 pbn_oxsemi_1_4000000
},
4697 { PCI_VENDOR_ID_OXSEMI
, 0xc4af, /* OXPCIe200 1 Native UART */
4698 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4699 pbn_oxsemi_1_4000000
},
4700 { PCI_VENDOR_ID_OXSEMI
, 0xc4bb, /* OXPCIe200 1 Native UART */
4701 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4702 pbn_oxsemi_1_4000000
},
4703 { PCI_VENDOR_ID_OXSEMI
, 0xc4bf, /* OXPCIe200 1 Native UART */
4704 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4705 pbn_oxsemi_1_4000000
},
4706 { PCI_VENDOR_ID_OXSEMI
, 0xc4cb, /* OXPCIe200 1 Native UART */
4707 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4708 pbn_oxsemi_1_4000000
},
4709 { PCI_VENDOR_ID_OXSEMI
, 0xc4cf, /* OXPCIe200 1 Native UART */
4710 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4711 pbn_oxsemi_1_4000000
},
4713 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4715 { PCI_VENDOR_ID_MAINPINE
, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4716 PCI_VENDOR_ID_MAINPINE
, 0x4001, 0, 0,
4717 pbn_oxsemi_1_4000000
},
4718 { PCI_VENDOR_ID_MAINPINE
, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4719 PCI_VENDOR_ID_MAINPINE
, 0x4002, 0, 0,
4720 pbn_oxsemi_2_4000000
},
4721 { PCI_VENDOR_ID_MAINPINE
, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4722 PCI_VENDOR_ID_MAINPINE
, 0x4004, 0, 0,
4723 pbn_oxsemi_4_4000000
},
4724 { PCI_VENDOR_ID_MAINPINE
, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4725 PCI_VENDOR_ID_MAINPINE
, 0x4008, 0, 0,
4726 pbn_oxsemi_8_4000000
},
4729 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4731 { PCI_VENDOR_ID_DIGI
, PCIE_DEVICE_ID_NEO_2_OX_IBM
,
4732 PCI_SUBVENDOR_ID_IBM
, PCI_ANY_ID
, 0, 0,
4733 pbn_oxsemi_2_4000000
},
4736 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4737 * from skokodyn@yahoo.com
4739 { PCI_VENDOR_ID_SBSMODULARIO
, PCI_DEVICE_ID_OCTPRO
,
4740 PCI_SUBVENDOR_ID_SBSMODULARIO
, PCI_SUBDEVICE_ID_OCTPRO232
, 0, 0,
4742 { PCI_VENDOR_ID_SBSMODULARIO
, PCI_DEVICE_ID_OCTPRO
,
4743 PCI_SUBVENDOR_ID_SBSMODULARIO
, PCI_SUBDEVICE_ID_OCTPRO422
, 0, 0,
4745 { PCI_VENDOR_ID_SBSMODULARIO
, PCI_DEVICE_ID_OCTPRO
,
4746 PCI_SUBVENDOR_ID_SBSMODULARIO
, PCI_SUBDEVICE_ID_POCTAL232
, 0, 0,
4748 { PCI_VENDOR_ID_SBSMODULARIO
, PCI_DEVICE_ID_OCTPRO
,
4749 PCI_SUBVENDOR_ID_SBSMODULARIO
, PCI_SUBDEVICE_ID_POCTAL422
, 0, 0,
4753 * Digitan DS560-558, from jimd@esoft.com
4755 { PCI_VENDOR_ID_ATT
, PCI_DEVICE_ID_ATT_VENUS_MODEM
,
4756 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4760 * Titan Electronic cards
4761 * The 400L and 800L have a custom setup quirk.
4763 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_100
,
4764 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4766 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_200
,
4767 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4769 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_400
,
4770 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4772 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_800B
,
4773 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4775 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_100L
,
4776 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4778 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_200L
,
4779 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4780 pbn_b1_bt_2_921600
},
4781 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_400L
,
4782 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4783 pbn_b0_bt_4_921600
},
4784 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_800L
,
4785 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4786 pbn_b0_bt_8_921600
},
4787 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_200I
,
4788 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4789 pbn_b4_bt_2_921600
},
4790 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_400I
,
4791 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4792 pbn_b4_bt_4_921600
},
4793 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_800I
,
4794 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4795 pbn_b4_bt_8_921600
},
4796 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_400EH
,
4797 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4799 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_800EH
,
4800 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4802 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_800EHB
,
4803 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4805 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_100E
,
4806 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4807 pbn_oxsemi_1_4000000
},
4808 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_200E
,
4809 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4810 pbn_oxsemi_2_4000000
},
4811 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_400E
,
4812 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4813 pbn_oxsemi_4_4000000
},
4814 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_800E
,
4815 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4816 pbn_oxsemi_8_4000000
},
4817 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_200EI
,
4818 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4819 pbn_oxsemi_2_4000000
},
4820 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_200EISI
,
4821 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4822 pbn_oxsemi_2_4000000
},
4823 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_200V3
,
4824 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4825 pbn_b0_bt_2_921600
},
4826 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_400V3
,
4827 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4829 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_410V3
,
4830 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4832 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_800V3
,
4833 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4835 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_800V3B
,
4836 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4839 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_10x_550
,
4840 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4842 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_10x_650
,
4843 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4845 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_10x_850
,
4846 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4848 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_10x_550
,
4849 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4850 pbn_b2_bt_2_921600
},
4851 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_10x_650
,
4852 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4853 pbn_b2_bt_2_921600
},
4854 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_10x_850
,
4855 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4856 pbn_b2_bt_2_921600
},
4857 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_10x_550
,
4858 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4859 pbn_b2_bt_4_921600
},
4860 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_10x_650
,
4861 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4862 pbn_b2_bt_4_921600
},
4863 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_10x_850
,
4864 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4865 pbn_b2_bt_4_921600
},
4866 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_20x_550
,
4867 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4869 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_20x_650
,
4870 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4872 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_20x_850
,
4873 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4875 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_20x_550
,
4876 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4877 pbn_b0_bt_2_921600
},
4878 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_20x_650
,
4879 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4880 pbn_b0_bt_2_921600
},
4881 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_20x_850
,
4882 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4883 pbn_b0_bt_2_921600
},
4884 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_20x_550
,
4885 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4886 pbn_b0_bt_4_921600
},
4887 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_20x_650
,
4888 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4889 pbn_b0_bt_4_921600
},
4890 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_20x_850
,
4891 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4892 pbn_b0_bt_4_921600
},
4893 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_8S_20x_550
,
4894 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4895 pbn_b0_bt_8_921600
},
4896 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_8S_20x_650
,
4897 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4898 pbn_b0_bt_8_921600
},
4899 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_8S_20x_850
,
4900 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4901 pbn_b0_bt_8_921600
},
4904 * Computone devices submitted by Doug McNash dmcnash@computone.com
4906 { PCI_VENDOR_ID_COMPUTONE
, PCI_DEVICE_ID_COMPUTONE_PG
,
4907 PCI_SUBVENDOR_ID_COMPUTONE
, PCI_SUBDEVICE_ID_COMPUTONE_PG4
,
4908 0, 0, pbn_computone_4
},
4909 { PCI_VENDOR_ID_COMPUTONE
, PCI_DEVICE_ID_COMPUTONE_PG
,
4910 PCI_SUBVENDOR_ID_COMPUTONE
, PCI_SUBDEVICE_ID_COMPUTONE_PG8
,
4911 0, 0, pbn_computone_8
},
4912 { PCI_VENDOR_ID_COMPUTONE
, PCI_DEVICE_ID_COMPUTONE_PG
,
4913 PCI_SUBVENDOR_ID_COMPUTONE
, PCI_SUBDEVICE_ID_COMPUTONE_PG6
,
4914 0, 0, pbn_computone_6
},
4916 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI95N
,
4917 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4919 { PCI_VENDOR_ID_TIMEDIA
, PCI_DEVICE_ID_TIMEDIA_1889
,
4920 PCI_VENDOR_ID_TIMEDIA
, PCI_ANY_ID
, 0, 0,
4921 pbn_b0_bt_1_921600
},
4926 { PCI_VENDOR_ID_SUNIX
, PCI_DEVICE_ID_SUNIX_1999
,
4927 PCI_VENDOR_ID_SUNIX
, PCI_ANY_ID
,
4928 PCI_CLASS_COMMUNICATION_SERIAL
<< 8, 0xffff00,
4929 pbn_b0_bt_1_921600
},
4931 { PCI_VENDOR_ID_SUNIX
, PCI_DEVICE_ID_SUNIX_1999
,
4932 PCI_VENDOR_ID_SUNIX
, PCI_ANY_ID
,
4933 PCI_CLASS_COMMUNICATION_MULTISERIAL
<< 8, 0xffff00,
4934 pbn_b0_bt_1_921600
},
4937 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4939 { PCI_VENDOR_ID_AFAVLAB
, PCI_DEVICE_ID_AFAVLAB_P028
,
4940 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4941 pbn_b0_bt_8_115200
},
4942 { PCI_VENDOR_ID_AFAVLAB
, PCI_DEVICE_ID_AFAVLAB_P030
,
4943 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4944 pbn_b0_bt_8_115200
},
4946 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_DSERIAL
,
4947 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4948 pbn_b0_bt_2_115200
},
4949 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_QUATRO_A
,
4950 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4951 pbn_b0_bt_2_115200
},
4952 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_QUATRO_B
,
4953 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4954 pbn_b0_bt_2_115200
},
4955 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_QUATTRO_A
,
4956 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4957 pbn_b0_bt_2_115200
},
4958 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_QUATTRO_B
,
4959 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4960 pbn_b0_bt_2_115200
},
4961 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_OCTO_A
,
4962 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4963 pbn_b0_bt_4_460800
},
4964 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_OCTO_B
,
4965 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4966 pbn_b0_bt_4_460800
},
4967 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_PORT_PLUS
,
4968 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4969 pbn_b0_bt_2_460800
},
4970 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_QUAD_A
,
4971 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4972 pbn_b0_bt_2_460800
},
4973 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_QUAD_B
,
4974 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4975 pbn_b0_bt_2_460800
},
4976 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_SSERIAL
,
4977 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4978 pbn_b0_bt_1_115200
},
4979 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_PORT_650
,
4980 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
4981 pbn_b0_bt_1_460800
},
4984 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4985 * Cards are identified by their subsystem vendor IDs, which
4986 * (in hex) match the model number.
4988 * Note that JC140x are RS422/485 cards which require ox950
4989 * ACR = 0x10, and as such are not currently fully supported.
4991 { PCI_VENDOR_ID_KORENIX
, PCI_DEVICE_ID_KORENIX_JETCARDF0
,
4992 0x1204, 0x0004, 0, 0,
4994 { PCI_VENDOR_ID_KORENIX
, PCI_DEVICE_ID_KORENIX_JETCARDF0
,
4995 0x1208, 0x0004, 0, 0,
4997 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4998 0x1402, 0x0002, 0, 0,
4999 pbn_b0_2_921600 }, */
5000 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5001 0x1404, 0x0004, 0, 0,
5002 pbn_b0_4_921600 }, */
5003 { PCI_VENDOR_ID_KORENIX
, PCI_DEVICE_ID_KORENIX_JETCARDF1
,
5004 0x1208, 0x0004, 0, 0,
5007 { PCI_VENDOR_ID_KORENIX
, PCI_DEVICE_ID_KORENIX_JETCARDF2
,
5008 0x1204, 0x0004, 0, 0,
5010 { PCI_VENDOR_ID_KORENIX
, PCI_DEVICE_ID_KORENIX_JETCARDF2
,
5011 0x1208, 0x0004, 0, 0,
5013 { PCI_VENDOR_ID_KORENIX
, PCI_DEVICE_ID_KORENIX_JETCARDF3
,
5014 0x1208, 0x0004, 0, 0,
5017 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
5019 { PCI_VENDOR_ID_DELL
, PCI_DEVICE_ID_DELL_RAC4
,
5020 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5024 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
5026 { PCI_VENDOR_ID_DELL
, PCI_DEVICE_ID_DELL_RACIII
,
5027 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5031 * RAStel 2 port modem, gerg@moreton.com.au
5033 { PCI_VENDOR_ID_MORETON
, PCI_DEVICE_ID_RASTEL_2PORT
,
5034 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5035 pbn_b2_bt_2_115200
},
5038 * EKF addition for i960 Boards form EKF with serial port
5040 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80960_RP
,
5041 0xE4BF, PCI_ANY_ID
, 0, 0,
5045 * Xircom Cardbus/Ethernet combos
5047 { PCI_VENDOR_ID_XIRCOM
, PCI_DEVICE_ID_XIRCOM_X3201_MDM
,
5048 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5051 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5053 { PCI_VENDOR_ID_XIRCOM
, PCI_DEVICE_ID_XIRCOM_RBM56G
,
5054 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5058 * Untested PCI modems, sent in from various folks...
5062 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5064 { PCI_VENDOR_ID_ROCKWELL
, 0x1004,
5065 0x1048, 0x1500, 0, 0,
5068 { PCI_VENDOR_ID_SGI
, PCI_DEVICE_ID_SGI_IOC3
,
5075 { PCI_VENDOR_ID_HP
, PCI_DEVICE_ID_HP_DIVA
,
5076 PCI_VENDOR_ID_HP
, PCI_DEVICE_ID_HP_DIVA_RMP3
, 0, 0,
5078 { PCI_VENDOR_ID_HP
, PCI_DEVICE_ID_HP_DIVA
,
5079 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5081 { PCI_VENDOR_ID_HP
, PCI_DEVICE_ID_HP_DIVA_AUX
,
5082 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5085 { PCI_VENDOR_ID_DCI
, PCI_DEVICE_ID_DCI_PCCOM2
,
5086 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5088 { PCI_VENDOR_ID_DCI
, PCI_DEVICE_ID_DCI_PCCOM4
,
5089 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5091 { PCI_VENDOR_ID_DCI
, PCI_DEVICE_ID_DCI_PCCOM8
,
5092 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5096 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
5098 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C152
,
5099 PCI_ANY_ID
, PCI_ANY_ID
,
5101 0, pbn_exar_XR17C152
},
5102 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C154
,
5103 PCI_ANY_ID
, PCI_ANY_ID
,
5105 0, pbn_exar_XR17C154
},
5106 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C158
,
5107 PCI_ANY_ID
, PCI_ANY_ID
,
5109 0, pbn_exar_XR17C158
},
5111 * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
5113 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17V352
,
5114 PCI_ANY_ID
, PCI_ANY_ID
,
5116 0, pbn_exar_XR17V352
},
5117 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17V354
,
5118 PCI_ANY_ID
, PCI_ANY_ID
,
5120 0, pbn_exar_XR17V354
},
5121 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17V358
,
5122 PCI_ANY_ID
, PCI_ANY_ID
,
5124 0, pbn_exar_XR17V358
},
5125 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17V4358
,
5126 PCI_ANY_ID
, PCI_ANY_ID
,
5128 0, pbn_exar_XR17V4358
},
5129 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17V8358
,
5130 PCI_ANY_ID
, PCI_ANY_ID
,
5132 0, pbn_exar_XR17V8358
},
5134 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
5136 { PCI_VENDOR_ID_PERICOM
, PCI_DEVICE_ID_PERICOM_PI7C9X7951
,
5137 PCI_ANY_ID
, PCI_ANY_ID
,
5139 0, pbn_pericom_PI7C9X7951
},
5140 { PCI_VENDOR_ID_PERICOM
, PCI_DEVICE_ID_PERICOM_PI7C9X7952
,
5141 PCI_ANY_ID
, PCI_ANY_ID
,
5143 0, pbn_pericom_PI7C9X7952
},
5144 { PCI_VENDOR_ID_PERICOM
, PCI_DEVICE_ID_PERICOM_PI7C9X7954
,
5145 PCI_ANY_ID
, PCI_ANY_ID
,
5147 0, pbn_pericom_PI7C9X7954
},
5148 { PCI_VENDOR_ID_PERICOM
, PCI_DEVICE_ID_PERICOM_PI7C9X7958
,
5149 PCI_ANY_ID
, PCI_ANY_ID
,
5151 0, pbn_pericom_PI7C9X7958
},
5153 * ACCES I/O Products quad
5155 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB
,
5156 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5157 pbn_pericom_PI7C9X7954
},
5158 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S
,
5159 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5160 pbn_pericom_PI7C9X7954
},
5161 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB
,
5162 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5163 pbn_pericom_PI7C9X7954
},
5164 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S
,
5165 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5166 pbn_pericom_PI7C9X7954
},
5167 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB
,
5168 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5169 pbn_pericom_PI7C9X7954
},
5170 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2
,
5171 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5172 pbn_pericom_PI7C9X7954
},
5173 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB
,
5174 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5175 pbn_pericom_PI7C9X7954
},
5176 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4
,
5177 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5178 pbn_pericom_PI7C9X7954
},
5179 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB
,
5180 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5181 pbn_pericom_PI7C9X7954
},
5182 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM
,
5183 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5184 pbn_pericom_PI7C9X7954
},
5185 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB
,
5186 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5187 pbn_pericom_PI7C9X7954
},
5188 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM
,
5189 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5190 pbn_pericom_PI7C9X7954
},
5191 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1
,
5192 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5193 pbn_pericom_PI7C9X7954
},
5194 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2
,
5195 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5196 pbn_pericom_PI7C9X7954
},
5197 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2
,
5198 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5199 pbn_pericom_PI7C9X7954
},
5200 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4
,
5201 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5202 pbn_pericom_PI7C9X7954
},
5203 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4
,
5204 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5205 pbn_pericom_PI7C9X7954
},
5206 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S
,
5207 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5208 pbn_pericom_PI7C9X7954
},
5209 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S
,
5210 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5211 pbn_pericom_PI7C9X7954
},
5212 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2
,
5213 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5214 pbn_pericom_PI7C9X7954
},
5215 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2
,
5216 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5217 pbn_pericom_PI7C9X7954
},
5218 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4
,
5219 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5220 pbn_pericom_PI7C9X7954
},
5221 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4
,
5222 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5223 pbn_pericom_PI7C9X7954
},
5224 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM
,
5225 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5226 pbn_pericom_PI7C9X7954
},
5227 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4
,
5228 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5229 pbn_pericom_PI7C9X7958
},
5230 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4
,
5231 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5232 pbn_pericom_PI7C9X7958
},
5233 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8
,
5234 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5235 pbn_pericom_PI7C9X7958
},
5236 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8
,
5237 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5238 pbn_pericom_PI7C9X7958
},
5239 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4
,
5240 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5241 pbn_pericom_PI7C9X7958
},
5242 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8
,
5243 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5244 pbn_pericom_PI7C9X7958
},
5245 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM
,
5246 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5247 pbn_pericom_PI7C9X7958
},
5248 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM
,
5249 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5250 pbn_pericom_PI7C9X7958
},
5251 { PCI_VENDOR_ID_ACCESIO
, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM
,
5252 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5253 pbn_pericom_PI7C9X7958
},
5255 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5257 { PCI_VENDOR_ID_TOPIC
, PCI_DEVICE_ID_TOPIC_TP560
,
5258 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5263 { PCI_VENDOR_ID_ITE
, PCI_DEVICE_ID_ITE_8872
,
5264 PCI_ANY_ID
, PCI_ANY_ID
,
5266 pbn_b1_bt_1_115200
},
5271 { PCI_VENDOR_ID_INTASHIELD
, PCI_DEVICE_ID_INTASHIELD_IS200
,
5272 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, /* 135a.0811 */
5277 { PCI_VENDOR_ID_INTASHIELD
, PCI_DEVICE_ID_INTASHIELD_IS400
,
5278 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, /* 135a.0dc0 */
5281 * Perle PCI-RAS cards
5283 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9030
,
5284 PCI_SUBVENDOR_ID_PERLE
, PCI_SUBDEVICE_ID_PCI_RAS4
,
5285 0, 0, pbn_b2_4_921600
},
5286 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9030
,
5287 PCI_SUBVENDOR_ID_PERLE
, PCI_SUBDEVICE_ID_PCI_RAS8
,
5288 0, 0, pbn_b2_8_921600
},
5291 * Mainpine series cards: Fairly standard layout but fools
5292 * parts of the autodetect in some cases and uses otherwise
5293 * unmatched communications subclasses in the PCI Express case
5296 { /* RockForceDUO */
5297 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5298 PCI_VENDOR_ID_MAINPINE
, 0x0200,
5299 0, 0, pbn_b0_2_115200
},
5300 { /* RockForceQUATRO */
5301 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5302 PCI_VENDOR_ID_MAINPINE
, 0x0300,
5303 0, 0, pbn_b0_4_115200
},
5304 { /* RockForceDUO+ */
5305 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5306 PCI_VENDOR_ID_MAINPINE
, 0x0400,
5307 0, 0, pbn_b0_2_115200
},
5308 { /* RockForceQUATRO+ */
5309 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5310 PCI_VENDOR_ID_MAINPINE
, 0x0500,
5311 0, 0, pbn_b0_4_115200
},
5313 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5314 PCI_VENDOR_ID_MAINPINE
, 0x0600,
5315 0, 0, pbn_b0_2_115200
},
5317 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5318 PCI_VENDOR_ID_MAINPINE
, 0x0700,
5319 0, 0, pbn_b0_4_115200
},
5320 { /* RockForceOCTO+ */
5321 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5322 PCI_VENDOR_ID_MAINPINE
, 0x0800,
5323 0, 0, pbn_b0_8_115200
},
5324 { /* RockForceDUO+ */
5325 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5326 PCI_VENDOR_ID_MAINPINE
, 0x0C00,
5327 0, 0, pbn_b0_2_115200
},
5328 { /* RockForceQUARTRO+ */
5329 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5330 PCI_VENDOR_ID_MAINPINE
, 0x0D00,
5331 0, 0, pbn_b0_4_115200
},
5332 { /* RockForceOCTO+ */
5333 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5334 PCI_VENDOR_ID_MAINPINE
, 0x1D00,
5335 0, 0, pbn_b0_8_115200
},
5337 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5338 PCI_VENDOR_ID_MAINPINE
, 0x2000,
5339 0, 0, pbn_b0_1_115200
},
5341 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5342 PCI_VENDOR_ID_MAINPINE
, 0x2100,
5343 0, 0, pbn_b0_1_115200
},
5345 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5346 PCI_VENDOR_ID_MAINPINE
, 0x2200,
5347 0, 0, pbn_b0_2_115200
},
5349 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5350 PCI_VENDOR_ID_MAINPINE
, 0x2300,
5351 0, 0, pbn_b0_2_115200
},
5353 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5354 PCI_VENDOR_ID_MAINPINE
, 0x2400,
5355 0, 0, pbn_b0_4_115200
},
5357 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5358 PCI_VENDOR_ID_MAINPINE
, 0x2500,
5359 0, 0, pbn_b0_4_115200
},
5361 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5362 PCI_VENDOR_ID_MAINPINE
, 0x2600,
5363 0, 0, pbn_b0_8_115200
},
5365 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5366 PCI_VENDOR_ID_MAINPINE
, 0x2700,
5367 0, 0, pbn_b0_8_115200
},
5368 { /* IQ Express D1 */
5369 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5370 PCI_VENDOR_ID_MAINPINE
, 0x3000,
5371 0, 0, pbn_b0_1_115200
},
5372 { /* IQ Express F1 */
5373 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5374 PCI_VENDOR_ID_MAINPINE
, 0x3100,
5375 0, 0, pbn_b0_1_115200
},
5376 { /* IQ Express D2 */
5377 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5378 PCI_VENDOR_ID_MAINPINE
, 0x3200,
5379 0, 0, pbn_b0_2_115200
},
5380 { /* IQ Express F2 */
5381 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5382 PCI_VENDOR_ID_MAINPINE
, 0x3300,
5383 0, 0, pbn_b0_2_115200
},
5384 { /* IQ Express D4 */
5385 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5386 PCI_VENDOR_ID_MAINPINE
, 0x3400,
5387 0, 0, pbn_b0_4_115200
},
5388 { /* IQ Express F4 */
5389 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5390 PCI_VENDOR_ID_MAINPINE
, 0x3500,
5391 0, 0, pbn_b0_4_115200
},
5392 { /* IQ Express D8 */
5393 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5394 PCI_VENDOR_ID_MAINPINE
, 0x3C00,
5395 0, 0, pbn_b0_8_115200
},
5396 { /* IQ Express F8 */
5397 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
5398 PCI_VENDOR_ID_MAINPINE
, 0x3D00,
5399 0, 0, pbn_b0_8_115200
},
5403 * PA Semi PA6T-1682M on-chip UART
5405 { PCI_VENDOR_ID_PASEMI
, 0xa004,
5406 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5410 * National Instruments
5412 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI23216
,
5413 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5415 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI2328
,
5416 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5418 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI2324
,
5419 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5420 pbn_b1_bt_4_115200
},
5421 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI2322
,
5422 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5423 pbn_b1_bt_2_115200
},
5424 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI2324I
,
5425 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5426 pbn_b1_bt_4_115200
},
5427 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI2322I
,
5428 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5429 pbn_b1_bt_2_115200
},
5430 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8420_23216
,
5431 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5433 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8420_2328
,
5434 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5436 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8420_2324
,
5437 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5438 pbn_b1_bt_4_115200
},
5439 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8420_2322
,
5440 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5441 pbn_b1_bt_2_115200
},
5442 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8422_2324
,
5443 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5444 pbn_b1_bt_4_115200
},
5445 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8422_2322
,
5446 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5447 pbn_b1_bt_2_115200
},
5448 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8430_2322
,
5449 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5451 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI8430_2322
,
5452 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5454 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8430_2324
,
5455 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5457 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI8430_2324
,
5458 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5460 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8430_2328
,
5461 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5463 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI8430_2328
,
5464 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5466 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8430_23216
,
5467 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5469 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI8430_23216
,
5470 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5472 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8432_2322
,
5473 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5475 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI8432_2322
,
5476 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5478 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8432_2324
,
5479 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5481 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI8432_2324
,
5482 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5486 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5488 { PCI_VENDOR_ID_ADDIDATA
,
5489 PCI_DEVICE_ID_ADDIDATA_APCI7500
,
5496 { PCI_VENDOR_ID_ADDIDATA
,
5497 PCI_DEVICE_ID_ADDIDATA_APCI7420
,
5504 { PCI_VENDOR_ID_ADDIDATA
,
5505 PCI_DEVICE_ID_ADDIDATA_APCI7300
,
5512 { PCI_VENDOR_ID_AMCC
,
5513 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800
,
5520 { PCI_VENDOR_ID_ADDIDATA
,
5521 PCI_DEVICE_ID_ADDIDATA_APCI7500_2
,
5528 { PCI_VENDOR_ID_ADDIDATA
,
5529 PCI_DEVICE_ID_ADDIDATA_APCI7420_2
,
5536 { PCI_VENDOR_ID_ADDIDATA
,
5537 PCI_DEVICE_ID_ADDIDATA_APCI7300_2
,
5544 { PCI_VENDOR_ID_ADDIDATA
,
5545 PCI_DEVICE_ID_ADDIDATA_APCI7500_3
,
5552 { PCI_VENDOR_ID_ADDIDATA
,
5553 PCI_DEVICE_ID_ADDIDATA_APCI7420_3
,
5560 { PCI_VENDOR_ID_ADDIDATA
,
5561 PCI_DEVICE_ID_ADDIDATA_APCI7300_3
,
5568 { PCI_VENDOR_ID_ADDIDATA
,
5569 PCI_DEVICE_ID_ADDIDATA_APCI7800_3
,
5576 { PCI_VENDOR_ID_ADDIDATA
,
5577 PCI_DEVICE_ID_ADDIDATA_APCIe7500
,
5582 pbn_ADDIDATA_PCIe_4_3906250
},
5584 { PCI_VENDOR_ID_ADDIDATA
,
5585 PCI_DEVICE_ID_ADDIDATA_APCIe7420
,
5590 pbn_ADDIDATA_PCIe_2_3906250
},
5592 { PCI_VENDOR_ID_ADDIDATA
,
5593 PCI_DEVICE_ID_ADDIDATA_APCIe7300
,
5598 pbn_ADDIDATA_PCIe_1_3906250
},
5600 { PCI_VENDOR_ID_ADDIDATA
,
5601 PCI_DEVICE_ID_ADDIDATA_APCIe7800
,
5606 pbn_ADDIDATA_PCIe_8_3906250
},
5608 { PCI_VENDOR_ID_NETMOS
, PCI_DEVICE_ID_NETMOS_9835
,
5609 PCI_VENDOR_ID_IBM
, 0x0299,
5610 0, 0, pbn_b0_bt_2_115200
},
5613 * other NetMos 9835 devices are most likely handled by the
5614 * parport_serial driver, check drivers/parport/parport_serial.c
5615 * before adding them here.
5618 { PCI_VENDOR_ID_NETMOS
, PCI_DEVICE_ID_NETMOS_9901
,
5620 0, 0, pbn_b0_1_115200
},
5622 /* the 9901 is a rebranded 9912 */
5623 { PCI_VENDOR_ID_NETMOS
, PCI_DEVICE_ID_NETMOS_9912
,
5625 0, 0, pbn_b0_1_115200
},
5627 { PCI_VENDOR_ID_NETMOS
, PCI_DEVICE_ID_NETMOS_9922
,
5629 0, 0, pbn_b0_1_115200
},
5631 { PCI_VENDOR_ID_NETMOS
, PCI_DEVICE_ID_NETMOS_9904
,
5633 0, 0, pbn_b0_1_115200
},
5635 { PCI_VENDOR_ID_NETMOS
, PCI_DEVICE_ID_NETMOS_9900
,
5637 0, 0, pbn_b0_1_115200
},
5639 { PCI_VENDOR_ID_NETMOS
, PCI_DEVICE_ID_NETMOS_9900
,
5641 0, 0, pbn_NETMOS9900_2s_115200
},
5644 * Best Connectivity and Rosewill PCI Multi I/O cards
5647 { PCI_VENDOR_ID_NETMOS
, PCI_DEVICE_ID_NETMOS_9865
,
5649 0, 0, pbn_b0_1_115200
},
5651 { PCI_VENDOR_ID_NETMOS
, PCI_DEVICE_ID_NETMOS_9865
,
5653 0, 0, pbn_b0_bt_2_115200
},
5655 { PCI_VENDOR_ID_NETMOS
, PCI_DEVICE_ID_NETMOS_9865
,
5657 0, 0, pbn_b0_bt_4_115200
},
5659 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_CE4100_UART
,
5660 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5661 pbn_ce4100_1_115200
},
5662 /* Intel BayTrail */
5663 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_BYT_UART1
,
5664 PCI_ANY_ID
, PCI_ANY_ID
,
5665 PCI_CLASS_COMMUNICATION_SERIAL
<< 8, 0xff0000,
5667 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_BYT_UART2
,
5668 PCI_ANY_ID
, PCI_ANY_ID
,
5669 PCI_CLASS_COMMUNICATION_SERIAL
<< 8, 0xff0000,
5671 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_BSW_UART1
,
5672 PCI_ANY_ID
, PCI_ANY_ID
,
5673 PCI_CLASS_COMMUNICATION_SERIAL
<< 8, 0xff0000,
5675 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_BSW_UART2
,
5676 PCI_ANY_ID
, PCI_ANY_ID
,
5677 PCI_CLASS_COMMUNICATION_SERIAL
<< 8, 0xff0000,
5680 /* Intel Broadwell */
5681 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_BDW_UART1
,
5682 PCI_ANY_ID
, PCI_ANY_ID
,
5683 PCI_CLASS_COMMUNICATION_SERIAL
<< 8, 0xff0000,
5685 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_BDW_UART2
,
5686 PCI_ANY_ID
, PCI_ANY_ID
,
5687 PCI_CLASS_COMMUNICATION_SERIAL
<< 8, 0xff0000,
5693 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_QRK_UART
,
5694 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5699 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_CRONYX_OMEGA
,
5700 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5704 * Broadcom TruManage
5706 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_BROADCOM_TRUMANAGE
,
5707 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
5708 pbn_brcm_trumanage
},
5711 * AgeStar as-prs2-009
5713 { PCI_VENDOR_ID_AGESTAR
, PCI_DEVICE_ID_AGESTAR_9375
,
5714 PCI_ANY_ID
, PCI_ANY_ID
,
5715 0, 0, pbn_b0_bt_2_115200
},
5718 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5719 * so not listed here.
5721 { PCI_VENDOR_ID_WCH
, PCI_DEVICE_ID_WCH_CH353_4S
,
5722 PCI_ANY_ID
, PCI_ANY_ID
,
5723 0, 0, pbn_b0_bt_4_115200
},
5725 { PCI_VENDOR_ID_WCH
, PCI_DEVICE_ID_WCH_CH353_2S1PF
,
5726 PCI_ANY_ID
, PCI_ANY_ID
,
5727 0, 0, pbn_b0_bt_2_115200
},
5729 { PCI_VENDOR_ID_WCH
, PCI_DEVICE_ID_WCH_CH355_4S
,
5730 PCI_ANY_ID
, PCI_ANY_ID
,
5731 0, 0, pbn_b0_bt_4_115200
},
5733 { PCIE_VENDOR_ID_WCH
, PCIE_DEVICE_ID_WCH_CH382_2S
,
5734 PCI_ANY_ID
, PCI_ANY_ID
,
5735 0, 0, pbn_wch382_2
},
5737 { PCIE_VENDOR_ID_WCH
, PCIE_DEVICE_ID_WCH_CH384_4S
,
5738 PCI_ANY_ID
, PCI_ANY_ID
,
5739 0, 0, pbn_wch384_4
},
5742 * Commtech, Inc. Fastcom adapters
5744 { PCI_VENDOR_ID_COMMTECH
, PCI_DEVICE_ID_COMMTECH_4222PCI335
,
5745 PCI_ANY_ID
, PCI_ANY_ID
,
5747 0, pbn_b0_2_1152000_200
},
5748 { PCI_VENDOR_ID_COMMTECH
, PCI_DEVICE_ID_COMMTECH_4224PCI335
,
5749 PCI_ANY_ID
, PCI_ANY_ID
,
5751 0, pbn_b0_4_1152000_200
},
5752 { PCI_VENDOR_ID_COMMTECH
, PCI_DEVICE_ID_COMMTECH_2324PCI335
,
5753 PCI_ANY_ID
, PCI_ANY_ID
,
5755 0, pbn_b0_4_1152000_200
},
5756 { PCI_VENDOR_ID_COMMTECH
, PCI_DEVICE_ID_COMMTECH_2328PCI335
,
5757 PCI_ANY_ID
, PCI_ANY_ID
,
5759 0, pbn_b0_8_1152000_200
},
5760 { PCI_VENDOR_ID_COMMTECH
, PCI_DEVICE_ID_COMMTECH_4222PCIE
,
5761 PCI_ANY_ID
, PCI_ANY_ID
,
5763 0, pbn_exar_XR17V352
},
5764 { PCI_VENDOR_ID_COMMTECH
, PCI_DEVICE_ID_COMMTECH_4224PCIE
,
5765 PCI_ANY_ID
, PCI_ANY_ID
,
5767 0, pbn_exar_XR17V354
},
5768 { PCI_VENDOR_ID_COMMTECH
, PCI_DEVICE_ID_COMMTECH_4228PCIE
,
5769 PCI_ANY_ID
, PCI_ANY_ID
,
5771 0, pbn_exar_XR17V358
},
5773 /* Fintek PCI serial cards */
5774 { PCI_DEVICE(0x1c29, 0x1104), .driver_data
= pbn_fintek_4
},
5775 { PCI_DEVICE(0x1c29, 0x1108), .driver_data
= pbn_fintek_8
},
5776 { PCI_DEVICE(0x1c29, 0x1112), .driver_data
= pbn_fintek_12
},
5779 * These entries match devices with class COMMUNICATION_SERIAL,
5780 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5782 { PCI_ANY_ID
, PCI_ANY_ID
,
5783 PCI_ANY_ID
, PCI_ANY_ID
,
5784 PCI_CLASS_COMMUNICATION_SERIAL
<< 8,
5785 0xffff00, pbn_default
},
5786 { PCI_ANY_ID
, PCI_ANY_ID
,
5787 PCI_ANY_ID
, PCI_ANY_ID
,
5788 PCI_CLASS_COMMUNICATION_MODEM
<< 8,
5789 0xffff00, pbn_default
},
5790 { PCI_ANY_ID
, PCI_ANY_ID
,
5791 PCI_ANY_ID
, PCI_ANY_ID
,
5792 PCI_CLASS_COMMUNICATION_MULTISERIAL
<< 8,
5793 0xffff00, pbn_default
},
5797 static pci_ers_result_t
serial8250_io_error_detected(struct pci_dev
*dev
,
5798 pci_channel_state_t state
)
5800 struct serial_private
*priv
= pci_get_drvdata(dev
);
5802 if (state
== pci_channel_io_perm_failure
)
5803 return PCI_ERS_RESULT_DISCONNECT
;
5806 pciserial_suspend_ports(priv
);
5808 pci_disable_device(dev
);
5810 return PCI_ERS_RESULT_NEED_RESET
;
5813 static pci_ers_result_t
serial8250_io_slot_reset(struct pci_dev
*dev
)
5817 rc
= pci_enable_device(dev
);
5820 return PCI_ERS_RESULT_DISCONNECT
;
5822 pci_restore_state(dev
);
5823 pci_save_state(dev
);
5825 return PCI_ERS_RESULT_RECOVERED
;
5828 static void serial8250_io_resume(struct pci_dev
*dev
)
5830 struct serial_private
*priv
= pci_get_drvdata(dev
);
5833 pciserial_resume_ports(priv
);
5836 static const struct pci_error_handlers serial8250_err_handler
= {
5837 .error_detected
= serial8250_io_error_detected
,
5838 .slot_reset
= serial8250_io_slot_reset
,
5839 .resume
= serial8250_io_resume
,
5842 static struct pci_driver serial_pci_driver
= {
5844 .probe
= pciserial_init_one
,
5845 .remove
= pciserial_remove_one
,
5847 .pm
= &pciserial_pm_ops
,
5849 .id_table
= serial_pci_tbl
,
5850 .err_handler
= &serial8250_err_handler
,
5853 module_pci_driver(serial_pci_driver
);
5855 MODULE_LICENSE("GPL");
5856 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5857 MODULE_DEVICE_TABLE(pci
, serial_pci_tbl
);