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UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / 8250 / 8250_pci.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type PCI serial ports.
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 */
9 #undef DEBUG
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/string.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/delay.h>
16 #include <linux/tty.h>
17 #include <linux/serial_reg.h>
18 #include <linux/serial_core.h>
19 #include <linux/8250_pci.h>
20 #include <linux/bitops.h>
21
22 #include <asm/byteorder.h>
23 #include <asm/io.h>
24
25 #include "8250.h"
26
27 /*
28 * init function returns:
29 * > 0 - number of ports
30 * = 0 - use board->num_ports
31 * < 0 - error
32 */
33 struct pci_serial_quirk {
34 u32 vendor;
35 u32 device;
36 u32 subvendor;
37 u32 subdevice;
38 int (*probe)(struct pci_dev *dev);
39 int (*init)(struct pci_dev *dev);
40 int (*setup)(struct serial_private *,
41 const struct pciserial_board *,
42 struct uart_8250_port *, int);
43 void (*exit)(struct pci_dev *dev);
44 };
45
46 #define PCI_NUM_BAR_RESOURCES 6
47
48 struct serial_private {
49 struct pci_dev *dev;
50 unsigned int nr;
51 struct pci_serial_quirk *quirk;
52 const struct pciserial_board *board;
53 int line[0];
54 };
55
56 static int pci_default_setup(struct serial_private*,
57 const struct pciserial_board*, struct uart_8250_port *, int);
58
59 static void moan_device(const char *str, struct pci_dev *dev)
60 {
61 dev_err(&dev->dev,
62 "%s: %s\n"
63 "Please send the output of lspci -vv, this\n"
64 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
65 "manufacturer and name of serial board or\n"
66 "modem board to <linux-serial@vger.kernel.org>.\n",
67 pci_name(dev), str, dev->vendor, dev->device,
68 dev->subsystem_vendor, dev->subsystem_device);
69 }
70
71 static int
72 setup_port(struct serial_private *priv, struct uart_8250_port *port,
73 int bar, int offset, int regshift)
74 {
75 struct pci_dev *dev = priv->dev;
76
77 if (bar >= PCI_NUM_BAR_RESOURCES)
78 return -EINVAL;
79
80 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
81 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
82 return -ENOMEM;
83
84 port->port.iotype = UPIO_MEM;
85 port->port.iobase = 0;
86 port->port.mapbase = pci_resource_start(dev, bar) + offset;
87 port->port.membase = pcim_iomap_table(dev)[bar] + offset;
88 port->port.regshift = regshift;
89 } else {
90 port->port.iotype = UPIO_PORT;
91 port->port.iobase = pci_resource_start(dev, bar) + offset;
92 port->port.mapbase = 0;
93 port->port.membase = NULL;
94 port->port.regshift = 0;
95 }
96 return 0;
97 }
98
99 /*
100 * ADDI-DATA GmbH communication cards <info@addi-data.com>
101 */
102 static int addidata_apci7800_setup(struct serial_private *priv,
103 const struct pciserial_board *board,
104 struct uart_8250_port *port, int idx)
105 {
106 unsigned int bar = 0, offset = board->first_offset;
107 bar = FL_GET_BASE(board->flags);
108
109 if (idx < 2) {
110 offset += idx * board->uart_offset;
111 } else if ((idx >= 2) && (idx < 4)) {
112 bar += 1;
113 offset += ((idx - 2) * board->uart_offset);
114 } else if ((idx >= 4) && (idx < 6)) {
115 bar += 2;
116 offset += ((idx - 4) * board->uart_offset);
117 } else if (idx >= 6) {
118 bar += 3;
119 offset += ((idx - 6) * board->uart_offset);
120 }
121
122 return setup_port(priv, port, bar, offset, board->reg_shift);
123 }
124
125 /*
126 * AFAVLAB uses a different mixture of BARs and offsets
127 * Not that ugly ;) -- HW
128 */
129 static int
130 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
131 struct uart_8250_port *port, int idx)
132 {
133 unsigned int bar, offset = board->first_offset;
134
135 bar = FL_GET_BASE(board->flags);
136 if (idx < 4)
137 bar += idx;
138 else {
139 bar = 4;
140 offset += (idx - 4) * board->uart_offset;
141 }
142
143 return setup_port(priv, port, bar, offset, board->reg_shift);
144 }
145
146 /*
147 * HP's Remote Management Console. The Diva chip came in several
148 * different versions. N-class, L2000 and A500 have two Diva chips, each
149 * with 3 UARTs (the third UART on the second chip is unused). Superdome
150 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
151 * one Diva chip, but it has been expanded to 5 UARTs.
152 */
153 static int pci_hp_diva_init(struct pci_dev *dev)
154 {
155 int rc = 0;
156
157 switch (dev->subsystem_device) {
158 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
159 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
160 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
161 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
162 rc = 3;
163 break;
164 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
165 rc = 2;
166 break;
167 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
168 rc = 4;
169 break;
170 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
171 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
172 rc = 1;
173 break;
174 }
175
176 return rc;
177 }
178
179 /*
180 * HP's Diva chip puts the 4th/5th serial port further out, and
181 * some serial ports are supposed to be hidden on certain models.
182 */
183 static int
184 pci_hp_diva_setup(struct serial_private *priv,
185 const struct pciserial_board *board,
186 struct uart_8250_port *port, int idx)
187 {
188 unsigned int offset = board->first_offset;
189 unsigned int bar = FL_GET_BASE(board->flags);
190
191 switch (priv->dev->subsystem_device) {
192 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
193 if (idx == 3)
194 idx++;
195 break;
196 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
197 if (idx > 0)
198 idx++;
199 if (idx > 2)
200 idx++;
201 break;
202 }
203 if (idx > 2)
204 offset = 0x18;
205
206 offset += idx * board->uart_offset;
207
208 return setup_port(priv, port, bar, offset, board->reg_shift);
209 }
210
211 /*
212 * Added for EKF Intel i960 serial boards
213 */
214 static int pci_inteli960ni_init(struct pci_dev *dev)
215 {
216 u32 oldval;
217
218 if (!(dev->subsystem_device & 0x1000))
219 return -ENODEV;
220
221 /* is firmware started? */
222 pci_read_config_dword(dev, 0x44, &oldval);
223 if (oldval == 0x00001000L) { /* RESET value */
224 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
225 return -ENODEV;
226 }
227 return 0;
228 }
229
230 /*
231 * Some PCI serial cards using the PLX 9050 PCI interface chip require
232 * that the card interrupt be explicitly enabled or disabled. This
233 * seems to be mainly needed on card using the PLX which also use I/O
234 * mapped memory.
235 */
236 static int pci_plx9050_init(struct pci_dev *dev)
237 {
238 u8 irq_config;
239 void __iomem *p;
240
241 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
242 moan_device("no memory in bar 0", dev);
243 return 0;
244 }
245
246 irq_config = 0x41;
247 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
248 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
249 irq_config = 0x43;
250
251 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
252 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
253 /*
254 * As the megawolf cards have the int pins active
255 * high, and have 2 UART chips, both ints must be
256 * enabled on the 9050. Also, the UARTS are set in
257 * 16450 mode by default, so we have to enable the
258 * 16C950 'enhanced' mode so that we can use the
259 * deep FIFOs
260 */
261 irq_config = 0x5b;
262 /*
263 * enable/disable interrupts
264 */
265 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
266 if (p == NULL)
267 return -ENOMEM;
268 writel(irq_config, p + 0x4c);
269
270 /*
271 * Read the register back to ensure that it took effect.
272 */
273 readl(p + 0x4c);
274 iounmap(p);
275
276 return 0;
277 }
278
279 static void pci_plx9050_exit(struct pci_dev *dev)
280 {
281 u8 __iomem *p;
282
283 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
284 return;
285
286 /*
287 * disable interrupts
288 */
289 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
290 if (p != NULL) {
291 writel(0, p + 0x4c);
292
293 /*
294 * Read the register back to ensure that it took effect.
295 */
296 readl(p + 0x4c);
297 iounmap(p);
298 }
299 }
300
301 #define NI8420_INT_ENABLE_REG 0x38
302 #define NI8420_INT_ENABLE_BIT 0x2000
303
304 static void pci_ni8420_exit(struct pci_dev *dev)
305 {
306 void __iomem *p;
307 unsigned int bar = 0;
308
309 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
310 moan_device("no memory in bar", dev);
311 return;
312 }
313
314 p = pci_ioremap_bar(dev, bar);
315 if (p == NULL)
316 return;
317
318 /* Disable the CPU Interrupt */
319 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
320 p + NI8420_INT_ENABLE_REG);
321 iounmap(p);
322 }
323
324
325 /* MITE registers */
326 #define MITE_IOWBSR1 0xc4
327 #define MITE_IOWCR1 0xf4
328 #define MITE_LCIMR1 0x08
329 #define MITE_LCIMR2 0x10
330
331 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
332
333 static void pci_ni8430_exit(struct pci_dev *dev)
334 {
335 void __iomem *p;
336 unsigned int bar = 0;
337
338 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
339 moan_device("no memory in bar", dev);
340 return;
341 }
342
343 p = pci_ioremap_bar(dev, bar);
344 if (p == NULL)
345 return;
346
347 /* Disable the CPU Interrupt */
348 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
349 iounmap(p);
350 }
351
352 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
353 static int
354 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
355 struct uart_8250_port *port, int idx)
356 {
357 unsigned int bar, offset = board->first_offset;
358
359 bar = 0;
360
361 if (idx < 4) {
362 /* first four channels map to 0, 0x100, 0x200, 0x300 */
363 offset += idx * board->uart_offset;
364 } else if (idx < 8) {
365 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
366 offset += idx * board->uart_offset + 0xC00;
367 } else /* we have only 8 ports on PMC-OCTALPRO */
368 return 1;
369
370 return setup_port(priv, port, bar, offset, board->reg_shift);
371 }
372
373 /*
374 * This does initialization for PMC OCTALPRO cards:
375 * maps the device memory, resets the UARTs (needed, bc
376 * if the module is removed and inserted again, the card
377 * is in the sleep mode) and enables global interrupt.
378 */
379
380 /* global control register offset for SBS PMC-OctalPro */
381 #define OCT_REG_CR_OFF 0x500
382
383 static int sbs_init(struct pci_dev *dev)
384 {
385 u8 __iomem *p;
386
387 p = pci_ioremap_bar(dev, 0);
388
389 if (p == NULL)
390 return -ENOMEM;
391 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
392 writeb(0x10, p + OCT_REG_CR_OFF);
393 udelay(50);
394 writeb(0x0, p + OCT_REG_CR_OFF);
395
396 /* Set bit-2 (INTENABLE) of Control Register */
397 writeb(0x4, p + OCT_REG_CR_OFF);
398 iounmap(p);
399
400 return 0;
401 }
402
403 /*
404 * Disables the global interrupt of PMC-OctalPro
405 */
406
407 static void sbs_exit(struct pci_dev *dev)
408 {
409 u8 __iomem *p;
410
411 p = pci_ioremap_bar(dev, 0);
412 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
413 if (p != NULL)
414 writeb(0, p + OCT_REG_CR_OFF);
415 iounmap(p);
416 }
417
418 /*
419 * SIIG serial cards have an PCI interface chip which also controls
420 * the UART clocking frequency. Each UART can be clocked independently
421 * (except cards equipped with 4 UARTs) and initial clocking settings
422 * are stored in the EEPROM chip. It can cause problems because this
423 * version of serial driver doesn't support differently clocked UART's
424 * on single PCI card. To prevent this, initialization functions set
425 * high frequency clocking for all UART's on given card. It is safe (I
426 * hope) because it doesn't touch EEPROM settings to prevent conflicts
427 * with other OSes (like M$ DOS).
428 *
429 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
430 *
431 * There is two family of SIIG serial cards with different PCI
432 * interface chip and different configuration methods:
433 * - 10x cards have control registers in IO and/or memory space;
434 * - 20x cards have control registers in standard PCI configuration space.
435 *
436 * Note: all 10x cards have PCI device ids 0x10..
437 * all 20x cards have PCI device ids 0x20..
438 *
439 * There are also Quartet Serial cards which use Oxford Semiconductor
440 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
441 *
442 * Note: some SIIG cards are probed by the parport_serial object.
443 */
444
445 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
446 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
447
448 static int pci_siig10x_init(struct pci_dev *dev)
449 {
450 u16 data;
451 void __iomem *p;
452
453 switch (dev->device & 0xfff8) {
454 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
455 data = 0xffdf;
456 break;
457 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
458 data = 0xf7ff;
459 break;
460 default: /* 1S1P, 4S */
461 data = 0xfffb;
462 break;
463 }
464
465 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
466 if (p == NULL)
467 return -ENOMEM;
468
469 writew(readw(p + 0x28) & data, p + 0x28);
470 readw(p + 0x28);
471 iounmap(p);
472 return 0;
473 }
474
475 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
476 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
477
478 static int pci_siig20x_init(struct pci_dev *dev)
479 {
480 u8 data;
481
482 /* Change clock frequency for the first UART. */
483 pci_read_config_byte(dev, 0x6f, &data);
484 pci_write_config_byte(dev, 0x6f, data & 0xef);
485
486 /* If this card has 2 UART, we have to do the same with second UART. */
487 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
488 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
489 pci_read_config_byte(dev, 0x73, &data);
490 pci_write_config_byte(dev, 0x73, data & 0xef);
491 }
492 return 0;
493 }
494
495 static int pci_siig_init(struct pci_dev *dev)
496 {
497 unsigned int type = dev->device & 0xff00;
498
499 if (type == 0x1000)
500 return pci_siig10x_init(dev);
501 else if (type == 0x2000)
502 return pci_siig20x_init(dev);
503
504 moan_device("Unknown SIIG card", dev);
505 return -ENODEV;
506 }
507
508 static int pci_siig_setup(struct serial_private *priv,
509 const struct pciserial_board *board,
510 struct uart_8250_port *port, int idx)
511 {
512 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
513
514 if (idx > 3) {
515 bar = 4;
516 offset = (idx - 4) * 8;
517 }
518
519 return setup_port(priv, port, bar, offset, 0);
520 }
521
522 /*
523 * Timedia has an explosion of boards, and to avoid the PCI table from
524 * growing *huge*, we use this function to collapse some 70 entries
525 * in the PCI table into one, for sanity's and compactness's sake.
526 */
527 static const unsigned short timedia_single_port[] = {
528 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
529 };
530
531 static const unsigned short timedia_dual_port[] = {
532 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
533 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
534 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
535 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
536 0xD079, 0
537 };
538
539 static const unsigned short timedia_quad_port[] = {
540 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
541 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
542 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
543 0xB157, 0
544 };
545
546 static const unsigned short timedia_eight_port[] = {
547 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
548 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
549 };
550
551 static const struct timedia_struct {
552 int num;
553 const unsigned short *ids;
554 } timedia_data[] = {
555 { 1, timedia_single_port },
556 { 2, timedia_dual_port },
557 { 4, timedia_quad_port },
558 { 8, timedia_eight_port }
559 };
560
561 /*
562 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
563 * listing them individually, this driver merely grabs them all with
564 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
565 * and should be left free to be claimed by parport_serial instead.
566 */
567 static int pci_timedia_probe(struct pci_dev *dev)
568 {
569 /*
570 * Check the third digit of the subdevice ID
571 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
572 */
573 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
574 dev_info(&dev->dev,
575 "ignoring Timedia subdevice %04x for parport_serial\n",
576 dev->subsystem_device);
577 return -ENODEV;
578 }
579
580 return 0;
581 }
582
583 static int pci_timedia_init(struct pci_dev *dev)
584 {
585 const unsigned short *ids;
586 int i, j;
587
588 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
589 ids = timedia_data[i].ids;
590 for (j = 0; ids[j]; j++)
591 if (dev->subsystem_device == ids[j])
592 return timedia_data[i].num;
593 }
594 return 0;
595 }
596
597 /*
598 * Timedia/SUNIX uses a mixture of BARs and offsets
599 * Ugh, this is ugly as all hell --- TYT
600 */
601 static int
602 pci_timedia_setup(struct serial_private *priv,
603 const struct pciserial_board *board,
604 struct uart_8250_port *port, int idx)
605 {
606 unsigned int bar = 0, offset = board->first_offset;
607
608 switch (idx) {
609 case 0:
610 bar = 0;
611 break;
612 case 1:
613 offset = board->uart_offset;
614 bar = 0;
615 break;
616 case 2:
617 bar = 1;
618 break;
619 case 3:
620 offset = board->uart_offset;
621 /* FALLTHROUGH */
622 case 4: /* BAR 2 */
623 case 5: /* BAR 3 */
624 case 6: /* BAR 4 */
625 case 7: /* BAR 5 */
626 bar = idx - 2;
627 }
628
629 return setup_port(priv, port, bar, offset, board->reg_shift);
630 }
631
632 /*
633 * Some Titan cards are also a little weird
634 */
635 static int
636 titan_400l_800l_setup(struct serial_private *priv,
637 const struct pciserial_board *board,
638 struct uart_8250_port *port, int idx)
639 {
640 unsigned int bar, offset = board->first_offset;
641
642 switch (idx) {
643 case 0:
644 bar = 1;
645 break;
646 case 1:
647 bar = 2;
648 break;
649 default:
650 bar = 4;
651 offset = (idx - 2) * board->uart_offset;
652 }
653
654 return setup_port(priv, port, bar, offset, board->reg_shift);
655 }
656
657 static int pci_xircom_init(struct pci_dev *dev)
658 {
659 msleep(100);
660 return 0;
661 }
662
663 static int pci_ni8420_init(struct pci_dev *dev)
664 {
665 void __iomem *p;
666 unsigned int bar = 0;
667
668 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
669 moan_device("no memory in bar", dev);
670 return 0;
671 }
672
673 p = pci_ioremap_bar(dev, bar);
674 if (p == NULL)
675 return -ENOMEM;
676
677 /* Enable CPU Interrupt */
678 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
679 p + NI8420_INT_ENABLE_REG);
680
681 iounmap(p);
682 return 0;
683 }
684
685 #define MITE_IOWBSR1_WSIZE 0xa
686 #define MITE_IOWBSR1_WIN_OFFSET 0x800
687 #define MITE_IOWBSR1_WENAB (1 << 7)
688 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
689 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
690 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
691
692 static int pci_ni8430_init(struct pci_dev *dev)
693 {
694 void __iomem *p;
695 struct pci_bus_region region;
696 u32 device_window;
697 unsigned int bar = 0;
698
699 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
700 moan_device("no memory in bar", dev);
701 return 0;
702 }
703
704 p = pci_ioremap_bar(dev, bar);
705 if (p == NULL)
706 return -ENOMEM;
707
708 /*
709 * Set device window address and size in BAR0, while acknowledging that
710 * the resource structure may contain a translated address that differs
711 * from the address the device responds to.
712 */
713 pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
714 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
715 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
716 writel(device_window, p + MITE_IOWBSR1);
717
718 /* Set window access to go to RAMSEL IO address space */
719 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
720 p + MITE_IOWCR1);
721
722 /* Enable IO Bus Interrupt 0 */
723 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
724
725 /* Enable CPU Interrupt */
726 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
727
728 iounmap(p);
729 return 0;
730 }
731
732 /* UART Port Control Register */
733 #define NI8430_PORTCON 0x0f
734 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
735
736 static int
737 pci_ni8430_setup(struct serial_private *priv,
738 const struct pciserial_board *board,
739 struct uart_8250_port *port, int idx)
740 {
741 struct pci_dev *dev = priv->dev;
742 void __iomem *p;
743 unsigned int bar, offset = board->first_offset;
744
745 if (idx >= board->num_ports)
746 return 1;
747
748 bar = FL_GET_BASE(board->flags);
749 offset += idx * board->uart_offset;
750
751 p = pci_ioremap_bar(dev, bar);
752 if (!p)
753 return -ENOMEM;
754
755 /* enable the transceiver */
756 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
757 p + offset + NI8430_PORTCON);
758
759 iounmap(p);
760
761 return setup_port(priv, port, bar, offset, board->reg_shift);
762 }
763
764 static int pci_netmos_9900_setup(struct serial_private *priv,
765 const struct pciserial_board *board,
766 struct uart_8250_port *port, int idx)
767 {
768 unsigned int bar;
769
770 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
771 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
772 /* netmos apparently orders BARs by datasheet layout, so serial
773 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
774 */
775 bar = 3 * idx;
776
777 return setup_port(priv, port, bar, 0, board->reg_shift);
778 } else {
779 return pci_default_setup(priv, board, port, idx);
780 }
781 }
782
783 /* the 99xx series comes with a range of device IDs and a variety
784 * of capabilities:
785 *
786 * 9900 has varying capabilities and can cascade to sub-controllers
787 * (cascading should be purely internal)
788 * 9904 is hardwired with 4 serial ports
789 * 9912 and 9922 are hardwired with 2 serial ports
790 */
791 static int pci_netmos_9900_numports(struct pci_dev *dev)
792 {
793 unsigned int c = dev->class;
794 unsigned int pi;
795 unsigned short sub_serports;
796
797 pi = c & 0xff;
798
799 if (pi == 2)
800 return 1;
801
802 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
803 /* two possibilities: 0x30ps encodes number of parallel and
804 * serial ports, or 0x1000 indicates *something*. This is not
805 * immediately obvious, since the 2s1p+4s configuration seems
806 * to offer all functionality on functions 0..2, while still
807 * advertising the same function 3 as the 4s+2s1p config.
808 */
809 sub_serports = dev->subsystem_device & 0xf;
810 if (sub_serports > 0)
811 return sub_serports;
812
813 dev_err(&dev->dev,
814 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
815 return 0;
816 }
817
818 moan_device("unknown NetMos/Mostech program interface", dev);
819 return 0;
820 }
821
822 static int pci_netmos_init(struct pci_dev *dev)
823 {
824 /* subdevice 0x00PS means <P> parallel, <S> serial */
825 unsigned int num_serial = dev->subsystem_device & 0xf;
826
827 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
828 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
829 return 0;
830
831 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
832 dev->subsystem_device == 0x0299)
833 return 0;
834
835 switch (dev->device) { /* FALLTHROUGH on all */
836 case PCI_DEVICE_ID_NETMOS_9904:
837 case PCI_DEVICE_ID_NETMOS_9912:
838 case PCI_DEVICE_ID_NETMOS_9922:
839 case PCI_DEVICE_ID_NETMOS_9900:
840 num_serial = pci_netmos_9900_numports(dev);
841 break;
842
843 default:
844 break;
845 }
846
847 if (num_serial == 0) {
848 moan_device("unknown NetMos/Mostech device", dev);
849 return -ENODEV;
850 }
851
852 return num_serial;
853 }
854
855 /*
856 * These chips are available with optionally one parallel port and up to
857 * two serial ports. Unfortunately they all have the same product id.
858 *
859 * Basic configuration is done over a region of 32 I/O ports. The base
860 * ioport is called INTA or INTC, depending on docs/other drivers.
861 *
862 * The region of the 32 I/O ports is configured in POSIO0R...
863 */
864
865 /* registers */
866 #define ITE_887x_MISCR 0x9c
867 #define ITE_887x_INTCBAR 0x78
868 #define ITE_887x_UARTBAR 0x7c
869 #define ITE_887x_PS0BAR 0x10
870 #define ITE_887x_POSIO0 0x60
871
872 /* I/O space size */
873 #define ITE_887x_IOSIZE 32
874 /* I/O space size (bits 26-24; 8 bytes = 011b) */
875 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
876 /* I/O space size (bits 26-24; 32 bytes = 101b) */
877 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
878 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
879 #define ITE_887x_POSIO_SPEED (3 << 29)
880 /* enable IO_Space bit */
881 #define ITE_887x_POSIO_ENABLE (1 << 31)
882
883 static int pci_ite887x_init(struct pci_dev *dev)
884 {
885 /* inta_addr are the configuration addresses of the ITE */
886 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
887 0x200, 0x280, 0 };
888 int ret, i, type;
889 struct resource *iobase = NULL;
890 u32 miscr, uartbar, ioport;
891
892 /* search for the base-ioport */
893 i = 0;
894 while (inta_addr[i] && iobase == NULL) {
895 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
896 "ite887x");
897 if (iobase != NULL) {
898 /* write POSIO0R - speed | size | ioport */
899 pci_write_config_dword(dev, ITE_887x_POSIO0,
900 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
901 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
902 /* write INTCBAR - ioport */
903 pci_write_config_dword(dev, ITE_887x_INTCBAR,
904 inta_addr[i]);
905 ret = inb(inta_addr[i]);
906 if (ret != 0xff) {
907 /* ioport connected */
908 break;
909 }
910 release_region(iobase->start, ITE_887x_IOSIZE);
911 iobase = NULL;
912 }
913 i++;
914 }
915
916 if (!inta_addr[i]) {
917 dev_err(&dev->dev, "ite887x: could not find iobase\n");
918 return -ENODEV;
919 }
920
921 /* start of undocumented type checking (see parport_pc.c) */
922 type = inb(iobase->start + 0x18) & 0x0f;
923
924 switch (type) {
925 case 0x2: /* ITE8871 (1P) */
926 case 0xa: /* ITE8875 (1P) */
927 ret = 0;
928 break;
929 case 0xe: /* ITE8872 (2S1P) */
930 ret = 2;
931 break;
932 case 0x6: /* ITE8873 (1S) */
933 ret = 1;
934 break;
935 case 0x8: /* ITE8874 (2S) */
936 ret = 2;
937 break;
938 default:
939 moan_device("Unknown ITE887x", dev);
940 ret = -ENODEV;
941 }
942
943 /* configure all serial ports */
944 for (i = 0; i < ret; i++) {
945 /* read the I/O port from the device */
946 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
947 &ioport);
948 ioport &= 0x0000FF00; /* the actual base address */
949 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
950 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
951 ITE_887x_POSIO_IOSIZE_8 | ioport);
952
953 /* write the ioport to the UARTBAR */
954 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
955 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
956 uartbar |= (ioport << (16 * i)); /* set the ioport */
957 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
958
959 /* get current config */
960 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
961 /* disable interrupts (UARTx_Routing[3:0]) */
962 miscr &= ~(0xf << (12 - 4 * i));
963 /* activate the UART (UARTx_En) */
964 miscr |= 1 << (23 - i);
965 /* write new config with activated UART */
966 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
967 }
968
969 if (ret <= 0) {
970 /* the device has no UARTs if we get here */
971 release_region(iobase->start, ITE_887x_IOSIZE);
972 }
973
974 return ret;
975 }
976
977 static void pci_ite887x_exit(struct pci_dev *dev)
978 {
979 u32 ioport;
980 /* the ioport is bit 0-15 in POSIO0R */
981 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
982 ioport &= 0xffff;
983 release_region(ioport, ITE_887x_IOSIZE);
984 }
985
986 /*
987 * EndRun Technologies.
988 * Determine the number of ports available on the device.
989 */
990 #define PCI_VENDOR_ID_ENDRUN 0x7401
991 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
992
993 static int pci_endrun_init(struct pci_dev *dev)
994 {
995 u8 __iomem *p;
996 unsigned long deviceID;
997 unsigned int number_uarts = 0;
998
999 /* EndRun device is all 0xexxx */
1000 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1001 (dev->device & 0xf000) != 0xe000)
1002 return 0;
1003
1004 p = pci_iomap(dev, 0, 5);
1005 if (p == NULL)
1006 return -ENOMEM;
1007
1008 deviceID = ioread32(p);
1009 /* EndRun device */
1010 if (deviceID == 0x07000200) {
1011 number_uarts = ioread8(p + 4);
1012 dev_dbg(&dev->dev,
1013 "%d ports detected on EndRun PCI Express device\n",
1014 number_uarts);
1015 }
1016 pci_iounmap(dev, p);
1017 return number_uarts;
1018 }
1019
1020 /*
1021 * Oxford Semiconductor Inc.
1022 * Check that device is part of the Tornado range of devices, then determine
1023 * the number of ports available on the device.
1024 */
1025 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1026 {
1027 u8 __iomem *p;
1028 unsigned long deviceID;
1029 unsigned int number_uarts = 0;
1030
1031 /* OxSemi Tornado devices are all 0xCxxx */
1032 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1033 (dev->device & 0xF000) != 0xC000)
1034 return 0;
1035
1036 p = pci_iomap(dev, 0, 5);
1037 if (p == NULL)
1038 return -ENOMEM;
1039
1040 deviceID = ioread32(p);
1041 /* Tornado device */
1042 if (deviceID == 0x07000200) {
1043 number_uarts = ioread8(p + 4);
1044 dev_dbg(&dev->dev,
1045 "%d ports detected on Oxford PCI Express device\n",
1046 number_uarts);
1047 }
1048 pci_iounmap(dev, p);
1049 return number_uarts;
1050 }
1051
1052 static int pci_asix_setup(struct serial_private *priv,
1053 const struct pciserial_board *board,
1054 struct uart_8250_port *port, int idx)
1055 {
1056 port->bugs |= UART_BUG_PARITY;
1057 return pci_default_setup(priv, board, port, idx);
1058 }
1059
1060 /* Quatech devices have their own extra interface features */
1061
1062 struct quatech_feature {
1063 u16 devid;
1064 bool amcc;
1065 };
1066
1067 #define QPCR_TEST_FOR1 0x3F
1068 #define QPCR_TEST_GET1 0x00
1069 #define QPCR_TEST_FOR2 0x40
1070 #define QPCR_TEST_GET2 0x40
1071 #define QPCR_TEST_FOR3 0x80
1072 #define QPCR_TEST_GET3 0x40
1073 #define QPCR_TEST_FOR4 0xC0
1074 #define QPCR_TEST_GET4 0x80
1075
1076 #define QOPR_CLOCK_X1 0x0000
1077 #define QOPR_CLOCK_X2 0x0001
1078 #define QOPR_CLOCK_X4 0x0002
1079 #define QOPR_CLOCK_X8 0x0003
1080 #define QOPR_CLOCK_RATE_MASK 0x0003
1081
1082
1083 static struct quatech_feature quatech_cards[] = {
1084 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1085 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1086 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1087 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1088 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1089 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1090 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1091 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1092 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1093 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1094 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1095 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1096 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1097 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1098 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1099 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1100 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1101 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1102 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1103 { 0, }
1104 };
1105
1106 static int pci_quatech_amcc(u16 devid)
1107 {
1108 struct quatech_feature *qf = &quatech_cards[0];
1109 while (qf->devid) {
1110 if (qf->devid == devid)
1111 return qf->amcc;
1112 qf++;
1113 }
1114 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1115 return 0;
1116 };
1117
1118 static int pci_quatech_rqopr(struct uart_8250_port *port)
1119 {
1120 unsigned long base = port->port.iobase;
1121 u8 LCR, val;
1122
1123 LCR = inb(base + UART_LCR);
1124 outb(0xBF, base + UART_LCR);
1125 val = inb(base + UART_SCR);
1126 outb(LCR, base + UART_LCR);
1127 return val;
1128 }
1129
1130 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1131 {
1132 unsigned long base = port->port.iobase;
1133 u8 LCR;
1134
1135 LCR = inb(base + UART_LCR);
1136 outb(0xBF, base + UART_LCR);
1137 inb(base + UART_SCR);
1138 outb(qopr, base + UART_SCR);
1139 outb(LCR, base + UART_LCR);
1140 }
1141
1142 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1143 {
1144 unsigned long base = port->port.iobase;
1145 u8 LCR, val, qmcr;
1146
1147 LCR = inb(base + UART_LCR);
1148 outb(0xBF, base + UART_LCR);
1149 val = inb(base + UART_SCR);
1150 outb(val | 0x10, base + UART_SCR);
1151 qmcr = inb(base + UART_MCR);
1152 outb(val, base + UART_SCR);
1153 outb(LCR, base + UART_LCR);
1154
1155 return qmcr;
1156 }
1157
1158 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1159 {
1160 unsigned long base = port->port.iobase;
1161 u8 LCR, val;
1162
1163 LCR = inb(base + UART_LCR);
1164 outb(0xBF, base + UART_LCR);
1165 val = inb(base + UART_SCR);
1166 outb(val | 0x10, base + UART_SCR);
1167 outb(qmcr, base + UART_MCR);
1168 outb(val, base + UART_SCR);
1169 outb(LCR, base + UART_LCR);
1170 }
1171
1172 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1173 {
1174 unsigned long base = port->port.iobase;
1175 u8 LCR, val;
1176
1177 LCR = inb(base + UART_LCR);
1178 outb(0xBF, base + UART_LCR);
1179 val = inb(base + UART_SCR);
1180 if (val & 0x20) {
1181 outb(0x80, UART_LCR);
1182 if (!(inb(UART_SCR) & 0x20)) {
1183 outb(LCR, base + UART_LCR);
1184 return 1;
1185 }
1186 }
1187 return 0;
1188 }
1189
1190 static int pci_quatech_test(struct uart_8250_port *port)
1191 {
1192 u8 reg, qopr;
1193
1194 qopr = pci_quatech_rqopr(port);
1195 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1196 reg = pci_quatech_rqopr(port) & 0xC0;
1197 if (reg != QPCR_TEST_GET1)
1198 return -EINVAL;
1199 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1200 reg = pci_quatech_rqopr(port) & 0xC0;
1201 if (reg != QPCR_TEST_GET2)
1202 return -EINVAL;
1203 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1204 reg = pci_quatech_rqopr(port) & 0xC0;
1205 if (reg != QPCR_TEST_GET3)
1206 return -EINVAL;
1207 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1208 reg = pci_quatech_rqopr(port) & 0xC0;
1209 if (reg != QPCR_TEST_GET4)
1210 return -EINVAL;
1211
1212 pci_quatech_wqopr(port, qopr);
1213 return 0;
1214 }
1215
1216 static int pci_quatech_clock(struct uart_8250_port *port)
1217 {
1218 u8 qopr, reg, set;
1219 unsigned long clock;
1220
1221 if (pci_quatech_test(port) < 0)
1222 return 1843200;
1223
1224 qopr = pci_quatech_rqopr(port);
1225
1226 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1227 reg = pci_quatech_rqopr(port);
1228 if (reg & QOPR_CLOCK_X8) {
1229 clock = 1843200;
1230 goto out;
1231 }
1232 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1233 reg = pci_quatech_rqopr(port);
1234 if (!(reg & QOPR_CLOCK_X8)) {
1235 clock = 1843200;
1236 goto out;
1237 }
1238 reg &= QOPR_CLOCK_X8;
1239 if (reg == QOPR_CLOCK_X2) {
1240 clock = 3685400;
1241 set = QOPR_CLOCK_X2;
1242 } else if (reg == QOPR_CLOCK_X4) {
1243 clock = 7372800;
1244 set = QOPR_CLOCK_X4;
1245 } else if (reg == QOPR_CLOCK_X8) {
1246 clock = 14745600;
1247 set = QOPR_CLOCK_X8;
1248 } else {
1249 clock = 1843200;
1250 set = QOPR_CLOCK_X1;
1251 }
1252 qopr &= ~QOPR_CLOCK_RATE_MASK;
1253 qopr |= set;
1254
1255 out:
1256 pci_quatech_wqopr(port, qopr);
1257 return clock;
1258 }
1259
1260 static int pci_quatech_rs422(struct uart_8250_port *port)
1261 {
1262 u8 qmcr;
1263 int rs422 = 0;
1264
1265 if (!pci_quatech_has_qmcr(port))
1266 return 0;
1267 qmcr = pci_quatech_rqmcr(port);
1268 pci_quatech_wqmcr(port, 0xFF);
1269 if (pci_quatech_rqmcr(port))
1270 rs422 = 1;
1271 pci_quatech_wqmcr(port, qmcr);
1272 return rs422;
1273 }
1274
1275 static int pci_quatech_init(struct pci_dev *dev)
1276 {
1277 if (pci_quatech_amcc(dev->device)) {
1278 unsigned long base = pci_resource_start(dev, 0);
1279 if (base) {
1280 u32 tmp;
1281
1282 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1283 tmp = inl(base + 0x3c);
1284 outl(tmp | 0x01000000, base + 0x3c);
1285 outl(tmp &= ~0x01000000, base + 0x3c);
1286 }
1287 }
1288 return 0;
1289 }
1290
1291 static int pci_quatech_setup(struct serial_private *priv,
1292 const struct pciserial_board *board,
1293 struct uart_8250_port *port, int idx)
1294 {
1295 /* Needed by pci_quatech calls below */
1296 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1297 /* Set up the clocking */
1298 port->port.uartclk = pci_quatech_clock(port);
1299 /* For now just warn about RS422 */
1300 if (pci_quatech_rs422(port))
1301 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1302 return pci_default_setup(priv, board, port, idx);
1303 }
1304
1305 static void pci_quatech_exit(struct pci_dev *dev)
1306 {
1307 }
1308
1309 static int pci_default_setup(struct serial_private *priv,
1310 const struct pciserial_board *board,
1311 struct uart_8250_port *port, int idx)
1312 {
1313 unsigned int bar, offset = board->first_offset, maxnr;
1314
1315 bar = FL_GET_BASE(board->flags);
1316 if (board->flags & FL_BASE_BARS)
1317 bar += idx;
1318 else
1319 offset += idx * board->uart_offset;
1320
1321 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1322 (board->reg_shift + 3);
1323
1324 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1325 return 1;
1326
1327 return setup_port(priv, port, bar, offset, board->reg_shift);
1328 }
1329
1330 static int pci_pericom_setup(struct serial_private *priv,
1331 const struct pciserial_board *board,
1332 struct uart_8250_port *port, int idx)
1333 {
1334 unsigned int bar, offset = board->first_offset, maxnr;
1335
1336 bar = FL_GET_BASE(board->flags);
1337 if (board->flags & FL_BASE_BARS)
1338 bar += idx;
1339 else
1340 offset += idx * board->uart_offset;
1341
1342 if (idx==3)
1343 offset = 0x38;
1344
1345 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1346 (board->reg_shift + 3);
1347
1348 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1349 return 1;
1350
1351 return setup_port(priv, port, bar, offset, board->reg_shift);
1352 }
1353
1354 static int
1355 ce4100_serial_setup(struct serial_private *priv,
1356 const struct pciserial_board *board,
1357 struct uart_8250_port *port, int idx)
1358 {
1359 int ret;
1360
1361 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1362 port->port.iotype = UPIO_MEM32;
1363 port->port.type = PORT_XSCALE;
1364 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1365 port->port.regshift = 2;
1366
1367 return ret;
1368 }
1369
1370 static int
1371 pci_omegapci_setup(struct serial_private *priv,
1372 const struct pciserial_board *board,
1373 struct uart_8250_port *port, int idx)
1374 {
1375 return setup_port(priv, port, 2, idx * 8, 0);
1376 }
1377
1378 static int
1379 pci_brcm_trumanage_setup(struct serial_private *priv,
1380 const struct pciserial_board *board,
1381 struct uart_8250_port *port, int idx)
1382 {
1383 int ret = pci_default_setup(priv, board, port, idx);
1384
1385 port->port.type = PORT_BRCM_TRUMANAGE;
1386 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1387 return ret;
1388 }
1389
1390 /* RTS will control by MCR if this bit is 0 */
1391 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1392 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1393 #define FINTEK_RTS_INVERT BIT(5)
1394
1395 /* We should do proper H/W transceiver setting before change to RS485 mode */
1396 static int pci_fintek_rs485_config(struct uart_port *port,
1397 struct serial_rs485 *rs485)
1398 {
1399 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1400 u8 setting;
1401 u8 *index = (u8 *) port->private_data;
1402
1403 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1404
1405 if (!rs485)
1406 rs485 = &port->rs485;
1407 else if (rs485->flags & SER_RS485_ENABLED)
1408 memset(rs485->padding, 0, sizeof(rs485->padding));
1409 else
1410 memset(rs485, 0, sizeof(*rs485));
1411
1412 /* F81504/508/512 not support RTS delay before or after send */
1413 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1414
1415 if (rs485->flags & SER_RS485_ENABLED) {
1416 /* Enable RTS H/W control mode */
1417 setting |= FINTEK_RTS_CONTROL_BY_HW;
1418
1419 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1420 /* RTS driving high on TX */
1421 setting &= ~FINTEK_RTS_INVERT;
1422 } else {
1423 /* RTS driving low on TX */
1424 setting |= FINTEK_RTS_INVERT;
1425 }
1426
1427 rs485->delay_rts_after_send = 0;
1428 rs485->delay_rts_before_send = 0;
1429 } else {
1430 /* Disable RTS H/W control mode */
1431 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1432 }
1433
1434 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1435
1436 if (rs485 != &port->rs485)
1437 port->rs485 = *rs485;
1438
1439 return 0;
1440 }
1441
1442 static int pci_fintek_setup(struct serial_private *priv,
1443 const struct pciserial_board *board,
1444 struct uart_8250_port *port, int idx)
1445 {
1446 struct pci_dev *pdev = priv->dev;
1447 u8 *data;
1448 u8 config_base;
1449 u16 iobase;
1450
1451 config_base = 0x40 + 0x08 * idx;
1452
1453 /* Get the io address from configuration space */
1454 pci_read_config_word(pdev, config_base + 4, &iobase);
1455
1456 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1457
1458 port->port.iotype = UPIO_PORT;
1459 port->port.iobase = iobase;
1460 port->port.rs485_config = pci_fintek_rs485_config;
1461
1462 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1463 if (!data)
1464 return -ENOMEM;
1465
1466 /* preserve index in PCI configuration space */
1467 *data = idx;
1468 port->port.private_data = data;
1469
1470 return 0;
1471 }
1472
1473 static int pci_fintek_init(struct pci_dev *dev)
1474 {
1475 unsigned long iobase;
1476 u32 max_port, i;
1477 resource_size_t bar_data[3];
1478 u8 config_base;
1479 struct serial_private *priv = pci_get_drvdata(dev);
1480 struct uart_8250_port *port;
1481
1482 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1483 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1484 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1485 return -ENODEV;
1486
1487 switch (dev->device) {
1488 case 0x1104: /* 4 ports */
1489 case 0x1108: /* 8 ports */
1490 max_port = dev->device & 0xff;
1491 break;
1492 case 0x1112: /* 12 ports */
1493 max_port = 12;
1494 break;
1495 default:
1496 return -EINVAL;
1497 }
1498
1499 /* Get the io address dispatch from the BIOS */
1500 bar_data[0] = pci_resource_start(dev, 5);
1501 bar_data[1] = pci_resource_start(dev, 4);
1502 bar_data[2] = pci_resource_start(dev, 3);
1503
1504 for (i = 0; i < max_port; ++i) {
1505 /* UART0 configuration offset start from 0x40 */
1506 config_base = 0x40 + 0x08 * i;
1507
1508 /* Calculate Real IO Port */
1509 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1510
1511 /* Enable UART I/O port */
1512 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1513
1514 /* Select 128-byte FIFO and 8x FIFO threshold */
1515 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1516
1517 /* LSB UART */
1518 pci_write_config_byte(dev, config_base + 0x04,
1519 (u8)(iobase & 0xff));
1520
1521 /* MSB UART */
1522 pci_write_config_byte(dev, config_base + 0x05,
1523 (u8)((iobase & 0xff00) >> 8));
1524
1525 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1526
1527 if (priv) {
1528 /* re-apply RS232/485 mode when
1529 * pciserial_resume_ports()
1530 */
1531 port = serial8250_get_port(priv->line[i]);
1532 pci_fintek_rs485_config(&port->port, NULL);
1533 } else {
1534 /* First init without port data
1535 * force init to RS232 Mode
1536 */
1537 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1538 }
1539 }
1540
1541 return max_port;
1542 }
1543
1544 static int skip_tx_en_setup(struct serial_private *priv,
1545 const struct pciserial_board *board,
1546 struct uart_8250_port *port, int idx)
1547 {
1548 port->port.quirks |= UPQ_NO_TXEN_TEST;
1549 dev_dbg(&priv->dev->dev,
1550 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1551 priv->dev->vendor, priv->dev->device,
1552 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1553
1554 return pci_default_setup(priv, board, port, idx);
1555 }
1556
1557 static void kt_handle_break(struct uart_port *p)
1558 {
1559 struct uart_8250_port *up = up_to_u8250p(p);
1560 /*
1561 * On receipt of a BI, serial device in Intel ME (Intel
1562 * management engine) needs to have its fifos cleared for sane
1563 * SOL (Serial Over Lan) output.
1564 */
1565 serial8250_clear_and_reinit_fifos(up);
1566 }
1567
1568 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1569 {
1570 struct uart_8250_port *up = up_to_u8250p(p);
1571 unsigned int val;
1572
1573 /*
1574 * When the Intel ME (management engine) gets reset its serial
1575 * port registers could return 0 momentarily. Functions like
1576 * serial8250_console_write, read and save the IER, perform
1577 * some operation and then restore it. In order to avoid
1578 * setting IER register inadvertently to 0, if the value read
1579 * is 0, double check with ier value in uart_8250_port and use
1580 * that instead. up->ier should be the same value as what is
1581 * currently configured.
1582 */
1583 val = inb(p->iobase + offset);
1584 if (offset == UART_IER) {
1585 if (val == 0)
1586 val = up->ier;
1587 }
1588 return val;
1589 }
1590
1591 static int kt_serial_setup(struct serial_private *priv,
1592 const struct pciserial_board *board,
1593 struct uart_8250_port *port, int idx)
1594 {
1595 port->port.flags |= UPF_BUG_THRE;
1596 port->port.serial_in = kt_serial_in;
1597 port->port.handle_break = kt_handle_break;
1598 return skip_tx_en_setup(priv, board, port, idx);
1599 }
1600
1601 static int pci_eg20t_init(struct pci_dev *dev)
1602 {
1603 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1604 return -ENODEV;
1605 #else
1606 return 0;
1607 #endif
1608 }
1609
1610 static int
1611 pci_wch_ch353_setup(struct serial_private *priv,
1612 const struct pciserial_board *board,
1613 struct uart_8250_port *port, int idx)
1614 {
1615 port->port.flags |= UPF_FIXED_TYPE;
1616 port->port.type = PORT_16550A;
1617 return pci_default_setup(priv, board, port, idx);
1618 }
1619
1620 static int
1621 pci_wch_ch355_setup(struct serial_private *priv,
1622 const struct pciserial_board *board,
1623 struct uart_8250_port *port, int idx)
1624 {
1625 port->port.flags |= UPF_FIXED_TYPE;
1626 port->port.type = PORT_16550A;
1627 return pci_default_setup(priv, board, port, idx);
1628 }
1629
1630 static int
1631 pci_wch_ch38x_setup(struct serial_private *priv,
1632 const struct pciserial_board *board,
1633 struct uart_8250_port *port, int idx)
1634 {
1635 port->port.flags |= UPF_FIXED_TYPE;
1636 port->port.type = PORT_16850;
1637 return pci_default_setup(priv, board, port, idx);
1638 }
1639
1640 static int
1641 pci_sunix_setup(struct serial_private *priv,
1642 const struct pciserial_board *board,
1643 struct uart_8250_port *port, int idx)
1644 {
1645 int bar;
1646 int offset;
1647
1648 port->port.flags |= UPF_FIXED_TYPE;
1649 port->port.type = PORT_SUNIX;
1650
1651 if (idx < 4) {
1652 bar = 0;
1653 offset = idx * board->uart_offset;
1654 } else {
1655 bar = 1;
1656 idx -= 4;
1657 idx = div_s64_rem(idx, 4, &offset);
1658 offset = idx * 64 + offset * board->uart_offset;
1659 }
1660
1661 return setup_port(priv, port, bar, offset, 0);
1662 }
1663
1664 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1665 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1666 #define PCI_DEVICE_ID_OCTPRO 0x0001
1667 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1668 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1669 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1670 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1671 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1672 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1673 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1674 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1675 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1676 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1677 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1678 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1679 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1680 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1681 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1682 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1683 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1684 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1685 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1686 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1687 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1688 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1689 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1690 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1691 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1692 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1693 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1694 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1695 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1696 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1697 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1698 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1699 #define PCI_VENDOR_ID_WCH 0x4348
1700 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1701 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1702 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1703 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1704 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1705 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
1706 #define PCI_VENDOR_ID_AGESTAR 0x5372
1707 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1708 #define PCI_VENDOR_ID_ASIX 0x9710
1709 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1710 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1711
1712 #define PCI_VENDOR_ID_SUNIX 0x1fd4
1713 #define PCI_DEVICE_ID_SUNIX_1999 0x1999
1714
1715 #define PCIE_VENDOR_ID_WCH 0x1c00
1716 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1717 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1718 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1719
1720 #define PCI_VENDOR_ID_PERICOM 0x12D8
1721 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951
1722 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952
1723 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954
1724 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958
1725
1726 #define PCI_VENDOR_ID_ACCESIO 0x494f
1727 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051
1728 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053
1729 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C
1730 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E
1731 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091
1732 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093
1733 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099
1734 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B
1735 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1
1736 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3
1737 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA
1738 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC
1739 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108
1740 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110
1741 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111
1742 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118
1743 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119
1744 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152
1745 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A
1746 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190
1747 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191
1748 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198
1749 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199
1750 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0
1751 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A
1752 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B
1753 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A
1754 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B
1755 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098
1756 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9
1757 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9
1758 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9
1759 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8
1760
1761
1762
1763 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1764 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1765 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1766
1767 /*
1768 * Master list of serial port init/setup/exit quirks.
1769 * This does not describe the general nature of the port.
1770 * (ie, baud base, number and location of ports, etc)
1771 *
1772 * This list is ordered alphabetically by vendor then device.
1773 * Specific entries must come before more generic entries.
1774 */
1775 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1776 /*
1777 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1778 */
1779 {
1780 .vendor = PCI_VENDOR_ID_AMCC,
1781 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1782 .subvendor = PCI_ANY_ID,
1783 .subdevice = PCI_ANY_ID,
1784 .setup = addidata_apci7800_setup,
1785 },
1786 /*
1787 * AFAVLAB cards - these may be called via parport_serial
1788 * It is not clear whether this applies to all products.
1789 */
1790 {
1791 .vendor = PCI_VENDOR_ID_AFAVLAB,
1792 .device = PCI_ANY_ID,
1793 .subvendor = PCI_ANY_ID,
1794 .subdevice = PCI_ANY_ID,
1795 .setup = afavlab_setup,
1796 },
1797 /*
1798 * HP Diva
1799 */
1800 {
1801 .vendor = PCI_VENDOR_ID_HP,
1802 .device = PCI_DEVICE_ID_HP_DIVA,
1803 .subvendor = PCI_ANY_ID,
1804 .subdevice = PCI_ANY_ID,
1805 .init = pci_hp_diva_init,
1806 .setup = pci_hp_diva_setup,
1807 },
1808 /*
1809 * Intel
1810 */
1811 {
1812 .vendor = PCI_VENDOR_ID_INTEL,
1813 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1814 .subvendor = 0xe4bf,
1815 .subdevice = PCI_ANY_ID,
1816 .init = pci_inteli960ni_init,
1817 .setup = pci_default_setup,
1818 },
1819 {
1820 .vendor = PCI_VENDOR_ID_INTEL,
1821 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1822 .subvendor = PCI_ANY_ID,
1823 .subdevice = PCI_ANY_ID,
1824 .setup = skip_tx_en_setup,
1825 },
1826 {
1827 .vendor = PCI_VENDOR_ID_INTEL,
1828 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1829 .subvendor = PCI_ANY_ID,
1830 .subdevice = PCI_ANY_ID,
1831 .setup = skip_tx_en_setup,
1832 },
1833 {
1834 .vendor = PCI_VENDOR_ID_INTEL,
1835 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1836 .subvendor = PCI_ANY_ID,
1837 .subdevice = PCI_ANY_ID,
1838 .setup = skip_tx_en_setup,
1839 },
1840 {
1841 .vendor = PCI_VENDOR_ID_INTEL,
1842 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1843 .subvendor = PCI_ANY_ID,
1844 .subdevice = PCI_ANY_ID,
1845 .setup = ce4100_serial_setup,
1846 },
1847 {
1848 .vendor = PCI_VENDOR_ID_INTEL,
1849 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1850 .subvendor = PCI_ANY_ID,
1851 .subdevice = PCI_ANY_ID,
1852 .setup = kt_serial_setup,
1853 },
1854 /*
1855 * ITE
1856 */
1857 {
1858 .vendor = PCI_VENDOR_ID_ITE,
1859 .device = PCI_DEVICE_ID_ITE_8872,
1860 .subvendor = PCI_ANY_ID,
1861 .subdevice = PCI_ANY_ID,
1862 .init = pci_ite887x_init,
1863 .setup = pci_default_setup,
1864 .exit = pci_ite887x_exit,
1865 },
1866 /*
1867 * National Instruments
1868 */
1869 {
1870 .vendor = PCI_VENDOR_ID_NI,
1871 .device = PCI_DEVICE_ID_NI_PCI23216,
1872 .subvendor = PCI_ANY_ID,
1873 .subdevice = PCI_ANY_ID,
1874 .init = pci_ni8420_init,
1875 .setup = pci_default_setup,
1876 .exit = pci_ni8420_exit,
1877 },
1878 {
1879 .vendor = PCI_VENDOR_ID_NI,
1880 .device = PCI_DEVICE_ID_NI_PCI2328,
1881 .subvendor = PCI_ANY_ID,
1882 .subdevice = PCI_ANY_ID,
1883 .init = pci_ni8420_init,
1884 .setup = pci_default_setup,
1885 .exit = pci_ni8420_exit,
1886 },
1887 {
1888 .vendor = PCI_VENDOR_ID_NI,
1889 .device = PCI_DEVICE_ID_NI_PCI2324,
1890 .subvendor = PCI_ANY_ID,
1891 .subdevice = PCI_ANY_ID,
1892 .init = pci_ni8420_init,
1893 .setup = pci_default_setup,
1894 .exit = pci_ni8420_exit,
1895 },
1896 {
1897 .vendor = PCI_VENDOR_ID_NI,
1898 .device = PCI_DEVICE_ID_NI_PCI2322,
1899 .subvendor = PCI_ANY_ID,
1900 .subdevice = PCI_ANY_ID,
1901 .init = pci_ni8420_init,
1902 .setup = pci_default_setup,
1903 .exit = pci_ni8420_exit,
1904 },
1905 {
1906 .vendor = PCI_VENDOR_ID_NI,
1907 .device = PCI_DEVICE_ID_NI_PCI2324I,
1908 .subvendor = PCI_ANY_ID,
1909 .subdevice = PCI_ANY_ID,
1910 .init = pci_ni8420_init,
1911 .setup = pci_default_setup,
1912 .exit = pci_ni8420_exit,
1913 },
1914 {
1915 .vendor = PCI_VENDOR_ID_NI,
1916 .device = PCI_DEVICE_ID_NI_PCI2322I,
1917 .subvendor = PCI_ANY_ID,
1918 .subdevice = PCI_ANY_ID,
1919 .init = pci_ni8420_init,
1920 .setup = pci_default_setup,
1921 .exit = pci_ni8420_exit,
1922 },
1923 {
1924 .vendor = PCI_VENDOR_ID_NI,
1925 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1926 .subvendor = PCI_ANY_ID,
1927 .subdevice = PCI_ANY_ID,
1928 .init = pci_ni8420_init,
1929 .setup = pci_default_setup,
1930 .exit = pci_ni8420_exit,
1931 },
1932 {
1933 .vendor = PCI_VENDOR_ID_NI,
1934 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1935 .subvendor = PCI_ANY_ID,
1936 .subdevice = PCI_ANY_ID,
1937 .init = pci_ni8420_init,
1938 .setup = pci_default_setup,
1939 .exit = pci_ni8420_exit,
1940 },
1941 {
1942 .vendor = PCI_VENDOR_ID_NI,
1943 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1944 .subvendor = PCI_ANY_ID,
1945 .subdevice = PCI_ANY_ID,
1946 .init = pci_ni8420_init,
1947 .setup = pci_default_setup,
1948 .exit = pci_ni8420_exit,
1949 },
1950 {
1951 .vendor = PCI_VENDOR_ID_NI,
1952 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1953 .subvendor = PCI_ANY_ID,
1954 .subdevice = PCI_ANY_ID,
1955 .init = pci_ni8420_init,
1956 .setup = pci_default_setup,
1957 .exit = pci_ni8420_exit,
1958 },
1959 {
1960 .vendor = PCI_VENDOR_ID_NI,
1961 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1962 .subvendor = PCI_ANY_ID,
1963 .subdevice = PCI_ANY_ID,
1964 .init = pci_ni8420_init,
1965 .setup = pci_default_setup,
1966 .exit = pci_ni8420_exit,
1967 },
1968 {
1969 .vendor = PCI_VENDOR_ID_NI,
1970 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1971 .subvendor = PCI_ANY_ID,
1972 .subdevice = PCI_ANY_ID,
1973 .init = pci_ni8420_init,
1974 .setup = pci_default_setup,
1975 .exit = pci_ni8420_exit,
1976 },
1977 {
1978 .vendor = PCI_VENDOR_ID_NI,
1979 .device = PCI_ANY_ID,
1980 .subvendor = PCI_ANY_ID,
1981 .subdevice = PCI_ANY_ID,
1982 .init = pci_ni8430_init,
1983 .setup = pci_ni8430_setup,
1984 .exit = pci_ni8430_exit,
1985 },
1986 /* Quatech */
1987 {
1988 .vendor = PCI_VENDOR_ID_QUATECH,
1989 .device = PCI_ANY_ID,
1990 .subvendor = PCI_ANY_ID,
1991 .subdevice = PCI_ANY_ID,
1992 .init = pci_quatech_init,
1993 .setup = pci_quatech_setup,
1994 .exit = pci_quatech_exit,
1995 },
1996 /*
1997 * Panacom
1998 */
1999 {
2000 .vendor = PCI_VENDOR_ID_PANACOM,
2001 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2002 .subvendor = PCI_ANY_ID,
2003 .subdevice = PCI_ANY_ID,
2004 .init = pci_plx9050_init,
2005 .setup = pci_default_setup,
2006 .exit = pci_plx9050_exit,
2007 },
2008 {
2009 .vendor = PCI_VENDOR_ID_PANACOM,
2010 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2011 .subvendor = PCI_ANY_ID,
2012 .subdevice = PCI_ANY_ID,
2013 .init = pci_plx9050_init,
2014 .setup = pci_default_setup,
2015 .exit = pci_plx9050_exit,
2016 },
2017 /*
2018 * Pericom (Only 7954 - It have a offset jump for port 4)
2019 */
2020 {
2021 .vendor = PCI_VENDOR_ID_PERICOM,
2022 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954,
2023 .subvendor = PCI_ANY_ID,
2024 .subdevice = PCI_ANY_ID,
2025 .setup = pci_pericom_setup,
2026 },
2027 /*
2028 * PLX
2029 */
2030 {
2031 .vendor = PCI_VENDOR_ID_PLX,
2032 .device = PCI_DEVICE_ID_PLX_9050,
2033 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2034 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2035 .init = pci_plx9050_init,
2036 .setup = pci_default_setup,
2037 .exit = pci_plx9050_exit,
2038 },
2039 {
2040 .vendor = PCI_VENDOR_ID_PLX,
2041 .device = PCI_DEVICE_ID_PLX_9050,
2042 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2043 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2044 .init = pci_plx9050_init,
2045 .setup = pci_default_setup,
2046 .exit = pci_plx9050_exit,
2047 },
2048 {
2049 .vendor = PCI_VENDOR_ID_PLX,
2050 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2051 .subvendor = PCI_VENDOR_ID_PLX,
2052 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2053 .init = pci_plx9050_init,
2054 .setup = pci_default_setup,
2055 .exit = pci_plx9050_exit,
2056 },
2057 {
2058 .vendor = PCI_VENDOR_ID_ACCESIO,
2059 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
2060 .subvendor = PCI_ANY_ID,
2061 .subdevice = PCI_ANY_ID,
2062 .setup = pci_pericom_setup,
2063 },
2064 {
2065 .vendor = PCI_VENDOR_ID_ACCESIO,
2066 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
2067 .subvendor = PCI_ANY_ID,
2068 .subdevice = PCI_ANY_ID,
2069 .setup = pci_pericom_setup,
2070 },
2071 {
2072 .vendor = PCI_VENDOR_ID_ACCESIO,
2073 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
2074 .subvendor = PCI_ANY_ID,
2075 .subdevice = PCI_ANY_ID,
2076 .setup = pci_pericom_setup,
2077 },
2078 {
2079 .vendor = PCI_VENDOR_ID_ACCESIO,
2080 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
2081 .subvendor = PCI_ANY_ID,
2082 .subdevice = PCI_ANY_ID,
2083 .setup = pci_pericom_setup,
2084 },
2085 {
2086 .vendor = PCI_VENDOR_ID_ACCESIO,
2087 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
2088 .subvendor = PCI_ANY_ID,
2089 .subdevice = PCI_ANY_ID,
2090 .setup = pci_pericom_setup,
2091 },
2092 {
2093 .vendor = PCI_VENDOR_ID_ACCESIO,
2094 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
2095 .subvendor = PCI_ANY_ID,
2096 .subdevice = PCI_ANY_ID,
2097 .setup = pci_pericom_setup,
2098 },
2099 {
2100 .vendor = PCI_VENDOR_ID_ACCESIO,
2101 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
2102 .subvendor = PCI_ANY_ID,
2103 .subdevice = PCI_ANY_ID,
2104 .setup = pci_pericom_setup,
2105 },
2106 {
2107 .vendor = PCI_VENDOR_ID_ACCESIO,
2108 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
2109 .subvendor = PCI_ANY_ID,
2110 .subdevice = PCI_ANY_ID,
2111 .setup = pci_pericom_setup,
2112 },
2113 {
2114 .vendor = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
2115 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
2116 .subvendor = PCI_ANY_ID,
2117 .subdevice = PCI_ANY_ID,
2118 .setup = pci_pericom_setup,
2119 },
2120 {
2121 .vendor = PCI_VENDOR_ID_ACCESIO,
2122 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
2123 .subvendor = PCI_ANY_ID,
2124 .subdevice = PCI_ANY_ID,
2125 .setup = pci_pericom_setup,
2126 },
2127 {
2128 .vendor = PCI_VENDOR_ID_ACCESIO,
2129 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
2130 .subvendor = PCI_ANY_ID,
2131 .subdevice = PCI_ANY_ID,
2132 .setup = pci_pericom_setup,
2133 },
2134 {
2135 .vendor = PCI_VENDOR_ID_ACCESIO,
2136 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
2137 .subvendor = PCI_ANY_ID,
2138 .subdevice = PCI_ANY_ID,
2139 .setup = pci_pericom_setup,
2140 },
2141 {
2142 .vendor = PCI_VENDOR_ID_ACCESIO,
2143 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
2144 .subvendor = PCI_ANY_ID,
2145 .subdevice = PCI_ANY_ID,
2146 .setup = pci_pericom_setup,
2147 },
2148 {
2149 .vendor = PCI_VENDOR_ID_ACCESIO,
2150 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
2151 .subvendor = PCI_ANY_ID,
2152 .subdevice = PCI_ANY_ID,
2153 .setup = pci_pericom_setup,
2154 },
2155 {
2156 .vendor = PCI_VENDOR_ID_ACCESIO,
2157 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
2158 .subvendor = PCI_ANY_ID,
2159 .subdevice = PCI_ANY_ID,
2160 .setup = pci_pericom_setup,
2161 },
2162 /*
2163 * SBS Technologies, Inc., PMC-OCTALPRO 232
2164 */
2165 {
2166 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2167 .device = PCI_DEVICE_ID_OCTPRO,
2168 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2169 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2170 .init = sbs_init,
2171 .setup = sbs_setup,
2172 .exit = sbs_exit,
2173 },
2174 /*
2175 * SBS Technologies, Inc., PMC-OCTALPRO 422
2176 */
2177 {
2178 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2179 .device = PCI_DEVICE_ID_OCTPRO,
2180 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2181 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2182 .init = sbs_init,
2183 .setup = sbs_setup,
2184 .exit = sbs_exit,
2185 },
2186 /*
2187 * SBS Technologies, Inc., P-Octal 232
2188 */
2189 {
2190 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2191 .device = PCI_DEVICE_ID_OCTPRO,
2192 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2193 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2194 .init = sbs_init,
2195 .setup = sbs_setup,
2196 .exit = sbs_exit,
2197 },
2198 /*
2199 * SBS Technologies, Inc., P-Octal 422
2200 */
2201 {
2202 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2203 .device = PCI_DEVICE_ID_OCTPRO,
2204 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2205 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2206 .init = sbs_init,
2207 .setup = sbs_setup,
2208 .exit = sbs_exit,
2209 },
2210 /*
2211 * SIIG cards - these may be called via parport_serial
2212 */
2213 {
2214 .vendor = PCI_VENDOR_ID_SIIG,
2215 .device = PCI_ANY_ID,
2216 .subvendor = PCI_ANY_ID,
2217 .subdevice = PCI_ANY_ID,
2218 .init = pci_siig_init,
2219 .setup = pci_siig_setup,
2220 },
2221 /*
2222 * Titan cards
2223 */
2224 {
2225 .vendor = PCI_VENDOR_ID_TITAN,
2226 .device = PCI_DEVICE_ID_TITAN_400L,
2227 .subvendor = PCI_ANY_ID,
2228 .subdevice = PCI_ANY_ID,
2229 .setup = titan_400l_800l_setup,
2230 },
2231 {
2232 .vendor = PCI_VENDOR_ID_TITAN,
2233 .device = PCI_DEVICE_ID_TITAN_800L,
2234 .subvendor = PCI_ANY_ID,
2235 .subdevice = PCI_ANY_ID,
2236 .setup = titan_400l_800l_setup,
2237 },
2238 /*
2239 * Timedia cards
2240 */
2241 {
2242 .vendor = PCI_VENDOR_ID_TIMEDIA,
2243 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2244 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2245 .subdevice = PCI_ANY_ID,
2246 .probe = pci_timedia_probe,
2247 .init = pci_timedia_init,
2248 .setup = pci_timedia_setup,
2249 },
2250 {
2251 .vendor = PCI_VENDOR_ID_TIMEDIA,
2252 .device = PCI_ANY_ID,
2253 .subvendor = PCI_ANY_ID,
2254 .subdevice = PCI_ANY_ID,
2255 .setup = pci_timedia_setup,
2256 },
2257 /*
2258 * Sunix PCI serial boards
2259 */
2260 {
2261 .vendor = PCI_VENDOR_ID_SUNIX,
2262 .device = PCI_DEVICE_ID_SUNIX_1999,
2263 .subvendor = PCI_VENDOR_ID_SUNIX,
2264 .subdevice = PCI_ANY_ID,
2265 .setup = pci_sunix_setup,
2266 },
2267 /*
2268 * Xircom cards
2269 */
2270 {
2271 .vendor = PCI_VENDOR_ID_XIRCOM,
2272 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2273 .subvendor = PCI_ANY_ID,
2274 .subdevice = PCI_ANY_ID,
2275 .init = pci_xircom_init,
2276 .setup = pci_default_setup,
2277 },
2278 /*
2279 * Netmos cards - these may be called via parport_serial
2280 */
2281 {
2282 .vendor = PCI_VENDOR_ID_NETMOS,
2283 .device = PCI_ANY_ID,
2284 .subvendor = PCI_ANY_ID,
2285 .subdevice = PCI_ANY_ID,
2286 .init = pci_netmos_init,
2287 .setup = pci_netmos_9900_setup,
2288 },
2289 /*
2290 * EndRun Technologies
2291 */
2292 {
2293 .vendor = PCI_VENDOR_ID_ENDRUN,
2294 .device = PCI_ANY_ID,
2295 .subvendor = PCI_ANY_ID,
2296 .subdevice = PCI_ANY_ID,
2297 .init = pci_endrun_init,
2298 .setup = pci_default_setup,
2299 },
2300 /*
2301 * For Oxford Semiconductor Tornado based devices
2302 */
2303 {
2304 .vendor = PCI_VENDOR_ID_OXSEMI,
2305 .device = PCI_ANY_ID,
2306 .subvendor = PCI_ANY_ID,
2307 .subdevice = PCI_ANY_ID,
2308 .init = pci_oxsemi_tornado_init,
2309 .setup = pci_default_setup,
2310 },
2311 {
2312 .vendor = PCI_VENDOR_ID_MAINPINE,
2313 .device = PCI_ANY_ID,
2314 .subvendor = PCI_ANY_ID,
2315 .subdevice = PCI_ANY_ID,
2316 .init = pci_oxsemi_tornado_init,
2317 .setup = pci_default_setup,
2318 },
2319 {
2320 .vendor = PCI_VENDOR_ID_DIGI,
2321 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2322 .subvendor = PCI_SUBVENDOR_ID_IBM,
2323 .subdevice = PCI_ANY_ID,
2324 .init = pci_oxsemi_tornado_init,
2325 .setup = pci_default_setup,
2326 },
2327 {
2328 .vendor = PCI_VENDOR_ID_INTEL,
2329 .device = 0x8811,
2330 .subvendor = PCI_ANY_ID,
2331 .subdevice = PCI_ANY_ID,
2332 .init = pci_eg20t_init,
2333 .setup = pci_default_setup,
2334 },
2335 {
2336 .vendor = PCI_VENDOR_ID_INTEL,
2337 .device = 0x8812,
2338 .subvendor = PCI_ANY_ID,
2339 .subdevice = PCI_ANY_ID,
2340 .init = pci_eg20t_init,
2341 .setup = pci_default_setup,
2342 },
2343 {
2344 .vendor = PCI_VENDOR_ID_INTEL,
2345 .device = 0x8813,
2346 .subvendor = PCI_ANY_ID,
2347 .subdevice = PCI_ANY_ID,
2348 .init = pci_eg20t_init,
2349 .setup = pci_default_setup,
2350 },
2351 {
2352 .vendor = PCI_VENDOR_ID_INTEL,
2353 .device = 0x8814,
2354 .subvendor = PCI_ANY_ID,
2355 .subdevice = PCI_ANY_ID,
2356 .init = pci_eg20t_init,
2357 .setup = pci_default_setup,
2358 },
2359 {
2360 .vendor = 0x10DB,
2361 .device = 0x8027,
2362 .subvendor = PCI_ANY_ID,
2363 .subdevice = PCI_ANY_ID,
2364 .init = pci_eg20t_init,
2365 .setup = pci_default_setup,
2366 },
2367 {
2368 .vendor = 0x10DB,
2369 .device = 0x8028,
2370 .subvendor = PCI_ANY_ID,
2371 .subdevice = PCI_ANY_ID,
2372 .init = pci_eg20t_init,
2373 .setup = pci_default_setup,
2374 },
2375 {
2376 .vendor = 0x10DB,
2377 .device = 0x8029,
2378 .subvendor = PCI_ANY_ID,
2379 .subdevice = PCI_ANY_ID,
2380 .init = pci_eg20t_init,
2381 .setup = pci_default_setup,
2382 },
2383 {
2384 .vendor = 0x10DB,
2385 .device = 0x800C,
2386 .subvendor = PCI_ANY_ID,
2387 .subdevice = PCI_ANY_ID,
2388 .init = pci_eg20t_init,
2389 .setup = pci_default_setup,
2390 },
2391 {
2392 .vendor = 0x10DB,
2393 .device = 0x800D,
2394 .subvendor = PCI_ANY_ID,
2395 .subdevice = PCI_ANY_ID,
2396 .init = pci_eg20t_init,
2397 .setup = pci_default_setup,
2398 },
2399 /*
2400 * Cronyx Omega PCI (PLX-chip based)
2401 */
2402 {
2403 .vendor = PCI_VENDOR_ID_PLX,
2404 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2405 .subvendor = PCI_ANY_ID,
2406 .subdevice = PCI_ANY_ID,
2407 .setup = pci_omegapci_setup,
2408 },
2409 /* WCH CH353 1S1P card (16550 clone) */
2410 {
2411 .vendor = PCI_VENDOR_ID_WCH,
2412 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2413 .subvendor = PCI_ANY_ID,
2414 .subdevice = PCI_ANY_ID,
2415 .setup = pci_wch_ch353_setup,
2416 },
2417 /* WCH CH353 2S1P card (16550 clone) */
2418 {
2419 .vendor = PCI_VENDOR_ID_WCH,
2420 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2421 .subvendor = PCI_ANY_ID,
2422 .subdevice = PCI_ANY_ID,
2423 .setup = pci_wch_ch353_setup,
2424 },
2425 /* WCH CH353 4S card (16550 clone) */
2426 {
2427 .vendor = PCI_VENDOR_ID_WCH,
2428 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2429 .subvendor = PCI_ANY_ID,
2430 .subdevice = PCI_ANY_ID,
2431 .setup = pci_wch_ch353_setup,
2432 },
2433 /* WCH CH353 2S1PF card (16550 clone) */
2434 {
2435 .vendor = PCI_VENDOR_ID_WCH,
2436 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2437 .subvendor = PCI_ANY_ID,
2438 .subdevice = PCI_ANY_ID,
2439 .setup = pci_wch_ch353_setup,
2440 },
2441 /* WCH CH352 2S card (16550 clone) */
2442 {
2443 .vendor = PCI_VENDOR_ID_WCH,
2444 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2445 .subvendor = PCI_ANY_ID,
2446 .subdevice = PCI_ANY_ID,
2447 .setup = pci_wch_ch353_setup,
2448 },
2449 /* WCH CH355 4S card (16550 clone) */
2450 {
2451 .vendor = PCI_VENDOR_ID_WCH,
2452 .device = PCI_DEVICE_ID_WCH_CH355_4S,
2453 .subvendor = PCI_ANY_ID,
2454 .subdevice = PCI_ANY_ID,
2455 .setup = pci_wch_ch355_setup,
2456 },
2457 /* WCH CH382 2S card (16850 clone) */
2458 {
2459 .vendor = PCIE_VENDOR_ID_WCH,
2460 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2461 .subvendor = PCI_ANY_ID,
2462 .subdevice = PCI_ANY_ID,
2463 .setup = pci_wch_ch38x_setup,
2464 },
2465 /* WCH CH382 2S1P card (16850 clone) */
2466 {
2467 .vendor = PCIE_VENDOR_ID_WCH,
2468 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2469 .subvendor = PCI_ANY_ID,
2470 .subdevice = PCI_ANY_ID,
2471 .setup = pci_wch_ch38x_setup,
2472 },
2473 /* WCH CH384 4S card (16850 clone) */
2474 {
2475 .vendor = PCIE_VENDOR_ID_WCH,
2476 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2477 .subvendor = PCI_ANY_ID,
2478 .subdevice = PCI_ANY_ID,
2479 .setup = pci_wch_ch38x_setup,
2480 },
2481 /*
2482 * ASIX devices with FIFO bug
2483 */
2484 {
2485 .vendor = PCI_VENDOR_ID_ASIX,
2486 .device = PCI_ANY_ID,
2487 .subvendor = PCI_ANY_ID,
2488 .subdevice = PCI_ANY_ID,
2489 .setup = pci_asix_setup,
2490 },
2491 /*
2492 * Broadcom TruManage (NetXtreme)
2493 */
2494 {
2495 .vendor = PCI_VENDOR_ID_BROADCOM,
2496 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2497 .subvendor = PCI_ANY_ID,
2498 .subdevice = PCI_ANY_ID,
2499 .setup = pci_brcm_trumanage_setup,
2500 },
2501 {
2502 .vendor = 0x1c29,
2503 .device = 0x1104,
2504 .subvendor = PCI_ANY_ID,
2505 .subdevice = PCI_ANY_ID,
2506 .setup = pci_fintek_setup,
2507 .init = pci_fintek_init,
2508 },
2509 {
2510 .vendor = 0x1c29,
2511 .device = 0x1108,
2512 .subvendor = PCI_ANY_ID,
2513 .subdevice = PCI_ANY_ID,
2514 .setup = pci_fintek_setup,
2515 .init = pci_fintek_init,
2516 },
2517 {
2518 .vendor = 0x1c29,
2519 .device = 0x1112,
2520 .subvendor = PCI_ANY_ID,
2521 .subdevice = PCI_ANY_ID,
2522 .setup = pci_fintek_setup,
2523 .init = pci_fintek_init,
2524 },
2525
2526 /*
2527 * Default "match everything" terminator entry
2528 */
2529 {
2530 .vendor = PCI_ANY_ID,
2531 .device = PCI_ANY_ID,
2532 .subvendor = PCI_ANY_ID,
2533 .subdevice = PCI_ANY_ID,
2534 .setup = pci_default_setup,
2535 }
2536 };
2537
2538 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2539 {
2540 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2541 }
2542
2543 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2544 {
2545 struct pci_serial_quirk *quirk;
2546
2547 for (quirk = pci_serial_quirks; ; quirk++)
2548 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2549 quirk_id_matches(quirk->device, dev->device) &&
2550 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2551 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2552 break;
2553 return quirk;
2554 }
2555
2556 static inline int get_pci_irq(struct pci_dev *dev,
2557 const struct pciserial_board *board)
2558 {
2559 if (board->flags & FL_NOIRQ)
2560 return 0;
2561 else
2562 return dev->irq;
2563 }
2564
2565 /*
2566 * This is the configuration table for all of the PCI serial boards
2567 * which we support. It is directly indexed by the pci_board_num_t enum
2568 * value, which is encoded in the pci_device_id PCI probe table's
2569 * driver_data member.
2570 *
2571 * The makeup of these names are:
2572 * pbn_bn{_bt}_n_baud{_offsetinhex}
2573 *
2574 * bn = PCI BAR number
2575 * bt = Index using PCI BARs
2576 * n = number of serial ports
2577 * baud = baud rate
2578 * offsetinhex = offset for each sequential port (in hex)
2579 *
2580 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2581 *
2582 * Please note: in theory if n = 1, _bt infix should make no difference.
2583 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2584 */
2585 enum pci_board_num_t {
2586 pbn_default = 0,
2587
2588 pbn_b0_1_115200,
2589 pbn_b0_2_115200,
2590 pbn_b0_4_115200,
2591 pbn_b0_5_115200,
2592 pbn_b0_8_115200,
2593
2594 pbn_b0_1_921600,
2595 pbn_b0_2_921600,
2596 pbn_b0_4_921600,
2597
2598 pbn_b0_2_1130000,
2599
2600 pbn_b0_4_1152000,
2601
2602 pbn_b0_4_1250000,
2603
2604 pbn_b0_2_1843200,
2605 pbn_b0_4_1843200,
2606
2607 pbn_b0_1_4000000,
2608
2609 pbn_b0_bt_1_115200,
2610 pbn_b0_bt_2_115200,
2611 pbn_b0_bt_4_115200,
2612 pbn_b0_bt_8_115200,
2613
2614 pbn_b0_bt_1_460800,
2615 pbn_b0_bt_2_460800,
2616 pbn_b0_bt_4_460800,
2617
2618 pbn_b0_bt_1_921600,
2619 pbn_b0_bt_2_921600,
2620 pbn_b0_bt_4_921600,
2621 pbn_b0_bt_8_921600,
2622
2623 pbn_b1_1_115200,
2624 pbn_b1_2_115200,
2625 pbn_b1_4_115200,
2626 pbn_b1_8_115200,
2627 pbn_b1_16_115200,
2628
2629 pbn_b1_1_921600,
2630 pbn_b1_2_921600,
2631 pbn_b1_4_921600,
2632 pbn_b1_8_921600,
2633
2634 pbn_b1_2_1250000,
2635
2636 pbn_b1_bt_1_115200,
2637 pbn_b1_bt_2_115200,
2638 pbn_b1_bt_4_115200,
2639
2640 pbn_b1_bt_2_921600,
2641
2642 pbn_b1_1_1382400,
2643 pbn_b1_2_1382400,
2644 pbn_b1_4_1382400,
2645 pbn_b1_8_1382400,
2646
2647 pbn_b2_1_115200,
2648 pbn_b2_2_115200,
2649 pbn_b2_4_115200,
2650 pbn_b2_8_115200,
2651
2652 pbn_b2_1_460800,
2653 pbn_b2_4_460800,
2654 pbn_b2_8_460800,
2655 pbn_b2_16_460800,
2656
2657 pbn_b2_1_921600,
2658 pbn_b2_4_921600,
2659 pbn_b2_8_921600,
2660
2661 pbn_b2_8_1152000,
2662
2663 pbn_b2_bt_1_115200,
2664 pbn_b2_bt_2_115200,
2665 pbn_b2_bt_4_115200,
2666
2667 pbn_b2_bt_2_921600,
2668 pbn_b2_bt_4_921600,
2669
2670 pbn_b3_2_115200,
2671 pbn_b3_4_115200,
2672 pbn_b3_8_115200,
2673
2674 pbn_b4_bt_2_921600,
2675 pbn_b4_bt_4_921600,
2676 pbn_b4_bt_8_921600,
2677
2678 /*
2679 * Board-specific versions.
2680 */
2681 pbn_panacom,
2682 pbn_panacom2,
2683 pbn_panacom4,
2684 pbn_plx_romulus,
2685 pbn_endrun_2_4000000,
2686 pbn_oxsemi,
2687 pbn_oxsemi_1_4000000,
2688 pbn_oxsemi_2_4000000,
2689 pbn_oxsemi_4_4000000,
2690 pbn_oxsemi_8_4000000,
2691 pbn_intel_i960,
2692 pbn_sgi_ioc3,
2693 pbn_computone_4,
2694 pbn_computone_6,
2695 pbn_computone_8,
2696 pbn_sbsxrsio,
2697 pbn_pasemi_1682M,
2698 pbn_ni8430_2,
2699 pbn_ni8430_4,
2700 pbn_ni8430_8,
2701 pbn_ni8430_16,
2702 pbn_ADDIDATA_PCIe_1_3906250,
2703 pbn_ADDIDATA_PCIe_2_3906250,
2704 pbn_ADDIDATA_PCIe_4_3906250,
2705 pbn_ADDIDATA_PCIe_8_3906250,
2706 pbn_ce4100_1_115200,
2707 pbn_omegapci,
2708 pbn_NETMOS9900_2s_115200,
2709 pbn_brcm_trumanage,
2710 pbn_fintek_4,
2711 pbn_fintek_8,
2712 pbn_fintek_12,
2713 pbn_wch382_2,
2714 pbn_wch384_4,
2715 pbn_pericom_PI7C9X7951,
2716 pbn_pericom_PI7C9X7952,
2717 pbn_pericom_PI7C9X7954,
2718 pbn_pericom_PI7C9X7958,
2719 pbn_sunix_pci_1s,
2720 pbn_sunix_pci_2s,
2721 pbn_sunix_pci_4s,
2722 pbn_sunix_pci_8s,
2723 pbn_sunix_pci_16s,
2724 };
2725
2726 /*
2727 * uart_offset - the space between channels
2728 * reg_shift - describes how the UART registers are mapped
2729 * to PCI memory by the card.
2730 * For example IER register on SBS, Inc. PMC-OctPro is located at
2731 * offset 0x10 from the UART base, while UART_IER is defined as 1
2732 * in include/linux/serial_reg.h,
2733 * see first lines of serial_in() and serial_out() in 8250.c
2734 */
2735
2736 static struct pciserial_board pci_boards[] = {
2737 [pbn_default] = {
2738 .flags = FL_BASE0,
2739 .num_ports = 1,
2740 .base_baud = 115200,
2741 .uart_offset = 8,
2742 },
2743 [pbn_b0_1_115200] = {
2744 .flags = FL_BASE0,
2745 .num_ports = 1,
2746 .base_baud = 115200,
2747 .uart_offset = 8,
2748 },
2749 [pbn_b0_2_115200] = {
2750 .flags = FL_BASE0,
2751 .num_ports = 2,
2752 .base_baud = 115200,
2753 .uart_offset = 8,
2754 },
2755 [pbn_b0_4_115200] = {
2756 .flags = FL_BASE0,
2757 .num_ports = 4,
2758 .base_baud = 115200,
2759 .uart_offset = 8,
2760 },
2761 [pbn_b0_5_115200] = {
2762 .flags = FL_BASE0,
2763 .num_ports = 5,
2764 .base_baud = 115200,
2765 .uart_offset = 8,
2766 },
2767 [pbn_b0_8_115200] = {
2768 .flags = FL_BASE0,
2769 .num_ports = 8,
2770 .base_baud = 115200,
2771 .uart_offset = 8,
2772 },
2773 [pbn_b0_1_921600] = {
2774 .flags = FL_BASE0,
2775 .num_ports = 1,
2776 .base_baud = 921600,
2777 .uart_offset = 8,
2778 },
2779 [pbn_b0_2_921600] = {
2780 .flags = FL_BASE0,
2781 .num_ports = 2,
2782 .base_baud = 921600,
2783 .uart_offset = 8,
2784 },
2785 [pbn_b0_4_921600] = {
2786 .flags = FL_BASE0,
2787 .num_ports = 4,
2788 .base_baud = 921600,
2789 .uart_offset = 8,
2790 },
2791
2792 [pbn_b0_2_1130000] = {
2793 .flags = FL_BASE0,
2794 .num_ports = 2,
2795 .base_baud = 1130000,
2796 .uart_offset = 8,
2797 },
2798
2799 [pbn_b0_4_1152000] = {
2800 .flags = FL_BASE0,
2801 .num_ports = 4,
2802 .base_baud = 1152000,
2803 .uart_offset = 8,
2804 },
2805
2806 [pbn_b0_4_1250000] = {
2807 .flags = FL_BASE0,
2808 .num_ports = 4,
2809 .base_baud = 1250000,
2810 .uart_offset = 8,
2811 },
2812
2813 [pbn_b0_2_1843200] = {
2814 .flags = FL_BASE0,
2815 .num_ports = 2,
2816 .base_baud = 1843200,
2817 .uart_offset = 8,
2818 },
2819 [pbn_b0_4_1843200] = {
2820 .flags = FL_BASE0,
2821 .num_ports = 4,
2822 .base_baud = 1843200,
2823 .uart_offset = 8,
2824 },
2825
2826 [pbn_b0_1_4000000] = {
2827 .flags = FL_BASE0,
2828 .num_ports = 1,
2829 .base_baud = 4000000,
2830 .uart_offset = 8,
2831 },
2832
2833 [pbn_b0_bt_1_115200] = {
2834 .flags = FL_BASE0|FL_BASE_BARS,
2835 .num_ports = 1,
2836 .base_baud = 115200,
2837 .uart_offset = 8,
2838 },
2839 [pbn_b0_bt_2_115200] = {
2840 .flags = FL_BASE0|FL_BASE_BARS,
2841 .num_ports = 2,
2842 .base_baud = 115200,
2843 .uart_offset = 8,
2844 },
2845 [pbn_b0_bt_4_115200] = {
2846 .flags = FL_BASE0|FL_BASE_BARS,
2847 .num_ports = 4,
2848 .base_baud = 115200,
2849 .uart_offset = 8,
2850 },
2851 [pbn_b0_bt_8_115200] = {
2852 .flags = FL_BASE0|FL_BASE_BARS,
2853 .num_ports = 8,
2854 .base_baud = 115200,
2855 .uart_offset = 8,
2856 },
2857
2858 [pbn_b0_bt_1_460800] = {
2859 .flags = FL_BASE0|FL_BASE_BARS,
2860 .num_ports = 1,
2861 .base_baud = 460800,
2862 .uart_offset = 8,
2863 },
2864 [pbn_b0_bt_2_460800] = {
2865 .flags = FL_BASE0|FL_BASE_BARS,
2866 .num_ports = 2,
2867 .base_baud = 460800,
2868 .uart_offset = 8,
2869 },
2870 [pbn_b0_bt_4_460800] = {
2871 .flags = FL_BASE0|FL_BASE_BARS,
2872 .num_ports = 4,
2873 .base_baud = 460800,
2874 .uart_offset = 8,
2875 },
2876
2877 [pbn_b0_bt_1_921600] = {
2878 .flags = FL_BASE0|FL_BASE_BARS,
2879 .num_ports = 1,
2880 .base_baud = 921600,
2881 .uart_offset = 8,
2882 },
2883 [pbn_b0_bt_2_921600] = {
2884 .flags = FL_BASE0|FL_BASE_BARS,
2885 .num_ports = 2,
2886 .base_baud = 921600,
2887 .uart_offset = 8,
2888 },
2889 [pbn_b0_bt_4_921600] = {
2890 .flags = FL_BASE0|FL_BASE_BARS,
2891 .num_ports = 4,
2892 .base_baud = 921600,
2893 .uart_offset = 8,
2894 },
2895 [pbn_b0_bt_8_921600] = {
2896 .flags = FL_BASE0|FL_BASE_BARS,
2897 .num_ports = 8,
2898 .base_baud = 921600,
2899 .uart_offset = 8,
2900 },
2901
2902 [pbn_b1_1_115200] = {
2903 .flags = FL_BASE1,
2904 .num_ports = 1,
2905 .base_baud = 115200,
2906 .uart_offset = 8,
2907 },
2908 [pbn_b1_2_115200] = {
2909 .flags = FL_BASE1,
2910 .num_ports = 2,
2911 .base_baud = 115200,
2912 .uart_offset = 8,
2913 },
2914 [pbn_b1_4_115200] = {
2915 .flags = FL_BASE1,
2916 .num_ports = 4,
2917 .base_baud = 115200,
2918 .uart_offset = 8,
2919 },
2920 [pbn_b1_8_115200] = {
2921 .flags = FL_BASE1,
2922 .num_ports = 8,
2923 .base_baud = 115200,
2924 .uart_offset = 8,
2925 },
2926 [pbn_b1_16_115200] = {
2927 .flags = FL_BASE1,
2928 .num_ports = 16,
2929 .base_baud = 115200,
2930 .uart_offset = 8,
2931 },
2932
2933 [pbn_b1_1_921600] = {
2934 .flags = FL_BASE1,
2935 .num_ports = 1,
2936 .base_baud = 921600,
2937 .uart_offset = 8,
2938 },
2939 [pbn_b1_2_921600] = {
2940 .flags = FL_BASE1,
2941 .num_ports = 2,
2942 .base_baud = 921600,
2943 .uart_offset = 8,
2944 },
2945 [pbn_b1_4_921600] = {
2946 .flags = FL_BASE1,
2947 .num_ports = 4,
2948 .base_baud = 921600,
2949 .uart_offset = 8,
2950 },
2951 [pbn_b1_8_921600] = {
2952 .flags = FL_BASE1,
2953 .num_ports = 8,
2954 .base_baud = 921600,
2955 .uart_offset = 8,
2956 },
2957 [pbn_b1_2_1250000] = {
2958 .flags = FL_BASE1,
2959 .num_ports = 2,
2960 .base_baud = 1250000,
2961 .uart_offset = 8,
2962 },
2963
2964 [pbn_b1_bt_1_115200] = {
2965 .flags = FL_BASE1|FL_BASE_BARS,
2966 .num_ports = 1,
2967 .base_baud = 115200,
2968 .uart_offset = 8,
2969 },
2970 [pbn_b1_bt_2_115200] = {
2971 .flags = FL_BASE1|FL_BASE_BARS,
2972 .num_ports = 2,
2973 .base_baud = 115200,
2974 .uart_offset = 8,
2975 },
2976 [pbn_b1_bt_4_115200] = {
2977 .flags = FL_BASE1|FL_BASE_BARS,
2978 .num_ports = 4,
2979 .base_baud = 115200,
2980 .uart_offset = 8,
2981 },
2982
2983 [pbn_b1_bt_2_921600] = {
2984 .flags = FL_BASE1|FL_BASE_BARS,
2985 .num_ports = 2,
2986 .base_baud = 921600,
2987 .uart_offset = 8,
2988 },
2989
2990 [pbn_b1_1_1382400] = {
2991 .flags = FL_BASE1,
2992 .num_ports = 1,
2993 .base_baud = 1382400,
2994 .uart_offset = 8,
2995 },
2996 [pbn_b1_2_1382400] = {
2997 .flags = FL_BASE1,
2998 .num_ports = 2,
2999 .base_baud = 1382400,
3000 .uart_offset = 8,
3001 },
3002 [pbn_b1_4_1382400] = {
3003 .flags = FL_BASE1,
3004 .num_ports = 4,
3005 .base_baud = 1382400,
3006 .uart_offset = 8,
3007 },
3008 [pbn_b1_8_1382400] = {
3009 .flags = FL_BASE1,
3010 .num_ports = 8,
3011 .base_baud = 1382400,
3012 .uart_offset = 8,
3013 },
3014
3015 [pbn_b2_1_115200] = {
3016 .flags = FL_BASE2,
3017 .num_ports = 1,
3018 .base_baud = 115200,
3019 .uart_offset = 8,
3020 },
3021 [pbn_b2_2_115200] = {
3022 .flags = FL_BASE2,
3023 .num_ports = 2,
3024 .base_baud = 115200,
3025 .uart_offset = 8,
3026 },
3027 [pbn_b2_4_115200] = {
3028 .flags = FL_BASE2,
3029 .num_ports = 4,
3030 .base_baud = 115200,
3031 .uart_offset = 8,
3032 },
3033 [pbn_b2_8_115200] = {
3034 .flags = FL_BASE2,
3035 .num_ports = 8,
3036 .base_baud = 115200,
3037 .uart_offset = 8,
3038 },
3039
3040 [pbn_b2_1_460800] = {
3041 .flags = FL_BASE2,
3042 .num_ports = 1,
3043 .base_baud = 460800,
3044 .uart_offset = 8,
3045 },
3046 [pbn_b2_4_460800] = {
3047 .flags = FL_BASE2,
3048 .num_ports = 4,
3049 .base_baud = 460800,
3050 .uart_offset = 8,
3051 },
3052 [pbn_b2_8_460800] = {
3053 .flags = FL_BASE2,
3054 .num_ports = 8,
3055 .base_baud = 460800,
3056 .uart_offset = 8,
3057 },
3058 [pbn_b2_16_460800] = {
3059 .flags = FL_BASE2,
3060 .num_ports = 16,
3061 .base_baud = 460800,
3062 .uart_offset = 8,
3063 },
3064
3065 [pbn_b2_1_921600] = {
3066 .flags = FL_BASE2,
3067 .num_ports = 1,
3068 .base_baud = 921600,
3069 .uart_offset = 8,
3070 },
3071 [pbn_b2_4_921600] = {
3072 .flags = FL_BASE2,
3073 .num_ports = 4,
3074 .base_baud = 921600,
3075 .uart_offset = 8,
3076 },
3077 [pbn_b2_8_921600] = {
3078 .flags = FL_BASE2,
3079 .num_ports = 8,
3080 .base_baud = 921600,
3081 .uart_offset = 8,
3082 },
3083
3084 [pbn_b2_8_1152000] = {
3085 .flags = FL_BASE2,
3086 .num_ports = 8,
3087 .base_baud = 1152000,
3088 .uart_offset = 8,
3089 },
3090
3091 [pbn_b2_bt_1_115200] = {
3092 .flags = FL_BASE2|FL_BASE_BARS,
3093 .num_ports = 1,
3094 .base_baud = 115200,
3095 .uart_offset = 8,
3096 },
3097 [pbn_b2_bt_2_115200] = {
3098 .flags = FL_BASE2|FL_BASE_BARS,
3099 .num_ports = 2,
3100 .base_baud = 115200,
3101 .uart_offset = 8,
3102 },
3103 [pbn_b2_bt_4_115200] = {
3104 .flags = FL_BASE2|FL_BASE_BARS,
3105 .num_ports = 4,
3106 .base_baud = 115200,
3107 .uart_offset = 8,
3108 },
3109
3110 [pbn_b2_bt_2_921600] = {
3111 .flags = FL_BASE2|FL_BASE_BARS,
3112 .num_ports = 2,
3113 .base_baud = 921600,
3114 .uart_offset = 8,
3115 },
3116 [pbn_b2_bt_4_921600] = {
3117 .flags = FL_BASE2|FL_BASE_BARS,
3118 .num_ports = 4,
3119 .base_baud = 921600,
3120 .uart_offset = 8,
3121 },
3122
3123 [pbn_b3_2_115200] = {
3124 .flags = FL_BASE3,
3125 .num_ports = 2,
3126 .base_baud = 115200,
3127 .uart_offset = 8,
3128 },
3129 [pbn_b3_4_115200] = {
3130 .flags = FL_BASE3,
3131 .num_ports = 4,
3132 .base_baud = 115200,
3133 .uart_offset = 8,
3134 },
3135 [pbn_b3_8_115200] = {
3136 .flags = FL_BASE3,
3137 .num_ports = 8,
3138 .base_baud = 115200,
3139 .uart_offset = 8,
3140 },
3141
3142 [pbn_b4_bt_2_921600] = {
3143 .flags = FL_BASE4,
3144 .num_ports = 2,
3145 .base_baud = 921600,
3146 .uart_offset = 8,
3147 },
3148 [pbn_b4_bt_4_921600] = {
3149 .flags = FL_BASE4,
3150 .num_ports = 4,
3151 .base_baud = 921600,
3152 .uart_offset = 8,
3153 },
3154 [pbn_b4_bt_8_921600] = {
3155 .flags = FL_BASE4,
3156 .num_ports = 8,
3157 .base_baud = 921600,
3158 .uart_offset = 8,
3159 },
3160
3161 /*
3162 * Entries following this are board-specific.
3163 */
3164
3165 /*
3166 * Panacom - IOMEM
3167 */
3168 [pbn_panacom] = {
3169 .flags = FL_BASE2,
3170 .num_ports = 2,
3171 .base_baud = 921600,
3172 .uart_offset = 0x400,
3173 .reg_shift = 7,
3174 },
3175 [pbn_panacom2] = {
3176 .flags = FL_BASE2|FL_BASE_BARS,
3177 .num_ports = 2,
3178 .base_baud = 921600,
3179 .uart_offset = 0x400,
3180 .reg_shift = 7,
3181 },
3182 [pbn_panacom4] = {
3183 .flags = FL_BASE2|FL_BASE_BARS,
3184 .num_ports = 4,
3185 .base_baud = 921600,
3186 .uart_offset = 0x400,
3187 .reg_shift = 7,
3188 },
3189
3190 /* I think this entry is broken - the first_offset looks wrong --rmk */
3191 [pbn_plx_romulus] = {
3192 .flags = FL_BASE2,
3193 .num_ports = 4,
3194 .base_baud = 921600,
3195 .uart_offset = 8 << 2,
3196 .reg_shift = 2,
3197 .first_offset = 0x03,
3198 },
3199
3200 /*
3201 * EndRun Technologies
3202 * Uses the size of PCI Base region 0 to
3203 * signal now many ports are available
3204 * 2 port 952 Uart support
3205 */
3206 [pbn_endrun_2_4000000] = {
3207 .flags = FL_BASE0,
3208 .num_ports = 2,
3209 .base_baud = 4000000,
3210 .uart_offset = 0x200,
3211 .first_offset = 0x1000,
3212 },
3213
3214 /*
3215 * This board uses the size of PCI Base region 0 to
3216 * signal now many ports are available
3217 */
3218 [pbn_oxsemi] = {
3219 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3220 .num_ports = 32,
3221 .base_baud = 115200,
3222 .uart_offset = 8,
3223 },
3224 [pbn_oxsemi_1_4000000] = {
3225 .flags = FL_BASE0,
3226 .num_ports = 1,
3227 .base_baud = 4000000,
3228 .uart_offset = 0x200,
3229 .first_offset = 0x1000,
3230 },
3231 [pbn_oxsemi_2_4000000] = {
3232 .flags = FL_BASE0,
3233 .num_ports = 2,
3234 .base_baud = 4000000,
3235 .uart_offset = 0x200,
3236 .first_offset = 0x1000,
3237 },
3238 [pbn_oxsemi_4_4000000] = {
3239 .flags = FL_BASE0,
3240 .num_ports = 4,
3241 .base_baud = 4000000,
3242 .uart_offset = 0x200,
3243 .first_offset = 0x1000,
3244 },
3245 [pbn_oxsemi_8_4000000] = {
3246 .flags = FL_BASE0,
3247 .num_ports = 8,
3248 .base_baud = 4000000,
3249 .uart_offset = 0x200,
3250 .first_offset = 0x1000,
3251 },
3252
3253
3254 /*
3255 * EKF addition for i960 Boards form EKF with serial port.
3256 * Max 256 ports.
3257 */
3258 [pbn_intel_i960] = {
3259 .flags = FL_BASE0,
3260 .num_ports = 32,
3261 .base_baud = 921600,
3262 .uart_offset = 8 << 2,
3263 .reg_shift = 2,
3264 .first_offset = 0x10000,
3265 },
3266 [pbn_sgi_ioc3] = {
3267 .flags = FL_BASE0|FL_NOIRQ,
3268 .num_ports = 1,
3269 .base_baud = 458333,
3270 .uart_offset = 8,
3271 .reg_shift = 0,
3272 .first_offset = 0x20178,
3273 },
3274
3275 /*
3276 * Computone - uses IOMEM.
3277 */
3278 [pbn_computone_4] = {
3279 .flags = FL_BASE0,
3280 .num_ports = 4,
3281 .base_baud = 921600,
3282 .uart_offset = 0x40,
3283 .reg_shift = 2,
3284 .first_offset = 0x200,
3285 },
3286 [pbn_computone_6] = {
3287 .flags = FL_BASE0,
3288 .num_ports = 6,
3289 .base_baud = 921600,
3290 .uart_offset = 0x40,
3291 .reg_shift = 2,
3292 .first_offset = 0x200,
3293 },
3294 [pbn_computone_8] = {
3295 .flags = FL_BASE0,
3296 .num_ports = 8,
3297 .base_baud = 921600,
3298 .uart_offset = 0x40,
3299 .reg_shift = 2,
3300 .first_offset = 0x200,
3301 },
3302 [pbn_sbsxrsio] = {
3303 .flags = FL_BASE0,
3304 .num_ports = 8,
3305 .base_baud = 460800,
3306 .uart_offset = 256,
3307 .reg_shift = 4,
3308 },
3309 /*
3310 * PA Semi PWRficient PA6T-1682M on-chip UART
3311 */
3312 [pbn_pasemi_1682M] = {
3313 .flags = FL_BASE0,
3314 .num_ports = 1,
3315 .base_baud = 8333333,
3316 },
3317 /*
3318 * National Instruments 843x
3319 */
3320 [pbn_ni8430_16] = {
3321 .flags = FL_BASE0,
3322 .num_ports = 16,
3323 .base_baud = 3686400,
3324 .uart_offset = 0x10,
3325 .first_offset = 0x800,
3326 },
3327 [pbn_ni8430_8] = {
3328 .flags = FL_BASE0,
3329 .num_ports = 8,
3330 .base_baud = 3686400,
3331 .uart_offset = 0x10,
3332 .first_offset = 0x800,
3333 },
3334 [pbn_ni8430_4] = {
3335 .flags = FL_BASE0,
3336 .num_ports = 4,
3337 .base_baud = 3686400,
3338 .uart_offset = 0x10,
3339 .first_offset = 0x800,
3340 },
3341 [pbn_ni8430_2] = {
3342 .flags = FL_BASE0,
3343 .num_ports = 2,
3344 .base_baud = 3686400,
3345 .uart_offset = 0x10,
3346 .first_offset = 0x800,
3347 },
3348 /*
3349 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3350 */
3351 [pbn_ADDIDATA_PCIe_1_3906250] = {
3352 .flags = FL_BASE0,
3353 .num_ports = 1,
3354 .base_baud = 3906250,
3355 .uart_offset = 0x200,
3356 .first_offset = 0x1000,
3357 },
3358 [pbn_ADDIDATA_PCIe_2_3906250] = {
3359 .flags = FL_BASE0,
3360 .num_ports = 2,
3361 .base_baud = 3906250,
3362 .uart_offset = 0x200,
3363 .first_offset = 0x1000,
3364 },
3365 [pbn_ADDIDATA_PCIe_4_3906250] = {
3366 .flags = FL_BASE0,
3367 .num_ports = 4,
3368 .base_baud = 3906250,
3369 .uart_offset = 0x200,
3370 .first_offset = 0x1000,
3371 },
3372 [pbn_ADDIDATA_PCIe_8_3906250] = {
3373 .flags = FL_BASE0,
3374 .num_ports = 8,
3375 .base_baud = 3906250,
3376 .uart_offset = 0x200,
3377 .first_offset = 0x1000,
3378 },
3379 [pbn_ce4100_1_115200] = {
3380 .flags = FL_BASE_BARS,
3381 .num_ports = 2,
3382 .base_baud = 921600,
3383 .reg_shift = 2,
3384 },
3385 [pbn_omegapci] = {
3386 .flags = FL_BASE0,
3387 .num_ports = 8,
3388 .base_baud = 115200,
3389 .uart_offset = 0x200,
3390 },
3391 [pbn_NETMOS9900_2s_115200] = {
3392 .flags = FL_BASE0,
3393 .num_ports = 2,
3394 .base_baud = 115200,
3395 },
3396 [pbn_brcm_trumanage] = {
3397 .flags = FL_BASE0,
3398 .num_ports = 1,
3399 .reg_shift = 2,
3400 .base_baud = 115200,
3401 },
3402 [pbn_fintek_4] = {
3403 .num_ports = 4,
3404 .uart_offset = 8,
3405 .base_baud = 115200,
3406 .first_offset = 0x40,
3407 },
3408 [pbn_fintek_8] = {
3409 .num_ports = 8,
3410 .uart_offset = 8,
3411 .base_baud = 115200,
3412 .first_offset = 0x40,
3413 },
3414 [pbn_fintek_12] = {
3415 .num_ports = 12,
3416 .uart_offset = 8,
3417 .base_baud = 115200,
3418 .first_offset = 0x40,
3419 },
3420 [pbn_wch382_2] = {
3421 .flags = FL_BASE0,
3422 .num_ports = 2,
3423 .base_baud = 115200,
3424 .uart_offset = 8,
3425 .first_offset = 0xC0,
3426 },
3427 [pbn_wch384_4] = {
3428 .flags = FL_BASE0,
3429 .num_ports = 4,
3430 .base_baud = 115200,
3431 .uart_offset = 8,
3432 .first_offset = 0xC0,
3433 },
3434 /*
3435 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3436 */
3437 [pbn_pericom_PI7C9X7951] = {
3438 .flags = FL_BASE0,
3439 .num_ports = 1,
3440 .base_baud = 921600,
3441 .uart_offset = 0x8,
3442 },
3443 [pbn_pericom_PI7C9X7952] = {
3444 .flags = FL_BASE0,
3445 .num_ports = 2,
3446 .base_baud = 921600,
3447 .uart_offset = 0x8,
3448 },
3449 [pbn_pericom_PI7C9X7954] = {
3450 .flags = FL_BASE0,
3451 .num_ports = 4,
3452 .base_baud = 921600,
3453 .uart_offset = 0x8,
3454 },
3455 [pbn_pericom_PI7C9X7958] = {
3456 .flags = FL_BASE0,
3457 .num_ports = 8,
3458 .base_baud = 921600,
3459 .uart_offset = 0x8,
3460 },
3461 [pbn_sunix_pci_1s] = {
3462 .num_ports = 1,
3463 .base_baud = 921600,
3464 .uart_offset = 0x8,
3465 },
3466 [pbn_sunix_pci_2s] = {
3467 .num_ports = 2,
3468 .base_baud = 921600,
3469 .uart_offset = 0x8,
3470 },
3471 [pbn_sunix_pci_4s] = {
3472 .num_ports = 4,
3473 .base_baud = 921600,
3474 .uart_offset = 0x8,
3475 },
3476 [pbn_sunix_pci_8s] = {
3477 .num_ports = 8,
3478 .base_baud = 921600,
3479 .uart_offset = 0x8,
3480 },
3481 [pbn_sunix_pci_16s] = {
3482 .num_ports = 16,
3483 .base_baud = 921600,
3484 .uart_offset = 0x8,
3485 },
3486 };
3487
3488 static const struct pci_device_id blacklist[] = {
3489 /* softmodems */
3490 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3491 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3492 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3493
3494 /* multi-io cards handled by parport_serial */
3495 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3496 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3497 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3498
3499 /* Moxa Smartio MUE boards handled by 8250_moxa */
3500 { PCI_VDEVICE(MOXA, 0x1024), },
3501 { PCI_VDEVICE(MOXA, 0x1025), },
3502 { PCI_VDEVICE(MOXA, 0x1045), },
3503 { PCI_VDEVICE(MOXA, 0x1144), },
3504 { PCI_VDEVICE(MOXA, 0x1160), },
3505 { PCI_VDEVICE(MOXA, 0x1161), },
3506 { PCI_VDEVICE(MOXA, 0x1182), },
3507 { PCI_VDEVICE(MOXA, 0x1183), },
3508 { PCI_VDEVICE(MOXA, 0x1322), },
3509 { PCI_VDEVICE(MOXA, 0x1342), },
3510 { PCI_VDEVICE(MOXA, 0x1381), },
3511 { PCI_VDEVICE(MOXA, 0x1683), },
3512
3513 /* Intel platforms with MID UART */
3514 { PCI_VDEVICE(INTEL, 0x081b), },
3515 { PCI_VDEVICE(INTEL, 0x081c), },
3516 { PCI_VDEVICE(INTEL, 0x081d), },
3517 { PCI_VDEVICE(INTEL, 0x1191), },
3518 { PCI_VDEVICE(INTEL, 0x18d8), },
3519 { PCI_VDEVICE(INTEL, 0x19d8), },
3520
3521 /* Intel platforms with DesignWare UART */
3522 { PCI_VDEVICE(INTEL, 0x0936), },
3523 { PCI_VDEVICE(INTEL, 0x0f0a), },
3524 { PCI_VDEVICE(INTEL, 0x0f0c), },
3525 { PCI_VDEVICE(INTEL, 0x228a), },
3526 { PCI_VDEVICE(INTEL, 0x228c), },
3527 { PCI_VDEVICE(INTEL, 0x9ce3), },
3528 { PCI_VDEVICE(INTEL, 0x9ce4), },
3529
3530 /* Exar devices */
3531 { PCI_VDEVICE(EXAR, PCI_ANY_ID), },
3532 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), },
3533 };
3534
3535 static int serial_pci_is_class_communication(struct pci_dev *dev)
3536 {
3537 /*
3538 * If it is not a communications device or the programming
3539 * interface is greater than 6, give up.
3540 */
3541 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3542 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
3543 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3544 (dev->class & 0xff) > 6)
3545 return -ENODEV;
3546
3547 return 0;
3548 }
3549
3550 static int serial_pci_is_blacklisted(struct pci_dev *dev)
3551 {
3552 const struct pci_device_id *bldev;
3553
3554 /*
3555 * Do not access blacklisted devices that are known not to
3556 * feature serial ports or are handled by other modules.
3557 */
3558 for (bldev = blacklist;
3559 bldev < blacklist + ARRAY_SIZE(blacklist);
3560 bldev++) {
3561 if (dev->vendor == bldev->vendor &&
3562 dev->device == bldev->device)
3563 return -ENODEV;
3564 }
3565
3566 return 0;
3567 }
3568
3569 /*
3570 * Given a complete unknown PCI device, try to use some heuristics to
3571 * guess what the configuration might be, based on the pitiful PCI
3572 * serial specs. Returns 0 on success, -ENODEV on failure.
3573 */
3574 static int
3575 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3576 {
3577 int num_iomem, num_port, first_port = -1, i;
3578 int rc;
3579
3580 rc = serial_pci_is_class_communication(dev);
3581 if (rc)
3582 return rc;
3583
3584 /*
3585 * Should we try to make guesses for multiport serial devices later?
3586 */
3587 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
3588 return -ENODEV;
3589
3590 num_iomem = num_port = 0;
3591 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3592 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3593 num_port++;
3594 if (first_port == -1)
3595 first_port = i;
3596 }
3597 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3598 num_iomem++;
3599 }
3600
3601 /*
3602 * If there is 1 or 0 iomem regions, and exactly one port,
3603 * use it. We guess the number of ports based on the IO
3604 * region size.
3605 */
3606 if (num_iomem <= 1 && num_port == 1) {
3607 board->flags = first_port;
3608 board->num_ports = pci_resource_len(dev, first_port) / 8;
3609 return 0;
3610 }
3611
3612 /*
3613 * Now guess if we've got a board which indexes by BARs.
3614 * Each IO BAR should be 8 bytes, and they should follow
3615 * consecutively.
3616 */
3617 first_port = -1;
3618 num_port = 0;
3619 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3620 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3621 pci_resource_len(dev, i) == 8 &&
3622 (first_port == -1 || (first_port + num_port) == i)) {
3623 num_port++;
3624 if (first_port == -1)
3625 first_port = i;
3626 }
3627 }
3628
3629 if (num_port > 1) {
3630 board->flags = first_port | FL_BASE_BARS;
3631 board->num_ports = num_port;
3632 return 0;
3633 }
3634
3635 return -ENODEV;
3636 }
3637
3638 static inline int
3639 serial_pci_matches(const struct pciserial_board *board,
3640 const struct pciserial_board *guessed)
3641 {
3642 return
3643 board->num_ports == guessed->num_ports &&
3644 board->base_baud == guessed->base_baud &&
3645 board->uart_offset == guessed->uart_offset &&
3646 board->reg_shift == guessed->reg_shift &&
3647 board->first_offset == guessed->first_offset;
3648 }
3649
3650 struct serial_private *
3651 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3652 {
3653 struct uart_8250_port uart;
3654 struct serial_private *priv;
3655 struct pci_serial_quirk *quirk;
3656 int rc, nr_ports, i;
3657
3658 nr_ports = board->num_ports;
3659
3660 /*
3661 * Find an init and setup quirks.
3662 */
3663 quirk = find_quirk(dev);
3664
3665 /*
3666 * Run the new-style initialization function.
3667 * The initialization function returns:
3668 * <0 - error
3669 * 0 - use board->num_ports
3670 * >0 - number of ports
3671 */
3672 if (quirk->init) {
3673 rc = quirk->init(dev);
3674 if (rc < 0) {
3675 priv = ERR_PTR(rc);
3676 goto err_out;
3677 }
3678 if (rc)
3679 nr_ports = rc;
3680 }
3681
3682 priv = kzalloc(sizeof(struct serial_private) +
3683 sizeof(unsigned int) * nr_ports,
3684 GFP_KERNEL);
3685 if (!priv) {
3686 priv = ERR_PTR(-ENOMEM);
3687 goto err_deinit;
3688 }
3689
3690 priv->dev = dev;
3691 priv->quirk = quirk;
3692
3693 memset(&uart, 0, sizeof(uart));
3694 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3695 uart.port.uartclk = board->base_baud * 16;
3696 uart.port.irq = get_pci_irq(dev, board);
3697 uart.port.dev = &dev->dev;
3698
3699 for (i = 0; i < nr_ports; i++) {
3700 if (quirk->setup(priv, board, &uart, i))
3701 break;
3702
3703 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3704 uart.port.iobase, uart.port.irq, uart.port.iotype);
3705
3706 priv->line[i] = serial8250_register_8250_port(&uart);
3707 if (priv->line[i] < 0) {
3708 dev_err(&dev->dev,
3709 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3710 uart.port.iobase, uart.port.irq,
3711 uart.port.iotype, priv->line[i]);
3712 break;
3713 }
3714 }
3715 priv->nr = i;
3716 priv->board = board;
3717 return priv;
3718
3719 err_deinit:
3720 if (quirk->exit)
3721 quirk->exit(dev);
3722 err_out:
3723 return priv;
3724 }
3725 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3726
3727 static void pciserial_detach_ports(struct serial_private *priv)
3728 {
3729 struct pci_serial_quirk *quirk;
3730 int i;
3731
3732 for (i = 0; i < priv->nr; i++)
3733 serial8250_unregister_port(priv->line[i]);
3734
3735 /*
3736 * Find the exit quirks.
3737 */
3738 quirk = find_quirk(priv->dev);
3739 if (quirk->exit)
3740 quirk->exit(priv->dev);
3741 }
3742
3743 void pciserial_remove_ports(struct serial_private *priv)
3744 {
3745 pciserial_detach_ports(priv);
3746 kfree(priv);
3747 }
3748 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3749
3750 void pciserial_suspend_ports(struct serial_private *priv)
3751 {
3752 int i;
3753
3754 for (i = 0; i < priv->nr; i++)
3755 if (priv->line[i] >= 0)
3756 serial8250_suspend_port(priv->line[i]);
3757
3758 /*
3759 * Ensure that every init quirk is properly torn down
3760 */
3761 if (priv->quirk->exit)
3762 priv->quirk->exit(priv->dev);
3763 }
3764 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3765
3766 void pciserial_resume_ports(struct serial_private *priv)
3767 {
3768 int i;
3769
3770 /*
3771 * Ensure that the board is correctly configured.
3772 */
3773 if (priv->quirk->init)
3774 priv->quirk->init(priv->dev);
3775
3776 for (i = 0; i < priv->nr; i++)
3777 if (priv->line[i] >= 0)
3778 serial8250_resume_port(priv->line[i]);
3779 }
3780 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3781
3782 /*
3783 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3784 * to the arrangement of serial ports on a PCI card.
3785 */
3786 static int
3787 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3788 {
3789 struct pci_serial_quirk *quirk;
3790 struct serial_private *priv;
3791 const struct pciserial_board *board;
3792 struct pciserial_board tmp;
3793 int rc;
3794
3795 quirk = find_quirk(dev);
3796 if (quirk->probe) {
3797 rc = quirk->probe(dev);
3798 if (rc)
3799 return rc;
3800 }
3801
3802 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3803 dev_err(&dev->dev, "invalid driver_data: %ld\n",
3804 ent->driver_data);
3805 return -EINVAL;
3806 }
3807
3808 board = &pci_boards[ent->driver_data];
3809
3810 rc = serial_pci_is_blacklisted(dev);
3811 if (rc)
3812 return rc;
3813
3814 rc = pcim_enable_device(dev);
3815 pci_save_state(dev);
3816 if (rc)
3817 return rc;
3818
3819 if (ent->driver_data == pbn_default) {
3820 /*
3821 * Use a copy of the pci_board entry for this;
3822 * avoid changing entries in the table.
3823 */
3824 memcpy(&tmp, board, sizeof(struct pciserial_board));
3825 board = &tmp;
3826
3827 /*
3828 * We matched one of our class entries. Try to
3829 * determine the parameters of this board.
3830 */
3831 rc = serial_pci_guess_board(dev, &tmp);
3832 if (rc)
3833 return rc;
3834 } else {
3835 /*
3836 * We matched an explicit entry. If we are able to
3837 * detect this boards settings with our heuristic,
3838 * then we no longer need this entry.
3839 */
3840 memcpy(&tmp, &pci_boards[pbn_default],
3841 sizeof(struct pciserial_board));
3842 rc = serial_pci_guess_board(dev, &tmp);
3843 if (rc == 0 && serial_pci_matches(board, &tmp))
3844 moan_device("Redundant entry in serial pci_table.",
3845 dev);
3846 }
3847
3848 priv = pciserial_init_ports(dev, board);
3849 if (IS_ERR(priv))
3850 return PTR_ERR(priv);
3851
3852 pci_set_drvdata(dev, priv);
3853 return 0;
3854 }
3855
3856 static void pciserial_remove_one(struct pci_dev *dev)
3857 {
3858 struct serial_private *priv = pci_get_drvdata(dev);
3859
3860 pciserial_remove_ports(priv);
3861 }
3862
3863 #ifdef CONFIG_PM_SLEEP
3864 static int pciserial_suspend_one(struct device *dev)
3865 {
3866 struct pci_dev *pdev = to_pci_dev(dev);
3867 struct serial_private *priv = pci_get_drvdata(pdev);
3868
3869 if (priv)
3870 pciserial_suspend_ports(priv);
3871
3872 return 0;
3873 }
3874
3875 static int pciserial_resume_one(struct device *dev)
3876 {
3877 struct pci_dev *pdev = to_pci_dev(dev);
3878 struct serial_private *priv = pci_get_drvdata(pdev);
3879 int err;
3880
3881 if (priv) {
3882 /*
3883 * The device may have been disabled. Re-enable it.
3884 */
3885 err = pci_enable_device(pdev);
3886 /* FIXME: We cannot simply error out here */
3887 if (err)
3888 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
3889 pciserial_resume_ports(priv);
3890 }
3891 return 0;
3892 }
3893 #endif
3894
3895 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
3896 pciserial_resume_one);
3897
3898 static const struct pci_device_id serial_pci_tbl[] = {
3899 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3900 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3901 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3902 pbn_b2_8_921600 },
3903 /* Advantech also use 0x3618 and 0xf618 */
3904 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
3905 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3906 pbn_b0_4_921600 },
3907 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
3908 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3909 pbn_b0_4_921600 },
3910 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3911 PCI_SUBVENDOR_ID_CONNECT_TECH,
3912 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3913 pbn_b1_8_1382400 },
3914 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3915 PCI_SUBVENDOR_ID_CONNECT_TECH,
3916 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3917 pbn_b1_4_1382400 },
3918 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3919 PCI_SUBVENDOR_ID_CONNECT_TECH,
3920 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3921 pbn_b1_2_1382400 },
3922 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3923 PCI_SUBVENDOR_ID_CONNECT_TECH,
3924 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3925 pbn_b1_8_1382400 },
3926 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3927 PCI_SUBVENDOR_ID_CONNECT_TECH,
3928 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3929 pbn_b1_4_1382400 },
3930 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3931 PCI_SUBVENDOR_ID_CONNECT_TECH,
3932 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3933 pbn_b1_2_1382400 },
3934 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3935 PCI_SUBVENDOR_ID_CONNECT_TECH,
3936 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3937 pbn_b1_8_921600 },
3938 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3939 PCI_SUBVENDOR_ID_CONNECT_TECH,
3940 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3941 pbn_b1_8_921600 },
3942 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3943 PCI_SUBVENDOR_ID_CONNECT_TECH,
3944 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3945 pbn_b1_4_921600 },
3946 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3947 PCI_SUBVENDOR_ID_CONNECT_TECH,
3948 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3949 pbn_b1_4_921600 },
3950 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3951 PCI_SUBVENDOR_ID_CONNECT_TECH,
3952 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3953 pbn_b1_2_921600 },
3954 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3955 PCI_SUBVENDOR_ID_CONNECT_TECH,
3956 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3957 pbn_b1_8_921600 },
3958 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3959 PCI_SUBVENDOR_ID_CONNECT_TECH,
3960 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3961 pbn_b1_8_921600 },
3962 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3963 PCI_SUBVENDOR_ID_CONNECT_TECH,
3964 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3965 pbn_b1_4_921600 },
3966 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3967 PCI_SUBVENDOR_ID_CONNECT_TECH,
3968 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3969 pbn_b1_2_1250000 },
3970 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3971 PCI_SUBVENDOR_ID_CONNECT_TECH,
3972 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3973 pbn_b0_2_1843200 },
3974 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3975 PCI_SUBVENDOR_ID_CONNECT_TECH,
3976 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3977 pbn_b0_4_1843200 },
3978 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3979 PCI_VENDOR_ID_AFAVLAB,
3980 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3981 pbn_b0_4_1152000 },
3982 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3983 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3984 pbn_b2_bt_1_115200 },
3985 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3986 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3987 pbn_b2_bt_2_115200 },
3988 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3989 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3990 pbn_b2_bt_4_115200 },
3991 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3992 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3993 pbn_b2_bt_2_115200 },
3994 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3995 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3996 pbn_b2_bt_4_115200 },
3997 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3998 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3999 pbn_b2_8_115200 },
4000 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4001 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4002 pbn_b2_8_460800 },
4003 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4004 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4005 pbn_b2_8_115200 },
4006
4007 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4008 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4009 pbn_b2_bt_2_115200 },
4010 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4011 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4012 pbn_b2_bt_2_921600 },
4013 /*
4014 * VScom SPCOM800, from sl@s.pl
4015 */
4016 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4017 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4018 pbn_b2_8_921600 },
4019 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4020 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4021 pbn_b2_4_921600 },
4022 /* Unknown card - subdevice 0x1584 */
4023 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4024 PCI_VENDOR_ID_PLX,
4025 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4026 pbn_b2_4_115200 },
4027 /* Unknown card - subdevice 0x1588 */
4028 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4029 PCI_VENDOR_ID_PLX,
4030 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4031 pbn_b2_8_115200 },
4032 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4033 PCI_SUBVENDOR_ID_KEYSPAN,
4034 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4035 pbn_panacom },
4036 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4037 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4038 pbn_panacom4 },
4039 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4040 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4041 pbn_panacom2 },
4042 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4043 PCI_VENDOR_ID_ESDGMBH,
4044 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4045 pbn_b2_4_115200 },
4046 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4047 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4048 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4049 pbn_b2_4_460800 },
4050 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4051 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4052 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4053 pbn_b2_8_460800 },
4054 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4055 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4056 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4057 pbn_b2_16_460800 },
4058 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4059 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4060 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4061 pbn_b2_16_460800 },
4062 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4063 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4064 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4065 pbn_b2_4_460800 },
4066 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4067 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4068 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4069 pbn_b2_8_460800 },
4070 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4071 PCI_SUBVENDOR_ID_EXSYS,
4072 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4073 pbn_b2_4_115200 },
4074 /*
4075 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4076 * (Exoray@isys.ca)
4077 */
4078 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4079 0x10b5, 0x106a, 0, 0,
4080 pbn_plx_romulus },
4081 /*
4082 * EndRun Technologies. PCI express device range.
4083 * EndRun PTP/1588 has 2 Native UARTs.
4084 */
4085 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4086 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4087 pbn_endrun_2_4000000 },
4088 /*
4089 * Quatech cards. These actually have configurable clocks but for
4090 * now we just use the default.
4091 *
4092 * 100 series are RS232, 200 series RS422,
4093 */
4094 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4095 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4096 pbn_b1_4_115200 },
4097 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4098 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4099 pbn_b1_2_115200 },
4100 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4101 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4102 pbn_b2_2_115200 },
4103 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4104 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4105 pbn_b1_2_115200 },
4106 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4107 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4108 pbn_b2_2_115200 },
4109 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4110 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4111 pbn_b1_4_115200 },
4112 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4113 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4114 pbn_b1_8_115200 },
4115 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4116 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4117 pbn_b1_8_115200 },
4118 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4119 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4120 pbn_b1_4_115200 },
4121 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4122 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4123 pbn_b1_2_115200 },
4124 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4125 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4126 pbn_b1_4_115200 },
4127 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4128 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4129 pbn_b1_2_115200 },
4130 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4131 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4132 pbn_b2_4_115200 },
4133 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4134 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4135 pbn_b2_2_115200 },
4136 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4137 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4138 pbn_b2_1_115200 },
4139 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4140 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4141 pbn_b2_4_115200 },
4142 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4143 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4144 pbn_b2_2_115200 },
4145 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4146 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4147 pbn_b2_1_115200 },
4148 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4149 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4150 pbn_b0_8_115200 },
4151
4152 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4153 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4154 0, 0,
4155 pbn_b0_4_921600 },
4156 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4157 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4158 0, 0,
4159 pbn_b0_4_1152000 },
4160 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4161 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4162 pbn_b0_bt_2_921600 },
4163
4164 /*
4165 * The below card is a little controversial since it is the
4166 * subject of a PCI vendor/device ID clash. (See
4167 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4168 * For now just used the hex ID 0x950a.
4169 */
4170 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4171 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4172 0, 0, pbn_b0_2_115200 },
4173 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4174 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4175 0, 0, pbn_b0_2_115200 },
4176 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4177 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4178 pbn_b0_2_1130000 },
4179 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4180 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4181 pbn_b0_1_921600 },
4182 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4183 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4184 pbn_b0_4_115200 },
4185 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4186 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4187 pbn_b0_bt_2_921600 },
4188 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4189 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4190 pbn_b2_8_1152000 },
4191
4192 /*
4193 * Oxford Semiconductor Inc. Tornado PCI express device range.
4194 */
4195 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4196 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4197 pbn_b0_1_4000000 },
4198 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4199 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4200 pbn_b0_1_4000000 },
4201 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4202 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4203 pbn_oxsemi_1_4000000 },
4204 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4205 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4206 pbn_oxsemi_1_4000000 },
4207 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4208 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4209 pbn_b0_1_4000000 },
4210 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4211 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4212 pbn_b0_1_4000000 },
4213 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4214 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4215 pbn_oxsemi_1_4000000 },
4216 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4218 pbn_oxsemi_1_4000000 },
4219 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4220 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4221 pbn_b0_1_4000000 },
4222 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4223 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4224 pbn_b0_1_4000000 },
4225 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4226 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4227 pbn_b0_1_4000000 },
4228 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4229 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4230 pbn_b0_1_4000000 },
4231 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4232 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4233 pbn_oxsemi_2_4000000 },
4234 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4235 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4236 pbn_oxsemi_2_4000000 },
4237 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4238 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4239 pbn_oxsemi_4_4000000 },
4240 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4241 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4242 pbn_oxsemi_4_4000000 },
4243 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4244 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4245 pbn_oxsemi_8_4000000 },
4246 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4247 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4248 pbn_oxsemi_8_4000000 },
4249 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4250 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4251 pbn_oxsemi_1_4000000 },
4252 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4253 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4254 pbn_oxsemi_1_4000000 },
4255 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4256 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4257 pbn_oxsemi_1_4000000 },
4258 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4259 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4260 pbn_oxsemi_1_4000000 },
4261 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4262 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4263 pbn_oxsemi_1_4000000 },
4264 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4265 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4266 pbn_oxsemi_1_4000000 },
4267 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4268 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4269 pbn_oxsemi_1_4000000 },
4270 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4271 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4272 pbn_oxsemi_1_4000000 },
4273 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4274 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4275 pbn_oxsemi_1_4000000 },
4276 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4278 pbn_oxsemi_1_4000000 },
4279 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4280 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4281 pbn_oxsemi_1_4000000 },
4282 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4283 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4284 pbn_oxsemi_1_4000000 },
4285 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4286 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4287 pbn_oxsemi_1_4000000 },
4288 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4289 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4290 pbn_oxsemi_1_4000000 },
4291 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4292 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4293 pbn_oxsemi_1_4000000 },
4294 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4295 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4296 pbn_oxsemi_1_4000000 },
4297 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4298 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4299 pbn_oxsemi_1_4000000 },
4300 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4301 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4302 pbn_oxsemi_1_4000000 },
4303 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4304 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4305 pbn_oxsemi_1_4000000 },
4306 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4307 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4308 pbn_oxsemi_1_4000000 },
4309 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4310 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4311 pbn_oxsemi_1_4000000 },
4312 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4313 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4314 pbn_oxsemi_1_4000000 },
4315 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4316 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4317 pbn_oxsemi_1_4000000 },
4318 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4319 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4320 pbn_oxsemi_1_4000000 },
4321 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4322 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4323 pbn_oxsemi_1_4000000 },
4324 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4325 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4326 pbn_oxsemi_1_4000000 },
4327 /*
4328 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4329 */
4330 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4331 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4332 pbn_oxsemi_1_4000000 },
4333 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4334 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4335 pbn_oxsemi_2_4000000 },
4336 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4337 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4338 pbn_oxsemi_4_4000000 },
4339 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4340 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4341 pbn_oxsemi_8_4000000 },
4342
4343 /*
4344 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4345 */
4346 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4347 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4348 pbn_oxsemi_2_4000000 },
4349
4350 /*
4351 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4352 * from skokodyn@yahoo.com
4353 */
4354 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4355 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4356 pbn_sbsxrsio },
4357 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4358 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4359 pbn_sbsxrsio },
4360 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4361 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4362 pbn_sbsxrsio },
4363 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4364 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4365 pbn_sbsxrsio },
4366
4367 /*
4368 * Digitan DS560-558, from jimd@esoft.com
4369 */
4370 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4371 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4372 pbn_b1_1_115200 },
4373
4374 /*
4375 * Titan Electronic cards
4376 * The 400L and 800L have a custom setup quirk.
4377 */
4378 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4379 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4380 pbn_b0_1_921600 },
4381 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4382 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4383 pbn_b0_2_921600 },
4384 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4385 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4386 pbn_b0_4_921600 },
4387 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4388 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4389 pbn_b0_4_921600 },
4390 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4391 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4392 pbn_b1_1_921600 },
4393 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4394 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4395 pbn_b1_bt_2_921600 },
4396 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4397 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4398 pbn_b0_bt_4_921600 },
4399 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4400 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4401 pbn_b0_bt_8_921600 },
4402 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4403 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4404 pbn_b4_bt_2_921600 },
4405 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4406 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4407 pbn_b4_bt_4_921600 },
4408 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4409 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4410 pbn_b4_bt_8_921600 },
4411 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4412 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4413 pbn_b0_4_921600 },
4414 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4415 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4416 pbn_b0_4_921600 },
4417 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4418 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4419 pbn_b0_4_921600 },
4420 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4421 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4422 pbn_oxsemi_1_4000000 },
4423 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4424 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4425 pbn_oxsemi_2_4000000 },
4426 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4427 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4428 pbn_oxsemi_4_4000000 },
4429 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4430 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4431 pbn_oxsemi_8_4000000 },
4432 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4433 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4434 pbn_oxsemi_2_4000000 },
4435 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4436 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4437 pbn_oxsemi_2_4000000 },
4438 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4439 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4440 pbn_b0_bt_2_921600 },
4441 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4442 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4443 pbn_b0_4_921600 },
4444 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4445 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4446 pbn_b0_4_921600 },
4447 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4448 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4449 pbn_b0_4_921600 },
4450 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4451 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4452 pbn_b0_4_921600 },
4453
4454 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4455 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4456 pbn_b2_1_460800 },
4457 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4458 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4459 pbn_b2_1_460800 },
4460 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4461 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4462 pbn_b2_1_460800 },
4463 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4464 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4465 pbn_b2_bt_2_921600 },
4466 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4467 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4468 pbn_b2_bt_2_921600 },
4469 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4470 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4471 pbn_b2_bt_2_921600 },
4472 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4473 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4474 pbn_b2_bt_4_921600 },
4475 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4476 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4477 pbn_b2_bt_4_921600 },
4478 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4479 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4480 pbn_b2_bt_4_921600 },
4481 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4482 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4483 pbn_b0_1_921600 },
4484 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4485 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4486 pbn_b0_1_921600 },
4487 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4488 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4489 pbn_b0_1_921600 },
4490 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4491 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4492 pbn_b0_bt_2_921600 },
4493 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4494 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4495 pbn_b0_bt_2_921600 },
4496 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4497 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4498 pbn_b0_bt_2_921600 },
4499 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4500 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4501 pbn_b0_bt_4_921600 },
4502 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4503 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4504 pbn_b0_bt_4_921600 },
4505 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4506 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4507 pbn_b0_bt_4_921600 },
4508 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4510 pbn_b0_bt_8_921600 },
4511 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4512 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4513 pbn_b0_bt_8_921600 },
4514 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4515 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4516 pbn_b0_bt_8_921600 },
4517
4518 /*
4519 * Computone devices submitted by Doug McNash dmcnash@computone.com
4520 */
4521 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4522 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4523 0, 0, pbn_computone_4 },
4524 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4525 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4526 0, 0, pbn_computone_8 },
4527 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4528 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4529 0, 0, pbn_computone_6 },
4530
4531 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4532 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4533 pbn_oxsemi },
4534 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4535 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4536 pbn_b0_bt_1_921600 },
4537
4538 /*
4539 * Sunix PCI serial boards
4540 */
4541 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4542 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
4543 pbn_sunix_pci_1s },
4544 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4545 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
4546 pbn_sunix_pci_2s },
4547 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4548 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
4549 pbn_sunix_pci_4s },
4550 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4551 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
4552 pbn_sunix_pci_4s },
4553 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4554 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
4555 pbn_sunix_pci_8s },
4556 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4557 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
4558 pbn_sunix_pci_8s },
4559 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4560 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
4561 pbn_sunix_pci_16s },
4562
4563 /*
4564 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4565 */
4566 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4567 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4568 pbn_b0_bt_8_115200 },
4569 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4570 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4571 pbn_b0_bt_8_115200 },
4572
4573 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4574 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4575 pbn_b0_bt_2_115200 },
4576 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4577 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4578 pbn_b0_bt_2_115200 },
4579 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4580 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4581 pbn_b0_bt_2_115200 },
4582 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4583 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4584 pbn_b0_bt_2_115200 },
4585 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4586 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4587 pbn_b0_bt_2_115200 },
4588 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4589 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4590 pbn_b0_bt_4_460800 },
4591 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593 pbn_b0_bt_4_460800 },
4594 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596 pbn_b0_bt_2_460800 },
4597 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599 pbn_b0_bt_2_460800 },
4600 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602 pbn_b0_bt_2_460800 },
4603 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 pbn_b0_bt_1_115200 },
4606 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608 pbn_b0_bt_1_460800 },
4609
4610 /*
4611 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4612 * Cards are identified by their subsystem vendor IDs, which
4613 * (in hex) match the model number.
4614 *
4615 * Note that JC140x are RS422/485 cards which require ox950
4616 * ACR = 0x10, and as such are not currently fully supported.
4617 */
4618 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4619 0x1204, 0x0004, 0, 0,
4620 pbn_b0_4_921600 },
4621 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4622 0x1208, 0x0004, 0, 0,
4623 pbn_b0_4_921600 },
4624 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4625 0x1402, 0x0002, 0, 0,
4626 pbn_b0_2_921600 }, */
4627 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4628 0x1404, 0x0004, 0, 0,
4629 pbn_b0_4_921600 }, */
4630 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4631 0x1208, 0x0004, 0, 0,
4632 pbn_b0_4_921600 },
4633
4634 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4635 0x1204, 0x0004, 0, 0,
4636 pbn_b0_4_921600 },
4637 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4638 0x1208, 0x0004, 0, 0,
4639 pbn_b0_4_921600 },
4640 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4641 0x1208, 0x0004, 0, 0,
4642 pbn_b0_4_921600 },
4643 /*
4644 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4645 */
4646 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4647 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4648 pbn_b1_1_1382400 },
4649
4650 /*
4651 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4652 */
4653 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4654 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4655 pbn_b1_1_1382400 },
4656
4657 /*
4658 * RAStel 2 port modem, gerg@moreton.com.au
4659 */
4660 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4661 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4662 pbn_b2_bt_2_115200 },
4663
4664 /*
4665 * EKF addition for i960 Boards form EKF with serial port
4666 */
4667 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4668 0xE4BF, PCI_ANY_ID, 0, 0,
4669 pbn_intel_i960 },
4670
4671 /*
4672 * Xircom Cardbus/Ethernet combos
4673 */
4674 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4675 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4676 pbn_b0_1_115200 },
4677 /*
4678 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4679 */
4680 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4681 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4682 pbn_b0_1_115200 },
4683
4684 /*
4685 * Untested PCI modems, sent in from various folks...
4686 */
4687
4688 /*
4689 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4690 */
4691 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4692 0x1048, 0x1500, 0, 0,
4693 pbn_b1_1_115200 },
4694
4695 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4696 0xFF00, 0, 0, 0,
4697 pbn_sgi_ioc3 },
4698
4699 /*
4700 * HP Diva card
4701 */
4702 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4703 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4704 pbn_b1_1_115200 },
4705 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4707 pbn_b0_5_115200 },
4708 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4709 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4710 pbn_b2_1_115200 },
4711
4712 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4713 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4714 pbn_b3_2_115200 },
4715 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4716 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4717 pbn_b3_4_115200 },
4718 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4719 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4720 pbn_b3_8_115200 },
4721 /*
4722 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
4723 */
4724 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
4725 PCI_ANY_ID, PCI_ANY_ID,
4726 0,
4727 0, pbn_pericom_PI7C9X7951 },
4728 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
4729 PCI_ANY_ID, PCI_ANY_ID,
4730 0,
4731 0, pbn_pericom_PI7C9X7952 },
4732 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
4733 PCI_ANY_ID, PCI_ANY_ID,
4734 0,
4735 0, pbn_pericom_PI7C9X7954 },
4736 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
4737 PCI_ANY_ID, PCI_ANY_ID,
4738 0,
4739 0, pbn_pericom_PI7C9X7958 },
4740 /*
4741 * ACCES I/O Products quad
4742 */
4743 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
4744 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4745 pbn_pericom_PI7C9X7952 },
4746 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
4747 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4748 pbn_pericom_PI7C9X7952 },
4749 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
4750 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4751 pbn_pericom_PI7C9X7954 },
4752 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
4753 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4754 pbn_pericom_PI7C9X7954 },
4755 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
4756 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4757 pbn_pericom_PI7C9X7952 },
4758 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
4759 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4760 pbn_pericom_PI7C9X7952 },
4761 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
4762 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4763 pbn_pericom_PI7C9X7954 },
4764 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
4765 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4766 pbn_pericom_PI7C9X7954 },
4767 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
4768 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4769 pbn_pericom_PI7C9X7952 },
4770 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
4771 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4772 pbn_pericom_PI7C9X7952 },
4773 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
4774 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4775 pbn_pericom_PI7C9X7954 },
4776 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
4777 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4778 pbn_pericom_PI7C9X7954 },
4779 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
4780 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4781 pbn_pericom_PI7C9X7951 },
4782 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
4783 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4784 pbn_pericom_PI7C9X7952 },
4785 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
4786 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4787 pbn_pericom_PI7C9X7952 },
4788 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
4789 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4790 pbn_pericom_PI7C9X7954 },
4791 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
4792 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4793 pbn_pericom_PI7C9X7954 },
4794 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
4795 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4796 pbn_pericom_PI7C9X7952 },
4797 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
4798 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4799 pbn_pericom_PI7C9X7954 },
4800 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
4801 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4802 pbn_pericom_PI7C9X7952 },
4803 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
4804 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4805 pbn_pericom_PI7C9X7952 },
4806 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
4807 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4808 pbn_pericom_PI7C9X7954 },
4809 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
4810 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4811 pbn_pericom_PI7C9X7954 },
4812 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
4813 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4814 pbn_pericom_PI7C9X7952 },
4815 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
4816 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4817 pbn_pericom_PI7C9X7954 },
4818 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
4819 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4820 pbn_pericom_PI7C9X7954 },
4821 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
4822 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4823 pbn_pericom_PI7C9X7958 },
4824 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
4825 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4826 pbn_pericom_PI7C9X7958 },
4827 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
4828 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4829 pbn_pericom_PI7C9X7954 },
4830 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
4831 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4832 pbn_pericom_PI7C9X7958 },
4833 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
4834 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4835 pbn_pericom_PI7C9X7954 },
4836 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
4837 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4838 pbn_pericom_PI7C9X7958 },
4839 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
4840 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4841 pbn_pericom_PI7C9X7954 },
4842 /*
4843 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4844 */
4845 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4846 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4847 pbn_b0_1_115200 },
4848 /*
4849 * ITE
4850 */
4851 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4852 PCI_ANY_ID, PCI_ANY_ID,
4853 0, 0,
4854 pbn_b1_bt_1_115200 },
4855
4856 /*
4857 * IntaShield IS-200
4858 */
4859 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4860 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4861 pbn_b2_2_115200 },
4862 /*
4863 * IntaShield IS-400
4864 */
4865 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4866 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4867 pbn_b2_4_115200 },
4868 /*
4869 * BrainBoxes UC-260
4870 */
4871 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
4872 PCI_ANY_ID, PCI_ANY_ID,
4873 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4874 pbn_b2_4_115200 },
4875 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
4876 PCI_ANY_ID, PCI_ANY_ID,
4877 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4878 pbn_b2_4_115200 },
4879 /*
4880 * Perle PCI-RAS cards
4881 */
4882 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4883 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4884 0, 0, pbn_b2_4_921600 },
4885 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4886 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4887 0, 0, pbn_b2_8_921600 },
4888
4889 /*
4890 * Mainpine series cards: Fairly standard layout but fools
4891 * parts of the autodetect in some cases and uses otherwise
4892 * unmatched communications subclasses in the PCI Express case
4893 */
4894
4895 { /* RockForceDUO */
4896 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4897 PCI_VENDOR_ID_MAINPINE, 0x0200,
4898 0, 0, pbn_b0_2_115200 },
4899 { /* RockForceQUATRO */
4900 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4901 PCI_VENDOR_ID_MAINPINE, 0x0300,
4902 0, 0, pbn_b0_4_115200 },
4903 { /* RockForceDUO+ */
4904 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4905 PCI_VENDOR_ID_MAINPINE, 0x0400,
4906 0, 0, pbn_b0_2_115200 },
4907 { /* RockForceQUATRO+ */
4908 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4909 PCI_VENDOR_ID_MAINPINE, 0x0500,
4910 0, 0, pbn_b0_4_115200 },
4911 { /* RockForce+ */
4912 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4913 PCI_VENDOR_ID_MAINPINE, 0x0600,
4914 0, 0, pbn_b0_2_115200 },
4915 { /* RockForce+ */
4916 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4917 PCI_VENDOR_ID_MAINPINE, 0x0700,
4918 0, 0, pbn_b0_4_115200 },
4919 { /* RockForceOCTO+ */
4920 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4921 PCI_VENDOR_ID_MAINPINE, 0x0800,
4922 0, 0, pbn_b0_8_115200 },
4923 { /* RockForceDUO+ */
4924 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4925 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4926 0, 0, pbn_b0_2_115200 },
4927 { /* RockForceQUARTRO+ */
4928 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4929 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4930 0, 0, pbn_b0_4_115200 },
4931 { /* RockForceOCTO+ */
4932 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4933 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4934 0, 0, pbn_b0_8_115200 },
4935 { /* RockForceD1 */
4936 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4937 PCI_VENDOR_ID_MAINPINE, 0x2000,
4938 0, 0, pbn_b0_1_115200 },
4939 { /* RockForceF1 */
4940 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4941 PCI_VENDOR_ID_MAINPINE, 0x2100,
4942 0, 0, pbn_b0_1_115200 },
4943 { /* RockForceD2 */
4944 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4945 PCI_VENDOR_ID_MAINPINE, 0x2200,
4946 0, 0, pbn_b0_2_115200 },
4947 { /* RockForceF2 */
4948 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4949 PCI_VENDOR_ID_MAINPINE, 0x2300,
4950 0, 0, pbn_b0_2_115200 },
4951 { /* RockForceD4 */
4952 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4953 PCI_VENDOR_ID_MAINPINE, 0x2400,
4954 0, 0, pbn_b0_4_115200 },
4955 { /* RockForceF4 */
4956 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4957 PCI_VENDOR_ID_MAINPINE, 0x2500,
4958 0, 0, pbn_b0_4_115200 },
4959 { /* RockForceD8 */
4960 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4961 PCI_VENDOR_ID_MAINPINE, 0x2600,
4962 0, 0, pbn_b0_8_115200 },
4963 { /* RockForceF8 */
4964 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4965 PCI_VENDOR_ID_MAINPINE, 0x2700,
4966 0, 0, pbn_b0_8_115200 },
4967 { /* IQ Express D1 */
4968 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4969 PCI_VENDOR_ID_MAINPINE, 0x3000,
4970 0, 0, pbn_b0_1_115200 },
4971 { /* IQ Express F1 */
4972 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4973 PCI_VENDOR_ID_MAINPINE, 0x3100,
4974 0, 0, pbn_b0_1_115200 },
4975 { /* IQ Express D2 */
4976 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4977 PCI_VENDOR_ID_MAINPINE, 0x3200,
4978 0, 0, pbn_b0_2_115200 },
4979 { /* IQ Express F2 */
4980 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4981 PCI_VENDOR_ID_MAINPINE, 0x3300,
4982 0, 0, pbn_b0_2_115200 },
4983 { /* IQ Express D4 */
4984 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4985 PCI_VENDOR_ID_MAINPINE, 0x3400,
4986 0, 0, pbn_b0_4_115200 },
4987 { /* IQ Express F4 */
4988 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4989 PCI_VENDOR_ID_MAINPINE, 0x3500,
4990 0, 0, pbn_b0_4_115200 },
4991 { /* IQ Express D8 */
4992 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4993 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4994 0, 0, pbn_b0_8_115200 },
4995 { /* IQ Express F8 */
4996 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4997 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4998 0, 0, pbn_b0_8_115200 },
4999
5000
5001 /*
5002 * PA Semi PA6T-1682M on-chip UART
5003 */
5004 { PCI_VENDOR_ID_PASEMI, 0xa004,
5005 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5006 pbn_pasemi_1682M },
5007
5008 /*
5009 * National Instruments
5010 */
5011 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5012 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5013 pbn_b1_16_115200 },
5014 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5015 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5016 pbn_b1_8_115200 },
5017 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5018 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5019 pbn_b1_bt_4_115200 },
5020 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5021 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5022 pbn_b1_bt_2_115200 },
5023 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5024 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5025 pbn_b1_bt_4_115200 },
5026 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5027 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5028 pbn_b1_bt_2_115200 },
5029 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5030 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5031 pbn_b1_16_115200 },
5032 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5033 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5034 pbn_b1_8_115200 },
5035 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5036 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5037 pbn_b1_bt_4_115200 },
5038 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5039 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5040 pbn_b1_bt_2_115200 },
5041 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5042 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5043 pbn_b1_bt_4_115200 },
5044 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5045 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5046 pbn_b1_bt_2_115200 },
5047 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5048 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5049 pbn_ni8430_2 },
5050 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5051 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5052 pbn_ni8430_2 },
5053 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5054 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5055 pbn_ni8430_4 },
5056 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5057 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5058 pbn_ni8430_4 },
5059 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5060 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5061 pbn_ni8430_8 },
5062 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5063 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5064 pbn_ni8430_8 },
5065 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5066 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5067 pbn_ni8430_16 },
5068 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5070 pbn_ni8430_16 },
5071 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5072 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5073 pbn_ni8430_2 },
5074 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5076 pbn_ni8430_2 },
5077 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5079 pbn_ni8430_4 },
5080 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5082 pbn_ni8430_4 },
5083
5084 /*
5085 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5086 */
5087 { PCI_VENDOR_ID_ADDIDATA,
5088 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5089 PCI_ANY_ID,
5090 PCI_ANY_ID,
5091 0,
5092 0,
5093 pbn_b0_4_115200 },
5094
5095 { PCI_VENDOR_ID_ADDIDATA,
5096 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5097 PCI_ANY_ID,
5098 PCI_ANY_ID,
5099 0,
5100 0,
5101 pbn_b0_2_115200 },
5102
5103 { PCI_VENDOR_ID_ADDIDATA,
5104 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5105 PCI_ANY_ID,
5106 PCI_ANY_ID,
5107 0,
5108 0,
5109 pbn_b0_1_115200 },
5110
5111 { PCI_VENDOR_ID_AMCC,
5112 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5113 PCI_ANY_ID,
5114 PCI_ANY_ID,
5115 0,
5116 0,
5117 pbn_b1_8_115200 },
5118
5119 { PCI_VENDOR_ID_ADDIDATA,
5120 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5121 PCI_ANY_ID,
5122 PCI_ANY_ID,
5123 0,
5124 0,
5125 pbn_b0_4_115200 },
5126
5127 { PCI_VENDOR_ID_ADDIDATA,
5128 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5129 PCI_ANY_ID,
5130 PCI_ANY_ID,
5131 0,
5132 0,
5133 pbn_b0_2_115200 },
5134
5135 { PCI_VENDOR_ID_ADDIDATA,
5136 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5137 PCI_ANY_ID,
5138 PCI_ANY_ID,
5139 0,
5140 0,
5141 pbn_b0_1_115200 },
5142
5143 { PCI_VENDOR_ID_ADDIDATA,
5144 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5145 PCI_ANY_ID,
5146 PCI_ANY_ID,
5147 0,
5148 0,
5149 pbn_b0_4_115200 },
5150
5151 { PCI_VENDOR_ID_ADDIDATA,
5152 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5153 PCI_ANY_ID,
5154 PCI_ANY_ID,
5155 0,
5156 0,
5157 pbn_b0_2_115200 },
5158
5159 { PCI_VENDOR_ID_ADDIDATA,
5160 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5161 PCI_ANY_ID,
5162 PCI_ANY_ID,
5163 0,
5164 0,
5165 pbn_b0_1_115200 },
5166
5167 { PCI_VENDOR_ID_ADDIDATA,
5168 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5169 PCI_ANY_ID,
5170 PCI_ANY_ID,
5171 0,
5172 0,
5173 pbn_b0_8_115200 },
5174
5175 { PCI_VENDOR_ID_ADDIDATA,
5176 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5177 PCI_ANY_ID,
5178 PCI_ANY_ID,
5179 0,
5180 0,
5181 pbn_ADDIDATA_PCIe_4_3906250 },
5182
5183 { PCI_VENDOR_ID_ADDIDATA,
5184 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5185 PCI_ANY_ID,
5186 PCI_ANY_ID,
5187 0,
5188 0,
5189 pbn_ADDIDATA_PCIe_2_3906250 },
5190
5191 { PCI_VENDOR_ID_ADDIDATA,
5192 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5193 PCI_ANY_ID,
5194 PCI_ANY_ID,
5195 0,
5196 0,
5197 pbn_ADDIDATA_PCIe_1_3906250 },
5198
5199 { PCI_VENDOR_ID_ADDIDATA,
5200 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5201 PCI_ANY_ID,
5202 PCI_ANY_ID,
5203 0,
5204 0,
5205 pbn_ADDIDATA_PCIe_8_3906250 },
5206
5207 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5208 PCI_VENDOR_ID_IBM, 0x0299,
5209 0, 0, pbn_b0_bt_2_115200 },
5210
5211 /*
5212 * other NetMos 9835 devices are most likely handled by the
5213 * parport_serial driver, check drivers/parport/parport_serial.c
5214 * before adding them here.
5215 */
5216
5217 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5218 0xA000, 0x1000,
5219 0, 0, pbn_b0_1_115200 },
5220
5221 /* the 9901 is a rebranded 9912 */
5222 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5223 0xA000, 0x1000,
5224 0, 0, pbn_b0_1_115200 },
5225
5226 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5227 0xA000, 0x1000,
5228 0, 0, pbn_b0_1_115200 },
5229
5230 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5231 0xA000, 0x1000,
5232 0, 0, pbn_b0_1_115200 },
5233
5234 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5235 0xA000, 0x1000,
5236 0, 0, pbn_b0_1_115200 },
5237
5238 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5239 0xA000, 0x3002,
5240 0, 0, pbn_NETMOS9900_2s_115200 },
5241
5242 /*
5243 * Best Connectivity and Rosewill PCI Multi I/O cards
5244 */
5245
5246 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5247 0xA000, 0x1000,
5248 0, 0, pbn_b0_1_115200 },
5249
5250 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5251 0xA000, 0x3002,
5252 0, 0, pbn_b0_bt_2_115200 },
5253
5254 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5255 0xA000, 0x3004,
5256 0, 0, pbn_b0_bt_4_115200 },
5257 /* Intel CE4100 */
5258 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5259 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5260 pbn_ce4100_1_115200 },
5261
5262 /*
5263 * Cronyx Omega PCI
5264 */
5265 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5266 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5267 pbn_omegapci },
5268
5269 /*
5270 * Broadcom TruManage
5271 */
5272 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5273 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5274 pbn_brcm_trumanage },
5275
5276 /*
5277 * AgeStar as-prs2-009
5278 */
5279 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5280 PCI_ANY_ID, PCI_ANY_ID,
5281 0, 0, pbn_b0_bt_2_115200 },
5282
5283 /*
5284 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5285 * so not listed here.
5286 */
5287 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5288 PCI_ANY_ID, PCI_ANY_ID,
5289 0, 0, pbn_b0_bt_4_115200 },
5290
5291 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5292 PCI_ANY_ID, PCI_ANY_ID,
5293 0, 0, pbn_b0_bt_2_115200 },
5294
5295 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5296 PCI_ANY_ID, PCI_ANY_ID,
5297 0, 0, pbn_b0_bt_4_115200 },
5298
5299 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5300 PCI_ANY_ID, PCI_ANY_ID,
5301 0, 0, pbn_wch382_2 },
5302
5303 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5304 PCI_ANY_ID, PCI_ANY_ID,
5305 0, 0, pbn_wch384_4 },
5306
5307 /* Fintek PCI serial cards */
5308 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5309 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5310 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5311
5312 /* MKS Tenta SCOM-080x serial cards */
5313 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5314 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5315
5316 /* Amazon PCI serial device */
5317 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
5318
5319 /*
5320 * These entries match devices with class COMMUNICATION_SERIAL,
5321 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5322 */
5323 { PCI_ANY_ID, PCI_ANY_ID,
5324 PCI_ANY_ID, PCI_ANY_ID,
5325 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5326 0xffff00, pbn_default },
5327 { PCI_ANY_ID, PCI_ANY_ID,
5328 PCI_ANY_ID, PCI_ANY_ID,
5329 PCI_CLASS_COMMUNICATION_MODEM << 8,
5330 0xffff00, pbn_default },
5331 { PCI_ANY_ID, PCI_ANY_ID,
5332 PCI_ANY_ID, PCI_ANY_ID,
5333 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5334 0xffff00, pbn_default },
5335 { 0, }
5336 };
5337
5338 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5339 pci_channel_state_t state)
5340 {
5341 struct serial_private *priv = pci_get_drvdata(dev);
5342
5343 if (state == pci_channel_io_perm_failure)
5344 return PCI_ERS_RESULT_DISCONNECT;
5345
5346 if (priv)
5347 pciserial_detach_ports(priv);
5348
5349 pci_disable_device(dev);
5350
5351 return PCI_ERS_RESULT_NEED_RESET;
5352 }
5353
5354 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5355 {
5356 int rc;
5357
5358 rc = pci_enable_device(dev);
5359
5360 if (rc)
5361 return PCI_ERS_RESULT_DISCONNECT;
5362
5363 pci_restore_state(dev);
5364 pci_save_state(dev);
5365
5366 return PCI_ERS_RESULT_RECOVERED;
5367 }
5368
5369 static void serial8250_io_resume(struct pci_dev *dev)
5370 {
5371 struct serial_private *priv = pci_get_drvdata(dev);
5372 struct serial_private *new;
5373
5374 if (!priv)
5375 return;
5376
5377 new = pciserial_init_ports(dev, priv->board);
5378 if (!IS_ERR(new)) {
5379 pci_set_drvdata(dev, new);
5380 kfree(priv);
5381 }
5382 }
5383
5384 static const struct pci_error_handlers serial8250_err_handler = {
5385 .error_detected = serial8250_io_error_detected,
5386 .slot_reset = serial8250_io_slot_reset,
5387 .resume = serial8250_io_resume,
5388 };
5389
5390 static struct pci_driver serial_pci_driver = {
5391 .name = "serial",
5392 .probe = pciserial_init_one,
5393 .remove = pciserial_remove_one,
5394 .driver = {
5395 .pm = &pciserial_pm_ops,
5396 },
5397 .id_table = serial_pci_tbl,
5398 .err_handler = &serial8250_err_handler,
5399 };
5400
5401 module_pci_driver(serial_pci_driver);
5402
5403 MODULE_LICENSE("GPL");
5404 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5405 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
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