2 * Base port operations for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * A note about mapbase / membase
14 * mapbase is the physical address of the IO port.
15 * membase is an 'ioremapped' cookie.
18 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/ioport.h>
25 #include <linux/init.h>
26 #include <linux/console.h>
27 #include <linux/sysrq.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/ratelimit.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/serial_8250.h>
35 #include <linux/nmi.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/timer.h>
48 * These are definitions for the Exar XR17V35X and XR17(C|D)15X
50 #define UART_EXAR_INT0 0x80
51 #define UART_EXAR_SLEEP 0x8b /* Sleep mode */
52 #define UART_EXAR_DVID 0x8d /* Device identification */
58 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
60 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
63 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
66 * Here we define the default xmit fifo size used for each type of UART.
68 static const struct serial8250_config uart_config
[] = {
93 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
|
94 UART_FCR_CLEAR_RCVR
| UART_FCR_CLEAR_XMIT
,
95 .rxtrig_bytes
= {1, 4, 8, 14},
96 .flags
= UART_CAP_FIFO
,
107 .flags
= UART_CAP_FIFO
| UART_CAP_EFR
| UART_CAP_SLEEP
,
113 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_01
|
115 .rxtrig_bytes
= {8, 16, 24, 28},
116 .flags
= UART_CAP_FIFO
| UART_CAP_EFR
| UART_CAP_SLEEP
,
122 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
|
124 .rxtrig_bytes
= {1, 16, 32, 56},
125 .flags
= UART_CAP_FIFO
| UART_CAP_SLEEP
| UART_CAP_AFE
,
133 .name
= "16C950/954",
136 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
,
137 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
138 .flags
= UART_CAP_FIFO
| UART_CAP_SLEEP
,
144 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_01
|
146 .rxtrig_bytes
= {8, 16, 56, 60},
147 .flags
= UART_CAP_FIFO
| UART_CAP_EFR
| UART_CAP_SLEEP
,
153 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
,
154 .flags
= UART_CAP_FIFO
| UART_CAP_EFR
| UART_CAP_SLEEP
,
160 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_11
,
161 .flags
= UART_CAP_FIFO
,
167 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
,
168 .flags
= UART_CAP_FIFO
| UART_NATSEMI
,
174 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
,
175 .flags
= UART_CAP_FIFO
| UART_CAP_UUE
| UART_CAP_RTOIE
,
181 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
,
182 .flags
= UART_CAP_FIFO
,
188 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_00
,
189 .flags
= UART_CAP_FIFO
/* | UART_CAP_AFE */,
195 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
,
196 .flags
= UART_CAP_FIFO
| UART_CAP_AFE
,
202 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_01
|
204 .rxtrig_bytes
= {1, 4, 8, 14},
205 .flags
= UART_CAP_FIFO
| UART_CAP_RTOIE
,
211 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
,
212 .flags
= UART_CAP_FIFO
| UART_CAP_AFE
| UART_CAP_EFR
|
219 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_11
|
221 .flags
= UART_CAP_FIFO
| UART_CAP_AFE
| UART_CAP_EFR
|
228 .fcr
= UART_FCR_DMA_SELECT
| UART_FCR_ENABLE_FIFO
|
229 UART_FCR_R_TRIG_00
| UART_FCR_T_TRIG_00
,
230 .flags
= UART_CAP_FIFO
,
232 [PORT_BRCM_TRUMANAGE
] = {
236 .flags
= UART_CAP_HFIFO
,
241 [PORT_ALTR_16550_F32
] = {
242 .name
= "Altera 16550 FIFO32",
245 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
,
246 .flags
= UART_CAP_FIFO
| UART_CAP_AFE
,
248 [PORT_ALTR_16550_F64
] = {
249 .name
= "Altera 16550 FIFO64",
252 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
,
253 .flags
= UART_CAP_FIFO
| UART_CAP_AFE
,
255 [PORT_ALTR_16550_F128
] = {
256 .name
= "Altera 16550 FIFO128",
259 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
,
260 .flags
= UART_CAP_FIFO
| UART_CAP_AFE
,
263 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
264 * workaround of errata A-008006 which states that tx_loadsz should
265 * be configured less than Maximum supported fifo bytes.
267 [PORT_16550A_FSL64
] = {
268 .name
= "16550A_FSL64",
271 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
|
273 .flags
= UART_CAP_FIFO
,
276 .name
= "Palmchip BK-3103",
279 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
,
280 .rxtrig_bytes
= {1, 4, 8, 14},
281 .flags
= UART_CAP_FIFO
,
284 .name
= "TI DA8xx/66AK2x",
287 .fcr
= UART_FCR_DMA_SELECT
| UART_FCR_ENABLE_FIFO
|
289 .rxtrig_bytes
= {1, 4, 8, 14},
290 .flags
= UART_CAP_FIFO
| UART_CAP_AFE
,
294 /* Uart divisor latch read */
295 static int default_serial_dl_read(struct uart_8250_port
*up
)
297 return serial_in(up
, UART_DLL
) | serial_in(up
, UART_DLM
) << 8;
300 /* Uart divisor latch write */
301 static void default_serial_dl_write(struct uart_8250_port
*up
, int value
)
303 serial_out(up
, UART_DLL
, value
& 0xff);
304 serial_out(up
, UART_DLM
, value
>> 8 & 0xff);
307 #ifdef CONFIG_SERIAL_8250_RT288X
309 /* Au1x00/RT288x UART hardware has a weird register layout */
310 static const s8 au_io_in_map
[8] = {
318 -1, /* UART_SCR (unmapped) */
321 static const s8 au_io_out_map
[8] = {
327 -1, /* UART_LSR (unmapped) */
328 -1, /* UART_MSR (unmapped) */
329 -1, /* UART_SCR (unmapped) */
332 unsigned int au_serial_in(struct uart_port
*p
, int offset
)
334 if (offset
>= ARRAY_SIZE(au_io_in_map
))
336 offset
= au_io_in_map
[offset
];
339 return __raw_readl(p
->membase
+ (offset
<< p
->regshift
));
342 void au_serial_out(struct uart_port
*p
, int offset
, int value
)
344 if (offset
>= ARRAY_SIZE(au_io_out_map
))
346 offset
= au_io_out_map
[offset
];
349 __raw_writel(value
, p
->membase
+ (offset
<< p
->regshift
));
352 /* Au1x00 haven't got a standard divisor latch */
353 static int au_serial_dl_read(struct uart_8250_port
*up
)
355 return __raw_readl(up
->port
.membase
+ 0x28);
358 static void au_serial_dl_write(struct uart_8250_port
*up
, int value
)
360 __raw_writel(value
, up
->port
.membase
+ 0x28);
365 static unsigned int hub6_serial_in(struct uart_port
*p
, int offset
)
367 offset
= offset
<< p
->regshift
;
368 outb(p
->hub6
- 1 + offset
, p
->iobase
);
369 return inb(p
->iobase
+ 1);
372 static void hub6_serial_out(struct uart_port
*p
, int offset
, int value
)
374 offset
= offset
<< p
->regshift
;
375 outb(p
->hub6
- 1 + offset
, p
->iobase
);
376 outb(value
, p
->iobase
+ 1);
379 static unsigned int mem_serial_in(struct uart_port
*p
, int offset
)
381 offset
= offset
<< p
->regshift
;
382 return readb(p
->membase
+ offset
);
385 static void mem_serial_out(struct uart_port
*p
, int offset
, int value
)
387 offset
= offset
<< p
->regshift
;
388 writeb(value
, p
->membase
+ offset
);
391 static void mem16_serial_out(struct uart_port
*p
, int offset
, int value
)
393 offset
= offset
<< p
->regshift
;
394 writew(value
, p
->membase
+ offset
);
397 static unsigned int mem16_serial_in(struct uart_port
*p
, int offset
)
399 offset
= offset
<< p
->regshift
;
400 return readw(p
->membase
+ offset
);
403 static void mem32_serial_out(struct uart_port
*p
, int offset
, int value
)
405 offset
= offset
<< p
->regshift
;
406 writel(value
, p
->membase
+ offset
);
409 static unsigned int mem32_serial_in(struct uart_port
*p
, int offset
)
411 offset
= offset
<< p
->regshift
;
412 return readl(p
->membase
+ offset
);
415 static void mem32be_serial_out(struct uart_port
*p
, int offset
, int value
)
417 offset
= offset
<< p
->regshift
;
418 iowrite32be(value
, p
->membase
+ offset
);
421 static unsigned int mem32be_serial_in(struct uart_port
*p
, int offset
)
423 offset
= offset
<< p
->regshift
;
424 return ioread32be(p
->membase
+ offset
);
427 static unsigned int io_serial_in(struct uart_port
*p
, int offset
)
429 offset
= offset
<< p
->regshift
;
430 return inb(p
->iobase
+ offset
);
433 static void io_serial_out(struct uart_port
*p
, int offset
, int value
)
435 offset
= offset
<< p
->regshift
;
436 outb(value
, p
->iobase
+ offset
);
439 static int serial8250_default_handle_irq(struct uart_port
*port
);
440 static int exar_handle_irq(struct uart_port
*port
);
442 static void set_io_from_upio(struct uart_port
*p
)
444 struct uart_8250_port
*up
= up_to_u8250p(p
);
446 up
->dl_read
= default_serial_dl_read
;
447 up
->dl_write
= default_serial_dl_write
;
451 p
->serial_in
= hub6_serial_in
;
452 p
->serial_out
= hub6_serial_out
;
456 p
->serial_in
= mem_serial_in
;
457 p
->serial_out
= mem_serial_out
;
461 p
->serial_in
= mem16_serial_in
;
462 p
->serial_out
= mem16_serial_out
;
466 p
->serial_in
= mem32_serial_in
;
467 p
->serial_out
= mem32_serial_out
;
471 p
->serial_in
= mem32be_serial_in
;
472 p
->serial_out
= mem32be_serial_out
;
475 #ifdef CONFIG_SERIAL_8250_RT288X
477 p
->serial_in
= au_serial_in
;
478 p
->serial_out
= au_serial_out
;
479 up
->dl_read
= au_serial_dl_read
;
480 up
->dl_write
= au_serial_dl_write
;
485 p
->serial_in
= io_serial_in
;
486 p
->serial_out
= io_serial_out
;
489 /* Remember loaded iotype */
490 up
->cur_iotype
= p
->iotype
;
491 p
->handle_irq
= serial8250_default_handle_irq
;
495 serial_port_out_sync(struct uart_port
*p
, int offset
, int value
)
503 p
->serial_out(p
, offset
, value
);
504 p
->serial_in(p
, UART_LCR
); /* safe, no side-effects */
507 p
->serial_out(p
, offset
, value
);
514 static void serial_icr_write(struct uart_8250_port
*up
, int offset
, int value
)
516 serial_out(up
, UART_SCR
, offset
);
517 serial_out(up
, UART_ICR
, value
);
520 static unsigned int serial_icr_read(struct uart_8250_port
*up
, int offset
)
524 serial_icr_write(up
, UART_ACR
, up
->acr
| UART_ACR_ICRRD
);
525 serial_out(up
, UART_SCR
, offset
);
526 value
= serial_in(up
, UART_ICR
);
527 serial_icr_write(up
, UART_ACR
, up
->acr
);
535 static void serial8250_clear_fifos(struct uart_8250_port
*p
)
537 if (p
->capabilities
& UART_CAP_FIFO
) {
538 serial_out(p
, UART_FCR
, UART_FCR_ENABLE_FIFO
);
539 serial_out(p
, UART_FCR
, UART_FCR_ENABLE_FIFO
|
540 UART_FCR_CLEAR_RCVR
| UART_FCR_CLEAR_XMIT
);
541 serial_out(p
, UART_FCR
, 0);
545 static inline void serial8250_em485_rts_after_send(struct uart_8250_port
*p
)
547 unsigned char mcr
= serial8250_in_MCR(p
);
549 if (p
->port
.rs485
.flags
& SER_RS485_RTS_AFTER_SEND
)
552 mcr
&= ~UART_MCR_RTS
;
553 serial8250_out_MCR(p
, mcr
);
556 static void serial8250_em485_handle_start_tx(unsigned long arg
);
557 static void serial8250_em485_handle_stop_tx(unsigned long arg
);
559 void serial8250_clear_and_reinit_fifos(struct uart_8250_port
*p
)
561 serial8250_clear_fifos(p
);
562 serial_out(p
, UART_FCR
, p
->fcr
);
564 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos
);
566 void serial8250_rpm_get(struct uart_8250_port
*p
)
568 if (!(p
->capabilities
& UART_CAP_RPM
))
570 pm_runtime_get_sync(p
->port
.dev
);
572 EXPORT_SYMBOL_GPL(serial8250_rpm_get
);
574 void serial8250_rpm_put(struct uart_8250_port
*p
)
576 if (!(p
->capabilities
& UART_CAP_RPM
))
578 pm_runtime_mark_last_busy(p
->port
.dev
);
579 pm_runtime_put_autosuspend(p
->port
.dev
);
581 EXPORT_SYMBOL_GPL(serial8250_rpm_put
);
584 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
585 * @p: uart_8250_port port instance
587 * The function is used to start rs485 software emulating on the
588 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
589 * transmission. The function is idempotent, so it is safe to call it
592 * The caller MUST enable interrupt on empty shift register before
593 * calling serial8250_em485_init(). This interrupt is not a part of
594 * 8250 standard, but implementation defined.
596 * The function is supposed to be called from .rs485_config callback
597 * or from any other callback protected with p->port.lock spinlock.
599 * See also serial8250_em485_destroy()
601 * Return 0 - success, -errno - otherwise
603 int serial8250_em485_init(struct uart_8250_port
*p
)
608 p
->em485
= kmalloc(sizeof(struct uart_8250_em485
), GFP_ATOMIC
);
612 setup_timer(&p
->em485
->stop_tx_timer
,
613 serial8250_em485_handle_stop_tx
, (unsigned long)p
);
614 setup_timer(&p
->em485
->start_tx_timer
,
615 serial8250_em485_handle_start_tx
, (unsigned long)p
);
616 p
->em485
->active_timer
= NULL
;
618 serial8250_em485_rts_after_send(p
);
622 EXPORT_SYMBOL_GPL(serial8250_em485_init
);
625 * serial8250_em485_destroy() - put uart_8250_port into normal state
626 * @p: uart_8250_port port instance
628 * The function is used to stop rs485 software emulating on the
629 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
630 * call it multiple times.
632 * The function is supposed to be called from .rs485_config callback
633 * or from any other callback protected with p->port.lock spinlock.
635 * See also serial8250_em485_init()
637 void serial8250_em485_destroy(struct uart_8250_port
*p
)
642 del_timer(&p
->em485
->start_tx_timer
);
643 del_timer(&p
->em485
->stop_tx_timer
);
648 EXPORT_SYMBOL_GPL(serial8250_em485_destroy
);
651 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
652 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
653 * empty and the HW can idle again.
655 void serial8250_rpm_get_tx(struct uart_8250_port
*p
)
657 unsigned char rpm_active
;
659 if (!(p
->capabilities
& UART_CAP_RPM
))
662 rpm_active
= xchg(&p
->rpm_tx_active
, 1);
665 pm_runtime_get_sync(p
->port
.dev
);
667 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx
);
669 void serial8250_rpm_put_tx(struct uart_8250_port
*p
)
671 unsigned char rpm_active
;
673 if (!(p
->capabilities
& UART_CAP_RPM
))
676 rpm_active
= xchg(&p
->rpm_tx_active
, 0);
679 pm_runtime_mark_last_busy(p
->port
.dev
);
680 pm_runtime_put_autosuspend(p
->port
.dev
);
682 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx
);
685 * IER sleep support. UARTs which have EFRs need the "extended
686 * capability" bit enabled. Note that on XR16C850s, we need to
687 * reset LCR to write to IER.
689 static void serial8250_set_sleep(struct uart_8250_port
*p
, int sleep
)
691 unsigned char lcr
= 0, efr
= 0;
693 * Exar UARTs have a SLEEP register that enables or disables
694 * each UART to enter sleep mode separately. On the XR17V35x the
695 * register is accessible to each UART at the UART_EXAR_SLEEP
696 * offset but the UART channel may only write to the corresponding
699 serial8250_rpm_get(p
);
700 if ((p
->port
.type
== PORT_XR17V35X
) ||
701 (p
->port
.type
== PORT_XR17D15X
)) {
702 serial_out(p
, UART_EXAR_SLEEP
, sleep
? 0xff : 0);
706 if (p
->capabilities
& UART_CAP_SLEEP
) {
707 if (p
->capabilities
& UART_CAP_EFR
) {
708 lcr
= serial_in(p
, UART_LCR
);
709 efr
= serial_in(p
, UART_EFR
);
710 serial_out(p
, UART_LCR
, UART_LCR_CONF_MODE_B
);
711 serial_out(p
, UART_EFR
, UART_EFR_ECB
);
712 serial_out(p
, UART_LCR
, 0);
714 serial_out(p
, UART_IER
, sleep
? UART_IERX_SLEEP
: 0);
715 if (p
->capabilities
& UART_CAP_EFR
) {
716 serial_out(p
, UART_LCR
, UART_LCR_CONF_MODE_B
);
717 serial_out(p
, UART_EFR
, efr
);
718 serial_out(p
, UART_LCR
, lcr
);
722 serial8250_rpm_put(p
);
725 #ifdef CONFIG_SERIAL_8250_RSA
727 * Attempts to turn on the RSA FIFO. Returns zero on failure.
728 * We set the port uart clock rate if we succeed.
730 static int __enable_rsa(struct uart_8250_port
*up
)
735 mode
= serial_in(up
, UART_RSA_MSR
);
736 result
= mode
& UART_RSA_MSR_FIFO
;
739 serial_out(up
, UART_RSA_MSR
, mode
| UART_RSA_MSR_FIFO
);
740 mode
= serial_in(up
, UART_RSA_MSR
);
741 result
= mode
& UART_RSA_MSR_FIFO
;
745 up
->port
.uartclk
= SERIAL_RSA_BAUD_BASE
* 16;
750 static void enable_rsa(struct uart_8250_port
*up
)
752 if (up
->port
.type
== PORT_RSA
) {
753 if (up
->port
.uartclk
!= SERIAL_RSA_BAUD_BASE
* 16) {
754 spin_lock_irq(&up
->port
.lock
);
756 spin_unlock_irq(&up
->port
.lock
);
758 if (up
->port
.uartclk
== SERIAL_RSA_BAUD_BASE
* 16)
759 serial_out(up
, UART_RSA_FRR
, 0);
764 * Attempts to turn off the RSA FIFO. Returns zero on failure.
765 * It is unknown why interrupts were disabled in here. However,
766 * the caller is expected to preserve this behaviour by grabbing
767 * the spinlock before calling this function.
769 static void disable_rsa(struct uart_8250_port
*up
)
774 if (up
->port
.type
== PORT_RSA
&&
775 up
->port
.uartclk
== SERIAL_RSA_BAUD_BASE
* 16) {
776 spin_lock_irq(&up
->port
.lock
);
778 mode
= serial_in(up
, UART_RSA_MSR
);
779 result
= !(mode
& UART_RSA_MSR_FIFO
);
782 serial_out(up
, UART_RSA_MSR
, mode
& ~UART_RSA_MSR_FIFO
);
783 mode
= serial_in(up
, UART_RSA_MSR
);
784 result
= !(mode
& UART_RSA_MSR_FIFO
);
788 up
->port
.uartclk
= SERIAL_RSA_BAUD_BASE_LO
* 16;
789 spin_unlock_irq(&up
->port
.lock
);
792 #endif /* CONFIG_SERIAL_8250_RSA */
795 * This is a quickie test to see how big the FIFO is.
796 * It doesn't work at all the time, more's the pity.
798 static int size_fifo(struct uart_8250_port
*up
)
800 unsigned char old_fcr
, old_mcr
, old_lcr
;
801 unsigned short old_dl
;
804 old_lcr
= serial_in(up
, UART_LCR
);
805 serial_out(up
, UART_LCR
, 0);
806 old_fcr
= serial_in(up
, UART_FCR
);
807 old_mcr
= serial8250_in_MCR(up
);
808 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
|
809 UART_FCR_CLEAR_RCVR
| UART_FCR_CLEAR_XMIT
);
810 serial8250_out_MCR(up
, UART_MCR_LOOP
);
811 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
812 old_dl
= serial_dl_read(up
);
813 serial_dl_write(up
, 0x0001);
814 serial_out(up
, UART_LCR
, 0x03);
815 for (count
= 0; count
< 256; count
++)
816 serial_out(up
, UART_TX
, count
);
817 mdelay(20);/* FIXME - schedule_timeout */
818 for (count
= 0; (serial_in(up
, UART_LSR
) & UART_LSR_DR
) &&
819 (count
< 256); count
++)
820 serial_in(up
, UART_RX
);
821 serial_out(up
, UART_FCR
, old_fcr
);
822 serial8250_out_MCR(up
, old_mcr
);
823 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
824 serial_dl_write(up
, old_dl
);
825 serial_out(up
, UART_LCR
, old_lcr
);
831 * Read UART ID using the divisor method - set DLL and DLM to zero
832 * and the revision will be in DLL and device type in DLM. We
833 * preserve the device state across this.
835 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port
*p
)
837 unsigned char old_lcr
;
838 unsigned int id
, old_dl
;
840 old_lcr
= serial_in(p
, UART_LCR
);
841 serial_out(p
, UART_LCR
, UART_LCR_CONF_MODE_A
);
842 old_dl
= serial_dl_read(p
);
843 serial_dl_write(p
, 0);
844 id
= serial_dl_read(p
);
845 serial_dl_write(p
, old_dl
);
847 serial_out(p
, UART_LCR
, old_lcr
);
853 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
854 * When this function is called we know it is at least a StarTech
855 * 16650 V2, but it might be one of several StarTech UARTs, or one of
856 * its clones. (We treat the broken original StarTech 16650 V1 as a
857 * 16550, and why not? Startech doesn't seem to even acknowledge its
860 * What evil have men's minds wrought...
862 static void autoconfig_has_efr(struct uart_8250_port
*up
)
864 unsigned int id1
, id2
, id3
, rev
;
867 * Everything with an EFR has SLEEP
869 up
->capabilities
|= UART_CAP_EFR
| UART_CAP_SLEEP
;
872 * First we check to see if it's an Oxford Semiconductor UART.
874 * If we have to do this here because some non-National
875 * Semiconductor clone chips lock up if you try writing to the
876 * LSR register (which serial_icr_read does)
880 * Check for Oxford Semiconductor 16C950.
882 * EFR [4] must be set else this test fails.
884 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
885 * claims that it's needed for 952 dual UART's (which are not
886 * recommended for new designs).
889 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
890 serial_out(up
, UART_EFR
, UART_EFR_ECB
);
891 serial_out(up
, UART_LCR
, 0x00);
892 id1
= serial_icr_read(up
, UART_ID1
);
893 id2
= serial_icr_read(up
, UART_ID2
);
894 id3
= serial_icr_read(up
, UART_ID3
);
895 rev
= serial_icr_read(up
, UART_REV
);
897 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1
, id2
, id3
, rev
);
899 if (id1
== 0x16 && id2
== 0xC9 &&
900 (id3
== 0x50 || id3
== 0x52 || id3
== 0x54)) {
901 up
->port
.type
= PORT_16C950
;
904 * Enable work around for the Oxford Semiconductor 952 rev B
905 * chip which causes it to seriously miscalculate baud rates
908 if (id3
== 0x52 && rev
== 0x01)
909 up
->bugs
|= UART_BUG_QUOT
;
914 * We check for a XR16C850 by setting DLL and DLM to 0, and then
915 * reading back DLL and DLM. The chip type depends on the DLM
917 * 0x10 - XR16C850 and the DLL contains the chip revision.
921 id1
= autoconfig_read_divisor_id(up
);
922 DEBUG_AUTOCONF("850id=%04x ", id1
);
925 if (id2
== 0x10 || id2
== 0x12 || id2
== 0x14) {
926 up
->port
.type
= PORT_16850
;
931 * It wasn't an XR16C850.
933 * We distinguish between the '654 and the '650 by counting
934 * how many bytes are in the FIFO. I'm using this for now,
935 * since that's the technique that was sent to me in the
936 * serial driver update, but I'm not convinced this works.
937 * I've had problems doing this in the past. -TYT
939 if (size_fifo(up
) == 64)
940 up
->port
.type
= PORT_16654
;
942 up
->port
.type
= PORT_16650V2
;
946 * We detected a chip without a FIFO. Only two fall into
947 * this category - the original 8250 and the 16450. The
948 * 16450 has a scratch register (accessible with LCR=0)
950 static void autoconfig_8250(struct uart_8250_port
*up
)
952 unsigned char scratch
, status1
, status2
;
954 up
->port
.type
= PORT_8250
;
956 scratch
= serial_in(up
, UART_SCR
);
957 serial_out(up
, UART_SCR
, 0xa5);
958 status1
= serial_in(up
, UART_SCR
);
959 serial_out(up
, UART_SCR
, 0x5a);
960 status2
= serial_in(up
, UART_SCR
);
961 serial_out(up
, UART_SCR
, scratch
);
963 if (status1
== 0xa5 && status2
== 0x5a)
964 up
->port
.type
= PORT_16450
;
967 static int broken_efr(struct uart_8250_port
*up
)
970 * Exar ST16C2550 "A2" devices incorrectly detect as
971 * having an EFR, and report an ID of 0x0201. See
972 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
974 if (autoconfig_read_divisor_id(up
) == 0x0201 && size_fifo(up
) == 16)
981 * We know that the chip has FIFOs. Does it have an EFR? The
982 * EFR is located in the same register position as the IIR and
983 * we know the top two bits of the IIR are currently set. The
984 * EFR should contain zero. Try to read the EFR.
986 static void autoconfig_16550a(struct uart_8250_port
*up
)
988 unsigned char status1
, status2
;
989 unsigned int iersave
;
991 up
->port
.type
= PORT_16550A
;
992 up
->capabilities
|= UART_CAP_FIFO
;
995 * XR17V35x UARTs have an extra divisor register, DLD
996 * that gets enabled with when DLAB is set which will
997 * cause the device to incorrectly match and assign
998 * port type to PORT_16650. The EFR for this UART is
999 * found at offset 0x09. Instead check the Deice ID (DVID)
1000 * register for a 2, 4 or 8 port UART.
1002 if (up
->port
.flags
& UPF_EXAR_EFR
) {
1003 status1
= serial_in(up
, UART_EXAR_DVID
);
1004 if (status1
== 0x82 || status1
== 0x84 || status1
== 0x88) {
1005 DEBUG_AUTOCONF("Exar XR17V35x ");
1006 up
->port
.type
= PORT_XR17V35X
;
1007 up
->capabilities
|= UART_CAP_AFE
| UART_CAP_EFR
|
1016 * Check for presence of the EFR when DLAB is set.
1017 * Only ST16C650V1 UARTs pass this test.
1019 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
1020 if (serial_in(up
, UART_EFR
) == 0) {
1021 serial_out(up
, UART_EFR
, 0xA8);
1022 if (serial_in(up
, UART_EFR
) != 0) {
1023 DEBUG_AUTOCONF("EFRv1 ");
1024 up
->port
.type
= PORT_16650
;
1025 up
->capabilities
|= UART_CAP_EFR
| UART_CAP_SLEEP
;
1027 serial_out(up
, UART_LCR
, 0);
1028 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
|
1030 status1
= serial_in(up
, UART_IIR
) >> 5;
1031 serial_out(up
, UART_FCR
, 0);
1032 serial_out(up
, UART_LCR
, 0);
1035 up
->port
.type
= PORT_16550A_FSL64
;
1037 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1039 serial_out(up
, UART_EFR
, 0);
1044 * Maybe it requires 0xbf to be written to the LCR.
1045 * (other ST16C650V2 UARTs, TI16C752A, etc)
1047 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
1048 if (serial_in(up
, UART_EFR
) == 0 && !broken_efr(up
)) {
1049 DEBUG_AUTOCONF("EFRv2 ");
1050 autoconfig_has_efr(up
);
1055 * Check for a National Semiconductor SuperIO chip.
1056 * Attempt to switch to bank 2, read the value of the LOOP bit
1057 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1058 * switch back to bank 2, read it from EXCR1 again and check
1059 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1061 serial_out(up
, UART_LCR
, 0);
1062 status1
= serial8250_in_MCR(up
);
1063 serial_out(up
, UART_LCR
, 0xE0);
1064 status2
= serial_in(up
, 0x02); /* EXCR1 */
1066 if (!((status2
^ status1
) & UART_MCR_LOOP
)) {
1067 serial_out(up
, UART_LCR
, 0);
1068 serial8250_out_MCR(up
, status1
^ UART_MCR_LOOP
);
1069 serial_out(up
, UART_LCR
, 0xE0);
1070 status2
= serial_in(up
, 0x02); /* EXCR1 */
1071 serial_out(up
, UART_LCR
, 0);
1072 serial8250_out_MCR(up
, status1
);
1074 if ((status2
^ status1
) & UART_MCR_LOOP
) {
1075 unsigned short quot
;
1077 serial_out(up
, UART_LCR
, 0xE0);
1079 quot
= serial_dl_read(up
);
1082 if (ns16550a_goto_highspeed(up
))
1083 serial_dl_write(up
, quot
);
1085 serial_out(up
, UART_LCR
, 0);
1087 up
->port
.uartclk
= 921600*16;
1088 up
->port
.type
= PORT_NS16550A
;
1089 up
->capabilities
|= UART_NATSEMI
;
1095 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1096 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1097 * Try setting it with and without DLAB set. Cheap clones
1098 * set bit 5 without DLAB set.
1100 serial_out(up
, UART_LCR
, 0);
1101 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
| UART_FCR7_64BYTE
);
1102 status1
= serial_in(up
, UART_IIR
) >> 5;
1103 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
);
1104 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
1105 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
| UART_FCR7_64BYTE
);
1106 status2
= serial_in(up
, UART_IIR
) >> 5;
1107 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
);
1108 serial_out(up
, UART_LCR
, 0);
1110 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1
, status2
);
1112 if (status1
== 6 && status2
== 7) {
1113 up
->port
.type
= PORT_16750
;
1114 up
->capabilities
|= UART_CAP_AFE
| UART_CAP_SLEEP
;
1119 * Try writing and reading the UART_IER_UUE bit (b6).
1120 * If it works, this is probably one of the Xscale platform's
1122 * We're going to explicitly set the UUE bit to 0 before
1123 * trying to write and read a 1 just to make sure it's not
1124 * already a 1 and maybe locked there before we even start start.
1126 iersave
= serial_in(up
, UART_IER
);
1127 serial_out(up
, UART_IER
, iersave
& ~UART_IER_UUE
);
1128 if (!(serial_in(up
, UART_IER
) & UART_IER_UUE
)) {
1130 * OK it's in a known zero state, try writing and reading
1131 * without disturbing the current state of the other bits.
1133 serial_out(up
, UART_IER
, iersave
| UART_IER_UUE
);
1134 if (serial_in(up
, UART_IER
) & UART_IER_UUE
) {
1137 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1139 DEBUG_AUTOCONF("Xscale ");
1140 up
->port
.type
= PORT_XSCALE
;
1141 up
->capabilities
|= UART_CAP_UUE
| UART_CAP_RTOIE
;
1146 * If we got here we couldn't force the IER_UUE bit to 0.
1147 * Log it and continue.
1149 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1151 serial_out(up
, UART_IER
, iersave
);
1154 * Exar uarts have EFR in a weird location
1156 if (up
->port
.flags
& UPF_EXAR_EFR
) {
1157 DEBUG_AUTOCONF("Exar XR17D15x ");
1158 up
->port
.type
= PORT_XR17D15X
;
1159 up
->capabilities
|= UART_CAP_AFE
| UART_CAP_EFR
|
1166 * We distinguish between 16550A and U6 16550A by counting
1167 * how many bytes are in the FIFO.
1169 if (up
->port
.type
== PORT_16550A
&& size_fifo(up
) == 64) {
1170 up
->port
.type
= PORT_U6_16550A
;
1171 up
->capabilities
|= UART_CAP_AFE
;
1176 * This routine is called by rs_init() to initialize a specific serial
1177 * port. It determines what type of UART chip this serial port is
1178 * using: 8250, 16450, 16550, 16550A. The important question is
1179 * whether or not this UART is a 16550A or not, since this will
1180 * determine whether or not we can use its FIFO features or not.
1182 static void autoconfig(struct uart_8250_port
*up
)
1184 unsigned char status1
, scratch
, scratch2
, scratch3
;
1185 unsigned char save_lcr
, save_mcr
;
1186 struct uart_port
*port
= &up
->port
;
1187 unsigned long flags
;
1188 unsigned int old_capabilities
;
1190 if (!port
->iobase
&& !port
->mapbase
&& !port
->membase
)
1193 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1194 serial_index(port
), port
->iobase
, port
->membase
);
1197 * We really do need global IRQs disabled here - we're going to
1198 * be frobbing the chips IRQ enable register to see if it exists.
1200 spin_lock_irqsave(&port
->lock
, flags
);
1202 up
->capabilities
= 0;
1205 if (!(port
->flags
& UPF_BUGGY_UART
)) {
1207 * Do a simple existence test first; if we fail this,
1208 * there's no point trying anything else.
1210 * 0x80 is used as a nonsense port to prevent against
1211 * false positives due to ISA bus float. The
1212 * assumption is that 0x80 is a non-existent port;
1213 * which should be safe since include/asm/io.h also
1214 * makes this assumption.
1216 * Note: this is safe as long as MCR bit 4 is clear
1217 * and the device is in "PC" mode.
1219 scratch
= serial_in(up
, UART_IER
);
1220 serial_out(up
, UART_IER
, 0);
1225 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1226 * 16C754B) allow only to modify them if an EFR bit is set.
1228 scratch2
= serial_in(up
, UART_IER
) & 0x0f;
1229 serial_out(up
, UART_IER
, 0x0F);
1233 scratch3
= serial_in(up
, UART_IER
) & 0x0f;
1234 serial_out(up
, UART_IER
, scratch
);
1235 if (scratch2
!= 0 || scratch3
!= 0x0F) {
1237 * We failed; there's nothing here
1239 spin_unlock_irqrestore(&port
->lock
, flags
);
1240 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1241 scratch2
, scratch3
);
1246 save_mcr
= serial8250_in_MCR(up
);
1247 save_lcr
= serial_in(up
, UART_LCR
);
1250 * Check to see if a UART is really there. Certain broken
1251 * internal modems based on the Rockwell chipset fail this
1252 * test, because they apparently don't implement the loopback
1253 * test mode. So this test is skipped on the COM 1 through
1254 * COM 4 ports. This *should* be safe, since no board
1255 * manufacturer would be stupid enough to design a board
1256 * that conflicts with COM 1-4 --- we hope!
1258 if (!(port
->flags
& UPF_SKIP_TEST
)) {
1259 serial8250_out_MCR(up
, UART_MCR_LOOP
| 0x0A);
1260 status1
= serial_in(up
, UART_MSR
) & 0xF0;
1261 serial8250_out_MCR(up
, save_mcr
);
1262 if (status1
!= 0x90) {
1263 spin_unlock_irqrestore(&port
->lock
, flags
);
1264 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1271 * We're pretty sure there's a port here. Lets find out what
1272 * type of port it is. The IIR top two bits allows us to find
1273 * out if it's 8250 or 16450, 16550, 16550A or later. This
1274 * determines what we test for next.
1276 * We also initialise the EFR (if any) to zero for later. The
1277 * EFR occupies the same register location as the FCR and IIR.
1279 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
1280 serial_out(up
, UART_EFR
, 0);
1281 serial_out(up
, UART_LCR
, 0);
1283 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
);
1284 scratch
= serial_in(up
, UART_IIR
) >> 6;
1288 autoconfig_8250(up
);
1291 port
->type
= PORT_UNKNOWN
;
1294 port
->type
= PORT_16550
;
1297 autoconfig_16550a(up
);
1301 #ifdef CONFIG_SERIAL_8250_RSA
1303 * Only probe for RSA ports if we got the region.
1305 if (port
->type
== PORT_16550A
&& up
->probe
& UART_PROBE_RSA
&&
1307 port
->type
= PORT_RSA
;
1310 serial_out(up
, UART_LCR
, save_lcr
);
1312 port
->fifosize
= uart_config
[up
->port
.type
].fifo_size
;
1313 old_capabilities
= up
->capabilities
;
1314 up
->capabilities
= uart_config
[port
->type
].flags
;
1315 up
->tx_loadsz
= uart_config
[port
->type
].tx_loadsz
;
1317 if (port
->type
== PORT_UNKNOWN
)
1323 #ifdef CONFIG_SERIAL_8250_RSA
1324 if (port
->type
== PORT_RSA
)
1325 serial_out(up
, UART_RSA_FRR
, 0);
1327 serial8250_out_MCR(up
, save_mcr
);
1328 serial8250_clear_fifos(up
);
1329 serial_in(up
, UART_RX
);
1330 if (up
->capabilities
& UART_CAP_UUE
)
1331 serial_out(up
, UART_IER
, UART_IER_UUE
);
1333 serial_out(up
, UART_IER
, 0);
1336 spin_unlock_irqrestore(&port
->lock
, flags
);
1339 * Check if the device is a Fintek F81216A
1341 if (port
->type
== PORT_16550A
&& port
->iotype
== UPIO_PORT
)
1342 fintek_8250_probe(up
);
1344 if (up
->capabilities
!= old_capabilities
) {
1345 pr_warn("ttyS%d: detected caps %08x should be %08x\n",
1346 serial_index(port
), old_capabilities
,
1350 DEBUG_AUTOCONF("iir=%d ", scratch
);
1351 DEBUG_AUTOCONF("type=%s\n", uart_config
[port
->type
].name
);
1354 static void autoconfig_irq(struct uart_8250_port
*up
)
1356 struct uart_port
*port
= &up
->port
;
1357 unsigned char save_mcr
, save_ier
;
1358 unsigned char save_ICP
= 0;
1359 unsigned int ICP
= 0;
1363 if (port
->flags
& UPF_FOURPORT
) {
1364 ICP
= (port
->iobase
& 0xfe0) | 0x1f;
1365 save_ICP
= inb_p(ICP
);
1370 if (uart_console(port
))
1373 /* forget possible initially masked and pending IRQ */
1374 probe_irq_off(probe_irq_on());
1375 save_mcr
= serial8250_in_MCR(up
);
1376 save_ier
= serial_in(up
, UART_IER
);
1377 serial8250_out_MCR(up
, UART_MCR_OUT1
| UART_MCR_OUT2
);
1379 irqs
= probe_irq_on();
1380 serial8250_out_MCR(up
, 0);
1382 if (port
->flags
& UPF_FOURPORT
) {
1383 serial8250_out_MCR(up
, UART_MCR_DTR
| UART_MCR_RTS
);
1385 serial8250_out_MCR(up
,
1386 UART_MCR_DTR
| UART_MCR_RTS
| UART_MCR_OUT2
);
1388 serial_out(up
, UART_IER
, 0x0f); /* enable all intrs */
1389 serial_in(up
, UART_LSR
);
1390 serial_in(up
, UART_RX
);
1391 serial_in(up
, UART_IIR
);
1392 serial_in(up
, UART_MSR
);
1393 serial_out(up
, UART_TX
, 0xFF);
1395 irq
= probe_irq_off(irqs
);
1397 serial8250_out_MCR(up
, save_mcr
);
1398 serial_out(up
, UART_IER
, save_ier
);
1400 if (port
->flags
& UPF_FOURPORT
)
1401 outb_p(save_ICP
, ICP
);
1403 if (uart_console(port
))
1406 port
->irq
= (irq
> 0) ? irq
: 0;
1409 static void serial8250_stop_rx(struct uart_port
*port
)
1411 struct uart_8250_port
*up
= up_to_u8250p(port
);
1413 serial8250_rpm_get(up
);
1415 up
->ier
&= ~(UART_IER_RLSI
| UART_IER_RDI
);
1416 up
->port
.read_status_mask
&= ~UART_LSR_DR
;
1417 serial_port_out(port
, UART_IER
, up
->ier
);
1419 serial8250_rpm_put(up
);
1422 static void __do_stop_tx_rs485(struct uart_8250_port
*p
)
1424 serial8250_em485_rts_after_send(p
);
1427 * Empty the RX FIFO, we are not interested in anything
1428 * received during the half-duplex transmission.
1429 * Enable previously disabled RX interrupts.
1431 if (!(p
->port
.rs485
.flags
& SER_RS485_RX_DURING_TX
)) {
1432 serial8250_clear_and_reinit_fifos(p
);
1434 p
->ier
|= UART_IER_RLSI
| UART_IER_RDI
;
1435 serial_port_out(&p
->port
, UART_IER
, p
->ier
);
1439 static void serial8250_em485_handle_stop_tx(unsigned long arg
)
1441 struct uart_8250_port
*p
= (struct uart_8250_port
*)arg
;
1442 struct uart_8250_em485
*em485
= p
->em485
;
1443 unsigned long flags
;
1445 serial8250_rpm_get(p
);
1446 spin_lock_irqsave(&p
->port
.lock
, flags
);
1448 em485
->active_timer
== &em485
->stop_tx_timer
) {
1449 __do_stop_tx_rs485(p
);
1450 em485
->active_timer
= NULL
;
1452 spin_unlock_irqrestore(&p
->port
.lock
, flags
);
1453 serial8250_rpm_put(p
);
1456 static void __stop_tx_rs485(struct uart_8250_port
*p
)
1458 struct uart_8250_em485
*em485
= p
->em485
;
1461 * __do_stop_tx_rs485 is going to set RTS according to config
1462 * AND flush RX FIFO if required.
1464 if (p
->port
.rs485
.delay_rts_after_send
> 0) {
1465 em485
->active_timer
= &em485
->stop_tx_timer
;
1466 mod_timer(&em485
->stop_tx_timer
, jiffies
+
1467 p
->port
.rs485
.delay_rts_after_send
* HZ
/ 1000);
1469 __do_stop_tx_rs485(p
);
1473 static inline void __do_stop_tx(struct uart_8250_port
*p
)
1475 if (p
->ier
& UART_IER_THRI
) {
1476 p
->ier
&= ~UART_IER_THRI
;
1477 serial_out(p
, UART_IER
, p
->ier
);
1478 serial8250_rpm_put_tx(p
);
1482 static inline void __stop_tx(struct uart_8250_port
*p
)
1484 struct uart_8250_em485
*em485
= p
->em485
;
1487 unsigned char lsr
= serial_in(p
, UART_LSR
);
1489 * To provide required timeing and allow FIFO transfer,
1490 * __stop_tx_rs485() must be called only when both FIFO and
1491 * shift register are empty. It is for device driver to enable
1492 * interrupt on TEMT.
1494 if ((lsr
& BOTH_EMPTY
) != BOTH_EMPTY
)
1497 del_timer(&em485
->start_tx_timer
);
1498 em485
->active_timer
= NULL
;
1505 static void serial8250_stop_tx(struct uart_port
*port
)
1507 struct uart_8250_port
*up
= up_to_u8250p(port
);
1509 serial8250_rpm_get(up
);
1513 * We really want to stop the transmitter from sending.
1515 if (port
->type
== PORT_16C950
) {
1516 up
->acr
|= UART_ACR_TXDIS
;
1517 serial_icr_write(up
, UART_ACR
, up
->acr
);
1519 serial8250_rpm_put(up
);
1522 static inline void __start_tx(struct uart_port
*port
)
1524 struct uart_8250_port
*up
= up_to_u8250p(port
);
1526 if (up
->dma
&& !up
->dma
->tx_dma(up
))
1529 if (!(up
->ier
& UART_IER_THRI
)) {
1530 up
->ier
|= UART_IER_THRI
;
1531 serial_port_out(port
, UART_IER
, up
->ier
);
1533 if (up
->bugs
& UART_BUG_TXEN
) {
1536 lsr
= serial_in(up
, UART_LSR
);
1537 up
->lsr_saved_flags
|= lsr
& LSR_SAVE_FLAGS
;
1538 if (lsr
& UART_LSR_THRE
)
1539 serial8250_tx_chars(up
);
1544 * Re-enable the transmitter if we disabled it.
1546 if (port
->type
== PORT_16C950
&& up
->acr
& UART_ACR_TXDIS
) {
1547 up
->acr
&= ~UART_ACR_TXDIS
;
1548 serial_icr_write(up
, UART_ACR
, up
->acr
);
1552 static inline void start_tx_rs485(struct uart_port
*port
)
1554 struct uart_8250_port
*up
= up_to_u8250p(port
);
1555 struct uart_8250_em485
*em485
= up
->em485
;
1558 if (!(up
->port
.rs485
.flags
& SER_RS485_RX_DURING_TX
))
1559 serial8250_stop_rx(&up
->port
);
1561 del_timer(&em485
->stop_tx_timer
);
1562 em485
->active_timer
= NULL
;
1564 mcr
= serial8250_in_MCR(up
);
1565 if (!!(up
->port
.rs485
.flags
& SER_RS485_RTS_ON_SEND
) !=
1566 !!(mcr
& UART_MCR_RTS
)) {
1567 if (up
->port
.rs485
.flags
& SER_RS485_RTS_ON_SEND
)
1568 mcr
|= UART_MCR_RTS
;
1570 mcr
&= ~UART_MCR_RTS
;
1571 serial8250_out_MCR(up
, mcr
);
1573 if (up
->port
.rs485
.delay_rts_before_send
> 0) {
1574 em485
->active_timer
= &em485
->start_tx_timer
;
1575 mod_timer(&em485
->start_tx_timer
, jiffies
+
1576 up
->port
.rs485
.delay_rts_before_send
* HZ
/ 1000);
1584 static void serial8250_em485_handle_start_tx(unsigned long arg
)
1586 struct uart_8250_port
*p
= (struct uart_8250_port
*)arg
;
1587 struct uart_8250_em485
*em485
= p
->em485
;
1588 unsigned long flags
;
1590 spin_lock_irqsave(&p
->port
.lock
, flags
);
1592 em485
->active_timer
== &em485
->start_tx_timer
) {
1593 __start_tx(&p
->port
);
1594 em485
->active_timer
= NULL
;
1596 spin_unlock_irqrestore(&p
->port
.lock
, flags
);
1599 static void serial8250_start_tx(struct uart_port
*port
)
1601 struct uart_8250_port
*up
= up_to_u8250p(port
);
1602 struct uart_8250_em485
*em485
= up
->em485
;
1604 serial8250_rpm_get_tx(up
);
1607 em485
->active_timer
== &em485
->start_tx_timer
)
1611 start_tx_rs485(port
);
1616 static void serial8250_throttle(struct uart_port
*port
)
1618 port
->throttle(port
);
1621 static void serial8250_unthrottle(struct uart_port
*port
)
1623 port
->unthrottle(port
);
1626 static void serial8250_disable_ms(struct uart_port
*port
)
1628 struct uart_8250_port
*up
= up_to_u8250p(port
);
1630 /* no MSR capabilities */
1631 if (up
->bugs
& UART_BUG_NOMSR
)
1634 up
->ier
&= ~UART_IER_MSI
;
1635 serial_port_out(port
, UART_IER
, up
->ier
);
1638 static void serial8250_enable_ms(struct uart_port
*port
)
1640 struct uart_8250_port
*up
= up_to_u8250p(port
);
1642 /* no MSR capabilities */
1643 if (up
->bugs
& UART_BUG_NOMSR
)
1646 up
->ier
|= UART_IER_MSI
;
1648 serial8250_rpm_get(up
);
1649 serial_port_out(port
, UART_IER
, up
->ier
);
1650 serial8250_rpm_put(up
);
1653 static void serial8250_read_char(struct uart_8250_port
*up
, unsigned char lsr
)
1655 struct uart_port
*port
= &up
->port
;
1657 char flag
= TTY_NORMAL
;
1659 if (likely(lsr
& UART_LSR_DR
))
1660 ch
= serial_in(up
, UART_RX
);
1663 * Intel 82571 has a Serial Over Lan device that will
1664 * set UART_LSR_BI without setting UART_LSR_DR when
1665 * it receives a break. To avoid reading from the
1666 * receive buffer without UART_LSR_DR bit set, we
1667 * just force the read character to be 0
1673 lsr
|= up
->lsr_saved_flags
;
1674 up
->lsr_saved_flags
= 0;
1676 if (unlikely(lsr
& UART_LSR_BRK_ERROR_BITS
)) {
1677 if (lsr
& UART_LSR_BI
) {
1678 lsr
&= ~(UART_LSR_FE
| UART_LSR_PE
);
1681 * We do the SysRQ and SAK checking
1682 * here because otherwise the break
1683 * may get masked by ignore_status_mask
1684 * or read_status_mask.
1686 if (uart_handle_break(port
))
1688 } else if (lsr
& UART_LSR_PE
)
1689 port
->icount
.parity
++;
1690 else if (lsr
& UART_LSR_FE
)
1691 port
->icount
.frame
++;
1692 if (lsr
& UART_LSR_OE
)
1693 port
->icount
.overrun
++;
1696 * Mask off conditions which should be ignored.
1698 lsr
&= port
->read_status_mask
;
1700 if (lsr
& UART_LSR_BI
) {
1701 pr_debug("%s: handling break\n", __func__
);
1703 } else if (lsr
& UART_LSR_PE
)
1705 else if (lsr
& UART_LSR_FE
)
1708 if (uart_handle_sysrq_char(port
, ch
))
1711 uart_insert_char(port
, lsr
, UART_LSR_OE
, ch
, flag
);
1715 * serial8250_rx_chars: processes according to the passed in LSR
1716 * value, and returns the remaining LSR bits not handled
1717 * by this Rx routine.
1719 unsigned char serial8250_rx_chars(struct uart_8250_port
*up
, unsigned char lsr
)
1721 struct uart_port
*port
= &up
->port
;
1722 int max_count
= 256;
1725 serial8250_read_char(up
, lsr
);
1726 if (--max_count
== 0)
1728 lsr
= serial_in(up
, UART_LSR
);
1729 } while (lsr
& (UART_LSR_DR
| UART_LSR_BI
));
1731 tty_flip_buffer_push(&port
->state
->port
);
1734 EXPORT_SYMBOL_GPL(serial8250_rx_chars
);
1736 void serial8250_tx_chars(struct uart_8250_port
*up
)
1738 struct uart_port
*port
= &up
->port
;
1739 struct circ_buf
*xmit
= &port
->state
->xmit
;
1743 serial_out(up
, UART_TX
, port
->x_char
);
1748 if (uart_tx_stopped(port
)) {
1749 serial8250_stop_tx(port
);
1752 if (uart_circ_empty(xmit
)) {
1757 count
= up
->tx_loadsz
;
1759 serial_out(up
, UART_TX
, xmit
->buf
[xmit
->tail
]);
1760 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
1762 if (uart_circ_empty(xmit
))
1764 if ((up
->capabilities
& UART_CAP_HFIFO
) &&
1765 (serial_in(up
, UART_LSR
) & BOTH_EMPTY
) != BOTH_EMPTY
)
1767 } while (--count
> 0);
1769 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
1770 uart_write_wakeup(port
);
1773 * With RPM enabled, we have to wait until the FIFO is empty before the
1774 * HW can go idle. So we get here once again with empty FIFO and disable
1775 * the interrupt and RPM in __stop_tx()
1777 if (uart_circ_empty(xmit
) && !(up
->capabilities
& UART_CAP_RPM
))
1780 EXPORT_SYMBOL_GPL(serial8250_tx_chars
);
1782 /* Caller holds uart port lock */
1783 unsigned int serial8250_modem_status(struct uart_8250_port
*up
)
1785 struct uart_port
*port
= &up
->port
;
1786 unsigned int status
= serial_in(up
, UART_MSR
);
1788 status
|= up
->msr_saved_flags
;
1789 up
->msr_saved_flags
= 0;
1790 if (status
& UART_MSR_ANY_DELTA
&& up
->ier
& UART_IER_MSI
&&
1791 port
->state
!= NULL
) {
1792 if (status
& UART_MSR_TERI
)
1794 if (status
& UART_MSR_DDSR
)
1796 if (status
& UART_MSR_DDCD
)
1797 uart_handle_dcd_change(port
, status
& UART_MSR_DCD
);
1798 if (status
& UART_MSR_DCTS
)
1799 uart_handle_cts_change(port
, status
& UART_MSR_CTS
);
1801 wake_up_interruptible(&port
->state
->port
.delta_msr_wait
);
1806 EXPORT_SYMBOL_GPL(serial8250_modem_status
);
1808 static bool handle_rx_dma(struct uart_8250_port
*up
, unsigned int iir
)
1810 switch (iir
& 0x3f) {
1811 case UART_IIR_RX_TIMEOUT
:
1812 serial8250_rx_dma_flush(up
);
1817 return up
->dma
->rx_dma(up
);
1821 * This handles the interrupt from one port.
1823 int serial8250_handle_irq(struct uart_port
*port
, unsigned int iir
)
1825 unsigned char status
;
1826 unsigned long flags
;
1827 struct uart_8250_port
*up
= up_to_u8250p(port
);
1829 if (iir
& UART_IIR_NO_INT
)
1832 spin_lock_irqsave(&port
->lock
, flags
);
1834 status
= serial_port_in(port
, UART_LSR
);
1836 if (status
& (UART_LSR_DR
| UART_LSR_BI
)) {
1837 if (!up
->dma
|| handle_rx_dma(up
, iir
))
1838 status
= serial8250_rx_chars(up
, status
);
1840 serial8250_modem_status(up
);
1841 if ((!up
->dma
|| up
->dma
->tx_err
) && (status
& UART_LSR_THRE
))
1842 serial8250_tx_chars(up
);
1844 spin_unlock_irqrestore(&port
->lock
, flags
);
1847 EXPORT_SYMBOL_GPL(serial8250_handle_irq
);
1849 static int serial8250_default_handle_irq(struct uart_port
*port
)
1851 struct uart_8250_port
*up
= up_to_u8250p(port
);
1855 serial8250_rpm_get(up
);
1857 iir
= serial_port_in(port
, UART_IIR
);
1858 ret
= serial8250_handle_irq(port
, iir
);
1860 serial8250_rpm_put(up
);
1865 * These Exar UARTs have an extra interrupt indicator that could
1866 * fire for a few unimplemented interrupts. One of which is a
1867 * wakeup event when coming out of sleep. Put this here just
1868 * to be on the safe side that these interrupts don't go unhandled.
1870 static int exar_handle_irq(struct uart_port
*port
)
1872 unsigned int iir
= serial_port_in(port
, UART_IIR
);
1875 if (((port
->type
== PORT_XR17V35X
) || (port
->type
== PORT_XR17D15X
)) &&
1876 serial_port_in(port
, UART_EXAR_INT0
) != 0)
1879 ret
|= serial8250_handle_irq(port
, iir
);
1885 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1886 * have a programmable TX threshold that triggers the THRE interrupt in
1887 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1888 * has space available. Load it up with tx_loadsz bytes.
1890 static int serial8250_tx_threshold_handle_irq(struct uart_port
*port
)
1892 unsigned long flags
;
1893 unsigned int iir
= serial_port_in(port
, UART_IIR
);
1895 /* TX Threshold IRQ triggered so load up FIFO */
1896 if ((iir
& UART_IIR_ID
) == UART_IIR_THRI
) {
1897 struct uart_8250_port
*up
= up_to_u8250p(port
);
1899 spin_lock_irqsave(&port
->lock
, flags
);
1900 serial8250_tx_chars(up
);
1901 spin_unlock_irqrestore(&port
->lock
, flags
);
1904 iir
= serial_port_in(port
, UART_IIR
);
1905 return serial8250_handle_irq(port
, iir
);
1908 static unsigned int serial8250_tx_empty(struct uart_port
*port
)
1910 struct uart_8250_port
*up
= up_to_u8250p(port
);
1911 unsigned long flags
;
1914 serial8250_rpm_get(up
);
1916 spin_lock_irqsave(&port
->lock
, flags
);
1917 lsr
= serial_port_in(port
, UART_LSR
);
1918 up
->lsr_saved_flags
|= lsr
& LSR_SAVE_FLAGS
;
1919 spin_unlock_irqrestore(&port
->lock
, flags
);
1921 serial8250_rpm_put(up
);
1923 return (lsr
& BOTH_EMPTY
) == BOTH_EMPTY
? TIOCSER_TEMT
: 0;
1926 unsigned int serial8250_do_get_mctrl(struct uart_port
*port
)
1928 struct uart_8250_port
*up
= up_to_u8250p(port
);
1929 unsigned int status
;
1932 serial8250_rpm_get(up
);
1933 status
= serial8250_modem_status(up
);
1934 serial8250_rpm_put(up
);
1937 if (status
& UART_MSR_DCD
)
1939 if (status
& UART_MSR_RI
)
1941 if (status
& UART_MSR_DSR
)
1943 if (status
& UART_MSR_CTS
)
1947 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl
);
1949 static unsigned int serial8250_get_mctrl(struct uart_port
*port
)
1951 if (port
->get_mctrl
)
1952 return port
->get_mctrl(port
);
1953 return serial8250_do_get_mctrl(port
);
1956 void serial8250_do_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
1958 struct uart_8250_port
*up
= up_to_u8250p(port
);
1959 unsigned char mcr
= 0;
1961 if (mctrl
& TIOCM_RTS
)
1962 mcr
|= UART_MCR_RTS
;
1963 if (mctrl
& TIOCM_DTR
)
1964 mcr
|= UART_MCR_DTR
;
1965 if (mctrl
& TIOCM_OUT1
)
1966 mcr
|= UART_MCR_OUT1
;
1967 if (mctrl
& TIOCM_OUT2
)
1968 mcr
|= UART_MCR_OUT2
;
1969 if (mctrl
& TIOCM_LOOP
)
1970 mcr
|= UART_MCR_LOOP
;
1972 mcr
= (mcr
& up
->mcr_mask
) | up
->mcr_force
| up
->mcr
;
1974 serial8250_out_MCR(up
, mcr
);
1976 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl
);
1978 static void serial8250_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
1980 if (port
->set_mctrl
)
1981 port
->set_mctrl(port
, mctrl
);
1983 serial8250_do_set_mctrl(port
, mctrl
);
1986 static void serial8250_break_ctl(struct uart_port
*port
, int break_state
)
1988 struct uart_8250_port
*up
= up_to_u8250p(port
);
1989 unsigned long flags
;
1991 serial8250_rpm_get(up
);
1992 spin_lock_irqsave(&port
->lock
, flags
);
1993 if (break_state
== -1)
1994 up
->lcr
|= UART_LCR_SBC
;
1996 up
->lcr
&= ~UART_LCR_SBC
;
1997 serial_port_out(port
, UART_LCR
, up
->lcr
);
1998 spin_unlock_irqrestore(&port
->lock
, flags
);
1999 serial8250_rpm_put(up
);
2003 * Wait for transmitter & holding register to empty
2005 static void wait_for_xmitr(struct uart_8250_port
*up
, int bits
)
2007 unsigned int status
, tmout
= 10000;
2009 /* Wait up to 10ms for the character(s) to be sent. */
2011 status
= serial_in(up
, UART_LSR
);
2013 up
->lsr_saved_flags
|= status
& LSR_SAVE_FLAGS
;
2015 if ((status
& bits
) == bits
)
2020 touch_nmi_watchdog();
2023 /* Wait up to 1s for flow control if necessary */
2024 if (up
->port
.flags
& UPF_CONS_FLOW
) {
2025 for (tmout
= 1000000; tmout
; tmout
--) {
2026 unsigned int msr
= serial_in(up
, UART_MSR
);
2027 up
->msr_saved_flags
|= msr
& MSR_SAVE_FLAGS
;
2028 if (msr
& UART_MSR_CTS
)
2031 touch_nmi_watchdog();
2036 #ifdef CONFIG_CONSOLE_POLL
2038 * Console polling routines for writing and reading from the uart while
2039 * in an interrupt or debug context.
2042 static int serial8250_get_poll_char(struct uart_port
*port
)
2044 struct uart_8250_port
*up
= up_to_u8250p(port
);
2048 serial8250_rpm_get(up
);
2050 lsr
= serial_port_in(port
, UART_LSR
);
2052 if (!(lsr
& UART_LSR_DR
)) {
2053 status
= NO_POLL_CHAR
;
2057 status
= serial_port_in(port
, UART_RX
);
2059 serial8250_rpm_put(up
);
2064 static void serial8250_put_poll_char(struct uart_port
*port
,
2068 struct uart_8250_port
*up
= up_to_u8250p(port
);
2070 serial8250_rpm_get(up
);
2072 * First save the IER then disable the interrupts
2074 ier
= serial_port_in(port
, UART_IER
);
2075 if (up
->capabilities
& UART_CAP_UUE
)
2076 serial_port_out(port
, UART_IER
, UART_IER_UUE
);
2078 serial_port_out(port
, UART_IER
, 0);
2080 wait_for_xmitr(up
, BOTH_EMPTY
);
2082 * Send the character out.
2084 serial_port_out(port
, UART_TX
, c
);
2087 * Finally, wait for transmitter to become empty
2088 * and restore the IER
2090 wait_for_xmitr(up
, BOTH_EMPTY
);
2091 serial_port_out(port
, UART_IER
, ier
);
2092 serial8250_rpm_put(up
);
2095 #endif /* CONFIG_CONSOLE_POLL */
2097 int serial8250_do_startup(struct uart_port
*port
)
2099 struct uart_8250_port
*up
= up_to_u8250p(port
);
2100 unsigned long flags
;
2101 unsigned char lsr
, iir
;
2104 if (!port
->fifosize
)
2105 port
->fifosize
= uart_config
[port
->type
].fifo_size
;
2107 up
->tx_loadsz
= uart_config
[port
->type
].tx_loadsz
;
2108 if (!up
->capabilities
)
2109 up
->capabilities
= uart_config
[port
->type
].flags
;
2112 if (port
->iotype
!= up
->cur_iotype
)
2113 set_io_from_upio(port
);
2115 serial8250_rpm_get(up
);
2116 if (port
->type
== PORT_16C950
) {
2117 /* Wake up and initialize UART */
2119 serial_port_out(port
, UART_LCR
, UART_LCR_CONF_MODE_B
);
2120 serial_port_out(port
, UART_EFR
, UART_EFR_ECB
);
2121 serial_port_out(port
, UART_IER
, 0);
2122 serial_port_out(port
, UART_LCR
, 0);
2123 serial_icr_write(up
, UART_CSR
, 0); /* Reset the UART */
2124 serial_port_out(port
, UART_LCR
, UART_LCR_CONF_MODE_B
);
2125 serial_port_out(port
, UART_EFR
, UART_EFR_ECB
);
2126 serial_port_out(port
, UART_LCR
, 0);
2129 if (port
->type
== PORT_DA830
) {
2130 /* Reset the port */
2131 serial_port_out(port
, UART_IER
, 0);
2132 serial_port_out(port
, UART_DA830_PWREMU_MGMT
, 0);
2135 /* Enable Tx, Rx and free run mode */
2136 serial_port_out(port
, UART_DA830_PWREMU_MGMT
,
2137 UART_DA830_PWREMU_MGMT_UTRST
|
2138 UART_DA830_PWREMU_MGMT_URRST
|
2139 UART_DA830_PWREMU_MGMT_FREE
);
2142 #ifdef CONFIG_SERIAL_8250_RSA
2144 * If this is an RSA port, see if we can kick it up to the
2145 * higher speed clock.
2150 if (port
->type
== PORT_XR17V35X
) {
2152 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
2153 * MCR [7:5] and MSR [7:0]
2155 serial_port_out(port
, UART_XR_EFR
, UART_EFR_ECB
);
2158 * Make sure all interrups are masked until initialization is
2159 * complete and the FIFOs are cleared
2161 serial_port_out(port
, UART_IER
, 0);
2165 * Clear the FIFO buffers and disable them.
2166 * (they will be reenabled in set_termios())
2168 serial8250_clear_fifos(up
);
2171 * Clear the interrupt registers.
2173 serial_port_in(port
, UART_LSR
);
2174 serial_port_in(port
, UART_RX
);
2175 serial_port_in(port
, UART_IIR
);
2176 serial_port_in(port
, UART_MSR
);
2177 if ((port
->type
== PORT_XR17V35X
) || (port
->type
== PORT_XR17D15X
))
2178 serial_port_in(port
, UART_EXAR_INT0
);
2181 * At this point, there's no way the LSR could still be 0xff;
2182 * if it is, then bail out, because there's likely no UART
2185 if (!(port
->flags
& UPF_BUGGY_UART
) &&
2186 (serial_port_in(port
, UART_LSR
) == 0xff)) {
2187 printk_ratelimited(KERN_INFO
"ttyS%d: LSR safety check engaged!\n",
2188 serial_index(port
));
2194 * For a XR16C850, we need to set the trigger levels
2196 if (port
->type
== PORT_16850
) {
2199 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
2201 fctr
= serial_in(up
, UART_FCTR
) & ~(UART_FCTR_RX
|UART_FCTR_TX
);
2202 serial_port_out(port
, UART_FCTR
,
2203 fctr
| UART_FCTR_TRGD
| UART_FCTR_RX
);
2204 serial_port_out(port
, UART_TRG
, UART_TRG_96
);
2205 serial_port_out(port
, UART_FCTR
,
2206 fctr
| UART_FCTR_TRGD
| UART_FCTR_TX
);
2207 serial_port_out(port
, UART_TRG
, UART_TRG_96
);
2209 serial_port_out(port
, UART_LCR
, 0);
2213 * For the Altera 16550 variants, set TX threshold trigger level.
2215 if (((port
->type
== PORT_ALTR_16550_F32
) ||
2216 (port
->type
== PORT_ALTR_16550_F64
) ||
2217 (port
->type
== PORT_ALTR_16550_F128
)) && (port
->fifosize
> 1)) {
2218 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2219 if ((up
->tx_loadsz
< 2) || (up
->tx_loadsz
> port
->fifosize
)) {
2220 pr_err("ttyS%d TX FIFO Threshold errors, skipping\n",
2221 serial_index(port
));
2223 serial_port_out(port
, UART_ALTR_AFR
,
2224 UART_ALTR_EN_TXFIFO_LW
);
2225 serial_port_out(port
, UART_ALTR_TX_LOW
,
2226 port
->fifosize
- up
->tx_loadsz
);
2227 port
->handle_irq
= serial8250_tx_threshold_handle_irq
;
2234 * Test for UARTs that do not reassert THRE when the
2235 * transmitter is idle and the interrupt has already
2236 * been cleared. Real 16550s should always reassert
2237 * this interrupt whenever the transmitter is idle and
2238 * the interrupt is enabled. Delays are necessary to
2239 * allow register changes to become visible.
2241 spin_lock_irqsave(&port
->lock
, flags
);
2242 if (up
->port
.irqflags
& IRQF_SHARED
)
2243 disable_irq_nosync(port
->irq
);
2245 wait_for_xmitr(up
, UART_LSR_THRE
);
2246 serial_port_out_sync(port
, UART_IER
, UART_IER_THRI
);
2247 udelay(1); /* allow THRE to set */
2248 iir1
= serial_port_in(port
, UART_IIR
);
2249 serial_port_out(port
, UART_IER
, 0);
2250 serial_port_out_sync(port
, UART_IER
, UART_IER_THRI
);
2251 udelay(1); /* allow a working UART time to re-assert THRE */
2252 iir
= serial_port_in(port
, UART_IIR
);
2253 serial_port_out(port
, UART_IER
, 0);
2255 if (port
->irqflags
& IRQF_SHARED
)
2256 enable_irq(port
->irq
);
2257 spin_unlock_irqrestore(&port
->lock
, flags
);
2260 * If the interrupt is not reasserted, or we otherwise
2261 * don't trust the iir, setup a timer to kick the UART
2262 * on a regular basis.
2264 if ((!(iir1
& UART_IIR_NO_INT
) && (iir
& UART_IIR_NO_INT
)) ||
2265 up
->port
.flags
& UPF_BUG_THRE
) {
2266 up
->bugs
|= UART_BUG_THRE
;
2270 retval
= up
->ops
->setup_irq(up
);
2275 * Now, initialize the UART
2277 serial_port_out(port
, UART_LCR
, UART_LCR_WLEN8
);
2279 spin_lock_irqsave(&port
->lock
, flags
);
2280 if (up
->port
.flags
& UPF_FOURPORT
) {
2282 up
->port
.mctrl
|= TIOCM_OUT1
;
2285 * Most PC uarts need OUT2 raised to enable interrupts.
2288 up
->port
.mctrl
|= TIOCM_OUT2
;
2290 serial8250_set_mctrl(port
, port
->mctrl
);
2293 * Serial over Lan (SoL) hack:
2294 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2295 * used for Serial Over Lan. Those chips take a longer time than a
2296 * normal serial device to signalize that a transmission data was
2297 * queued. Due to that, the above test generally fails. One solution
2298 * would be to delay the reading of iir. However, this is not
2299 * reliable, since the timeout is variable. So, let's just don't
2300 * test if we receive TX irq. This way, we'll never enable
2303 if (up
->port
.flags
& UPF_NO_TXEN_TEST
)
2304 goto dont_test_tx_en
;
2307 * Do a quick test to see if we receive an interrupt when we enable
2310 serial_port_out(port
, UART_IER
, UART_IER_THRI
);
2311 lsr
= serial_port_in(port
, UART_LSR
);
2312 iir
= serial_port_in(port
, UART_IIR
);
2313 serial_port_out(port
, UART_IER
, 0);
2315 if (lsr
& UART_LSR_TEMT
&& iir
& UART_IIR_NO_INT
) {
2316 if (!(up
->bugs
& UART_BUG_TXEN
)) {
2317 up
->bugs
|= UART_BUG_TXEN
;
2318 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2319 serial_index(port
));
2322 up
->bugs
&= ~UART_BUG_TXEN
;
2326 spin_unlock_irqrestore(&port
->lock
, flags
);
2329 * Clear the interrupt registers again for luck, and clear the
2330 * saved flags to avoid getting false values from polling
2331 * routines or the previous session.
2333 serial_port_in(port
, UART_LSR
);
2334 serial_port_in(port
, UART_RX
);
2335 serial_port_in(port
, UART_IIR
);
2336 serial_port_in(port
, UART_MSR
);
2337 if ((port
->type
== PORT_XR17V35X
) || (port
->type
== PORT_XR17D15X
))
2338 serial_port_in(port
, UART_EXAR_INT0
);
2339 up
->lsr_saved_flags
= 0;
2340 up
->msr_saved_flags
= 0;
2343 * Request DMA channels for both RX and TX.
2346 retval
= serial8250_request_dma(up
);
2348 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2349 serial_index(port
));
2355 * Set the IER shadow for rx interrupts but defer actual interrupt
2356 * enable until after the FIFOs are enabled; otherwise, an already-
2357 * active sender can swamp the interrupt handler with "too much work".
2359 up
->ier
= UART_IER_RLSI
| UART_IER_RDI
;
2361 if (port
->flags
& UPF_FOURPORT
) {
2364 * Enable interrupts on the AST Fourport board
2366 icp
= (port
->iobase
& 0xfe0) | 0x01f;
2372 serial8250_rpm_put(up
);
2375 EXPORT_SYMBOL_GPL(serial8250_do_startup
);
2377 static int serial8250_startup(struct uart_port
*port
)
2380 return port
->startup(port
);
2381 return serial8250_do_startup(port
);
2384 void serial8250_do_shutdown(struct uart_port
*port
)
2386 struct uart_8250_port
*up
= up_to_u8250p(port
);
2387 unsigned long flags
;
2389 serial8250_rpm_get(up
);
2391 * Disable interrupts from this port
2393 spin_lock_irqsave(&port
->lock
, flags
);
2395 serial_port_out(port
, UART_IER
, 0);
2396 spin_unlock_irqrestore(&port
->lock
, flags
);
2398 synchronize_irq(port
->irq
);
2401 serial8250_release_dma(up
);
2403 spin_lock_irqsave(&port
->lock
, flags
);
2404 if (port
->flags
& UPF_FOURPORT
) {
2405 /* reset interrupts on the AST Fourport board */
2406 inb((port
->iobase
& 0xfe0) | 0x1f);
2407 port
->mctrl
|= TIOCM_OUT1
;
2409 port
->mctrl
&= ~TIOCM_OUT2
;
2411 serial8250_set_mctrl(port
, port
->mctrl
);
2412 spin_unlock_irqrestore(&port
->lock
, flags
);
2415 * Disable break condition and FIFOs
2417 serial_port_out(port
, UART_LCR
,
2418 serial_port_in(port
, UART_LCR
) & ~UART_LCR_SBC
);
2419 serial8250_clear_fifos(up
);
2421 #ifdef CONFIG_SERIAL_8250_RSA
2423 * Reset the RSA board back to 115kbps compat mode.
2429 * Read data port to reset things, and then unlink from
2432 serial_port_in(port
, UART_RX
);
2433 serial8250_rpm_put(up
);
2435 up
->ops
->release_irq(up
);
2437 EXPORT_SYMBOL_GPL(serial8250_do_shutdown
);
2439 static void serial8250_shutdown(struct uart_port
*port
)
2442 port
->shutdown(port
);
2444 serial8250_do_shutdown(port
);
2448 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2449 * Calculate divisor with extra 4-bit fractional portion
2451 static unsigned int xr17v35x_get_divisor(struct uart_8250_port
*up
,
2455 struct uart_port
*port
= &up
->port
;
2456 unsigned int quot_16
;
2458 quot_16
= DIV_ROUND_CLOSEST(port
->uartclk
, baud
);
2459 *frac
= quot_16
& 0x0f;
2461 return quot_16
>> 4;
2464 static unsigned int serial8250_get_divisor(struct uart_8250_port
*up
,
2468 struct uart_port
*port
= &up
->port
;
2472 * Handle magic divisors for baud rates above baud_base on
2473 * SMSC SuperIO chips.
2476 if ((port
->flags
& UPF_MAGIC_MULTIPLIER
) &&
2477 baud
== (port
->uartclk
/4))
2479 else if ((port
->flags
& UPF_MAGIC_MULTIPLIER
) &&
2480 baud
== (port
->uartclk
/8))
2482 else if (up
->port
.type
== PORT_XR17V35X
)
2483 quot
= xr17v35x_get_divisor(up
, baud
, frac
);
2485 quot
= uart_get_divisor(port
, baud
);
2488 * Oxford Semi 952 rev B workaround
2490 if (up
->bugs
& UART_BUG_QUOT
&& (quot
& 0xff) == 0)
2496 static unsigned char serial8250_compute_lcr(struct uart_8250_port
*up
,
2501 switch (c_cflag
& CSIZE
) {
2503 cval
= UART_LCR_WLEN5
;
2506 cval
= UART_LCR_WLEN6
;
2509 cval
= UART_LCR_WLEN7
;
2513 cval
= UART_LCR_WLEN8
;
2517 if (c_cflag
& CSTOPB
)
2518 cval
|= UART_LCR_STOP
;
2519 if (c_cflag
& PARENB
) {
2520 cval
|= UART_LCR_PARITY
;
2521 if (up
->bugs
& UART_BUG_PARITY
)
2522 up
->fifo_bug
= true;
2524 if (!(c_cflag
& PARODD
))
2525 cval
|= UART_LCR_EPAR
;
2527 if (c_cflag
& CMSPAR
)
2528 cval
|= UART_LCR_SPAR
;
2534 static void serial8250_set_divisor(struct uart_port
*port
, unsigned int baud
,
2535 unsigned int quot
, unsigned int quot_frac
)
2537 struct uart_8250_port
*up
= up_to_u8250p(port
);
2539 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2540 if (is_omap1510_8250(up
)) {
2541 if (baud
== 115200) {
2543 serial_port_out(port
, UART_OMAP_OSC_12M_SEL
, 1);
2545 serial_port_out(port
, UART_OMAP_OSC_12M_SEL
, 0);
2549 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2550 * otherwise just set DLAB
2552 if (up
->capabilities
& UART_NATSEMI
)
2553 serial_port_out(port
, UART_LCR
, 0xe0);
2555 serial_port_out(port
, UART_LCR
, up
->lcr
| UART_LCR_DLAB
);
2557 serial_dl_write(up
, quot
);
2559 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2560 if (up
->port
.type
== PORT_XR17V35X
)
2561 serial_port_out(port
, 0x2, quot_frac
);
2564 static unsigned int serial8250_get_baud_rate(struct uart_port
*port
,
2565 struct ktermios
*termios
,
2566 struct ktermios
*old
)
2569 * Ask the core to calculate the divisor for us.
2570 * Allow 1% tolerance at the upper limit so uart clks marginally
2571 * slower than nominal still match standard baud rates without
2572 * causing transmission errors.
2574 return uart_get_baud_rate(port
, termios
, old
,
2575 port
->uartclk
/ 16 / 0xffff,
2580 serial8250_do_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
2581 struct ktermios
*old
)
2583 struct uart_8250_port
*up
= up_to_u8250p(port
);
2585 unsigned long flags
;
2586 unsigned int baud
, quot
, frac
= 0;
2588 cval
= serial8250_compute_lcr(up
, termios
->c_cflag
);
2590 baud
= serial8250_get_baud_rate(port
, termios
, old
);
2591 quot
= serial8250_get_divisor(up
, baud
, &frac
);
2594 * Ok, we're now changing the port state. Do it with
2595 * interrupts disabled.
2597 serial8250_rpm_get(up
);
2598 spin_lock_irqsave(&port
->lock
, flags
);
2600 up
->lcr
= cval
; /* Save computed LCR */
2602 if (up
->capabilities
& UART_CAP_FIFO
&& port
->fifosize
> 1) {
2603 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2604 if ((baud
< 2400 && !up
->dma
) || up
->fifo_bug
) {
2605 up
->fcr
&= ~UART_FCR_TRIGGER_MASK
;
2606 up
->fcr
|= UART_FCR_TRIGGER_1
;
2611 * MCR-based auto flow control. When AFE is enabled, RTS will be
2612 * deasserted when the receive FIFO contains more characters than
2613 * the trigger, or the MCR RTS bit is cleared.
2615 if (up
->capabilities
& UART_CAP_AFE
) {
2616 up
->mcr
&= ~UART_MCR_AFE
;
2617 if (termios
->c_cflag
& CRTSCTS
)
2618 up
->mcr
|= UART_MCR_AFE
;
2622 * Update the per-port timeout.
2624 uart_update_timeout(port
, termios
->c_cflag
, baud
);
2626 port
->read_status_mask
= UART_LSR_OE
| UART_LSR_THRE
| UART_LSR_DR
;
2627 if (termios
->c_iflag
& INPCK
)
2628 port
->read_status_mask
|= UART_LSR_FE
| UART_LSR_PE
;
2629 if (termios
->c_iflag
& (IGNBRK
| BRKINT
| PARMRK
))
2630 port
->read_status_mask
|= UART_LSR_BI
;
2633 * Characteres to ignore
2635 port
->ignore_status_mask
= 0;
2636 if (termios
->c_iflag
& IGNPAR
)
2637 port
->ignore_status_mask
|= UART_LSR_PE
| UART_LSR_FE
;
2638 if (termios
->c_iflag
& IGNBRK
) {
2639 port
->ignore_status_mask
|= UART_LSR_BI
;
2641 * If we're ignoring parity and break indicators,
2642 * ignore overruns too (for real raw support).
2644 if (termios
->c_iflag
& IGNPAR
)
2645 port
->ignore_status_mask
|= UART_LSR_OE
;
2649 * ignore all characters if CREAD is not set
2651 if ((termios
->c_cflag
& CREAD
) == 0)
2652 port
->ignore_status_mask
|= UART_LSR_DR
;
2655 * CTS flow control flag and modem status interrupts
2657 up
->ier
&= ~UART_IER_MSI
;
2658 if (!(up
->bugs
& UART_BUG_NOMSR
) &&
2659 UART_ENABLE_MS(&up
->port
, termios
->c_cflag
))
2660 up
->ier
|= UART_IER_MSI
;
2661 if (up
->capabilities
& UART_CAP_UUE
)
2662 up
->ier
|= UART_IER_UUE
;
2663 if (up
->capabilities
& UART_CAP_RTOIE
)
2664 up
->ier
|= UART_IER_RTOIE
;
2666 serial_port_out(port
, UART_IER
, up
->ier
);
2668 if (up
->capabilities
& UART_CAP_EFR
) {
2669 unsigned char efr
= 0;
2671 * TI16C752/Startech hardware flow control. FIXME:
2672 * - TI16C752 requires control thresholds to be set.
2673 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2675 if (termios
->c_cflag
& CRTSCTS
)
2676 efr
|= UART_EFR_CTS
;
2678 serial_port_out(port
, UART_LCR
, UART_LCR_CONF_MODE_B
);
2679 if (port
->flags
& UPF_EXAR_EFR
)
2680 serial_port_out(port
, UART_XR_EFR
, efr
);
2682 serial_port_out(port
, UART_EFR
, efr
);
2685 serial8250_set_divisor(port
, baud
, quot
, frac
);
2688 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2689 * is written without DLAB set, this mode will be disabled.
2691 if (port
->type
== PORT_16750
)
2692 serial_port_out(port
, UART_FCR
, up
->fcr
);
2694 serial_port_out(port
, UART_LCR
, up
->lcr
); /* reset DLAB */
2695 if (port
->type
!= PORT_16750
) {
2696 /* emulated UARTs (Lucent Venus 167x) need two steps */
2697 if (up
->fcr
& UART_FCR_ENABLE_FIFO
)
2698 serial_port_out(port
, UART_FCR
, UART_FCR_ENABLE_FIFO
);
2699 serial_port_out(port
, UART_FCR
, up
->fcr
); /* set fcr */
2701 serial8250_set_mctrl(port
, port
->mctrl
);
2702 spin_unlock_irqrestore(&port
->lock
, flags
);
2703 serial8250_rpm_put(up
);
2705 /* Don't rewrite B0 */
2706 if (tty_termios_baud_rate(termios
))
2707 tty_termios_encode_baud_rate(termios
, baud
, baud
);
2709 EXPORT_SYMBOL(serial8250_do_set_termios
);
2712 serial8250_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
2713 struct ktermios
*old
)
2715 if (port
->set_termios
)
2716 port
->set_termios(port
, termios
, old
);
2718 serial8250_do_set_termios(port
, termios
, old
);
2721 void serial8250_do_set_ldisc(struct uart_port
*port
, struct ktermios
*termios
)
2723 if (termios
->c_line
== N_PPS
) {
2724 port
->flags
|= UPF_HARDPPS_CD
;
2725 spin_lock_irq(&port
->lock
);
2726 serial8250_enable_ms(port
);
2727 spin_unlock_irq(&port
->lock
);
2729 port
->flags
&= ~UPF_HARDPPS_CD
;
2730 if (!UART_ENABLE_MS(port
, termios
->c_cflag
)) {
2731 spin_lock_irq(&port
->lock
);
2732 serial8250_disable_ms(port
);
2733 spin_unlock_irq(&port
->lock
);
2737 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc
);
2740 serial8250_set_ldisc(struct uart_port
*port
, struct ktermios
*termios
)
2742 if (port
->set_ldisc
)
2743 port
->set_ldisc(port
, termios
);
2745 serial8250_do_set_ldisc(port
, termios
);
2748 void serial8250_do_pm(struct uart_port
*port
, unsigned int state
,
2749 unsigned int oldstate
)
2751 struct uart_8250_port
*p
= up_to_u8250p(port
);
2753 serial8250_set_sleep(p
, state
!= 0);
2755 EXPORT_SYMBOL(serial8250_do_pm
);
2758 serial8250_pm(struct uart_port
*port
, unsigned int state
,
2759 unsigned int oldstate
)
2762 port
->pm(port
, state
, oldstate
);
2764 serial8250_do_pm(port
, state
, oldstate
);
2767 static unsigned int serial8250_port_size(struct uart_8250_port
*pt
)
2769 if (pt
->port
.mapsize
)
2770 return pt
->port
.mapsize
;
2771 if (pt
->port
.iotype
== UPIO_AU
) {
2772 if (pt
->port
.type
== PORT_RT2880
)
2776 if (is_omap1_8250(pt
))
2777 return 0x16 << pt
->port
.regshift
;
2779 return 8 << pt
->port
.regshift
;
2783 * Resource handling.
2785 static int serial8250_request_std_resource(struct uart_8250_port
*up
)
2787 unsigned int size
= serial8250_port_size(up
);
2788 struct uart_port
*port
= &up
->port
;
2791 switch (port
->iotype
) {
2801 if (!request_mem_region(port
->mapbase
, size
, "serial")) {
2806 if (port
->flags
& UPF_IOREMAP
) {
2807 port
->membase
= ioremap_nocache(port
->mapbase
, size
);
2808 if (!port
->membase
) {
2809 release_mem_region(port
->mapbase
, size
);
2817 if (!request_region(port
->iobase
, size
, "serial"))
2824 static void serial8250_release_std_resource(struct uart_8250_port
*up
)
2826 unsigned int size
= serial8250_port_size(up
);
2827 struct uart_port
*port
= &up
->port
;
2829 switch (port
->iotype
) {
2839 if (port
->flags
& UPF_IOREMAP
) {
2840 iounmap(port
->membase
);
2841 port
->membase
= NULL
;
2844 release_mem_region(port
->mapbase
, size
);
2849 release_region(port
->iobase
, size
);
2854 static void serial8250_release_port(struct uart_port
*port
)
2856 struct uart_8250_port
*up
= up_to_u8250p(port
);
2858 serial8250_release_std_resource(up
);
2861 static int serial8250_request_port(struct uart_port
*port
)
2863 struct uart_8250_port
*up
= up_to_u8250p(port
);
2865 return serial8250_request_std_resource(up
);
2868 static int fcr_get_rxtrig_bytes(struct uart_8250_port
*up
)
2870 const struct serial8250_config
*conf_type
= &uart_config
[up
->port
.type
];
2871 unsigned char bytes
;
2873 bytes
= conf_type
->rxtrig_bytes
[UART_FCR_R_TRIG_BITS(up
->fcr
)];
2875 return bytes
? bytes
: -EOPNOTSUPP
;
2878 static int bytes_to_fcr_rxtrig(struct uart_8250_port
*up
, unsigned char bytes
)
2880 const struct serial8250_config
*conf_type
= &uart_config
[up
->port
.type
];
2883 if (!conf_type
->rxtrig_bytes
[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00
)])
2886 for (i
= 1; i
< UART_FCR_R_TRIG_MAX_STATE
; i
++) {
2887 if (bytes
< conf_type
->rxtrig_bytes
[i
])
2888 /* Use the nearest lower value */
2889 return (--i
) << UART_FCR_R_TRIG_SHIFT
;
2892 return UART_FCR_R_TRIG_11
;
2895 static int do_get_rxtrig(struct tty_port
*port
)
2897 struct uart_state
*state
= container_of(port
, struct uart_state
, port
);
2898 struct uart_port
*uport
= state
->uart_port
;
2899 struct uart_8250_port
*up
= up_to_u8250p(uport
);
2901 if (!(up
->capabilities
& UART_CAP_FIFO
) || uport
->fifosize
<= 1)
2904 return fcr_get_rxtrig_bytes(up
);
2907 static int do_serial8250_get_rxtrig(struct tty_port
*port
)
2911 mutex_lock(&port
->mutex
);
2912 rxtrig_bytes
= do_get_rxtrig(port
);
2913 mutex_unlock(&port
->mutex
);
2915 return rxtrig_bytes
;
2918 static ssize_t
serial8250_get_attr_rx_trig_bytes(struct device
*dev
,
2919 struct device_attribute
*attr
, char *buf
)
2921 struct tty_port
*port
= dev_get_drvdata(dev
);
2924 rxtrig_bytes
= do_serial8250_get_rxtrig(port
);
2925 if (rxtrig_bytes
< 0)
2926 return rxtrig_bytes
;
2928 return snprintf(buf
, PAGE_SIZE
, "%d\n", rxtrig_bytes
);
2931 static int do_set_rxtrig(struct tty_port
*port
, unsigned char bytes
)
2933 struct uart_state
*state
= container_of(port
, struct uart_state
, port
);
2934 struct uart_port
*uport
= state
->uart_port
;
2935 struct uart_8250_port
*up
= up_to_u8250p(uport
);
2938 if (!(up
->capabilities
& UART_CAP_FIFO
) || uport
->fifosize
<= 1 ||
2942 rxtrig
= bytes_to_fcr_rxtrig(up
, bytes
);
2946 serial8250_clear_fifos(up
);
2947 up
->fcr
&= ~UART_FCR_TRIGGER_MASK
;
2948 up
->fcr
|= (unsigned char)rxtrig
;
2949 serial_out(up
, UART_FCR
, up
->fcr
);
2953 static int do_serial8250_set_rxtrig(struct tty_port
*port
, unsigned char bytes
)
2957 mutex_lock(&port
->mutex
);
2958 ret
= do_set_rxtrig(port
, bytes
);
2959 mutex_unlock(&port
->mutex
);
2964 static ssize_t
serial8250_set_attr_rx_trig_bytes(struct device
*dev
,
2965 struct device_attribute
*attr
, const char *buf
, size_t count
)
2967 struct tty_port
*port
= dev_get_drvdata(dev
);
2968 unsigned char bytes
;
2974 ret
= kstrtou8(buf
, 10, &bytes
);
2978 ret
= do_serial8250_set_rxtrig(port
, bytes
);
2985 static DEVICE_ATTR(rx_trig_bytes
, S_IRUSR
| S_IWUSR
| S_IRGRP
,
2986 serial8250_get_attr_rx_trig_bytes
,
2987 serial8250_set_attr_rx_trig_bytes
);
2989 static struct attribute
*serial8250_dev_attrs
[] = {
2990 &dev_attr_rx_trig_bytes
.attr
,
2994 static struct attribute_group serial8250_dev_attr_group
= {
2995 .attrs
= serial8250_dev_attrs
,
2998 static void register_dev_spec_attr_grp(struct uart_8250_port
*up
)
3000 const struct serial8250_config
*conf_type
= &uart_config
[up
->port
.type
];
3002 if (conf_type
->rxtrig_bytes
[0])
3003 up
->port
.attr_group
= &serial8250_dev_attr_group
;
3006 static void serial8250_config_port(struct uart_port
*port
, int flags
)
3008 struct uart_8250_port
*up
= up_to_u8250p(port
);
3012 * Find the region that we can probe for. This in turn
3013 * tells us whether we can probe for the type of port.
3015 ret
= serial8250_request_std_resource(up
);
3019 if (port
->iotype
!= up
->cur_iotype
)
3020 set_io_from_upio(port
);
3022 if (flags
& UART_CONFIG_TYPE
)
3025 /* if access method is AU, it is a 16550 with a quirk */
3026 if (port
->type
== PORT_16550A
&& port
->iotype
== UPIO_AU
)
3027 up
->bugs
|= UART_BUG_NOMSR
;
3029 /* HW bugs may trigger IRQ while IIR == NO_INT */
3030 if (port
->type
== PORT_TEGRA
)
3031 up
->bugs
|= UART_BUG_NOMSR
;
3033 if (port
->type
!= PORT_UNKNOWN
&& flags
& UART_CONFIG_IRQ
)
3036 if (port
->type
== PORT_UNKNOWN
)
3037 serial8250_release_std_resource(up
);
3039 /* Fixme: probably not the best place for this */
3040 if ((port
->type
== PORT_XR17V35X
) ||
3041 (port
->type
== PORT_XR17D15X
))
3042 port
->handle_irq
= exar_handle_irq
;
3044 register_dev_spec_attr_grp(up
);
3045 up
->fcr
= uart_config
[up
->port
.type
].fcr
;
3049 serial8250_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
3051 if (ser
->irq
>= nr_irqs
|| ser
->irq
< 0 ||
3052 ser
->baud_base
< 9600 || ser
->type
< PORT_UNKNOWN
||
3053 ser
->type
>= ARRAY_SIZE(uart_config
) || ser
->type
== PORT_CIRRUS
||
3054 ser
->type
== PORT_STARTECH
)
3059 static const char *serial8250_type(struct uart_port
*port
)
3061 int type
= port
->type
;
3063 if (type
>= ARRAY_SIZE(uart_config
))
3065 return uart_config
[type
].name
;
3068 static const struct uart_ops serial8250_pops
= {
3069 .tx_empty
= serial8250_tx_empty
,
3070 .set_mctrl
= serial8250_set_mctrl
,
3071 .get_mctrl
= serial8250_get_mctrl
,
3072 .stop_tx
= serial8250_stop_tx
,
3073 .start_tx
= serial8250_start_tx
,
3074 .throttle
= serial8250_throttle
,
3075 .unthrottle
= serial8250_unthrottle
,
3076 .stop_rx
= serial8250_stop_rx
,
3077 .enable_ms
= serial8250_enable_ms
,
3078 .break_ctl
= serial8250_break_ctl
,
3079 .startup
= serial8250_startup
,
3080 .shutdown
= serial8250_shutdown
,
3081 .set_termios
= serial8250_set_termios
,
3082 .set_ldisc
= serial8250_set_ldisc
,
3083 .pm
= serial8250_pm
,
3084 .type
= serial8250_type
,
3085 .release_port
= serial8250_release_port
,
3086 .request_port
= serial8250_request_port
,
3087 .config_port
= serial8250_config_port
,
3088 .verify_port
= serial8250_verify_port
,
3089 #ifdef CONFIG_CONSOLE_POLL
3090 .poll_get_char
= serial8250_get_poll_char
,
3091 .poll_put_char
= serial8250_put_poll_char
,
3095 void serial8250_init_port(struct uart_8250_port
*up
)
3097 struct uart_port
*port
= &up
->port
;
3099 spin_lock_init(&port
->lock
);
3100 port
->ops
= &serial8250_pops
;
3102 up
->cur_iotype
= 0xFF;
3104 EXPORT_SYMBOL_GPL(serial8250_init_port
);
3106 void serial8250_set_defaults(struct uart_8250_port
*up
)
3108 struct uart_port
*port
= &up
->port
;
3110 if (up
->port
.flags
& UPF_FIXED_TYPE
) {
3111 unsigned int type
= up
->port
.type
;
3113 if (!up
->port
.fifosize
)
3114 up
->port
.fifosize
= uart_config
[type
].fifo_size
;
3116 up
->tx_loadsz
= uart_config
[type
].tx_loadsz
;
3117 if (!up
->capabilities
)
3118 up
->capabilities
= uart_config
[type
].flags
;
3121 set_io_from_upio(port
);
3123 /* default dma handlers */
3125 if (!up
->dma
->tx_dma
)
3126 up
->dma
->tx_dma
= serial8250_tx_dma
;
3127 if (!up
->dma
->rx_dma
)
3128 up
->dma
->rx_dma
= serial8250_rx_dma
;
3131 EXPORT_SYMBOL_GPL(serial8250_set_defaults
);
3133 #ifdef CONFIG_SERIAL_8250_CONSOLE
3135 static void serial8250_console_putchar(struct uart_port
*port
, int ch
)
3137 struct uart_8250_port
*up
= up_to_u8250p(port
);
3139 wait_for_xmitr(up
, UART_LSR_THRE
);
3140 serial_port_out(port
, UART_TX
, ch
);
3144 * Restore serial console when h/w power-off detected
3146 static void serial8250_console_restore(struct uart_8250_port
*up
)
3148 struct uart_port
*port
= &up
->port
;
3149 struct ktermios termios
;
3150 unsigned int baud
, quot
, frac
= 0;
3152 termios
.c_cflag
= port
->cons
->cflag
;
3153 if (port
->state
->port
.tty
&& termios
.c_cflag
== 0)
3154 termios
.c_cflag
= port
->state
->port
.tty
->termios
.c_cflag
;
3156 baud
= serial8250_get_baud_rate(port
, &termios
, NULL
);
3157 quot
= serial8250_get_divisor(up
, baud
, &frac
);
3159 serial8250_set_divisor(port
, baud
, quot
, frac
);
3160 serial_port_out(port
, UART_LCR
, up
->lcr
);
3161 serial8250_out_MCR(up
, UART_MCR_DTR
| UART_MCR_RTS
);
3165 * Print a string to the serial port trying not to disturb
3166 * any possible real use of the port...
3168 * The console_lock must be held when we get here.
3170 void serial8250_console_write(struct uart_8250_port
*up
, const char *s
,
3173 struct uart_port
*port
= &up
->port
;
3174 unsigned long flags
;
3178 touch_nmi_watchdog();
3180 serial8250_rpm_get(up
);
3184 else if (oops_in_progress
)
3185 locked
= spin_trylock_irqsave(&port
->lock
, flags
);
3187 spin_lock_irqsave(&port
->lock
, flags
);
3190 * First save the IER then disable the interrupts
3192 ier
= serial_port_in(port
, UART_IER
);
3194 if (up
->capabilities
& UART_CAP_UUE
)
3195 serial_port_out(port
, UART_IER
, UART_IER_UUE
);
3197 serial_port_out(port
, UART_IER
, 0);
3199 /* check scratch reg to see if port powered off during system sleep */
3200 if (up
->canary
&& (up
->canary
!= serial_port_in(port
, UART_SCR
))) {
3201 serial8250_console_restore(up
);
3205 uart_console_write(port
, s
, count
, serial8250_console_putchar
);
3208 * Finally, wait for transmitter to become empty
3209 * and restore the IER
3211 wait_for_xmitr(up
, BOTH_EMPTY
);
3212 serial_port_out(port
, UART_IER
, ier
);
3215 * The receive handling will happen properly because the
3216 * receive ready bit will still be set; it is not cleared
3217 * on read. However, modem control will not, we must
3218 * call it if we have saved something in the saved flags
3219 * while processing with interrupts off.
3221 if (up
->msr_saved_flags
)
3222 serial8250_modem_status(up
);
3225 spin_unlock_irqrestore(&port
->lock
, flags
);
3226 serial8250_rpm_put(up
);
3229 static unsigned int probe_baud(struct uart_port
*port
)
3231 unsigned char lcr
, dll
, dlm
;
3234 lcr
= serial_port_in(port
, UART_LCR
);
3235 serial_port_out(port
, UART_LCR
, lcr
| UART_LCR_DLAB
);
3236 dll
= serial_port_in(port
, UART_DLL
);
3237 dlm
= serial_port_in(port
, UART_DLM
);
3238 serial_port_out(port
, UART_LCR
, lcr
);
3240 quot
= (dlm
<< 8) | dll
;
3241 return (port
->uartclk
/ 16) / quot
;
3244 int serial8250_console_setup(struct uart_port
*port
, char *options
, bool probe
)
3251 if (!port
->iobase
&& !port
->membase
)
3255 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
3257 baud
= probe_baud(port
);
3259 return uart_set_options(port
, port
->cons
, baud
, parity
, bits
, flow
);
3262 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3264 MODULE_LICENSE("GPL");