2 * Driver for AMBA serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
33 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
37 #include <linux/module.h>
38 #include <linux/ioport.h>
39 #include <linux/init.h>
40 #include <linux/console.h>
41 #include <linux/sysrq.h>
42 #include <linux/device.h>
43 #include <linux/tty.h>
44 #include <linux/tty_flip.h>
45 #include <linux/serial_core.h>
46 #include <linux/serial.h>
47 #include <linux/amba/bus.h>
48 #include <linux/amba/serial.h>
49 #include <linux/clk.h>
50 #include <linux/slab.h>
51 #include <linux/dmaengine.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/scatterlist.h>
54 #include <linux/delay.h>
55 #include <linux/types.h>
57 #include <linux/of_device.h>
58 #include <linux/pinctrl/consumer.h>
59 #include <linux/sizes.h>
61 #include <linux/acpi.h>
63 #include "amba-pl011.h"
67 #define SERIAL_AMBA_MAJOR 204
68 #define SERIAL_AMBA_MINOR 64
69 #define SERIAL_AMBA_NR UART_NR
71 #define AMBA_ISR_PASS_LIMIT 256
73 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
74 #define UART_DUMMY_DR_RX (1 << 16)
76 static u16 pl011_std_offsets
[REG_ARRAY_SIZE
] = {
77 [REG_DR
] = UART01x_DR
,
78 [REG_FR
] = UART01x_FR
,
79 [REG_LCRH_RX
] = UART011_LCRH
,
80 [REG_LCRH_TX
] = UART011_LCRH
,
81 [REG_IBRD
] = UART011_IBRD
,
82 [REG_FBRD
] = UART011_FBRD
,
83 [REG_CR
] = UART011_CR
,
84 [REG_IFLS
] = UART011_IFLS
,
85 [REG_IMSC
] = UART011_IMSC
,
86 [REG_RIS
] = UART011_RIS
,
87 [REG_MIS
] = UART011_MIS
,
88 [REG_ICR
] = UART011_ICR
,
89 [REG_DMACR
] = UART011_DMACR
,
92 /* There is by now at least one vendor with differing details, so handle it */
94 const u16
*reg_offset
;
104 bool cts_event_workaround
;
108 unsigned int (*get_fifosize
)(struct amba_device
*dev
);
111 static unsigned int get_fifosize_arm(struct amba_device
*dev
)
113 return amba_rev(dev
) < 3 ? 16 : 32;
116 static struct vendor_data vendor_arm
= {
117 .reg_offset
= pl011_std_offsets
,
118 .ifls
= UART011_IFLS_RX4_8
|UART011_IFLS_TX4_8
,
119 .fr_busy
= UART01x_FR_BUSY
,
120 .fr_dsr
= UART01x_FR_DSR
,
121 .fr_cts
= UART01x_FR_CTS
,
122 .fr_ri
= UART011_FR_RI
,
123 .oversampling
= false,
124 .dma_threshold
= false,
125 .cts_event_workaround
= false,
126 .always_enabled
= false,
127 .fixed_options
= false,
128 .get_fifosize
= get_fifosize_arm
,
131 static struct vendor_data vendor_sbsa
= {
132 .reg_offset
= pl011_std_offsets
,
133 .fr_busy
= UART01x_FR_BUSY
,
134 .fr_dsr
= UART01x_FR_DSR
,
135 .fr_cts
= UART01x_FR_CTS
,
136 .fr_ri
= UART011_FR_RI
,
138 .oversampling
= false,
139 .dma_threshold
= false,
140 .cts_event_workaround
= false,
141 .always_enabled
= true,
142 .fixed_options
= true,
145 #ifdef CONFIG_ACPI_SPCR_TABLE
146 static struct vendor_data vendor_qdt_qdf2400_e44
= {
147 .reg_offset
= pl011_std_offsets
,
148 .fr_busy
= UART011_FR_TXFE
,
149 .fr_dsr
= UART01x_FR_DSR
,
150 .fr_cts
= UART01x_FR_CTS
,
151 .fr_ri
= UART011_FR_RI
,
152 .inv_fr
= UART011_FR_TXFE
,
154 .oversampling
= false,
155 .dma_threshold
= false,
156 .cts_event_workaround
= false,
157 .always_enabled
= true,
158 .fixed_options
= true,
162 static u16 pl011_st_offsets
[REG_ARRAY_SIZE
] = {
163 [REG_DR
] = UART01x_DR
,
164 [REG_ST_DMAWM
] = ST_UART011_DMAWM
,
165 [REG_ST_TIMEOUT
] = ST_UART011_TIMEOUT
,
166 [REG_FR
] = UART01x_FR
,
167 [REG_LCRH_RX
] = ST_UART011_LCRH_RX
,
168 [REG_LCRH_TX
] = ST_UART011_LCRH_TX
,
169 [REG_IBRD
] = UART011_IBRD
,
170 [REG_FBRD
] = UART011_FBRD
,
171 [REG_CR
] = UART011_CR
,
172 [REG_IFLS
] = UART011_IFLS
,
173 [REG_IMSC
] = UART011_IMSC
,
174 [REG_RIS
] = UART011_RIS
,
175 [REG_MIS
] = UART011_MIS
,
176 [REG_ICR
] = UART011_ICR
,
177 [REG_DMACR
] = UART011_DMACR
,
178 [REG_ST_XFCR
] = ST_UART011_XFCR
,
179 [REG_ST_XON1
] = ST_UART011_XON1
,
180 [REG_ST_XON2
] = ST_UART011_XON2
,
181 [REG_ST_XOFF1
] = ST_UART011_XOFF1
,
182 [REG_ST_XOFF2
] = ST_UART011_XOFF2
,
183 [REG_ST_ITCR
] = ST_UART011_ITCR
,
184 [REG_ST_ITIP
] = ST_UART011_ITIP
,
185 [REG_ST_ABCR
] = ST_UART011_ABCR
,
186 [REG_ST_ABIMSC
] = ST_UART011_ABIMSC
,
189 static unsigned int get_fifosize_st(struct amba_device
*dev
)
194 static struct vendor_data vendor_st
= {
195 .reg_offset
= pl011_st_offsets
,
196 .ifls
= UART011_IFLS_RX_HALF
|UART011_IFLS_TX_HALF
,
197 .fr_busy
= UART01x_FR_BUSY
,
198 .fr_dsr
= UART01x_FR_DSR
,
199 .fr_cts
= UART01x_FR_CTS
,
200 .fr_ri
= UART011_FR_RI
,
201 .oversampling
= true,
202 .dma_threshold
= true,
203 .cts_event_workaround
= true,
204 .always_enabled
= false,
205 .fixed_options
= false,
206 .get_fifosize
= get_fifosize_st
,
209 static const u16 pl011_zte_offsets
[REG_ARRAY_SIZE
] = {
210 [REG_DR
] = ZX_UART011_DR
,
211 [REG_FR
] = ZX_UART011_FR
,
212 [REG_LCRH_RX
] = ZX_UART011_LCRH
,
213 [REG_LCRH_TX
] = ZX_UART011_LCRH
,
214 [REG_IBRD
] = ZX_UART011_IBRD
,
215 [REG_FBRD
] = ZX_UART011_FBRD
,
216 [REG_CR
] = ZX_UART011_CR
,
217 [REG_IFLS
] = ZX_UART011_IFLS
,
218 [REG_IMSC
] = ZX_UART011_IMSC
,
219 [REG_RIS
] = ZX_UART011_RIS
,
220 [REG_MIS
] = ZX_UART011_MIS
,
221 [REG_ICR
] = ZX_UART011_ICR
,
222 [REG_DMACR
] = ZX_UART011_DMACR
,
225 static unsigned int get_fifosize_zte(struct amba_device
*dev
)
230 static struct vendor_data vendor_zte
= {
231 .reg_offset
= pl011_zte_offsets
,
233 .ifls
= UART011_IFLS_RX4_8
|UART011_IFLS_TX4_8
,
234 .fr_busy
= ZX_UART01x_FR_BUSY
,
235 .fr_dsr
= ZX_UART01x_FR_DSR
,
236 .fr_cts
= ZX_UART01x_FR_CTS
,
237 .fr_ri
= ZX_UART011_FR_RI
,
238 .get_fifosize
= get_fifosize_zte
,
241 /* Deals with DMA transactions */
244 struct scatterlist sg
;
248 struct pl011_dmarx_data
{
249 struct dma_chan
*chan
;
250 struct completion complete
;
252 struct pl011_sgbuf sgbuf_a
;
253 struct pl011_sgbuf sgbuf_b
;
256 struct timer_list timer
;
257 unsigned int last_residue
;
258 unsigned long last_jiffies
;
260 unsigned int poll_rate
;
261 unsigned int poll_timeout
;
264 struct pl011_dmatx_data
{
265 struct dma_chan
*chan
;
266 struct scatterlist sg
;
272 * We wrap our port structure around the generic uart_port.
274 struct uart_amba_port
{
275 struct uart_port port
;
276 const u16
*reg_offset
;
278 const struct vendor_data
*vendor
;
279 unsigned int dmacr
; /* dma control reg */
280 unsigned int im
; /* interrupt mask */
281 unsigned int old_status
;
282 unsigned int fifosize
; /* vendor-specific */
283 unsigned int old_cr
; /* state during shutdown */
285 unsigned int fixed_baud
; /* vendor-set fixed baud rate */
287 #ifdef CONFIG_DMA_ENGINE
291 struct pl011_dmarx_data dmarx
;
292 struct pl011_dmatx_data dmatx
;
297 static unsigned int pl011_reg_to_offset(const struct uart_amba_port
*uap
,
300 return uap
->reg_offset
[reg
];
303 static unsigned int pl011_read(const struct uart_amba_port
*uap
,
306 void __iomem
*addr
= uap
->port
.membase
+ pl011_reg_to_offset(uap
, reg
);
308 return (uap
->port
.iotype
== UPIO_MEM32
) ?
309 readl_relaxed(addr
) : readw_relaxed(addr
);
312 static void pl011_write(unsigned int val
, const struct uart_amba_port
*uap
,
315 void __iomem
*addr
= uap
->port
.membase
+ pl011_reg_to_offset(uap
, reg
);
317 if (uap
->port
.iotype
== UPIO_MEM32
)
318 writel_relaxed(val
, addr
);
320 writew_relaxed(val
, addr
);
324 * Reads up to 256 characters from the FIFO or until it's empty and
325 * inserts them into the TTY layer. Returns the number of characters
326 * read from the FIFO.
328 static int pl011_fifo_to_tty(struct uart_amba_port
*uap
)
331 unsigned int ch
, flag
, max_count
= 256;
334 while (max_count
--) {
335 status
= pl011_read(uap
, REG_FR
);
336 if (status
& UART01x_FR_RXFE
)
339 /* Take chars from the FIFO and update status */
340 ch
= pl011_read(uap
, REG_DR
) | UART_DUMMY_DR_RX
;
342 uap
->port
.icount
.rx
++;
345 if (unlikely(ch
& UART_DR_ERROR
)) {
346 if (ch
& UART011_DR_BE
) {
347 ch
&= ~(UART011_DR_FE
| UART011_DR_PE
);
348 uap
->port
.icount
.brk
++;
349 if (uart_handle_break(&uap
->port
))
351 } else if (ch
& UART011_DR_PE
)
352 uap
->port
.icount
.parity
++;
353 else if (ch
& UART011_DR_FE
)
354 uap
->port
.icount
.frame
++;
355 if (ch
& UART011_DR_OE
)
356 uap
->port
.icount
.overrun
++;
358 ch
&= uap
->port
.read_status_mask
;
360 if (ch
& UART011_DR_BE
)
362 else if (ch
& UART011_DR_PE
)
364 else if (ch
& UART011_DR_FE
)
368 if (uart_handle_sysrq_char(&uap
->port
, ch
& 255))
371 uart_insert_char(&uap
->port
, ch
, UART011_DR_OE
, ch
, flag
);
379 * All the DMA operation mode stuff goes inside this ifdef.
380 * This assumes that you have a generic DMA device interface,
381 * no custom DMA interfaces are supported.
383 #ifdef CONFIG_DMA_ENGINE
385 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
387 static int pl011_sgbuf_init(struct dma_chan
*chan
, struct pl011_sgbuf
*sg
,
388 enum dma_data_direction dir
)
392 sg
->buf
= dma_alloc_coherent(chan
->device
->dev
,
393 PL011_DMA_BUFFER_SIZE
, &dma_addr
, GFP_KERNEL
);
397 sg_init_table(&sg
->sg
, 1);
398 sg_set_page(&sg
->sg
, phys_to_page(dma_addr
),
399 PL011_DMA_BUFFER_SIZE
, offset_in_page(dma_addr
));
400 sg_dma_address(&sg
->sg
) = dma_addr
;
401 sg_dma_len(&sg
->sg
) = PL011_DMA_BUFFER_SIZE
;
406 static void pl011_sgbuf_free(struct dma_chan
*chan
, struct pl011_sgbuf
*sg
,
407 enum dma_data_direction dir
)
410 dma_free_coherent(chan
->device
->dev
,
411 PL011_DMA_BUFFER_SIZE
, sg
->buf
,
412 sg_dma_address(&sg
->sg
));
416 static void pl011_dma_probe(struct uart_amba_port
*uap
)
418 /* DMA is the sole user of the platform data right now */
419 struct amba_pl011_data
*plat
= dev_get_platdata(uap
->port
.dev
);
420 struct device
*dev
= uap
->port
.dev
;
421 struct dma_slave_config tx_conf
= {
422 .dst_addr
= uap
->port
.mapbase
+
423 pl011_reg_to_offset(uap
, REG_DR
),
424 .dst_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
,
425 .direction
= DMA_MEM_TO_DEV
,
426 .dst_maxburst
= uap
->fifosize
>> 1,
429 struct dma_chan
*chan
;
432 uap
->dma_probed
= true;
433 chan
= dma_request_slave_channel_reason(dev
, "tx");
435 if (PTR_ERR(chan
) == -EPROBE_DEFER
) {
436 uap
->dma_probed
= false;
440 /* We need platform data */
441 if (!plat
|| !plat
->dma_filter
) {
442 dev_info(uap
->port
.dev
, "no DMA platform data\n");
446 /* Try to acquire a generic DMA engine slave TX channel */
448 dma_cap_set(DMA_SLAVE
, mask
);
450 chan
= dma_request_channel(mask
, plat
->dma_filter
,
453 dev_err(uap
->port
.dev
, "no TX DMA channel!\n");
458 dmaengine_slave_config(chan
, &tx_conf
);
459 uap
->dmatx
.chan
= chan
;
461 dev_info(uap
->port
.dev
, "DMA channel TX %s\n",
462 dma_chan_name(uap
->dmatx
.chan
));
464 /* Optionally make use of an RX channel as well */
465 chan
= dma_request_slave_channel(dev
, "rx");
467 if (!chan
&& plat
&& plat
->dma_rx_param
) {
468 chan
= dma_request_channel(mask
, plat
->dma_filter
, plat
->dma_rx_param
);
471 dev_err(uap
->port
.dev
, "no RX DMA channel!\n");
477 struct dma_slave_config rx_conf
= {
478 .src_addr
= uap
->port
.mapbase
+
479 pl011_reg_to_offset(uap
, REG_DR
),
480 .src_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
,
481 .direction
= DMA_DEV_TO_MEM
,
482 .src_maxburst
= uap
->fifosize
>> 2,
485 struct dma_slave_caps caps
;
488 * Some DMA controllers provide information on their capabilities.
489 * If the controller does, check for suitable residue processing
490 * otherwise assime all is well.
492 if (0 == dma_get_slave_caps(chan
, &caps
)) {
493 if (caps
.residue_granularity
==
494 DMA_RESIDUE_GRANULARITY_DESCRIPTOR
) {
495 dma_release_channel(chan
);
496 dev_info(uap
->port
.dev
,
497 "RX DMA disabled - no residue processing\n");
501 dmaengine_slave_config(chan
, &rx_conf
);
502 uap
->dmarx
.chan
= chan
;
504 uap
->dmarx
.auto_poll_rate
= false;
505 if (plat
&& plat
->dma_rx_poll_enable
) {
506 /* Set poll rate if specified. */
507 if (plat
->dma_rx_poll_rate
) {
508 uap
->dmarx
.auto_poll_rate
= false;
509 uap
->dmarx
.poll_rate
= plat
->dma_rx_poll_rate
;
512 * 100 ms defaults to poll rate if not
513 * specified. This will be adjusted with
514 * the baud rate at set_termios.
516 uap
->dmarx
.auto_poll_rate
= true;
517 uap
->dmarx
.poll_rate
= 100;
519 /* 3 secs defaults poll_timeout if not specified. */
520 if (plat
->dma_rx_poll_timeout
)
521 uap
->dmarx
.poll_timeout
=
522 plat
->dma_rx_poll_timeout
;
524 uap
->dmarx
.poll_timeout
= 3000;
525 } else if (!plat
&& dev
->of_node
) {
526 uap
->dmarx
.auto_poll_rate
= of_property_read_bool(
527 dev
->of_node
, "auto-poll");
528 if (uap
->dmarx
.auto_poll_rate
) {
531 if (0 == of_property_read_u32(dev
->of_node
,
533 uap
->dmarx
.poll_rate
= x
;
535 uap
->dmarx
.poll_rate
= 100;
536 if (0 == of_property_read_u32(dev
->of_node
,
537 "poll-timeout-ms", &x
))
538 uap
->dmarx
.poll_timeout
= x
;
540 uap
->dmarx
.poll_timeout
= 3000;
543 dev_info(uap
->port
.dev
, "DMA channel RX %s\n",
544 dma_chan_name(uap
->dmarx
.chan
));
548 static void pl011_dma_remove(struct uart_amba_port
*uap
)
551 dma_release_channel(uap
->dmatx
.chan
);
553 dma_release_channel(uap
->dmarx
.chan
);
556 /* Forward declare these for the refill routine */
557 static int pl011_dma_tx_refill(struct uart_amba_port
*uap
);
558 static void pl011_start_tx_pio(struct uart_amba_port
*uap
);
561 * The current DMA TX buffer has been sent.
562 * Try to queue up another DMA buffer.
564 static void pl011_dma_tx_callback(void *data
)
566 struct uart_amba_port
*uap
= data
;
567 struct pl011_dmatx_data
*dmatx
= &uap
->dmatx
;
571 spin_lock_irqsave(&uap
->port
.lock
, flags
);
572 if (uap
->dmatx
.queued
)
573 dma_unmap_sg(dmatx
->chan
->device
->dev
, &dmatx
->sg
, 1,
577 uap
->dmacr
= dmacr
& ~UART011_TXDMAE
;
578 pl011_write(uap
->dmacr
, uap
, REG_DMACR
);
581 * If TX DMA was disabled, it means that we've stopped the DMA for
582 * some reason (eg, XOFF received, or we want to send an X-char.)
584 * Note: we need to be careful here of a potential race between DMA
585 * and the rest of the driver - if the driver disables TX DMA while
586 * a TX buffer completing, we must update the tx queued status to
587 * get further refills (hence we check dmacr).
589 if (!(dmacr
& UART011_TXDMAE
) || uart_tx_stopped(&uap
->port
) ||
590 uart_circ_empty(&uap
->port
.state
->xmit
)) {
591 uap
->dmatx
.queued
= false;
592 spin_unlock_irqrestore(&uap
->port
.lock
, flags
);
596 if (pl011_dma_tx_refill(uap
) <= 0)
598 * We didn't queue a DMA buffer for some reason, but we
599 * have data pending to be sent. Re-enable the TX IRQ.
601 pl011_start_tx_pio(uap
);
603 spin_unlock_irqrestore(&uap
->port
.lock
, flags
);
607 * Try to refill the TX DMA buffer.
608 * Locking: called with port lock held and IRQs disabled.
610 * 1 if we queued up a TX DMA buffer.
611 * 0 if we didn't want to handle this by DMA
614 static int pl011_dma_tx_refill(struct uart_amba_port
*uap
)
616 struct pl011_dmatx_data
*dmatx
= &uap
->dmatx
;
617 struct dma_chan
*chan
= dmatx
->chan
;
618 struct dma_device
*dma_dev
= chan
->device
;
619 struct dma_async_tx_descriptor
*desc
;
620 struct circ_buf
*xmit
= &uap
->port
.state
->xmit
;
624 * Try to avoid the overhead involved in using DMA if the
625 * transaction fits in the first half of the FIFO, by using
626 * the standard interrupt handling. This ensures that we
627 * issue a uart_write_wakeup() at the appropriate time.
629 count
= uart_circ_chars_pending(xmit
);
630 if (count
< (uap
->fifosize
>> 1)) {
631 uap
->dmatx
.queued
= false;
636 * Bodge: don't send the last character by DMA, as this
637 * will prevent XON from notifying us to restart DMA.
641 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
642 if (count
> PL011_DMA_BUFFER_SIZE
)
643 count
= PL011_DMA_BUFFER_SIZE
;
645 if (xmit
->tail
< xmit
->head
)
646 memcpy(&dmatx
->buf
[0], &xmit
->buf
[xmit
->tail
], count
);
648 size_t first
= UART_XMIT_SIZE
- xmit
->tail
;
653 second
= count
- first
;
655 memcpy(&dmatx
->buf
[0], &xmit
->buf
[xmit
->tail
], first
);
657 memcpy(&dmatx
->buf
[first
], &xmit
->buf
[0], second
);
660 dmatx
->sg
.length
= count
;
662 if (dma_map_sg(dma_dev
->dev
, &dmatx
->sg
, 1, DMA_TO_DEVICE
) != 1) {
663 uap
->dmatx
.queued
= false;
664 dev_dbg(uap
->port
.dev
, "unable to map TX DMA\n");
668 desc
= dmaengine_prep_slave_sg(chan
, &dmatx
->sg
, 1, DMA_MEM_TO_DEV
,
669 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
671 dma_unmap_sg(dma_dev
->dev
, &dmatx
->sg
, 1, DMA_TO_DEVICE
);
672 uap
->dmatx
.queued
= false;
674 * If DMA cannot be used right now, we complete this
675 * transaction via IRQ and let the TTY layer retry.
677 dev_dbg(uap
->port
.dev
, "TX DMA busy\n");
681 /* Some data to go along to the callback */
682 desc
->callback
= pl011_dma_tx_callback
;
683 desc
->callback_param
= uap
;
685 /* All errors should happen at prepare time */
686 dmaengine_submit(desc
);
688 /* Fire the DMA transaction */
689 dma_dev
->device_issue_pending(chan
);
691 uap
->dmacr
|= UART011_TXDMAE
;
692 pl011_write(uap
->dmacr
, uap
, REG_DMACR
);
693 uap
->dmatx
.queued
= true;
696 * Now we know that DMA will fire, so advance the ring buffer
697 * with the stuff we just dispatched.
699 xmit
->tail
= (xmit
->tail
+ count
) & (UART_XMIT_SIZE
- 1);
700 uap
->port
.icount
.tx
+= count
;
702 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
703 uart_write_wakeup(&uap
->port
);
709 * We received a transmit interrupt without a pending X-char but with
710 * pending characters.
711 * Locking: called with port lock held and IRQs disabled.
713 * false if we want to use PIO to transmit
714 * true if we queued a DMA buffer
716 static bool pl011_dma_tx_irq(struct uart_amba_port
*uap
)
718 if (!uap
->using_tx_dma
)
722 * If we already have a TX buffer queued, but received a
723 * TX interrupt, it will be because we've just sent an X-char.
724 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
726 if (uap
->dmatx
.queued
) {
727 uap
->dmacr
|= UART011_TXDMAE
;
728 pl011_write(uap
->dmacr
, uap
, REG_DMACR
);
729 uap
->im
&= ~UART011_TXIM
;
730 pl011_write(uap
->im
, uap
, REG_IMSC
);
735 * We don't have a TX buffer queued, so try to queue one.
736 * If we successfully queued a buffer, mask the TX IRQ.
738 if (pl011_dma_tx_refill(uap
) > 0) {
739 uap
->im
&= ~UART011_TXIM
;
740 pl011_write(uap
->im
, uap
, REG_IMSC
);
747 * Stop the DMA transmit (eg, due to received XOFF).
748 * Locking: called with port lock held and IRQs disabled.
750 static inline void pl011_dma_tx_stop(struct uart_amba_port
*uap
)
752 if (uap
->dmatx
.queued
) {
753 uap
->dmacr
&= ~UART011_TXDMAE
;
754 pl011_write(uap
->dmacr
, uap
, REG_DMACR
);
759 * Try to start a DMA transmit, or in the case of an XON/OFF
760 * character queued for send, try to get that character out ASAP.
761 * Locking: called with port lock held and IRQs disabled.
763 * false if we want the TX IRQ to be enabled
764 * true if we have a buffer queued
766 static inline bool pl011_dma_tx_start(struct uart_amba_port
*uap
)
770 if (!uap
->using_tx_dma
)
773 if (!uap
->port
.x_char
) {
774 /* no X-char, try to push chars out in DMA mode */
777 if (!uap
->dmatx
.queued
) {
778 if (pl011_dma_tx_refill(uap
) > 0) {
779 uap
->im
&= ~UART011_TXIM
;
780 pl011_write(uap
->im
, uap
, REG_IMSC
);
783 } else if (!(uap
->dmacr
& UART011_TXDMAE
)) {
784 uap
->dmacr
|= UART011_TXDMAE
;
785 pl011_write(uap
->dmacr
, uap
, REG_DMACR
);
791 * We have an X-char to send. Disable DMA to prevent it loading
792 * the TX fifo, and then see if we can stuff it into the FIFO.
795 uap
->dmacr
&= ~UART011_TXDMAE
;
796 pl011_write(uap
->dmacr
, uap
, REG_DMACR
);
798 if (pl011_read(uap
, REG_FR
) & UART01x_FR_TXFF
) {
800 * No space in the FIFO, so enable the transmit interrupt
801 * so we know when there is space. Note that once we've
802 * loaded the character, we should just re-enable DMA.
807 pl011_write(uap
->port
.x_char
, uap
, REG_DR
);
808 uap
->port
.icount
.tx
++;
809 uap
->port
.x_char
= 0;
811 /* Success - restore the DMA state */
813 pl011_write(dmacr
, uap
, REG_DMACR
);
819 * Flush the transmit buffer.
820 * Locking: called with port lock held and IRQs disabled.
822 static void pl011_dma_flush_buffer(struct uart_port
*port
)
823 __releases(&uap
->port
.lock
)
824 __acquires(&uap
->port
.lock
)
826 struct uart_amba_port
*uap
=
827 container_of(port
, struct uart_amba_port
, port
);
829 if (!uap
->using_tx_dma
)
832 /* Avoid deadlock with the DMA engine callback */
833 spin_unlock(&uap
->port
.lock
);
834 dmaengine_terminate_all(uap
->dmatx
.chan
);
835 spin_lock(&uap
->port
.lock
);
836 if (uap
->dmatx
.queued
) {
837 dma_unmap_sg(uap
->dmatx
.chan
->device
->dev
, &uap
->dmatx
.sg
, 1,
839 uap
->dmatx
.queued
= false;
840 uap
->dmacr
&= ~UART011_TXDMAE
;
841 pl011_write(uap
->dmacr
, uap
, REG_DMACR
);
845 static void pl011_dma_rx_callback(void *data
);
847 static int pl011_dma_rx_trigger_dma(struct uart_amba_port
*uap
)
849 struct dma_chan
*rxchan
= uap
->dmarx
.chan
;
850 struct pl011_dmarx_data
*dmarx
= &uap
->dmarx
;
851 struct dma_async_tx_descriptor
*desc
;
852 struct pl011_sgbuf
*sgbuf
;
857 /* Start the RX DMA job */
858 sgbuf
= uap
->dmarx
.use_buf_b
?
859 &uap
->dmarx
.sgbuf_b
: &uap
->dmarx
.sgbuf_a
;
860 desc
= dmaengine_prep_slave_sg(rxchan
, &sgbuf
->sg
, 1,
862 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
864 * If the DMA engine is busy and cannot prepare a
865 * channel, no big deal, the driver will fall back
866 * to interrupt mode as a result of this error code.
869 uap
->dmarx
.running
= false;
870 dmaengine_terminate_all(rxchan
);
874 /* Some data to go along to the callback */
875 desc
->callback
= pl011_dma_rx_callback
;
876 desc
->callback_param
= uap
;
877 dmarx
->cookie
= dmaengine_submit(desc
);
878 dma_async_issue_pending(rxchan
);
880 uap
->dmacr
|= UART011_RXDMAE
;
881 pl011_write(uap
->dmacr
, uap
, REG_DMACR
);
882 uap
->dmarx
.running
= true;
884 uap
->im
&= ~UART011_RXIM
;
885 pl011_write(uap
->im
, uap
, REG_IMSC
);
891 * This is called when either the DMA job is complete, or
892 * the FIFO timeout interrupt occurred. This must be called
893 * with the port spinlock uap->port.lock held.
895 static void pl011_dma_rx_chars(struct uart_amba_port
*uap
,
896 u32 pending
, bool use_buf_b
,
899 struct tty_port
*port
= &uap
->port
.state
->port
;
900 struct pl011_sgbuf
*sgbuf
= use_buf_b
?
901 &uap
->dmarx
.sgbuf_b
: &uap
->dmarx
.sgbuf_a
;
903 u32 fifotaken
= 0; /* only used for vdbg() */
905 struct pl011_dmarx_data
*dmarx
= &uap
->dmarx
;
908 if (uap
->dmarx
.poll_rate
) {
909 /* The data can be taken by polling */
910 dmataken
= sgbuf
->sg
.length
- dmarx
->last_residue
;
911 /* Recalculate the pending size */
912 if (pending
>= dmataken
)
916 /* Pick the remain data from the DMA */
920 * First take all chars in the DMA pipe, then look in the FIFO.
921 * Note that tty_insert_flip_buf() tries to take as many chars
924 dma_count
= tty_insert_flip_string(port
, sgbuf
->buf
+ dmataken
,
927 uap
->port
.icount
.rx
+= dma_count
;
928 if (dma_count
< pending
)
929 dev_warn(uap
->port
.dev
,
930 "couldn't insert all characters (TTY is full?)\n");
933 /* Reset the last_residue for Rx DMA poll */
934 if (uap
->dmarx
.poll_rate
)
935 dmarx
->last_residue
= sgbuf
->sg
.length
;
938 * Only continue with trying to read the FIFO if all DMA chars have
941 if (dma_count
== pending
&& readfifo
) {
942 /* Clear any error flags */
943 pl011_write(UART011_OEIS
| UART011_BEIS
| UART011_PEIS
|
944 UART011_FEIS
, uap
, REG_ICR
);
947 * If we read all the DMA'd characters, and we had an
948 * incomplete buffer, that could be due to an rx error, or
949 * maybe we just timed out. Read any pending chars and check
952 * Error conditions will only occur in the FIFO, these will
953 * trigger an immediate interrupt and stop the DMA job, so we
954 * will always find the error in the FIFO, never in the DMA
957 fifotaken
= pl011_fifo_to_tty(uap
);
960 spin_unlock(&uap
->port
.lock
);
961 dev_vdbg(uap
->port
.dev
,
962 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
963 dma_count
, fifotaken
);
964 tty_flip_buffer_push(port
);
965 spin_lock(&uap
->port
.lock
);
968 static void pl011_dma_rx_irq(struct uart_amba_port
*uap
)
970 struct pl011_dmarx_data
*dmarx
= &uap
->dmarx
;
971 struct dma_chan
*rxchan
= dmarx
->chan
;
972 struct pl011_sgbuf
*sgbuf
= dmarx
->use_buf_b
?
973 &dmarx
->sgbuf_b
: &dmarx
->sgbuf_a
;
975 struct dma_tx_state state
;
976 enum dma_status dmastat
;
979 * Pause the transfer so we can trust the current counter,
980 * do this before we pause the PL011 block, else we may
983 if (dmaengine_pause(rxchan
))
984 dev_err(uap
->port
.dev
, "unable to pause DMA transfer\n");
985 dmastat
= rxchan
->device
->device_tx_status(rxchan
,
986 dmarx
->cookie
, &state
);
987 if (dmastat
!= DMA_PAUSED
)
988 dev_err(uap
->port
.dev
, "unable to pause DMA transfer\n");
990 /* Disable RX DMA - incoming data will wait in the FIFO */
991 uap
->dmacr
&= ~UART011_RXDMAE
;
992 pl011_write(uap
->dmacr
, uap
, REG_DMACR
);
993 uap
->dmarx
.running
= false;
995 pending
= sgbuf
->sg
.length
- state
.residue
;
996 BUG_ON(pending
> PL011_DMA_BUFFER_SIZE
);
997 /* Then we terminate the transfer - we now know our residue */
998 dmaengine_terminate_all(rxchan
);
1001 * This will take the chars we have so far and insert
1002 * into the framework.
1004 pl011_dma_rx_chars(uap
, pending
, dmarx
->use_buf_b
, true);
1006 /* Switch buffer & re-trigger DMA job */
1007 dmarx
->use_buf_b
= !dmarx
->use_buf_b
;
1008 if (pl011_dma_rx_trigger_dma(uap
)) {
1009 dev_dbg(uap
->port
.dev
, "could not retrigger RX DMA job "
1010 "fall back to interrupt mode\n");
1011 uap
->im
|= UART011_RXIM
;
1012 pl011_write(uap
->im
, uap
, REG_IMSC
);
1016 static void pl011_dma_rx_callback(void *data
)
1018 struct uart_amba_port
*uap
= data
;
1019 struct pl011_dmarx_data
*dmarx
= &uap
->dmarx
;
1020 struct dma_chan
*rxchan
= dmarx
->chan
;
1021 bool lastbuf
= dmarx
->use_buf_b
;
1022 struct pl011_sgbuf
*sgbuf
= dmarx
->use_buf_b
?
1023 &dmarx
->sgbuf_b
: &dmarx
->sgbuf_a
;
1025 struct dma_tx_state state
;
1029 * This completion interrupt occurs typically when the
1030 * RX buffer is totally stuffed but no timeout has yet
1031 * occurred. When that happens, we just want the RX
1032 * routine to flush out the secondary DMA buffer while
1033 * we immediately trigger the next DMA job.
1035 spin_lock_irq(&uap
->port
.lock
);
1037 * Rx data can be taken by the UART interrupts during
1038 * the DMA irq handler. So we check the residue here.
1040 rxchan
->device
->device_tx_status(rxchan
, dmarx
->cookie
, &state
);
1041 pending
= sgbuf
->sg
.length
- state
.residue
;
1042 BUG_ON(pending
> PL011_DMA_BUFFER_SIZE
);
1043 /* Then we terminate the transfer - we now know our residue */
1044 dmaengine_terminate_all(rxchan
);
1046 uap
->dmarx
.running
= false;
1047 dmarx
->use_buf_b
= !lastbuf
;
1048 ret
= pl011_dma_rx_trigger_dma(uap
);
1050 pl011_dma_rx_chars(uap
, pending
, lastbuf
, false);
1051 spin_unlock_irq(&uap
->port
.lock
);
1053 * Do this check after we picked the DMA chars so we don't
1054 * get some IRQ immediately from RX.
1057 dev_dbg(uap
->port
.dev
, "could not retrigger RX DMA job "
1058 "fall back to interrupt mode\n");
1059 uap
->im
|= UART011_RXIM
;
1060 pl011_write(uap
->im
, uap
, REG_IMSC
);
1065 * Stop accepting received characters, when we're shutting down or
1066 * suspending this port.
1067 * Locking: called with port lock held and IRQs disabled.
1069 static inline void pl011_dma_rx_stop(struct uart_amba_port
*uap
)
1071 /* FIXME. Just disable the DMA enable */
1072 uap
->dmacr
&= ~UART011_RXDMAE
;
1073 pl011_write(uap
->dmacr
, uap
, REG_DMACR
);
1077 * Timer handler for Rx DMA polling.
1078 * Every polling, It checks the residue in the dma buffer and transfer
1079 * data to the tty. Also, last_residue is updated for the next polling.
1081 static void pl011_dma_rx_poll(unsigned long args
)
1083 struct uart_amba_port
*uap
= (struct uart_amba_port
*)args
;
1084 struct tty_port
*port
= &uap
->port
.state
->port
;
1085 struct pl011_dmarx_data
*dmarx
= &uap
->dmarx
;
1086 struct dma_chan
*rxchan
= uap
->dmarx
.chan
;
1087 unsigned long flags
= 0;
1088 unsigned int dmataken
= 0;
1089 unsigned int size
= 0;
1090 struct pl011_sgbuf
*sgbuf
;
1092 struct dma_tx_state state
;
1094 sgbuf
= dmarx
->use_buf_b
? &uap
->dmarx
.sgbuf_b
: &uap
->dmarx
.sgbuf_a
;
1095 rxchan
->device
->device_tx_status(rxchan
, dmarx
->cookie
, &state
);
1096 if (likely(state
.residue
< dmarx
->last_residue
)) {
1097 dmataken
= sgbuf
->sg
.length
- dmarx
->last_residue
;
1098 size
= dmarx
->last_residue
- state
.residue
;
1099 dma_count
= tty_insert_flip_string(port
, sgbuf
->buf
+ dmataken
,
1101 if (dma_count
== size
)
1102 dmarx
->last_residue
= state
.residue
;
1103 dmarx
->last_jiffies
= jiffies
;
1105 tty_flip_buffer_push(port
);
1108 * If no data is received in poll_timeout, the driver will fall back
1109 * to interrupt mode. We will retrigger DMA at the first interrupt.
1111 if (jiffies_to_msecs(jiffies
- dmarx
->last_jiffies
)
1112 > uap
->dmarx
.poll_timeout
) {
1114 spin_lock_irqsave(&uap
->port
.lock
, flags
);
1115 pl011_dma_rx_stop(uap
);
1116 uap
->im
|= UART011_RXIM
;
1117 pl011_write(uap
->im
, uap
, REG_IMSC
);
1118 spin_unlock_irqrestore(&uap
->port
.lock
, flags
);
1120 uap
->dmarx
.running
= false;
1121 dmaengine_terminate_all(rxchan
);
1122 del_timer(&uap
->dmarx
.timer
);
1124 mod_timer(&uap
->dmarx
.timer
,
1125 jiffies
+ msecs_to_jiffies(uap
->dmarx
.poll_rate
));
1129 static void pl011_dma_startup(struct uart_amba_port
*uap
)
1133 if (!uap
->dma_probed
)
1134 pl011_dma_probe(uap
);
1136 if (!uap
->dmatx
.chan
)
1139 uap
->dmatx
.buf
= kmalloc(PL011_DMA_BUFFER_SIZE
, GFP_KERNEL
| __GFP_DMA
);
1140 if (!uap
->dmatx
.buf
) {
1141 dev_err(uap
->port
.dev
, "no memory for DMA TX buffer\n");
1142 uap
->port
.fifosize
= uap
->fifosize
;
1146 sg_init_one(&uap
->dmatx
.sg
, uap
->dmatx
.buf
, PL011_DMA_BUFFER_SIZE
);
1148 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1149 uap
->port
.fifosize
= PL011_DMA_BUFFER_SIZE
;
1150 uap
->using_tx_dma
= true;
1152 if (!uap
->dmarx
.chan
)
1155 /* Allocate and map DMA RX buffers */
1156 ret
= pl011_sgbuf_init(uap
->dmarx
.chan
, &uap
->dmarx
.sgbuf_a
,
1159 dev_err(uap
->port
.dev
, "failed to init DMA %s: %d\n",
1160 "RX buffer A", ret
);
1164 ret
= pl011_sgbuf_init(uap
->dmarx
.chan
, &uap
->dmarx
.sgbuf_b
,
1167 dev_err(uap
->port
.dev
, "failed to init DMA %s: %d\n",
1168 "RX buffer B", ret
);
1169 pl011_sgbuf_free(uap
->dmarx
.chan
, &uap
->dmarx
.sgbuf_a
,
1174 uap
->using_rx_dma
= true;
1177 /* Turn on DMA error (RX/TX will be enabled on demand) */
1178 uap
->dmacr
|= UART011_DMAONERR
;
1179 pl011_write(uap
->dmacr
, uap
, REG_DMACR
);
1182 * ST Micro variants has some specific dma burst threshold
1183 * compensation. Set this to 16 bytes, so burst will only
1184 * be issued above/below 16 bytes.
1186 if (uap
->vendor
->dma_threshold
)
1187 pl011_write(ST_UART011_DMAWM_RX_16
| ST_UART011_DMAWM_TX_16
,
1190 if (uap
->using_rx_dma
) {
1191 if (pl011_dma_rx_trigger_dma(uap
))
1192 dev_dbg(uap
->port
.dev
, "could not trigger initial "
1193 "RX DMA job, fall back to interrupt mode\n");
1194 if (uap
->dmarx
.poll_rate
) {
1195 init_timer(&(uap
->dmarx
.timer
));
1196 uap
->dmarx
.timer
.function
= pl011_dma_rx_poll
;
1197 uap
->dmarx
.timer
.data
= (unsigned long)uap
;
1198 mod_timer(&uap
->dmarx
.timer
,
1200 msecs_to_jiffies(uap
->dmarx
.poll_rate
));
1201 uap
->dmarx
.last_residue
= PL011_DMA_BUFFER_SIZE
;
1202 uap
->dmarx
.last_jiffies
= jiffies
;
1207 static void pl011_dma_shutdown(struct uart_amba_port
*uap
)
1209 if (!(uap
->using_tx_dma
|| uap
->using_rx_dma
))
1212 /* Disable RX and TX DMA */
1213 while (pl011_read(uap
, REG_FR
) & uap
->vendor
->fr_busy
)
1216 spin_lock_irq(&uap
->port
.lock
);
1217 uap
->dmacr
&= ~(UART011_DMAONERR
| UART011_RXDMAE
| UART011_TXDMAE
);
1218 pl011_write(uap
->dmacr
, uap
, REG_DMACR
);
1219 spin_unlock_irq(&uap
->port
.lock
);
1221 if (uap
->using_tx_dma
) {
1222 /* In theory, this should already be done by pl011_dma_flush_buffer */
1223 dmaengine_terminate_all(uap
->dmatx
.chan
);
1224 if (uap
->dmatx
.queued
) {
1225 dma_unmap_sg(uap
->dmatx
.chan
->device
->dev
, &uap
->dmatx
.sg
, 1,
1227 uap
->dmatx
.queued
= false;
1230 kfree(uap
->dmatx
.buf
);
1231 uap
->using_tx_dma
= false;
1234 if (uap
->using_rx_dma
) {
1235 dmaengine_terminate_all(uap
->dmarx
.chan
);
1236 /* Clean up the RX DMA */
1237 pl011_sgbuf_free(uap
->dmarx
.chan
, &uap
->dmarx
.sgbuf_a
, DMA_FROM_DEVICE
);
1238 pl011_sgbuf_free(uap
->dmarx
.chan
, &uap
->dmarx
.sgbuf_b
, DMA_FROM_DEVICE
);
1239 if (uap
->dmarx
.poll_rate
)
1240 del_timer_sync(&uap
->dmarx
.timer
);
1241 uap
->using_rx_dma
= false;
1245 static inline bool pl011_dma_rx_available(struct uart_amba_port
*uap
)
1247 return uap
->using_rx_dma
;
1250 static inline bool pl011_dma_rx_running(struct uart_amba_port
*uap
)
1252 return uap
->using_rx_dma
&& uap
->dmarx
.running
;
1256 /* Blank functions if the DMA engine is not available */
1257 static inline void pl011_dma_probe(struct uart_amba_port
*uap
)
1261 static inline void pl011_dma_remove(struct uart_amba_port
*uap
)
1265 static inline void pl011_dma_startup(struct uart_amba_port
*uap
)
1269 static inline void pl011_dma_shutdown(struct uart_amba_port
*uap
)
1273 static inline bool pl011_dma_tx_irq(struct uart_amba_port
*uap
)
1278 static inline void pl011_dma_tx_stop(struct uart_amba_port
*uap
)
1282 static inline bool pl011_dma_tx_start(struct uart_amba_port
*uap
)
1287 static inline void pl011_dma_rx_irq(struct uart_amba_port
*uap
)
1291 static inline void pl011_dma_rx_stop(struct uart_amba_port
*uap
)
1295 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port
*uap
)
1300 static inline bool pl011_dma_rx_available(struct uart_amba_port
*uap
)
1305 static inline bool pl011_dma_rx_running(struct uart_amba_port
*uap
)
1310 #define pl011_dma_flush_buffer NULL
1313 static void pl011_stop_tx(struct uart_port
*port
)
1315 struct uart_amba_port
*uap
=
1316 container_of(port
, struct uart_amba_port
, port
);
1318 uap
->im
&= ~UART011_TXIM
;
1319 pl011_write(uap
->im
, uap
, REG_IMSC
);
1320 pl011_dma_tx_stop(uap
);
1323 static bool pl011_tx_chars(struct uart_amba_port
*uap
, bool from_irq
);
1325 /* Start TX with programmed I/O only (no DMA) */
1326 static void pl011_start_tx_pio(struct uart_amba_port
*uap
)
1328 if (pl011_tx_chars(uap
, false)) {
1329 uap
->im
|= UART011_TXIM
;
1330 pl011_write(uap
->im
, uap
, REG_IMSC
);
1334 static void pl011_start_tx(struct uart_port
*port
)
1336 struct uart_amba_port
*uap
=
1337 container_of(port
, struct uart_amba_port
, port
);
1339 if (!pl011_dma_tx_start(uap
))
1340 pl011_start_tx_pio(uap
);
1343 static void pl011_stop_rx(struct uart_port
*port
)
1345 struct uart_amba_port
*uap
=
1346 container_of(port
, struct uart_amba_port
, port
);
1348 uap
->im
&= ~(UART011_RXIM
|UART011_RTIM
|UART011_FEIM
|
1349 UART011_PEIM
|UART011_BEIM
|UART011_OEIM
);
1350 pl011_write(uap
->im
, uap
, REG_IMSC
);
1352 pl011_dma_rx_stop(uap
);
1355 static void pl011_enable_ms(struct uart_port
*port
)
1357 struct uart_amba_port
*uap
=
1358 container_of(port
, struct uart_amba_port
, port
);
1360 uap
->im
|= UART011_RIMIM
|UART011_CTSMIM
|UART011_DCDMIM
|UART011_DSRMIM
;
1361 pl011_write(uap
->im
, uap
, REG_IMSC
);
1364 static void pl011_rx_chars(struct uart_amba_port
*uap
)
1365 __releases(&uap
->port
.lock
)
1366 __acquires(&uap
->port
.lock
)
1368 pl011_fifo_to_tty(uap
);
1370 spin_unlock(&uap
->port
.lock
);
1371 tty_flip_buffer_push(&uap
->port
.state
->port
);
1373 * If we were temporarily out of DMA mode for a while,
1374 * attempt to switch back to DMA mode again.
1376 if (pl011_dma_rx_available(uap
)) {
1377 if (pl011_dma_rx_trigger_dma(uap
)) {
1378 dev_dbg(uap
->port
.dev
, "could not trigger RX DMA job "
1379 "fall back to interrupt mode again\n");
1380 uap
->im
|= UART011_RXIM
;
1381 pl011_write(uap
->im
, uap
, REG_IMSC
);
1383 #ifdef CONFIG_DMA_ENGINE
1384 /* Start Rx DMA poll */
1385 if (uap
->dmarx
.poll_rate
) {
1386 uap
->dmarx
.last_jiffies
= jiffies
;
1387 uap
->dmarx
.last_residue
= PL011_DMA_BUFFER_SIZE
;
1388 mod_timer(&uap
->dmarx
.timer
,
1390 msecs_to_jiffies(uap
->dmarx
.poll_rate
));
1395 spin_lock(&uap
->port
.lock
);
1398 static bool pl011_tx_char(struct uart_amba_port
*uap
, unsigned char c
,
1401 if (unlikely(!from_irq
) &&
1402 pl011_read(uap
, REG_FR
) & UART01x_FR_TXFF
)
1403 return false; /* unable to transmit character */
1405 pl011_write(c
, uap
, REG_DR
);
1406 uap
->port
.icount
.tx
++;
1411 /* Returns true if tx interrupts have to be (kept) enabled */
1412 static bool pl011_tx_chars(struct uart_amba_port
*uap
, bool from_irq
)
1414 struct circ_buf
*xmit
= &uap
->port
.state
->xmit
;
1415 int count
= uap
->fifosize
>> 1;
1417 if (uap
->port
.x_char
) {
1418 if (!pl011_tx_char(uap
, uap
->port
.x_char
, from_irq
))
1420 uap
->port
.x_char
= 0;
1423 if (uart_circ_empty(xmit
) || uart_tx_stopped(&uap
->port
)) {
1424 pl011_stop_tx(&uap
->port
);
1428 /* If we are using DMA mode, try to send some characters. */
1429 if (pl011_dma_tx_irq(uap
))
1433 if (likely(from_irq
) && count
-- == 0)
1436 if (!pl011_tx_char(uap
, xmit
->buf
[xmit
->tail
], from_irq
))
1439 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
1440 } while (!uart_circ_empty(xmit
));
1442 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
1443 uart_write_wakeup(&uap
->port
);
1445 if (uart_circ_empty(xmit
)) {
1446 pl011_stop_tx(&uap
->port
);
1452 static void pl011_modem_status(struct uart_amba_port
*uap
)
1454 unsigned int status
, delta
;
1456 status
= pl011_read(uap
, REG_FR
) & UART01x_FR_MODEM_ANY
;
1458 delta
= status
^ uap
->old_status
;
1459 uap
->old_status
= status
;
1464 if (delta
& UART01x_FR_DCD
)
1465 uart_handle_dcd_change(&uap
->port
, status
& UART01x_FR_DCD
);
1467 if (delta
& uap
->vendor
->fr_dsr
)
1468 uap
->port
.icount
.dsr
++;
1470 if (delta
& uap
->vendor
->fr_cts
)
1471 uart_handle_cts_change(&uap
->port
,
1472 status
& uap
->vendor
->fr_cts
);
1474 wake_up_interruptible(&uap
->port
.state
->port
.delta_msr_wait
);
1477 static void check_apply_cts_event_workaround(struct uart_amba_port
*uap
)
1479 unsigned int dummy_read
;
1481 if (!uap
->vendor
->cts_event_workaround
)
1484 /* workaround to make sure that all bits are unlocked.. */
1485 pl011_write(0x00, uap
, REG_ICR
);
1488 * WA: introduce 26ns(1 uart clk) delay before W1C;
1489 * single apb access will incur 2 pclk(133.12Mhz) delay,
1490 * so add 2 dummy reads
1492 dummy_read
= pl011_read(uap
, REG_ICR
);
1493 dummy_read
= pl011_read(uap
, REG_ICR
);
1496 static irqreturn_t
pl011_int(int irq
, void *dev_id
)
1498 struct uart_amba_port
*uap
= dev_id
;
1499 unsigned long flags
;
1500 unsigned int status
, pass_counter
= AMBA_ISR_PASS_LIMIT
;
1504 spin_lock_irqsave(&uap
->port
.lock
, flags
);
1505 imsc
= pl011_read(uap
, REG_IMSC
);
1506 status
= pl011_read(uap
, REG_RIS
) & imsc
;
1509 check_apply_cts_event_workaround(uap
);
1511 pl011_write(status
& ~(UART011_TXIS
|UART011_RTIS
|
1515 if (status
& (UART011_RTIS
|UART011_RXIS
)) {
1516 if (pl011_dma_rx_running(uap
))
1517 pl011_dma_rx_irq(uap
);
1519 pl011_rx_chars(uap
);
1521 if (status
& (UART011_DSRMIS
|UART011_DCDMIS
|
1522 UART011_CTSMIS
|UART011_RIMIS
))
1523 pl011_modem_status(uap
);
1524 if (status
& UART011_TXIS
)
1525 pl011_tx_chars(uap
, true);
1527 if (pass_counter
-- == 0)
1530 status
= pl011_read(uap
, REG_RIS
) & imsc
;
1531 } while (status
!= 0);
1535 spin_unlock_irqrestore(&uap
->port
.lock
, flags
);
1537 return IRQ_RETVAL(handled
);
1540 static unsigned int pl011_tx_empty(struct uart_port
*port
)
1542 struct uart_amba_port
*uap
=
1543 container_of(port
, struct uart_amba_port
, port
);
1545 /* Allow feature register bits to be inverted to work around errata */
1546 unsigned int status
= pl011_read(uap
, REG_FR
) ^ uap
->vendor
->inv_fr
;
1548 return status
& (uap
->vendor
->fr_busy
| UART01x_FR_TXFF
) ?
1552 static unsigned int pl011_get_mctrl(struct uart_port
*port
)
1554 struct uart_amba_port
*uap
=
1555 container_of(port
, struct uart_amba_port
, port
);
1556 unsigned int result
= 0;
1557 unsigned int status
= pl011_read(uap
, REG_FR
);
1559 #define TIOCMBIT(uartbit, tiocmbit) \
1560 if (status & uartbit) \
1563 TIOCMBIT(UART01x_FR_DCD
, TIOCM_CAR
);
1564 TIOCMBIT(uap
->vendor
->fr_dsr
, TIOCM_DSR
);
1565 TIOCMBIT(uap
->vendor
->fr_cts
, TIOCM_CTS
);
1566 TIOCMBIT(uap
->vendor
->fr_ri
, TIOCM_RNG
);
1571 static void pl011_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
1573 struct uart_amba_port
*uap
=
1574 container_of(port
, struct uart_amba_port
, port
);
1577 cr
= pl011_read(uap
, REG_CR
);
1579 #define TIOCMBIT(tiocmbit, uartbit) \
1580 if (mctrl & tiocmbit) \
1585 TIOCMBIT(TIOCM_RTS
, UART011_CR_RTS
);
1586 TIOCMBIT(TIOCM_DTR
, UART011_CR_DTR
);
1587 TIOCMBIT(TIOCM_OUT1
, UART011_CR_OUT1
);
1588 TIOCMBIT(TIOCM_OUT2
, UART011_CR_OUT2
);
1589 TIOCMBIT(TIOCM_LOOP
, UART011_CR_LBE
);
1592 /* We need to disable auto-RTS if we want to turn RTS off */
1593 TIOCMBIT(TIOCM_RTS
, UART011_CR_RTSEN
);
1597 pl011_write(cr
, uap
, REG_CR
);
1600 static void pl011_break_ctl(struct uart_port
*port
, int break_state
)
1602 struct uart_amba_port
*uap
=
1603 container_of(port
, struct uart_amba_port
, port
);
1604 unsigned long flags
;
1607 spin_lock_irqsave(&uap
->port
.lock
, flags
);
1608 lcr_h
= pl011_read(uap
, REG_LCRH_TX
);
1609 if (break_state
== -1)
1610 lcr_h
|= UART01x_LCRH_BRK
;
1612 lcr_h
&= ~UART01x_LCRH_BRK
;
1613 pl011_write(lcr_h
, uap
, REG_LCRH_TX
);
1614 spin_unlock_irqrestore(&uap
->port
.lock
, flags
);
1617 #ifdef CONFIG_CONSOLE_POLL
1619 static void pl011_quiesce_irqs(struct uart_port
*port
)
1621 struct uart_amba_port
*uap
=
1622 container_of(port
, struct uart_amba_port
, port
);
1624 pl011_write(pl011_read(uap
, REG_MIS
), uap
, REG_ICR
);
1626 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1627 * we simply mask it. start_tx() will unmask it.
1629 * Note we can race with start_tx(), and if the race happens, the
1630 * polling user might get another interrupt just after we clear it.
1631 * But it should be OK and can happen even w/o the race, e.g.
1632 * controller immediately got some new data and raised the IRQ.
1634 * And whoever uses polling routines assumes that it manages the device
1635 * (including tx queue), so we're also fine with start_tx()'s caller
1638 pl011_write(pl011_read(uap
, REG_IMSC
) & ~UART011_TXIM
, uap
,
1642 static int pl011_get_poll_char(struct uart_port
*port
)
1644 struct uart_amba_port
*uap
=
1645 container_of(port
, struct uart_amba_port
, port
);
1646 unsigned int status
;
1649 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1652 pl011_quiesce_irqs(port
);
1654 status
= pl011_read(uap
, REG_FR
);
1655 if (status
& UART01x_FR_RXFE
)
1656 return NO_POLL_CHAR
;
1658 return pl011_read(uap
, REG_DR
);
1661 static void pl011_put_poll_char(struct uart_port
*port
,
1664 struct uart_amba_port
*uap
=
1665 container_of(port
, struct uart_amba_port
, port
);
1667 while (pl011_read(uap
, REG_FR
) & UART01x_FR_TXFF
)
1670 pl011_write(ch
, uap
, REG_DR
);
1673 #endif /* CONFIG_CONSOLE_POLL */
1675 static int pl011_hwinit(struct uart_port
*port
)
1677 struct uart_amba_port
*uap
=
1678 container_of(port
, struct uart_amba_port
, port
);
1681 /* Optionaly enable pins to be muxed in and configured */
1682 pinctrl_pm_select_default_state(port
->dev
);
1685 * Try to enable the clock producer.
1687 retval
= clk_prepare_enable(uap
->clk
);
1691 uap
->port
.uartclk
= clk_get_rate(uap
->clk
);
1693 /* Clear pending error and receive interrupts */
1694 pl011_write(UART011_OEIS
| UART011_BEIS
| UART011_PEIS
|
1695 UART011_FEIS
| UART011_RTIS
| UART011_RXIS
,
1699 * Save interrupts enable mask, and enable RX interrupts in case if
1700 * the interrupt is used for NMI entry.
1702 uap
->im
= pl011_read(uap
, REG_IMSC
);
1703 pl011_write(UART011_RTIM
| UART011_RXIM
, uap
, REG_IMSC
);
1705 if (dev_get_platdata(uap
->port
.dev
)) {
1706 struct amba_pl011_data
*plat
;
1708 plat
= dev_get_platdata(uap
->port
.dev
);
1715 static bool pl011_split_lcrh(const struct uart_amba_port
*uap
)
1717 return pl011_reg_to_offset(uap
, REG_LCRH_RX
) !=
1718 pl011_reg_to_offset(uap
, REG_LCRH_TX
);
1721 static void pl011_write_lcr_h(struct uart_amba_port
*uap
, unsigned int lcr_h
)
1723 pl011_write(lcr_h
, uap
, REG_LCRH_RX
);
1724 if (pl011_split_lcrh(uap
)) {
1727 * Wait 10 PCLKs before writing LCRH_TX register,
1728 * to get this delay write read only register 10 times
1730 for (i
= 0; i
< 10; ++i
)
1731 pl011_write(0xff, uap
, REG_MIS
);
1732 pl011_write(lcr_h
, uap
, REG_LCRH_TX
);
1736 static int pl011_allocate_irq(struct uart_amba_port
*uap
)
1738 pl011_write(uap
->im
, uap
, REG_IMSC
);
1740 return request_irq(uap
->port
.irq
, pl011_int
, 0, "uart-pl011", uap
);
1744 * Enable interrupts, only timeouts when using DMA
1745 * if initial RX DMA job failed, start in interrupt mode
1748 static void pl011_enable_interrupts(struct uart_amba_port
*uap
)
1750 spin_lock_irq(&uap
->port
.lock
);
1752 /* Clear out any spuriously appearing RX interrupts */
1753 pl011_write(UART011_RTIS
| UART011_RXIS
, uap
, REG_ICR
);
1754 uap
->im
= UART011_RTIM
;
1755 if (!pl011_dma_rx_running(uap
))
1756 uap
->im
|= UART011_RXIM
;
1757 pl011_write(uap
->im
, uap
, REG_IMSC
);
1758 spin_unlock_irq(&uap
->port
.lock
);
1761 static int pl011_startup(struct uart_port
*port
)
1763 struct uart_amba_port
*uap
=
1764 container_of(port
, struct uart_amba_port
, port
);
1768 retval
= pl011_hwinit(port
);
1772 retval
= pl011_allocate_irq(uap
);
1776 pl011_write(uap
->vendor
->ifls
, uap
, REG_IFLS
);
1778 spin_lock_irq(&uap
->port
.lock
);
1780 /* restore RTS and DTR */
1781 cr
= uap
->old_cr
& (UART011_CR_RTS
| UART011_CR_DTR
);
1782 cr
|= UART01x_CR_UARTEN
| UART011_CR_RXE
| UART011_CR_TXE
;
1783 pl011_write(cr
, uap
, REG_CR
);
1785 spin_unlock_irq(&uap
->port
.lock
);
1788 * initialise the old status of the modem signals
1790 uap
->old_status
= pl011_read(uap
, REG_FR
) & UART01x_FR_MODEM_ANY
;
1793 pl011_dma_startup(uap
);
1795 pl011_enable_interrupts(uap
);
1800 clk_disable_unprepare(uap
->clk
);
1804 static int sbsa_uart_startup(struct uart_port
*port
)
1806 struct uart_amba_port
*uap
=
1807 container_of(port
, struct uart_amba_port
, port
);
1810 retval
= pl011_hwinit(port
);
1814 retval
= pl011_allocate_irq(uap
);
1818 /* The SBSA UART does not support any modem status lines. */
1819 uap
->old_status
= 0;
1821 pl011_enable_interrupts(uap
);
1826 static void pl011_shutdown_channel(struct uart_amba_port
*uap
,
1831 val
= pl011_read(uap
, lcrh
);
1832 val
&= ~(UART01x_LCRH_BRK
| UART01x_LCRH_FEN
);
1833 pl011_write(val
, uap
, lcrh
);
1837 * disable the port. It should not disable RTS and DTR.
1838 * Also RTS and DTR state should be preserved to restore
1839 * it during startup().
1841 static void pl011_disable_uart(struct uart_amba_port
*uap
)
1845 uap
->autorts
= false;
1846 spin_lock_irq(&uap
->port
.lock
);
1847 cr
= pl011_read(uap
, REG_CR
);
1849 cr
&= UART011_CR_RTS
| UART011_CR_DTR
;
1850 cr
|= UART01x_CR_UARTEN
| UART011_CR_TXE
;
1851 pl011_write(cr
, uap
, REG_CR
);
1852 spin_unlock_irq(&uap
->port
.lock
);
1855 * disable break condition and fifos
1857 pl011_shutdown_channel(uap
, REG_LCRH_RX
);
1858 if (pl011_split_lcrh(uap
))
1859 pl011_shutdown_channel(uap
, REG_LCRH_TX
);
1862 static void pl011_disable_interrupts(struct uart_amba_port
*uap
)
1864 spin_lock_irq(&uap
->port
.lock
);
1866 /* mask all interrupts and clear all pending ones */
1868 pl011_write(uap
->im
, uap
, REG_IMSC
);
1869 pl011_write(0xffff, uap
, REG_ICR
);
1871 spin_unlock_irq(&uap
->port
.lock
);
1874 static void pl011_shutdown(struct uart_port
*port
)
1876 struct uart_amba_port
*uap
=
1877 container_of(port
, struct uart_amba_port
, port
);
1879 pl011_disable_interrupts(uap
);
1881 pl011_dma_shutdown(uap
);
1883 free_irq(uap
->port
.irq
, uap
);
1885 pl011_disable_uart(uap
);
1888 * Shut down the clock producer
1890 clk_disable_unprepare(uap
->clk
);
1891 /* Optionally let pins go into sleep states */
1892 pinctrl_pm_select_sleep_state(port
->dev
);
1894 if (dev_get_platdata(uap
->port
.dev
)) {
1895 struct amba_pl011_data
*plat
;
1897 plat
= dev_get_platdata(uap
->port
.dev
);
1902 if (uap
->port
.ops
->flush_buffer
)
1903 uap
->port
.ops
->flush_buffer(port
);
1906 static void sbsa_uart_shutdown(struct uart_port
*port
)
1908 struct uart_amba_port
*uap
=
1909 container_of(port
, struct uart_amba_port
, port
);
1911 pl011_disable_interrupts(uap
);
1913 free_irq(uap
->port
.irq
, uap
);
1915 if (uap
->port
.ops
->flush_buffer
)
1916 uap
->port
.ops
->flush_buffer(port
);
1920 pl011_setup_status_masks(struct uart_port
*port
, struct ktermios
*termios
)
1922 port
->read_status_mask
= UART011_DR_OE
| 255;
1923 if (termios
->c_iflag
& INPCK
)
1924 port
->read_status_mask
|= UART011_DR_FE
| UART011_DR_PE
;
1925 if (termios
->c_iflag
& (IGNBRK
| BRKINT
| PARMRK
))
1926 port
->read_status_mask
|= UART011_DR_BE
;
1929 * Characters to ignore
1931 port
->ignore_status_mask
= 0;
1932 if (termios
->c_iflag
& IGNPAR
)
1933 port
->ignore_status_mask
|= UART011_DR_FE
| UART011_DR_PE
;
1934 if (termios
->c_iflag
& IGNBRK
) {
1935 port
->ignore_status_mask
|= UART011_DR_BE
;
1937 * If we're ignoring parity and break indicators,
1938 * ignore overruns too (for real raw support).
1940 if (termios
->c_iflag
& IGNPAR
)
1941 port
->ignore_status_mask
|= UART011_DR_OE
;
1945 * Ignore all characters if CREAD is not set.
1947 if ((termios
->c_cflag
& CREAD
) == 0)
1948 port
->ignore_status_mask
|= UART_DUMMY_DR_RX
;
1952 pl011_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
1953 struct ktermios
*old
)
1955 struct uart_amba_port
*uap
=
1956 container_of(port
, struct uart_amba_port
, port
);
1957 unsigned int lcr_h
, old_cr
;
1958 unsigned long flags
;
1959 unsigned int baud
, quot
, clkdiv
;
1961 if (uap
->vendor
->oversampling
)
1967 * Ask the core to calculate the divisor for us.
1969 baud
= uart_get_baud_rate(port
, termios
, old
, 0,
1970 port
->uartclk
/ clkdiv
);
1971 #ifdef CONFIG_DMA_ENGINE
1973 * Adjust RX DMA polling rate with baud rate if not specified.
1975 if (uap
->dmarx
.auto_poll_rate
)
1976 uap
->dmarx
.poll_rate
= DIV_ROUND_UP(10000000, baud
);
1979 if (baud
> port
->uartclk
/16)
1980 quot
= DIV_ROUND_CLOSEST(port
->uartclk
* 8, baud
);
1982 quot
= DIV_ROUND_CLOSEST(port
->uartclk
* 4, baud
);
1984 switch (termios
->c_cflag
& CSIZE
) {
1986 lcr_h
= UART01x_LCRH_WLEN_5
;
1989 lcr_h
= UART01x_LCRH_WLEN_6
;
1992 lcr_h
= UART01x_LCRH_WLEN_7
;
1995 lcr_h
= UART01x_LCRH_WLEN_8
;
1998 if (termios
->c_cflag
& CSTOPB
)
1999 lcr_h
|= UART01x_LCRH_STP2
;
2000 if (termios
->c_cflag
& PARENB
) {
2001 lcr_h
|= UART01x_LCRH_PEN
;
2002 if (!(termios
->c_cflag
& PARODD
))
2003 lcr_h
|= UART01x_LCRH_EPS
;
2004 if (termios
->c_cflag
& CMSPAR
)
2005 lcr_h
|= UART011_LCRH_SPS
;
2007 if (uap
->fifosize
> 1)
2008 lcr_h
|= UART01x_LCRH_FEN
;
2010 spin_lock_irqsave(&port
->lock
, flags
);
2013 * Update the per-port timeout.
2015 uart_update_timeout(port
, termios
->c_cflag
, baud
);
2017 pl011_setup_status_masks(port
, termios
);
2019 if (UART_ENABLE_MS(port
, termios
->c_cflag
))
2020 pl011_enable_ms(port
);
2022 /* first, disable everything */
2023 old_cr
= pl011_read(uap
, REG_CR
);
2024 pl011_write(0, uap
, REG_CR
);
2026 if (termios
->c_cflag
& CRTSCTS
) {
2027 if (old_cr
& UART011_CR_RTS
)
2028 old_cr
|= UART011_CR_RTSEN
;
2030 old_cr
|= UART011_CR_CTSEN
;
2031 uap
->autorts
= true;
2033 old_cr
&= ~(UART011_CR_CTSEN
| UART011_CR_RTSEN
);
2034 uap
->autorts
= false;
2037 if (uap
->vendor
->oversampling
) {
2038 if (baud
> port
->uartclk
/ 16)
2039 old_cr
|= ST_UART011_CR_OVSFACT
;
2041 old_cr
&= ~ST_UART011_CR_OVSFACT
;
2045 * Workaround for the ST Micro oversampling variants to
2046 * increase the bitrate slightly, by lowering the divisor,
2047 * to avoid delayed sampling of start bit at high speeds,
2048 * else we see data corruption.
2050 if (uap
->vendor
->oversampling
) {
2051 if ((baud
>= 3000000) && (baud
< 3250000) && (quot
> 1))
2053 else if ((baud
> 3250000) && (quot
> 2))
2057 pl011_write(quot
& 0x3f, uap
, REG_FBRD
);
2058 pl011_write(quot
>> 6, uap
, REG_IBRD
);
2061 * ----------v----------v----------v----------v-----
2062 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
2063 * REG_FBRD & REG_IBRD.
2064 * ----------^----------^----------^----------^-----
2066 pl011_write_lcr_h(uap
, lcr_h
);
2067 pl011_write(old_cr
, uap
, REG_CR
);
2069 spin_unlock_irqrestore(&port
->lock
, flags
);
2073 sbsa_uart_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
2074 struct ktermios
*old
)
2076 struct uart_amba_port
*uap
=
2077 container_of(port
, struct uart_amba_port
, port
);
2078 unsigned long flags
;
2080 tty_termios_encode_baud_rate(termios
, uap
->fixed_baud
, uap
->fixed_baud
);
2082 /* The SBSA UART only supports 8n1 without hardware flow control. */
2083 termios
->c_cflag
&= ~(CSIZE
| CSTOPB
| PARENB
| PARODD
);
2084 termios
->c_cflag
&= ~(CMSPAR
| CRTSCTS
);
2085 termios
->c_cflag
|= CS8
| CLOCAL
;
2087 spin_lock_irqsave(&port
->lock
, flags
);
2088 uart_update_timeout(port
, CS8
, uap
->fixed_baud
);
2089 pl011_setup_status_masks(port
, termios
);
2090 spin_unlock_irqrestore(&port
->lock
, flags
);
2093 static const char *pl011_type(struct uart_port
*port
)
2095 struct uart_amba_port
*uap
=
2096 container_of(port
, struct uart_amba_port
, port
);
2097 return uap
->port
.type
== PORT_AMBA
? uap
->type
: NULL
;
2101 * Release the memory region(s) being used by 'port'
2103 static void pl011_release_port(struct uart_port
*port
)
2105 release_mem_region(port
->mapbase
, SZ_4K
);
2109 * Request the memory region(s) being used by 'port'
2111 static int pl011_request_port(struct uart_port
*port
)
2113 return request_mem_region(port
->mapbase
, SZ_4K
, "uart-pl011")
2114 != NULL
? 0 : -EBUSY
;
2118 * Configure/autoconfigure the port.
2120 static void pl011_config_port(struct uart_port
*port
, int flags
)
2122 if (flags
& UART_CONFIG_TYPE
) {
2123 port
->type
= PORT_AMBA
;
2124 pl011_request_port(port
);
2129 * verify the new serial_struct (for TIOCSSERIAL).
2131 static int pl011_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
2134 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_AMBA
)
2136 if (ser
->irq
< 0 || ser
->irq
>= nr_irqs
)
2138 if (ser
->baud_base
< 9600)
2143 static const struct uart_ops amba_pl011_pops
= {
2144 .tx_empty
= pl011_tx_empty
,
2145 .set_mctrl
= pl011_set_mctrl
,
2146 .get_mctrl
= pl011_get_mctrl
,
2147 .stop_tx
= pl011_stop_tx
,
2148 .start_tx
= pl011_start_tx
,
2149 .stop_rx
= pl011_stop_rx
,
2150 .enable_ms
= pl011_enable_ms
,
2151 .break_ctl
= pl011_break_ctl
,
2152 .startup
= pl011_startup
,
2153 .shutdown
= pl011_shutdown
,
2154 .flush_buffer
= pl011_dma_flush_buffer
,
2155 .set_termios
= pl011_set_termios
,
2157 .release_port
= pl011_release_port
,
2158 .request_port
= pl011_request_port
,
2159 .config_port
= pl011_config_port
,
2160 .verify_port
= pl011_verify_port
,
2161 #ifdef CONFIG_CONSOLE_POLL
2162 .poll_init
= pl011_hwinit
,
2163 .poll_get_char
= pl011_get_poll_char
,
2164 .poll_put_char
= pl011_put_poll_char
,
2168 static void sbsa_uart_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
2172 static unsigned int sbsa_uart_get_mctrl(struct uart_port
*port
)
2177 static const struct uart_ops sbsa_uart_pops
= {
2178 .tx_empty
= pl011_tx_empty
,
2179 .set_mctrl
= sbsa_uart_set_mctrl
,
2180 .get_mctrl
= sbsa_uart_get_mctrl
,
2181 .stop_tx
= pl011_stop_tx
,
2182 .start_tx
= pl011_start_tx
,
2183 .stop_rx
= pl011_stop_rx
,
2184 .startup
= sbsa_uart_startup
,
2185 .shutdown
= sbsa_uart_shutdown
,
2186 .set_termios
= sbsa_uart_set_termios
,
2188 .release_port
= pl011_release_port
,
2189 .request_port
= pl011_request_port
,
2190 .config_port
= pl011_config_port
,
2191 .verify_port
= pl011_verify_port
,
2192 #ifdef CONFIG_CONSOLE_POLL
2193 .poll_init
= pl011_hwinit
,
2194 .poll_get_char
= pl011_get_poll_char
,
2195 .poll_put_char
= pl011_put_poll_char
,
2199 static struct uart_amba_port
*amba_ports
[UART_NR
];
2201 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2203 static void pl011_console_putchar(struct uart_port
*port
, int ch
)
2205 struct uart_amba_port
*uap
=
2206 container_of(port
, struct uart_amba_port
, port
);
2208 while (pl011_read(uap
, REG_FR
) & UART01x_FR_TXFF
)
2210 pl011_write(ch
, uap
, REG_DR
);
2214 pl011_console_write(struct console
*co
, const char *s
, unsigned int count
)
2216 struct uart_amba_port
*uap
= amba_ports
[co
->index
];
2217 unsigned int old_cr
= 0, new_cr
;
2218 unsigned long flags
;
2221 clk_enable(uap
->clk
);
2223 local_irq_save(flags
);
2224 if (uap
->port
.sysrq
)
2226 else if (oops_in_progress
)
2227 locked
= spin_trylock(&uap
->port
.lock
);
2229 spin_lock(&uap
->port
.lock
);
2232 * First save the CR then disable the interrupts
2234 if (!uap
->vendor
->always_enabled
) {
2235 old_cr
= pl011_read(uap
, REG_CR
);
2236 new_cr
= old_cr
& ~UART011_CR_CTSEN
;
2237 new_cr
|= UART01x_CR_UARTEN
| UART011_CR_TXE
;
2238 pl011_write(new_cr
, uap
, REG_CR
);
2241 uart_console_write(&uap
->port
, s
, count
, pl011_console_putchar
);
2244 * Finally, wait for transmitter to become empty and restore the
2245 * TCR. Allow feature register bits to be inverted to work around
2248 while ((pl011_read(uap
, REG_FR
) ^ uap
->vendor
->inv_fr
)
2249 & uap
->vendor
->fr_busy
)
2251 if (!uap
->vendor
->always_enabled
)
2252 pl011_write(old_cr
, uap
, REG_CR
);
2255 spin_unlock(&uap
->port
.lock
);
2256 local_irq_restore(flags
);
2258 clk_disable(uap
->clk
);
2262 pl011_console_get_options(struct uart_amba_port
*uap
, int *baud
,
2263 int *parity
, int *bits
)
2265 if (pl011_read(uap
, REG_CR
) & UART01x_CR_UARTEN
) {
2266 unsigned int lcr_h
, ibrd
, fbrd
;
2268 lcr_h
= pl011_read(uap
, REG_LCRH_TX
);
2271 if (lcr_h
& UART01x_LCRH_PEN
) {
2272 if (lcr_h
& UART01x_LCRH_EPS
)
2278 if ((lcr_h
& 0x60) == UART01x_LCRH_WLEN_7
)
2283 ibrd
= pl011_read(uap
, REG_IBRD
);
2284 fbrd
= pl011_read(uap
, REG_FBRD
);
2286 *baud
= uap
->port
.uartclk
* 4 / (64 * ibrd
+ fbrd
);
2288 if (uap
->vendor
->oversampling
) {
2289 if (pl011_read(uap
, REG_CR
)
2290 & ST_UART011_CR_OVSFACT
)
2296 static int __init
pl011_console_setup(struct console
*co
, char *options
)
2298 struct uart_amba_port
*uap
;
2306 * Check whether an invalid uart number has been specified, and
2307 * if so, search for the first available port that does have
2310 if (co
->index
>= UART_NR
)
2312 uap
= amba_ports
[co
->index
];
2316 /* Allow pins to be muxed in and configured */
2317 pinctrl_pm_select_default_state(uap
->port
.dev
);
2319 ret
= clk_prepare(uap
->clk
);
2323 if (dev_get_platdata(uap
->port
.dev
)) {
2324 struct amba_pl011_data
*plat
;
2326 plat
= dev_get_platdata(uap
->port
.dev
);
2331 uap
->port
.uartclk
= clk_get_rate(uap
->clk
);
2333 if (uap
->vendor
->fixed_options
) {
2334 baud
= uap
->fixed_baud
;
2337 uart_parse_options(options
,
2338 &baud
, &parity
, &bits
, &flow
);
2340 pl011_console_get_options(uap
, &baud
, &parity
, &bits
);
2343 return uart_set_options(&uap
->port
, co
, baud
, parity
, bits
, flow
);
2347 * pl011_console_match - non-standard console matching
2348 * @co: registering console
2349 * @name: name from console command line
2350 * @idx: index from console command line
2351 * @options: ptr to option string from console command line
2353 * Only attempts to match console command lines of the form:
2354 * console=pl011,mmio|mmio32,<addr>[,<options>]
2355 * console=pl011,0x<addr>[,<options>]
2356 * This form is used to register an initial earlycon boot console and
2357 * replace it with the amba_console at pl011 driver init.
2359 * Performs console setup for a match (as required by interface)
2360 * If no <options> are specified, then assume the h/w is already setup.
2362 * Returns 0 if console matches; otherwise non-zero to use default matching
2364 static int __init
pl011_console_match(struct console
*co
, char *name
, int idx
,
2367 unsigned char iotype
;
2368 resource_size_t addr
;
2372 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum
2373 * have a distinct console name, so make sure we check for that.
2374 * The actual implementation of the erratum occurs in the probe
2377 if ((strcmp(name
, "qdf2400_e44") != 0) && (strcmp(name
, "pl011") != 0))
2380 if (uart_parse_earlycon(options
, &iotype
, &addr
, &options
))
2383 if (iotype
!= UPIO_MEM
&& iotype
!= UPIO_MEM32
)
2386 /* try to match the port specified on the command line */
2387 for (i
= 0; i
< ARRAY_SIZE(amba_ports
); i
++) {
2388 struct uart_port
*port
;
2393 port
= &amba_ports
[i
]->port
;
2395 if (port
->mapbase
!= addr
)
2400 return pl011_console_setup(co
, options
);
2406 static struct uart_driver amba_reg
;
2407 static struct console amba_console
= {
2409 .write
= pl011_console_write
,
2410 .device
= uart_console_device
,
2411 .setup
= pl011_console_setup
,
2412 .match
= pl011_console_match
,
2413 .flags
= CON_PRINTBUFFER
| CON_ANYTIME
,
2418 #define AMBA_CONSOLE (&amba_console)
2420 static void qdf2400_e44_putc(struct uart_port
*port
, int c
)
2422 while (readl(port
->membase
+ UART01x_FR
) & UART01x_FR_TXFF
)
2424 writel(c
, port
->membase
+ UART01x_DR
);
2425 while (!(readl(port
->membase
+ UART01x_FR
) & UART011_FR_TXFE
))
2429 static void qdf2400_e44_early_write(struct console
*con
, const char *s
, unsigned n
)
2431 struct earlycon_device
*dev
= con
->data
;
2433 uart_console_write(&dev
->port
, s
, n
, qdf2400_e44_putc
);
2436 static void pl011_putc(struct uart_port
*port
, int c
)
2438 while (readl(port
->membase
+ UART01x_FR
) & UART01x_FR_TXFF
)
2440 if (port
->iotype
== UPIO_MEM32
)
2441 writel(c
, port
->membase
+ UART01x_DR
);
2443 writeb(c
, port
->membase
+ UART01x_DR
);
2444 while (readl(port
->membase
+ UART01x_FR
) & UART01x_FR_BUSY
)
2448 static void pl011_early_write(struct console
*con
, const char *s
, unsigned n
)
2450 struct earlycon_device
*dev
= con
->data
;
2452 uart_console_write(&dev
->port
, s
, n
, pl011_putc
);
2456 * On non-ACPI systems, earlycon is enabled by specifying
2457 * "earlycon=pl011,<address>" on the kernel command line.
2459 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table,
2460 * by specifying only "earlycon" on the command line. Because it requires
2461 * SPCR, the console starts after ACPI is parsed, which is later than a
2462 * traditional early console.
2464 * To get the traditional early console that starts before ACPI is parsed,
2465 * specify the full "earlycon=pl011,<address>" option.
2467 static int __init
pl011_early_console_setup(struct earlycon_device
*device
,
2470 if (!device
->port
.membase
)
2473 device
->con
->write
= pl011_early_write
;
2477 OF_EARLYCON_DECLARE(pl011
, "arm,pl011", pl011_early_console_setup
);
2478 OF_EARLYCON_DECLARE(pl011
, "arm,sbsa-uart", pl011_early_console_setup
);
2481 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by
2482 * Erratum 44, traditional earlycon can be enabled by specifying
2483 * "earlycon=qdf2400_e44,<address>". Any options are ignored.
2485 * Alternatively, you can just specify "earlycon", and the early console
2486 * will be enabled with the information from the SPCR table. In this
2487 * case, the SPCR code will detect the need for the E44 work-around,
2488 * and set the console name to "qdf2400_e44".
2491 qdf2400_e44_early_console_setup(struct earlycon_device
*device
,
2494 if (!device
->port
.membase
)
2497 device
->con
->write
= qdf2400_e44_early_write
;
2500 EARLYCON_DECLARE(qdf2400_e44
, qdf2400_e44_early_console_setup
);
2503 #define AMBA_CONSOLE NULL
2506 static struct uart_driver amba_reg
= {
2507 .owner
= THIS_MODULE
,
2508 .driver_name
= "ttyAMA",
2509 .dev_name
= "ttyAMA",
2510 .major
= SERIAL_AMBA_MAJOR
,
2511 .minor
= SERIAL_AMBA_MINOR
,
2513 .cons
= AMBA_CONSOLE
,
2516 static int pl011_probe_dt_alias(int index
, struct device
*dev
)
2518 struct device_node
*np
;
2519 static bool seen_dev_with_alias
= false;
2520 static bool seen_dev_without_alias
= false;
2523 if (!IS_ENABLED(CONFIG_OF
))
2530 ret
= of_alias_get_id(np
, "serial");
2532 seen_dev_without_alias
= true;
2535 seen_dev_with_alias
= true;
2536 if (ret
>= ARRAY_SIZE(amba_ports
) || amba_ports
[ret
] != NULL
) {
2537 dev_warn(dev
, "requested serial port %d not available.\n", ret
);
2542 if (seen_dev_with_alias
&& seen_dev_without_alias
)
2543 dev_warn(dev
, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2548 /* unregisters the driver also if no more ports are left */
2549 static void pl011_unregister_port(struct uart_amba_port
*uap
)
2554 for (i
= 0; i
< ARRAY_SIZE(amba_ports
); i
++) {
2555 if (amba_ports
[i
] == uap
)
2556 amba_ports
[i
] = NULL
;
2557 else if (amba_ports
[i
])
2560 pl011_dma_remove(uap
);
2562 uart_unregister_driver(&amba_reg
);
2565 static int pl011_find_free_port(void)
2569 for (i
= 0; i
< ARRAY_SIZE(amba_ports
); i
++)
2570 if (amba_ports
[i
] == NULL
)
2576 static int pl011_setup_port(struct device
*dev
, struct uart_amba_port
*uap
,
2577 struct resource
*mmiobase
, int index
)
2581 base
= devm_ioremap_resource(dev
, mmiobase
);
2583 return PTR_ERR(base
);
2585 index
= pl011_probe_dt_alias(index
, dev
);
2588 uap
->port
.dev
= dev
;
2589 uap
->port
.mapbase
= mmiobase
->start
;
2590 uap
->port
.membase
= base
;
2591 uap
->port
.fifosize
= uap
->fifosize
;
2592 uap
->port
.flags
= UPF_BOOT_AUTOCONF
;
2593 uap
->port
.line
= index
;
2595 amba_ports
[index
] = uap
;
2600 static int pl011_register_port(struct uart_amba_port
*uap
)
2604 /* Ensure interrupts from this UART are masked and cleared */
2605 pl011_write(0, uap
, REG_IMSC
);
2606 pl011_write(0xffff, uap
, REG_ICR
);
2608 if (!amba_reg
.state
) {
2609 ret
= uart_register_driver(&amba_reg
);
2611 dev_err(uap
->port
.dev
,
2612 "Failed to register AMBA-PL011 driver\n");
2617 ret
= uart_add_one_port(&amba_reg
, &uap
->port
);
2619 pl011_unregister_port(uap
);
2624 static int pl011_probe(struct amba_device
*dev
, const struct amba_id
*id
)
2626 struct uart_amba_port
*uap
;
2627 struct vendor_data
*vendor
= id
->data
;
2630 portnr
= pl011_find_free_port();
2634 uap
= devm_kzalloc(&dev
->dev
, sizeof(struct uart_amba_port
),
2639 uap
->clk
= devm_clk_get(&dev
->dev
, NULL
);
2640 if (IS_ERR(uap
->clk
))
2641 return PTR_ERR(uap
->clk
);
2643 uap
->reg_offset
= vendor
->reg_offset
;
2644 uap
->vendor
= vendor
;
2645 uap
->fifosize
= vendor
->get_fifosize(dev
);
2646 uap
->port
.iotype
= vendor
->access_32b
? UPIO_MEM32
: UPIO_MEM
;
2647 uap
->port
.irq
= dev
->irq
[0];
2648 uap
->port
.ops
= &amba_pl011_pops
;
2650 snprintf(uap
->type
, sizeof(uap
->type
), "PL011 rev%u", amba_rev(dev
));
2652 ret
= pl011_setup_port(&dev
->dev
, uap
, &dev
->res
, portnr
);
2656 amba_set_drvdata(dev
, uap
);
2658 return pl011_register_port(uap
);
2661 static int pl011_remove(struct amba_device
*dev
)
2663 struct uart_amba_port
*uap
= amba_get_drvdata(dev
);
2665 uart_remove_one_port(&amba_reg
, &uap
->port
);
2666 pl011_unregister_port(uap
);
2670 #ifdef CONFIG_PM_SLEEP
2671 static int pl011_suspend(struct device
*dev
)
2673 struct uart_amba_port
*uap
= dev_get_drvdata(dev
);
2678 return uart_suspend_port(&amba_reg
, &uap
->port
);
2681 static int pl011_resume(struct device
*dev
)
2683 struct uart_amba_port
*uap
= dev_get_drvdata(dev
);
2688 return uart_resume_port(&amba_reg
, &uap
->port
);
2692 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops
, pl011_suspend
, pl011_resume
);
2694 static int sbsa_uart_probe(struct platform_device
*pdev
)
2696 struct uart_amba_port
*uap
;
2702 * Check the mandatory baud rate parameter in the DT node early
2703 * so that we can easily exit with the error.
2705 if (pdev
->dev
.of_node
) {
2706 struct device_node
*np
= pdev
->dev
.of_node
;
2708 ret
= of_property_read_u32(np
, "current-speed", &baudrate
);
2715 portnr
= pl011_find_free_port();
2719 uap
= devm_kzalloc(&pdev
->dev
, sizeof(struct uart_amba_port
),
2724 ret
= platform_get_irq(pdev
, 0);
2726 if (ret
!= -EPROBE_DEFER
)
2727 dev_err(&pdev
->dev
, "cannot obtain irq\n");
2730 uap
->port
.irq
= ret
;
2732 #ifdef CONFIG_ACPI_SPCR_TABLE
2733 if (qdf2400_e44_present
) {
2734 dev_info(&pdev
->dev
, "working around QDF2400 SoC erratum 44\n");
2735 uap
->vendor
= &vendor_qdt_qdf2400_e44
;
2738 uap
->vendor
= &vendor_sbsa
;
2740 uap
->reg_offset
= uap
->vendor
->reg_offset
;
2742 uap
->port
.iotype
= uap
->vendor
->access_32b
? UPIO_MEM32
: UPIO_MEM
;
2743 uap
->port
.ops
= &sbsa_uart_pops
;
2744 uap
->fixed_baud
= baudrate
;
2746 snprintf(uap
->type
, sizeof(uap
->type
), "SBSA");
2748 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2750 ret
= pl011_setup_port(&pdev
->dev
, uap
, r
, portnr
);
2754 platform_set_drvdata(pdev
, uap
);
2756 return pl011_register_port(uap
);
2759 static int sbsa_uart_remove(struct platform_device
*pdev
)
2761 struct uart_amba_port
*uap
= platform_get_drvdata(pdev
);
2763 uart_remove_one_port(&amba_reg
, &uap
->port
);
2764 pl011_unregister_port(uap
);
2768 static const struct of_device_id sbsa_uart_of_match
[] = {
2769 { .compatible
= "arm,sbsa-uart", },
2772 MODULE_DEVICE_TABLE(of
, sbsa_uart_of_match
);
2774 static const struct acpi_device_id sbsa_uart_acpi_match
[] = {
2778 MODULE_DEVICE_TABLE(acpi
, sbsa_uart_acpi_match
);
2780 static struct platform_driver arm_sbsa_uart_platform_driver
= {
2781 .probe
= sbsa_uart_probe
,
2782 .remove
= sbsa_uart_remove
,
2784 .name
= "sbsa-uart",
2785 .of_match_table
= of_match_ptr(sbsa_uart_of_match
),
2786 .acpi_match_table
= ACPI_PTR(sbsa_uart_acpi_match
),
2790 static struct amba_id pl011_ids
[] = {
2794 .data
= &vendor_arm
,
2802 .id
= AMBA_LINUX_ID(0x00, 0x1, 0xffe),
2804 .data
= &vendor_zte
,
2809 MODULE_DEVICE_TABLE(amba
, pl011_ids
);
2811 static struct amba_driver pl011_driver
= {
2813 .name
= "uart-pl011",
2814 .pm
= &pl011_dev_pm_ops
,
2816 .id_table
= pl011_ids
,
2817 .probe
= pl011_probe
,
2818 .remove
= pl011_remove
,
2821 static int __init
pl011_init(void)
2823 printk(KERN_INFO
"Serial: AMBA PL011 UART driver\n");
2825 if (platform_driver_register(&arm_sbsa_uart_platform_driver
))
2826 pr_warn("could not register SBSA UART platform driver\n");
2827 return amba_driver_register(&pl011_driver
);
2830 static void __exit
pl011_exit(void)
2832 platform_driver_unregister(&arm_sbsa_uart_platform_driver
);
2833 amba_driver_unregister(&pl011_driver
);
2837 * While this can be a module, if builtin it's most likely the console
2838 * So let's leave module_exit but move module_init to an earlier place
2840 arch_initcall(pl011_init
);
2841 module_exit(pl011_exit
);
2843 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2844 MODULE_DESCRIPTION("ARM AMBA serial port driver");
2845 MODULE_LICENSE("GPL");