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[mirror_ubuntu-artful-kernel.git] / drivers / tty / serial / atmel_serial.c
1 /*
2 * Driver for Atmel AT91 / AT32 Serial ports
3 * Copyright (C) 2003 Rick Bronson
4 *
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * DMA support added by Chip Coldwell.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25 #include <linux/module.h>
26 #include <linux/tty.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/init.h>
30 #include <linux/serial.h>
31 #include <linux/clk.h>
32 #include <linux/console.h>
33 #include <linux/sysrq.h>
34 #include <linux/tty_flip.h>
35 #include <linux/platform_device.h>
36 #include <linux/of.h>
37 #include <linux/of_device.h>
38 #include <linux/of_gpio.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/atmel_pdc.h>
41 #include <linux/atmel_serial.h>
42 #include <linux/uaccess.h>
43 #include <linux/platform_data/atmel.h>
44 #include <linux/timer.h>
45 #include <linux/gpio.h>
46
47 #include <asm/io.h>
48 #include <asm/ioctls.h>
49
50 #define PDC_BUFFER_SIZE 512
51 /* Revisit: We should calculate this based on the actual port settings */
52 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
53
54 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
55 #define SUPPORT_SYSRQ
56 #endif
57
58 #include <linux/serial_core.h>
59
60 static void atmel_start_rx(struct uart_port *port);
61 static void atmel_stop_rx(struct uart_port *port);
62
63 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
64
65 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
66 * should coexist with the 8250 driver, such as if we have an external 16C550
67 * UART. */
68 #define SERIAL_ATMEL_MAJOR 204
69 #define MINOR_START 154
70 #define ATMEL_DEVICENAME "ttyAT"
71
72 #else
73
74 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
75 * name, but it is legally reserved for the 8250 driver. */
76 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
77 #define MINOR_START 64
78 #define ATMEL_DEVICENAME "ttyS"
79
80 #endif
81
82 #define ATMEL_ISR_PASS_LIMIT 256
83
84 /* UART registers. CR is write-only, hence no GET macro */
85 #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
86 #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
87 #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
88 #define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER)
89 #define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR)
90 #define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR)
91 #define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR)
92 #define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR)
93 #define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR)
94 #define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR)
95 #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR)
96 #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR)
97 #define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR)
98 #define UART_GET_IP_NAME(port) __raw_readl((port)->membase + ATMEL_US_NAME)
99 #define UART_GET_IP_VERSION(port) __raw_readl((port)->membase + ATMEL_US_VERSION)
100
101 /* PDC registers */
102 #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
103 #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR)
104
105 #define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR)
106 #define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR)
107 #define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR)
108 #define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR)
109 #define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR)
110
111 #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
112 #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
113 #define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR)
114
115 static int (*atmel_open_hook)(struct uart_port *);
116 static void (*atmel_close_hook)(struct uart_port *);
117
118 struct atmel_dma_buffer {
119 unsigned char *buf;
120 dma_addr_t dma_addr;
121 unsigned int dma_size;
122 unsigned int ofs;
123 };
124
125 struct atmel_uart_char {
126 u16 status;
127 u16 ch;
128 };
129
130 #define ATMEL_SERIAL_RINGSIZE 1024
131
132 /*
133 * We wrap our port structure around the generic uart_port.
134 */
135 struct atmel_uart_port {
136 struct uart_port uart; /* uart */
137 struct clk *clk; /* uart clock */
138 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
139 u32 backup_imr; /* IMR saved during suspend */
140 int break_active; /* break being received */
141
142 bool use_dma_rx; /* enable DMA receiver */
143 bool use_pdc_rx; /* enable PDC receiver */
144 short pdc_rx_idx; /* current PDC RX buffer */
145 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
146
147 bool use_dma_tx; /* enable DMA transmitter */
148 bool use_pdc_tx; /* enable PDC transmitter */
149 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
150
151 spinlock_t lock_tx; /* port lock */
152 spinlock_t lock_rx; /* port lock */
153 struct dma_chan *chan_tx;
154 struct dma_chan *chan_rx;
155 struct dma_async_tx_descriptor *desc_tx;
156 struct dma_async_tx_descriptor *desc_rx;
157 dma_cookie_t cookie_tx;
158 dma_cookie_t cookie_rx;
159 struct scatterlist sg_tx;
160 struct scatterlist sg_rx;
161 struct tasklet_struct tasklet;
162 unsigned int irq_status;
163 unsigned int irq_status_prev;
164
165 struct circ_buf rx_ring;
166
167 struct serial_rs485 rs485; /* rs485 settings */
168 int rts_gpio; /* optional RTS GPIO */
169 unsigned int tx_done_mask;
170 bool is_usart; /* usart or uart */
171 struct timer_list uart_timer; /* uart timer */
172 int (*prepare_rx)(struct uart_port *port);
173 int (*prepare_tx)(struct uart_port *port);
174 void (*schedule_rx)(struct uart_port *port);
175 void (*schedule_tx)(struct uart_port *port);
176 void (*release_rx)(struct uart_port *port);
177 void (*release_tx)(struct uart_port *port);
178 };
179
180 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
181 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
182
183 #ifdef SUPPORT_SYSRQ
184 static struct console atmel_console;
185 #endif
186
187 #if defined(CONFIG_OF)
188 static const struct of_device_id atmel_serial_dt_ids[] = {
189 { .compatible = "atmel,at91rm9200-usart" },
190 { .compatible = "atmel,at91sam9260-usart" },
191 { /* sentinel */ }
192 };
193
194 MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids);
195 #endif
196
197 static inline struct atmel_uart_port *
198 to_atmel_uart_port(struct uart_port *uart)
199 {
200 return container_of(uart, struct atmel_uart_port, uart);
201 }
202
203 #ifdef CONFIG_SERIAL_ATMEL_PDC
204 static bool atmel_use_pdc_rx(struct uart_port *port)
205 {
206 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
207
208 return atmel_port->use_pdc_rx;
209 }
210
211 static bool atmel_use_pdc_tx(struct uart_port *port)
212 {
213 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
214
215 return atmel_port->use_pdc_tx;
216 }
217 #else
218 static bool atmel_use_pdc_rx(struct uart_port *port)
219 {
220 return false;
221 }
222
223 static bool atmel_use_pdc_tx(struct uart_port *port)
224 {
225 return false;
226 }
227 #endif
228
229 static bool atmel_use_dma_tx(struct uart_port *port)
230 {
231 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
232
233 return atmel_port->use_dma_tx;
234 }
235
236 static bool atmel_use_dma_rx(struct uart_port *port)
237 {
238 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
239
240 return atmel_port->use_dma_rx;
241 }
242
243 /* Enable or disable the rs485 support */
244 void atmel_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
245 {
246 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
247 unsigned int mode;
248 unsigned long flags;
249
250 spin_lock_irqsave(&port->lock, flags);
251
252 /* Disable interrupts */
253 UART_PUT_IDR(port, atmel_port->tx_done_mask);
254
255 mode = UART_GET_MR(port);
256
257 /* Resetting serial mode to RS232 (0x0) */
258 mode &= ~ATMEL_US_USMODE;
259
260 atmel_port->rs485 = *rs485conf;
261
262 if (rs485conf->flags & SER_RS485_ENABLED) {
263 dev_dbg(port->dev, "Setting UART to RS485\n");
264 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
265 if ((rs485conf->delay_rts_after_send) > 0)
266 UART_PUT_TTGR(port, rs485conf->delay_rts_after_send);
267 mode |= ATMEL_US_USMODE_RS485;
268 } else {
269 dev_dbg(port->dev, "Setting UART to RS232\n");
270 if (atmel_use_pdc_tx(port))
271 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
272 ATMEL_US_TXBUFE;
273 else
274 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
275 }
276 UART_PUT_MR(port, mode);
277
278 /* Enable interrupts */
279 UART_PUT_IER(port, atmel_port->tx_done_mask);
280
281 spin_unlock_irqrestore(&port->lock, flags);
282
283 }
284
285 /*
286 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
287 */
288 static u_int atmel_tx_empty(struct uart_port *port)
289 {
290 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0;
291 }
292
293 /*
294 * Set state of the modem control output lines
295 */
296 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
297 {
298 unsigned int control = 0;
299 unsigned int mode;
300 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
301
302 /*
303 * AT91RM9200 Errata #39: RTS0 is not internally connected
304 * to PA21. We need to drive the pin as a GPIO.
305 */
306 if (gpio_is_valid(atmel_port->rts_gpio)) {
307 if (mctrl & TIOCM_RTS)
308 gpio_set_value(atmel_port->rts_gpio, 0);
309 else
310 gpio_set_value(atmel_port->rts_gpio, 1);
311 }
312
313 if (mctrl & TIOCM_RTS)
314 control |= ATMEL_US_RTSEN;
315 else
316 control |= ATMEL_US_RTSDIS;
317
318 if (mctrl & TIOCM_DTR)
319 control |= ATMEL_US_DTREN;
320 else
321 control |= ATMEL_US_DTRDIS;
322
323 UART_PUT_CR(port, control);
324
325 /* Local loopback mode? */
326 mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE;
327 if (mctrl & TIOCM_LOOP)
328 mode |= ATMEL_US_CHMODE_LOC_LOOP;
329 else
330 mode |= ATMEL_US_CHMODE_NORMAL;
331
332 /* Resetting serial mode to RS232 (0x0) */
333 mode &= ~ATMEL_US_USMODE;
334
335 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
336 dev_dbg(port->dev, "Setting UART to RS485\n");
337 if ((atmel_port->rs485.delay_rts_after_send) > 0)
338 UART_PUT_TTGR(port,
339 atmel_port->rs485.delay_rts_after_send);
340 mode |= ATMEL_US_USMODE_RS485;
341 } else {
342 dev_dbg(port->dev, "Setting UART to RS232\n");
343 }
344 UART_PUT_MR(port, mode);
345 }
346
347 /*
348 * Get state of the modem control input lines
349 */
350 static u_int atmel_get_mctrl(struct uart_port *port)
351 {
352 unsigned int status, ret = 0;
353
354 status = UART_GET_CSR(port);
355
356 /*
357 * The control signals are active low.
358 */
359 if (!(status & ATMEL_US_DCD))
360 ret |= TIOCM_CD;
361 if (!(status & ATMEL_US_CTS))
362 ret |= TIOCM_CTS;
363 if (!(status & ATMEL_US_DSR))
364 ret |= TIOCM_DSR;
365 if (!(status & ATMEL_US_RI))
366 ret |= TIOCM_RI;
367
368 return ret;
369 }
370
371 /*
372 * Stop transmitting.
373 */
374 static void atmel_stop_tx(struct uart_port *port)
375 {
376 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
377
378 if (atmel_use_pdc_tx(port)) {
379 /* disable PDC transmit */
380 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
381 }
382 /* Disable interrupts */
383 UART_PUT_IDR(port, atmel_port->tx_done_mask);
384
385 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) &&
386 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX))
387 atmel_start_rx(port);
388 }
389
390 /*
391 * Start transmitting.
392 */
393 static void atmel_start_tx(struct uart_port *port)
394 {
395 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
396
397 if (atmel_use_pdc_tx(port)) {
398 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN)
399 /* The transmitter is already running. Yes, we
400 really need this.*/
401 return;
402
403 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) &&
404 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX))
405 atmel_stop_rx(port);
406
407 /* re-enable PDC transmit */
408 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
409 }
410 /* Enable interrupts */
411 UART_PUT_IER(port, atmel_port->tx_done_mask);
412 }
413
414 /*
415 * start receiving - port is in process of being opened.
416 */
417 static void atmel_start_rx(struct uart_port *port)
418 {
419 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */
420
421 UART_PUT_CR(port, ATMEL_US_RXEN);
422
423 if (atmel_use_pdc_rx(port)) {
424 /* enable PDC controller */
425 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
426 port->read_status_mask);
427 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
428 } else {
429 UART_PUT_IER(port, ATMEL_US_RXRDY);
430 }
431 }
432
433 /*
434 * Stop receiving - port is in process of being closed.
435 */
436 static void atmel_stop_rx(struct uart_port *port)
437 {
438 UART_PUT_CR(port, ATMEL_US_RXDIS);
439
440 if (atmel_use_pdc_rx(port)) {
441 /* disable PDC receive */
442 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);
443 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
444 port->read_status_mask);
445 } else {
446 UART_PUT_IDR(port, ATMEL_US_RXRDY);
447 }
448 }
449
450 /*
451 * Enable modem status interrupts
452 */
453 static void atmel_enable_ms(struct uart_port *port)
454 {
455 UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC
456 | ATMEL_US_DCDIC | ATMEL_US_CTSIC);
457 }
458
459 /*
460 * Control the transmission of a break signal
461 */
462 static void atmel_break_ctl(struct uart_port *port, int break_state)
463 {
464 if (break_state != 0)
465 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */
466 else
467 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */
468 }
469
470 /*
471 * Stores the incoming character in the ring buffer
472 */
473 static void
474 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
475 unsigned int ch)
476 {
477 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
478 struct circ_buf *ring = &atmel_port->rx_ring;
479 struct atmel_uart_char *c;
480
481 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
482 /* Buffer overflow, ignore char */
483 return;
484
485 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
486 c->status = status;
487 c->ch = ch;
488
489 /* Make sure the character is stored before we update head. */
490 smp_wmb();
491
492 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
493 }
494
495 /*
496 * Deal with parity, framing and overrun errors.
497 */
498 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
499 {
500 /* clear error */
501 UART_PUT_CR(port, ATMEL_US_RSTSTA);
502
503 if (status & ATMEL_US_RXBRK) {
504 /* ignore side-effect */
505 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
506 port->icount.brk++;
507 }
508 if (status & ATMEL_US_PARE)
509 port->icount.parity++;
510 if (status & ATMEL_US_FRAME)
511 port->icount.frame++;
512 if (status & ATMEL_US_OVRE)
513 port->icount.overrun++;
514 }
515
516 /*
517 * Characters received (called from interrupt handler)
518 */
519 static void atmel_rx_chars(struct uart_port *port)
520 {
521 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
522 unsigned int status, ch;
523
524 status = UART_GET_CSR(port);
525 while (status & ATMEL_US_RXRDY) {
526 ch = UART_GET_CHAR(port);
527
528 /*
529 * note that the error handling code is
530 * out of the main execution path
531 */
532 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
533 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
534 || atmel_port->break_active)) {
535
536 /* clear error */
537 UART_PUT_CR(port, ATMEL_US_RSTSTA);
538
539 if (status & ATMEL_US_RXBRK
540 && !atmel_port->break_active) {
541 atmel_port->break_active = 1;
542 UART_PUT_IER(port, ATMEL_US_RXBRK);
543 } else {
544 /*
545 * This is either the end-of-break
546 * condition or we've received at
547 * least one character without RXBRK
548 * being set. In both cases, the next
549 * RXBRK will indicate start-of-break.
550 */
551 UART_PUT_IDR(port, ATMEL_US_RXBRK);
552 status &= ~ATMEL_US_RXBRK;
553 atmel_port->break_active = 0;
554 }
555 }
556
557 atmel_buffer_rx_char(port, status, ch);
558 status = UART_GET_CSR(port);
559 }
560
561 tasklet_schedule(&atmel_port->tasklet);
562 }
563
564 /*
565 * Transmit characters (called from tasklet with TXRDY interrupt
566 * disabled)
567 */
568 static void atmel_tx_chars(struct uart_port *port)
569 {
570 struct circ_buf *xmit = &port->state->xmit;
571 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
572
573 if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) {
574 UART_PUT_CHAR(port, port->x_char);
575 port->icount.tx++;
576 port->x_char = 0;
577 }
578 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
579 return;
580
581 while (UART_GET_CSR(port) & atmel_port->tx_done_mask) {
582 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
583 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
584 port->icount.tx++;
585 if (uart_circ_empty(xmit))
586 break;
587 }
588
589 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
590 uart_write_wakeup(port);
591
592 if (!uart_circ_empty(xmit))
593 /* Enable interrupts */
594 UART_PUT_IER(port, atmel_port->tx_done_mask);
595 }
596
597 static void atmel_complete_tx_dma(void *arg)
598 {
599 struct atmel_uart_port *atmel_port = arg;
600 struct uart_port *port = &atmel_port->uart;
601 struct circ_buf *xmit = &port->state->xmit;
602 struct dma_chan *chan = atmel_port->chan_tx;
603 unsigned long flags;
604
605 spin_lock_irqsave(&port->lock, flags);
606
607 if (chan)
608 dmaengine_terminate_all(chan);
609 xmit->tail += sg_dma_len(&atmel_port->sg_tx);
610 xmit->tail &= UART_XMIT_SIZE - 1;
611
612 port->icount.tx += sg_dma_len(&atmel_port->sg_tx);
613
614 spin_lock_irq(&atmel_port->lock_tx);
615 async_tx_ack(atmel_port->desc_tx);
616 atmel_port->cookie_tx = -EINVAL;
617 atmel_port->desc_tx = NULL;
618 spin_unlock_irq(&atmel_port->lock_tx);
619
620 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
621 uart_write_wakeup(port);
622
623 /* Do we really need this? */
624 if (!uart_circ_empty(xmit))
625 tasklet_schedule(&atmel_port->tasklet);
626
627 spin_unlock_irqrestore(&port->lock, flags);
628 }
629
630 static void atmel_release_tx_dma(struct uart_port *port)
631 {
632 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
633 struct dma_chan *chan = atmel_port->chan_tx;
634
635 if (chan) {
636 dmaengine_terminate_all(chan);
637 dma_release_channel(chan);
638 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
639 DMA_MEM_TO_DEV);
640 }
641
642 atmel_port->desc_tx = NULL;
643 atmel_port->chan_tx = NULL;
644 atmel_port->cookie_tx = -EINVAL;
645 }
646
647 /*
648 * Called from tasklet with TXRDY interrupt is disabled.
649 */
650 static void atmel_tx_dma(struct uart_port *port)
651 {
652 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
653 struct circ_buf *xmit = &port->state->xmit;
654 struct dma_chan *chan = atmel_port->chan_tx;
655 struct dma_async_tx_descriptor *desc;
656 struct scatterlist *sg = &atmel_port->sg_tx;
657
658 /* Make sure we have an idle channel */
659 if (atmel_port->desc_tx != NULL)
660 return;
661
662 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
663 /*
664 * DMA is idle now.
665 * Port xmit buffer is already mapped,
666 * and it is one page... Just adjust
667 * offsets and lengths. Since it is a circular buffer,
668 * we have to transmit till the end, and then the rest.
669 * Take the port lock to get a
670 * consistent xmit buffer state.
671 */
672 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
673 sg_dma_address(sg) = (sg_dma_address(sg) &
674 ~(UART_XMIT_SIZE - 1))
675 + sg->offset;
676 sg_dma_len(sg) = CIRC_CNT_TO_END(xmit->head,
677 xmit->tail,
678 UART_XMIT_SIZE);
679 BUG_ON(!sg_dma_len(sg));
680
681 desc = dmaengine_prep_slave_sg(chan,
682 sg,
683 1,
684 DMA_MEM_TO_DEV,
685 DMA_PREP_INTERRUPT |
686 DMA_CTRL_ACK);
687 if (!desc) {
688 dev_err(port->dev, "Failed to send via dma!\n");
689 return;
690 }
691
692 dma_sync_sg_for_device(port->dev, sg, 1, DMA_MEM_TO_DEV);
693
694 atmel_port->desc_tx = desc;
695 desc->callback = atmel_complete_tx_dma;
696 desc->callback_param = atmel_port;
697 atmel_port->cookie_tx = dmaengine_submit(desc);
698
699 } else {
700 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
701 /* DMA done, stop TX, start RX for RS485 */
702 atmel_start_rx(port);
703 }
704 }
705
706 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
707 uart_write_wakeup(port);
708 }
709
710 static int atmel_prepare_tx_dma(struct uart_port *port)
711 {
712 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
713 dma_cap_mask_t mask;
714 struct dma_slave_config config;
715 int ret, nent;
716
717 dma_cap_zero(mask);
718 dma_cap_set(DMA_SLAVE, mask);
719
720 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
721 if (atmel_port->chan_tx == NULL)
722 goto chan_err;
723 dev_info(port->dev, "using %s for tx DMA transfers\n",
724 dma_chan_name(atmel_port->chan_tx));
725
726 spin_lock_init(&atmel_port->lock_tx);
727 sg_init_table(&atmel_port->sg_tx, 1);
728 /* UART circular tx buffer is an aligned page. */
729 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
730 sg_set_page(&atmel_port->sg_tx,
731 virt_to_page(port->state->xmit.buf),
732 UART_XMIT_SIZE,
733 (int)port->state->xmit.buf & ~PAGE_MASK);
734 nent = dma_map_sg(port->dev,
735 &atmel_port->sg_tx,
736 1,
737 DMA_MEM_TO_DEV);
738
739 if (!nent) {
740 dev_dbg(port->dev, "need to release resource of dma\n");
741 goto chan_err;
742 } else {
743 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
744 sg_dma_len(&atmel_port->sg_tx),
745 port->state->xmit.buf,
746 sg_dma_address(&atmel_port->sg_tx));
747 }
748
749 /* Configure the slave DMA */
750 memset(&config, 0, sizeof(config));
751 config.direction = DMA_MEM_TO_DEV;
752 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
753 config.dst_addr = port->mapbase + ATMEL_US_THR;
754
755 ret = dmaengine_device_control(atmel_port->chan_tx,
756 DMA_SLAVE_CONFIG,
757 (unsigned long)&config);
758 if (ret) {
759 dev_err(port->dev, "DMA tx slave configuration failed\n");
760 goto chan_err;
761 }
762
763 return 0;
764
765 chan_err:
766 dev_err(port->dev, "TX channel not available, switch to pio\n");
767 atmel_port->use_dma_tx = 0;
768 if (atmel_port->chan_tx)
769 atmel_release_tx_dma(port);
770 return -EINVAL;
771 }
772
773 static void atmel_flip_buffer_rx_dma(struct uart_port *port,
774 char *buf, size_t count)
775 {
776 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
777 struct tty_port *tport = &port->state->port;
778
779 dma_sync_sg_for_cpu(port->dev,
780 &atmel_port->sg_rx,
781 1,
782 DMA_DEV_TO_MEM);
783
784 tty_insert_flip_string(tport, buf, count);
785
786 dma_sync_sg_for_device(port->dev,
787 &atmel_port->sg_rx,
788 1,
789 DMA_DEV_TO_MEM);
790 /*
791 * Drop the lock here since it might end up calling
792 * uart_start(), which takes the lock.
793 */
794 spin_unlock(&port->lock);
795 tty_flip_buffer_push(tport);
796 spin_lock(&port->lock);
797 }
798
799 static void atmel_complete_rx_dma(void *arg)
800 {
801 struct uart_port *port = arg;
802 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
803
804 tasklet_schedule(&atmel_port->tasklet);
805 }
806
807 static void atmel_release_rx_dma(struct uart_port *port)
808 {
809 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
810 struct dma_chan *chan = atmel_port->chan_rx;
811
812 if (chan) {
813 dmaengine_terminate_all(chan);
814 dma_release_channel(chan);
815 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
816 DMA_DEV_TO_MEM);
817 }
818
819 atmel_port->desc_rx = NULL;
820 atmel_port->chan_rx = NULL;
821 atmel_port->cookie_rx = -EINVAL;
822 }
823
824 static void atmel_rx_from_dma(struct uart_port *port)
825 {
826 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
827 struct circ_buf *ring = &atmel_port->rx_ring;
828 struct dma_chan *chan = atmel_port->chan_rx;
829 struct dma_tx_state state;
830 enum dma_status dmastat;
831 size_t pending, count;
832
833
834 /* Reset the UART timeout early so that we don't miss one */
835 UART_PUT_CR(port, ATMEL_US_STTTO);
836 dmastat = dmaengine_tx_status(chan,
837 atmel_port->cookie_rx,
838 &state);
839 /* Restart a new tasklet if DMA status is error */
840 if (dmastat == DMA_ERROR) {
841 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
842 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
843 tasklet_schedule(&atmel_port->tasklet);
844 return;
845 }
846 /* current transfer size should no larger than dma buffer */
847 pending = sg_dma_len(&atmel_port->sg_rx) - state.residue;
848 BUG_ON(pending > sg_dma_len(&atmel_port->sg_rx));
849
850 /*
851 * This will take the chars we have so far,
852 * ring->head will record the transfer size, only new bytes come
853 * will insert into the framework.
854 */
855 if (pending > ring->head) {
856 count = pending - ring->head;
857
858 atmel_flip_buffer_rx_dma(port, ring->buf + ring->head, count);
859
860 ring->head += count;
861 if (ring->head == sg_dma_len(&atmel_port->sg_rx))
862 ring->head = 0;
863
864 port->icount.rx += count;
865 }
866
867 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
868 }
869
870 static int atmel_prepare_rx_dma(struct uart_port *port)
871 {
872 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
873 struct dma_async_tx_descriptor *desc;
874 dma_cap_mask_t mask;
875 struct dma_slave_config config;
876 struct circ_buf *ring;
877 int ret, nent;
878
879 ring = &atmel_port->rx_ring;
880
881 dma_cap_zero(mask);
882 dma_cap_set(DMA_CYCLIC, mask);
883
884 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
885 if (atmel_port->chan_rx == NULL)
886 goto chan_err;
887 dev_info(port->dev, "using %s for rx DMA transfers\n",
888 dma_chan_name(atmel_port->chan_rx));
889
890 spin_lock_init(&atmel_port->lock_rx);
891 sg_init_table(&atmel_port->sg_rx, 1);
892 /* UART circular rx buffer is an aligned page. */
893 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
894 sg_set_page(&atmel_port->sg_rx,
895 virt_to_page(ring->buf),
896 ATMEL_SERIAL_RINGSIZE,
897 (int)ring->buf & ~PAGE_MASK);
898 nent = dma_map_sg(port->dev,
899 &atmel_port->sg_rx,
900 1,
901 DMA_DEV_TO_MEM);
902
903 if (!nent) {
904 dev_dbg(port->dev, "need to release resource of dma\n");
905 goto chan_err;
906 } else {
907 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
908 sg_dma_len(&atmel_port->sg_rx),
909 ring->buf,
910 sg_dma_address(&atmel_port->sg_rx));
911 }
912
913 /* Configure the slave DMA */
914 memset(&config, 0, sizeof(config));
915 config.direction = DMA_DEV_TO_MEM;
916 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
917 config.src_addr = port->mapbase + ATMEL_US_RHR;
918
919 ret = dmaengine_device_control(atmel_port->chan_rx,
920 DMA_SLAVE_CONFIG,
921 (unsigned long)&config);
922 if (ret) {
923 dev_err(port->dev, "DMA rx slave configuration failed\n");
924 goto chan_err;
925 }
926 /*
927 * Prepare a cyclic dma transfer, assign 2 descriptors,
928 * each one is half ring buffer size
929 */
930 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
931 sg_dma_address(&atmel_port->sg_rx),
932 sg_dma_len(&atmel_port->sg_rx),
933 sg_dma_len(&atmel_port->sg_rx)/2,
934 DMA_DEV_TO_MEM,
935 DMA_PREP_INTERRUPT);
936 desc->callback = atmel_complete_rx_dma;
937 desc->callback_param = port;
938 atmel_port->desc_rx = desc;
939 atmel_port->cookie_rx = dmaengine_submit(desc);
940
941 return 0;
942
943 chan_err:
944 dev_err(port->dev, "RX channel not available, switch to pio\n");
945 atmel_port->use_dma_rx = 0;
946 if (atmel_port->chan_rx)
947 atmel_release_rx_dma(port);
948 return -EINVAL;
949 }
950
951 static void atmel_uart_timer_callback(unsigned long data)
952 {
953 struct uart_port *port = (void *)data;
954 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
955
956 tasklet_schedule(&atmel_port->tasklet);
957 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port));
958 }
959
960 /*
961 * receive interrupt handler.
962 */
963 static void
964 atmel_handle_receive(struct uart_port *port, unsigned int pending)
965 {
966 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
967
968 if (atmel_use_pdc_rx(port)) {
969 /*
970 * PDC receive. Just schedule the tasklet and let it
971 * figure out the details.
972 *
973 * TODO: We're not handling error flags correctly at
974 * the moment.
975 */
976 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
977 UART_PUT_IDR(port, (ATMEL_US_ENDRX
978 | ATMEL_US_TIMEOUT));
979 tasklet_schedule(&atmel_port->tasklet);
980 }
981
982 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
983 ATMEL_US_FRAME | ATMEL_US_PARE))
984 atmel_pdc_rxerr(port, pending);
985 }
986
987 if (atmel_use_dma_rx(port)) {
988 if (pending & ATMEL_US_TIMEOUT) {
989 UART_PUT_IDR(port, ATMEL_US_TIMEOUT);
990 tasklet_schedule(&atmel_port->tasklet);
991 }
992 }
993
994 /* Interrupt receive */
995 if (pending & ATMEL_US_RXRDY)
996 atmel_rx_chars(port);
997 else if (pending & ATMEL_US_RXBRK) {
998 /*
999 * End of break detected. If it came along with a
1000 * character, atmel_rx_chars will handle it.
1001 */
1002 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1003 UART_PUT_IDR(port, ATMEL_US_RXBRK);
1004 atmel_port->break_active = 0;
1005 }
1006 }
1007
1008 /*
1009 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1010 */
1011 static void
1012 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1013 {
1014 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1015
1016 if (pending & atmel_port->tx_done_mask) {
1017 /* Either PDC or interrupt transmission */
1018 UART_PUT_IDR(port, atmel_port->tx_done_mask);
1019 tasklet_schedule(&atmel_port->tasklet);
1020 }
1021 }
1022
1023 /*
1024 * status flags interrupt handler.
1025 */
1026 static void
1027 atmel_handle_status(struct uart_port *port, unsigned int pending,
1028 unsigned int status)
1029 {
1030 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1031
1032 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1033 | ATMEL_US_CTSIC)) {
1034 atmel_port->irq_status = status;
1035 tasklet_schedule(&atmel_port->tasklet);
1036 }
1037 }
1038
1039 /*
1040 * Interrupt handler
1041 */
1042 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1043 {
1044 struct uart_port *port = dev_id;
1045 unsigned int status, pending, pass_counter = 0;
1046
1047 do {
1048 status = UART_GET_CSR(port);
1049 pending = status & UART_GET_IMR(port);
1050 if (!pending)
1051 break;
1052
1053 atmel_handle_receive(port, pending);
1054 atmel_handle_status(port, pending, status);
1055 atmel_handle_transmit(port, pending);
1056 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1057
1058 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1059 }
1060
1061 static void atmel_release_tx_pdc(struct uart_port *port)
1062 {
1063 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1064 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1065
1066 dma_unmap_single(port->dev,
1067 pdc->dma_addr,
1068 pdc->dma_size,
1069 DMA_TO_DEVICE);
1070 }
1071
1072 /*
1073 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1074 */
1075 static void atmel_tx_pdc(struct uart_port *port)
1076 {
1077 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1078 struct circ_buf *xmit = &port->state->xmit;
1079 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1080 int count;
1081
1082 /* nothing left to transmit? */
1083 if (UART_GET_TCR(port))
1084 return;
1085
1086 xmit->tail += pdc->ofs;
1087 xmit->tail &= UART_XMIT_SIZE - 1;
1088
1089 port->icount.tx += pdc->ofs;
1090 pdc->ofs = 0;
1091
1092 /* more to transmit - setup next transfer */
1093
1094 /* disable PDC transmit */
1095 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
1096
1097 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1098 dma_sync_single_for_device(port->dev,
1099 pdc->dma_addr,
1100 pdc->dma_size,
1101 DMA_TO_DEVICE);
1102
1103 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1104 pdc->ofs = count;
1105
1106 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
1107 UART_PUT_TCR(port, count);
1108 /* re-enable PDC transmit */
1109 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
1110 /* Enable interrupts */
1111 UART_PUT_IER(port, atmel_port->tx_done_mask);
1112 } else {
1113 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) &&
1114 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) {
1115 /* DMA done, stop TX, start RX for RS485 */
1116 atmel_start_rx(port);
1117 }
1118 }
1119
1120 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1121 uart_write_wakeup(port);
1122 }
1123
1124 static int atmel_prepare_tx_pdc(struct uart_port *port)
1125 {
1126 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1127 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1128 struct circ_buf *xmit = &port->state->xmit;
1129
1130 pdc->buf = xmit->buf;
1131 pdc->dma_addr = dma_map_single(port->dev,
1132 pdc->buf,
1133 UART_XMIT_SIZE,
1134 DMA_TO_DEVICE);
1135 pdc->dma_size = UART_XMIT_SIZE;
1136 pdc->ofs = 0;
1137
1138 return 0;
1139 }
1140
1141 static void atmel_rx_from_ring(struct uart_port *port)
1142 {
1143 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1144 struct circ_buf *ring = &atmel_port->rx_ring;
1145 unsigned int flg;
1146 unsigned int status;
1147
1148 while (ring->head != ring->tail) {
1149 struct atmel_uart_char c;
1150
1151 /* Make sure c is loaded after head. */
1152 smp_rmb();
1153
1154 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1155
1156 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1157
1158 port->icount.rx++;
1159 status = c.status;
1160 flg = TTY_NORMAL;
1161
1162 /*
1163 * note that the error handling code is
1164 * out of the main execution path
1165 */
1166 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1167 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1168 if (status & ATMEL_US_RXBRK) {
1169 /* ignore side-effect */
1170 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1171
1172 port->icount.brk++;
1173 if (uart_handle_break(port))
1174 continue;
1175 }
1176 if (status & ATMEL_US_PARE)
1177 port->icount.parity++;
1178 if (status & ATMEL_US_FRAME)
1179 port->icount.frame++;
1180 if (status & ATMEL_US_OVRE)
1181 port->icount.overrun++;
1182
1183 status &= port->read_status_mask;
1184
1185 if (status & ATMEL_US_RXBRK)
1186 flg = TTY_BREAK;
1187 else if (status & ATMEL_US_PARE)
1188 flg = TTY_PARITY;
1189 else if (status & ATMEL_US_FRAME)
1190 flg = TTY_FRAME;
1191 }
1192
1193
1194 if (uart_handle_sysrq_char(port, c.ch))
1195 continue;
1196
1197 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1198 }
1199
1200 /*
1201 * Drop the lock here since it might end up calling
1202 * uart_start(), which takes the lock.
1203 */
1204 spin_unlock(&port->lock);
1205 tty_flip_buffer_push(&port->state->port);
1206 spin_lock(&port->lock);
1207 }
1208
1209 static void atmel_release_rx_pdc(struct uart_port *port)
1210 {
1211 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1212 int i;
1213
1214 for (i = 0; i < 2; i++) {
1215 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1216
1217 dma_unmap_single(port->dev,
1218 pdc->dma_addr,
1219 pdc->dma_size,
1220 DMA_FROM_DEVICE);
1221 kfree(pdc->buf);
1222 }
1223 }
1224
1225 static void atmel_rx_from_pdc(struct uart_port *port)
1226 {
1227 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1228 struct tty_port *tport = &port->state->port;
1229 struct atmel_dma_buffer *pdc;
1230 int rx_idx = atmel_port->pdc_rx_idx;
1231 unsigned int head;
1232 unsigned int tail;
1233 unsigned int count;
1234
1235 do {
1236 /* Reset the UART timeout early so that we don't miss one */
1237 UART_PUT_CR(port, ATMEL_US_STTTO);
1238
1239 pdc = &atmel_port->pdc_rx[rx_idx];
1240 head = UART_GET_RPR(port) - pdc->dma_addr;
1241 tail = pdc->ofs;
1242
1243 /* If the PDC has switched buffers, RPR won't contain
1244 * any address within the current buffer. Since head
1245 * is unsigned, we just need a one-way comparison to
1246 * find out.
1247 *
1248 * In this case, we just need to consume the entire
1249 * buffer and resubmit it for DMA. This will clear the
1250 * ENDRX bit as well, so that we can safely re-enable
1251 * all interrupts below.
1252 */
1253 head = min(head, pdc->dma_size);
1254
1255 if (likely(head != tail)) {
1256 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1257 pdc->dma_size, DMA_FROM_DEVICE);
1258
1259 /*
1260 * head will only wrap around when we recycle
1261 * the DMA buffer, and when that happens, we
1262 * explicitly set tail to 0. So head will
1263 * always be greater than tail.
1264 */
1265 count = head - tail;
1266
1267 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1268 count);
1269
1270 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1271 pdc->dma_size, DMA_FROM_DEVICE);
1272
1273 port->icount.rx += count;
1274 pdc->ofs = head;
1275 }
1276
1277 /*
1278 * If the current buffer is full, we need to check if
1279 * the next one contains any additional data.
1280 */
1281 if (head >= pdc->dma_size) {
1282 pdc->ofs = 0;
1283 UART_PUT_RNPR(port, pdc->dma_addr);
1284 UART_PUT_RNCR(port, pdc->dma_size);
1285
1286 rx_idx = !rx_idx;
1287 atmel_port->pdc_rx_idx = rx_idx;
1288 }
1289 } while (head >= pdc->dma_size);
1290
1291 /*
1292 * Drop the lock here since it might end up calling
1293 * uart_start(), which takes the lock.
1294 */
1295 spin_unlock(&port->lock);
1296 tty_flip_buffer_push(tport);
1297 spin_lock(&port->lock);
1298
1299 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1300 }
1301
1302 static int atmel_prepare_rx_pdc(struct uart_port *port)
1303 {
1304 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1305 int i;
1306
1307 for (i = 0; i < 2; i++) {
1308 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1309
1310 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1311 if (pdc->buf == NULL) {
1312 if (i != 0) {
1313 dma_unmap_single(port->dev,
1314 atmel_port->pdc_rx[0].dma_addr,
1315 PDC_BUFFER_SIZE,
1316 DMA_FROM_DEVICE);
1317 kfree(atmel_port->pdc_rx[0].buf);
1318 }
1319 atmel_port->use_pdc_rx = 0;
1320 return -ENOMEM;
1321 }
1322 pdc->dma_addr = dma_map_single(port->dev,
1323 pdc->buf,
1324 PDC_BUFFER_SIZE,
1325 DMA_FROM_DEVICE);
1326 pdc->dma_size = PDC_BUFFER_SIZE;
1327 pdc->ofs = 0;
1328 }
1329
1330 atmel_port->pdc_rx_idx = 0;
1331
1332 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
1333 UART_PUT_RCR(port, PDC_BUFFER_SIZE);
1334
1335 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
1336 UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
1337
1338 return 0;
1339 }
1340
1341 /*
1342 * tasklet handling tty stuff outside the interrupt handler.
1343 */
1344 static void atmel_tasklet_func(unsigned long data)
1345 {
1346 struct uart_port *port = (struct uart_port *)data;
1347 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1348 unsigned int status;
1349 unsigned int status_change;
1350
1351 /* The interrupt handler does not take the lock */
1352 spin_lock(&port->lock);
1353
1354 atmel_port->schedule_tx(port);
1355
1356 status = atmel_port->irq_status;
1357 status_change = status ^ atmel_port->irq_status_prev;
1358
1359 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1360 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1361 /* TODO: All reads to CSR will clear these interrupts! */
1362 if (status_change & ATMEL_US_RI)
1363 port->icount.rng++;
1364 if (status_change & ATMEL_US_DSR)
1365 port->icount.dsr++;
1366 if (status_change & ATMEL_US_DCD)
1367 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1368 if (status_change & ATMEL_US_CTS)
1369 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1370
1371 wake_up_interruptible(&port->state->port.delta_msr_wait);
1372
1373 atmel_port->irq_status_prev = status;
1374 }
1375
1376 atmel_port->schedule_rx(port);
1377
1378 spin_unlock(&port->lock);
1379 }
1380
1381 static int atmel_init_property(struct atmel_uart_port *atmel_port,
1382 struct platform_device *pdev)
1383 {
1384 struct device_node *np = pdev->dev.of_node;
1385 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1386
1387 if (np) {
1388 /* DMA/PDC usage specification */
1389 if (of_get_property(np, "atmel,use-dma-rx", NULL)) {
1390 if (of_get_property(np, "dmas", NULL)) {
1391 atmel_port->use_dma_rx = true;
1392 atmel_port->use_pdc_rx = false;
1393 } else {
1394 atmel_port->use_dma_rx = false;
1395 atmel_port->use_pdc_rx = true;
1396 }
1397 } else {
1398 atmel_port->use_dma_rx = false;
1399 atmel_port->use_pdc_rx = false;
1400 }
1401
1402 if (of_get_property(np, "atmel,use-dma-tx", NULL)) {
1403 if (of_get_property(np, "dmas", NULL)) {
1404 atmel_port->use_dma_tx = true;
1405 atmel_port->use_pdc_tx = false;
1406 } else {
1407 atmel_port->use_dma_tx = false;
1408 atmel_port->use_pdc_tx = true;
1409 }
1410 } else {
1411 atmel_port->use_dma_tx = false;
1412 atmel_port->use_pdc_tx = false;
1413 }
1414
1415 } else {
1416 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1417 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1418 atmel_port->use_dma_rx = false;
1419 atmel_port->use_dma_tx = false;
1420 }
1421
1422 return 0;
1423 }
1424
1425 static void atmel_init_rs485(struct atmel_uart_port *atmel_port,
1426 struct platform_device *pdev)
1427 {
1428 struct device_node *np = pdev->dev.of_node;
1429 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1430
1431 if (np) {
1432 u32 rs485_delay[2];
1433 /* rs485 properties */
1434 if (of_property_read_u32_array(np, "rs485-rts-delay",
1435 rs485_delay, 2) == 0) {
1436 struct serial_rs485 *rs485conf = &atmel_port->rs485;
1437
1438 rs485conf->delay_rts_before_send = rs485_delay[0];
1439 rs485conf->delay_rts_after_send = rs485_delay[1];
1440 rs485conf->flags = 0;
1441
1442 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1443 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1444
1445 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1446 NULL))
1447 rs485conf->flags |= SER_RS485_ENABLED;
1448 }
1449 } else {
1450 atmel_port->rs485 = pdata->rs485;
1451 }
1452
1453 }
1454
1455 static void atmel_set_ops(struct uart_port *port)
1456 {
1457 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1458
1459 if (atmel_use_dma_rx(port)) {
1460 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1461 atmel_port->schedule_rx = &atmel_rx_from_dma;
1462 atmel_port->release_rx = &atmel_release_rx_dma;
1463 } else if (atmel_use_pdc_rx(port)) {
1464 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1465 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1466 atmel_port->release_rx = &atmel_release_rx_pdc;
1467 } else {
1468 atmel_port->prepare_rx = NULL;
1469 atmel_port->schedule_rx = &atmel_rx_from_ring;
1470 atmel_port->release_rx = NULL;
1471 }
1472
1473 if (atmel_use_dma_tx(port)) {
1474 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1475 atmel_port->schedule_tx = &atmel_tx_dma;
1476 atmel_port->release_tx = &atmel_release_tx_dma;
1477 } else if (atmel_use_pdc_tx(port)) {
1478 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1479 atmel_port->schedule_tx = &atmel_tx_pdc;
1480 atmel_port->release_tx = &atmel_release_tx_pdc;
1481 } else {
1482 atmel_port->prepare_tx = NULL;
1483 atmel_port->schedule_tx = &atmel_tx_chars;
1484 atmel_port->release_tx = NULL;
1485 }
1486 }
1487
1488 /*
1489 * Get ip name usart or uart
1490 */
1491 static void atmel_get_ip_name(struct uart_port *port)
1492 {
1493 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1494 int name = UART_GET_IP_NAME(port);
1495 u32 version;
1496 int usart, uart;
1497 /* usart and uart ascii */
1498 usart = 0x55534152;
1499 uart = 0x44424755;
1500
1501 atmel_port->is_usart = false;
1502
1503 if (name == usart) {
1504 dev_dbg(port->dev, "This is usart\n");
1505 atmel_port->is_usart = true;
1506 } else if (name == uart) {
1507 dev_dbg(port->dev, "This is uart\n");
1508 atmel_port->is_usart = false;
1509 } else {
1510 /* fallback for older SoCs: use version field */
1511 version = UART_GET_IP_VERSION(port);
1512 switch (version) {
1513 case 0x302:
1514 case 0x10213:
1515 dev_dbg(port->dev, "This version is usart\n");
1516 atmel_port->is_usart = true;
1517 break;
1518 case 0x203:
1519 case 0x10202:
1520 dev_dbg(port->dev, "This version is uart\n");
1521 atmel_port->is_usart = false;
1522 break;
1523 default:
1524 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1525 }
1526 }
1527 }
1528
1529 /*
1530 * Perform initialization and enable port for reception
1531 */
1532 static int atmel_startup(struct uart_port *port)
1533 {
1534 struct platform_device *pdev = to_platform_device(port->dev);
1535 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1536 struct tty_struct *tty = port->state->port.tty;
1537 int retval;
1538
1539 /*
1540 * Ensure that no interrupts are enabled otherwise when
1541 * request_irq() is called we could get stuck trying to
1542 * handle an unexpected interrupt
1543 */
1544 UART_PUT_IDR(port, -1);
1545
1546 /*
1547 * Allocate the IRQ
1548 */
1549 retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED,
1550 tty ? tty->name : "atmel_serial", port);
1551 if (retval) {
1552 printk("atmel_serial: atmel_startup - Can't get irq\n");
1553 return retval;
1554 }
1555
1556 /*
1557 * Initialize DMA (if necessary)
1558 */
1559 atmel_init_property(atmel_port, pdev);
1560
1561 if (atmel_port->prepare_rx) {
1562 retval = atmel_port->prepare_rx(port);
1563 if (retval < 0)
1564 atmel_set_ops(port);
1565 }
1566
1567 if (atmel_port->prepare_tx) {
1568 retval = atmel_port->prepare_tx(port);
1569 if (retval < 0)
1570 atmel_set_ops(port);
1571 }
1572 /*
1573 * If there is a specific "open" function (to register
1574 * control line interrupts)
1575 */
1576 if (atmel_open_hook) {
1577 retval = atmel_open_hook(port);
1578 if (retval) {
1579 free_irq(port->irq, port);
1580 return retval;
1581 }
1582 }
1583
1584 /* Save current CSR for comparison in atmel_tasklet_func() */
1585 atmel_port->irq_status_prev = UART_GET_CSR(port);
1586 atmel_port->irq_status = atmel_port->irq_status_prev;
1587
1588 /*
1589 * Finally, enable the serial port
1590 */
1591 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1592 /* enable xmit & rcvr */
1593 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1594
1595 setup_timer(&atmel_port->uart_timer,
1596 atmel_uart_timer_callback,
1597 (unsigned long)port);
1598
1599 if (atmel_use_pdc_rx(port)) {
1600 /* set UART timeout */
1601 if (!atmel_port->is_usart) {
1602 mod_timer(&atmel_port->uart_timer,
1603 jiffies + uart_poll_timeout(port));
1604 /* set USART timeout */
1605 } else {
1606 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
1607 UART_PUT_CR(port, ATMEL_US_STTTO);
1608
1609 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1610 }
1611 /* enable PDC controller */
1612 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
1613 } else if (atmel_use_dma_rx(port)) {
1614 /* set UART timeout */
1615 if (!atmel_port->is_usart) {
1616 mod_timer(&atmel_port->uart_timer,
1617 jiffies + uart_poll_timeout(port));
1618 /* set USART timeout */
1619 } else {
1620 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
1621 UART_PUT_CR(port, ATMEL_US_STTTO);
1622
1623 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
1624 }
1625 } else {
1626 /* enable receive only */
1627 UART_PUT_IER(port, ATMEL_US_RXRDY);
1628 }
1629
1630 return 0;
1631 }
1632
1633 /*
1634 * Disable the port
1635 */
1636 static void atmel_shutdown(struct uart_port *port)
1637 {
1638 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1639
1640 /*
1641 * Prevent any tasklets being scheduled during
1642 * cleanup
1643 */
1644 del_timer_sync(&atmel_port->uart_timer);
1645
1646 /*
1647 * Clear out any scheduled tasklets before
1648 * we destroy the buffers
1649 */
1650 tasklet_kill(&atmel_port->tasklet);
1651
1652 /*
1653 * Ensure everything is stopped and
1654 * disable all interrupts, port and break condition.
1655 */
1656 atmel_stop_rx(port);
1657 atmel_stop_tx(port);
1658
1659 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1660 UART_PUT_IDR(port, -1);
1661
1662
1663 /*
1664 * Shut-down the DMA.
1665 */
1666 if (atmel_port->release_rx)
1667 atmel_port->release_rx(port);
1668 if (atmel_port->release_tx)
1669 atmel_port->release_tx(port);
1670
1671 /*
1672 * Reset ring buffer pointers
1673 */
1674 atmel_port->rx_ring.head = 0;
1675 atmel_port->rx_ring.tail = 0;
1676
1677 /*
1678 * Free the interrupt
1679 */
1680 free_irq(port->irq, port);
1681
1682 /*
1683 * If there is a specific "close" function (to unregister
1684 * control line interrupts)
1685 */
1686 if (atmel_close_hook)
1687 atmel_close_hook(port);
1688 }
1689
1690 /*
1691 * Flush any TX data submitted for DMA. Called when the TX circular
1692 * buffer is reset.
1693 */
1694 static void atmel_flush_buffer(struct uart_port *port)
1695 {
1696 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1697
1698 if (atmel_use_pdc_tx(port)) {
1699 UART_PUT_TCR(port, 0);
1700 atmel_port->pdc_tx.ofs = 0;
1701 }
1702 }
1703
1704 /*
1705 * Power / Clock management.
1706 */
1707 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
1708 unsigned int oldstate)
1709 {
1710 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1711
1712 switch (state) {
1713 case 0:
1714 /*
1715 * Enable the peripheral clock for this serial port.
1716 * This is called on uart_open() or a resume event.
1717 */
1718 clk_prepare_enable(atmel_port->clk);
1719
1720 /* re-enable interrupts if we disabled some on suspend */
1721 UART_PUT_IER(port, atmel_port->backup_imr);
1722 break;
1723 case 3:
1724 /* Back up the interrupt mask and disable all interrupts */
1725 atmel_port->backup_imr = UART_GET_IMR(port);
1726 UART_PUT_IDR(port, -1);
1727
1728 /*
1729 * Disable the peripheral clock for this serial port.
1730 * This is called on uart_close() or a suspend event.
1731 */
1732 clk_disable_unprepare(atmel_port->clk);
1733 break;
1734 default:
1735 printk(KERN_ERR "atmel_serial: unknown pm %d\n", state);
1736 }
1737 }
1738
1739 /*
1740 * Change the port parameters
1741 */
1742 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
1743 struct ktermios *old)
1744 {
1745 unsigned long flags;
1746 unsigned int mode, imr, quot, baud;
1747 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1748
1749 /* Get current mode register */
1750 mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL
1751 | ATMEL_US_NBSTOP | ATMEL_US_PAR
1752 | ATMEL_US_USMODE);
1753
1754 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1755 quot = uart_get_divisor(port, baud);
1756
1757 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
1758 quot /= 8;
1759 mode |= ATMEL_US_USCLKS_MCK_DIV8;
1760 }
1761
1762 /* byte size */
1763 switch (termios->c_cflag & CSIZE) {
1764 case CS5:
1765 mode |= ATMEL_US_CHRL_5;
1766 break;
1767 case CS6:
1768 mode |= ATMEL_US_CHRL_6;
1769 break;
1770 case CS7:
1771 mode |= ATMEL_US_CHRL_7;
1772 break;
1773 default:
1774 mode |= ATMEL_US_CHRL_8;
1775 break;
1776 }
1777
1778 /* stop bits */
1779 if (termios->c_cflag & CSTOPB)
1780 mode |= ATMEL_US_NBSTOP_2;
1781
1782 /* parity */
1783 if (termios->c_cflag & PARENB) {
1784 /* Mark or Space parity */
1785 if (termios->c_cflag & CMSPAR) {
1786 if (termios->c_cflag & PARODD)
1787 mode |= ATMEL_US_PAR_MARK;
1788 else
1789 mode |= ATMEL_US_PAR_SPACE;
1790 } else if (termios->c_cflag & PARODD)
1791 mode |= ATMEL_US_PAR_ODD;
1792 else
1793 mode |= ATMEL_US_PAR_EVEN;
1794 } else
1795 mode |= ATMEL_US_PAR_NONE;
1796
1797 /* hardware handshake (RTS/CTS) */
1798 if (termios->c_cflag & CRTSCTS)
1799 mode |= ATMEL_US_USMODE_HWHS;
1800 else
1801 mode |= ATMEL_US_USMODE_NORMAL;
1802
1803 spin_lock_irqsave(&port->lock, flags);
1804
1805 port->read_status_mask = ATMEL_US_OVRE;
1806 if (termios->c_iflag & INPCK)
1807 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1808 if (termios->c_iflag & (BRKINT | PARMRK))
1809 port->read_status_mask |= ATMEL_US_RXBRK;
1810
1811 if (atmel_use_pdc_rx(port))
1812 /* need to enable error interrupts */
1813 UART_PUT_IER(port, port->read_status_mask);
1814
1815 /*
1816 * Characters to ignore
1817 */
1818 port->ignore_status_mask = 0;
1819 if (termios->c_iflag & IGNPAR)
1820 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1821 if (termios->c_iflag & IGNBRK) {
1822 port->ignore_status_mask |= ATMEL_US_RXBRK;
1823 /*
1824 * If we're ignoring parity and break indicators,
1825 * ignore overruns too (for real raw support).
1826 */
1827 if (termios->c_iflag & IGNPAR)
1828 port->ignore_status_mask |= ATMEL_US_OVRE;
1829 }
1830 /* TODO: Ignore all characters if CREAD is set.*/
1831
1832 /* update the per-port timeout */
1833 uart_update_timeout(port, termios->c_cflag, baud);
1834
1835 /*
1836 * save/disable interrupts. The tty layer will ensure that the
1837 * transmitter is empty if requested by the caller, so there's
1838 * no need to wait for it here.
1839 */
1840 imr = UART_GET_IMR(port);
1841 UART_PUT_IDR(port, -1);
1842
1843 /* disable receiver and transmitter */
1844 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
1845
1846 /* Resetting serial mode to RS232 (0x0) */
1847 mode &= ~ATMEL_US_USMODE;
1848
1849 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
1850 dev_dbg(port->dev, "Setting UART to RS485\n");
1851 if ((atmel_port->rs485.delay_rts_after_send) > 0)
1852 UART_PUT_TTGR(port,
1853 atmel_port->rs485.delay_rts_after_send);
1854 mode |= ATMEL_US_USMODE_RS485;
1855 } else {
1856 dev_dbg(port->dev, "Setting UART to RS232\n");
1857 }
1858
1859 /* set the parity, stop bits and data size */
1860 UART_PUT_MR(port, mode);
1861
1862 /* set the baud rate */
1863 UART_PUT_BRGR(port, quot);
1864 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1865 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1866
1867 /* restore interrupts */
1868 UART_PUT_IER(port, imr);
1869
1870 /* CTS flow-control and modem-status interrupts */
1871 if (UART_ENABLE_MS(port, termios->c_cflag))
1872 port->ops->enable_ms(port);
1873
1874 spin_unlock_irqrestore(&port->lock, flags);
1875 }
1876
1877 static void atmel_set_ldisc(struct uart_port *port, int new)
1878 {
1879 if (new == N_PPS) {
1880 port->flags |= UPF_HARDPPS_CD;
1881 atmel_enable_ms(port);
1882 } else {
1883 port->flags &= ~UPF_HARDPPS_CD;
1884 }
1885 }
1886
1887 /*
1888 * Return string describing the specified port
1889 */
1890 static const char *atmel_type(struct uart_port *port)
1891 {
1892 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1893 }
1894
1895 /*
1896 * Release the memory region(s) being used by 'port'.
1897 */
1898 static void atmel_release_port(struct uart_port *port)
1899 {
1900 struct platform_device *pdev = to_platform_device(port->dev);
1901 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1902
1903 release_mem_region(port->mapbase, size);
1904
1905 if (port->flags & UPF_IOREMAP) {
1906 iounmap(port->membase);
1907 port->membase = NULL;
1908 }
1909 }
1910
1911 /*
1912 * Request the memory region(s) being used by 'port'.
1913 */
1914 static int atmel_request_port(struct uart_port *port)
1915 {
1916 struct platform_device *pdev = to_platform_device(port->dev);
1917 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1918
1919 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
1920 return -EBUSY;
1921
1922 if (port->flags & UPF_IOREMAP) {
1923 port->membase = ioremap(port->mapbase, size);
1924 if (port->membase == NULL) {
1925 release_mem_region(port->mapbase, size);
1926 return -ENOMEM;
1927 }
1928 }
1929
1930 return 0;
1931 }
1932
1933 /*
1934 * Configure/autoconfigure the port.
1935 */
1936 static void atmel_config_port(struct uart_port *port, int flags)
1937 {
1938 if (flags & UART_CONFIG_TYPE) {
1939 port->type = PORT_ATMEL;
1940 atmel_request_port(port);
1941 }
1942 }
1943
1944 /*
1945 * Verify the new serial_struct (for TIOCSSERIAL).
1946 */
1947 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1948 {
1949 int ret = 0;
1950 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1951 ret = -EINVAL;
1952 if (port->irq != ser->irq)
1953 ret = -EINVAL;
1954 if (ser->io_type != SERIAL_IO_MEM)
1955 ret = -EINVAL;
1956 if (port->uartclk / 16 != ser->baud_base)
1957 ret = -EINVAL;
1958 if ((void *)port->mapbase != ser->iomem_base)
1959 ret = -EINVAL;
1960 if (port->iobase != ser->port)
1961 ret = -EINVAL;
1962 if (ser->hub6 != 0)
1963 ret = -EINVAL;
1964 return ret;
1965 }
1966
1967 #ifdef CONFIG_CONSOLE_POLL
1968 static int atmel_poll_get_char(struct uart_port *port)
1969 {
1970 while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY))
1971 cpu_relax();
1972
1973 return UART_GET_CHAR(port);
1974 }
1975
1976 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
1977 {
1978 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
1979 cpu_relax();
1980
1981 UART_PUT_CHAR(port, ch);
1982 }
1983 #endif
1984
1985 static int
1986 atmel_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
1987 {
1988 struct serial_rs485 rs485conf;
1989
1990 switch (cmd) {
1991 case TIOCSRS485:
1992 if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg,
1993 sizeof(rs485conf)))
1994 return -EFAULT;
1995
1996 atmel_config_rs485(port, &rs485conf);
1997 break;
1998
1999 case TIOCGRS485:
2000 if (copy_to_user((struct serial_rs485 *) arg,
2001 &(to_atmel_uart_port(port)->rs485),
2002 sizeof(rs485conf)))
2003 return -EFAULT;
2004 break;
2005
2006 default:
2007 return -ENOIOCTLCMD;
2008 }
2009 return 0;
2010 }
2011
2012
2013
2014 static struct uart_ops atmel_pops = {
2015 .tx_empty = atmel_tx_empty,
2016 .set_mctrl = atmel_set_mctrl,
2017 .get_mctrl = atmel_get_mctrl,
2018 .stop_tx = atmel_stop_tx,
2019 .start_tx = atmel_start_tx,
2020 .stop_rx = atmel_stop_rx,
2021 .enable_ms = atmel_enable_ms,
2022 .break_ctl = atmel_break_ctl,
2023 .startup = atmel_startup,
2024 .shutdown = atmel_shutdown,
2025 .flush_buffer = atmel_flush_buffer,
2026 .set_termios = atmel_set_termios,
2027 .set_ldisc = atmel_set_ldisc,
2028 .type = atmel_type,
2029 .release_port = atmel_release_port,
2030 .request_port = atmel_request_port,
2031 .config_port = atmel_config_port,
2032 .verify_port = atmel_verify_port,
2033 .pm = atmel_serial_pm,
2034 .ioctl = atmel_ioctl,
2035 #ifdef CONFIG_CONSOLE_POLL
2036 .poll_get_char = atmel_poll_get_char,
2037 .poll_put_char = atmel_poll_put_char,
2038 #endif
2039 };
2040
2041 /*
2042 * Configure the port from the platform device resource info.
2043 */
2044 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2045 struct platform_device *pdev)
2046 {
2047 int ret;
2048 struct uart_port *port = &atmel_port->uart;
2049 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2050
2051 if (!atmel_init_property(atmel_port, pdev))
2052 atmel_set_ops(port);
2053
2054 atmel_init_rs485(atmel_port, pdev);
2055
2056 port->iotype = UPIO_MEM;
2057 port->flags = UPF_BOOT_AUTOCONF;
2058 port->ops = &atmel_pops;
2059 port->fifosize = 1;
2060 port->dev = &pdev->dev;
2061 port->mapbase = pdev->resource[0].start;
2062 port->irq = pdev->resource[1].start;
2063
2064 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
2065 (unsigned long)port);
2066
2067 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2068
2069 if (pdata && pdata->regs) {
2070 /* Already mapped by setup code */
2071 port->membase = pdata->regs;
2072 } else {
2073 port->flags |= UPF_IOREMAP;
2074 port->membase = NULL;
2075 }
2076
2077 /* for console, the clock could already be configured */
2078 if (!atmel_port->clk) {
2079 atmel_port->clk = clk_get(&pdev->dev, "usart");
2080 if (IS_ERR(atmel_port->clk)) {
2081 ret = PTR_ERR(atmel_port->clk);
2082 atmel_port->clk = NULL;
2083 return ret;
2084 }
2085 ret = clk_prepare_enable(atmel_port->clk);
2086 if (ret) {
2087 clk_put(atmel_port->clk);
2088 atmel_port->clk = NULL;
2089 return ret;
2090 }
2091 port->uartclk = clk_get_rate(atmel_port->clk);
2092 clk_disable_unprepare(atmel_port->clk);
2093 /* only enable clock when USART is in use */
2094 }
2095
2096 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2097 if (atmel_port->rs485.flags & SER_RS485_ENABLED)
2098 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2099 else if (atmel_use_pdc_tx(port)) {
2100 port->fifosize = PDC_BUFFER_SIZE;
2101 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2102 } else {
2103 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2104 }
2105
2106 return 0;
2107 }
2108
2109 struct platform_device *atmel_default_console_device; /* the serial console device */
2110
2111 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2112 static void atmel_console_putchar(struct uart_port *port, int ch)
2113 {
2114 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
2115 cpu_relax();
2116 UART_PUT_CHAR(port, ch);
2117 }
2118
2119 /*
2120 * Interrupts are disabled on entering
2121 */
2122 static void atmel_console_write(struct console *co, const char *s, u_int count)
2123 {
2124 struct uart_port *port = &atmel_ports[co->index].uart;
2125 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2126 unsigned int status, imr;
2127 unsigned int pdc_tx;
2128
2129 /*
2130 * First, save IMR and then disable interrupts
2131 */
2132 imr = UART_GET_IMR(port);
2133 UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2134
2135 /* Store PDC transmit status and disable it */
2136 pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN;
2137 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
2138
2139 uart_console_write(port, s, count, atmel_console_putchar);
2140
2141 /*
2142 * Finally, wait for transmitter to become empty
2143 * and restore IMR
2144 */
2145 do {
2146 status = UART_GET_CSR(port);
2147 } while (!(status & ATMEL_US_TXRDY));
2148
2149 /* Restore PDC transmit status */
2150 if (pdc_tx)
2151 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
2152
2153 /* set interrupts back the way they were */
2154 UART_PUT_IER(port, imr);
2155 }
2156
2157 /*
2158 * If the port was already initialised (eg, by a boot loader),
2159 * try to determine the current setup.
2160 */
2161 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2162 int *parity, int *bits)
2163 {
2164 unsigned int mr, quot;
2165
2166 /*
2167 * If the baud rate generator isn't running, the port wasn't
2168 * initialized by the boot loader.
2169 */
2170 quot = UART_GET_BRGR(port) & ATMEL_US_CD;
2171 if (!quot)
2172 return;
2173
2174 mr = UART_GET_MR(port) & ATMEL_US_CHRL;
2175 if (mr == ATMEL_US_CHRL_8)
2176 *bits = 8;
2177 else
2178 *bits = 7;
2179
2180 mr = UART_GET_MR(port) & ATMEL_US_PAR;
2181 if (mr == ATMEL_US_PAR_EVEN)
2182 *parity = 'e';
2183 else if (mr == ATMEL_US_PAR_ODD)
2184 *parity = 'o';
2185
2186 /*
2187 * The serial core only rounds down when matching this to a
2188 * supported baud rate. Make sure we don't end up slightly
2189 * lower than one of those, as it would make us fall through
2190 * to a much lower baud rate than we really want.
2191 */
2192 *baud = port->uartclk / (16 * (quot - 1));
2193 }
2194
2195 static int __init atmel_console_setup(struct console *co, char *options)
2196 {
2197 int ret;
2198 struct uart_port *port = &atmel_ports[co->index].uart;
2199 int baud = 115200;
2200 int bits = 8;
2201 int parity = 'n';
2202 int flow = 'n';
2203
2204 if (port->membase == NULL) {
2205 /* Port not initialized yet - delay setup */
2206 return -ENODEV;
2207 }
2208
2209 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2210 if (ret)
2211 return ret;
2212
2213 UART_PUT_IDR(port, -1);
2214 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2215 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
2216
2217 if (options)
2218 uart_parse_options(options, &baud, &parity, &bits, &flow);
2219 else
2220 atmel_console_get_options(port, &baud, &parity, &bits);
2221
2222 return uart_set_options(port, co, baud, parity, bits, flow);
2223 }
2224
2225 static struct uart_driver atmel_uart;
2226
2227 static struct console atmel_console = {
2228 .name = ATMEL_DEVICENAME,
2229 .write = atmel_console_write,
2230 .device = uart_console_device,
2231 .setup = atmel_console_setup,
2232 .flags = CON_PRINTBUFFER,
2233 .index = -1,
2234 .data = &atmel_uart,
2235 };
2236
2237 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2238
2239 /*
2240 * Early console initialization (before VM subsystem initialized).
2241 */
2242 static int __init atmel_console_init(void)
2243 {
2244 int ret;
2245 if (atmel_default_console_device) {
2246 struct atmel_uart_data *pdata =
2247 dev_get_platdata(&atmel_default_console_device->dev);
2248 int id = pdata->num;
2249 struct atmel_uart_port *port = &atmel_ports[id];
2250
2251 port->backup_imr = 0;
2252 port->uart.line = id;
2253
2254 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
2255 ret = atmel_init_port(port, atmel_default_console_device);
2256 if (ret)
2257 return ret;
2258 register_console(&atmel_console);
2259 }
2260
2261 return 0;
2262 }
2263
2264 console_initcall(atmel_console_init);
2265
2266 /*
2267 * Late console initialization.
2268 */
2269 static int __init atmel_late_console_init(void)
2270 {
2271 if (atmel_default_console_device
2272 && !(atmel_console.flags & CON_ENABLED))
2273 register_console(&atmel_console);
2274
2275 return 0;
2276 }
2277
2278 core_initcall(atmel_late_console_init);
2279
2280 static inline bool atmel_is_console_port(struct uart_port *port)
2281 {
2282 return port->cons && port->cons->index == port->line;
2283 }
2284
2285 #else
2286 #define ATMEL_CONSOLE_DEVICE NULL
2287
2288 static inline bool atmel_is_console_port(struct uart_port *port)
2289 {
2290 return false;
2291 }
2292 #endif
2293
2294 static struct uart_driver atmel_uart = {
2295 .owner = THIS_MODULE,
2296 .driver_name = "atmel_serial",
2297 .dev_name = ATMEL_DEVICENAME,
2298 .major = SERIAL_ATMEL_MAJOR,
2299 .minor = MINOR_START,
2300 .nr = ATMEL_MAX_UART,
2301 .cons = ATMEL_CONSOLE_DEVICE,
2302 };
2303
2304 #ifdef CONFIG_PM
2305 static bool atmel_serial_clk_will_stop(void)
2306 {
2307 #ifdef CONFIG_ARCH_AT91
2308 return at91_suspend_entering_slow_clock();
2309 #else
2310 return false;
2311 #endif
2312 }
2313
2314 static int atmel_serial_suspend(struct platform_device *pdev,
2315 pm_message_t state)
2316 {
2317 struct uart_port *port = platform_get_drvdata(pdev);
2318 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2319
2320 if (atmel_is_console_port(port) && console_suspend_enabled) {
2321 /* Drain the TX shifter */
2322 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY))
2323 cpu_relax();
2324 }
2325
2326 /* we can not wake up if we're running on slow clock */
2327 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2328 if (atmel_serial_clk_will_stop())
2329 device_set_wakeup_enable(&pdev->dev, 0);
2330
2331 uart_suspend_port(&atmel_uart, port);
2332
2333 return 0;
2334 }
2335
2336 static int atmel_serial_resume(struct platform_device *pdev)
2337 {
2338 struct uart_port *port = platform_get_drvdata(pdev);
2339 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2340
2341 uart_resume_port(&atmel_uart, port);
2342 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2343
2344 return 0;
2345 }
2346 #else
2347 #define atmel_serial_suspend NULL
2348 #define atmel_serial_resume NULL
2349 #endif
2350
2351 static int atmel_serial_probe(struct platform_device *pdev)
2352 {
2353 struct atmel_uart_port *port;
2354 struct device_node *np = pdev->dev.of_node;
2355 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2356 void *data;
2357 int ret = -ENODEV;
2358
2359 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2360
2361 if (np)
2362 ret = of_alias_get_id(np, "serial");
2363 else
2364 if (pdata)
2365 ret = pdata->num;
2366
2367 if (ret < 0)
2368 /* port id not found in platform data nor device-tree aliases:
2369 * auto-enumerate it */
2370 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2371
2372 if (ret >= ATMEL_MAX_UART) {
2373 ret = -ENODEV;
2374 goto err;
2375 }
2376
2377 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2378 /* port already in use */
2379 ret = -EBUSY;
2380 goto err;
2381 }
2382
2383 port = &atmel_ports[ret];
2384 port->backup_imr = 0;
2385 port->uart.line = ret;
2386 port->rts_gpio = -EINVAL; /* Invalid, zero could be valid */
2387 if (pdata)
2388 port->rts_gpio = pdata->rts_gpio;
2389 else if (np)
2390 port->rts_gpio = of_get_named_gpio(np, "rts-gpios", 0);
2391
2392 if (gpio_is_valid(port->rts_gpio)) {
2393 ret = devm_gpio_request(&pdev->dev, port->rts_gpio, "RTS");
2394 if (ret) {
2395 dev_err(&pdev->dev, "error requesting RTS GPIO\n");
2396 goto err;
2397 }
2398 /* Default to 1 as RTS is active low */
2399 ret = gpio_direction_output(port->rts_gpio, 1);
2400 if (ret) {
2401 dev_err(&pdev->dev, "error setting up RTS GPIO\n");
2402 goto err;
2403 }
2404 }
2405
2406 ret = atmel_init_port(port, pdev);
2407 if (ret)
2408 goto err;
2409
2410 if (!atmel_use_pdc_rx(&port->uart)) {
2411 ret = -ENOMEM;
2412 data = kmalloc(sizeof(struct atmel_uart_char)
2413 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2414 if (!data)
2415 goto err_alloc_ring;
2416 port->rx_ring.buf = data;
2417 }
2418
2419 ret = uart_add_one_port(&atmel_uart, &port->uart);
2420 if (ret)
2421 goto err_add_port;
2422
2423 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2424 if (atmel_is_console_port(&port->uart)
2425 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2426 /*
2427 * The serial core enabled the clock for us, so undo
2428 * the clk_prepare_enable() in atmel_console_setup()
2429 */
2430 clk_disable_unprepare(port->clk);
2431 }
2432 #endif
2433
2434 device_init_wakeup(&pdev->dev, 1);
2435 platform_set_drvdata(pdev, port);
2436
2437 if (port->rs485.flags & SER_RS485_ENABLED) {
2438 UART_PUT_MR(&port->uart, ATMEL_US_USMODE_NORMAL);
2439 UART_PUT_CR(&port->uart, ATMEL_US_RTSEN);
2440 }
2441
2442 /*
2443 * Get port name of usart or uart
2444 */
2445 atmel_get_ip_name(&port->uart);
2446
2447 return 0;
2448
2449 err_add_port:
2450 kfree(port->rx_ring.buf);
2451 port->rx_ring.buf = NULL;
2452 err_alloc_ring:
2453 if (!atmel_is_console_port(&port->uart)) {
2454 clk_put(port->clk);
2455 port->clk = NULL;
2456 }
2457 err:
2458 return ret;
2459 }
2460
2461 static int atmel_serial_remove(struct platform_device *pdev)
2462 {
2463 struct uart_port *port = platform_get_drvdata(pdev);
2464 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2465 int ret = 0;
2466
2467 tasklet_kill(&atmel_port->tasklet);
2468
2469 device_init_wakeup(&pdev->dev, 0);
2470
2471 ret = uart_remove_one_port(&atmel_uart, port);
2472
2473 kfree(atmel_port->rx_ring.buf);
2474
2475 /* "port" is allocated statically, so we shouldn't free it */
2476
2477 clear_bit(port->line, atmel_ports_in_use);
2478
2479 clk_put(atmel_port->clk);
2480
2481 return ret;
2482 }
2483
2484 static struct platform_driver atmel_serial_driver = {
2485 .probe = atmel_serial_probe,
2486 .remove = atmel_serial_remove,
2487 .suspend = atmel_serial_suspend,
2488 .resume = atmel_serial_resume,
2489 .driver = {
2490 .name = "atmel_usart",
2491 .owner = THIS_MODULE,
2492 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2493 },
2494 };
2495
2496 static int __init atmel_serial_init(void)
2497 {
2498 int ret;
2499
2500 ret = uart_register_driver(&atmel_uart);
2501 if (ret)
2502 return ret;
2503
2504 ret = platform_driver_register(&atmel_serial_driver);
2505 if (ret)
2506 uart_unregister_driver(&atmel_uart);
2507
2508 return ret;
2509 }
2510
2511 static void __exit atmel_serial_exit(void)
2512 {
2513 platform_driver_unregister(&atmel_serial_driver);
2514 uart_unregister_driver(&atmel_uart);
2515 }
2516
2517 module_init(atmel_serial_init);
2518 module_exit(atmel_serial_exit);
2519
2520 MODULE_AUTHOR("Rick Bronson");
2521 MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
2522 MODULE_LICENSE("GPL");
2523 MODULE_ALIAS("platform:atmel_usart");
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