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tty/serial: atmel: fix out of range clock divider handling
[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / atmel_serial.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Atmel AT91 Serial ports
4 * Copyright (C) 2003 Rick Bronson
5 *
6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 *
9 * DMA support added by Chip Coldwell.
10 */
11 #include <linux/tty.h>
12 #include <linux/ioport.h>
13 #include <linux/slab.h>
14 #include <linux/init.h>
15 #include <linux/serial.h>
16 #include <linux/clk.h>
17 #include <linux/console.h>
18 #include <linux/sysrq.h>
19 #include <linux/tty_flip.h>
20 #include <linux/platform_device.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23 #include <linux/of_gpio.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/atmel_pdc.h>
27 #include <linux/uaccess.h>
28 #include <linux/platform_data/atmel.h>
29 #include <linux/timer.h>
30 #include <linux/gpio.h>
31 #include <linux/gpio/consumer.h>
32 #include <linux/err.h>
33 #include <linux/irq.h>
34 #include <linux/suspend.h>
35 #include <linux/mm.h>
36
37 #include <asm/io.h>
38 #include <asm/ioctls.h>
39
40 #define PDC_BUFFER_SIZE 512
41 /* Revisit: We should calculate this based on the actual port settings */
42 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
43
44 /* The minium number of data FIFOs should be able to contain */
45 #define ATMEL_MIN_FIFO_SIZE 8
46 /*
47 * These two offsets are substracted from the RX FIFO size to define the RTS
48 * high and low thresholds
49 */
50 #define ATMEL_RTS_HIGH_OFFSET 16
51 #define ATMEL_RTS_LOW_OFFSET 20
52
53 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
54 #define SUPPORT_SYSRQ
55 #endif
56
57 #include <linux/serial_core.h>
58
59 #include "serial_mctrl_gpio.h"
60 #include "atmel_serial.h"
61
62 static void atmel_start_rx(struct uart_port *port);
63 static void atmel_stop_rx(struct uart_port *port);
64
65 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
66
67 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
68 * should coexist with the 8250 driver, such as if we have an external 16C550
69 * UART. */
70 #define SERIAL_ATMEL_MAJOR 204
71 #define MINOR_START 154
72 #define ATMEL_DEVICENAME "ttyAT"
73
74 #else
75
76 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
77 * name, but it is legally reserved for the 8250 driver. */
78 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
79 #define MINOR_START 64
80 #define ATMEL_DEVICENAME "ttyS"
81
82 #endif
83
84 #define ATMEL_ISR_PASS_LIMIT 256
85
86 struct atmel_dma_buffer {
87 unsigned char *buf;
88 dma_addr_t dma_addr;
89 unsigned int dma_size;
90 unsigned int ofs;
91 };
92
93 struct atmel_uart_char {
94 u16 status;
95 u16 ch;
96 };
97
98 /*
99 * Be careful, the real size of the ring buffer is
100 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
101 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
102 * DMA mode.
103 */
104 #define ATMEL_SERIAL_RINGSIZE 1024
105
106 /*
107 * at91: 6 USARTs and one DBGU port (SAM9260)
108 * samx7: 3 USARTs and 5 UARTs
109 */
110 #define ATMEL_MAX_UART 8
111
112 /*
113 * We wrap our port structure around the generic uart_port.
114 */
115 struct atmel_uart_port {
116 struct uart_port uart; /* uart */
117 struct clk *clk; /* uart clock */
118 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
119 u32 backup_imr; /* IMR saved during suspend */
120 int break_active; /* break being received */
121
122 bool use_dma_rx; /* enable DMA receiver */
123 bool use_pdc_rx; /* enable PDC receiver */
124 short pdc_rx_idx; /* current PDC RX buffer */
125 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
126
127 bool use_dma_tx; /* enable DMA transmitter */
128 bool use_pdc_tx; /* enable PDC transmitter */
129 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
130
131 spinlock_t lock_tx; /* port lock */
132 spinlock_t lock_rx; /* port lock */
133 struct dma_chan *chan_tx;
134 struct dma_chan *chan_rx;
135 struct dma_async_tx_descriptor *desc_tx;
136 struct dma_async_tx_descriptor *desc_rx;
137 dma_cookie_t cookie_tx;
138 dma_cookie_t cookie_rx;
139 struct scatterlist sg_tx;
140 struct scatterlist sg_rx;
141 struct tasklet_struct tasklet_rx;
142 struct tasklet_struct tasklet_tx;
143 atomic_t tasklet_shutdown;
144 unsigned int irq_status_prev;
145 unsigned int tx_len;
146
147 struct circ_buf rx_ring;
148
149 struct mctrl_gpios *gpios;
150 unsigned int tx_done_mask;
151 u32 fifo_size;
152 u32 rts_high;
153 u32 rts_low;
154 bool ms_irq_enabled;
155 u32 rtor; /* address of receiver timeout register if it exists */
156 bool has_frac_baudrate;
157 bool has_hw_timer;
158 struct timer_list uart_timer;
159
160 bool tx_stopped;
161 bool suspended;
162 unsigned int pending;
163 unsigned int pending_status;
164 spinlock_t lock_suspended;
165
166 bool hd_start_rx; /* can start RX during half-duplex operation */
167
168 #ifdef CONFIG_PM
169 struct {
170 u32 cr;
171 u32 mr;
172 u32 imr;
173 u32 brgr;
174 u32 rtor;
175 u32 ttgr;
176 u32 fmr;
177 u32 fimr;
178 } cache;
179 #endif
180
181 int (*prepare_rx)(struct uart_port *port);
182 int (*prepare_tx)(struct uart_port *port);
183 void (*schedule_rx)(struct uart_port *port);
184 void (*schedule_tx)(struct uart_port *port);
185 void (*release_rx)(struct uart_port *port);
186 void (*release_tx)(struct uart_port *port);
187 };
188
189 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
190 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
191
192 #ifdef SUPPORT_SYSRQ
193 static struct console atmel_console;
194 #endif
195
196 #if defined(CONFIG_OF)
197 static const struct of_device_id atmel_serial_dt_ids[] = {
198 { .compatible = "atmel,at91rm9200-usart" },
199 { .compatible = "atmel,at91sam9260-usart" },
200 { /* sentinel */ }
201 };
202 #endif
203
204 static inline struct atmel_uart_port *
205 to_atmel_uart_port(struct uart_port *uart)
206 {
207 return container_of(uart, struct atmel_uart_port, uart);
208 }
209
210 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
211 {
212 return __raw_readl(port->membase + reg);
213 }
214
215 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
216 {
217 __raw_writel(value, port->membase + reg);
218 }
219
220 static inline u8 atmel_uart_read_char(struct uart_port *port)
221 {
222 return __raw_readb(port->membase + ATMEL_US_RHR);
223 }
224
225 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
226 {
227 __raw_writeb(value, port->membase + ATMEL_US_THR);
228 }
229
230 static inline int atmel_uart_is_half_duplex(struct uart_port *port)
231 {
232 return (port->rs485.flags & SER_RS485_ENABLED) &&
233 !(port->rs485.flags & SER_RS485_RX_DURING_TX);
234 }
235
236 #ifdef CONFIG_SERIAL_ATMEL_PDC
237 static bool atmel_use_pdc_rx(struct uart_port *port)
238 {
239 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
240
241 return atmel_port->use_pdc_rx;
242 }
243
244 static bool atmel_use_pdc_tx(struct uart_port *port)
245 {
246 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
247
248 return atmel_port->use_pdc_tx;
249 }
250 #else
251 static bool atmel_use_pdc_rx(struct uart_port *port)
252 {
253 return false;
254 }
255
256 static bool atmel_use_pdc_tx(struct uart_port *port)
257 {
258 return false;
259 }
260 #endif
261
262 static bool atmel_use_dma_tx(struct uart_port *port)
263 {
264 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
265
266 return atmel_port->use_dma_tx;
267 }
268
269 static bool atmel_use_dma_rx(struct uart_port *port)
270 {
271 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
272
273 return atmel_port->use_dma_rx;
274 }
275
276 static bool atmel_use_fifo(struct uart_port *port)
277 {
278 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
279
280 return atmel_port->fifo_size;
281 }
282
283 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
284 struct tasklet_struct *t)
285 {
286 if (!atomic_read(&atmel_port->tasklet_shutdown))
287 tasklet_schedule(t);
288 }
289
290 static unsigned int atmel_get_lines_status(struct uart_port *port)
291 {
292 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
293 unsigned int status, ret = 0;
294
295 status = atmel_uart_readl(port, ATMEL_US_CSR);
296
297 mctrl_gpio_get(atmel_port->gpios, &ret);
298
299 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
300 UART_GPIO_CTS))) {
301 if (ret & TIOCM_CTS)
302 status &= ~ATMEL_US_CTS;
303 else
304 status |= ATMEL_US_CTS;
305 }
306
307 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
308 UART_GPIO_DSR))) {
309 if (ret & TIOCM_DSR)
310 status &= ~ATMEL_US_DSR;
311 else
312 status |= ATMEL_US_DSR;
313 }
314
315 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
316 UART_GPIO_RI))) {
317 if (ret & TIOCM_RI)
318 status &= ~ATMEL_US_RI;
319 else
320 status |= ATMEL_US_RI;
321 }
322
323 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
324 UART_GPIO_DCD))) {
325 if (ret & TIOCM_CD)
326 status &= ~ATMEL_US_DCD;
327 else
328 status |= ATMEL_US_DCD;
329 }
330
331 return status;
332 }
333
334 /* Enable or disable the rs485 support */
335 static int atmel_config_rs485(struct uart_port *port,
336 struct serial_rs485 *rs485conf)
337 {
338 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
339 unsigned int mode;
340
341 /* Disable interrupts */
342 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
343
344 mode = atmel_uart_readl(port, ATMEL_US_MR);
345
346 /* Resetting serial mode to RS232 (0x0) */
347 mode &= ~ATMEL_US_USMODE;
348
349 port->rs485 = *rs485conf;
350
351 if (rs485conf->flags & SER_RS485_ENABLED) {
352 dev_dbg(port->dev, "Setting UART to RS485\n");
353 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
354 atmel_uart_writel(port, ATMEL_US_TTGR,
355 rs485conf->delay_rts_after_send);
356 mode |= ATMEL_US_USMODE_RS485;
357 } else {
358 dev_dbg(port->dev, "Setting UART to RS232\n");
359 if (atmel_use_pdc_tx(port))
360 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
361 ATMEL_US_TXBUFE;
362 else
363 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
364 }
365 atmel_uart_writel(port, ATMEL_US_MR, mode);
366
367 /* Enable interrupts */
368 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
369
370 return 0;
371 }
372
373 /*
374 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
375 */
376 static u_int atmel_tx_empty(struct uart_port *port)
377 {
378 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
379
380 if (atmel_port->tx_stopped)
381 return TIOCSER_TEMT;
382 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
383 TIOCSER_TEMT :
384 0;
385 }
386
387 /*
388 * Set state of the modem control output lines
389 */
390 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
391 {
392 unsigned int control = 0;
393 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
394 unsigned int rts_paused, rts_ready;
395 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
396
397 /* override mode to RS485 if needed, otherwise keep the current mode */
398 if (port->rs485.flags & SER_RS485_ENABLED) {
399 atmel_uart_writel(port, ATMEL_US_TTGR,
400 port->rs485.delay_rts_after_send);
401 mode &= ~ATMEL_US_USMODE;
402 mode |= ATMEL_US_USMODE_RS485;
403 }
404
405 /* set the RTS line state according to the mode */
406 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
407 /* force RTS line to high level */
408 rts_paused = ATMEL_US_RTSEN;
409
410 /* give the control of the RTS line back to the hardware */
411 rts_ready = ATMEL_US_RTSDIS;
412 } else {
413 /* force RTS line to high level */
414 rts_paused = ATMEL_US_RTSDIS;
415
416 /* force RTS line to low level */
417 rts_ready = ATMEL_US_RTSEN;
418 }
419
420 if (mctrl & TIOCM_RTS)
421 control |= rts_ready;
422 else
423 control |= rts_paused;
424
425 if (mctrl & TIOCM_DTR)
426 control |= ATMEL_US_DTREN;
427 else
428 control |= ATMEL_US_DTRDIS;
429
430 atmel_uart_writel(port, ATMEL_US_CR, control);
431
432 mctrl_gpio_set(atmel_port->gpios, mctrl);
433
434 /* Local loopback mode? */
435 mode &= ~ATMEL_US_CHMODE;
436 if (mctrl & TIOCM_LOOP)
437 mode |= ATMEL_US_CHMODE_LOC_LOOP;
438 else
439 mode |= ATMEL_US_CHMODE_NORMAL;
440
441 atmel_uart_writel(port, ATMEL_US_MR, mode);
442 }
443
444 /*
445 * Get state of the modem control input lines
446 */
447 static u_int atmel_get_mctrl(struct uart_port *port)
448 {
449 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
450 unsigned int ret = 0, status;
451
452 status = atmel_uart_readl(port, ATMEL_US_CSR);
453
454 /*
455 * The control signals are active low.
456 */
457 if (!(status & ATMEL_US_DCD))
458 ret |= TIOCM_CD;
459 if (!(status & ATMEL_US_CTS))
460 ret |= TIOCM_CTS;
461 if (!(status & ATMEL_US_DSR))
462 ret |= TIOCM_DSR;
463 if (!(status & ATMEL_US_RI))
464 ret |= TIOCM_RI;
465
466 return mctrl_gpio_get(atmel_port->gpios, &ret);
467 }
468
469 /*
470 * Stop transmitting.
471 */
472 static void atmel_stop_tx(struct uart_port *port)
473 {
474 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
475
476 if (atmel_use_pdc_tx(port)) {
477 /* disable PDC transmit */
478 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
479 }
480
481 /*
482 * Disable the transmitter.
483 * This is mandatory when DMA is used, otherwise the DMA buffer
484 * is fully transmitted.
485 */
486 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
487 atmel_port->tx_stopped = true;
488
489 /* Disable interrupts */
490 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
491
492 if (atmel_uart_is_half_duplex(port))
493 atmel_start_rx(port);
494
495 }
496
497 /*
498 * Start transmitting.
499 */
500 static void atmel_start_tx(struct uart_port *port)
501 {
502 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
503
504 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
505 & ATMEL_PDC_TXTEN))
506 /* The transmitter is already running. Yes, we
507 really need this.*/
508 return;
509
510 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
511 if (atmel_uart_is_half_duplex(port))
512 atmel_stop_rx(port);
513
514 if (atmel_use_pdc_tx(port))
515 /* re-enable PDC transmit */
516 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
517
518 /* Enable interrupts */
519 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
520
521 /* re-enable the transmitter */
522 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
523 atmel_port->tx_stopped = false;
524 }
525
526 /*
527 * start receiving - port is in process of being opened.
528 */
529 static void atmel_start_rx(struct uart_port *port)
530 {
531 /* reset status and receiver */
532 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
533
534 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
535
536 if (atmel_use_pdc_rx(port)) {
537 /* enable PDC controller */
538 atmel_uart_writel(port, ATMEL_US_IER,
539 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
540 port->read_status_mask);
541 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
542 } else {
543 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
544 }
545 }
546
547 /*
548 * Stop receiving - port is in process of being closed.
549 */
550 static void atmel_stop_rx(struct uart_port *port)
551 {
552 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
553
554 if (atmel_use_pdc_rx(port)) {
555 /* disable PDC receive */
556 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
557 atmel_uart_writel(port, ATMEL_US_IDR,
558 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
559 port->read_status_mask);
560 } else {
561 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
562 }
563 }
564
565 /*
566 * Enable modem status interrupts
567 */
568 static void atmel_enable_ms(struct uart_port *port)
569 {
570 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
571 uint32_t ier = 0;
572
573 /*
574 * Interrupt should not be enabled twice
575 */
576 if (atmel_port->ms_irq_enabled)
577 return;
578
579 atmel_port->ms_irq_enabled = true;
580
581 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
582 ier |= ATMEL_US_CTSIC;
583
584 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
585 ier |= ATMEL_US_DSRIC;
586
587 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
588 ier |= ATMEL_US_RIIC;
589
590 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
591 ier |= ATMEL_US_DCDIC;
592
593 atmel_uart_writel(port, ATMEL_US_IER, ier);
594
595 mctrl_gpio_enable_ms(atmel_port->gpios);
596 }
597
598 /*
599 * Disable modem status interrupts
600 */
601 static void atmel_disable_ms(struct uart_port *port)
602 {
603 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
604 uint32_t idr = 0;
605
606 /*
607 * Interrupt should not be disabled twice
608 */
609 if (!atmel_port->ms_irq_enabled)
610 return;
611
612 atmel_port->ms_irq_enabled = false;
613
614 mctrl_gpio_disable_ms(atmel_port->gpios);
615
616 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
617 idr |= ATMEL_US_CTSIC;
618
619 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
620 idr |= ATMEL_US_DSRIC;
621
622 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
623 idr |= ATMEL_US_RIIC;
624
625 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
626 idr |= ATMEL_US_DCDIC;
627
628 atmel_uart_writel(port, ATMEL_US_IDR, idr);
629 }
630
631 /*
632 * Control the transmission of a break signal
633 */
634 static void atmel_break_ctl(struct uart_port *port, int break_state)
635 {
636 if (break_state != 0)
637 /* start break */
638 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
639 else
640 /* stop break */
641 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
642 }
643
644 /*
645 * Stores the incoming character in the ring buffer
646 */
647 static void
648 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
649 unsigned int ch)
650 {
651 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
652 struct circ_buf *ring = &atmel_port->rx_ring;
653 struct atmel_uart_char *c;
654
655 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
656 /* Buffer overflow, ignore char */
657 return;
658
659 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
660 c->status = status;
661 c->ch = ch;
662
663 /* Make sure the character is stored before we update head. */
664 smp_wmb();
665
666 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
667 }
668
669 /*
670 * Deal with parity, framing and overrun errors.
671 */
672 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
673 {
674 /* clear error */
675 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
676
677 if (status & ATMEL_US_RXBRK) {
678 /* ignore side-effect */
679 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
680 port->icount.brk++;
681 }
682 if (status & ATMEL_US_PARE)
683 port->icount.parity++;
684 if (status & ATMEL_US_FRAME)
685 port->icount.frame++;
686 if (status & ATMEL_US_OVRE)
687 port->icount.overrun++;
688 }
689
690 /*
691 * Characters received (called from interrupt handler)
692 */
693 static void atmel_rx_chars(struct uart_port *port)
694 {
695 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
696 unsigned int status, ch;
697
698 status = atmel_uart_readl(port, ATMEL_US_CSR);
699 while (status & ATMEL_US_RXRDY) {
700 ch = atmel_uart_read_char(port);
701
702 /*
703 * note that the error handling code is
704 * out of the main execution path
705 */
706 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
707 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
708 || atmel_port->break_active)) {
709
710 /* clear error */
711 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
712
713 if (status & ATMEL_US_RXBRK
714 && !atmel_port->break_active) {
715 atmel_port->break_active = 1;
716 atmel_uart_writel(port, ATMEL_US_IER,
717 ATMEL_US_RXBRK);
718 } else {
719 /*
720 * This is either the end-of-break
721 * condition or we've received at
722 * least one character without RXBRK
723 * being set. In both cases, the next
724 * RXBRK will indicate start-of-break.
725 */
726 atmel_uart_writel(port, ATMEL_US_IDR,
727 ATMEL_US_RXBRK);
728 status &= ~ATMEL_US_RXBRK;
729 atmel_port->break_active = 0;
730 }
731 }
732
733 atmel_buffer_rx_char(port, status, ch);
734 status = atmel_uart_readl(port, ATMEL_US_CSR);
735 }
736
737 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
738 }
739
740 /*
741 * Transmit characters (called from tasklet with TXRDY interrupt
742 * disabled)
743 */
744 static void atmel_tx_chars(struct uart_port *port)
745 {
746 struct circ_buf *xmit = &port->state->xmit;
747 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
748
749 if (port->x_char &&
750 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
751 atmel_uart_write_char(port, port->x_char);
752 port->icount.tx++;
753 port->x_char = 0;
754 }
755 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
756 return;
757
758 while (atmel_uart_readl(port, ATMEL_US_CSR) &
759 atmel_port->tx_done_mask) {
760 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
761 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
762 port->icount.tx++;
763 if (uart_circ_empty(xmit))
764 break;
765 }
766
767 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
768 uart_write_wakeup(port);
769
770 if (!uart_circ_empty(xmit))
771 /* Enable interrupts */
772 atmel_uart_writel(port, ATMEL_US_IER,
773 atmel_port->tx_done_mask);
774 }
775
776 static void atmel_complete_tx_dma(void *arg)
777 {
778 struct atmel_uart_port *atmel_port = arg;
779 struct uart_port *port = &atmel_port->uart;
780 struct circ_buf *xmit = &port->state->xmit;
781 struct dma_chan *chan = atmel_port->chan_tx;
782 unsigned long flags;
783
784 spin_lock_irqsave(&port->lock, flags);
785
786 if (chan)
787 dmaengine_terminate_all(chan);
788 xmit->tail += atmel_port->tx_len;
789 xmit->tail &= UART_XMIT_SIZE - 1;
790
791 port->icount.tx += atmel_port->tx_len;
792
793 spin_lock_irq(&atmel_port->lock_tx);
794 async_tx_ack(atmel_port->desc_tx);
795 atmel_port->cookie_tx = -EINVAL;
796 atmel_port->desc_tx = NULL;
797 spin_unlock_irq(&atmel_port->lock_tx);
798
799 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
800 uart_write_wakeup(port);
801
802 /*
803 * xmit is a circular buffer so, if we have just send data from
804 * xmit->tail to the end of xmit->buf, now we have to transmit the
805 * remaining data from the beginning of xmit->buf to xmit->head.
806 */
807 if (!uart_circ_empty(xmit))
808 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
809 else if (atmel_uart_is_half_duplex(port)) {
810 /*
811 * DMA done, re-enable TXEMPTY and signal that we can stop
812 * TX and start RX for RS485
813 */
814 atmel_port->hd_start_rx = true;
815 atmel_uart_writel(port, ATMEL_US_IER,
816 atmel_port->tx_done_mask);
817 }
818
819 spin_unlock_irqrestore(&port->lock, flags);
820 }
821
822 static void atmel_release_tx_dma(struct uart_port *port)
823 {
824 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
825 struct dma_chan *chan = atmel_port->chan_tx;
826
827 if (chan) {
828 dmaengine_terminate_all(chan);
829 dma_release_channel(chan);
830 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
831 DMA_TO_DEVICE);
832 }
833
834 atmel_port->desc_tx = NULL;
835 atmel_port->chan_tx = NULL;
836 atmel_port->cookie_tx = -EINVAL;
837 }
838
839 /*
840 * Called from tasklet with TXRDY interrupt is disabled.
841 */
842 static void atmel_tx_dma(struct uart_port *port)
843 {
844 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
845 struct circ_buf *xmit = &port->state->xmit;
846 struct dma_chan *chan = atmel_port->chan_tx;
847 struct dma_async_tx_descriptor *desc;
848 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
849 unsigned int tx_len, part1_len, part2_len, sg_len;
850 dma_addr_t phys_addr;
851
852 /* Make sure we have an idle channel */
853 if (atmel_port->desc_tx != NULL)
854 return;
855
856 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
857 /*
858 * DMA is idle now.
859 * Port xmit buffer is already mapped,
860 * and it is one page... Just adjust
861 * offsets and lengths. Since it is a circular buffer,
862 * we have to transmit till the end, and then the rest.
863 * Take the port lock to get a
864 * consistent xmit buffer state.
865 */
866 tx_len = CIRC_CNT_TO_END(xmit->head,
867 xmit->tail,
868 UART_XMIT_SIZE);
869
870 if (atmel_port->fifo_size) {
871 /* multi data mode */
872 part1_len = (tx_len & ~0x3); /* DWORD access */
873 part2_len = (tx_len & 0x3); /* BYTE access */
874 } else {
875 /* single data (legacy) mode */
876 part1_len = 0;
877 part2_len = tx_len; /* BYTE access only */
878 }
879
880 sg_init_table(sgl, 2);
881 sg_len = 0;
882 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
883 if (part1_len) {
884 sg = &sgl[sg_len++];
885 sg_dma_address(sg) = phys_addr;
886 sg_dma_len(sg) = part1_len;
887
888 phys_addr += part1_len;
889 }
890
891 if (part2_len) {
892 sg = &sgl[sg_len++];
893 sg_dma_address(sg) = phys_addr;
894 sg_dma_len(sg) = part2_len;
895 }
896
897 /*
898 * save tx_len so atmel_complete_tx_dma() will increase
899 * xmit->tail correctly
900 */
901 atmel_port->tx_len = tx_len;
902
903 desc = dmaengine_prep_slave_sg(chan,
904 sgl,
905 sg_len,
906 DMA_MEM_TO_DEV,
907 DMA_PREP_INTERRUPT |
908 DMA_CTRL_ACK);
909 if (!desc) {
910 dev_err(port->dev, "Failed to send via dma!\n");
911 return;
912 }
913
914 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
915
916 atmel_port->desc_tx = desc;
917 desc->callback = atmel_complete_tx_dma;
918 desc->callback_param = atmel_port;
919 atmel_port->cookie_tx = dmaengine_submit(desc);
920 }
921
922 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
923 uart_write_wakeup(port);
924 }
925
926 static int atmel_prepare_tx_dma(struct uart_port *port)
927 {
928 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
929 dma_cap_mask_t mask;
930 struct dma_slave_config config;
931 int ret, nent;
932
933 dma_cap_zero(mask);
934 dma_cap_set(DMA_SLAVE, mask);
935
936 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
937 if (atmel_port->chan_tx == NULL)
938 goto chan_err;
939 dev_info(port->dev, "using %s for tx DMA transfers\n",
940 dma_chan_name(atmel_port->chan_tx));
941
942 spin_lock_init(&atmel_port->lock_tx);
943 sg_init_table(&atmel_port->sg_tx, 1);
944 /* UART circular tx buffer is an aligned page. */
945 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
946 sg_set_page(&atmel_port->sg_tx,
947 virt_to_page(port->state->xmit.buf),
948 UART_XMIT_SIZE,
949 offset_in_page(port->state->xmit.buf));
950 nent = dma_map_sg(port->dev,
951 &atmel_port->sg_tx,
952 1,
953 DMA_TO_DEVICE);
954
955 if (!nent) {
956 dev_dbg(port->dev, "need to release resource of dma\n");
957 goto chan_err;
958 } else {
959 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
960 sg_dma_len(&atmel_port->sg_tx),
961 port->state->xmit.buf,
962 &sg_dma_address(&atmel_port->sg_tx));
963 }
964
965 /* Configure the slave DMA */
966 memset(&config, 0, sizeof(config));
967 config.direction = DMA_MEM_TO_DEV;
968 config.dst_addr_width = (atmel_port->fifo_size) ?
969 DMA_SLAVE_BUSWIDTH_4_BYTES :
970 DMA_SLAVE_BUSWIDTH_1_BYTE;
971 config.dst_addr = port->mapbase + ATMEL_US_THR;
972 config.dst_maxburst = 1;
973
974 ret = dmaengine_slave_config(atmel_port->chan_tx,
975 &config);
976 if (ret) {
977 dev_err(port->dev, "DMA tx slave configuration failed\n");
978 goto chan_err;
979 }
980
981 return 0;
982
983 chan_err:
984 dev_err(port->dev, "TX channel not available, switch to pio\n");
985 atmel_port->use_dma_tx = 0;
986 if (atmel_port->chan_tx)
987 atmel_release_tx_dma(port);
988 return -EINVAL;
989 }
990
991 static void atmel_complete_rx_dma(void *arg)
992 {
993 struct uart_port *port = arg;
994 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
995
996 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
997 }
998
999 static void atmel_release_rx_dma(struct uart_port *port)
1000 {
1001 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1002 struct dma_chan *chan = atmel_port->chan_rx;
1003
1004 if (chan) {
1005 dmaengine_terminate_all(chan);
1006 dma_release_channel(chan);
1007 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1008 DMA_FROM_DEVICE);
1009 }
1010
1011 atmel_port->desc_rx = NULL;
1012 atmel_port->chan_rx = NULL;
1013 atmel_port->cookie_rx = -EINVAL;
1014 }
1015
1016 static void atmel_rx_from_dma(struct uart_port *port)
1017 {
1018 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1019 struct tty_port *tport = &port->state->port;
1020 struct circ_buf *ring = &atmel_port->rx_ring;
1021 struct dma_chan *chan = atmel_port->chan_rx;
1022 struct dma_tx_state state;
1023 enum dma_status dmastat;
1024 size_t count;
1025
1026
1027 /* Reset the UART timeout early so that we don't miss one */
1028 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1029 dmastat = dmaengine_tx_status(chan,
1030 atmel_port->cookie_rx,
1031 &state);
1032 /* Restart a new tasklet if DMA status is error */
1033 if (dmastat == DMA_ERROR) {
1034 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1035 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1036 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1037 return;
1038 }
1039
1040 /* CPU claims ownership of RX DMA buffer */
1041 dma_sync_sg_for_cpu(port->dev,
1042 &atmel_port->sg_rx,
1043 1,
1044 DMA_FROM_DEVICE);
1045
1046 /*
1047 * ring->head points to the end of data already written by the DMA.
1048 * ring->tail points to the beginning of data to be read by the
1049 * framework.
1050 * The current transfer size should not be larger than the dma buffer
1051 * length.
1052 */
1053 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1054 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1055 /*
1056 * At this point ring->head may point to the first byte right after the
1057 * last byte of the dma buffer:
1058 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1059 *
1060 * However ring->tail must always points inside the dma buffer:
1061 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1062 *
1063 * Since we use a ring buffer, we have to handle the case
1064 * where head is lower than tail. In such a case, we first read from
1065 * tail to the end of the buffer then reset tail.
1066 */
1067 if (ring->head < ring->tail) {
1068 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1069
1070 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1071 ring->tail = 0;
1072 port->icount.rx += count;
1073 }
1074
1075 /* Finally we read data from tail to head */
1076 if (ring->tail < ring->head) {
1077 count = ring->head - ring->tail;
1078
1079 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1080 /* Wrap ring->head if needed */
1081 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1082 ring->head = 0;
1083 ring->tail = ring->head;
1084 port->icount.rx += count;
1085 }
1086
1087 /* USART retreives ownership of RX DMA buffer */
1088 dma_sync_sg_for_device(port->dev,
1089 &atmel_port->sg_rx,
1090 1,
1091 DMA_FROM_DEVICE);
1092
1093 /*
1094 * Drop the lock here since it might end up calling
1095 * uart_start(), which takes the lock.
1096 */
1097 spin_unlock(&port->lock);
1098 tty_flip_buffer_push(tport);
1099 spin_lock(&port->lock);
1100
1101 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1102 }
1103
1104 static int atmel_prepare_rx_dma(struct uart_port *port)
1105 {
1106 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1107 struct dma_async_tx_descriptor *desc;
1108 dma_cap_mask_t mask;
1109 struct dma_slave_config config;
1110 struct circ_buf *ring;
1111 int ret, nent;
1112
1113 ring = &atmel_port->rx_ring;
1114
1115 dma_cap_zero(mask);
1116 dma_cap_set(DMA_CYCLIC, mask);
1117
1118 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1119 if (atmel_port->chan_rx == NULL)
1120 goto chan_err;
1121 dev_info(port->dev, "using %s for rx DMA transfers\n",
1122 dma_chan_name(atmel_port->chan_rx));
1123
1124 spin_lock_init(&atmel_port->lock_rx);
1125 sg_init_table(&atmel_port->sg_rx, 1);
1126 /* UART circular rx buffer is an aligned page. */
1127 BUG_ON(!PAGE_ALIGNED(ring->buf));
1128 sg_set_page(&atmel_port->sg_rx,
1129 virt_to_page(ring->buf),
1130 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1131 offset_in_page(ring->buf));
1132 nent = dma_map_sg(port->dev,
1133 &atmel_port->sg_rx,
1134 1,
1135 DMA_FROM_DEVICE);
1136
1137 if (!nent) {
1138 dev_dbg(port->dev, "need to release resource of dma\n");
1139 goto chan_err;
1140 } else {
1141 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1142 sg_dma_len(&atmel_port->sg_rx),
1143 ring->buf,
1144 &sg_dma_address(&atmel_port->sg_rx));
1145 }
1146
1147 /* Configure the slave DMA */
1148 memset(&config, 0, sizeof(config));
1149 config.direction = DMA_DEV_TO_MEM;
1150 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1151 config.src_addr = port->mapbase + ATMEL_US_RHR;
1152 config.src_maxburst = 1;
1153
1154 ret = dmaengine_slave_config(atmel_port->chan_rx,
1155 &config);
1156 if (ret) {
1157 dev_err(port->dev, "DMA rx slave configuration failed\n");
1158 goto chan_err;
1159 }
1160 /*
1161 * Prepare a cyclic dma transfer, assign 2 descriptors,
1162 * each one is half ring buffer size
1163 */
1164 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1165 sg_dma_address(&atmel_port->sg_rx),
1166 sg_dma_len(&atmel_port->sg_rx),
1167 sg_dma_len(&atmel_port->sg_rx)/2,
1168 DMA_DEV_TO_MEM,
1169 DMA_PREP_INTERRUPT);
1170 if (!desc) {
1171 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1172 goto chan_err;
1173 }
1174 desc->callback = atmel_complete_rx_dma;
1175 desc->callback_param = port;
1176 atmel_port->desc_rx = desc;
1177 atmel_port->cookie_rx = dmaengine_submit(desc);
1178
1179 return 0;
1180
1181 chan_err:
1182 dev_err(port->dev, "RX channel not available, switch to pio\n");
1183 atmel_port->use_dma_rx = 0;
1184 if (atmel_port->chan_rx)
1185 atmel_release_rx_dma(port);
1186 return -EINVAL;
1187 }
1188
1189 static void atmel_uart_timer_callback(struct timer_list *t)
1190 {
1191 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
1192 uart_timer);
1193 struct uart_port *port = &atmel_port->uart;
1194
1195 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1196 tasklet_schedule(&atmel_port->tasklet_rx);
1197 mod_timer(&atmel_port->uart_timer,
1198 jiffies + uart_poll_timeout(port));
1199 }
1200 }
1201
1202 /*
1203 * receive interrupt handler.
1204 */
1205 static void
1206 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1207 {
1208 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1209
1210 if (atmel_use_pdc_rx(port)) {
1211 /*
1212 * PDC receive. Just schedule the tasklet and let it
1213 * figure out the details.
1214 *
1215 * TODO: We're not handling error flags correctly at
1216 * the moment.
1217 */
1218 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1219 atmel_uart_writel(port, ATMEL_US_IDR,
1220 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1221 atmel_tasklet_schedule(atmel_port,
1222 &atmel_port->tasklet_rx);
1223 }
1224
1225 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1226 ATMEL_US_FRAME | ATMEL_US_PARE))
1227 atmel_pdc_rxerr(port, pending);
1228 }
1229
1230 if (atmel_use_dma_rx(port)) {
1231 if (pending & ATMEL_US_TIMEOUT) {
1232 atmel_uart_writel(port, ATMEL_US_IDR,
1233 ATMEL_US_TIMEOUT);
1234 atmel_tasklet_schedule(atmel_port,
1235 &atmel_port->tasklet_rx);
1236 }
1237 }
1238
1239 /* Interrupt receive */
1240 if (pending & ATMEL_US_RXRDY)
1241 atmel_rx_chars(port);
1242 else if (pending & ATMEL_US_RXBRK) {
1243 /*
1244 * End of break detected. If it came along with a
1245 * character, atmel_rx_chars will handle it.
1246 */
1247 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1248 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1249 atmel_port->break_active = 0;
1250 }
1251 }
1252
1253 /*
1254 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1255 */
1256 static void
1257 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1258 {
1259 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1260
1261 if (pending & atmel_port->tx_done_mask) {
1262 atmel_uart_writel(port, ATMEL_US_IDR,
1263 atmel_port->tx_done_mask);
1264
1265 /* Start RX if flag was set and FIFO is empty */
1266 if (atmel_port->hd_start_rx) {
1267 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1268 & ATMEL_US_TXEMPTY))
1269 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1270
1271 atmel_port->hd_start_rx = false;
1272 atmel_start_rx(port);
1273 }
1274
1275 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1276 }
1277 }
1278
1279 /*
1280 * status flags interrupt handler.
1281 */
1282 static void
1283 atmel_handle_status(struct uart_port *port, unsigned int pending,
1284 unsigned int status)
1285 {
1286 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1287 unsigned int status_change;
1288
1289 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1290 | ATMEL_US_CTSIC)) {
1291 status_change = status ^ atmel_port->irq_status_prev;
1292 atmel_port->irq_status_prev = status;
1293
1294 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1295 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1296 /* TODO: All reads to CSR will clear these interrupts! */
1297 if (status_change & ATMEL_US_RI)
1298 port->icount.rng++;
1299 if (status_change & ATMEL_US_DSR)
1300 port->icount.dsr++;
1301 if (status_change & ATMEL_US_DCD)
1302 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1303 if (status_change & ATMEL_US_CTS)
1304 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1305
1306 wake_up_interruptible(&port->state->port.delta_msr_wait);
1307 }
1308 }
1309 }
1310
1311 /*
1312 * Interrupt handler
1313 */
1314 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1315 {
1316 struct uart_port *port = dev_id;
1317 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1318 unsigned int status, pending, mask, pass_counter = 0;
1319
1320 spin_lock(&atmel_port->lock_suspended);
1321
1322 do {
1323 status = atmel_get_lines_status(port);
1324 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1325 pending = status & mask;
1326 if (!pending)
1327 break;
1328
1329 if (atmel_port->suspended) {
1330 atmel_port->pending |= pending;
1331 atmel_port->pending_status = status;
1332 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1333 pm_system_wakeup();
1334 break;
1335 }
1336
1337 atmel_handle_receive(port, pending);
1338 atmel_handle_status(port, pending, status);
1339 atmel_handle_transmit(port, pending);
1340 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1341
1342 spin_unlock(&atmel_port->lock_suspended);
1343
1344 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1345 }
1346
1347 static void atmel_release_tx_pdc(struct uart_port *port)
1348 {
1349 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1350 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1351
1352 dma_unmap_single(port->dev,
1353 pdc->dma_addr,
1354 pdc->dma_size,
1355 DMA_TO_DEVICE);
1356 }
1357
1358 /*
1359 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1360 */
1361 static void atmel_tx_pdc(struct uart_port *port)
1362 {
1363 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1364 struct circ_buf *xmit = &port->state->xmit;
1365 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1366 int count;
1367
1368 /* nothing left to transmit? */
1369 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1370 return;
1371
1372 xmit->tail += pdc->ofs;
1373 xmit->tail &= UART_XMIT_SIZE - 1;
1374
1375 port->icount.tx += pdc->ofs;
1376 pdc->ofs = 0;
1377
1378 /* more to transmit - setup next transfer */
1379
1380 /* disable PDC transmit */
1381 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1382
1383 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1384 dma_sync_single_for_device(port->dev,
1385 pdc->dma_addr,
1386 pdc->dma_size,
1387 DMA_TO_DEVICE);
1388
1389 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1390 pdc->ofs = count;
1391
1392 atmel_uart_writel(port, ATMEL_PDC_TPR,
1393 pdc->dma_addr + xmit->tail);
1394 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1395 /* re-enable PDC transmit */
1396 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1397 /* Enable interrupts */
1398 atmel_uart_writel(port, ATMEL_US_IER,
1399 atmel_port->tx_done_mask);
1400 } else {
1401 if (atmel_uart_is_half_duplex(port)) {
1402 /* DMA done, stop TX, start RX for RS485 */
1403 atmel_start_rx(port);
1404 }
1405 }
1406
1407 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1408 uart_write_wakeup(port);
1409 }
1410
1411 static int atmel_prepare_tx_pdc(struct uart_port *port)
1412 {
1413 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1414 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1415 struct circ_buf *xmit = &port->state->xmit;
1416
1417 pdc->buf = xmit->buf;
1418 pdc->dma_addr = dma_map_single(port->dev,
1419 pdc->buf,
1420 UART_XMIT_SIZE,
1421 DMA_TO_DEVICE);
1422 pdc->dma_size = UART_XMIT_SIZE;
1423 pdc->ofs = 0;
1424
1425 return 0;
1426 }
1427
1428 static void atmel_rx_from_ring(struct uart_port *port)
1429 {
1430 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1431 struct circ_buf *ring = &atmel_port->rx_ring;
1432 unsigned int flg;
1433 unsigned int status;
1434
1435 while (ring->head != ring->tail) {
1436 struct atmel_uart_char c;
1437
1438 /* Make sure c is loaded after head. */
1439 smp_rmb();
1440
1441 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1442
1443 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1444
1445 port->icount.rx++;
1446 status = c.status;
1447 flg = TTY_NORMAL;
1448
1449 /*
1450 * note that the error handling code is
1451 * out of the main execution path
1452 */
1453 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1454 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1455 if (status & ATMEL_US_RXBRK) {
1456 /* ignore side-effect */
1457 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1458
1459 port->icount.brk++;
1460 if (uart_handle_break(port))
1461 continue;
1462 }
1463 if (status & ATMEL_US_PARE)
1464 port->icount.parity++;
1465 if (status & ATMEL_US_FRAME)
1466 port->icount.frame++;
1467 if (status & ATMEL_US_OVRE)
1468 port->icount.overrun++;
1469
1470 status &= port->read_status_mask;
1471
1472 if (status & ATMEL_US_RXBRK)
1473 flg = TTY_BREAK;
1474 else if (status & ATMEL_US_PARE)
1475 flg = TTY_PARITY;
1476 else if (status & ATMEL_US_FRAME)
1477 flg = TTY_FRAME;
1478 }
1479
1480
1481 if (uart_handle_sysrq_char(port, c.ch))
1482 continue;
1483
1484 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1485 }
1486
1487 /*
1488 * Drop the lock here since it might end up calling
1489 * uart_start(), which takes the lock.
1490 */
1491 spin_unlock(&port->lock);
1492 tty_flip_buffer_push(&port->state->port);
1493 spin_lock(&port->lock);
1494 }
1495
1496 static void atmel_release_rx_pdc(struct uart_port *port)
1497 {
1498 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1499 int i;
1500
1501 for (i = 0; i < 2; i++) {
1502 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1503
1504 dma_unmap_single(port->dev,
1505 pdc->dma_addr,
1506 pdc->dma_size,
1507 DMA_FROM_DEVICE);
1508 kfree(pdc->buf);
1509 }
1510 }
1511
1512 static void atmel_rx_from_pdc(struct uart_port *port)
1513 {
1514 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1515 struct tty_port *tport = &port->state->port;
1516 struct atmel_dma_buffer *pdc;
1517 int rx_idx = atmel_port->pdc_rx_idx;
1518 unsigned int head;
1519 unsigned int tail;
1520 unsigned int count;
1521
1522 do {
1523 /* Reset the UART timeout early so that we don't miss one */
1524 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1525
1526 pdc = &atmel_port->pdc_rx[rx_idx];
1527 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1528 tail = pdc->ofs;
1529
1530 /* If the PDC has switched buffers, RPR won't contain
1531 * any address within the current buffer. Since head
1532 * is unsigned, we just need a one-way comparison to
1533 * find out.
1534 *
1535 * In this case, we just need to consume the entire
1536 * buffer and resubmit it for DMA. This will clear the
1537 * ENDRX bit as well, so that we can safely re-enable
1538 * all interrupts below.
1539 */
1540 head = min(head, pdc->dma_size);
1541
1542 if (likely(head != tail)) {
1543 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1544 pdc->dma_size, DMA_FROM_DEVICE);
1545
1546 /*
1547 * head will only wrap around when we recycle
1548 * the DMA buffer, and when that happens, we
1549 * explicitly set tail to 0. So head will
1550 * always be greater than tail.
1551 */
1552 count = head - tail;
1553
1554 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1555 count);
1556
1557 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1558 pdc->dma_size, DMA_FROM_DEVICE);
1559
1560 port->icount.rx += count;
1561 pdc->ofs = head;
1562 }
1563
1564 /*
1565 * If the current buffer is full, we need to check if
1566 * the next one contains any additional data.
1567 */
1568 if (head >= pdc->dma_size) {
1569 pdc->ofs = 0;
1570 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1571 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1572
1573 rx_idx = !rx_idx;
1574 atmel_port->pdc_rx_idx = rx_idx;
1575 }
1576 } while (head >= pdc->dma_size);
1577
1578 /*
1579 * Drop the lock here since it might end up calling
1580 * uart_start(), which takes the lock.
1581 */
1582 spin_unlock(&port->lock);
1583 tty_flip_buffer_push(tport);
1584 spin_lock(&port->lock);
1585
1586 atmel_uart_writel(port, ATMEL_US_IER,
1587 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1588 }
1589
1590 static int atmel_prepare_rx_pdc(struct uart_port *port)
1591 {
1592 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1593 int i;
1594
1595 for (i = 0; i < 2; i++) {
1596 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1597
1598 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1599 if (pdc->buf == NULL) {
1600 if (i != 0) {
1601 dma_unmap_single(port->dev,
1602 atmel_port->pdc_rx[0].dma_addr,
1603 PDC_BUFFER_SIZE,
1604 DMA_FROM_DEVICE);
1605 kfree(atmel_port->pdc_rx[0].buf);
1606 }
1607 atmel_port->use_pdc_rx = 0;
1608 return -ENOMEM;
1609 }
1610 pdc->dma_addr = dma_map_single(port->dev,
1611 pdc->buf,
1612 PDC_BUFFER_SIZE,
1613 DMA_FROM_DEVICE);
1614 pdc->dma_size = PDC_BUFFER_SIZE;
1615 pdc->ofs = 0;
1616 }
1617
1618 atmel_port->pdc_rx_idx = 0;
1619
1620 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1621 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1622
1623 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1624 atmel_port->pdc_rx[1].dma_addr);
1625 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1626
1627 return 0;
1628 }
1629
1630 /*
1631 * tasklet handling tty stuff outside the interrupt handler.
1632 */
1633 static void atmel_tasklet_rx_func(unsigned long data)
1634 {
1635 struct uart_port *port = (struct uart_port *)data;
1636 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1637
1638 /* The interrupt handler does not take the lock */
1639 spin_lock(&port->lock);
1640 atmel_port->schedule_rx(port);
1641 spin_unlock(&port->lock);
1642 }
1643
1644 static void atmel_tasklet_tx_func(unsigned long data)
1645 {
1646 struct uart_port *port = (struct uart_port *)data;
1647 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1648
1649 /* The interrupt handler does not take the lock */
1650 spin_lock(&port->lock);
1651 atmel_port->schedule_tx(port);
1652 spin_unlock(&port->lock);
1653 }
1654
1655 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1656 struct platform_device *pdev)
1657 {
1658 struct device_node *np = pdev->dev.of_node;
1659
1660 /* DMA/PDC usage specification */
1661 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1662 if (of_property_read_bool(np, "dmas")) {
1663 atmel_port->use_dma_rx = true;
1664 atmel_port->use_pdc_rx = false;
1665 } else {
1666 atmel_port->use_dma_rx = false;
1667 atmel_port->use_pdc_rx = true;
1668 }
1669 } else {
1670 atmel_port->use_dma_rx = false;
1671 atmel_port->use_pdc_rx = false;
1672 }
1673
1674 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1675 if (of_property_read_bool(np, "dmas")) {
1676 atmel_port->use_dma_tx = true;
1677 atmel_port->use_pdc_tx = false;
1678 } else {
1679 atmel_port->use_dma_tx = false;
1680 atmel_port->use_pdc_tx = true;
1681 }
1682 } else {
1683 atmel_port->use_dma_tx = false;
1684 atmel_port->use_pdc_tx = false;
1685 }
1686 }
1687
1688 static void atmel_set_ops(struct uart_port *port)
1689 {
1690 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1691
1692 if (atmel_use_dma_rx(port)) {
1693 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1694 atmel_port->schedule_rx = &atmel_rx_from_dma;
1695 atmel_port->release_rx = &atmel_release_rx_dma;
1696 } else if (atmel_use_pdc_rx(port)) {
1697 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1698 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1699 atmel_port->release_rx = &atmel_release_rx_pdc;
1700 } else {
1701 atmel_port->prepare_rx = NULL;
1702 atmel_port->schedule_rx = &atmel_rx_from_ring;
1703 atmel_port->release_rx = NULL;
1704 }
1705
1706 if (atmel_use_dma_tx(port)) {
1707 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1708 atmel_port->schedule_tx = &atmel_tx_dma;
1709 atmel_port->release_tx = &atmel_release_tx_dma;
1710 } else if (atmel_use_pdc_tx(port)) {
1711 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1712 atmel_port->schedule_tx = &atmel_tx_pdc;
1713 atmel_port->release_tx = &atmel_release_tx_pdc;
1714 } else {
1715 atmel_port->prepare_tx = NULL;
1716 atmel_port->schedule_tx = &atmel_tx_chars;
1717 atmel_port->release_tx = NULL;
1718 }
1719 }
1720
1721 /*
1722 * Get ip name usart or uart
1723 */
1724 static void atmel_get_ip_name(struct uart_port *port)
1725 {
1726 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1727 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1728 u32 version;
1729 u32 usart, dbgu_uart, new_uart;
1730 /* ASCII decoding for IP version */
1731 usart = 0x55534152; /* USAR(T) */
1732 dbgu_uart = 0x44424755; /* DBGU */
1733 new_uart = 0x55415254; /* UART */
1734
1735 /*
1736 * Only USART devices from at91sam9260 SOC implement fractional
1737 * baudrate. It is available for all asynchronous modes, with the
1738 * following restriction: the sampling clock's duty cycle is not
1739 * constant.
1740 */
1741 atmel_port->has_frac_baudrate = false;
1742 atmel_port->has_hw_timer = false;
1743
1744 if (name == new_uart) {
1745 dev_dbg(port->dev, "Uart with hw timer");
1746 atmel_port->has_hw_timer = true;
1747 atmel_port->rtor = ATMEL_UA_RTOR;
1748 } else if (name == usart) {
1749 dev_dbg(port->dev, "Usart\n");
1750 atmel_port->has_frac_baudrate = true;
1751 atmel_port->has_hw_timer = true;
1752 atmel_port->rtor = ATMEL_US_RTOR;
1753 } else if (name == dbgu_uart) {
1754 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1755 } else {
1756 /* fallback for older SoCs: use version field */
1757 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1758 switch (version) {
1759 case 0x302:
1760 case 0x10213:
1761 case 0x10302:
1762 dev_dbg(port->dev, "This version is usart\n");
1763 atmel_port->has_frac_baudrate = true;
1764 atmel_port->has_hw_timer = true;
1765 atmel_port->rtor = ATMEL_US_RTOR;
1766 break;
1767 case 0x203:
1768 case 0x10202:
1769 dev_dbg(port->dev, "This version is uart\n");
1770 break;
1771 default:
1772 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1773 }
1774 }
1775 }
1776
1777 /*
1778 * Perform initialization and enable port for reception
1779 */
1780 static int atmel_startup(struct uart_port *port)
1781 {
1782 struct platform_device *pdev = to_platform_device(port->dev);
1783 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1784 int retval;
1785
1786 /*
1787 * Ensure that no interrupts are enabled otherwise when
1788 * request_irq() is called we could get stuck trying to
1789 * handle an unexpected interrupt
1790 */
1791 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1792 atmel_port->ms_irq_enabled = false;
1793
1794 /*
1795 * Allocate the IRQ
1796 */
1797 retval = request_irq(port->irq, atmel_interrupt,
1798 IRQF_SHARED | IRQF_COND_SUSPEND,
1799 dev_name(&pdev->dev), port);
1800 if (retval) {
1801 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1802 return retval;
1803 }
1804
1805 atomic_set(&atmel_port->tasklet_shutdown, 0);
1806 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
1807 (unsigned long)port);
1808 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
1809 (unsigned long)port);
1810
1811 /*
1812 * Initialize DMA (if necessary)
1813 */
1814 atmel_init_property(atmel_port, pdev);
1815 atmel_set_ops(port);
1816
1817 if (atmel_port->prepare_rx) {
1818 retval = atmel_port->prepare_rx(port);
1819 if (retval < 0)
1820 atmel_set_ops(port);
1821 }
1822
1823 if (atmel_port->prepare_tx) {
1824 retval = atmel_port->prepare_tx(port);
1825 if (retval < 0)
1826 atmel_set_ops(port);
1827 }
1828
1829 /*
1830 * Enable FIFO when available
1831 */
1832 if (atmel_port->fifo_size) {
1833 unsigned int txrdym = ATMEL_US_ONE_DATA;
1834 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1835 unsigned int fmr;
1836
1837 atmel_uart_writel(port, ATMEL_US_CR,
1838 ATMEL_US_FIFOEN |
1839 ATMEL_US_RXFCLR |
1840 ATMEL_US_TXFLCLR);
1841
1842 if (atmel_use_dma_tx(port))
1843 txrdym = ATMEL_US_FOUR_DATA;
1844
1845 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1846 if (atmel_port->rts_high &&
1847 atmel_port->rts_low)
1848 fmr |= ATMEL_US_FRTSC |
1849 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1850 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1851
1852 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1853 }
1854
1855 /* Save current CSR for comparison in atmel_tasklet_func() */
1856 atmel_port->irq_status_prev = atmel_get_lines_status(port);
1857
1858 /*
1859 * Finally, enable the serial port
1860 */
1861 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1862 /* enable xmit & rcvr */
1863 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1864 atmel_port->tx_stopped = false;
1865
1866 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
1867
1868 if (atmel_use_pdc_rx(port)) {
1869 /* set UART timeout */
1870 if (!atmel_port->has_hw_timer) {
1871 mod_timer(&atmel_port->uart_timer,
1872 jiffies + uart_poll_timeout(port));
1873 /* set USART timeout */
1874 } else {
1875 atmel_uart_writel(port, atmel_port->rtor,
1876 PDC_RX_TIMEOUT);
1877 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1878
1879 atmel_uart_writel(port, ATMEL_US_IER,
1880 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1881 }
1882 /* enable PDC controller */
1883 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1884 } else if (atmel_use_dma_rx(port)) {
1885 /* set UART timeout */
1886 if (!atmel_port->has_hw_timer) {
1887 mod_timer(&atmel_port->uart_timer,
1888 jiffies + uart_poll_timeout(port));
1889 /* set USART timeout */
1890 } else {
1891 atmel_uart_writel(port, atmel_port->rtor,
1892 PDC_RX_TIMEOUT);
1893 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1894
1895 atmel_uart_writel(port, ATMEL_US_IER,
1896 ATMEL_US_TIMEOUT);
1897 }
1898 } else {
1899 /* enable receive only */
1900 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
1901 }
1902
1903 return 0;
1904 }
1905
1906 /*
1907 * Flush any TX data submitted for DMA. Called when the TX circular
1908 * buffer is reset.
1909 */
1910 static void atmel_flush_buffer(struct uart_port *port)
1911 {
1912 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1913
1914 if (atmel_use_pdc_tx(port)) {
1915 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
1916 atmel_port->pdc_tx.ofs = 0;
1917 }
1918 /*
1919 * in uart_flush_buffer(), the xmit circular buffer has just
1920 * been cleared, so we have to reset tx_len accordingly.
1921 */
1922 atmel_port->tx_len = 0;
1923 }
1924
1925 /*
1926 * Disable the port
1927 */
1928 static void atmel_shutdown(struct uart_port *port)
1929 {
1930 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1931
1932 /* Disable modem control lines interrupts */
1933 atmel_disable_ms(port);
1934
1935 /* Disable interrupts at device level */
1936 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1937
1938 /* Prevent spurious interrupts from scheduling the tasklet */
1939 atomic_inc(&atmel_port->tasklet_shutdown);
1940
1941 /*
1942 * Prevent any tasklets being scheduled during
1943 * cleanup
1944 */
1945 del_timer_sync(&atmel_port->uart_timer);
1946
1947 /* Make sure that no interrupt is on the fly */
1948 synchronize_irq(port->irq);
1949
1950 /*
1951 * Clear out any scheduled tasklets before
1952 * we destroy the buffers
1953 */
1954 tasklet_kill(&atmel_port->tasklet_rx);
1955 tasklet_kill(&atmel_port->tasklet_tx);
1956
1957 /*
1958 * Ensure everything is stopped and
1959 * disable port and break condition.
1960 */
1961 atmel_stop_rx(port);
1962 atmel_stop_tx(port);
1963
1964 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1965
1966 /*
1967 * Shut-down the DMA.
1968 */
1969 if (atmel_port->release_rx)
1970 atmel_port->release_rx(port);
1971 if (atmel_port->release_tx)
1972 atmel_port->release_tx(port);
1973
1974 /*
1975 * Reset ring buffer pointers
1976 */
1977 atmel_port->rx_ring.head = 0;
1978 atmel_port->rx_ring.tail = 0;
1979
1980 /*
1981 * Free the interrupts
1982 */
1983 free_irq(port->irq, port);
1984
1985 atmel_flush_buffer(port);
1986 }
1987
1988 /*
1989 * Power / Clock management.
1990 */
1991 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
1992 unsigned int oldstate)
1993 {
1994 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1995
1996 switch (state) {
1997 case 0:
1998 /*
1999 * Enable the peripheral clock for this serial port.
2000 * This is called on uart_open() or a resume event.
2001 */
2002 clk_prepare_enable(atmel_port->clk);
2003
2004 /* re-enable interrupts if we disabled some on suspend */
2005 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2006 break;
2007 case 3:
2008 /* Back up the interrupt mask and disable all interrupts */
2009 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2010 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2011
2012 /*
2013 * Disable the peripheral clock for this serial port.
2014 * This is called on uart_close() or a suspend event.
2015 */
2016 clk_disable_unprepare(atmel_port->clk);
2017 break;
2018 default:
2019 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2020 }
2021 }
2022
2023 /*
2024 * Change the port parameters
2025 */
2026 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2027 struct ktermios *old)
2028 {
2029 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2030 unsigned long flags;
2031 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
2032
2033 /* save the current mode register */
2034 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2035
2036 /* reset the mode, clock divisor, parity, stop bits and data size */
2037 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2038 ATMEL_US_PAR | ATMEL_US_USMODE);
2039
2040 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2041
2042 /* byte size */
2043 switch (termios->c_cflag & CSIZE) {
2044 case CS5:
2045 mode |= ATMEL_US_CHRL_5;
2046 break;
2047 case CS6:
2048 mode |= ATMEL_US_CHRL_6;
2049 break;
2050 case CS7:
2051 mode |= ATMEL_US_CHRL_7;
2052 break;
2053 default:
2054 mode |= ATMEL_US_CHRL_8;
2055 break;
2056 }
2057
2058 /* stop bits */
2059 if (termios->c_cflag & CSTOPB)
2060 mode |= ATMEL_US_NBSTOP_2;
2061
2062 /* parity */
2063 if (termios->c_cflag & PARENB) {
2064 /* Mark or Space parity */
2065 if (termios->c_cflag & CMSPAR) {
2066 if (termios->c_cflag & PARODD)
2067 mode |= ATMEL_US_PAR_MARK;
2068 else
2069 mode |= ATMEL_US_PAR_SPACE;
2070 } else if (termios->c_cflag & PARODD)
2071 mode |= ATMEL_US_PAR_ODD;
2072 else
2073 mode |= ATMEL_US_PAR_EVEN;
2074 } else
2075 mode |= ATMEL_US_PAR_NONE;
2076
2077 spin_lock_irqsave(&port->lock, flags);
2078
2079 port->read_status_mask = ATMEL_US_OVRE;
2080 if (termios->c_iflag & INPCK)
2081 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2082 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2083 port->read_status_mask |= ATMEL_US_RXBRK;
2084
2085 if (atmel_use_pdc_rx(port))
2086 /* need to enable error interrupts */
2087 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2088
2089 /*
2090 * Characters to ignore
2091 */
2092 port->ignore_status_mask = 0;
2093 if (termios->c_iflag & IGNPAR)
2094 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2095 if (termios->c_iflag & IGNBRK) {
2096 port->ignore_status_mask |= ATMEL_US_RXBRK;
2097 /*
2098 * If we're ignoring parity and break indicators,
2099 * ignore overruns too (for real raw support).
2100 */
2101 if (termios->c_iflag & IGNPAR)
2102 port->ignore_status_mask |= ATMEL_US_OVRE;
2103 }
2104 /* TODO: Ignore all characters if CREAD is set.*/
2105
2106 /* update the per-port timeout */
2107 uart_update_timeout(port, termios->c_cflag, baud);
2108
2109 /*
2110 * save/disable interrupts. The tty layer will ensure that the
2111 * transmitter is empty if requested by the caller, so there's
2112 * no need to wait for it here.
2113 */
2114 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2115 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2116
2117 /* disable receiver and transmitter */
2118 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2119 atmel_port->tx_stopped = true;
2120
2121 /* mode */
2122 if (port->rs485.flags & SER_RS485_ENABLED) {
2123 atmel_uart_writel(port, ATMEL_US_TTGR,
2124 port->rs485.delay_rts_after_send);
2125 mode |= ATMEL_US_USMODE_RS485;
2126 } else if (termios->c_cflag & CRTSCTS) {
2127 /* RS232 with hardware handshake (RTS/CTS) */
2128 if (atmel_use_fifo(port) &&
2129 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2130 /*
2131 * with ATMEL_US_USMODE_HWHS set, the controller will
2132 * be able to drive the RTS pin high/low when the RX
2133 * FIFO is above RXFTHRES/below RXFTHRES2.
2134 * It will also disable the transmitter when the CTS
2135 * pin is high.
2136 * This mode is not activated if CTS pin is a GPIO
2137 * because in this case, the transmitter is always
2138 * disabled (there must be an internal pull-up
2139 * responsible for this behaviour).
2140 * If the RTS pin is a GPIO, the controller won't be
2141 * able to drive it according to the FIFO thresholds,
2142 * but it will be handled by the driver.
2143 */
2144 mode |= ATMEL_US_USMODE_HWHS;
2145 } else {
2146 /*
2147 * For platforms without FIFO, the flow control is
2148 * handled by the driver.
2149 */
2150 mode |= ATMEL_US_USMODE_NORMAL;
2151 }
2152 } else {
2153 /* RS232 without hadware handshake */
2154 mode |= ATMEL_US_USMODE_NORMAL;
2155 }
2156
2157 /*
2158 * Set the baud rate:
2159 * Fractional baudrate allows to setup output frequency more
2160 * accurately. This feature is enabled only when using normal mode.
2161 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2162 * Currently, OVER is always set to 0 so we get
2163 * baudrate = selected clock / (16 * (CD + FP / 8))
2164 * then
2165 * 8 CD + FP = selected clock / (2 * baudrate)
2166 */
2167 if (atmel_port->has_frac_baudrate) {
2168 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2169 cd = div >> 3;
2170 fp = div & ATMEL_US_FP_MASK;
2171 } else {
2172 cd = uart_get_divisor(port, baud);
2173 }
2174
2175 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2176 cd /= 8;
2177 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2178 }
2179 quot = cd | fp << ATMEL_US_FP_OFFSET;
2180
2181 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2182
2183 /* set the mode, clock divisor, parity, stop bits and data size */
2184 atmel_uart_writel(port, ATMEL_US_MR, mode);
2185
2186 /*
2187 * when switching the mode, set the RTS line state according to the
2188 * new mode, otherwise keep the former state
2189 */
2190 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2191 unsigned int rts_state;
2192
2193 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2194 /* let the hardware control the RTS line */
2195 rts_state = ATMEL_US_RTSDIS;
2196 } else {
2197 /* force RTS line to low level */
2198 rts_state = ATMEL_US_RTSEN;
2199 }
2200
2201 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2202 }
2203
2204 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2205 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2206 atmel_port->tx_stopped = false;
2207
2208 /* restore interrupts */
2209 atmel_uart_writel(port, ATMEL_US_IER, imr);
2210
2211 /* CTS flow-control and modem-status interrupts */
2212 if (UART_ENABLE_MS(port, termios->c_cflag))
2213 atmel_enable_ms(port);
2214 else
2215 atmel_disable_ms(port);
2216
2217 spin_unlock_irqrestore(&port->lock, flags);
2218 }
2219
2220 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2221 {
2222 if (termios->c_line == N_PPS) {
2223 port->flags |= UPF_HARDPPS_CD;
2224 spin_lock_irq(&port->lock);
2225 atmel_enable_ms(port);
2226 spin_unlock_irq(&port->lock);
2227 } else {
2228 port->flags &= ~UPF_HARDPPS_CD;
2229 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2230 spin_lock_irq(&port->lock);
2231 atmel_disable_ms(port);
2232 spin_unlock_irq(&port->lock);
2233 }
2234 }
2235 }
2236
2237 /*
2238 * Return string describing the specified port
2239 */
2240 static const char *atmel_type(struct uart_port *port)
2241 {
2242 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2243 }
2244
2245 /*
2246 * Release the memory region(s) being used by 'port'.
2247 */
2248 static void atmel_release_port(struct uart_port *port)
2249 {
2250 struct platform_device *pdev = to_platform_device(port->dev);
2251 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2252
2253 release_mem_region(port->mapbase, size);
2254
2255 if (port->flags & UPF_IOREMAP) {
2256 iounmap(port->membase);
2257 port->membase = NULL;
2258 }
2259 }
2260
2261 /*
2262 * Request the memory region(s) being used by 'port'.
2263 */
2264 static int atmel_request_port(struct uart_port *port)
2265 {
2266 struct platform_device *pdev = to_platform_device(port->dev);
2267 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2268
2269 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2270 return -EBUSY;
2271
2272 if (port->flags & UPF_IOREMAP) {
2273 port->membase = ioremap(port->mapbase, size);
2274 if (port->membase == NULL) {
2275 release_mem_region(port->mapbase, size);
2276 return -ENOMEM;
2277 }
2278 }
2279
2280 return 0;
2281 }
2282
2283 /*
2284 * Configure/autoconfigure the port.
2285 */
2286 static void atmel_config_port(struct uart_port *port, int flags)
2287 {
2288 if (flags & UART_CONFIG_TYPE) {
2289 port->type = PORT_ATMEL;
2290 atmel_request_port(port);
2291 }
2292 }
2293
2294 /*
2295 * Verify the new serial_struct (for TIOCSSERIAL).
2296 */
2297 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2298 {
2299 int ret = 0;
2300 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2301 ret = -EINVAL;
2302 if (port->irq != ser->irq)
2303 ret = -EINVAL;
2304 if (ser->io_type != SERIAL_IO_MEM)
2305 ret = -EINVAL;
2306 if (port->uartclk / 16 != ser->baud_base)
2307 ret = -EINVAL;
2308 if (port->mapbase != (unsigned long)ser->iomem_base)
2309 ret = -EINVAL;
2310 if (port->iobase != ser->port)
2311 ret = -EINVAL;
2312 if (ser->hub6 != 0)
2313 ret = -EINVAL;
2314 return ret;
2315 }
2316
2317 #ifdef CONFIG_CONSOLE_POLL
2318 static int atmel_poll_get_char(struct uart_port *port)
2319 {
2320 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2321 cpu_relax();
2322
2323 return atmel_uart_read_char(port);
2324 }
2325
2326 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2327 {
2328 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2329 cpu_relax();
2330
2331 atmel_uart_write_char(port, ch);
2332 }
2333 #endif
2334
2335 static const struct uart_ops atmel_pops = {
2336 .tx_empty = atmel_tx_empty,
2337 .set_mctrl = atmel_set_mctrl,
2338 .get_mctrl = atmel_get_mctrl,
2339 .stop_tx = atmel_stop_tx,
2340 .start_tx = atmel_start_tx,
2341 .stop_rx = atmel_stop_rx,
2342 .enable_ms = atmel_enable_ms,
2343 .break_ctl = atmel_break_ctl,
2344 .startup = atmel_startup,
2345 .shutdown = atmel_shutdown,
2346 .flush_buffer = atmel_flush_buffer,
2347 .set_termios = atmel_set_termios,
2348 .set_ldisc = atmel_set_ldisc,
2349 .type = atmel_type,
2350 .release_port = atmel_release_port,
2351 .request_port = atmel_request_port,
2352 .config_port = atmel_config_port,
2353 .verify_port = atmel_verify_port,
2354 .pm = atmel_serial_pm,
2355 #ifdef CONFIG_CONSOLE_POLL
2356 .poll_get_char = atmel_poll_get_char,
2357 .poll_put_char = atmel_poll_put_char,
2358 #endif
2359 };
2360
2361 /*
2362 * Configure the port from the platform device resource info.
2363 */
2364 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2365 struct platform_device *pdev)
2366 {
2367 int ret;
2368 struct uart_port *port = &atmel_port->uart;
2369
2370 atmel_init_property(atmel_port, pdev);
2371 atmel_set_ops(port);
2372
2373 of_get_rs485_mode(pdev->dev.of_node, &port->rs485);
2374
2375 port->iotype = UPIO_MEM;
2376 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
2377 port->ops = &atmel_pops;
2378 port->fifosize = 1;
2379 port->dev = &pdev->dev;
2380 port->mapbase = pdev->resource[0].start;
2381 port->irq = pdev->resource[1].start;
2382 port->rs485_config = atmel_config_rs485;
2383 port->membase = NULL;
2384
2385 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2386
2387 /* for console, the clock could already be configured */
2388 if (!atmel_port->clk) {
2389 atmel_port->clk = clk_get(&pdev->dev, "usart");
2390 if (IS_ERR(atmel_port->clk)) {
2391 ret = PTR_ERR(atmel_port->clk);
2392 atmel_port->clk = NULL;
2393 return ret;
2394 }
2395 ret = clk_prepare_enable(atmel_port->clk);
2396 if (ret) {
2397 clk_put(atmel_port->clk);
2398 atmel_port->clk = NULL;
2399 return ret;
2400 }
2401 port->uartclk = clk_get_rate(atmel_port->clk);
2402 clk_disable_unprepare(atmel_port->clk);
2403 /* only enable clock when USART is in use */
2404 }
2405
2406 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2407 if (port->rs485.flags & SER_RS485_ENABLED)
2408 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2409 else if (atmel_use_pdc_tx(port)) {
2410 port->fifosize = PDC_BUFFER_SIZE;
2411 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2412 } else {
2413 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2414 }
2415
2416 return 0;
2417 }
2418
2419 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2420 static void atmel_console_putchar(struct uart_port *port, int ch)
2421 {
2422 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2423 cpu_relax();
2424 atmel_uart_write_char(port, ch);
2425 }
2426
2427 /*
2428 * Interrupts are disabled on entering
2429 */
2430 static void atmel_console_write(struct console *co, const char *s, u_int count)
2431 {
2432 struct uart_port *port = &atmel_ports[co->index].uart;
2433 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2434 unsigned int status, imr;
2435 unsigned int pdc_tx;
2436
2437 /*
2438 * First, save IMR and then disable interrupts
2439 */
2440 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2441 atmel_uart_writel(port, ATMEL_US_IDR,
2442 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2443
2444 /* Store PDC transmit status and disable it */
2445 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2446 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2447
2448 /* Make sure that tx path is actually able to send characters */
2449 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2450 atmel_port->tx_stopped = false;
2451
2452 uart_console_write(port, s, count, atmel_console_putchar);
2453
2454 /*
2455 * Finally, wait for transmitter to become empty
2456 * and restore IMR
2457 */
2458 do {
2459 status = atmel_uart_readl(port, ATMEL_US_CSR);
2460 } while (!(status & ATMEL_US_TXRDY));
2461
2462 /* Restore PDC transmit status */
2463 if (pdc_tx)
2464 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2465
2466 /* set interrupts back the way they were */
2467 atmel_uart_writel(port, ATMEL_US_IER, imr);
2468 }
2469
2470 /*
2471 * If the port was already initialised (eg, by a boot loader),
2472 * try to determine the current setup.
2473 */
2474 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2475 int *parity, int *bits)
2476 {
2477 unsigned int mr, quot;
2478
2479 /*
2480 * If the baud rate generator isn't running, the port wasn't
2481 * initialized by the boot loader.
2482 */
2483 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2484 if (!quot)
2485 return;
2486
2487 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2488 if (mr == ATMEL_US_CHRL_8)
2489 *bits = 8;
2490 else
2491 *bits = 7;
2492
2493 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2494 if (mr == ATMEL_US_PAR_EVEN)
2495 *parity = 'e';
2496 else if (mr == ATMEL_US_PAR_ODD)
2497 *parity = 'o';
2498
2499 /*
2500 * The serial core only rounds down when matching this to a
2501 * supported baud rate. Make sure we don't end up slightly
2502 * lower than one of those, as it would make us fall through
2503 * to a much lower baud rate than we really want.
2504 */
2505 *baud = port->uartclk / (16 * (quot - 1));
2506 }
2507
2508 static int __init atmel_console_setup(struct console *co, char *options)
2509 {
2510 int ret;
2511 struct uart_port *port = &atmel_ports[co->index].uart;
2512 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2513 int baud = 115200;
2514 int bits = 8;
2515 int parity = 'n';
2516 int flow = 'n';
2517
2518 if (port->membase == NULL) {
2519 /* Port not initialized yet - delay setup */
2520 return -ENODEV;
2521 }
2522
2523 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2524 if (ret)
2525 return ret;
2526
2527 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2528 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2529 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2530 atmel_port->tx_stopped = false;
2531
2532 if (options)
2533 uart_parse_options(options, &baud, &parity, &bits, &flow);
2534 else
2535 atmel_console_get_options(port, &baud, &parity, &bits);
2536
2537 return uart_set_options(port, co, baud, parity, bits, flow);
2538 }
2539
2540 static struct uart_driver atmel_uart;
2541
2542 static struct console atmel_console = {
2543 .name = ATMEL_DEVICENAME,
2544 .write = atmel_console_write,
2545 .device = uart_console_device,
2546 .setup = atmel_console_setup,
2547 .flags = CON_PRINTBUFFER,
2548 .index = -1,
2549 .data = &atmel_uart,
2550 };
2551
2552 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2553
2554 static inline bool atmel_is_console_port(struct uart_port *port)
2555 {
2556 return port->cons && port->cons->index == port->line;
2557 }
2558
2559 #else
2560 #define ATMEL_CONSOLE_DEVICE NULL
2561
2562 static inline bool atmel_is_console_port(struct uart_port *port)
2563 {
2564 return false;
2565 }
2566 #endif
2567
2568 static struct uart_driver atmel_uart = {
2569 .owner = THIS_MODULE,
2570 .driver_name = "atmel_serial",
2571 .dev_name = ATMEL_DEVICENAME,
2572 .major = SERIAL_ATMEL_MAJOR,
2573 .minor = MINOR_START,
2574 .nr = ATMEL_MAX_UART,
2575 .cons = ATMEL_CONSOLE_DEVICE,
2576 };
2577
2578 #ifdef CONFIG_PM
2579 static bool atmel_serial_clk_will_stop(void)
2580 {
2581 #ifdef CONFIG_ARCH_AT91
2582 return at91_suspend_entering_slow_clock();
2583 #else
2584 return false;
2585 #endif
2586 }
2587
2588 static int atmel_serial_suspend(struct platform_device *pdev,
2589 pm_message_t state)
2590 {
2591 struct uart_port *port = platform_get_drvdata(pdev);
2592 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2593
2594 if (atmel_is_console_port(port) && console_suspend_enabled) {
2595 /* Drain the TX shifter */
2596 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2597 ATMEL_US_TXEMPTY))
2598 cpu_relax();
2599 }
2600
2601 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2602 /* Cache register values as we won't get a full shutdown/startup
2603 * cycle
2604 */
2605 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2606 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2607 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2608 atmel_port->cache.rtor = atmel_uart_readl(port,
2609 atmel_port->rtor);
2610 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2611 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2612 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2613 }
2614
2615 /* we can not wake up if we're running on slow clock */
2616 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2617 if (atmel_serial_clk_will_stop()) {
2618 unsigned long flags;
2619
2620 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2621 atmel_port->suspended = true;
2622 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2623 device_set_wakeup_enable(&pdev->dev, 0);
2624 }
2625
2626 uart_suspend_port(&atmel_uart, port);
2627
2628 return 0;
2629 }
2630
2631 static int atmel_serial_resume(struct platform_device *pdev)
2632 {
2633 struct uart_port *port = platform_get_drvdata(pdev);
2634 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2635 unsigned long flags;
2636
2637 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2638 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2639 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2640 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2641 atmel_uart_writel(port, atmel_port->rtor,
2642 atmel_port->cache.rtor);
2643 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2644
2645 if (atmel_port->fifo_size) {
2646 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2647 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2648 atmel_uart_writel(port, ATMEL_US_FMR,
2649 atmel_port->cache.fmr);
2650 atmel_uart_writel(port, ATMEL_US_FIER,
2651 atmel_port->cache.fimr);
2652 }
2653 atmel_start_rx(port);
2654 }
2655
2656 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2657 if (atmel_port->pending) {
2658 atmel_handle_receive(port, atmel_port->pending);
2659 atmel_handle_status(port, atmel_port->pending,
2660 atmel_port->pending_status);
2661 atmel_handle_transmit(port, atmel_port->pending);
2662 atmel_port->pending = 0;
2663 }
2664 atmel_port->suspended = false;
2665 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2666
2667 uart_resume_port(&atmel_uart, port);
2668 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2669
2670 return 0;
2671 }
2672 #else
2673 #define atmel_serial_suspend NULL
2674 #define atmel_serial_resume NULL
2675 #endif
2676
2677 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2678 struct platform_device *pdev)
2679 {
2680 atmel_port->fifo_size = 0;
2681 atmel_port->rts_low = 0;
2682 atmel_port->rts_high = 0;
2683
2684 if (of_property_read_u32(pdev->dev.of_node,
2685 "atmel,fifo-size",
2686 &atmel_port->fifo_size))
2687 return;
2688
2689 if (!atmel_port->fifo_size)
2690 return;
2691
2692 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2693 atmel_port->fifo_size = 0;
2694 dev_err(&pdev->dev, "Invalid FIFO size\n");
2695 return;
2696 }
2697
2698 /*
2699 * 0 <= rts_low <= rts_high <= fifo_size
2700 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2701 * to flush their internal TX FIFO, commonly up to 16 data, before
2702 * actually stopping to send new data. So we try to set the RTS High
2703 * Threshold to a reasonably high value respecting this 16 data
2704 * empirical rule when possible.
2705 */
2706 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2707 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2708 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2709 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2710
2711 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2712 atmel_port->fifo_size);
2713 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2714 atmel_port->rts_high);
2715 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2716 atmel_port->rts_low);
2717 }
2718
2719 static int atmel_serial_probe(struct platform_device *pdev)
2720 {
2721 struct atmel_uart_port *atmel_port;
2722 struct device_node *np = pdev->dev.of_node;
2723 void *data;
2724 int ret = -ENODEV;
2725 bool rs485_enabled;
2726
2727 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2728
2729 ret = of_alias_get_id(np, "serial");
2730 if (ret < 0)
2731 /* port id not found in platform data nor device-tree aliases:
2732 * auto-enumerate it */
2733 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2734
2735 if (ret >= ATMEL_MAX_UART) {
2736 ret = -ENODEV;
2737 goto err;
2738 }
2739
2740 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2741 /* port already in use */
2742 ret = -EBUSY;
2743 goto err;
2744 }
2745
2746 atmel_port = &atmel_ports[ret];
2747 atmel_port->backup_imr = 0;
2748 atmel_port->uart.line = ret;
2749 atmel_serial_probe_fifos(atmel_port, pdev);
2750
2751 atomic_set(&atmel_port->tasklet_shutdown, 0);
2752 spin_lock_init(&atmel_port->lock_suspended);
2753
2754 ret = atmel_init_port(atmel_port, pdev);
2755 if (ret)
2756 goto err_clear_bit;
2757
2758 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2759 if (IS_ERR(atmel_port->gpios)) {
2760 ret = PTR_ERR(atmel_port->gpios);
2761 goto err_clear_bit;
2762 }
2763
2764 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2765 ret = -ENOMEM;
2766 data = kmalloc(sizeof(struct atmel_uart_char)
2767 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2768 if (!data)
2769 goto err_alloc_ring;
2770 atmel_port->rx_ring.buf = data;
2771 }
2772
2773 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2774
2775 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2776 if (ret)
2777 goto err_add_port;
2778
2779 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2780 if (atmel_is_console_port(&atmel_port->uart)
2781 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2782 /*
2783 * The serial core enabled the clock for us, so undo
2784 * the clk_prepare_enable() in atmel_console_setup()
2785 */
2786 clk_disable_unprepare(atmel_port->clk);
2787 }
2788 #endif
2789
2790 device_init_wakeup(&pdev->dev, 1);
2791 platform_set_drvdata(pdev, atmel_port);
2792
2793 /*
2794 * The peripheral clock has been disabled by atmel_init_port():
2795 * enable it before accessing I/O registers
2796 */
2797 clk_prepare_enable(atmel_port->clk);
2798
2799 if (rs485_enabled) {
2800 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2801 ATMEL_US_USMODE_NORMAL);
2802 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2803 ATMEL_US_RTSEN);
2804 }
2805
2806 /*
2807 * Get port name of usart or uart
2808 */
2809 atmel_get_ip_name(&atmel_port->uart);
2810
2811 /*
2812 * The peripheral clock can now safely be disabled till the port
2813 * is used
2814 */
2815 clk_disable_unprepare(atmel_port->clk);
2816
2817 return 0;
2818
2819 err_add_port:
2820 kfree(atmel_port->rx_ring.buf);
2821 atmel_port->rx_ring.buf = NULL;
2822 err_alloc_ring:
2823 if (!atmel_is_console_port(&atmel_port->uart)) {
2824 clk_put(atmel_port->clk);
2825 atmel_port->clk = NULL;
2826 }
2827 err_clear_bit:
2828 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2829 err:
2830 return ret;
2831 }
2832
2833 /*
2834 * Even if the driver is not modular, it makes sense to be able to
2835 * unbind a device: there can be many bound devices, and there are
2836 * situations where dynamic binding and unbinding can be useful.
2837 *
2838 * For example, a connected device can require a specific firmware update
2839 * protocol that needs bitbanging on IO lines, but use the regular serial
2840 * port in the normal case.
2841 */
2842 static int atmel_serial_remove(struct platform_device *pdev)
2843 {
2844 struct uart_port *port = platform_get_drvdata(pdev);
2845 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2846 int ret = 0;
2847
2848 tasklet_kill(&atmel_port->tasklet_rx);
2849 tasklet_kill(&atmel_port->tasklet_tx);
2850
2851 device_init_wakeup(&pdev->dev, 0);
2852
2853 ret = uart_remove_one_port(&atmel_uart, port);
2854
2855 kfree(atmel_port->rx_ring.buf);
2856
2857 /* "port" is allocated statically, so we shouldn't free it */
2858
2859 clear_bit(port->line, atmel_ports_in_use);
2860
2861 clk_put(atmel_port->clk);
2862 atmel_port->clk = NULL;
2863
2864 return ret;
2865 }
2866
2867 static struct platform_driver atmel_serial_driver = {
2868 .probe = atmel_serial_probe,
2869 .remove = atmel_serial_remove,
2870 .suspend = atmel_serial_suspend,
2871 .resume = atmel_serial_resume,
2872 .driver = {
2873 .name = "atmel_usart",
2874 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2875 },
2876 };
2877
2878 static int __init atmel_serial_init(void)
2879 {
2880 int ret;
2881
2882 ret = uart_register_driver(&atmel_uart);
2883 if (ret)
2884 return ret;
2885
2886 ret = platform_driver_register(&atmel_serial_driver);
2887 if (ret)
2888 uart_unregister_driver(&atmel_uart);
2889
2890 return ret;
2891 }
2892 device_initcall(atmel_serial_init);
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