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Merge tag 'apparmor-pr-2017-11-21' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / cpm_uart / cpm_uart_core.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for CPM (SCC/SMC) serial ports; core driver
4 *
5 * Based on arch/ppc/cpm2_io/uart.c by Dan Malek
6 * Based on ppc8xx.c by Thomas Gleixner
7 * Based on drivers/serial/amba.c by Russell King
8 *
9 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
10 * Pantelis Antoniou (panto@intracom.gr) (CPM1)
11 *
12 * Copyright (C) 2004, 2007 Freescale Semiconductor, Inc.
13 * (C) 2004 Intracom, S.A.
14 * (C) 2005-2006 MontaVista Software, Inc.
15 * Vitaly Bordug <vbordug@ru.mvista.com>
16 */
17
18 #include <linux/module.h>
19 #include <linux/tty.h>
20 #include <linux/tty_flip.h>
21 #include <linux/ioport.h>
22 #include <linux/init.h>
23 #include <linux/serial.h>
24 #include <linux/console.h>
25 #include <linux/sysrq.h>
26 #include <linux/device.h>
27 #include <linux/bootmem.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/fs_uart_pd.h>
30 #include <linux/of_address.h>
31 #include <linux/of_irq.h>
32 #include <linux/of_platform.h>
33 #include <linux/gpio.h>
34 #include <linux/of_gpio.h>
35 #include <linux/clk.h>
36
37 #include <asm/io.h>
38 #include <asm/irq.h>
39 #include <asm/delay.h>
40 #include <asm/fs_pd.h>
41 #include <asm/udbg.h>
42
43 #if defined(CONFIG_SERIAL_CPM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
44 #define SUPPORT_SYSRQ
45 #endif
46
47 #include <linux/serial_core.h>
48 #include <linux/kernel.h>
49
50 #include "cpm_uart.h"
51
52
53 /**************************************************************/
54
55 static int cpm_uart_tx_pump(struct uart_port *port);
56 static void cpm_uart_init_smc(struct uart_cpm_port *pinfo);
57 static void cpm_uart_init_scc(struct uart_cpm_port *pinfo);
58 static void cpm_uart_initbd(struct uart_cpm_port *pinfo);
59
60 /**************************************************************/
61
62 #define HW_BUF_SPD_THRESHOLD 2400
63
64 /*
65 * Check, if transmit buffers are processed
66 */
67 static unsigned int cpm_uart_tx_empty(struct uart_port *port)
68 {
69 struct uart_cpm_port *pinfo =
70 container_of(port, struct uart_cpm_port, port);
71 cbd_t __iomem *bdp = pinfo->tx_bd_base;
72 int ret = 0;
73
74 while (1) {
75 if (in_be16(&bdp->cbd_sc) & BD_SC_READY)
76 break;
77
78 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) {
79 ret = TIOCSER_TEMT;
80 break;
81 }
82 bdp++;
83 }
84
85 pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret);
86
87 return ret;
88 }
89
90 static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
91 {
92 struct uart_cpm_port *pinfo =
93 container_of(port, struct uart_cpm_port, port);
94
95 if (pinfo->gpios[GPIO_RTS] >= 0)
96 gpio_set_value(pinfo->gpios[GPIO_RTS], !(mctrl & TIOCM_RTS));
97
98 if (pinfo->gpios[GPIO_DTR] >= 0)
99 gpio_set_value(pinfo->gpios[GPIO_DTR], !(mctrl & TIOCM_DTR));
100 }
101
102 static unsigned int cpm_uart_get_mctrl(struct uart_port *port)
103 {
104 struct uart_cpm_port *pinfo =
105 container_of(port, struct uart_cpm_port, port);
106 unsigned int mctrl = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
107
108 if (pinfo->gpios[GPIO_CTS] >= 0) {
109 if (gpio_get_value(pinfo->gpios[GPIO_CTS]))
110 mctrl &= ~TIOCM_CTS;
111 }
112
113 if (pinfo->gpios[GPIO_DSR] >= 0) {
114 if (gpio_get_value(pinfo->gpios[GPIO_DSR]))
115 mctrl &= ~TIOCM_DSR;
116 }
117
118 if (pinfo->gpios[GPIO_DCD] >= 0) {
119 if (gpio_get_value(pinfo->gpios[GPIO_DCD]))
120 mctrl &= ~TIOCM_CAR;
121 }
122
123 if (pinfo->gpios[GPIO_RI] >= 0) {
124 if (!gpio_get_value(pinfo->gpios[GPIO_RI]))
125 mctrl |= TIOCM_RNG;
126 }
127
128 return mctrl;
129 }
130
131 /*
132 * Stop transmitter
133 */
134 static void cpm_uart_stop_tx(struct uart_port *port)
135 {
136 struct uart_cpm_port *pinfo =
137 container_of(port, struct uart_cpm_port, port);
138 smc_t __iomem *smcp = pinfo->smcp;
139 scc_t __iomem *sccp = pinfo->sccp;
140
141 pr_debug("CPM uart[%d]:stop tx\n", port->line);
142
143 if (IS_SMC(pinfo))
144 clrbits8(&smcp->smc_smcm, SMCM_TX);
145 else
146 clrbits16(&sccp->scc_sccm, UART_SCCM_TX);
147 }
148
149 /*
150 * Start transmitter
151 */
152 static void cpm_uart_start_tx(struct uart_port *port)
153 {
154 struct uart_cpm_port *pinfo =
155 container_of(port, struct uart_cpm_port, port);
156 smc_t __iomem *smcp = pinfo->smcp;
157 scc_t __iomem *sccp = pinfo->sccp;
158
159 pr_debug("CPM uart[%d]:start tx\n", port->line);
160
161 if (IS_SMC(pinfo)) {
162 if (in_8(&smcp->smc_smcm) & SMCM_TX)
163 return;
164 } else {
165 if (in_be16(&sccp->scc_sccm) & UART_SCCM_TX)
166 return;
167 }
168
169 if (cpm_uart_tx_pump(port) != 0) {
170 if (IS_SMC(pinfo)) {
171 setbits8(&smcp->smc_smcm, SMCM_TX);
172 } else {
173 setbits16(&sccp->scc_sccm, UART_SCCM_TX);
174 }
175 }
176 }
177
178 /*
179 * Stop receiver
180 */
181 static void cpm_uart_stop_rx(struct uart_port *port)
182 {
183 struct uart_cpm_port *pinfo =
184 container_of(port, struct uart_cpm_port, port);
185 smc_t __iomem *smcp = pinfo->smcp;
186 scc_t __iomem *sccp = pinfo->sccp;
187
188 pr_debug("CPM uart[%d]:stop rx\n", port->line);
189
190 if (IS_SMC(pinfo))
191 clrbits8(&smcp->smc_smcm, SMCM_RX);
192 else
193 clrbits16(&sccp->scc_sccm, UART_SCCM_RX);
194 }
195
196 /*
197 * Generate a break.
198 */
199 static void cpm_uart_break_ctl(struct uart_port *port, int break_state)
200 {
201 struct uart_cpm_port *pinfo =
202 container_of(port, struct uart_cpm_port, port);
203
204 pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line,
205 break_state);
206
207 if (break_state)
208 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
209 else
210 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
211 }
212
213 /*
214 * Transmit characters, refill buffer descriptor, if possible
215 */
216 static void cpm_uart_int_tx(struct uart_port *port)
217 {
218 pr_debug("CPM uart[%d]:TX INT\n", port->line);
219
220 cpm_uart_tx_pump(port);
221 }
222
223 #ifdef CONFIG_CONSOLE_POLL
224 static int serial_polled;
225 #endif
226
227 /*
228 * Receive characters
229 */
230 static void cpm_uart_int_rx(struct uart_port *port)
231 {
232 int i;
233 unsigned char ch;
234 u8 *cp;
235 struct tty_port *tport = &port->state->port;
236 struct uart_cpm_port *pinfo =
237 container_of(port, struct uart_cpm_port, port);
238 cbd_t __iomem *bdp;
239 u16 status;
240 unsigned int flg;
241
242 pr_debug("CPM uart[%d]:RX INT\n", port->line);
243
244 /* Just loop through the closed BDs and copy the characters into
245 * the buffer.
246 */
247 bdp = pinfo->rx_cur;
248 for (;;) {
249 #ifdef CONFIG_CONSOLE_POLL
250 if (unlikely(serial_polled)) {
251 serial_polled = 0;
252 return;
253 }
254 #endif
255 /* get status */
256 status = in_be16(&bdp->cbd_sc);
257 /* If this one is empty, return happy */
258 if (status & BD_SC_EMPTY)
259 break;
260
261 /* get number of characters, and check spce in flip-buffer */
262 i = in_be16(&bdp->cbd_datlen);
263
264 /* If we have not enough room in tty flip buffer, then we try
265 * later, which will be the next rx-interrupt or a timeout
266 */
267 if (tty_buffer_request_room(tport, i) < i) {
268 printk(KERN_WARNING "No room in flip buffer\n");
269 return;
270 }
271
272 /* get pointer */
273 cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
274
275 /* loop through the buffer */
276 while (i-- > 0) {
277 ch = *cp++;
278 port->icount.rx++;
279 flg = TTY_NORMAL;
280
281 if (status &
282 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
283 goto handle_error;
284 if (uart_handle_sysrq_char(port, ch))
285 continue;
286 #ifdef CONFIG_CONSOLE_POLL
287 if (unlikely(serial_polled)) {
288 serial_polled = 0;
289 return;
290 }
291 #endif
292 error_return:
293 tty_insert_flip_char(tport, ch, flg);
294
295 } /* End while (i--) */
296
297 /* This BD is ready to be used again. Clear status. get next */
298 clrbits16(&bdp->cbd_sc, BD_SC_BR | BD_SC_FR | BD_SC_PR |
299 BD_SC_OV | BD_SC_ID);
300 setbits16(&bdp->cbd_sc, BD_SC_EMPTY);
301
302 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
303 bdp = pinfo->rx_bd_base;
304 else
305 bdp++;
306
307 } /* End for (;;) */
308
309 /* Write back buffer pointer */
310 pinfo->rx_cur = bdp;
311
312 /* activate BH processing */
313 tty_flip_buffer_push(tport);
314
315 return;
316
317 /* Error processing */
318
319 handle_error:
320 /* Statistics */
321 if (status & BD_SC_BR)
322 port->icount.brk++;
323 if (status & BD_SC_PR)
324 port->icount.parity++;
325 if (status & BD_SC_FR)
326 port->icount.frame++;
327 if (status & BD_SC_OV)
328 port->icount.overrun++;
329
330 /* Mask out ignored conditions */
331 status &= port->read_status_mask;
332
333 /* Handle the remaining ones */
334 if (status & BD_SC_BR)
335 flg = TTY_BREAK;
336 else if (status & BD_SC_PR)
337 flg = TTY_PARITY;
338 else if (status & BD_SC_FR)
339 flg = TTY_FRAME;
340
341 /* overrun does not affect the current character ! */
342 if (status & BD_SC_OV) {
343 ch = 0;
344 flg = TTY_OVERRUN;
345 /* We skip this buffer */
346 /* CHECK: Is really nothing senseful there */
347 /* ASSUMPTION: it contains nothing valid */
348 i = 0;
349 }
350 #ifdef SUPPORT_SYSRQ
351 port->sysrq = 0;
352 #endif
353 goto error_return;
354 }
355
356 /*
357 * Asynchron mode interrupt handler
358 */
359 static irqreturn_t cpm_uart_int(int irq, void *data)
360 {
361 u8 events;
362 struct uart_port *port = data;
363 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
364 smc_t __iomem *smcp = pinfo->smcp;
365 scc_t __iomem *sccp = pinfo->sccp;
366
367 pr_debug("CPM uart[%d]:IRQ\n", port->line);
368
369 if (IS_SMC(pinfo)) {
370 events = in_8(&smcp->smc_smce);
371 out_8(&smcp->smc_smce, events);
372 if (events & SMCM_BRKE)
373 uart_handle_break(port);
374 if (events & SMCM_RX)
375 cpm_uart_int_rx(port);
376 if (events & SMCM_TX)
377 cpm_uart_int_tx(port);
378 } else {
379 events = in_be16(&sccp->scc_scce);
380 out_be16(&sccp->scc_scce, events);
381 if (events & UART_SCCM_BRKE)
382 uart_handle_break(port);
383 if (events & UART_SCCM_RX)
384 cpm_uart_int_rx(port);
385 if (events & UART_SCCM_TX)
386 cpm_uart_int_tx(port);
387 }
388 return (events) ? IRQ_HANDLED : IRQ_NONE;
389 }
390
391 static int cpm_uart_startup(struct uart_port *port)
392 {
393 int retval;
394 struct uart_cpm_port *pinfo =
395 container_of(port, struct uart_cpm_port, port);
396
397 pr_debug("CPM uart[%d]:startup\n", port->line);
398
399 /* If the port is not the console, make sure rx is disabled. */
400 if (!(pinfo->flags & FLAG_CONSOLE)) {
401 /* Disable UART rx */
402 if (IS_SMC(pinfo)) {
403 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN);
404 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
405 } else {
406 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR);
407 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
408 }
409 cpm_uart_initbd(pinfo);
410 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
411 }
412 /* Install interrupt handler. */
413 retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port);
414 if (retval)
415 return retval;
416
417 /* Startup rx-int */
418 if (IS_SMC(pinfo)) {
419 setbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
420 setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN));
421 } else {
422 setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
423 setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT));
424 }
425
426 return 0;
427 }
428
429 inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo)
430 {
431 set_current_state(TASK_UNINTERRUPTIBLE);
432 schedule_timeout(pinfo->wait_closing);
433 }
434
435 /*
436 * Shutdown the uart
437 */
438 static void cpm_uart_shutdown(struct uart_port *port)
439 {
440 struct uart_cpm_port *pinfo =
441 container_of(port, struct uart_cpm_port, port);
442
443 pr_debug("CPM uart[%d]:shutdown\n", port->line);
444
445 /* free interrupt handler */
446 free_irq(port->irq, port);
447
448 /* If the port is not the console, disable Rx and Tx. */
449 if (!(pinfo->flags & FLAG_CONSOLE)) {
450 /* Wait for all the BDs marked sent */
451 while(!cpm_uart_tx_empty(port)) {
452 set_current_state(TASK_UNINTERRUPTIBLE);
453 schedule_timeout(2);
454 }
455
456 if (pinfo->wait_closing)
457 cpm_uart_wait_until_send(pinfo);
458
459 /* Stop uarts */
460 if (IS_SMC(pinfo)) {
461 smc_t __iomem *smcp = pinfo->smcp;
462 clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
463 clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX);
464 } else {
465 scc_t __iomem *sccp = pinfo->sccp;
466 clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
467 clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
468 }
469
470 /* Shut them really down and reinit buffer descriptors */
471 if (IS_SMC(pinfo)) {
472 out_be16(&pinfo->smcup->smc_brkcr, 0);
473 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
474 } else {
475 out_be16(&pinfo->sccup->scc_brkcr, 0);
476 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
477 }
478
479 cpm_uart_initbd(pinfo);
480 }
481 }
482
483 static void cpm_uart_set_termios(struct uart_port *port,
484 struct ktermios *termios,
485 struct ktermios *old)
486 {
487 int baud;
488 unsigned long flags;
489 u16 cval, scval, prev_mode;
490 int bits, sbits;
491 struct uart_cpm_port *pinfo =
492 container_of(port, struct uart_cpm_port, port);
493 smc_t __iomem *smcp = pinfo->smcp;
494 scc_t __iomem *sccp = pinfo->sccp;
495 int maxidl;
496
497 pr_debug("CPM uart[%d]:set_termios\n", port->line);
498
499 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
500 if (baud < HW_BUF_SPD_THRESHOLD ||
501 (pinfo->port.state && pinfo->port.state->port.low_latency))
502 pinfo->rx_fifosize = 1;
503 else
504 pinfo->rx_fifosize = RX_BUF_SIZE;
505
506 /* MAXIDL is the timeout after which a receive buffer is closed
507 * when not full if no more characters are received.
508 * We calculate it from the baudrate so that the duration is
509 * always the same at standard rates: about 4ms.
510 */
511 maxidl = baud / 2400;
512 if (maxidl < 1)
513 maxidl = 1;
514 if (maxidl > 0x10)
515 maxidl = 0x10;
516
517 /* Character length programmed into the mode register is the
518 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
519 * 1 or 2 stop bits, minus 1.
520 * The value 'bits' counts this for us.
521 */
522 cval = 0;
523 scval = 0;
524
525 /* byte size */
526 switch (termios->c_cflag & CSIZE) {
527 case CS5:
528 bits = 5;
529 break;
530 case CS6:
531 bits = 6;
532 break;
533 case CS7:
534 bits = 7;
535 break;
536 case CS8:
537 bits = 8;
538 break;
539 /* Never happens, but GCC is too dumb to figure it out */
540 default:
541 bits = 8;
542 break;
543 }
544 sbits = bits - 5;
545
546 if (termios->c_cflag & CSTOPB) {
547 cval |= SMCMR_SL; /* Two stops */
548 scval |= SCU_PSMR_SL;
549 bits++;
550 }
551
552 if (termios->c_cflag & PARENB) {
553 cval |= SMCMR_PEN;
554 scval |= SCU_PSMR_PEN;
555 bits++;
556 if (!(termios->c_cflag & PARODD)) {
557 cval |= SMCMR_PM_EVEN;
558 scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP);
559 }
560 }
561
562 /*
563 * Update the timeout
564 */
565 uart_update_timeout(port, termios->c_cflag, baud);
566
567 /*
568 * Set up parity check flag
569 */
570 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
571
572 port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV);
573 if (termios->c_iflag & INPCK)
574 port->read_status_mask |= BD_SC_FR | BD_SC_PR;
575 if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK))
576 port->read_status_mask |= BD_SC_BR;
577
578 /*
579 * Characters to ignore
580 */
581 port->ignore_status_mask = 0;
582 if (termios->c_iflag & IGNPAR)
583 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
584 if (termios->c_iflag & IGNBRK) {
585 port->ignore_status_mask |= BD_SC_BR;
586 /*
587 * If we're ignore parity and break indicators, ignore
588 * overruns too. (For real raw support).
589 */
590 if (termios->c_iflag & IGNPAR)
591 port->ignore_status_mask |= BD_SC_OV;
592 }
593 /*
594 * !!! ignore all characters if CREAD is not set
595 */
596 if ((termios->c_cflag & CREAD) == 0)
597 port->read_status_mask &= ~BD_SC_EMPTY;
598
599 spin_lock_irqsave(&port->lock, flags);
600
601 /* Start bit has not been added (so don't, because we would just
602 * subtract it later), and we need to add one for the number of
603 * stops bits (there is always at least one).
604 */
605 bits++;
606 if (IS_SMC(pinfo)) {
607 /*
608 * MRBLR can be changed while an SMC/SCC is operating only
609 * if it is done in a single bus cycle with one 16-bit move
610 * (not two 8-bit bus cycles back-to-back). This occurs when
611 * the cp shifts control to the next RxBD, so the change does
612 * not take effect immediately. To guarantee the exact RxBD
613 * on which the change occurs, change MRBLR only while the
614 * SMC/SCC receiver is disabled.
615 */
616 out_be16(&pinfo->smcup->smc_mrblr, pinfo->rx_fifosize);
617 out_be16(&pinfo->smcup->smc_maxidl, maxidl);
618
619 /* Set the mode register. We want to keep a copy of the
620 * enables, because we want to put them back if they were
621 * present.
622 */
623 prev_mode = in_be16(&smcp->smc_smcmr) & (SMCMR_REN | SMCMR_TEN);
624 /* Output in *one* operation, so we don't interrupt RX/TX if they
625 * were already enabled. */
626 out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits) | cval |
627 SMCMR_SM_UART | prev_mode);
628 } else {
629 out_be16(&pinfo->sccup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
630 out_be16(&pinfo->sccup->scc_maxidl, maxidl);
631 out_be16(&sccp->scc_psmr, (sbits << 12) | scval);
632 }
633
634 if (pinfo->clk)
635 clk_set_rate(pinfo->clk, baud);
636 else
637 cpm_set_brg(pinfo->brg - 1, baud);
638 spin_unlock_irqrestore(&port->lock, flags);
639 }
640
641 static const char *cpm_uart_type(struct uart_port *port)
642 {
643 pr_debug("CPM uart[%d]:uart_type\n", port->line);
644
645 return port->type == PORT_CPM ? "CPM UART" : NULL;
646 }
647
648 /*
649 * verify the new serial_struct (for TIOCSSERIAL).
650 */
651 static int cpm_uart_verify_port(struct uart_port *port,
652 struct serial_struct *ser)
653 {
654 int ret = 0;
655
656 pr_debug("CPM uart[%d]:verify_port\n", port->line);
657
658 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
659 ret = -EINVAL;
660 if (ser->irq < 0 || ser->irq >= nr_irqs)
661 ret = -EINVAL;
662 if (ser->baud_base < 9600)
663 ret = -EINVAL;
664 return ret;
665 }
666
667 /*
668 * Transmit characters, refill buffer descriptor, if possible
669 */
670 static int cpm_uart_tx_pump(struct uart_port *port)
671 {
672 cbd_t __iomem *bdp;
673 u8 *p;
674 int count;
675 struct uart_cpm_port *pinfo =
676 container_of(port, struct uart_cpm_port, port);
677 struct circ_buf *xmit = &port->state->xmit;
678
679 /* Handle xon/xoff */
680 if (port->x_char) {
681 /* Pick next descriptor and fill from buffer */
682 bdp = pinfo->tx_cur;
683
684 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
685
686 *p++ = port->x_char;
687
688 out_be16(&bdp->cbd_datlen, 1);
689 setbits16(&bdp->cbd_sc, BD_SC_READY);
690 /* Get next BD. */
691 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
692 bdp = pinfo->tx_bd_base;
693 else
694 bdp++;
695 pinfo->tx_cur = bdp;
696
697 port->icount.tx++;
698 port->x_char = 0;
699 return 1;
700 }
701
702 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
703 cpm_uart_stop_tx(port);
704 return 0;
705 }
706
707 /* Pick next descriptor and fill from buffer */
708 bdp = pinfo->tx_cur;
709
710 while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) &&
711 xmit->tail != xmit->head) {
712 count = 0;
713 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
714 while (count < pinfo->tx_fifosize) {
715 *p++ = xmit->buf[xmit->tail];
716 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
717 port->icount.tx++;
718 count++;
719 if (xmit->head == xmit->tail)
720 break;
721 }
722 out_be16(&bdp->cbd_datlen, count);
723 setbits16(&bdp->cbd_sc, BD_SC_READY);
724 /* Get next BD. */
725 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
726 bdp = pinfo->tx_bd_base;
727 else
728 bdp++;
729 }
730 pinfo->tx_cur = bdp;
731
732 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
733 uart_write_wakeup(port);
734
735 if (uart_circ_empty(xmit)) {
736 cpm_uart_stop_tx(port);
737 return 0;
738 }
739
740 return 1;
741 }
742
743 /*
744 * init buffer descriptors
745 */
746 static void cpm_uart_initbd(struct uart_cpm_port *pinfo)
747 {
748 int i;
749 u8 *mem_addr;
750 cbd_t __iomem *bdp;
751
752 pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line);
753
754 /* Set the physical address of the host memory
755 * buffers in the buffer descriptors, and the
756 * virtual address for us to work with.
757 */
758 mem_addr = pinfo->mem_addr;
759 bdp = pinfo->rx_cur = pinfo->rx_bd_base;
760 for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) {
761 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
762 out_be16(&bdp->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT);
763 mem_addr += pinfo->rx_fifosize;
764 }
765
766 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
767 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);
768
769 /* Set the physical address of the host memory
770 * buffers in the buffer descriptors, and the
771 * virtual address for us to work with.
772 */
773 mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize);
774 bdp = pinfo->tx_cur = pinfo->tx_bd_base;
775 for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) {
776 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
777 out_be16(&bdp->cbd_sc, BD_SC_INTRPT);
778 mem_addr += pinfo->tx_fifosize;
779 }
780
781 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
782 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_INTRPT);
783 }
784
785 static void cpm_uart_init_scc(struct uart_cpm_port *pinfo)
786 {
787 scc_t __iomem *scp;
788 scc_uart_t __iomem *sup;
789
790 pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line);
791
792 scp = pinfo->sccp;
793 sup = pinfo->sccup;
794
795 /* Store address */
796 out_be16(&pinfo->sccup->scc_genscc.scc_rbase,
797 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
798 out_be16(&pinfo->sccup->scc_genscc.scc_tbase,
799 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
800
801 /* Set up the uart parameters in the
802 * parameter ram.
803 */
804
805 cpm_set_scc_fcr(sup);
806
807 out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
808 out_be16(&sup->scc_maxidl, 0x10);
809 out_be16(&sup->scc_brkcr, 1);
810 out_be16(&sup->scc_parec, 0);
811 out_be16(&sup->scc_frmec, 0);
812 out_be16(&sup->scc_nosec, 0);
813 out_be16(&sup->scc_brkec, 0);
814 out_be16(&sup->scc_uaddr1, 0);
815 out_be16(&sup->scc_uaddr2, 0);
816 out_be16(&sup->scc_toseq, 0);
817 out_be16(&sup->scc_char1, 0x8000);
818 out_be16(&sup->scc_char2, 0x8000);
819 out_be16(&sup->scc_char3, 0x8000);
820 out_be16(&sup->scc_char4, 0x8000);
821 out_be16(&sup->scc_char5, 0x8000);
822 out_be16(&sup->scc_char6, 0x8000);
823 out_be16(&sup->scc_char7, 0x8000);
824 out_be16(&sup->scc_char8, 0x8000);
825 out_be16(&sup->scc_rccm, 0xc0ff);
826
827 /* Send the CPM an initialize command.
828 */
829 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
830
831 /* Set UART mode, 8 bit, no parity, one stop.
832 * Enable receive and transmit.
833 */
834 out_be32(&scp->scc_gsmrh, 0);
835 out_be32(&scp->scc_gsmrl,
836 SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
837
838 /* Enable rx interrupts and clear all pending events. */
839 out_be16(&scp->scc_sccm, 0);
840 out_be16(&scp->scc_scce, 0xffff);
841 out_be16(&scp->scc_dsr, 0x7e7e);
842 out_be16(&scp->scc_psmr, 0x3000);
843
844 setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
845 }
846
847 static void cpm_uart_init_smc(struct uart_cpm_port *pinfo)
848 {
849 smc_t __iomem *sp;
850 smc_uart_t __iomem *up;
851
852 pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line);
853
854 sp = pinfo->smcp;
855 up = pinfo->smcup;
856
857 /* Store address */
858 out_be16(&pinfo->smcup->smc_rbase,
859 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
860 out_be16(&pinfo->smcup->smc_tbase,
861 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
862
863 /*
864 * In case SMC1 is being relocated...
865 */
866 #if defined (CONFIG_I2C_SPI_SMC1_UCODE_PATCH)
867 out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase));
868 out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase));
869 out_be32(&up->smc_rstate, 0);
870 out_be32(&up->smc_tstate, 0);
871 out_be16(&up->smc_brkcr, 1); /* number of break chars */
872 out_be16(&up->smc_brkec, 0);
873 #endif
874
875 /* Set up the uart parameters in the
876 * parameter ram.
877 */
878 cpm_set_smc_fcr(up);
879
880 /* Using idle character time requires some additional tuning. */
881 out_be16(&up->smc_mrblr, pinfo->rx_fifosize);
882 out_be16(&up->smc_maxidl, 0x10);
883 out_be16(&up->smc_brklen, 0);
884 out_be16(&up->smc_brkec, 0);
885 out_be16(&up->smc_brkcr, 1);
886
887 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
888
889 /* Set UART mode, 8 bit, no parity, one stop.
890 * Enable receive and transmit.
891 */
892 out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART);
893
894 /* Enable only rx interrupts clear all pending events. */
895 out_8(&sp->smc_smcm, 0);
896 out_8(&sp->smc_smce, 0xff);
897
898 setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
899 }
900
901 /*
902 * Initialize port. This is called from early_console stuff
903 * so we have to be careful here !
904 */
905 static int cpm_uart_request_port(struct uart_port *port)
906 {
907 struct uart_cpm_port *pinfo =
908 container_of(port, struct uart_cpm_port, port);
909 int ret;
910
911 pr_debug("CPM uart[%d]:request port\n", port->line);
912
913 if (pinfo->flags & FLAG_CONSOLE)
914 return 0;
915
916 if (IS_SMC(pinfo)) {
917 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
918 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
919 } else {
920 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
921 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
922 }
923
924 ret = cpm_uart_allocbuf(pinfo, 0);
925
926 if (ret)
927 return ret;
928
929 cpm_uart_initbd(pinfo);
930 if (IS_SMC(pinfo))
931 cpm_uart_init_smc(pinfo);
932 else
933 cpm_uart_init_scc(pinfo);
934
935 return 0;
936 }
937
938 static void cpm_uart_release_port(struct uart_port *port)
939 {
940 struct uart_cpm_port *pinfo =
941 container_of(port, struct uart_cpm_port, port);
942
943 if (!(pinfo->flags & FLAG_CONSOLE))
944 cpm_uart_freebuf(pinfo);
945 }
946
947 /*
948 * Configure/autoconfigure the port.
949 */
950 static void cpm_uart_config_port(struct uart_port *port, int flags)
951 {
952 pr_debug("CPM uart[%d]:config_port\n", port->line);
953
954 if (flags & UART_CONFIG_TYPE) {
955 port->type = PORT_CPM;
956 cpm_uart_request_port(port);
957 }
958 }
959
960 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_CPM_CONSOLE)
961 /*
962 * Write a string to the serial port
963 * Note that this is called with interrupts already disabled
964 */
965 static void cpm_uart_early_write(struct uart_cpm_port *pinfo,
966 const char *string, u_int count, bool handle_linefeed)
967 {
968 unsigned int i;
969 cbd_t __iomem *bdp, *bdbase;
970 unsigned char *cpm_outp_addr;
971
972 /* Get the address of the host memory buffer.
973 */
974 bdp = pinfo->tx_cur;
975 bdbase = pinfo->tx_bd_base;
976
977 /*
978 * Now, do each character. This is not as bad as it looks
979 * since this is a holding FIFO and not a transmitting FIFO.
980 * We could add the complexity of filling the entire transmit
981 * buffer, but we would just wait longer between accesses......
982 */
983 for (i = 0; i < count; i++, string++) {
984 /* Wait for transmitter fifo to empty.
985 * Ready indicates output is ready, and xmt is doing
986 * that, not that it is ready for us to send.
987 */
988 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
989 ;
990
991 /* Send the character out.
992 * If the buffer address is in the CPM DPRAM, don't
993 * convert it.
994 */
995 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
996 pinfo);
997 *cpm_outp_addr = *string;
998
999 out_be16(&bdp->cbd_datlen, 1);
1000 setbits16(&bdp->cbd_sc, BD_SC_READY);
1001
1002 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
1003 bdp = bdbase;
1004 else
1005 bdp++;
1006
1007 /* if a LF, also do CR... */
1008 if (handle_linefeed && *string == 10) {
1009 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
1010 ;
1011
1012 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
1013 pinfo);
1014 *cpm_outp_addr = 13;
1015
1016 out_be16(&bdp->cbd_datlen, 1);
1017 setbits16(&bdp->cbd_sc, BD_SC_READY);
1018
1019 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
1020 bdp = bdbase;
1021 else
1022 bdp++;
1023 }
1024 }
1025
1026 /*
1027 * Finally, Wait for transmitter & holding register to empty
1028 * and restore the IER
1029 */
1030 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
1031 ;
1032
1033 pinfo->tx_cur = bdp;
1034 }
1035 #endif
1036
1037 #ifdef CONFIG_CONSOLE_POLL
1038 /* Serial polling routines for writing and reading from the uart while
1039 * in an interrupt or debug context.
1040 */
1041
1042 #define GDB_BUF_SIZE 512 /* power of 2, please */
1043
1044 static char poll_buf[GDB_BUF_SIZE];
1045 static char *pollp;
1046 static int poll_chars;
1047
1048 static int poll_wait_key(char *obuf, struct uart_cpm_port *pinfo)
1049 {
1050 u_char c, *cp;
1051 volatile cbd_t *bdp;
1052 int i;
1053
1054 /* Get the address of the host memory buffer.
1055 */
1056 bdp = pinfo->rx_cur;
1057 while (bdp->cbd_sc & BD_SC_EMPTY)
1058 ;
1059
1060 /* If the buffer address is in the CPM DPRAM, don't
1061 * convert it.
1062 */
1063 cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo);
1064
1065 if (obuf) {
1066 i = c = bdp->cbd_datlen;
1067 while (i-- > 0)
1068 *obuf++ = *cp++;
1069 } else
1070 c = *cp;
1071 bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID);
1072 bdp->cbd_sc |= BD_SC_EMPTY;
1073
1074 if (bdp->cbd_sc & BD_SC_WRAP)
1075 bdp = pinfo->rx_bd_base;
1076 else
1077 bdp++;
1078 pinfo->rx_cur = (cbd_t *)bdp;
1079
1080 return (int)c;
1081 }
1082
1083 static int cpm_get_poll_char(struct uart_port *port)
1084 {
1085 struct uart_cpm_port *pinfo =
1086 container_of(port, struct uart_cpm_port, port);
1087
1088 if (!serial_polled) {
1089 serial_polled = 1;
1090 poll_chars = 0;
1091 }
1092 if (poll_chars <= 0) {
1093 poll_chars = poll_wait_key(poll_buf, pinfo);
1094 pollp = poll_buf;
1095 }
1096 poll_chars--;
1097 return *pollp++;
1098 }
1099
1100 static void cpm_put_poll_char(struct uart_port *port,
1101 unsigned char c)
1102 {
1103 struct uart_cpm_port *pinfo =
1104 container_of(port, struct uart_cpm_port, port);
1105 static char ch[2];
1106
1107 ch[0] = (char)c;
1108 cpm_uart_early_write(pinfo, ch, 1, false);
1109 }
1110 #endif /* CONFIG_CONSOLE_POLL */
1111
1112 static const struct uart_ops cpm_uart_pops = {
1113 .tx_empty = cpm_uart_tx_empty,
1114 .set_mctrl = cpm_uart_set_mctrl,
1115 .get_mctrl = cpm_uart_get_mctrl,
1116 .stop_tx = cpm_uart_stop_tx,
1117 .start_tx = cpm_uart_start_tx,
1118 .stop_rx = cpm_uart_stop_rx,
1119 .break_ctl = cpm_uart_break_ctl,
1120 .startup = cpm_uart_startup,
1121 .shutdown = cpm_uart_shutdown,
1122 .set_termios = cpm_uart_set_termios,
1123 .type = cpm_uart_type,
1124 .release_port = cpm_uart_release_port,
1125 .request_port = cpm_uart_request_port,
1126 .config_port = cpm_uart_config_port,
1127 .verify_port = cpm_uart_verify_port,
1128 #ifdef CONFIG_CONSOLE_POLL
1129 .poll_get_char = cpm_get_poll_char,
1130 .poll_put_char = cpm_put_poll_char,
1131 #endif
1132 };
1133
1134 struct uart_cpm_port cpm_uart_ports[UART_NR];
1135
1136 static int cpm_uart_init_port(struct device_node *np,
1137 struct uart_cpm_port *pinfo)
1138 {
1139 const u32 *data;
1140 void __iomem *mem, *pram;
1141 int len;
1142 int ret;
1143 int i;
1144
1145 data = of_get_property(np, "clock", NULL);
1146 if (data) {
1147 struct clk *clk = clk_get(NULL, (const char*)data);
1148 if (!IS_ERR(clk))
1149 pinfo->clk = clk;
1150 }
1151 if (!pinfo->clk) {
1152 data = of_get_property(np, "fsl,cpm-brg", &len);
1153 if (!data || len != 4) {
1154 printk(KERN_ERR "CPM UART %s has no/invalid "
1155 "fsl,cpm-brg property.\n", np->name);
1156 return -EINVAL;
1157 }
1158 pinfo->brg = *data;
1159 }
1160
1161 data = of_get_property(np, "fsl,cpm-command", &len);
1162 if (!data || len != 4) {
1163 printk(KERN_ERR "CPM UART %s has no/invalid "
1164 "fsl,cpm-command property.\n", np->name);
1165 return -EINVAL;
1166 }
1167 pinfo->command = *data;
1168
1169 mem = of_iomap(np, 0);
1170 if (!mem)
1171 return -ENOMEM;
1172
1173 if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") ||
1174 of_device_is_compatible(np, "fsl,cpm2-scc-uart")) {
1175 pinfo->sccp = mem;
1176 pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np);
1177 } else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") ||
1178 of_device_is_compatible(np, "fsl,cpm2-smc-uart")) {
1179 pinfo->flags |= FLAG_SMC;
1180 pinfo->smcp = mem;
1181 pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np);
1182 } else {
1183 ret = -ENODEV;
1184 goto out_mem;
1185 }
1186
1187 if (!pram) {
1188 ret = -ENOMEM;
1189 goto out_mem;
1190 }
1191
1192 pinfo->tx_nrfifos = TX_NUM_FIFO;
1193 pinfo->tx_fifosize = TX_BUF_SIZE;
1194 pinfo->rx_nrfifos = RX_NUM_FIFO;
1195 pinfo->rx_fifosize = RX_BUF_SIZE;
1196
1197 pinfo->port.uartclk = ppc_proc_freq;
1198 pinfo->port.mapbase = (unsigned long)mem;
1199 pinfo->port.type = PORT_CPM;
1200 pinfo->port.ops = &cpm_uart_pops,
1201 pinfo->port.iotype = UPIO_MEM;
1202 pinfo->port.fifosize = pinfo->tx_nrfifos * pinfo->tx_fifosize;
1203 spin_lock_init(&pinfo->port.lock);
1204
1205 pinfo->port.irq = irq_of_parse_and_map(np, 0);
1206 if (pinfo->port.irq == NO_IRQ) {
1207 ret = -EINVAL;
1208 goto out_pram;
1209 }
1210
1211 for (i = 0; i < NUM_GPIOS; i++) {
1212 int gpio;
1213
1214 pinfo->gpios[i] = -1;
1215
1216 gpio = of_get_gpio(np, i);
1217
1218 if (gpio_is_valid(gpio)) {
1219 ret = gpio_request(gpio, "cpm_uart");
1220 if (ret) {
1221 pr_err("can't request gpio #%d: %d\n", i, ret);
1222 continue;
1223 }
1224 if (i == GPIO_RTS || i == GPIO_DTR)
1225 ret = gpio_direction_output(gpio, 0);
1226 else
1227 ret = gpio_direction_input(gpio);
1228 if (ret) {
1229 pr_err("can't set direction for gpio #%d: %d\n",
1230 i, ret);
1231 gpio_free(gpio);
1232 continue;
1233 }
1234 pinfo->gpios[i] = gpio;
1235 }
1236 }
1237
1238 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1239 udbg_putc = NULL;
1240 #endif
1241
1242 return cpm_uart_request_port(&pinfo->port);
1243
1244 out_pram:
1245 cpm_uart_unmap_pram(pinfo, pram);
1246 out_mem:
1247 iounmap(mem);
1248 return ret;
1249 }
1250
1251 #ifdef CONFIG_SERIAL_CPM_CONSOLE
1252 /*
1253 * Print a string to the serial port trying not to disturb
1254 * any possible real use of the port...
1255 *
1256 * Note that this is called with interrupts already disabled
1257 */
1258 static void cpm_uart_console_write(struct console *co, const char *s,
1259 u_int count)
1260 {
1261 struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index];
1262 unsigned long flags;
1263 int nolock = oops_in_progress;
1264
1265 if (unlikely(nolock)) {
1266 local_irq_save(flags);
1267 } else {
1268 spin_lock_irqsave(&pinfo->port.lock, flags);
1269 }
1270
1271 cpm_uart_early_write(pinfo, s, count, true);
1272
1273 if (unlikely(nolock)) {
1274 local_irq_restore(flags);
1275 } else {
1276 spin_unlock_irqrestore(&pinfo->port.lock, flags);
1277 }
1278 }
1279
1280
1281 static int __init cpm_uart_console_setup(struct console *co, char *options)
1282 {
1283 int baud = 38400;
1284 int bits = 8;
1285 int parity = 'n';
1286 int flow = 'n';
1287 int ret;
1288 struct uart_cpm_port *pinfo;
1289 struct uart_port *port;
1290
1291 struct device_node *np;
1292 int i = 0;
1293
1294 if (co->index >= UART_NR) {
1295 printk(KERN_ERR "cpm_uart: console index %d too high\n",
1296 co->index);
1297 return -ENODEV;
1298 }
1299
1300 for_each_node_by_type(np, "serial") {
1301 if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") &&
1302 !of_device_is_compatible(np, "fsl,cpm1-scc-uart") &&
1303 !of_device_is_compatible(np, "fsl,cpm2-smc-uart") &&
1304 !of_device_is_compatible(np, "fsl,cpm2-scc-uart"))
1305 continue;
1306
1307 if (i++ == co->index)
1308 break;
1309 }
1310
1311 if (!np)
1312 return -ENODEV;
1313
1314 pinfo = &cpm_uart_ports[co->index];
1315
1316 pinfo->flags |= FLAG_CONSOLE;
1317 port = &pinfo->port;
1318
1319 ret = cpm_uart_init_port(np, pinfo);
1320 of_node_put(np);
1321 if (ret)
1322 return ret;
1323
1324 if (options) {
1325 uart_parse_options(options, &baud, &parity, &bits, &flow);
1326 } else {
1327 if ((baud = uart_baudrate()) == -1)
1328 baud = 9600;
1329 }
1330
1331 if (IS_SMC(pinfo)) {
1332 out_be16(&pinfo->smcup->smc_brkcr, 0);
1333 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
1334 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
1335 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
1336 } else {
1337 out_be16(&pinfo->sccup->scc_brkcr, 0);
1338 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
1339 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
1340 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
1341 }
1342
1343 ret = cpm_uart_allocbuf(pinfo, 1);
1344
1345 if (ret)
1346 return ret;
1347
1348 cpm_uart_initbd(pinfo);
1349
1350 if (IS_SMC(pinfo))
1351 cpm_uart_init_smc(pinfo);
1352 else
1353 cpm_uart_init_scc(pinfo);
1354
1355 uart_set_options(port, co, baud, parity, bits, flow);
1356 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
1357
1358 return 0;
1359 }
1360
1361 static struct uart_driver cpm_reg;
1362 static struct console cpm_scc_uart_console = {
1363 .name = "ttyCPM",
1364 .write = cpm_uart_console_write,
1365 .device = uart_console_device,
1366 .setup = cpm_uart_console_setup,
1367 .flags = CON_PRINTBUFFER,
1368 .index = -1,
1369 .data = &cpm_reg,
1370 };
1371
1372 static int __init cpm_uart_console_init(void)
1373 {
1374 register_console(&cpm_scc_uart_console);
1375 return 0;
1376 }
1377
1378 console_initcall(cpm_uart_console_init);
1379
1380 #define CPM_UART_CONSOLE &cpm_scc_uart_console
1381 #else
1382 #define CPM_UART_CONSOLE NULL
1383 #endif
1384
1385 static struct uart_driver cpm_reg = {
1386 .owner = THIS_MODULE,
1387 .driver_name = "ttyCPM",
1388 .dev_name = "ttyCPM",
1389 .major = SERIAL_CPM_MAJOR,
1390 .minor = SERIAL_CPM_MINOR,
1391 .cons = CPM_UART_CONSOLE,
1392 .nr = UART_NR,
1393 };
1394
1395 static int probe_index;
1396
1397 static int cpm_uart_probe(struct platform_device *ofdev)
1398 {
1399 int index = probe_index++;
1400 struct uart_cpm_port *pinfo = &cpm_uart_ports[index];
1401 int ret;
1402
1403 pinfo->port.line = index;
1404
1405 if (index >= UART_NR)
1406 return -ENODEV;
1407
1408 platform_set_drvdata(ofdev, pinfo);
1409
1410 /* initialize the device pointer for the port */
1411 pinfo->port.dev = &ofdev->dev;
1412
1413 ret = cpm_uart_init_port(ofdev->dev.of_node, pinfo);
1414 if (ret)
1415 return ret;
1416
1417 return uart_add_one_port(&cpm_reg, &pinfo->port);
1418 }
1419
1420 static int cpm_uart_remove(struct platform_device *ofdev)
1421 {
1422 struct uart_cpm_port *pinfo = platform_get_drvdata(ofdev);
1423 return uart_remove_one_port(&cpm_reg, &pinfo->port);
1424 }
1425
1426 static const struct of_device_id cpm_uart_match[] = {
1427 {
1428 .compatible = "fsl,cpm1-smc-uart",
1429 },
1430 {
1431 .compatible = "fsl,cpm1-scc-uart",
1432 },
1433 {
1434 .compatible = "fsl,cpm2-smc-uart",
1435 },
1436 {
1437 .compatible = "fsl,cpm2-scc-uart",
1438 },
1439 {}
1440 };
1441 MODULE_DEVICE_TABLE(of, cpm_uart_match);
1442
1443 static struct platform_driver cpm_uart_driver = {
1444 .driver = {
1445 .name = "cpm_uart",
1446 .of_match_table = cpm_uart_match,
1447 },
1448 .probe = cpm_uart_probe,
1449 .remove = cpm_uart_remove,
1450 };
1451
1452 static int __init cpm_uart_init(void)
1453 {
1454 int ret = uart_register_driver(&cpm_reg);
1455 if (ret)
1456 return ret;
1457
1458 ret = platform_driver_register(&cpm_uart_driver);
1459 if (ret)
1460 uart_unregister_driver(&cpm_reg);
1461
1462 return ret;
1463 }
1464
1465 static void __exit cpm_uart_exit(void)
1466 {
1467 platform_driver_unregister(&cpm_uart_driver);
1468 uart_unregister_driver(&cpm_reg);
1469 }
1470
1471 module_init(cpm_uart_init);
1472 module_exit(cpm_uart_exit);
1473
1474 MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis");
1475 MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $");
1476 MODULE_LICENSE("GPL");
1477 MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR);
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