1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale lpuart serial port driver
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
8 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12 #include <linux/clk.h>
13 #include <linux/console.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dmapool.h>
18 #include <linux/irq.h>
19 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/of_dma.h>
23 #include <linux/serial_core.h>
24 #include <linux/slab.h>
25 #include <linux/tty_flip.h>
27 /* All registers are 8-bit width */
37 #define UARTMODEM 0x0d
38 #define UARTPFIFO 0x10
39 #define UARTCFIFO 0x11
40 #define UARTSFIFO 0x12
41 #define UARTTWFIFO 0x13
42 #define UARTTCFIFO 0x14
43 #define UARTRWFIFO 0x15
45 #define UARTBDH_LBKDIE 0x80
46 #define UARTBDH_RXEDGIE 0x40
47 #define UARTBDH_SBR_MASK 0x1f
49 #define UARTCR1_LOOPS 0x80
50 #define UARTCR1_RSRC 0x20
51 #define UARTCR1_M 0x10
52 #define UARTCR1_WAKE 0x08
53 #define UARTCR1_ILT 0x04
54 #define UARTCR1_PE 0x02
55 #define UARTCR1_PT 0x01
57 #define UARTCR2_TIE 0x80
58 #define UARTCR2_TCIE 0x40
59 #define UARTCR2_RIE 0x20
60 #define UARTCR2_ILIE 0x10
61 #define UARTCR2_TE 0x08
62 #define UARTCR2_RE 0x04
63 #define UARTCR2_RWU 0x02
64 #define UARTCR2_SBK 0x01
66 #define UARTSR1_TDRE 0x80
67 #define UARTSR1_TC 0x40
68 #define UARTSR1_RDRF 0x20
69 #define UARTSR1_IDLE 0x10
70 #define UARTSR1_OR 0x08
71 #define UARTSR1_NF 0x04
72 #define UARTSR1_FE 0x02
73 #define UARTSR1_PE 0x01
75 #define UARTCR3_R8 0x80
76 #define UARTCR3_T8 0x40
77 #define UARTCR3_TXDIR 0x20
78 #define UARTCR3_TXINV 0x10
79 #define UARTCR3_ORIE 0x08
80 #define UARTCR3_NEIE 0x04
81 #define UARTCR3_FEIE 0x02
82 #define UARTCR3_PEIE 0x01
84 #define UARTCR4_MAEN1 0x80
85 #define UARTCR4_MAEN2 0x40
86 #define UARTCR4_M10 0x20
87 #define UARTCR4_BRFA_MASK 0x1f
88 #define UARTCR4_BRFA_OFF 0
90 #define UARTCR5_TDMAS 0x80
91 #define UARTCR5_RDMAS 0x20
93 #define UARTMODEM_RXRTSE 0x08
94 #define UARTMODEM_TXRTSPOL 0x04
95 #define UARTMODEM_TXRTSE 0x02
96 #define UARTMODEM_TXCTSE 0x01
98 #define UARTPFIFO_TXFE 0x80
99 #define UARTPFIFO_FIFOSIZE_MASK 0x7
100 #define UARTPFIFO_TXSIZE_OFF 4
101 #define UARTPFIFO_RXFE 0x08
102 #define UARTPFIFO_RXSIZE_OFF 0
104 #define UARTCFIFO_TXFLUSH 0x80
105 #define UARTCFIFO_RXFLUSH 0x40
106 #define UARTCFIFO_RXOFE 0x04
107 #define UARTCFIFO_TXOFE 0x02
108 #define UARTCFIFO_RXUFE 0x01
110 #define UARTSFIFO_TXEMPT 0x80
111 #define UARTSFIFO_RXEMPT 0x40
112 #define UARTSFIFO_RXOF 0x04
113 #define UARTSFIFO_TXOF 0x02
114 #define UARTSFIFO_RXUF 0x01
116 /* 32-bit register definition */
117 #define UARTBAUD 0x00
118 #define UARTSTAT 0x04
119 #define UARTCTRL 0x08
120 #define UARTDATA 0x0C
121 #define UARTMATCH 0x10
122 #define UARTMODIR 0x14
123 #define UARTFIFO 0x18
124 #define UARTWATER 0x1c
126 #define UARTBAUD_MAEN1 0x80000000
127 #define UARTBAUD_MAEN2 0x40000000
128 #define UARTBAUD_M10 0x20000000
129 #define UARTBAUD_TDMAE 0x00800000
130 #define UARTBAUD_RDMAE 0x00200000
131 #define UARTBAUD_MATCFG 0x00400000
132 #define UARTBAUD_BOTHEDGE 0x00020000
133 #define UARTBAUD_RESYNCDIS 0x00010000
134 #define UARTBAUD_LBKDIE 0x00008000
135 #define UARTBAUD_RXEDGIE 0x00004000
136 #define UARTBAUD_SBNS 0x00002000
137 #define UARTBAUD_SBR 0x00000000
138 #define UARTBAUD_SBR_MASK 0x1fff
139 #define UARTBAUD_OSR_MASK 0x1f
140 #define UARTBAUD_OSR_SHIFT 24
142 #define UARTSTAT_LBKDIF 0x80000000
143 #define UARTSTAT_RXEDGIF 0x40000000
144 #define UARTSTAT_MSBF 0x20000000
145 #define UARTSTAT_RXINV 0x10000000
146 #define UARTSTAT_RWUID 0x08000000
147 #define UARTSTAT_BRK13 0x04000000
148 #define UARTSTAT_LBKDE 0x02000000
149 #define UARTSTAT_RAF 0x01000000
150 #define UARTSTAT_TDRE 0x00800000
151 #define UARTSTAT_TC 0x00400000
152 #define UARTSTAT_RDRF 0x00200000
153 #define UARTSTAT_IDLE 0x00100000
154 #define UARTSTAT_OR 0x00080000
155 #define UARTSTAT_NF 0x00040000
156 #define UARTSTAT_FE 0x00020000
157 #define UARTSTAT_PE 0x00010000
158 #define UARTSTAT_MA1F 0x00008000
159 #define UARTSTAT_M21F 0x00004000
161 #define UARTCTRL_R8T9 0x80000000
162 #define UARTCTRL_R9T8 0x40000000
163 #define UARTCTRL_TXDIR 0x20000000
164 #define UARTCTRL_TXINV 0x10000000
165 #define UARTCTRL_ORIE 0x08000000
166 #define UARTCTRL_NEIE 0x04000000
167 #define UARTCTRL_FEIE 0x02000000
168 #define UARTCTRL_PEIE 0x01000000
169 #define UARTCTRL_TIE 0x00800000
170 #define UARTCTRL_TCIE 0x00400000
171 #define UARTCTRL_RIE 0x00200000
172 #define UARTCTRL_ILIE 0x00100000
173 #define UARTCTRL_TE 0x00080000
174 #define UARTCTRL_RE 0x00040000
175 #define UARTCTRL_RWU 0x00020000
176 #define UARTCTRL_SBK 0x00010000
177 #define UARTCTRL_MA1IE 0x00008000
178 #define UARTCTRL_MA2IE 0x00004000
179 #define UARTCTRL_IDLECFG 0x00000100
180 #define UARTCTRL_LOOPS 0x00000080
181 #define UARTCTRL_DOZEEN 0x00000040
182 #define UARTCTRL_RSRC 0x00000020
183 #define UARTCTRL_M 0x00000010
184 #define UARTCTRL_WAKE 0x00000008
185 #define UARTCTRL_ILT 0x00000004
186 #define UARTCTRL_PE 0x00000002
187 #define UARTCTRL_PT 0x00000001
189 #define UARTDATA_NOISY 0x00008000
190 #define UARTDATA_PARITYE 0x00004000
191 #define UARTDATA_FRETSC 0x00002000
192 #define UARTDATA_RXEMPT 0x00001000
193 #define UARTDATA_IDLINE 0x00000800
194 #define UARTDATA_MASK 0x3ff
196 #define UARTMODIR_IREN 0x00020000
197 #define UARTMODIR_TXCTSSRC 0x00000020
198 #define UARTMODIR_TXCTSC 0x00000010
199 #define UARTMODIR_RXRTSE 0x00000008
200 #define UARTMODIR_TXRTSPOL 0x00000004
201 #define UARTMODIR_TXRTSE 0x00000002
202 #define UARTMODIR_TXCTSE 0x00000001
204 #define UARTFIFO_TXEMPT 0x00800000
205 #define UARTFIFO_RXEMPT 0x00400000
206 #define UARTFIFO_TXOF 0x00020000
207 #define UARTFIFO_RXUF 0x00010000
208 #define UARTFIFO_TXFLUSH 0x00008000
209 #define UARTFIFO_RXFLUSH 0x00004000
210 #define UARTFIFO_TXOFE 0x00000200
211 #define UARTFIFO_RXUFE 0x00000100
212 #define UARTFIFO_TXFE 0x00000080
213 #define UARTFIFO_FIFOSIZE_MASK 0x7
214 #define UARTFIFO_TXSIZE_OFF 4
215 #define UARTFIFO_RXFE 0x00000008
216 #define UARTFIFO_RXSIZE_OFF 0
218 #define UARTWATER_COUNT_MASK 0xff
219 #define UARTWATER_TXCNT_OFF 8
220 #define UARTWATER_RXCNT_OFF 24
221 #define UARTWATER_WATER_MASK 0xff
222 #define UARTWATER_TXWATER_OFF 0
223 #define UARTWATER_RXWATER_OFF 16
225 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
226 #define DMA_RX_TIMEOUT (10)
228 #define DRIVER_NAME "fsl-lpuart"
229 #define DEV_NAME "ttyLP"
232 /* IMX lpuart has four extra unused regs located at the beginning */
233 #define IMX_REG_OFF 0x10
236 struct uart_port port
;
238 unsigned int txfifo_size
;
239 unsigned int rxfifo_size
;
241 bool lpuart_dma_tx_use
;
242 bool lpuart_dma_rx_use
;
243 struct dma_chan
*dma_tx_chan
;
244 struct dma_chan
*dma_rx_chan
;
245 struct dma_async_tx_descriptor
*dma_tx_desc
;
246 struct dma_async_tx_descriptor
*dma_rx_desc
;
247 dma_cookie_t dma_tx_cookie
;
248 dma_cookie_t dma_rx_cookie
;
249 unsigned int dma_tx_bytes
;
250 unsigned int dma_rx_bytes
;
251 bool dma_tx_in_progress
;
252 unsigned int dma_rx_timeout
;
253 struct timer_list lpuart_timer
;
254 struct scatterlist rx_sgl
, tx_sgl
[2];
255 struct circ_buf rx_ring
;
256 int rx_dma_rng_buf_len
;
257 unsigned int dma_tx_nents
;
258 wait_queue_head_t dma_wait
;
261 struct lpuart_soc_data
{
266 static const struct lpuart_soc_data vf_data
= {
270 static const struct lpuart_soc_data ls_data
= {
271 .iotype
= UPIO_MEM32BE
,
274 static struct lpuart_soc_data imx_data
= {
275 .iotype
= UPIO_MEM32
,
276 .reg_off
= IMX_REG_OFF
,
279 static const struct of_device_id lpuart_dt_ids
[] = {
280 { .compatible
= "fsl,vf610-lpuart", .data
= &vf_data
, },
281 { .compatible
= "fsl,ls1021a-lpuart", .data
= &ls_data
, },
282 { .compatible
= "fsl,imx7ulp-lpuart", .data
= &imx_data
, },
285 MODULE_DEVICE_TABLE(of
, lpuart_dt_ids
);
287 /* Forward declare this for the dma callbacks*/
288 static void lpuart_dma_tx_complete(void *arg
);
290 static inline u32
lpuart32_read(struct uart_port
*port
, u32 off
)
292 switch (port
->iotype
) {
294 return readl(port
->membase
+ off
);
296 return ioread32be(port
->membase
+ off
);
302 static inline void lpuart32_write(struct uart_port
*port
, u32 val
,
305 switch (port
->iotype
) {
307 writel(val
, port
->membase
+ off
);
310 iowrite32be(val
, port
->membase
+ off
);
315 static void lpuart_stop_tx(struct uart_port
*port
)
319 temp
= readb(port
->membase
+ UARTCR2
);
320 temp
&= ~(UARTCR2_TIE
| UARTCR2_TCIE
);
321 writeb(temp
, port
->membase
+ UARTCR2
);
324 static void lpuart32_stop_tx(struct uart_port
*port
)
328 temp
= lpuart32_read(port
, UARTCTRL
);
329 temp
&= ~(UARTCTRL_TIE
| UARTCTRL_TCIE
);
330 lpuart32_write(port
, temp
, UARTCTRL
);
333 static void lpuart_stop_rx(struct uart_port
*port
)
337 temp
= readb(port
->membase
+ UARTCR2
);
338 writeb(temp
& ~UARTCR2_RE
, port
->membase
+ UARTCR2
);
341 static void lpuart32_stop_rx(struct uart_port
*port
)
345 temp
= lpuart32_read(port
, UARTCTRL
);
346 lpuart32_write(port
, temp
& ~UARTCTRL_RE
, UARTCTRL
);
349 static void lpuart_dma_tx(struct lpuart_port
*sport
)
351 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
352 struct scatterlist
*sgl
= sport
->tx_sgl
;
353 struct device
*dev
= sport
->port
.dev
;
356 if (sport
->dma_tx_in_progress
)
359 sport
->dma_tx_bytes
= uart_circ_chars_pending(xmit
);
361 if (xmit
->tail
< xmit
->head
|| xmit
->head
== 0) {
362 sport
->dma_tx_nents
= 1;
363 sg_init_one(sgl
, xmit
->buf
+ xmit
->tail
, sport
->dma_tx_bytes
);
365 sport
->dma_tx_nents
= 2;
366 sg_init_table(sgl
, 2);
367 sg_set_buf(sgl
, xmit
->buf
+ xmit
->tail
,
368 UART_XMIT_SIZE
- xmit
->tail
);
369 sg_set_buf(sgl
+ 1, xmit
->buf
, xmit
->head
);
372 ret
= dma_map_sg(dev
, sgl
, sport
->dma_tx_nents
, DMA_TO_DEVICE
);
374 dev_err(dev
, "DMA mapping error for TX.\n");
378 sport
->dma_tx_desc
= dmaengine_prep_slave_sg(sport
->dma_tx_chan
, sgl
,
380 DMA_MEM_TO_DEV
, DMA_PREP_INTERRUPT
);
381 if (!sport
->dma_tx_desc
) {
382 dma_unmap_sg(dev
, sgl
, sport
->dma_tx_nents
, DMA_TO_DEVICE
);
383 dev_err(dev
, "Cannot prepare TX slave DMA!\n");
387 sport
->dma_tx_desc
->callback
= lpuart_dma_tx_complete
;
388 sport
->dma_tx_desc
->callback_param
= sport
;
389 sport
->dma_tx_in_progress
= true;
390 sport
->dma_tx_cookie
= dmaengine_submit(sport
->dma_tx_desc
);
391 dma_async_issue_pending(sport
->dma_tx_chan
);
394 static void lpuart_dma_tx_complete(void *arg
)
396 struct lpuart_port
*sport
= arg
;
397 struct scatterlist
*sgl
= &sport
->tx_sgl
[0];
398 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
401 spin_lock_irqsave(&sport
->port
.lock
, flags
);
403 dma_unmap_sg(sport
->port
.dev
, sgl
, sport
->dma_tx_nents
, DMA_TO_DEVICE
);
405 xmit
->tail
= (xmit
->tail
+ sport
->dma_tx_bytes
) & (UART_XMIT_SIZE
- 1);
407 sport
->port
.icount
.tx
+= sport
->dma_tx_bytes
;
408 sport
->dma_tx_in_progress
= false;
409 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
411 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
412 uart_write_wakeup(&sport
->port
);
414 if (waitqueue_active(&sport
->dma_wait
)) {
415 wake_up(&sport
->dma_wait
);
419 spin_lock_irqsave(&sport
->port
.lock
, flags
);
421 if (!uart_circ_empty(xmit
) && !uart_tx_stopped(&sport
->port
))
422 lpuart_dma_tx(sport
);
424 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
427 static int lpuart_dma_tx_request(struct uart_port
*port
)
429 struct lpuart_port
*sport
= container_of(port
,
430 struct lpuart_port
, port
);
431 struct dma_slave_config dma_tx_sconfig
= {};
434 dma_tx_sconfig
.dst_addr
= sport
->port
.mapbase
+ UARTDR
;
435 dma_tx_sconfig
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
436 dma_tx_sconfig
.dst_maxburst
= 1;
437 dma_tx_sconfig
.direction
= DMA_MEM_TO_DEV
;
438 ret
= dmaengine_slave_config(sport
->dma_tx_chan
, &dma_tx_sconfig
);
441 dev_err(sport
->port
.dev
,
442 "DMA slave config failed, err = %d\n", ret
);
449 static void lpuart_flush_buffer(struct uart_port
*port
)
451 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
453 if (sport
->lpuart_dma_tx_use
) {
454 if (sport
->dma_tx_in_progress
) {
455 dma_unmap_sg(sport
->port
.dev
, &sport
->tx_sgl
[0],
456 sport
->dma_tx_nents
, DMA_TO_DEVICE
);
457 sport
->dma_tx_in_progress
= false;
459 dmaengine_terminate_all(sport
->dma_tx_chan
);
463 #if defined(CONFIG_CONSOLE_POLL)
465 static int lpuart_poll_init(struct uart_port
*port
)
467 struct lpuart_port
*sport
= container_of(port
,
468 struct lpuart_port
, port
);
472 sport
->port
.fifosize
= 0;
474 spin_lock_irqsave(&sport
->port
.lock
, flags
);
475 /* Disable Rx & Tx */
476 writeb(0, sport
->port
.membase
+ UARTCR2
);
478 temp
= readb(sport
->port
.membase
+ UARTPFIFO
);
479 /* Enable Rx and Tx FIFO */
480 writeb(temp
| UARTPFIFO_RXFE
| UARTPFIFO_TXFE
,
481 sport
->port
.membase
+ UARTPFIFO
);
483 /* flush Tx and Rx FIFO */
484 writeb(UARTCFIFO_TXFLUSH
| UARTCFIFO_RXFLUSH
,
485 sport
->port
.membase
+ UARTCFIFO
);
487 /* explicitly clear RDRF */
488 if (readb(sport
->port
.membase
+ UARTSR1
) & UARTSR1_RDRF
) {
489 readb(sport
->port
.membase
+ UARTDR
);
490 writeb(UARTSFIFO_RXUF
, sport
->port
.membase
+ UARTSFIFO
);
493 writeb(0, sport
->port
.membase
+ UARTTWFIFO
);
494 writeb(1, sport
->port
.membase
+ UARTRWFIFO
);
496 /* Enable Rx and Tx */
497 writeb(UARTCR2_RE
| UARTCR2_TE
, sport
->port
.membase
+ UARTCR2
);
498 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
503 static void lpuart_poll_put_char(struct uart_port
*port
, unsigned char c
)
506 while (!(readb(port
->membase
+ UARTSR1
) & UARTSR1_TDRE
))
509 writeb(c
, port
->membase
+ UARTDR
);
512 static int lpuart_poll_get_char(struct uart_port
*port
)
514 if (!(readb(port
->membase
+ UARTSR1
) & UARTSR1_RDRF
))
517 return readb(port
->membase
+ UARTDR
);
520 static int lpuart32_poll_init(struct uart_port
*port
)
523 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
526 sport
->port
.fifosize
= 0;
528 spin_lock_irqsave(&sport
->port
.lock
, flags
);
530 /* Disable Rx & Tx */
531 writel(0, sport
->port
.membase
+ UARTCTRL
);
533 temp
= readl(sport
->port
.membase
+ UARTFIFO
);
535 /* Enable Rx and Tx FIFO */
536 writel(temp
| UARTFIFO_RXFE
| UARTFIFO_TXFE
,
537 sport
->port
.membase
+ UARTFIFO
);
539 /* flush Tx and Rx FIFO */
540 writel(UARTFIFO_TXFLUSH
| UARTFIFO_RXFLUSH
,
541 sport
->port
.membase
+ UARTFIFO
);
543 /* explicitly clear RDRF */
544 if (readl(sport
->port
.membase
+ UARTSTAT
) & UARTSTAT_RDRF
) {
545 readl(sport
->port
.membase
+ UARTDATA
);
546 writel(UARTFIFO_RXUF
, sport
->port
.membase
+ UARTFIFO
);
549 /* Enable Rx and Tx */
550 writel(UARTCTRL_RE
| UARTCTRL_TE
, sport
->port
.membase
+ UARTCTRL
);
551 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
556 static void lpuart32_poll_put_char(struct uart_port
*port
, unsigned char c
)
558 while (!(readl(port
->membase
+ UARTSTAT
) & UARTSTAT_TDRE
))
561 writel(c
, port
->membase
+ UARTDATA
);
564 static int lpuart32_poll_get_char(struct uart_port
*port
)
566 if (!(readl(port
->membase
+ UARTSTAT
) & UARTSTAT_RDRF
))
569 return readl(port
->membase
+ UARTDATA
);
573 static inline void lpuart_transmit_buffer(struct lpuart_port
*sport
)
575 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
577 while (!uart_circ_empty(xmit
) &&
578 (readb(sport
->port
.membase
+ UARTTCFIFO
) < sport
->txfifo_size
)) {
579 writeb(xmit
->buf
[xmit
->tail
], sport
->port
.membase
+ UARTDR
);
580 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
581 sport
->port
.icount
.tx
++;
584 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
585 uart_write_wakeup(&sport
->port
);
587 if (uart_circ_empty(xmit
))
588 lpuart_stop_tx(&sport
->port
);
591 static inline void lpuart32_transmit_buffer(struct lpuart_port
*sport
)
593 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
596 txcnt
= lpuart32_read(&sport
->port
, UARTWATER
);
597 txcnt
= txcnt
>> UARTWATER_TXCNT_OFF
;
598 txcnt
&= UARTWATER_COUNT_MASK
;
599 while (!uart_circ_empty(xmit
) && (txcnt
< sport
->txfifo_size
)) {
600 lpuart32_write(&sport
->port
, xmit
->buf
[xmit
->tail
], UARTDATA
);
601 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
602 sport
->port
.icount
.tx
++;
603 txcnt
= lpuart32_read(&sport
->port
, UARTWATER
);
604 txcnt
= txcnt
>> UARTWATER_TXCNT_OFF
;
605 txcnt
&= UARTWATER_COUNT_MASK
;
608 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
609 uart_write_wakeup(&sport
->port
);
611 if (uart_circ_empty(xmit
))
612 lpuart32_stop_tx(&sport
->port
);
615 static void lpuart_start_tx(struct uart_port
*port
)
617 struct lpuart_port
*sport
= container_of(port
,
618 struct lpuart_port
, port
);
619 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
622 temp
= readb(port
->membase
+ UARTCR2
);
623 writeb(temp
| UARTCR2_TIE
, port
->membase
+ UARTCR2
);
625 if (sport
->lpuart_dma_tx_use
) {
626 if (!uart_circ_empty(xmit
) && !uart_tx_stopped(port
))
627 lpuart_dma_tx(sport
);
629 if (readb(port
->membase
+ UARTSR1
) & UARTSR1_TDRE
)
630 lpuart_transmit_buffer(sport
);
634 static void lpuart32_start_tx(struct uart_port
*port
)
636 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
639 temp
= lpuart32_read(port
, UARTCTRL
);
640 lpuart32_write(port
, temp
| UARTCTRL_TIE
, UARTCTRL
);
642 if (lpuart32_read(port
, UARTSTAT
) & UARTSTAT_TDRE
)
643 lpuart32_transmit_buffer(sport
);
646 /* return TIOCSER_TEMT when transmitter is not busy */
647 static unsigned int lpuart_tx_empty(struct uart_port
*port
)
649 struct lpuart_port
*sport
= container_of(port
,
650 struct lpuart_port
, port
);
651 unsigned char sr1
= readb(port
->membase
+ UARTSR1
);
652 unsigned char sfifo
= readb(port
->membase
+ UARTSFIFO
);
654 if (sport
->dma_tx_in_progress
)
657 if (sr1
& UARTSR1_TC
&& sfifo
& UARTSFIFO_TXEMPT
)
663 static unsigned int lpuart32_tx_empty(struct uart_port
*port
)
665 return (lpuart32_read(port
, UARTSTAT
) & UARTSTAT_TC
) ?
669 static bool lpuart_is_32(struct lpuart_port
*sport
)
671 return sport
->port
.iotype
== UPIO_MEM32
||
672 sport
->port
.iotype
== UPIO_MEM32BE
;
675 static irqreturn_t
lpuart_txint(int irq
, void *dev_id
)
677 struct lpuart_port
*sport
= dev_id
;
678 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
681 spin_lock_irqsave(&sport
->port
.lock
, flags
);
682 if (sport
->port
.x_char
) {
683 if (lpuart_is_32(sport
))
684 lpuart32_write(&sport
->port
, sport
->port
.x_char
, UARTDATA
);
686 writeb(sport
->port
.x_char
, sport
->port
.membase
+ UARTDR
);
690 if (uart_circ_empty(xmit
) || uart_tx_stopped(&sport
->port
)) {
691 if (lpuart_is_32(sport
))
692 lpuart32_stop_tx(&sport
->port
);
694 lpuart_stop_tx(&sport
->port
);
698 if (lpuart_is_32(sport
))
699 lpuart32_transmit_buffer(sport
);
701 lpuart_transmit_buffer(sport
);
703 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
704 uart_write_wakeup(&sport
->port
);
707 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
711 static irqreturn_t
lpuart_rxint(int irq
, void *dev_id
)
713 struct lpuart_port
*sport
= dev_id
;
714 unsigned int flg
, ignored
= 0;
715 struct tty_port
*port
= &sport
->port
.state
->port
;
717 unsigned char rx
, sr
;
719 spin_lock_irqsave(&sport
->port
.lock
, flags
);
721 while (!(readb(sport
->port
.membase
+ UARTSFIFO
) & UARTSFIFO_RXEMPT
)) {
723 sport
->port
.icount
.rx
++;
725 * to clear the FE, OR, NF, FE, PE flags,
726 * read SR1 then read DR
728 sr
= readb(sport
->port
.membase
+ UARTSR1
);
729 rx
= readb(sport
->port
.membase
+ UARTDR
);
731 if (uart_handle_sysrq_char(&sport
->port
, (unsigned char)rx
))
734 if (sr
& (UARTSR1_PE
| UARTSR1_OR
| UARTSR1_FE
)) {
736 sport
->port
.icount
.parity
++;
737 else if (sr
& UARTSR1_FE
)
738 sport
->port
.icount
.frame
++;
741 sport
->port
.icount
.overrun
++;
743 if (sr
& sport
->port
.ignore_status_mask
) {
749 sr
&= sport
->port
.read_status_mask
;
753 else if (sr
& UARTSR1_FE
)
760 sport
->port
.sysrq
= 0;
764 tty_insert_flip_char(port
, rx
, flg
);
768 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
770 tty_flip_buffer_push(port
);
774 static irqreturn_t
lpuart32_rxint(int irq
, void *dev_id
)
776 struct lpuart_port
*sport
= dev_id
;
777 unsigned int flg
, ignored
= 0;
778 struct tty_port
*port
= &sport
->port
.state
->port
;
780 unsigned long rx
, sr
;
782 spin_lock_irqsave(&sport
->port
.lock
, flags
);
784 while (!(lpuart32_read(&sport
->port
, UARTFIFO
) & UARTFIFO_RXEMPT
)) {
786 sport
->port
.icount
.rx
++;
788 * to clear the FE, OR, NF, FE, PE flags,
789 * read STAT then read DATA reg
791 sr
= lpuart32_read(&sport
->port
, UARTSTAT
);
792 rx
= lpuart32_read(&sport
->port
, UARTDATA
);
795 if (uart_handle_sysrq_char(&sport
->port
, (unsigned char)rx
))
798 if (sr
& (UARTSTAT_PE
| UARTSTAT_OR
| UARTSTAT_FE
)) {
799 if (sr
& UARTSTAT_PE
)
800 sport
->port
.icount
.parity
++;
801 else if (sr
& UARTSTAT_FE
)
802 sport
->port
.icount
.frame
++;
804 if (sr
& UARTSTAT_OR
)
805 sport
->port
.icount
.overrun
++;
807 if (sr
& sport
->port
.ignore_status_mask
) {
813 sr
&= sport
->port
.read_status_mask
;
815 if (sr
& UARTSTAT_PE
)
817 else if (sr
& UARTSTAT_FE
)
820 if (sr
& UARTSTAT_OR
)
824 sport
->port
.sysrq
= 0;
828 tty_insert_flip_char(port
, rx
, flg
);
832 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
834 tty_flip_buffer_push(port
);
838 static irqreturn_t
lpuart_int(int irq
, void *dev_id
)
840 struct lpuart_port
*sport
= dev_id
;
843 sts
= readb(sport
->port
.membase
+ UARTSR1
);
845 if (sts
& UARTSR1_RDRF
)
846 lpuart_rxint(irq
, dev_id
);
848 if (sts
& UARTSR1_TDRE
)
849 lpuart_txint(irq
, dev_id
);
854 static irqreturn_t
lpuart32_int(int irq
, void *dev_id
)
856 struct lpuart_port
*sport
= dev_id
;
857 unsigned long sts
, rxcount
;
859 sts
= lpuart32_read(&sport
->port
, UARTSTAT
);
860 rxcount
= lpuart32_read(&sport
->port
, UARTWATER
);
861 rxcount
= rxcount
>> UARTWATER_RXCNT_OFF
;
863 if (sts
& UARTSTAT_RDRF
|| rxcount
> 0)
864 lpuart32_rxint(irq
, dev_id
);
866 if ((sts
& UARTSTAT_TDRE
) &&
867 !(lpuart32_read(&sport
->port
, UARTBAUD
) & UARTBAUD_TDMAE
))
868 lpuart_txint(irq
, dev_id
);
870 lpuart32_write(&sport
->port
, sts
, UARTSTAT
);
874 static void lpuart_copy_rx_to_tty(struct lpuart_port
*sport
)
876 struct tty_port
*port
= &sport
->port
.state
->port
;
877 struct dma_tx_state state
;
878 enum dma_status dmastat
;
879 struct circ_buf
*ring
= &sport
->rx_ring
;
884 sr
= readb(sport
->port
.membase
+ UARTSR1
);
886 if (sr
& (UARTSR1_PE
| UARTSR1_FE
)) {
887 /* Read DR to clear the error flags */
888 readb(sport
->port
.membase
+ UARTDR
);
891 sport
->port
.icount
.parity
++;
892 else if (sr
& UARTSR1_FE
)
893 sport
->port
.icount
.frame
++;
896 async_tx_ack(sport
->dma_rx_desc
);
898 spin_lock_irqsave(&sport
->port
.lock
, flags
);
900 dmastat
= dmaengine_tx_status(sport
->dma_rx_chan
,
901 sport
->dma_rx_cookie
,
904 if (dmastat
== DMA_ERROR
) {
905 dev_err(sport
->port
.dev
, "Rx DMA transfer failed!\n");
906 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
910 /* CPU claims ownership of RX DMA buffer */
911 dma_sync_sg_for_cpu(sport
->port
.dev
, &sport
->rx_sgl
, 1, DMA_FROM_DEVICE
);
914 * ring->head points to the end of data already written by the DMA.
915 * ring->tail points to the beginning of data to be read by the
917 * The current transfer size should not be larger than the dma buffer
920 ring
->head
= sport
->rx_sgl
.length
- state
.residue
;
921 BUG_ON(ring
->head
> sport
->rx_sgl
.length
);
923 * At this point ring->head may point to the first byte right after the
924 * last byte of the dma buffer:
925 * 0 <= ring->head <= sport->rx_sgl.length
927 * However ring->tail must always points inside the dma buffer:
928 * 0 <= ring->tail <= sport->rx_sgl.length - 1
930 * Since we use a ring buffer, we have to handle the case
931 * where head is lower than tail. In such a case, we first read from
932 * tail to the end of the buffer then reset tail.
934 if (ring
->head
< ring
->tail
) {
935 count
= sport
->rx_sgl
.length
- ring
->tail
;
937 tty_insert_flip_string(port
, ring
->buf
+ ring
->tail
, count
);
939 sport
->port
.icount
.rx
+= count
;
942 /* Finally we read data from tail to head */
943 if (ring
->tail
< ring
->head
) {
944 count
= ring
->head
- ring
->tail
;
945 tty_insert_flip_string(port
, ring
->buf
+ ring
->tail
, count
);
946 /* Wrap ring->head if needed */
947 if (ring
->head
>= sport
->rx_sgl
.length
)
949 ring
->tail
= ring
->head
;
950 sport
->port
.icount
.rx
+= count
;
953 dma_sync_sg_for_device(sport
->port
.dev
, &sport
->rx_sgl
, 1,
956 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
958 tty_flip_buffer_push(port
);
959 mod_timer(&sport
->lpuart_timer
, jiffies
+ sport
->dma_rx_timeout
);
962 static void lpuart_dma_rx_complete(void *arg
)
964 struct lpuart_port
*sport
= arg
;
966 lpuart_copy_rx_to_tty(sport
);
969 static void lpuart_timer_func(struct timer_list
*t
)
971 struct lpuart_port
*sport
= from_timer(sport
, t
, lpuart_timer
);
973 lpuart_copy_rx_to_tty(sport
);
976 static inline int lpuart_start_rx_dma(struct lpuart_port
*sport
)
978 struct dma_slave_config dma_rx_sconfig
= {};
979 struct circ_buf
*ring
= &sport
->rx_ring
;
982 struct tty_port
*port
= &sport
->port
.state
->port
;
983 struct tty_struct
*tty
= port
->tty
;
984 struct ktermios
*termios
= &tty
->termios
;
986 baud
= tty_get_baud_rate(tty
);
988 bits
= (termios
->c_cflag
& CSIZE
) == CS7
? 9 : 10;
989 if (termios
->c_cflag
& PARENB
)
993 * Calculate length of one DMA buffer size to keep latency below
994 * 10ms at any baud rate.
996 sport
->rx_dma_rng_buf_len
= (DMA_RX_TIMEOUT
* baud
/ bits
/ 1000) * 2;
997 sport
->rx_dma_rng_buf_len
= (1 << (fls(sport
->rx_dma_rng_buf_len
) - 1));
998 if (sport
->rx_dma_rng_buf_len
< 16)
999 sport
->rx_dma_rng_buf_len
= 16;
1001 ring
->buf
= kmalloc(sport
->rx_dma_rng_buf_len
, GFP_ATOMIC
);
1003 dev_err(sport
->port
.dev
, "Ring buf alloc failed\n");
1007 sg_init_one(&sport
->rx_sgl
, ring
->buf
, sport
->rx_dma_rng_buf_len
);
1008 sg_set_buf(&sport
->rx_sgl
, ring
->buf
, sport
->rx_dma_rng_buf_len
);
1009 nent
= dma_map_sg(sport
->port
.dev
, &sport
->rx_sgl
, 1, DMA_FROM_DEVICE
);
1012 dev_err(sport
->port
.dev
, "DMA Rx mapping error\n");
1016 dma_rx_sconfig
.src_addr
= sport
->port
.mapbase
+ UARTDR
;
1017 dma_rx_sconfig
.src_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
1018 dma_rx_sconfig
.src_maxburst
= 1;
1019 dma_rx_sconfig
.direction
= DMA_DEV_TO_MEM
;
1020 ret
= dmaengine_slave_config(sport
->dma_rx_chan
, &dma_rx_sconfig
);
1023 dev_err(sport
->port
.dev
,
1024 "DMA Rx slave config failed, err = %d\n", ret
);
1028 sport
->dma_rx_desc
= dmaengine_prep_dma_cyclic(sport
->dma_rx_chan
,
1029 sg_dma_address(&sport
->rx_sgl
),
1030 sport
->rx_sgl
.length
,
1031 sport
->rx_sgl
.length
/ 2,
1033 DMA_PREP_INTERRUPT
);
1034 if (!sport
->dma_rx_desc
) {
1035 dev_err(sport
->port
.dev
, "Cannot prepare cyclic DMA\n");
1039 sport
->dma_rx_desc
->callback
= lpuart_dma_rx_complete
;
1040 sport
->dma_rx_desc
->callback_param
= sport
;
1041 sport
->dma_rx_cookie
= dmaengine_submit(sport
->dma_rx_desc
);
1042 dma_async_issue_pending(sport
->dma_rx_chan
);
1044 writeb(readb(sport
->port
.membase
+ UARTCR5
) | UARTCR5_RDMAS
,
1045 sport
->port
.membase
+ UARTCR5
);
1050 static void lpuart_dma_rx_free(struct uart_port
*port
)
1052 struct lpuart_port
*sport
= container_of(port
,
1053 struct lpuart_port
, port
);
1055 if (sport
->dma_rx_chan
)
1056 dmaengine_terminate_all(sport
->dma_rx_chan
);
1058 dma_unmap_sg(sport
->port
.dev
, &sport
->rx_sgl
, 1, DMA_FROM_DEVICE
);
1059 kfree(sport
->rx_ring
.buf
);
1060 sport
->rx_ring
.tail
= 0;
1061 sport
->rx_ring
.head
= 0;
1062 sport
->dma_rx_desc
= NULL
;
1063 sport
->dma_rx_cookie
= -EINVAL
;
1066 static int lpuart_config_rs485(struct uart_port
*port
,
1067 struct serial_rs485
*rs485
)
1069 struct lpuart_port
*sport
= container_of(port
,
1070 struct lpuart_port
, port
);
1072 u8 modem
= readb(sport
->port
.membase
+ UARTMODEM
) &
1073 ~(UARTMODEM_TXRTSPOL
| UARTMODEM_TXRTSE
);
1074 writeb(modem
, sport
->port
.membase
+ UARTMODEM
);
1076 /* clear unsupported configurations */
1077 rs485
->delay_rts_before_send
= 0;
1078 rs485
->delay_rts_after_send
= 0;
1079 rs485
->flags
&= ~SER_RS485_RX_DURING_TX
;
1081 if (rs485
->flags
& SER_RS485_ENABLED
) {
1082 /* Enable auto RS-485 RTS mode */
1083 modem
|= UARTMODEM_TXRTSE
;
1086 * RTS needs to be logic HIGH either during transer _or_ after
1087 * transfer, other variants are not supported by the hardware.
1090 if (!(rs485
->flags
& (SER_RS485_RTS_ON_SEND
|
1091 SER_RS485_RTS_AFTER_SEND
)))
1092 rs485
->flags
|= SER_RS485_RTS_ON_SEND
;
1094 if (rs485
->flags
& SER_RS485_RTS_ON_SEND
&&
1095 rs485
->flags
& SER_RS485_RTS_AFTER_SEND
)
1096 rs485
->flags
&= ~SER_RS485_RTS_AFTER_SEND
;
1099 * The hardware defaults to RTS logic HIGH while transfer.
1100 * Switch polarity in case RTS shall be logic HIGH
1102 * Note: UART is assumed to be active high.
1104 if (rs485
->flags
& SER_RS485_RTS_ON_SEND
)
1105 modem
&= ~UARTMODEM_TXRTSPOL
;
1106 else if (rs485
->flags
& SER_RS485_RTS_AFTER_SEND
)
1107 modem
|= UARTMODEM_TXRTSPOL
;
1110 /* Store the new configuration */
1111 sport
->port
.rs485
= *rs485
;
1113 writeb(modem
, sport
->port
.membase
+ UARTMODEM
);
1117 static unsigned int lpuart_get_mctrl(struct uart_port
*port
)
1119 unsigned int temp
= 0;
1122 reg
= readb(port
->membase
+ UARTMODEM
);
1123 if (reg
& UARTMODEM_TXCTSE
)
1126 if (reg
& UARTMODEM_RXRTSE
)
1132 static unsigned int lpuart32_get_mctrl(struct uart_port
*port
)
1134 unsigned int temp
= 0;
1137 reg
= lpuart32_read(port
, UARTMODIR
);
1138 if (reg
& UARTMODIR_TXCTSE
)
1141 if (reg
& UARTMODIR_RXRTSE
)
1147 static void lpuart_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
1150 struct lpuart_port
*sport
= container_of(port
,
1151 struct lpuart_port
, port
);
1153 /* Make sure RXRTSE bit is not set when RS485 is enabled */
1154 if (!(sport
->port
.rs485
.flags
& SER_RS485_ENABLED
)) {
1155 temp
= readb(sport
->port
.membase
+ UARTMODEM
) &
1156 ~(UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1158 if (mctrl
& TIOCM_RTS
)
1159 temp
|= UARTMODEM_RXRTSE
;
1161 if (mctrl
& TIOCM_CTS
)
1162 temp
|= UARTMODEM_TXCTSE
;
1164 writeb(temp
, port
->membase
+ UARTMODEM
);
1168 static void lpuart32_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
1172 temp
= lpuart32_read(port
, UARTMODIR
) &
1173 ~(UARTMODIR_RXRTSE
| UARTMODIR_TXCTSE
);
1175 if (mctrl
& TIOCM_RTS
)
1176 temp
|= UARTMODIR_RXRTSE
;
1178 if (mctrl
& TIOCM_CTS
)
1179 temp
|= UARTMODIR_TXCTSE
;
1181 lpuart32_write(port
, temp
, UARTMODIR
);
1184 static void lpuart_break_ctl(struct uart_port
*port
, int break_state
)
1188 temp
= readb(port
->membase
+ UARTCR2
) & ~UARTCR2_SBK
;
1190 if (break_state
!= 0)
1191 temp
|= UARTCR2_SBK
;
1193 writeb(temp
, port
->membase
+ UARTCR2
);
1196 static void lpuart32_break_ctl(struct uart_port
*port
, int break_state
)
1200 temp
= lpuart32_read(port
, UARTCTRL
) & ~UARTCTRL_SBK
;
1202 if (break_state
!= 0)
1203 temp
|= UARTCTRL_SBK
;
1205 lpuart32_write(port
, temp
, UARTCTRL
);
1208 static void lpuart_setup_watermark(struct lpuart_port
*sport
)
1210 unsigned char val
, cr2
;
1211 unsigned char cr2_saved
;
1213 cr2
= readb(sport
->port
.membase
+ UARTCR2
);
1215 cr2
&= ~(UARTCR2_TIE
| UARTCR2_TCIE
| UARTCR2_TE
|
1216 UARTCR2_RIE
| UARTCR2_RE
);
1217 writeb(cr2
, sport
->port
.membase
+ UARTCR2
);
1219 val
= readb(sport
->port
.membase
+ UARTPFIFO
);
1220 writeb(val
| UARTPFIFO_TXFE
| UARTPFIFO_RXFE
,
1221 sport
->port
.membase
+ UARTPFIFO
);
1223 /* flush Tx and Rx FIFO */
1224 writeb(UARTCFIFO_TXFLUSH
| UARTCFIFO_RXFLUSH
,
1225 sport
->port
.membase
+ UARTCFIFO
);
1227 /* explicitly clear RDRF */
1228 if (readb(sport
->port
.membase
+ UARTSR1
) & UARTSR1_RDRF
) {
1229 readb(sport
->port
.membase
+ UARTDR
);
1230 writeb(UARTSFIFO_RXUF
, sport
->port
.membase
+ UARTSFIFO
);
1233 writeb(0, sport
->port
.membase
+ UARTTWFIFO
);
1234 writeb(1, sport
->port
.membase
+ UARTRWFIFO
);
1237 writeb(cr2_saved
, sport
->port
.membase
+ UARTCR2
);
1240 static void lpuart32_setup_watermark(struct lpuart_port
*sport
)
1242 unsigned long val
, ctrl
;
1243 unsigned long ctrl_saved
;
1245 ctrl
= lpuart32_read(&sport
->port
, UARTCTRL
);
1247 ctrl
&= ~(UARTCTRL_TIE
| UARTCTRL_TCIE
| UARTCTRL_TE
|
1248 UARTCTRL_RIE
| UARTCTRL_RE
);
1249 lpuart32_write(&sport
->port
, ctrl
, UARTCTRL
);
1251 /* enable FIFO mode */
1252 val
= lpuart32_read(&sport
->port
, UARTFIFO
);
1253 val
|= UARTFIFO_TXFE
| UARTFIFO_RXFE
;
1254 val
|= UARTFIFO_TXFLUSH
| UARTFIFO_RXFLUSH
;
1255 lpuart32_write(&sport
->port
, val
, UARTFIFO
);
1257 /* set the watermark */
1258 val
= (0x1 << UARTWATER_RXWATER_OFF
) | (0x0 << UARTWATER_TXWATER_OFF
);
1259 lpuart32_write(&sport
->port
, val
, UARTWATER
);
1262 lpuart32_write(&sport
->port
, ctrl_saved
, UARTCTRL
);
1265 static void rx_dma_timer_init(struct lpuart_port
*sport
)
1267 timer_setup(&sport
->lpuart_timer
, lpuart_timer_func
, 0);
1268 sport
->lpuart_timer
.expires
= jiffies
+ sport
->dma_rx_timeout
;
1269 add_timer(&sport
->lpuart_timer
);
1272 static int lpuart_startup(struct uart_port
*port
)
1274 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1275 unsigned long flags
;
1278 /* determine FIFO size and enable FIFO mode */
1279 temp
= readb(sport
->port
.membase
+ UARTPFIFO
);
1281 sport
->txfifo_size
= 0x1 << (((temp
>> UARTPFIFO_TXSIZE_OFF
) &
1282 UARTPFIFO_FIFOSIZE_MASK
) + 1);
1284 sport
->port
.fifosize
= sport
->txfifo_size
;
1286 sport
->rxfifo_size
= 0x1 << (((temp
>> UARTPFIFO_RXSIZE_OFF
) &
1287 UARTPFIFO_FIFOSIZE_MASK
) + 1);
1289 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1291 lpuart_setup_watermark(sport
);
1293 temp
= readb(sport
->port
.membase
+ UARTCR2
);
1294 temp
|= (UARTCR2_RIE
| UARTCR2_TIE
| UARTCR2_RE
| UARTCR2_TE
);
1295 writeb(temp
, sport
->port
.membase
+ UARTCR2
);
1297 if (sport
->dma_rx_chan
&& !lpuart_start_rx_dma(sport
)) {
1298 /* set Rx DMA timeout */
1299 sport
->dma_rx_timeout
= msecs_to_jiffies(DMA_RX_TIMEOUT
);
1300 if (!sport
->dma_rx_timeout
)
1301 sport
->dma_rx_timeout
= 1;
1303 sport
->lpuart_dma_rx_use
= true;
1304 rx_dma_timer_init(sport
);
1306 sport
->lpuart_dma_rx_use
= false;
1309 if (sport
->dma_tx_chan
&& !lpuart_dma_tx_request(port
)) {
1310 init_waitqueue_head(&sport
->dma_wait
);
1311 sport
->lpuart_dma_tx_use
= true;
1312 temp
= readb(port
->membase
+ UARTCR5
);
1313 writeb(temp
| UARTCR5_TDMAS
, port
->membase
+ UARTCR5
);
1315 sport
->lpuart_dma_tx_use
= false;
1318 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1323 static int lpuart32_startup(struct uart_port
*port
)
1325 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1326 unsigned long flags
;
1329 /* determine FIFO size */
1330 temp
= lpuart32_read(&sport
->port
, UARTFIFO
);
1332 sport
->txfifo_size
= 0x1 << (((temp
>> UARTFIFO_TXSIZE_OFF
) &
1333 UARTFIFO_FIFOSIZE_MASK
) - 1);
1335 sport
->rxfifo_size
= 0x1 << (((temp
>> UARTFIFO_RXSIZE_OFF
) &
1336 UARTFIFO_FIFOSIZE_MASK
) - 1);
1338 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1340 lpuart32_setup_watermark(sport
);
1342 temp
= lpuart32_read(&sport
->port
, UARTCTRL
);
1343 temp
|= (UARTCTRL_RIE
| UARTCTRL_TIE
| UARTCTRL_RE
| UARTCTRL_TE
);
1344 temp
|= UARTCTRL_ILIE
;
1345 lpuart32_write(&sport
->port
, temp
, UARTCTRL
);
1347 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1351 static void lpuart_shutdown(struct uart_port
*port
)
1353 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1355 unsigned long flags
;
1357 spin_lock_irqsave(&port
->lock
, flags
);
1359 /* disable Rx/Tx and interrupts */
1360 temp
= readb(port
->membase
+ UARTCR2
);
1361 temp
&= ~(UARTCR2_TE
| UARTCR2_RE
|
1362 UARTCR2_TIE
| UARTCR2_TCIE
| UARTCR2_RIE
);
1363 writeb(temp
, port
->membase
+ UARTCR2
);
1365 spin_unlock_irqrestore(&port
->lock
, flags
);
1367 if (sport
->lpuart_dma_rx_use
) {
1368 del_timer_sync(&sport
->lpuart_timer
);
1369 lpuart_dma_rx_free(&sport
->port
);
1372 if (sport
->lpuart_dma_tx_use
) {
1373 if (wait_event_interruptible(sport
->dma_wait
,
1374 !sport
->dma_tx_in_progress
) != false) {
1375 sport
->dma_tx_in_progress
= false;
1376 dmaengine_terminate_all(sport
->dma_tx_chan
);
1379 lpuart_stop_tx(port
);
1383 static void lpuart32_shutdown(struct uart_port
*port
)
1386 unsigned long flags
;
1388 spin_lock_irqsave(&port
->lock
, flags
);
1390 /* disable Rx/Tx and interrupts */
1391 temp
= lpuart32_read(port
, UARTCTRL
);
1392 temp
&= ~(UARTCTRL_TE
| UARTCTRL_RE
|
1393 UARTCTRL_TIE
| UARTCTRL_TCIE
| UARTCTRL_RIE
);
1394 lpuart32_write(port
, temp
, UARTCTRL
);
1396 spin_unlock_irqrestore(&port
->lock
, flags
);
1400 lpuart_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
1401 struct ktermios
*old
)
1403 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1404 unsigned long flags
;
1405 unsigned char cr1
, old_cr1
, old_cr2
, cr3
, cr4
, bdh
, modem
;
1407 unsigned int old_csize
= old
? old
->c_cflag
& CSIZE
: CS8
;
1408 unsigned int sbr
, brfa
;
1410 cr1
= old_cr1
= readb(sport
->port
.membase
+ UARTCR1
);
1411 old_cr2
= readb(sport
->port
.membase
+ UARTCR2
);
1412 cr3
= readb(sport
->port
.membase
+ UARTCR3
);
1413 cr4
= readb(sport
->port
.membase
+ UARTCR4
);
1414 bdh
= readb(sport
->port
.membase
+ UARTBDH
);
1415 modem
= readb(sport
->port
.membase
+ UARTMODEM
);
1417 * only support CS8 and CS7, and for CS7 must enable PE.
1424 while ((termios
->c_cflag
& CSIZE
) != CS8
&&
1425 (termios
->c_cflag
& CSIZE
) != CS7
) {
1426 termios
->c_cflag
&= ~CSIZE
;
1427 termios
->c_cflag
|= old_csize
;
1431 if ((termios
->c_cflag
& CSIZE
) == CS8
||
1432 (termios
->c_cflag
& CSIZE
) == CS7
)
1433 cr1
= old_cr1
& ~UARTCR1_M
;
1435 if (termios
->c_cflag
& CMSPAR
) {
1436 if ((termios
->c_cflag
& CSIZE
) != CS8
) {
1437 termios
->c_cflag
&= ~CSIZE
;
1438 termios
->c_cflag
|= CS8
;
1444 * When auto RS-485 RTS mode is enabled,
1445 * hardware flow control need to be disabled.
1447 if (sport
->port
.rs485
.flags
& SER_RS485_ENABLED
)
1448 termios
->c_cflag
&= ~CRTSCTS
;
1450 if (termios
->c_cflag
& CRTSCTS
) {
1451 modem
|= (UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1453 termios
->c_cflag
&= ~CRTSCTS
;
1454 modem
&= ~(UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1457 if (termios
->c_cflag
& CSTOPB
)
1458 termios
->c_cflag
&= ~CSTOPB
;
1460 /* parity must be enabled when CS7 to match 8-bits format */
1461 if ((termios
->c_cflag
& CSIZE
) == CS7
)
1462 termios
->c_cflag
|= PARENB
;
1464 if ((termios
->c_cflag
& PARENB
)) {
1465 if (termios
->c_cflag
& CMSPAR
) {
1467 if (termios
->c_cflag
& PARODD
)
1473 if ((termios
->c_cflag
& CSIZE
) == CS8
)
1475 if (termios
->c_cflag
& PARODD
)
1482 /* ask the core to calculate the divisor */
1483 baud
= uart_get_baud_rate(port
, termios
, old
, 50, port
->uartclk
/ 16);
1486 * Need to update the Ring buffer length according to the selected
1487 * baud rate and restart Rx DMA path.
1489 * Since timer function acqures sport->port.lock, need to stop before
1490 * acquring same lock because otherwise del_timer_sync() can deadlock.
1492 if (old
&& sport
->lpuart_dma_rx_use
) {
1493 del_timer_sync(&sport
->lpuart_timer
);
1494 lpuart_dma_rx_free(&sport
->port
);
1497 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1499 sport
->port
.read_status_mask
= 0;
1500 if (termios
->c_iflag
& INPCK
)
1501 sport
->port
.read_status_mask
|= (UARTSR1_FE
| UARTSR1_PE
);
1502 if (termios
->c_iflag
& (IGNBRK
| BRKINT
| PARMRK
))
1503 sport
->port
.read_status_mask
|= UARTSR1_FE
;
1505 /* characters to ignore */
1506 sport
->port
.ignore_status_mask
= 0;
1507 if (termios
->c_iflag
& IGNPAR
)
1508 sport
->port
.ignore_status_mask
|= UARTSR1_PE
;
1509 if (termios
->c_iflag
& IGNBRK
) {
1510 sport
->port
.ignore_status_mask
|= UARTSR1_FE
;
1512 * if we're ignoring parity and break indicators,
1513 * ignore overruns too (for real raw support).
1515 if (termios
->c_iflag
& IGNPAR
)
1516 sport
->port
.ignore_status_mask
|= UARTSR1_OR
;
1519 /* update the per-port timeout */
1520 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1522 /* wait transmit engin complete */
1523 while (!(readb(sport
->port
.membase
+ UARTSR1
) & UARTSR1_TC
))
1526 /* disable transmit and receive */
1527 writeb(old_cr2
& ~(UARTCR2_TE
| UARTCR2_RE
),
1528 sport
->port
.membase
+ UARTCR2
);
1530 sbr
= sport
->port
.uartclk
/ (16 * baud
);
1531 brfa
= ((sport
->port
.uartclk
- (16 * sbr
* baud
)) * 2) / baud
;
1532 bdh
&= ~UARTBDH_SBR_MASK
;
1533 bdh
|= (sbr
>> 8) & 0x1F;
1534 cr4
&= ~UARTCR4_BRFA_MASK
;
1535 brfa
&= UARTCR4_BRFA_MASK
;
1536 writeb(cr4
| brfa
, sport
->port
.membase
+ UARTCR4
);
1537 writeb(bdh
, sport
->port
.membase
+ UARTBDH
);
1538 writeb(sbr
& 0xFF, sport
->port
.membase
+ UARTBDL
);
1539 writeb(cr3
, sport
->port
.membase
+ UARTCR3
);
1540 writeb(cr1
, sport
->port
.membase
+ UARTCR1
);
1541 writeb(modem
, sport
->port
.membase
+ UARTMODEM
);
1543 /* restore control register */
1544 writeb(old_cr2
, sport
->port
.membase
+ UARTCR2
);
1546 if (old
&& sport
->lpuart_dma_rx_use
) {
1547 if (!lpuart_start_rx_dma(sport
))
1548 rx_dma_timer_init(sport
);
1550 sport
->lpuart_dma_rx_use
= false;
1553 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1557 lpuart32_serial_setbrg(struct lpuart_port
*sport
, unsigned int baudrate
)
1559 u32 sbr
, osr
, baud_diff
, tmp_osr
, tmp_sbr
, tmp_diff
, tmp
;
1560 u32 clk
= sport
->port
.uartclk
;
1563 * The idea is to use the best OSR (over-sampling rate) possible.
1564 * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
1565 * Loop to find the best OSR value possible, one that generates minimum
1566 * baud_diff iterate through the rest of the supported values of OSR.
1568 * Calculation Formula:
1569 * Baud Rate = baud clock / ((OSR+1) × SBR)
1571 baud_diff
= baudrate
;
1575 for (tmp_osr
= 4; tmp_osr
<= 32; tmp_osr
++) {
1576 /* calculate the temporary sbr value */
1577 tmp_sbr
= (clk
/ (baudrate
* tmp_osr
));
1582 * calculate the baud rate difference based on the temporary
1583 * osr and sbr values
1585 tmp_diff
= clk
/ (tmp_osr
* tmp_sbr
) - baudrate
;
1587 /* select best values between sbr and sbr+1 */
1588 tmp
= clk
/ (tmp_osr
* (tmp_sbr
+ 1));
1589 if (tmp_diff
> (baudrate
- tmp
)) {
1590 tmp_diff
= baudrate
- tmp
;
1594 if (tmp_diff
<= baud_diff
) {
1595 baud_diff
= tmp_diff
;
1604 /* handle buadrate outside acceptable rate */
1605 if (baud_diff
> ((baudrate
/ 100) * 3))
1606 dev_warn(sport
->port
.dev
,
1607 "unacceptable baud rate difference of more than 3%%\n");
1609 tmp
= lpuart32_read(&sport
->port
, UARTBAUD
);
1611 if ((osr
> 3) && (osr
< 8))
1612 tmp
|= UARTBAUD_BOTHEDGE
;
1614 tmp
&= ~(UARTBAUD_OSR_MASK
<< UARTBAUD_OSR_SHIFT
);
1615 tmp
|= (((osr
-1) & UARTBAUD_OSR_MASK
) << UARTBAUD_OSR_SHIFT
);
1617 tmp
&= ~UARTBAUD_SBR_MASK
;
1618 tmp
|= sbr
& UARTBAUD_SBR_MASK
;
1620 tmp
&= ~(UARTBAUD_TDMAE
| UARTBAUD_RDMAE
);
1622 lpuart32_write(&sport
->port
, tmp
, UARTBAUD
);
1626 lpuart32_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
1627 struct ktermios
*old
)
1629 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1630 unsigned long flags
;
1631 unsigned long ctrl
, old_ctrl
, modem
;
1633 unsigned int old_csize
= old
? old
->c_cflag
& CSIZE
: CS8
;
1635 ctrl
= old_ctrl
= lpuart32_read(&sport
->port
, UARTCTRL
);
1636 modem
= lpuart32_read(&sport
->port
, UARTMODIR
);
1638 * only support CS8 and CS7, and for CS7 must enable PE.
1645 while ((termios
->c_cflag
& CSIZE
) != CS8
&&
1646 (termios
->c_cflag
& CSIZE
) != CS7
) {
1647 termios
->c_cflag
&= ~CSIZE
;
1648 termios
->c_cflag
|= old_csize
;
1652 if ((termios
->c_cflag
& CSIZE
) == CS8
||
1653 (termios
->c_cflag
& CSIZE
) == CS7
)
1654 ctrl
= old_ctrl
& ~UARTCTRL_M
;
1656 if (termios
->c_cflag
& CMSPAR
) {
1657 if ((termios
->c_cflag
& CSIZE
) != CS8
) {
1658 termios
->c_cflag
&= ~CSIZE
;
1659 termios
->c_cflag
|= CS8
;
1664 if (termios
->c_cflag
& CRTSCTS
) {
1665 modem
|= (UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1667 termios
->c_cflag
&= ~CRTSCTS
;
1668 modem
&= ~(UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1671 if (termios
->c_cflag
& CSTOPB
)
1672 termios
->c_cflag
&= ~CSTOPB
;
1674 /* parity must be enabled when CS7 to match 8-bits format */
1675 if ((termios
->c_cflag
& CSIZE
) == CS7
)
1676 termios
->c_cflag
|= PARENB
;
1678 if ((termios
->c_cflag
& PARENB
)) {
1679 if (termios
->c_cflag
& CMSPAR
) {
1680 ctrl
&= ~UARTCTRL_PE
;
1684 if ((termios
->c_cflag
& CSIZE
) == CS8
)
1686 if (termios
->c_cflag
& PARODD
)
1687 ctrl
|= UARTCTRL_PT
;
1689 ctrl
&= ~UARTCTRL_PT
;
1693 /* ask the core to calculate the divisor */
1694 baud
= uart_get_baud_rate(port
, termios
, old
, 50, port
->uartclk
/ 16);
1696 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1698 sport
->port
.read_status_mask
= 0;
1699 if (termios
->c_iflag
& INPCK
)
1700 sport
->port
.read_status_mask
|= (UARTSTAT_FE
| UARTSTAT_PE
);
1701 if (termios
->c_iflag
& (IGNBRK
| BRKINT
| PARMRK
))
1702 sport
->port
.read_status_mask
|= UARTSTAT_FE
;
1704 /* characters to ignore */
1705 sport
->port
.ignore_status_mask
= 0;
1706 if (termios
->c_iflag
& IGNPAR
)
1707 sport
->port
.ignore_status_mask
|= UARTSTAT_PE
;
1708 if (termios
->c_iflag
& IGNBRK
) {
1709 sport
->port
.ignore_status_mask
|= UARTSTAT_FE
;
1711 * if we're ignoring parity and break indicators,
1712 * ignore overruns too (for real raw support).
1714 if (termios
->c_iflag
& IGNPAR
)
1715 sport
->port
.ignore_status_mask
|= UARTSTAT_OR
;
1718 /* update the per-port timeout */
1719 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1721 /* wait transmit engin complete */
1722 while (!(lpuart32_read(&sport
->port
, UARTSTAT
) & UARTSTAT_TC
))
1725 /* disable transmit and receive */
1726 lpuart32_write(&sport
->port
, old_ctrl
& ~(UARTCTRL_TE
| UARTCTRL_RE
),
1729 lpuart32_serial_setbrg(sport
, baud
);
1730 lpuart32_write(&sport
->port
, modem
, UARTMODIR
);
1731 lpuart32_write(&sport
->port
, ctrl
, UARTCTRL
);
1732 /* restore control register */
1734 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1737 static const char *lpuart_type(struct uart_port
*port
)
1739 return "FSL_LPUART";
1742 static void lpuart_release_port(struct uart_port
*port
)
1747 static int lpuart_request_port(struct uart_port
*port
)
1752 /* configure/autoconfigure the port */
1753 static void lpuart_config_port(struct uart_port
*port
, int flags
)
1755 if (flags
& UART_CONFIG_TYPE
)
1756 port
->type
= PORT_LPUART
;
1759 static int lpuart_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
1763 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_LPUART
)
1765 if (port
->irq
!= ser
->irq
)
1767 if (ser
->io_type
!= UPIO_MEM
)
1769 if (port
->uartclk
/ 16 != ser
->baud_base
)
1771 if (port
->iobase
!= ser
->port
)
1778 static const struct uart_ops lpuart_pops
= {
1779 .tx_empty
= lpuart_tx_empty
,
1780 .set_mctrl
= lpuart_set_mctrl
,
1781 .get_mctrl
= lpuart_get_mctrl
,
1782 .stop_tx
= lpuart_stop_tx
,
1783 .start_tx
= lpuart_start_tx
,
1784 .stop_rx
= lpuart_stop_rx
,
1785 .break_ctl
= lpuart_break_ctl
,
1786 .startup
= lpuart_startup
,
1787 .shutdown
= lpuart_shutdown
,
1788 .set_termios
= lpuart_set_termios
,
1789 .type
= lpuart_type
,
1790 .request_port
= lpuart_request_port
,
1791 .release_port
= lpuart_release_port
,
1792 .config_port
= lpuart_config_port
,
1793 .verify_port
= lpuart_verify_port
,
1794 .flush_buffer
= lpuart_flush_buffer
,
1795 #if defined(CONFIG_CONSOLE_POLL)
1796 .poll_init
= lpuart_poll_init
,
1797 .poll_get_char
= lpuart_poll_get_char
,
1798 .poll_put_char
= lpuart_poll_put_char
,
1802 static const struct uart_ops lpuart32_pops
= {
1803 .tx_empty
= lpuart32_tx_empty
,
1804 .set_mctrl
= lpuart32_set_mctrl
,
1805 .get_mctrl
= lpuart32_get_mctrl
,
1806 .stop_tx
= lpuart32_stop_tx
,
1807 .start_tx
= lpuart32_start_tx
,
1808 .stop_rx
= lpuart32_stop_rx
,
1809 .break_ctl
= lpuart32_break_ctl
,
1810 .startup
= lpuart32_startup
,
1811 .shutdown
= lpuart32_shutdown
,
1812 .set_termios
= lpuart32_set_termios
,
1813 .type
= lpuart_type
,
1814 .request_port
= lpuart_request_port
,
1815 .release_port
= lpuart_release_port
,
1816 .config_port
= lpuart_config_port
,
1817 .verify_port
= lpuart_verify_port
,
1818 .flush_buffer
= lpuart_flush_buffer
,
1819 #if defined(CONFIG_CONSOLE_POLL)
1820 .poll_init
= lpuart32_poll_init
,
1821 .poll_get_char
= lpuart32_poll_get_char
,
1822 .poll_put_char
= lpuart32_poll_put_char
,
1826 static struct lpuart_port
*lpuart_ports
[UART_NR
];
1828 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1829 static void lpuart_console_putchar(struct uart_port
*port
, int ch
)
1831 while (!(readb(port
->membase
+ UARTSR1
) & UARTSR1_TDRE
))
1834 writeb(ch
, port
->membase
+ UARTDR
);
1837 static void lpuart32_console_putchar(struct uart_port
*port
, int ch
)
1839 while (!(lpuart32_read(port
, UARTSTAT
) & UARTSTAT_TDRE
))
1842 lpuart32_write(port
, ch
, UARTDATA
);
1846 lpuart_console_write(struct console
*co
, const char *s
, unsigned int count
)
1848 struct lpuart_port
*sport
= lpuart_ports
[co
->index
];
1849 unsigned char old_cr2
, cr2
;
1850 unsigned long flags
;
1853 if (sport
->port
.sysrq
|| oops_in_progress
)
1854 locked
= spin_trylock_irqsave(&sport
->port
.lock
, flags
);
1856 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1858 /* first save CR2 and then disable interrupts */
1859 cr2
= old_cr2
= readb(sport
->port
.membase
+ UARTCR2
);
1860 cr2
|= (UARTCR2_TE
| UARTCR2_RE
);
1861 cr2
&= ~(UARTCR2_TIE
| UARTCR2_TCIE
| UARTCR2_RIE
);
1862 writeb(cr2
, sport
->port
.membase
+ UARTCR2
);
1864 uart_console_write(&sport
->port
, s
, count
, lpuart_console_putchar
);
1866 /* wait for transmitter finish complete and restore CR2 */
1867 while (!(readb(sport
->port
.membase
+ UARTSR1
) & UARTSR1_TC
))
1870 writeb(old_cr2
, sport
->port
.membase
+ UARTCR2
);
1873 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1877 lpuart32_console_write(struct console
*co
, const char *s
, unsigned int count
)
1879 struct lpuart_port
*sport
= lpuart_ports
[co
->index
];
1880 unsigned long old_cr
, cr
;
1881 unsigned long flags
;
1884 if (sport
->port
.sysrq
|| oops_in_progress
)
1885 locked
= spin_trylock_irqsave(&sport
->port
.lock
, flags
);
1887 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1889 /* first save CR2 and then disable interrupts */
1890 cr
= old_cr
= lpuart32_read(&sport
->port
, UARTCTRL
);
1891 cr
|= (UARTCTRL_TE
| UARTCTRL_RE
);
1892 cr
&= ~(UARTCTRL_TIE
| UARTCTRL_TCIE
| UARTCTRL_RIE
);
1893 lpuart32_write(&sport
->port
, cr
, UARTCTRL
);
1895 uart_console_write(&sport
->port
, s
, count
, lpuart32_console_putchar
);
1897 /* wait for transmitter finish complete and restore CR2 */
1898 while (!(lpuart32_read(&sport
->port
, UARTSTAT
) & UARTSTAT_TC
))
1901 lpuart32_write(&sport
->port
, old_cr
, UARTCTRL
);
1904 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1908 * if the port was already initialised (eg, by a boot loader),
1909 * try to determine the current setup.
1912 lpuart_console_get_options(struct lpuart_port
*sport
, int *baud
,
1913 int *parity
, int *bits
)
1915 unsigned char cr
, bdh
, bdl
, brfa
;
1916 unsigned int sbr
, uartclk
, baud_raw
;
1918 cr
= readb(sport
->port
.membase
+ UARTCR2
);
1919 cr
&= UARTCR2_TE
| UARTCR2_RE
;
1923 /* ok, the port was enabled */
1925 cr
= readb(sport
->port
.membase
+ UARTCR1
);
1928 if (cr
& UARTCR1_PE
) {
1929 if (cr
& UARTCR1_PT
)
1940 bdh
= readb(sport
->port
.membase
+ UARTBDH
);
1941 bdh
&= UARTBDH_SBR_MASK
;
1942 bdl
= readb(sport
->port
.membase
+ UARTBDL
);
1946 brfa
= readb(sport
->port
.membase
+ UARTCR4
);
1947 brfa
&= UARTCR4_BRFA_MASK
;
1949 uartclk
= clk_get_rate(sport
->clk
);
1951 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1953 baud_raw
= uartclk
/ (16 * (sbr
+ brfa
/ 32));
1955 if (*baud
!= baud_raw
)
1956 printk(KERN_INFO
"Serial: Console lpuart rounded baud rate"
1957 "from %d to %d\n", baud_raw
, *baud
);
1961 lpuart32_console_get_options(struct lpuart_port
*sport
, int *baud
,
1962 int *parity
, int *bits
)
1964 unsigned long cr
, bd
;
1965 unsigned int sbr
, uartclk
, baud_raw
;
1967 cr
= lpuart32_read(&sport
->port
, UARTCTRL
);
1968 cr
&= UARTCTRL_TE
| UARTCTRL_RE
;
1972 /* ok, the port was enabled */
1974 cr
= lpuart32_read(&sport
->port
, UARTCTRL
);
1977 if (cr
& UARTCTRL_PE
) {
1978 if (cr
& UARTCTRL_PT
)
1984 if (cr
& UARTCTRL_M
)
1989 bd
= lpuart32_read(&sport
->port
, UARTBAUD
);
1990 bd
&= UARTBAUD_SBR_MASK
;
1992 uartclk
= clk_get_rate(sport
->clk
);
1994 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1996 baud_raw
= uartclk
/ (16 * sbr
);
1998 if (*baud
!= baud_raw
)
1999 printk(KERN_INFO
"Serial: Console lpuart rounded baud rate"
2000 "from %d to %d\n", baud_raw
, *baud
);
2003 static int __init
lpuart_console_setup(struct console
*co
, char *options
)
2005 struct lpuart_port
*sport
;
2012 * check whether an invalid uart number has been specified, and
2013 * if so, search for the first available port that does have
2016 if (co
->index
== -1 || co
->index
>= ARRAY_SIZE(lpuart_ports
))
2019 sport
= lpuart_ports
[co
->index
];
2024 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
2026 if (lpuart_is_32(sport
))
2027 lpuart32_console_get_options(sport
, &baud
, &parity
, &bits
);
2029 lpuart_console_get_options(sport
, &baud
, &parity
, &bits
);
2031 if (lpuart_is_32(sport
))
2032 lpuart32_setup_watermark(sport
);
2034 lpuart_setup_watermark(sport
);
2036 return uart_set_options(&sport
->port
, co
, baud
, parity
, bits
, flow
);
2039 static struct uart_driver lpuart_reg
;
2040 static struct console lpuart_console
= {
2042 .write
= lpuart_console_write
,
2043 .device
= uart_console_device
,
2044 .setup
= lpuart_console_setup
,
2045 .flags
= CON_PRINTBUFFER
,
2047 .data
= &lpuart_reg
,
2050 static struct console lpuart32_console
= {
2052 .write
= lpuart32_console_write
,
2053 .device
= uart_console_device
,
2054 .setup
= lpuart_console_setup
,
2055 .flags
= CON_PRINTBUFFER
,
2057 .data
= &lpuart_reg
,
2060 static void lpuart_early_write(struct console
*con
, const char *s
, unsigned n
)
2062 struct earlycon_device
*dev
= con
->data
;
2064 uart_console_write(&dev
->port
, s
, n
, lpuart_console_putchar
);
2067 static void lpuart32_early_write(struct console
*con
, const char *s
, unsigned n
)
2069 struct earlycon_device
*dev
= con
->data
;
2071 uart_console_write(&dev
->port
, s
, n
, lpuart32_console_putchar
);
2074 static int __init
lpuart_early_console_setup(struct earlycon_device
*device
,
2077 if (!device
->port
.membase
)
2080 device
->con
->write
= lpuart_early_write
;
2084 static int __init
lpuart32_early_console_setup(struct earlycon_device
*device
,
2087 if (!device
->port
.membase
)
2090 device
->port
.iotype
= UPIO_MEM32BE
;
2091 device
->con
->write
= lpuart32_early_write
;
2095 static int __init
lpuart32_imx_early_console_setup(struct earlycon_device
*device
,
2098 if (!device
->port
.membase
)
2101 device
->port
.iotype
= UPIO_MEM32
;
2102 device
->port
.membase
+= IMX_REG_OFF
;
2103 device
->con
->write
= lpuart32_early_write
;
2107 OF_EARLYCON_DECLARE(lpuart
, "fsl,vf610-lpuart", lpuart_early_console_setup
);
2108 OF_EARLYCON_DECLARE(lpuart32
, "fsl,ls1021a-lpuart", lpuart32_early_console_setup
);
2109 OF_EARLYCON_DECLARE(lpuart32
, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup
);
2110 EARLYCON_DECLARE(lpuart
, lpuart_early_console_setup
);
2111 EARLYCON_DECLARE(lpuart32
, lpuart32_early_console_setup
);
2113 #define LPUART_CONSOLE (&lpuart_console)
2114 #define LPUART32_CONSOLE (&lpuart32_console)
2116 #define LPUART_CONSOLE NULL
2117 #define LPUART32_CONSOLE NULL
2120 static struct uart_driver lpuart_reg
= {
2121 .owner
= THIS_MODULE
,
2122 .driver_name
= DRIVER_NAME
,
2123 .dev_name
= DEV_NAME
,
2124 .nr
= ARRAY_SIZE(lpuart_ports
),
2125 .cons
= LPUART_CONSOLE
,
2128 static int lpuart_probe(struct platform_device
*pdev
)
2130 const struct of_device_id
*of_id
= of_match_device(lpuart_dt_ids
,
2132 const struct lpuart_soc_data
*sdata
= of_id
->data
;
2133 struct device_node
*np
= pdev
->dev
.of_node
;
2134 struct lpuart_port
*sport
;
2135 struct resource
*res
;
2138 sport
= devm_kzalloc(&pdev
->dev
, sizeof(*sport
), GFP_KERNEL
);
2142 pdev
->dev
.coherent_dma_mask
= 0;
2144 ret
= of_alias_get_id(np
, "serial");
2146 dev_err(&pdev
->dev
, "failed to get alias id, errno %d\n", ret
);
2149 if (ret
>= ARRAY_SIZE(lpuart_ports
)) {
2150 dev_err(&pdev
->dev
, "serial%d out of range\n", ret
);
2153 sport
->port
.line
= ret
;
2154 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2155 sport
->port
.membase
= devm_ioremap_resource(&pdev
->dev
, res
);
2156 if (IS_ERR(sport
->port
.membase
))
2157 return PTR_ERR(sport
->port
.membase
);
2159 sport
->port
.membase
+= sdata
->reg_off
;
2160 sport
->port
.mapbase
= res
->start
;
2161 sport
->port
.dev
= &pdev
->dev
;
2162 sport
->port
.type
= PORT_LPUART
;
2163 ret
= platform_get_irq(pdev
, 0);
2165 dev_err(&pdev
->dev
, "cannot obtain irq\n");
2168 sport
->port
.irq
= ret
;
2169 sport
->port
.iotype
= sdata
->iotype
;
2170 if (lpuart_is_32(sport
))
2171 sport
->port
.ops
= &lpuart32_pops
;
2173 sport
->port
.ops
= &lpuart_pops
;
2174 sport
->port
.flags
= UPF_BOOT_AUTOCONF
;
2176 sport
->port
.rs485_config
= lpuart_config_rs485
;
2178 sport
->clk
= devm_clk_get(&pdev
->dev
, "ipg");
2179 if (IS_ERR(sport
->clk
)) {
2180 ret
= PTR_ERR(sport
->clk
);
2181 dev_err(&pdev
->dev
, "failed to get uart clk: %d\n", ret
);
2185 ret
= clk_prepare_enable(sport
->clk
);
2187 dev_err(&pdev
->dev
, "failed to enable uart clk: %d\n", ret
);
2191 sport
->port
.uartclk
= clk_get_rate(sport
->clk
);
2193 lpuart_ports
[sport
->port
.line
] = sport
;
2195 platform_set_drvdata(pdev
, &sport
->port
);
2197 if (lpuart_is_32(sport
)) {
2198 lpuart_reg
.cons
= LPUART32_CONSOLE
;
2199 ret
= devm_request_irq(&pdev
->dev
, sport
->port
.irq
, lpuart32_int
, 0,
2200 DRIVER_NAME
, sport
);
2202 lpuart_reg
.cons
= LPUART_CONSOLE
;
2203 ret
= devm_request_irq(&pdev
->dev
, sport
->port
.irq
, lpuart_int
, 0,
2204 DRIVER_NAME
, sport
);
2208 goto failed_irq_request
;
2210 ret
= uart_add_one_port(&lpuart_reg
, &sport
->port
);
2212 goto failed_attach_port
;
2214 of_get_rs485_mode(np
, &sport
->port
.rs485
);
2216 if (sport
->port
.rs485
.flags
& SER_RS485_RX_DURING_TX
) {
2217 dev_err(&pdev
->dev
, "driver doesn't support RX during TX\n");
2221 if (sport
->port
.rs485
.delay_rts_before_send
||
2222 sport
->port
.rs485
.delay_rts_after_send
) {
2223 dev_err(&pdev
->dev
, "driver doesn't support RTS delays\n");
2227 if (sport
->port
.rs485
.flags
& SER_RS485_ENABLED
) {
2228 sport
->port
.rs485
.flags
|= SER_RS485_RTS_ON_SEND
;
2229 writeb(UARTMODEM_TXRTSE
, sport
->port
.membase
+ UARTMODEM
);
2232 sport
->dma_tx_chan
= dma_request_slave_channel(sport
->port
.dev
, "tx");
2233 if (!sport
->dma_tx_chan
)
2234 dev_info(sport
->port
.dev
, "DMA tx channel request failed, "
2235 "operating without tx DMA\n");
2237 sport
->dma_rx_chan
= dma_request_slave_channel(sport
->port
.dev
, "rx");
2238 if (!sport
->dma_rx_chan
)
2239 dev_info(sport
->port
.dev
, "DMA rx channel request failed, "
2240 "operating without rx DMA\n");
2246 clk_disable_unprepare(sport
->clk
);
2250 static int lpuart_remove(struct platform_device
*pdev
)
2252 struct lpuart_port
*sport
= platform_get_drvdata(pdev
);
2254 uart_remove_one_port(&lpuart_reg
, &sport
->port
);
2256 clk_disable_unprepare(sport
->clk
);
2258 if (sport
->dma_tx_chan
)
2259 dma_release_channel(sport
->dma_tx_chan
);
2261 if (sport
->dma_rx_chan
)
2262 dma_release_channel(sport
->dma_rx_chan
);
2267 #ifdef CONFIG_PM_SLEEP
2268 static int lpuart_suspend(struct device
*dev
)
2270 struct lpuart_port
*sport
= dev_get_drvdata(dev
);
2274 if (lpuart_is_32(sport
)) {
2275 /* disable Rx/Tx and interrupts */
2276 temp
= lpuart32_read(&sport
->port
, UARTCTRL
);
2277 temp
&= ~(UARTCTRL_TE
| UARTCTRL_TIE
| UARTCTRL_TCIE
);
2278 lpuart32_write(&sport
->port
, temp
, UARTCTRL
);
2280 /* disable Rx/Tx and interrupts */
2281 temp
= readb(sport
->port
.membase
+ UARTCR2
);
2282 temp
&= ~(UARTCR2_TE
| UARTCR2_TIE
| UARTCR2_TCIE
);
2283 writeb(temp
, sport
->port
.membase
+ UARTCR2
);
2286 uart_suspend_port(&lpuart_reg
, &sport
->port
);
2288 /* uart_suspend_port() might set wakeup flag */
2289 irq_wake
= irqd_is_wakeup_set(irq_get_irq_data(sport
->port
.irq
));
2291 if (sport
->lpuart_dma_rx_use
) {
2293 * EDMA driver during suspend will forcefully release any
2294 * non-idle DMA channels. If port wakeup is enabled or if port
2295 * is console port or 'no_console_suspend' is set the Rx DMA
2296 * cannot resume as as expected, hence gracefully release the
2297 * Rx DMA path before suspend and start Rx DMA path on resume.
2300 del_timer_sync(&sport
->lpuart_timer
);
2301 lpuart_dma_rx_free(&sport
->port
);
2304 /* Disable Rx DMA to use UART port as wakeup source */
2305 writeb(readb(sport
->port
.membase
+ UARTCR5
) & ~UARTCR5_RDMAS
,
2306 sport
->port
.membase
+ UARTCR5
);
2309 if (sport
->lpuart_dma_tx_use
) {
2310 sport
->dma_tx_in_progress
= false;
2311 dmaengine_terminate_all(sport
->dma_tx_chan
);
2314 if (sport
->port
.suspended
&& !irq_wake
)
2315 clk_disable_unprepare(sport
->clk
);
2320 static int lpuart_resume(struct device
*dev
)
2322 struct lpuart_port
*sport
= dev_get_drvdata(dev
);
2323 bool irq_wake
= irqd_is_wakeup_set(irq_get_irq_data(sport
->port
.irq
));
2326 if (sport
->port
.suspended
&& !irq_wake
)
2327 clk_prepare_enable(sport
->clk
);
2329 if (lpuart_is_32(sport
)) {
2330 lpuart32_setup_watermark(sport
);
2331 temp
= lpuart32_read(&sport
->port
, UARTCTRL
);
2332 temp
|= (UARTCTRL_RIE
| UARTCTRL_TIE
| UARTCTRL_RE
|
2333 UARTCTRL_TE
| UARTCTRL_ILIE
);
2334 lpuart32_write(&sport
->port
, temp
, UARTCTRL
);
2336 lpuart_setup_watermark(sport
);
2337 temp
= readb(sport
->port
.membase
+ UARTCR2
);
2338 temp
|= (UARTCR2_RIE
| UARTCR2_TIE
| UARTCR2_RE
| UARTCR2_TE
);
2339 writeb(temp
, sport
->port
.membase
+ UARTCR2
);
2342 if (sport
->lpuart_dma_rx_use
) {
2344 if (!lpuart_start_rx_dma(sport
))
2345 rx_dma_timer_init(sport
);
2347 sport
->lpuart_dma_rx_use
= false;
2351 if (sport
->dma_tx_chan
&& !lpuart_dma_tx_request(&sport
->port
)) {
2352 init_waitqueue_head(&sport
->dma_wait
);
2353 sport
->lpuart_dma_tx_use
= true;
2354 writeb(readb(sport
->port
.membase
+ UARTCR5
) |
2355 UARTCR5_TDMAS
, sport
->port
.membase
+ UARTCR5
);
2357 sport
->lpuart_dma_tx_use
= false;
2360 uart_resume_port(&lpuart_reg
, &sport
->port
);
2366 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops
, lpuart_suspend
, lpuart_resume
);
2368 static struct platform_driver lpuart_driver
= {
2369 .probe
= lpuart_probe
,
2370 .remove
= lpuart_remove
,
2372 .name
= "fsl-lpuart",
2373 .of_match_table
= lpuart_dt_ids
,
2374 .pm
= &lpuart_pm_ops
,
2378 static int __init
lpuart_serial_init(void)
2380 int ret
= uart_register_driver(&lpuart_reg
);
2385 ret
= platform_driver_register(&lpuart_driver
);
2387 uart_unregister_driver(&lpuart_reg
);
2392 static void __exit
lpuart_serial_exit(void)
2394 platform_driver_unregister(&lpuart_driver
);
2395 uart_unregister_driver(&lpuart_reg
);
2398 module_init(lpuart_serial_init
);
2399 module_exit(lpuart_serial_exit
);
2401 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2402 MODULE_LICENSE("GPL v2");