2 * Freescale lpuart serial port driver
4 * Copyright 2012-2014 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
16 #include <linux/clk.h>
17 #include <linux/console.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/dmaengine.h>
20 #include <linux/dmapool.h>
22 #include <linux/irq.h>
23 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/of_dma.h>
27 #include <linux/serial_core.h>
28 #include <linux/slab.h>
29 #include <linux/tty_flip.h>
31 /* All registers are 8-bit width */
41 #define UARTMODEM 0x0d
42 #define UARTPFIFO 0x10
43 #define UARTCFIFO 0x11
44 #define UARTSFIFO 0x12
45 #define UARTTWFIFO 0x13
46 #define UARTTCFIFO 0x14
47 #define UARTRWFIFO 0x15
49 #define UARTBDH_LBKDIE 0x80
50 #define UARTBDH_RXEDGIE 0x40
51 #define UARTBDH_SBR_MASK 0x1f
53 #define UARTCR1_LOOPS 0x80
54 #define UARTCR1_RSRC 0x20
55 #define UARTCR1_M 0x10
56 #define UARTCR1_WAKE 0x08
57 #define UARTCR1_ILT 0x04
58 #define UARTCR1_PE 0x02
59 #define UARTCR1_PT 0x01
61 #define UARTCR2_TIE 0x80
62 #define UARTCR2_TCIE 0x40
63 #define UARTCR2_RIE 0x20
64 #define UARTCR2_ILIE 0x10
65 #define UARTCR2_TE 0x08
66 #define UARTCR2_RE 0x04
67 #define UARTCR2_RWU 0x02
68 #define UARTCR2_SBK 0x01
70 #define UARTSR1_TDRE 0x80
71 #define UARTSR1_TC 0x40
72 #define UARTSR1_RDRF 0x20
73 #define UARTSR1_IDLE 0x10
74 #define UARTSR1_OR 0x08
75 #define UARTSR1_NF 0x04
76 #define UARTSR1_FE 0x02
77 #define UARTSR1_PE 0x01
79 #define UARTCR3_R8 0x80
80 #define UARTCR3_T8 0x40
81 #define UARTCR3_TXDIR 0x20
82 #define UARTCR3_TXINV 0x10
83 #define UARTCR3_ORIE 0x08
84 #define UARTCR3_NEIE 0x04
85 #define UARTCR3_FEIE 0x02
86 #define UARTCR3_PEIE 0x01
88 #define UARTCR4_MAEN1 0x80
89 #define UARTCR4_MAEN2 0x40
90 #define UARTCR4_M10 0x20
91 #define UARTCR4_BRFA_MASK 0x1f
92 #define UARTCR4_BRFA_OFF 0
94 #define UARTCR5_TDMAS 0x80
95 #define UARTCR5_RDMAS 0x20
97 #define UARTMODEM_RXRTSE 0x08
98 #define UARTMODEM_TXRTSPOL 0x04
99 #define UARTMODEM_TXRTSE 0x02
100 #define UARTMODEM_TXCTSE 0x01
102 #define UARTPFIFO_TXFE 0x80
103 #define UARTPFIFO_FIFOSIZE_MASK 0x7
104 #define UARTPFIFO_TXSIZE_OFF 4
105 #define UARTPFIFO_RXFE 0x08
106 #define UARTPFIFO_RXSIZE_OFF 0
108 #define UARTCFIFO_TXFLUSH 0x80
109 #define UARTCFIFO_RXFLUSH 0x40
110 #define UARTCFIFO_RXOFE 0x04
111 #define UARTCFIFO_TXOFE 0x02
112 #define UARTCFIFO_RXUFE 0x01
114 #define UARTSFIFO_TXEMPT 0x80
115 #define UARTSFIFO_RXEMPT 0x40
116 #define UARTSFIFO_RXOF 0x04
117 #define UARTSFIFO_TXOF 0x02
118 #define UARTSFIFO_RXUF 0x01
120 /* 32-bit register defination */
121 #define UARTBAUD 0x00
122 #define UARTSTAT 0x04
123 #define UARTCTRL 0x08
124 #define UARTDATA 0x0C
125 #define UARTMATCH 0x10
126 #define UARTMODIR 0x14
127 #define UARTFIFO 0x18
128 #define UARTWATER 0x1c
130 #define UARTBAUD_MAEN1 0x80000000
131 #define UARTBAUD_MAEN2 0x40000000
132 #define UARTBAUD_M10 0x20000000
133 #define UARTBAUD_TDMAE 0x00800000
134 #define UARTBAUD_RDMAE 0x00200000
135 #define UARTBAUD_MATCFG 0x00400000
136 #define UARTBAUD_BOTHEDGE 0x00020000
137 #define UARTBAUD_RESYNCDIS 0x00010000
138 #define UARTBAUD_LBKDIE 0x00008000
139 #define UARTBAUD_RXEDGIE 0x00004000
140 #define UARTBAUD_SBNS 0x00002000
141 #define UARTBAUD_SBR 0x00000000
142 #define UARTBAUD_SBR_MASK 0x1fff
143 #define UARTBAUD_OSR_MASK 0x1f
144 #define UARTBAUD_OSR_SHIFT 24
146 #define UARTSTAT_LBKDIF 0x80000000
147 #define UARTSTAT_RXEDGIF 0x40000000
148 #define UARTSTAT_MSBF 0x20000000
149 #define UARTSTAT_RXINV 0x10000000
150 #define UARTSTAT_RWUID 0x08000000
151 #define UARTSTAT_BRK13 0x04000000
152 #define UARTSTAT_LBKDE 0x02000000
153 #define UARTSTAT_RAF 0x01000000
154 #define UARTSTAT_TDRE 0x00800000
155 #define UARTSTAT_TC 0x00400000
156 #define UARTSTAT_RDRF 0x00200000
157 #define UARTSTAT_IDLE 0x00100000
158 #define UARTSTAT_OR 0x00080000
159 #define UARTSTAT_NF 0x00040000
160 #define UARTSTAT_FE 0x00020000
161 #define UARTSTAT_PE 0x00010000
162 #define UARTSTAT_MA1F 0x00008000
163 #define UARTSTAT_M21F 0x00004000
165 #define UARTCTRL_R8T9 0x80000000
166 #define UARTCTRL_R9T8 0x40000000
167 #define UARTCTRL_TXDIR 0x20000000
168 #define UARTCTRL_TXINV 0x10000000
169 #define UARTCTRL_ORIE 0x08000000
170 #define UARTCTRL_NEIE 0x04000000
171 #define UARTCTRL_FEIE 0x02000000
172 #define UARTCTRL_PEIE 0x01000000
173 #define UARTCTRL_TIE 0x00800000
174 #define UARTCTRL_TCIE 0x00400000
175 #define UARTCTRL_RIE 0x00200000
176 #define UARTCTRL_ILIE 0x00100000
177 #define UARTCTRL_TE 0x00080000
178 #define UARTCTRL_RE 0x00040000
179 #define UARTCTRL_RWU 0x00020000
180 #define UARTCTRL_SBK 0x00010000
181 #define UARTCTRL_MA1IE 0x00008000
182 #define UARTCTRL_MA2IE 0x00004000
183 #define UARTCTRL_IDLECFG 0x00000100
184 #define UARTCTRL_LOOPS 0x00000080
185 #define UARTCTRL_DOZEEN 0x00000040
186 #define UARTCTRL_RSRC 0x00000020
187 #define UARTCTRL_M 0x00000010
188 #define UARTCTRL_WAKE 0x00000008
189 #define UARTCTRL_ILT 0x00000004
190 #define UARTCTRL_PE 0x00000002
191 #define UARTCTRL_PT 0x00000001
193 #define UARTDATA_NOISY 0x00008000
194 #define UARTDATA_PARITYE 0x00004000
195 #define UARTDATA_FRETSC 0x00002000
196 #define UARTDATA_RXEMPT 0x00001000
197 #define UARTDATA_IDLINE 0x00000800
198 #define UARTDATA_MASK 0x3ff
200 #define UARTMODIR_IREN 0x00020000
201 #define UARTMODIR_TXCTSSRC 0x00000020
202 #define UARTMODIR_TXCTSC 0x00000010
203 #define UARTMODIR_RXRTSE 0x00000008
204 #define UARTMODIR_TXRTSPOL 0x00000004
205 #define UARTMODIR_TXRTSE 0x00000002
206 #define UARTMODIR_TXCTSE 0x00000001
208 #define UARTFIFO_TXEMPT 0x00800000
209 #define UARTFIFO_RXEMPT 0x00400000
210 #define UARTFIFO_TXOF 0x00020000
211 #define UARTFIFO_RXUF 0x00010000
212 #define UARTFIFO_TXFLUSH 0x00008000
213 #define UARTFIFO_RXFLUSH 0x00004000
214 #define UARTFIFO_TXOFE 0x00000200
215 #define UARTFIFO_RXUFE 0x00000100
216 #define UARTFIFO_TXFE 0x00000080
217 #define UARTFIFO_FIFOSIZE_MASK 0x7
218 #define UARTFIFO_TXSIZE_OFF 4
219 #define UARTFIFO_RXFE 0x00000008
220 #define UARTFIFO_RXSIZE_OFF 0
222 #define UARTWATER_COUNT_MASK 0xff
223 #define UARTWATER_TXCNT_OFF 8
224 #define UARTWATER_RXCNT_OFF 24
225 #define UARTWATER_WATER_MASK 0xff
226 #define UARTWATER_TXWATER_OFF 0
227 #define UARTWATER_RXWATER_OFF 16
229 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
230 #define DMA_RX_TIMEOUT (10)
232 #define DRIVER_NAME "fsl-lpuart"
233 #define DEV_NAME "ttyLP"
236 /* IMX lpuart has four extra unused regs located at the beginning */
237 #define IMX_REG_OFF 0x10
240 struct uart_port port
;
242 unsigned int txfifo_size
;
243 unsigned int rxfifo_size
;
245 bool lpuart_dma_tx_use
;
246 bool lpuart_dma_rx_use
;
247 struct dma_chan
*dma_tx_chan
;
248 struct dma_chan
*dma_rx_chan
;
249 struct dma_async_tx_descriptor
*dma_tx_desc
;
250 struct dma_async_tx_descriptor
*dma_rx_desc
;
251 dma_cookie_t dma_tx_cookie
;
252 dma_cookie_t dma_rx_cookie
;
253 unsigned int dma_tx_bytes
;
254 unsigned int dma_rx_bytes
;
255 bool dma_tx_in_progress
;
256 unsigned int dma_rx_timeout
;
257 struct timer_list lpuart_timer
;
258 struct scatterlist rx_sgl
, tx_sgl
[2];
259 struct circ_buf rx_ring
;
260 int rx_dma_rng_buf_len
;
261 unsigned int dma_tx_nents
;
262 wait_queue_head_t dma_wait
;
265 struct lpuart_soc_data
{
270 static const struct lpuart_soc_data vf_data
= {
274 static const struct lpuart_soc_data ls_data
= {
275 .iotype
= UPIO_MEM32BE
,
278 static struct lpuart_soc_data imx_data
= {
279 .iotype
= UPIO_MEM32
,
280 .reg_off
= IMX_REG_OFF
,
283 static const struct of_device_id lpuart_dt_ids
[] = {
284 { .compatible
= "fsl,vf610-lpuart", .data
= &vf_data
, },
285 { .compatible
= "fsl,ls1021a-lpuart", .data
= &ls_data
, },
286 { .compatible
= "fsl,imx7ulp-lpuart", .data
= &imx_data
, },
289 MODULE_DEVICE_TABLE(of
, lpuart_dt_ids
);
291 /* Forward declare this for the dma callbacks*/
292 static void lpuart_dma_tx_complete(void *arg
);
294 static inline u32
lpuart32_read(struct uart_port
*port
, u32 off
)
296 switch (port
->iotype
) {
298 return readl(port
->membase
+ off
);
300 return ioread32be(port
->membase
+ off
);
306 static inline void lpuart32_write(struct uart_port
*port
, u32 val
,
309 switch (port
->iotype
) {
311 writel(val
, port
->membase
+ off
);
314 iowrite32be(val
, port
->membase
+ off
);
319 static void lpuart_stop_tx(struct uart_port
*port
)
323 temp
= readb(port
->membase
+ UARTCR2
);
324 temp
&= ~(UARTCR2_TIE
| UARTCR2_TCIE
);
325 writeb(temp
, port
->membase
+ UARTCR2
);
328 static void lpuart32_stop_tx(struct uart_port
*port
)
332 temp
= lpuart32_read(port
, UARTCTRL
);
333 temp
&= ~(UARTCTRL_TIE
| UARTCTRL_TCIE
);
334 lpuart32_write(port
, temp
, UARTCTRL
);
337 static void lpuart_stop_rx(struct uart_port
*port
)
341 temp
= readb(port
->membase
+ UARTCR2
);
342 writeb(temp
& ~UARTCR2_RE
, port
->membase
+ UARTCR2
);
345 static void lpuart32_stop_rx(struct uart_port
*port
)
349 temp
= lpuart32_read(port
, UARTCTRL
);
350 lpuart32_write(port
, temp
& ~UARTCTRL_RE
, UARTCTRL
);
353 static void lpuart_dma_tx(struct lpuart_port
*sport
)
355 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
356 struct scatterlist
*sgl
= sport
->tx_sgl
;
357 struct device
*dev
= sport
->port
.dev
;
360 if (sport
->dma_tx_in_progress
)
363 sport
->dma_tx_bytes
= uart_circ_chars_pending(xmit
);
365 if (xmit
->tail
< xmit
->head
|| xmit
->head
== 0) {
366 sport
->dma_tx_nents
= 1;
367 sg_init_one(sgl
, xmit
->buf
+ xmit
->tail
, sport
->dma_tx_bytes
);
369 sport
->dma_tx_nents
= 2;
370 sg_init_table(sgl
, 2);
371 sg_set_buf(sgl
, xmit
->buf
+ xmit
->tail
,
372 UART_XMIT_SIZE
- xmit
->tail
);
373 sg_set_buf(sgl
+ 1, xmit
->buf
, xmit
->head
);
376 ret
= dma_map_sg(dev
, sgl
, sport
->dma_tx_nents
, DMA_TO_DEVICE
);
378 dev_err(dev
, "DMA mapping error for TX.\n");
382 sport
->dma_tx_desc
= dmaengine_prep_slave_sg(sport
->dma_tx_chan
, sgl
,
384 DMA_MEM_TO_DEV
, DMA_PREP_INTERRUPT
);
385 if (!sport
->dma_tx_desc
) {
386 dma_unmap_sg(dev
, sgl
, sport
->dma_tx_nents
, DMA_TO_DEVICE
);
387 dev_err(dev
, "Cannot prepare TX slave DMA!\n");
391 sport
->dma_tx_desc
->callback
= lpuart_dma_tx_complete
;
392 sport
->dma_tx_desc
->callback_param
= sport
;
393 sport
->dma_tx_in_progress
= true;
394 sport
->dma_tx_cookie
= dmaengine_submit(sport
->dma_tx_desc
);
395 dma_async_issue_pending(sport
->dma_tx_chan
);
398 static void lpuart_dma_tx_complete(void *arg
)
400 struct lpuart_port
*sport
= arg
;
401 struct scatterlist
*sgl
= &sport
->tx_sgl
[0];
402 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
405 spin_lock_irqsave(&sport
->port
.lock
, flags
);
407 dma_unmap_sg(sport
->port
.dev
, sgl
, sport
->dma_tx_nents
, DMA_TO_DEVICE
);
409 xmit
->tail
= (xmit
->tail
+ sport
->dma_tx_bytes
) & (UART_XMIT_SIZE
- 1);
411 sport
->port
.icount
.tx
+= sport
->dma_tx_bytes
;
412 sport
->dma_tx_in_progress
= false;
413 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
415 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
416 uart_write_wakeup(&sport
->port
);
418 if (waitqueue_active(&sport
->dma_wait
)) {
419 wake_up(&sport
->dma_wait
);
423 spin_lock_irqsave(&sport
->port
.lock
, flags
);
425 if (!uart_circ_empty(xmit
) && !uart_tx_stopped(&sport
->port
))
426 lpuart_dma_tx(sport
);
428 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
431 static int lpuart_dma_tx_request(struct uart_port
*port
)
433 struct lpuart_port
*sport
= container_of(port
,
434 struct lpuart_port
, port
);
435 struct dma_slave_config dma_tx_sconfig
= {};
438 dma_tx_sconfig
.dst_addr
= sport
->port
.mapbase
+ UARTDR
;
439 dma_tx_sconfig
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
440 dma_tx_sconfig
.dst_maxburst
= 1;
441 dma_tx_sconfig
.direction
= DMA_MEM_TO_DEV
;
442 ret
= dmaengine_slave_config(sport
->dma_tx_chan
, &dma_tx_sconfig
);
445 dev_err(sport
->port
.dev
,
446 "DMA slave config failed, err = %d\n", ret
);
453 static void lpuart_flush_buffer(struct uart_port
*port
)
455 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
457 if (sport
->lpuart_dma_tx_use
) {
458 if (sport
->dma_tx_in_progress
) {
459 dma_unmap_sg(sport
->port
.dev
, &sport
->tx_sgl
[0],
460 sport
->dma_tx_nents
, DMA_TO_DEVICE
);
461 sport
->dma_tx_in_progress
= false;
463 dmaengine_terminate_all(sport
->dma_tx_chan
);
467 #if defined(CONFIG_CONSOLE_POLL)
469 static int lpuart_poll_init(struct uart_port
*port
)
471 struct lpuart_port
*sport
= container_of(port
,
472 struct lpuart_port
, port
);
476 sport
->port
.fifosize
= 0;
478 spin_lock_irqsave(&sport
->port
.lock
, flags
);
479 /* Disable Rx & Tx */
480 writeb(0, sport
->port
.membase
+ UARTCR2
);
482 temp
= readb(sport
->port
.membase
+ UARTPFIFO
);
483 /* Enable Rx and Tx FIFO */
484 writeb(temp
| UARTPFIFO_RXFE
| UARTPFIFO_TXFE
,
485 sport
->port
.membase
+ UARTPFIFO
);
487 /* flush Tx and Rx FIFO */
488 writeb(UARTCFIFO_TXFLUSH
| UARTCFIFO_RXFLUSH
,
489 sport
->port
.membase
+ UARTCFIFO
);
491 /* explicitly clear RDRF */
492 if (readb(sport
->port
.membase
+ UARTSR1
) & UARTSR1_RDRF
) {
493 readb(sport
->port
.membase
+ UARTDR
);
494 writeb(UARTSFIFO_RXUF
, sport
->port
.membase
+ UARTSFIFO
);
497 writeb(0, sport
->port
.membase
+ UARTTWFIFO
);
498 writeb(1, sport
->port
.membase
+ UARTRWFIFO
);
500 /* Enable Rx and Tx */
501 writeb(UARTCR2_RE
| UARTCR2_TE
, sport
->port
.membase
+ UARTCR2
);
502 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
507 static void lpuart_poll_put_char(struct uart_port
*port
, unsigned char c
)
510 while (!(readb(port
->membase
+ UARTSR1
) & UARTSR1_TDRE
))
513 writeb(c
, port
->membase
+ UARTDR
);
516 static int lpuart_poll_get_char(struct uart_port
*port
)
518 if (!(readb(port
->membase
+ UARTSR1
) & UARTSR1_RDRF
))
521 return readb(port
->membase
+ UARTDR
);
526 static inline void lpuart_transmit_buffer(struct lpuart_port
*sport
)
528 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
530 while (!uart_circ_empty(xmit
) &&
531 (readb(sport
->port
.membase
+ UARTTCFIFO
) < sport
->txfifo_size
)) {
532 writeb(xmit
->buf
[xmit
->tail
], sport
->port
.membase
+ UARTDR
);
533 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
534 sport
->port
.icount
.tx
++;
537 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
538 uart_write_wakeup(&sport
->port
);
540 if (uart_circ_empty(xmit
))
541 lpuart_stop_tx(&sport
->port
);
544 static inline void lpuart32_transmit_buffer(struct lpuart_port
*sport
)
546 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
549 txcnt
= lpuart32_read(&sport
->port
, UARTWATER
);
550 txcnt
= txcnt
>> UARTWATER_TXCNT_OFF
;
551 txcnt
&= UARTWATER_COUNT_MASK
;
552 while (!uart_circ_empty(xmit
) && (txcnt
< sport
->txfifo_size
)) {
553 lpuart32_write(&sport
->port
, xmit
->buf
[xmit
->tail
], UARTDATA
);
554 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
555 sport
->port
.icount
.tx
++;
556 txcnt
= lpuart32_read(&sport
->port
, UARTWATER
);
557 txcnt
= txcnt
>> UARTWATER_TXCNT_OFF
;
558 txcnt
&= UARTWATER_COUNT_MASK
;
561 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
562 uart_write_wakeup(&sport
->port
);
564 if (uart_circ_empty(xmit
))
565 lpuart32_stop_tx(&sport
->port
);
568 static void lpuart_start_tx(struct uart_port
*port
)
570 struct lpuart_port
*sport
= container_of(port
,
571 struct lpuart_port
, port
);
572 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
575 temp
= readb(port
->membase
+ UARTCR2
);
576 writeb(temp
| UARTCR2_TIE
, port
->membase
+ UARTCR2
);
578 if (sport
->lpuart_dma_tx_use
) {
579 if (!uart_circ_empty(xmit
) && !uart_tx_stopped(port
))
580 lpuart_dma_tx(sport
);
582 if (readb(port
->membase
+ UARTSR1
) & UARTSR1_TDRE
)
583 lpuart_transmit_buffer(sport
);
587 static void lpuart32_start_tx(struct uart_port
*port
)
589 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
592 temp
= lpuart32_read(port
, UARTCTRL
);
593 lpuart32_write(port
, temp
| UARTCTRL_TIE
, UARTCTRL
);
595 if (lpuart32_read(port
, UARTSTAT
) & UARTSTAT_TDRE
)
596 lpuart32_transmit_buffer(sport
);
599 /* return TIOCSER_TEMT when transmitter is not busy */
600 static unsigned int lpuart_tx_empty(struct uart_port
*port
)
602 struct lpuart_port
*sport
= container_of(port
,
603 struct lpuart_port
, port
);
604 unsigned char sr1
= readb(port
->membase
+ UARTSR1
);
605 unsigned char sfifo
= readb(port
->membase
+ UARTSFIFO
);
607 if (sport
->dma_tx_in_progress
)
610 if (sr1
& UARTSR1_TC
&& sfifo
& UARTSFIFO_TXEMPT
)
616 static unsigned int lpuart32_tx_empty(struct uart_port
*port
)
618 return (lpuart32_read(port
, UARTSTAT
) & UARTSTAT_TC
) ?
622 static bool lpuart_is_32(struct lpuart_port
*sport
)
624 return sport
->port
.iotype
== UPIO_MEM32
||
625 sport
->port
.iotype
== UPIO_MEM32BE
;
628 static irqreturn_t
lpuart_txint(int irq
, void *dev_id
)
630 struct lpuart_port
*sport
= dev_id
;
631 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
634 spin_lock_irqsave(&sport
->port
.lock
, flags
);
635 if (sport
->port
.x_char
) {
636 if (lpuart_is_32(sport
))
637 lpuart32_write(&sport
->port
, sport
->port
.x_char
, UARTDATA
);
639 writeb(sport
->port
.x_char
, sport
->port
.membase
+ UARTDR
);
643 if (uart_circ_empty(xmit
) || uart_tx_stopped(&sport
->port
)) {
644 if (lpuart_is_32(sport
))
645 lpuart32_stop_tx(&sport
->port
);
647 lpuart_stop_tx(&sport
->port
);
651 if (lpuart_is_32(sport
))
652 lpuart32_transmit_buffer(sport
);
654 lpuart_transmit_buffer(sport
);
656 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
657 uart_write_wakeup(&sport
->port
);
660 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
664 static irqreturn_t
lpuart_rxint(int irq
, void *dev_id
)
666 struct lpuart_port
*sport
= dev_id
;
667 unsigned int flg
, ignored
= 0;
668 struct tty_port
*port
= &sport
->port
.state
->port
;
670 unsigned char rx
, sr
;
672 spin_lock_irqsave(&sport
->port
.lock
, flags
);
674 while (!(readb(sport
->port
.membase
+ UARTSFIFO
) & UARTSFIFO_RXEMPT
)) {
676 sport
->port
.icount
.rx
++;
678 * to clear the FE, OR, NF, FE, PE flags,
679 * read SR1 then read DR
681 sr
= readb(sport
->port
.membase
+ UARTSR1
);
682 rx
= readb(sport
->port
.membase
+ UARTDR
);
684 if (uart_handle_sysrq_char(&sport
->port
, (unsigned char)rx
))
687 if (sr
& (UARTSR1_PE
| UARTSR1_OR
| UARTSR1_FE
)) {
689 sport
->port
.icount
.parity
++;
690 else if (sr
& UARTSR1_FE
)
691 sport
->port
.icount
.frame
++;
694 sport
->port
.icount
.overrun
++;
696 if (sr
& sport
->port
.ignore_status_mask
) {
702 sr
&= sport
->port
.read_status_mask
;
706 else if (sr
& UARTSR1_FE
)
713 sport
->port
.sysrq
= 0;
717 tty_insert_flip_char(port
, rx
, flg
);
721 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
723 tty_flip_buffer_push(port
);
727 static irqreturn_t
lpuart32_rxint(int irq
, void *dev_id
)
729 struct lpuart_port
*sport
= dev_id
;
730 unsigned int flg
, ignored
= 0;
731 struct tty_port
*port
= &sport
->port
.state
->port
;
733 unsigned long rx
, sr
;
735 spin_lock_irqsave(&sport
->port
.lock
, flags
);
737 while (!(lpuart32_read(&sport
->port
, UARTFIFO
) & UARTFIFO_RXEMPT
)) {
739 sport
->port
.icount
.rx
++;
741 * to clear the FE, OR, NF, FE, PE flags,
742 * read STAT then read DATA reg
744 sr
= lpuart32_read(&sport
->port
, UARTSTAT
);
745 rx
= lpuart32_read(&sport
->port
, UARTDATA
);
748 if (uart_handle_sysrq_char(&sport
->port
, (unsigned char)rx
))
751 if (sr
& (UARTSTAT_PE
| UARTSTAT_OR
| UARTSTAT_FE
)) {
752 if (sr
& UARTSTAT_PE
)
753 sport
->port
.icount
.parity
++;
754 else if (sr
& UARTSTAT_FE
)
755 sport
->port
.icount
.frame
++;
757 if (sr
& UARTSTAT_OR
)
758 sport
->port
.icount
.overrun
++;
760 if (sr
& sport
->port
.ignore_status_mask
) {
766 sr
&= sport
->port
.read_status_mask
;
768 if (sr
& UARTSTAT_PE
)
770 else if (sr
& UARTSTAT_FE
)
773 if (sr
& UARTSTAT_OR
)
777 sport
->port
.sysrq
= 0;
781 tty_insert_flip_char(port
, rx
, flg
);
785 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
787 tty_flip_buffer_push(port
);
791 static irqreturn_t
lpuart_int(int irq
, void *dev_id
)
793 struct lpuart_port
*sport
= dev_id
;
796 sts
= readb(sport
->port
.membase
+ UARTSR1
);
798 if (sts
& UARTSR1_RDRF
)
799 lpuart_rxint(irq
, dev_id
);
801 if (sts
& UARTSR1_TDRE
)
802 lpuart_txint(irq
, dev_id
);
807 static irqreturn_t
lpuart32_int(int irq
, void *dev_id
)
809 struct lpuart_port
*sport
= dev_id
;
810 unsigned long sts
, rxcount
;
812 sts
= lpuart32_read(&sport
->port
, UARTSTAT
);
813 rxcount
= lpuart32_read(&sport
->port
, UARTWATER
);
814 rxcount
= rxcount
>> UARTWATER_RXCNT_OFF
;
816 if (sts
& UARTSTAT_RDRF
|| rxcount
> 0)
817 lpuart32_rxint(irq
, dev_id
);
819 if ((sts
& UARTSTAT_TDRE
) &&
820 !(lpuart32_read(&sport
->port
, UARTBAUD
) & UARTBAUD_TDMAE
))
821 lpuart_txint(irq
, dev_id
);
823 lpuart32_write(&sport
->port
, sts
, UARTSTAT
);
827 static void lpuart_copy_rx_to_tty(struct lpuart_port
*sport
)
829 struct tty_port
*port
= &sport
->port
.state
->port
;
830 struct dma_tx_state state
;
831 enum dma_status dmastat
;
832 struct circ_buf
*ring
= &sport
->rx_ring
;
837 sr
= readb(sport
->port
.membase
+ UARTSR1
);
839 if (sr
& (UARTSR1_PE
| UARTSR1_FE
)) {
840 /* Read DR to clear the error flags */
841 readb(sport
->port
.membase
+ UARTDR
);
844 sport
->port
.icount
.parity
++;
845 else if (sr
& UARTSR1_FE
)
846 sport
->port
.icount
.frame
++;
849 async_tx_ack(sport
->dma_rx_desc
);
851 spin_lock_irqsave(&sport
->port
.lock
, flags
);
853 dmastat
= dmaengine_tx_status(sport
->dma_rx_chan
,
854 sport
->dma_rx_cookie
,
857 if (dmastat
== DMA_ERROR
) {
858 dev_err(sport
->port
.dev
, "Rx DMA transfer failed!\n");
859 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
863 /* CPU claims ownership of RX DMA buffer */
864 dma_sync_sg_for_cpu(sport
->port
.dev
, &sport
->rx_sgl
, 1, DMA_FROM_DEVICE
);
867 * ring->head points to the end of data already written by the DMA.
868 * ring->tail points to the beginning of data to be read by the
870 * The current transfer size should not be larger than the dma buffer
873 ring
->head
= sport
->rx_sgl
.length
- state
.residue
;
874 BUG_ON(ring
->head
> sport
->rx_sgl
.length
);
876 * At this point ring->head may point to the first byte right after the
877 * last byte of the dma buffer:
878 * 0 <= ring->head <= sport->rx_sgl.length
880 * However ring->tail must always points inside the dma buffer:
881 * 0 <= ring->tail <= sport->rx_sgl.length - 1
883 * Since we use a ring buffer, we have to handle the case
884 * where head is lower than tail. In such a case, we first read from
885 * tail to the end of the buffer then reset tail.
887 if (ring
->head
< ring
->tail
) {
888 count
= sport
->rx_sgl
.length
- ring
->tail
;
890 tty_insert_flip_string(port
, ring
->buf
+ ring
->tail
, count
);
892 sport
->port
.icount
.rx
+= count
;
895 /* Finally we read data from tail to head */
896 if (ring
->tail
< ring
->head
) {
897 count
= ring
->head
- ring
->tail
;
898 tty_insert_flip_string(port
, ring
->buf
+ ring
->tail
, count
);
899 /* Wrap ring->head if needed */
900 if (ring
->head
>= sport
->rx_sgl
.length
)
902 ring
->tail
= ring
->head
;
903 sport
->port
.icount
.rx
+= count
;
906 dma_sync_sg_for_device(sport
->port
.dev
, &sport
->rx_sgl
, 1,
909 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
911 tty_flip_buffer_push(port
);
912 mod_timer(&sport
->lpuart_timer
, jiffies
+ sport
->dma_rx_timeout
);
915 static void lpuart_dma_rx_complete(void *arg
)
917 struct lpuart_port
*sport
= arg
;
919 lpuart_copy_rx_to_tty(sport
);
922 static void lpuart_timer_func(unsigned long data
)
924 struct lpuart_port
*sport
= (struct lpuart_port
*)data
;
926 lpuart_copy_rx_to_tty(sport
);
929 static inline int lpuart_start_rx_dma(struct lpuart_port
*sport
)
931 struct dma_slave_config dma_rx_sconfig
= {};
932 struct circ_buf
*ring
= &sport
->rx_ring
;
935 struct tty_struct
*tty
= tty_port_tty_get(&sport
->port
.state
->port
);
936 struct ktermios
*termios
= &tty
->termios
;
938 baud
= tty_get_baud_rate(tty
);
940 bits
= (termios
->c_cflag
& CSIZE
) == CS7
? 9 : 10;
941 if (termios
->c_cflag
& PARENB
)
945 * Calculate length of one DMA buffer size to keep latency below
946 * 10ms at any baud rate.
948 sport
->rx_dma_rng_buf_len
= (DMA_RX_TIMEOUT
* baud
/ bits
/ 1000) * 2;
949 sport
->rx_dma_rng_buf_len
= (1 << (fls(sport
->rx_dma_rng_buf_len
) - 1));
950 if (sport
->rx_dma_rng_buf_len
< 16)
951 sport
->rx_dma_rng_buf_len
= 16;
953 ring
->buf
= kmalloc(sport
->rx_dma_rng_buf_len
, GFP_ATOMIC
);
955 dev_err(sport
->port
.dev
, "Ring buf alloc failed\n");
959 sg_init_one(&sport
->rx_sgl
, ring
->buf
, sport
->rx_dma_rng_buf_len
);
960 sg_set_buf(&sport
->rx_sgl
, ring
->buf
, sport
->rx_dma_rng_buf_len
);
961 nent
= dma_map_sg(sport
->port
.dev
, &sport
->rx_sgl
, 1, DMA_FROM_DEVICE
);
964 dev_err(sport
->port
.dev
, "DMA Rx mapping error\n");
968 dma_rx_sconfig
.src_addr
= sport
->port
.mapbase
+ UARTDR
;
969 dma_rx_sconfig
.src_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
970 dma_rx_sconfig
.src_maxburst
= 1;
971 dma_rx_sconfig
.direction
= DMA_DEV_TO_MEM
;
972 ret
= dmaengine_slave_config(sport
->dma_rx_chan
, &dma_rx_sconfig
);
975 dev_err(sport
->port
.dev
,
976 "DMA Rx slave config failed, err = %d\n", ret
);
980 sport
->dma_rx_desc
= dmaengine_prep_dma_cyclic(sport
->dma_rx_chan
,
981 sg_dma_address(&sport
->rx_sgl
),
982 sport
->rx_sgl
.length
,
983 sport
->rx_sgl
.length
/ 2,
986 if (!sport
->dma_rx_desc
) {
987 dev_err(sport
->port
.dev
, "Cannot prepare cyclic DMA\n");
991 sport
->dma_rx_desc
->callback
= lpuart_dma_rx_complete
;
992 sport
->dma_rx_desc
->callback_param
= sport
;
993 sport
->dma_rx_cookie
= dmaengine_submit(sport
->dma_rx_desc
);
994 dma_async_issue_pending(sport
->dma_rx_chan
);
996 writeb(readb(sport
->port
.membase
+ UARTCR5
) | UARTCR5_RDMAS
,
997 sport
->port
.membase
+ UARTCR5
);
1002 static void lpuart_dma_rx_free(struct uart_port
*port
)
1004 struct lpuart_port
*sport
= container_of(port
,
1005 struct lpuart_port
, port
);
1007 if (sport
->dma_rx_chan
)
1008 dmaengine_terminate_all(sport
->dma_rx_chan
);
1010 dma_unmap_sg(sport
->port
.dev
, &sport
->rx_sgl
, 1, DMA_FROM_DEVICE
);
1011 kfree(sport
->rx_ring
.buf
);
1012 sport
->rx_ring
.tail
= 0;
1013 sport
->rx_ring
.head
= 0;
1014 sport
->dma_rx_desc
= NULL
;
1015 sport
->dma_rx_cookie
= -EINVAL
;
1018 static int lpuart_config_rs485(struct uart_port
*port
,
1019 struct serial_rs485
*rs485
)
1021 struct lpuart_port
*sport
= container_of(port
,
1022 struct lpuart_port
, port
);
1024 u8 modem
= readb(sport
->port
.membase
+ UARTMODEM
) &
1025 ~(UARTMODEM_TXRTSPOL
| UARTMODEM_TXRTSE
);
1026 writeb(modem
, sport
->port
.membase
+ UARTMODEM
);
1028 if (rs485
->flags
& SER_RS485_ENABLED
) {
1029 /* Enable auto RS-485 RTS mode */
1030 modem
|= UARTMODEM_TXRTSE
;
1033 * RTS needs to be logic HIGH either during transer _or_ after
1034 * transfer, other variants are not supported by the hardware.
1037 if (!(rs485
->flags
& (SER_RS485_RTS_ON_SEND
|
1038 SER_RS485_RTS_AFTER_SEND
)))
1039 rs485
->flags
|= SER_RS485_RTS_ON_SEND
;
1041 if (rs485
->flags
& SER_RS485_RTS_ON_SEND
&&
1042 rs485
->flags
& SER_RS485_RTS_AFTER_SEND
)
1043 rs485
->flags
&= ~SER_RS485_RTS_AFTER_SEND
;
1046 * The hardware defaults to RTS logic HIGH while transfer.
1047 * Switch polarity in case RTS shall be logic HIGH
1049 * Note: UART is assumed to be active high.
1051 if (rs485
->flags
& SER_RS485_RTS_ON_SEND
)
1052 modem
&= ~UARTMODEM_TXRTSPOL
;
1053 else if (rs485
->flags
& SER_RS485_RTS_AFTER_SEND
)
1054 modem
|= UARTMODEM_TXRTSPOL
;
1057 /* Store the new configuration */
1058 sport
->port
.rs485
= *rs485
;
1060 writeb(modem
, sport
->port
.membase
+ UARTMODEM
);
1064 static unsigned int lpuart_get_mctrl(struct uart_port
*port
)
1066 unsigned int temp
= 0;
1069 reg
= readb(port
->membase
+ UARTMODEM
);
1070 if (reg
& UARTMODEM_TXCTSE
)
1073 if (reg
& UARTMODEM_RXRTSE
)
1079 static unsigned int lpuart32_get_mctrl(struct uart_port
*port
)
1081 unsigned int temp
= 0;
1084 reg
= lpuart32_read(port
, UARTMODIR
);
1085 if (reg
& UARTMODIR_TXCTSE
)
1088 if (reg
& UARTMODIR_RXRTSE
)
1094 static void lpuart_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
1097 struct lpuart_port
*sport
= container_of(port
,
1098 struct lpuart_port
, port
);
1100 /* Make sure RXRTSE bit is not set when RS485 is enabled */
1101 if (!(sport
->port
.rs485
.flags
& SER_RS485_ENABLED
)) {
1102 temp
= readb(sport
->port
.membase
+ UARTMODEM
) &
1103 ~(UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1105 if (mctrl
& TIOCM_RTS
)
1106 temp
|= UARTMODEM_RXRTSE
;
1108 if (mctrl
& TIOCM_CTS
)
1109 temp
|= UARTMODEM_TXCTSE
;
1111 writeb(temp
, port
->membase
+ UARTMODEM
);
1115 static void lpuart32_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
1119 temp
= lpuart32_read(port
, UARTMODIR
) &
1120 ~(UARTMODIR_RXRTSE
| UARTMODIR_TXCTSE
);
1122 if (mctrl
& TIOCM_RTS
)
1123 temp
|= UARTMODIR_RXRTSE
;
1125 if (mctrl
& TIOCM_CTS
)
1126 temp
|= UARTMODIR_TXCTSE
;
1128 lpuart32_write(port
, temp
, UARTMODIR
);
1131 static void lpuart_break_ctl(struct uart_port
*port
, int break_state
)
1135 temp
= readb(port
->membase
+ UARTCR2
) & ~UARTCR2_SBK
;
1137 if (break_state
!= 0)
1138 temp
|= UARTCR2_SBK
;
1140 writeb(temp
, port
->membase
+ UARTCR2
);
1143 static void lpuart32_break_ctl(struct uart_port
*port
, int break_state
)
1147 temp
= lpuart32_read(port
, UARTCTRL
) & ~UARTCTRL_SBK
;
1149 if (break_state
!= 0)
1150 temp
|= UARTCTRL_SBK
;
1152 lpuart32_write(port
, temp
, UARTCTRL
);
1155 static void lpuart_setup_watermark(struct lpuart_port
*sport
)
1157 unsigned char val
, cr2
;
1158 unsigned char cr2_saved
;
1160 cr2
= readb(sport
->port
.membase
+ UARTCR2
);
1162 cr2
&= ~(UARTCR2_TIE
| UARTCR2_TCIE
| UARTCR2_TE
|
1163 UARTCR2_RIE
| UARTCR2_RE
);
1164 writeb(cr2
, sport
->port
.membase
+ UARTCR2
);
1166 val
= readb(sport
->port
.membase
+ UARTPFIFO
);
1167 writeb(val
| UARTPFIFO_TXFE
| UARTPFIFO_RXFE
,
1168 sport
->port
.membase
+ UARTPFIFO
);
1170 /* flush Tx and Rx FIFO */
1171 writeb(UARTCFIFO_TXFLUSH
| UARTCFIFO_RXFLUSH
,
1172 sport
->port
.membase
+ UARTCFIFO
);
1174 /* explicitly clear RDRF */
1175 if (readb(sport
->port
.membase
+ UARTSR1
) & UARTSR1_RDRF
) {
1176 readb(sport
->port
.membase
+ UARTDR
);
1177 writeb(UARTSFIFO_RXUF
, sport
->port
.membase
+ UARTSFIFO
);
1180 writeb(0, sport
->port
.membase
+ UARTTWFIFO
);
1181 writeb(1, sport
->port
.membase
+ UARTRWFIFO
);
1184 writeb(cr2_saved
, sport
->port
.membase
+ UARTCR2
);
1187 static void lpuart32_setup_watermark(struct lpuart_port
*sport
)
1189 unsigned long val
, ctrl
;
1190 unsigned long ctrl_saved
;
1192 ctrl
= lpuart32_read(&sport
->port
, UARTCTRL
);
1194 ctrl
&= ~(UARTCTRL_TIE
| UARTCTRL_TCIE
| UARTCTRL_TE
|
1195 UARTCTRL_RIE
| UARTCTRL_RE
);
1196 lpuart32_write(&sport
->port
, ctrl
, UARTCTRL
);
1198 /* enable FIFO mode */
1199 val
= lpuart32_read(&sport
->port
, UARTFIFO
);
1200 val
|= UARTFIFO_TXFE
| UARTFIFO_RXFE
;
1201 val
|= UARTFIFO_TXFLUSH
| UARTFIFO_RXFLUSH
;
1202 lpuart32_write(&sport
->port
, val
, UARTFIFO
);
1204 /* set the watermark */
1205 val
= (0x1 << UARTWATER_RXWATER_OFF
) | (0x0 << UARTWATER_TXWATER_OFF
);
1206 lpuart32_write(&sport
->port
, val
, UARTWATER
);
1209 lpuart32_write(&sport
->port
, ctrl_saved
, UARTCTRL
);
1212 static void rx_dma_timer_init(struct lpuart_port
*sport
)
1214 setup_timer(&sport
->lpuart_timer
, lpuart_timer_func
,
1215 (unsigned long)sport
);
1216 sport
->lpuart_timer
.expires
= jiffies
+ sport
->dma_rx_timeout
;
1217 add_timer(&sport
->lpuart_timer
);
1220 static int lpuart_startup(struct uart_port
*port
)
1222 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1224 unsigned long flags
;
1227 /* determine FIFO size and enable FIFO mode */
1228 temp
= readb(sport
->port
.membase
+ UARTPFIFO
);
1230 sport
->txfifo_size
= 0x1 << (((temp
>> UARTPFIFO_TXSIZE_OFF
) &
1231 UARTPFIFO_FIFOSIZE_MASK
) + 1);
1233 sport
->port
.fifosize
= sport
->txfifo_size
;
1235 sport
->rxfifo_size
= 0x1 << (((temp
>> UARTPFIFO_RXSIZE_OFF
) &
1236 UARTPFIFO_FIFOSIZE_MASK
) + 1);
1238 ret
= devm_request_irq(port
->dev
, port
->irq
, lpuart_int
, 0,
1239 DRIVER_NAME
, sport
);
1243 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1245 lpuart_setup_watermark(sport
);
1247 temp
= readb(sport
->port
.membase
+ UARTCR2
);
1248 temp
|= (UARTCR2_RIE
| UARTCR2_TIE
| UARTCR2_RE
| UARTCR2_TE
);
1249 writeb(temp
, sport
->port
.membase
+ UARTCR2
);
1251 if (sport
->dma_rx_chan
&& !lpuart_start_rx_dma(sport
)) {
1252 /* set Rx DMA timeout */
1253 sport
->dma_rx_timeout
= msecs_to_jiffies(DMA_RX_TIMEOUT
);
1254 if (!sport
->dma_rx_timeout
)
1255 sport
->dma_rx_timeout
= 1;
1257 sport
->lpuart_dma_rx_use
= true;
1258 rx_dma_timer_init(sport
);
1260 sport
->lpuart_dma_rx_use
= false;
1263 if (sport
->dma_tx_chan
&& !lpuart_dma_tx_request(port
)) {
1264 init_waitqueue_head(&sport
->dma_wait
);
1265 sport
->lpuart_dma_tx_use
= true;
1266 temp
= readb(port
->membase
+ UARTCR5
);
1267 writeb(temp
| UARTCR5_TDMAS
, port
->membase
+ UARTCR5
);
1269 sport
->lpuart_dma_tx_use
= false;
1272 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1277 static int lpuart32_startup(struct uart_port
*port
)
1279 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1281 unsigned long flags
;
1284 /* determine FIFO size */
1285 temp
= lpuart32_read(&sport
->port
, UARTFIFO
);
1287 sport
->txfifo_size
= 0x1 << (((temp
>> UARTFIFO_TXSIZE_OFF
) &
1288 UARTFIFO_FIFOSIZE_MASK
) - 1);
1290 sport
->rxfifo_size
= 0x1 << (((temp
>> UARTFIFO_RXSIZE_OFF
) &
1291 UARTFIFO_FIFOSIZE_MASK
) - 1);
1293 ret
= devm_request_irq(port
->dev
, port
->irq
, lpuart32_int
, 0,
1294 DRIVER_NAME
, sport
);
1298 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1300 lpuart32_setup_watermark(sport
);
1302 temp
= lpuart32_read(&sport
->port
, UARTCTRL
);
1303 temp
|= (UARTCTRL_RIE
| UARTCTRL_TIE
| UARTCTRL_RE
| UARTCTRL_TE
);
1304 temp
|= UARTCTRL_ILIE
;
1305 lpuart32_write(&sport
->port
, temp
, UARTCTRL
);
1307 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1311 static void lpuart_shutdown(struct uart_port
*port
)
1313 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1315 unsigned long flags
;
1317 spin_lock_irqsave(&port
->lock
, flags
);
1319 /* disable Rx/Tx and interrupts */
1320 temp
= readb(port
->membase
+ UARTCR2
);
1321 temp
&= ~(UARTCR2_TE
| UARTCR2_RE
|
1322 UARTCR2_TIE
| UARTCR2_TCIE
| UARTCR2_RIE
);
1323 writeb(temp
, port
->membase
+ UARTCR2
);
1325 spin_unlock_irqrestore(&port
->lock
, flags
);
1327 devm_free_irq(port
->dev
, port
->irq
, sport
);
1329 if (sport
->lpuart_dma_rx_use
) {
1330 del_timer_sync(&sport
->lpuart_timer
);
1331 lpuart_dma_rx_free(&sport
->port
);
1334 if (sport
->lpuart_dma_tx_use
) {
1335 if (wait_event_interruptible(sport
->dma_wait
,
1336 !sport
->dma_tx_in_progress
) != false) {
1337 sport
->dma_tx_in_progress
= false;
1338 dmaengine_terminate_all(sport
->dma_tx_chan
);
1341 lpuart_stop_tx(port
);
1345 static void lpuart32_shutdown(struct uart_port
*port
)
1347 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1349 unsigned long flags
;
1351 spin_lock_irqsave(&port
->lock
, flags
);
1353 /* disable Rx/Tx and interrupts */
1354 temp
= lpuart32_read(port
, UARTCTRL
);
1355 temp
&= ~(UARTCTRL_TE
| UARTCTRL_RE
|
1356 UARTCTRL_TIE
| UARTCTRL_TCIE
| UARTCTRL_RIE
);
1357 lpuart32_write(port
, temp
, UARTCTRL
);
1359 spin_unlock_irqrestore(&port
->lock
, flags
);
1361 devm_free_irq(port
->dev
, port
->irq
, sport
);
1365 lpuart_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
1366 struct ktermios
*old
)
1368 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1369 unsigned long flags
;
1370 unsigned char cr1
, old_cr1
, old_cr2
, cr3
, cr4
, bdh
, modem
;
1372 unsigned int old_csize
= old
? old
->c_cflag
& CSIZE
: CS8
;
1373 unsigned int sbr
, brfa
;
1375 cr1
= old_cr1
= readb(sport
->port
.membase
+ UARTCR1
);
1376 old_cr2
= readb(sport
->port
.membase
+ UARTCR2
);
1377 cr3
= readb(sport
->port
.membase
+ UARTCR3
);
1378 cr4
= readb(sport
->port
.membase
+ UARTCR4
);
1379 bdh
= readb(sport
->port
.membase
+ UARTBDH
);
1380 modem
= readb(sport
->port
.membase
+ UARTMODEM
);
1382 * only support CS8 and CS7, and for CS7 must enable PE.
1389 while ((termios
->c_cflag
& CSIZE
) != CS8
&&
1390 (termios
->c_cflag
& CSIZE
) != CS7
) {
1391 termios
->c_cflag
&= ~CSIZE
;
1392 termios
->c_cflag
|= old_csize
;
1396 if ((termios
->c_cflag
& CSIZE
) == CS8
||
1397 (termios
->c_cflag
& CSIZE
) == CS7
)
1398 cr1
= old_cr1
& ~UARTCR1_M
;
1400 if (termios
->c_cflag
& CMSPAR
) {
1401 if ((termios
->c_cflag
& CSIZE
) != CS8
) {
1402 termios
->c_cflag
&= ~CSIZE
;
1403 termios
->c_cflag
|= CS8
;
1409 * When auto RS-485 RTS mode is enabled,
1410 * hardware flow control need to be disabled.
1412 if (sport
->port
.rs485
.flags
& SER_RS485_ENABLED
)
1413 termios
->c_cflag
&= ~CRTSCTS
;
1415 if (termios
->c_cflag
& CRTSCTS
) {
1416 modem
|= (UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1418 termios
->c_cflag
&= ~CRTSCTS
;
1419 modem
&= ~(UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1422 if (termios
->c_cflag
& CSTOPB
)
1423 termios
->c_cflag
&= ~CSTOPB
;
1425 /* parity must be enabled when CS7 to match 8-bits format */
1426 if ((termios
->c_cflag
& CSIZE
) == CS7
)
1427 termios
->c_cflag
|= PARENB
;
1429 if ((termios
->c_cflag
& PARENB
)) {
1430 if (termios
->c_cflag
& CMSPAR
) {
1432 if (termios
->c_cflag
& PARODD
)
1438 if ((termios
->c_cflag
& CSIZE
) == CS8
)
1440 if (termios
->c_cflag
& PARODD
)
1447 /* ask the core to calculate the divisor */
1448 baud
= uart_get_baud_rate(port
, termios
, old
, 50, port
->uartclk
/ 16);
1451 * Need to update the Ring buffer length according to the selected
1452 * baud rate and restart Rx DMA path.
1454 * Since timer function acqures sport->port.lock, need to stop before
1455 * acquring same lock because otherwise del_timer_sync() can deadlock.
1457 if (old
&& sport
->lpuart_dma_rx_use
) {
1458 del_timer_sync(&sport
->lpuart_timer
);
1459 lpuart_dma_rx_free(&sport
->port
);
1462 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1464 sport
->port
.read_status_mask
= 0;
1465 if (termios
->c_iflag
& INPCK
)
1466 sport
->port
.read_status_mask
|= (UARTSR1_FE
| UARTSR1_PE
);
1467 if (termios
->c_iflag
& (IGNBRK
| BRKINT
| PARMRK
))
1468 sport
->port
.read_status_mask
|= UARTSR1_FE
;
1470 /* characters to ignore */
1471 sport
->port
.ignore_status_mask
= 0;
1472 if (termios
->c_iflag
& IGNPAR
)
1473 sport
->port
.ignore_status_mask
|= UARTSR1_PE
;
1474 if (termios
->c_iflag
& IGNBRK
) {
1475 sport
->port
.ignore_status_mask
|= UARTSR1_FE
;
1477 * if we're ignoring parity and break indicators,
1478 * ignore overruns too (for real raw support).
1480 if (termios
->c_iflag
& IGNPAR
)
1481 sport
->port
.ignore_status_mask
|= UARTSR1_OR
;
1484 /* update the per-port timeout */
1485 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1487 /* wait transmit engin complete */
1488 while (!(readb(sport
->port
.membase
+ UARTSR1
) & UARTSR1_TC
))
1491 /* disable transmit and receive */
1492 writeb(old_cr2
& ~(UARTCR2_TE
| UARTCR2_RE
),
1493 sport
->port
.membase
+ UARTCR2
);
1495 sbr
= sport
->port
.uartclk
/ (16 * baud
);
1496 brfa
= ((sport
->port
.uartclk
- (16 * sbr
* baud
)) * 2) / baud
;
1497 bdh
&= ~UARTBDH_SBR_MASK
;
1498 bdh
|= (sbr
>> 8) & 0x1F;
1499 cr4
&= ~UARTCR4_BRFA_MASK
;
1500 brfa
&= UARTCR4_BRFA_MASK
;
1501 writeb(cr4
| brfa
, sport
->port
.membase
+ UARTCR4
);
1502 writeb(bdh
, sport
->port
.membase
+ UARTBDH
);
1503 writeb(sbr
& 0xFF, sport
->port
.membase
+ UARTBDL
);
1504 writeb(cr3
, sport
->port
.membase
+ UARTCR3
);
1505 writeb(cr1
, sport
->port
.membase
+ UARTCR1
);
1506 writeb(modem
, sport
->port
.membase
+ UARTMODEM
);
1508 /* restore control register */
1509 writeb(old_cr2
, sport
->port
.membase
+ UARTCR2
);
1511 if (old
&& sport
->lpuart_dma_rx_use
) {
1512 if (!lpuart_start_rx_dma(sport
))
1513 rx_dma_timer_init(sport
);
1515 sport
->lpuart_dma_rx_use
= false;
1518 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1522 lpuart32_serial_setbrg(struct lpuart_port
*sport
, unsigned int baudrate
)
1524 u32 sbr
, osr
, baud_diff
, tmp_osr
, tmp_sbr
, tmp_diff
, tmp
;
1525 u32 clk
= sport
->port
.uartclk
;
1528 * The idea is to use the best OSR (over-sampling rate) possible.
1529 * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
1530 * Loop to find the best OSR value possible, one that generates minimum
1531 * baud_diff iterate through the rest of the supported values of OSR.
1533 * Calculation Formula:
1534 * Baud Rate = baud clock / ((OSR+1) × SBR)
1536 baud_diff
= baudrate
;
1540 for (tmp_osr
= 4; tmp_osr
<= 32; tmp_osr
++) {
1541 /* calculate the temporary sbr value */
1542 tmp_sbr
= (clk
/ (baudrate
* tmp_osr
));
1547 * calculate the baud rate difference based on the temporary
1548 * osr and sbr values
1550 tmp_diff
= clk
/ (tmp_osr
* tmp_sbr
) - baudrate
;
1552 /* select best values between sbr and sbr+1 */
1553 tmp
= clk
/ (tmp_osr
* (tmp_sbr
+ 1));
1554 if (tmp_diff
> (baudrate
- tmp
)) {
1555 tmp_diff
= baudrate
- tmp
;
1559 if (tmp_diff
<= baud_diff
) {
1560 baud_diff
= tmp_diff
;
1569 /* handle buadrate outside acceptable rate */
1570 if (baud_diff
> ((baudrate
/ 100) * 3))
1571 dev_warn(sport
->port
.dev
,
1572 "unacceptable baud rate difference of more than 3%%\n");
1574 tmp
= lpuart32_read(&sport
->port
, UARTBAUD
);
1576 if ((osr
> 3) && (osr
< 8))
1577 tmp
|= UARTBAUD_BOTHEDGE
;
1579 tmp
&= ~(UARTBAUD_OSR_MASK
<< UARTBAUD_OSR_SHIFT
);
1580 tmp
|= (((osr
-1) & UARTBAUD_OSR_MASK
) << UARTBAUD_OSR_SHIFT
);
1582 tmp
&= ~UARTBAUD_SBR_MASK
;
1583 tmp
|= sbr
& UARTBAUD_SBR_MASK
;
1585 tmp
&= ~(UARTBAUD_TDMAE
| UARTBAUD_RDMAE
);
1587 lpuart32_write(&sport
->port
, tmp
, UARTBAUD
);
1591 lpuart32_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
1592 struct ktermios
*old
)
1594 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1595 unsigned long flags
;
1596 unsigned long ctrl
, old_ctrl
, bd
, modem
;
1598 unsigned int old_csize
= old
? old
->c_cflag
& CSIZE
: CS8
;
1600 ctrl
= old_ctrl
= lpuart32_read(&sport
->port
, UARTCTRL
);
1601 bd
= lpuart32_read(&sport
->port
, UARTBAUD
);
1602 modem
= lpuart32_read(&sport
->port
, UARTMODIR
);
1604 * only support CS8 and CS7, and for CS7 must enable PE.
1611 while ((termios
->c_cflag
& CSIZE
) != CS8
&&
1612 (termios
->c_cflag
& CSIZE
) != CS7
) {
1613 termios
->c_cflag
&= ~CSIZE
;
1614 termios
->c_cflag
|= old_csize
;
1618 if ((termios
->c_cflag
& CSIZE
) == CS8
||
1619 (termios
->c_cflag
& CSIZE
) == CS7
)
1620 ctrl
= old_ctrl
& ~UARTCTRL_M
;
1622 if (termios
->c_cflag
& CMSPAR
) {
1623 if ((termios
->c_cflag
& CSIZE
) != CS8
) {
1624 termios
->c_cflag
&= ~CSIZE
;
1625 termios
->c_cflag
|= CS8
;
1630 if (termios
->c_cflag
& CRTSCTS
) {
1631 modem
|= (UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1633 termios
->c_cflag
&= ~CRTSCTS
;
1634 modem
&= ~(UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1637 if (termios
->c_cflag
& CSTOPB
)
1638 termios
->c_cflag
&= ~CSTOPB
;
1640 /* parity must be enabled when CS7 to match 8-bits format */
1641 if ((termios
->c_cflag
& CSIZE
) == CS7
)
1642 termios
->c_cflag
|= PARENB
;
1644 if ((termios
->c_cflag
& PARENB
)) {
1645 if (termios
->c_cflag
& CMSPAR
) {
1646 ctrl
&= ~UARTCTRL_PE
;
1650 if ((termios
->c_cflag
& CSIZE
) == CS8
)
1652 if (termios
->c_cflag
& PARODD
)
1653 ctrl
|= UARTCTRL_PT
;
1655 ctrl
&= ~UARTCTRL_PT
;
1659 /* ask the core to calculate the divisor */
1660 baud
= uart_get_baud_rate(port
, termios
, old
, 50, port
->uartclk
/ 16);
1662 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1664 sport
->port
.read_status_mask
= 0;
1665 if (termios
->c_iflag
& INPCK
)
1666 sport
->port
.read_status_mask
|= (UARTSTAT_FE
| UARTSTAT_PE
);
1667 if (termios
->c_iflag
& (IGNBRK
| BRKINT
| PARMRK
))
1668 sport
->port
.read_status_mask
|= UARTSTAT_FE
;
1670 /* characters to ignore */
1671 sport
->port
.ignore_status_mask
= 0;
1672 if (termios
->c_iflag
& IGNPAR
)
1673 sport
->port
.ignore_status_mask
|= UARTSTAT_PE
;
1674 if (termios
->c_iflag
& IGNBRK
) {
1675 sport
->port
.ignore_status_mask
|= UARTSTAT_FE
;
1677 * if we're ignoring parity and break indicators,
1678 * ignore overruns too (for real raw support).
1680 if (termios
->c_iflag
& IGNPAR
)
1681 sport
->port
.ignore_status_mask
|= UARTSTAT_OR
;
1684 /* update the per-port timeout */
1685 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1687 /* wait transmit engin complete */
1688 while (!(lpuart32_read(&sport
->port
, UARTSTAT
) & UARTSTAT_TC
))
1691 /* disable transmit and receive */
1692 lpuart32_write(&sport
->port
, old_ctrl
& ~(UARTCTRL_TE
| UARTCTRL_RE
),
1695 lpuart32_serial_setbrg(sport
, baud
);
1696 lpuart32_write(&sport
->port
, modem
, UARTMODIR
);
1697 lpuart32_write(&sport
->port
, ctrl
, UARTCTRL
);
1698 /* restore control register */
1700 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1703 static const char *lpuart_type(struct uart_port
*port
)
1705 return "FSL_LPUART";
1708 static void lpuart_release_port(struct uart_port
*port
)
1713 static int lpuart_request_port(struct uart_port
*port
)
1718 /* configure/autoconfigure the port */
1719 static void lpuart_config_port(struct uart_port
*port
, int flags
)
1721 if (flags
& UART_CONFIG_TYPE
)
1722 port
->type
= PORT_LPUART
;
1725 static int lpuart_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
1729 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_LPUART
)
1731 if (port
->irq
!= ser
->irq
)
1733 if (ser
->io_type
!= UPIO_MEM
)
1735 if (port
->uartclk
/ 16 != ser
->baud_base
)
1737 if (port
->iobase
!= ser
->port
)
1744 static const struct uart_ops lpuart_pops
= {
1745 .tx_empty
= lpuart_tx_empty
,
1746 .set_mctrl
= lpuart_set_mctrl
,
1747 .get_mctrl
= lpuart_get_mctrl
,
1748 .stop_tx
= lpuart_stop_tx
,
1749 .start_tx
= lpuart_start_tx
,
1750 .stop_rx
= lpuart_stop_rx
,
1751 .break_ctl
= lpuart_break_ctl
,
1752 .startup
= lpuart_startup
,
1753 .shutdown
= lpuart_shutdown
,
1754 .set_termios
= lpuart_set_termios
,
1755 .type
= lpuart_type
,
1756 .request_port
= lpuart_request_port
,
1757 .release_port
= lpuart_release_port
,
1758 .config_port
= lpuart_config_port
,
1759 .verify_port
= lpuart_verify_port
,
1760 .flush_buffer
= lpuart_flush_buffer
,
1761 #if defined(CONFIG_CONSOLE_POLL)
1762 .poll_init
= lpuart_poll_init
,
1763 .poll_get_char
= lpuart_poll_get_char
,
1764 .poll_put_char
= lpuart_poll_put_char
,
1768 static const struct uart_ops lpuart32_pops
= {
1769 .tx_empty
= lpuart32_tx_empty
,
1770 .set_mctrl
= lpuart32_set_mctrl
,
1771 .get_mctrl
= lpuart32_get_mctrl
,
1772 .stop_tx
= lpuart32_stop_tx
,
1773 .start_tx
= lpuart32_start_tx
,
1774 .stop_rx
= lpuart32_stop_rx
,
1775 .break_ctl
= lpuart32_break_ctl
,
1776 .startup
= lpuart32_startup
,
1777 .shutdown
= lpuart32_shutdown
,
1778 .set_termios
= lpuart32_set_termios
,
1779 .type
= lpuart_type
,
1780 .request_port
= lpuart_request_port
,
1781 .release_port
= lpuart_release_port
,
1782 .config_port
= lpuart_config_port
,
1783 .verify_port
= lpuart_verify_port
,
1784 .flush_buffer
= lpuart_flush_buffer
,
1787 static struct lpuart_port
*lpuart_ports
[UART_NR
];
1789 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1790 static void lpuart_console_putchar(struct uart_port
*port
, int ch
)
1792 while (!(readb(port
->membase
+ UARTSR1
) & UARTSR1_TDRE
))
1795 writeb(ch
, port
->membase
+ UARTDR
);
1798 static void lpuart32_console_putchar(struct uart_port
*port
, int ch
)
1800 while (!(lpuart32_read(port
, UARTSTAT
) & UARTSTAT_TDRE
))
1803 lpuart32_write(port
, ch
, UARTDATA
);
1807 lpuart_console_write(struct console
*co
, const char *s
, unsigned int count
)
1809 struct lpuart_port
*sport
= lpuart_ports
[co
->index
];
1810 unsigned char old_cr2
, cr2
;
1811 unsigned long flags
;
1814 if (sport
->port
.sysrq
|| oops_in_progress
)
1815 locked
= spin_trylock_irqsave(&sport
->port
.lock
, flags
);
1817 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1819 /* first save CR2 and then disable interrupts */
1820 cr2
= old_cr2
= readb(sport
->port
.membase
+ UARTCR2
);
1821 cr2
|= (UARTCR2_TE
| UARTCR2_RE
);
1822 cr2
&= ~(UARTCR2_TIE
| UARTCR2_TCIE
| UARTCR2_RIE
);
1823 writeb(cr2
, sport
->port
.membase
+ UARTCR2
);
1825 uart_console_write(&sport
->port
, s
, count
, lpuart_console_putchar
);
1827 /* wait for transmitter finish complete and restore CR2 */
1828 while (!(readb(sport
->port
.membase
+ UARTSR1
) & UARTSR1_TC
))
1831 writeb(old_cr2
, sport
->port
.membase
+ UARTCR2
);
1834 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1838 lpuart32_console_write(struct console
*co
, const char *s
, unsigned int count
)
1840 struct lpuart_port
*sport
= lpuart_ports
[co
->index
];
1841 unsigned long old_cr
, cr
;
1842 unsigned long flags
;
1845 if (sport
->port
.sysrq
|| oops_in_progress
)
1846 locked
= spin_trylock_irqsave(&sport
->port
.lock
, flags
);
1848 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1850 /* first save CR2 and then disable interrupts */
1851 cr
= old_cr
= lpuart32_read(&sport
->port
, UARTCTRL
);
1852 cr
|= (UARTCTRL_TE
| UARTCTRL_RE
);
1853 cr
&= ~(UARTCTRL_TIE
| UARTCTRL_TCIE
| UARTCTRL_RIE
);
1854 lpuart32_write(&sport
->port
, cr
, UARTCTRL
);
1856 uart_console_write(&sport
->port
, s
, count
, lpuart32_console_putchar
);
1858 /* wait for transmitter finish complete and restore CR2 */
1859 while (!(lpuart32_read(&sport
->port
, UARTSTAT
) & UARTSTAT_TC
))
1862 lpuart32_write(&sport
->port
, old_cr
, UARTCTRL
);
1865 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1869 * if the port was already initialised (eg, by a boot loader),
1870 * try to determine the current setup.
1873 lpuart_console_get_options(struct lpuart_port
*sport
, int *baud
,
1874 int *parity
, int *bits
)
1876 unsigned char cr
, bdh
, bdl
, brfa
;
1877 unsigned int sbr
, uartclk
, baud_raw
;
1879 cr
= readb(sport
->port
.membase
+ UARTCR2
);
1880 cr
&= UARTCR2_TE
| UARTCR2_RE
;
1884 /* ok, the port was enabled */
1886 cr
= readb(sport
->port
.membase
+ UARTCR1
);
1889 if (cr
& UARTCR1_PE
) {
1890 if (cr
& UARTCR1_PT
)
1901 bdh
= readb(sport
->port
.membase
+ UARTBDH
);
1902 bdh
&= UARTBDH_SBR_MASK
;
1903 bdl
= readb(sport
->port
.membase
+ UARTBDL
);
1907 brfa
= readb(sport
->port
.membase
+ UARTCR4
);
1908 brfa
&= UARTCR4_BRFA_MASK
;
1910 uartclk
= clk_get_rate(sport
->clk
);
1912 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1914 baud_raw
= uartclk
/ (16 * (sbr
+ brfa
/ 32));
1916 if (*baud
!= baud_raw
)
1917 printk(KERN_INFO
"Serial: Console lpuart rounded baud rate"
1918 "from %d to %d\n", baud_raw
, *baud
);
1922 lpuart32_console_get_options(struct lpuart_port
*sport
, int *baud
,
1923 int *parity
, int *bits
)
1925 unsigned long cr
, bd
;
1926 unsigned int sbr
, uartclk
, baud_raw
;
1928 cr
= lpuart32_read(&sport
->port
, UARTCTRL
);
1929 cr
&= UARTCTRL_TE
| UARTCTRL_RE
;
1933 /* ok, the port was enabled */
1935 cr
= lpuart32_read(&sport
->port
, UARTCTRL
);
1938 if (cr
& UARTCTRL_PE
) {
1939 if (cr
& UARTCTRL_PT
)
1945 if (cr
& UARTCTRL_M
)
1950 bd
= lpuart32_read(&sport
->port
, UARTBAUD
);
1951 bd
&= UARTBAUD_SBR_MASK
;
1953 uartclk
= clk_get_rate(sport
->clk
);
1955 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1957 baud_raw
= uartclk
/ (16 * sbr
);
1959 if (*baud
!= baud_raw
)
1960 printk(KERN_INFO
"Serial: Console lpuart rounded baud rate"
1961 "from %d to %d\n", baud_raw
, *baud
);
1964 static int __init
lpuart_console_setup(struct console
*co
, char *options
)
1966 struct lpuart_port
*sport
;
1973 * check whether an invalid uart number has been specified, and
1974 * if so, search for the first available port that does have
1977 if (co
->index
== -1 || co
->index
>= ARRAY_SIZE(lpuart_ports
))
1980 sport
= lpuart_ports
[co
->index
];
1985 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1987 if (lpuart_is_32(sport
))
1988 lpuart32_console_get_options(sport
, &baud
, &parity
, &bits
);
1990 lpuart_console_get_options(sport
, &baud
, &parity
, &bits
);
1992 if (lpuart_is_32(sport
))
1993 lpuart32_setup_watermark(sport
);
1995 lpuart_setup_watermark(sport
);
1997 return uart_set_options(&sport
->port
, co
, baud
, parity
, bits
, flow
);
2000 static struct uart_driver lpuart_reg
;
2001 static struct console lpuart_console
= {
2003 .write
= lpuart_console_write
,
2004 .device
= uart_console_device
,
2005 .setup
= lpuart_console_setup
,
2006 .flags
= CON_PRINTBUFFER
,
2008 .data
= &lpuart_reg
,
2011 static struct console lpuart32_console
= {
2013 .write
= lpuart32_console_write
,
2014 .device
= uart_console_device
,
2015 .setup
= lpuart_console_setup
,
2016 .flags
= CON_PRINTBUFFER
,
2018 .data
= &lpuart_reg
,
2021 static void lpuart_early_write(struct console
*con
, const char *s
, unsigned n
)
2023 struct earlycon_device
*dev
= con
->data
;
2025 uart_console_write(&dev
->port
, s
, n
, lpuart_console_putchar
);
2028 static void lpuart32_early_write(struct console
*con
, const char *s
, unsigned n
)
2030 struct earlycon_device
*dev
= con
->data
;
2032 uart_console_write(&dev
->port
, s
, n
, lpuart32_console_putchar
);
2035 static int __init
lpuart_early_console_setup(struct earlycon_device
*device
,
2038 if (!device
->port
.membase
)
2041 device
->con
->write
= lpuart_early_write
;
2045 static int __init
lpuart32_early_console_setup(struct earlycon_device
*device
,
2048 if (!device
->port
.membase
)
2051 device
->port
.iotype
= UPIO_MEM32BE
;
2052 device
->con
->write
= lpuart32_early_write
;
2056 static int __init
lpuart32_imx_early_console_setup(struct earlycon_device
*device
,
2059 if (!device
->port
.membase
)
2062 device
->port
.iotype
= UPIO_MEM32
;
2063 device
->port
.membase
+= IMX_REG_OFF
;
2064 device
->con
->write
= lpuart32_early_write
;
2068 OF_EARLYCON_DECLARE(lpuart
, "fsl,vf610-lpuart", lpuart_early_console_setup
);
2069 OF_EARLYCON_DECLARE(lpuart32
, "fsl,ls1021a-lpuart", lpuart32_early_console_setup
);
2070 OF_EARLYCON_DECLARE(lpuart32
, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup
);
2071 EARLYCON_DECLARE(lpuart
, lpuart_early_console_setup
);
2072 EARLYCON_DECLARE(lpuart32
, lpuart32_early_console_setup
);
2074 #define LPUART_CONSOLE (&lpuart_console)
2075 #define LPUART32_CONSOLE (&lpuart32_console)
2077 #define LPUART_CONSOLE NULL
2078 #define LPUART32_CONSOLE NULL
2081 static struct uart_driver lpuart_reg
= {
2082 .owner
= THIS_MODULE
,
2083 .driver_name
= DRIVER_NAME
,
2084 .dev_name
= DEV_NAME
,
2085 .nr
= ARRAY_SIZE(lpuart_ports
),
2086 .cons
= LPUART_CONSOLE
,
2089 static int lpuart_probe(struct platform_device
*pdev
)
2091 const struct of_device_id
*of_id
= of_match_device(lpuart_dt_ids
,
2093 const struct lpuart_soc_data
*sdata
= of_id
->data
;
2094 struct device_node
*np
= pdev
->dev
.of_node
;
2095 struct lpuart_port
*sport
;
2096 struct resource
*res
;
2099 sport
= devm_kzalloc(&pdev
->dev
, sizeof(*sport
), GFP_KERNEL
);
2103 pdev
->dev
.coherent_dma_mask
= 0;
2105 ret
= of_alias_get_id(np
, "serial");
2107 dev_err(&pdev
->dev
, "failed to get alias id, errno %d\n", ret
);
2110 sport
->port
.line
= ret
;
2111 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2112 sport
->port
.membase
= devm_ioremap_resource(&pdev
->dev
, res
);
2113 if (IS_ERR(sport
->port
.membase
))
2114 return PTR_ERR(sport
->port
.membase
);
2116 sport
->port
.membase
+= sdata
->reg_off
;
2117 sport
->port
.mapbase
= res
->start
;
2118 sport
->port
.dev
= &pdev
->dev
;
2119 sport
->port
.type
= PORT_LPUART
;
2120 ret
= platform_get_irq(pdev
, 0);
2122 dev_err(&pdev
->dev
, "cannot obtain irq\n");
2125 sport
->port
.irq
= ret
;
2126 sport
->port
.iotype
= sdata
->iotype
;
2127 if (lpuart_is_32(sport
))
2128 sport
->port
.ops
= &lpuart32_pops
;
2130 sport
->port
.ops
= &lpuart_pops
;
2131 sport
->port
.flags
= UPF_BOOT_AUTOCONF
;
2133 sport
->port
.rs485_config
= lpuart_config_rs485
;
2135 sport
->clk
= devm_clk_get(&pdev
->dev
, "ipg");
2136 if (IS_ERR(sport
->clk
)) {
2137 ret
= PTR_ERR(sport
->clk
);
2138 dev_err(&pdev
->dev
, "failed to get uart clk: %d\n", ret
);
2142 ret
= clk_prepare_enable(sport
->clk
);
2144 dev_err(&pdev
->dev
, "failed to enable uart clk: %d\n", ret
);
2148 sport
->port
.uartclk
= clk_get_rate(sport
->clk
);
2150 lpuart_ports
[sport
->port
.line
] = sport
;
2152 platform_set_drvdata(pdev
, &sport
->port
);
2154 if (lpuart_is_32(sport
))
2155 lpuart_reg
.cons
= LPUART32_CONSOLE
;
2157 lpuart_reg
.cons
= LPUART_CONSOLE
;
2159 ret
= uart_add_one_port(&lpuart_reg
, &sport
->port
);
2161 clk_disable_unprepare(sport
->clk
);
2165 sport
->dma_tx_chan
= dma_request_slave_channel(sport
->port
.dev
, "tx");
2166 if (!sport
->dma_tx_chan
)
2167 dev_info(sport
->port
.dev
, "DMA tx channel request failed, "
2168 "operating without tx DMA\n");
2170 sport
->dma_rx_chan
= dma_request_slave_channel(sport
->port
.dev
, "rx");
2171 if (!sport
->dma_rx_chan
)
2172 dev_info(sport
->port
.dev
, "DMA rx channel request failed, "
2173 "operating without rx DMA\n");
2175 if (of_property_read_bool(np
, "linux,rs485-enabled-at-boot-time")) {
2176 sport
->port
.rs485
.flags
|= SER_RS485_ENABLED
;
2177 sport
->port
.rs485
.flags
|= SER_RS485_RTS_ON_SEND
;
2178 writeb(UARTMODEM_TXRTSE
, sport
->port
.membase
+ UARTMODEM
);
2184 static int lpuart_remove(struct platform_device
*pdev
)
2186 struct lpuart_port
*sport
= platform_get_drvdata(pdev
);
2188 uart_remove_one_port(&lpuart_reg
, &sport
->port
);
2190 clk_disable_unprepare(sport
->clk
);
2192 if (sport
->dma_tx_chan
)
2193 dma_release_channel(sport
->dma_tx_chan
);
2195 if (sport
->dma_rx_chan
)
2196 dma_release_channel(sport
->dma_rx_chan
);
2201 #ifdef CONFIG_PM_SLEEP
2202 static int lpuart_suspend(struct device
*dev
)
2204 struct lpuart_port
*sport
= dev_get_drvdata(dev
);
2207 if (lpuart_is_32(sport
)) {
2208 /* disable Rx/Tx and interrupts */
2209 temp
= lpuart32_read(&sport
->port
, UARTCTRL
);
2210 temp
&= ~(UARTCTRL_TE
| UARTCTRL_TIE
| UARTCTRL_TCIE
);
2211 lpuart32_write(&sport
->port
, temp
, UARTCTRL
);
2213 /* disable Rx/Tx and interrupts */
2214 temp
= readb(sport
->port
.membase
+ UARTCR2
);
2215 temp
&= ~(UARTCR2_TE
| UARTCR2_TIE
| UARTCR2_TCIE
);
2216 writeb(temp
, sport
->port
.membase
+ UARTCR2
);
2219 uart_suspend_port(&lpuart_reg
, &sport
->port
);
2221 if (sport
->lpuart_dma_rx_use
) {
2223 * EDMA driver during suspend will forcefully release any
2224 * non-idle DMA channels. If port wakeup is enabled or if port
2225 * is console port or 'no_console_suspend' is set the Rx DMA
2226 * cannot resume as as expected, hence gracefully release the
2227 * Rx DMA path before suspend and start Rx DMA path on resume.
2229 if (sport
->port
.irq_wake
) {
2230 del_timer_sync(&sport
->lpuart_timer
);
2231 lpuart_dma_rx_free(&sport
->port
);
2234 /* Disable Rx DMA to use UART port as wakeup source */
2235 writeb(readb(sport
->port
.membase
+ UARTCR5
) & ~UARTCR5_RDMAS
,
2236 sport
->port
.membase
+ UARTCR5
);
2239 if (sport
->lpuart_dma_tx_use
) {
2240 sport
->dma_tx_in_progress
= false;
2241 dmaengine_terminate_all(sport
->dma_tx_chan
);
2244 if (sport
->port
.suspended
&& !sport
->port
.irq_wake
)
2245 clk_disable_unprepare(sport
->clk
);
2250 static int lpuart_resume(struct device
*dev
)
2252 struct lpuart_port
*sport
= dev_get_drvdata(dev
);
2255 if (sport
->port
.suspended
&& !sport
->port
.irq_wake
)
2256 clk_prepare_enable(sport
->clk
);
2258 if (lpuart_is_32(sport
)) {
2259 lpuart32_setup_watermark(sport
);
2260 temp
= lpuart32_read(&sport
->port
, UARTCTRL
);
2261 temp
|= (UARTCTRL_RIE
| UARTCTRL_TIE
| UARTCTRL_RE
|
2262 UARTCTRL_TE
| UARTCTRL_ILIE
);
2263 lpuart32_write(&sport
->port
, temp
, UARTCTRL
);
2265 lpuart_setup_watermark(sport
);
2266 temp
= readb(sport
->port
.membase
+ UARTCR2
);
2267 temp
|= (UARTCR2_RIE
| UARTCR2_TIE
| UARTCR2_RE
| UARTCR2_TE
);
2268 writeb(temp
, sport
->port
.membase
+ UARTCR2
);
2271 if (sport
->lpuart_dma_rx_use
) {
2272 if (sport
->port
.irq_wake
) {
2273 if (!lpuart_start_rx_dma(sport
))
2274 rx_dma_timer_init(sport
);
2276 sport
->lpuart_dma_rx_use
= false;
2280 if (sport
->dma_tx_chan
&& !lpuart_dma_tx_request(&sport
->port
)) {
2281 init_waitqueue_head(&sport
->dma_wait
);
2282 sport
->lpuart_dma_tx_use
= true;
2283 writeb(readb(sport
->port
.membase
+ UARTCR5
) |
2284 UARTCR5_TDMAS
, sport
->port
.membase
+ UARTCR5
);
2286 sport
->lpuart_dma_tx_use
= false;
2289 uart_resume_port(&lpuart_reg
, &sport
->port
);
2295 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops
, lpuart_suspend
, lpuart_resume
);
2297 static struct platform_driver lpuart_driver
= {
2298 .probe
= lpuart_probe
,
2299 .remove
= lpuart_remove
,
2301 .name
= "fsl-lpuart",
2302 .of_match_table
= lpuart_dt_ids
,
2303 .pm
= &lpuart_pm_ops
,
2307 static int __init
lpuart_serial_init(void)
2309 int ret
= uart_register_driver(&lpuart_reg
);
2314 ret
= platform_driver_register(&lpuart_driver
);
2316 uart_unregister_driver(&lpuart_reg
);
2321 static void __exit
lpuart_serial_exit(void)
2323 platform_driver_unregister(&lpuart_driver
);
2324 uart_unregister_driver(&lpuart_reg
);
2327 module_init(lpuart_serial_init
);
2328 module_exit(lpuart_serial_exit
);
2330 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2331 MODULE_LICENSE("GPL v2");