2 * Freescale lpuart serial port driver
4 * Copyright 2012-2014 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
16 #include <linux/clk.h>
17 #include <linux/console.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/dmaengine.h>
20 #include <linux/dmapool.h>
22 #include <linux/irq.h>
23 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/of_dma.h>
27 #include <linux/serial_core.h>
28 #include <linux/slab.h>
29 #include <linux/tty_flip.h>
31 /* All registers are 8-bit width */
41 #define UARTMODEM 0x0d
42 #define UARTPFIFO 0x10
43 #define UARTCFIFO 0x11
44 #define UARTSFIFO 0x12
45 #define UARTTWFIFO 0x13
46 #define UARTTCFIFO 0x14
47 #define UARTRWFIFO 0x15
49 #define UARTBDH_LBKDIE 0x80
50 #define UARTBDH_RXEDGIE 0x40
51 #define UARTBDH_SBR_MASK 0x1f
53 #define UARTCR1_LOOPS 0x80
54 #define UARTCR1_RSRC 0x20
55 #define UARTCR1_M 0x10
56 #define UARTCR1_WAKE 0x08
57 #define UARTCR1_ILT 0x04
58 #define UARTCR1_PE 0x02
59 #define UARTCR1_PT 0x01
61 #define UARTCR2_TIE 0x80
62 #define UARTCR2_TCIE 0x40
63 #define UARTCR2_RIE 0x20
64 #define UARTCR2_ILIE 0x10
65 #define UARTCR2_TE 0x08
66 #define UARTCR2_RE 0x04
67 #define UARTCR2_RWU 0x02
68 #define UARTCR2_SBK 0x01
70 #define UARTSR1_TDRE 0x80
71 #define UARTSR1_TC 0x40
72 #define UARTSR1_RDRF 0x20
73 #define UARTSR1_IDLE 0x10
74 #define UARTSR1_OR 0x08
75 #define UARTSR1_NF 0x04
76 #define UARTSR1_FE 0x02
77 #define UARTSR1_PE 0x01
79 #define UARTCR3_R8 0x80
80 #define UARTCR3_T8 0x40
81 #define UARTCR3_TXDIR 0x20
82 #define UARTCR3_TXINV 0x10
83 #define UARTCR3_ORIE 0x08
84 #define UARTCR3_NEIE 0x04
85 #define UARTCR3_FEIE 0x02
86 #define UARTCR3_PEIE 0x01
88 #define UARTCR4_MAEN1 0x80
89 #define UARTCR4_MAEN2 0x40
90 #define UARTCR4_M10 0x20
91 #define UARTCR4_BRFA_MASK 0x1f
92 #define UARTCR4_BRFA_OFF 0
94 #define UARTCR5_TDMAS 0x80
95 #define UARTCR5_RDMAS 0x20
97 #define UARTMODEM_RXRTSE 0x08
98 #define UARTMODEM_TXRTSPOL 0x04
99 #define UARTMODEM_TXRTSE 0x02
100 #define UARTMODEM_TXCTSE 0x01
102 #define UARTPFIFO_TXFE 0x80
103 #define UARTPFIFO_FIFOSIZE_MASK 0x7
104 #define UARTPFIFO_TXSIZE_OFF 4
105 #define UARTPFIFO_RXFE 0x08
106 #define UARTPFIFO_RXSIZE_OFF 0
108 #define UARTCFIFO_TXFLUSH 0x80
109 #define UARTCFIFO_RXFLUSH 0x40
110 #define UARTCFIFO_RXOFE 0x04
111 #define UARTCFIFO_TXOFE 0x02
112 #define UARTCFIFO_RXUFE 0x01
114 #define UARTSFIFO_TXEMPT 0x80
115 #define UARTSFIFO_RXEMPT 0x40
116 #define UARTSFIFO_RXOF 0x04
117 #define UARTSFIFO_TXOF 0x02
118 #define UARTSFIFO_RXUF 0x01
120 /* 32-bit register defination */
121 #define UARTBAUD 0x00
122 #define UARTSTAT 0x04
123 #define UARTCTRL 0x08
124 #define UARTDATA 0x0C
125 #define UARTMATCH 0x10
126 #define UARTMODIR 0x14
127 #define UARTFIFO 0x18
128 #define UARTWATER 0x1c
130 #define UARTBAUD_MAEN1 0x80000000
131 #define UARTBAUD_MAEN2 0x40000000
132 #define UARTBAUD_M10 0x20000000
133 #define UARTBAUD_TDMAE 0x00800000
134 #define UARTBAUD_RDMAE 0x00200000
135 #define UARTBAUD_MATCFG 0x00400000
136 #define UARTBAUD_BOTHEDGE 0x00020000
137 #define UARTBAUD_RESYNCDIS 0x00010000
138 #define UARTBAUD_LBKDIE 0x00008000
139 #define UARTBAUD_RXEDGIE 0x00004000
140 #define UARTBAUD_SBNS 0x00002000
141 #define UARTBAUD_SBR 0x00000000
142 #define UARTBAUD_SBR_MASK 0x1fff
144 #define UARTSTAT_LBKDIF 0x80000000
145 #define UARTSTAT_RXEDGIF 0x40000000
146 #define UARTSTAT_MSBF 0x20000000
147 #define UARTSTAT_RXINV 0x10000000
148 #define UARTSTAT_RWUID 0x08000000
149 #define UARTSTAT_BRK13 0x04000000
150 #define UARTSTAT_LBKDE 0x02000000
151 #define UARTSTAT_RAF 0x01000000
152 #define UARTSTAT_TDRE 0x00800000
153 #define UARTSTAT_TC 0x00400000
154 #define UARTSTAT_RDRF 0x00200000
155 #define UARTSTAT_IDLE 0x00100000
156 #define UARTSTAT_OR 0x00080000
157 #define UARTSTAT_NF 0x00040000
158 #define UARTSTAT_FE 0x00020000
159 #define UARTSTAT_PE 0x00010000
160 #define UARTSTAT_MA1F 0x00008000
161 #define UARTSTAT_M21F 0x00004000
163 #define UARTCTRL_R8T9 0x80000000
164 #define UARTCTRL_R9T8 0x40000000
165 #define UARTCTRL_TXDIR 0x20000000
166 #define UARTCTRL_TXINV 0x10000000
167 #define UARTCTRL_ORIE 0x08000000
168 #define UARTCTRL_NEIE 0x04000000
169 #define UARTCTRL_FEIE 0x02000000
170 #define UARTCTRL_PEIE 0x01000000
171 #define UARTCTRL_TIE 0x00800000
172 #define UARTCTRL_TCIE 0x00400000
173 #define UARTCTRL_RIE 0x00200000
174 #define UARTCTRL_ILIE 0x00100000
175 #define UARTCTRL_TE 0x00080000
176 #define UARTCTRL_RE 0x00040000
177 #define UARTCTRL_RWU 0x00020000
178 #define UARTCTRL_SBK 0x00010000
179 #define UARTCTRL_MA1IE 0x00008000
180 #define UARTCTRL_MA2IE 0x00004000
181 #define UARTCTRL_IDLECFG 0x00000100
182 #define UARTCTRL_LOOPS 0x00000080
183 #define UARTCTRL_DOZEEN 0x00000040
184 #define UARTCTRL_RSRC 0x00000020
185 #define UARTCTRL_M 0x00000010
186 #define UARTCTRL_WAKE 0x00000008
187 #define UARTCTRL_ILT 0x00000004
188 #define UARTCTRL_PE 0x00000002
189 #define UARTCTRL_PT 0x00000001
191 #define UARTDATA_NOISY 0x00008000
192 #define UARTDATA_PARITYE 0x00004000
193 #define UARTDATA_FRETSC 0x00002000
194 #define UARTDATA_RXEMPT 0x00001000
195 #define UARTDATA_IDLINE 0x00000800
196 #define UARTDATA_MASK 0x3ff
198 #define UARTMODIR_IREN 0x00020000
199 #define UARTMODIR_TXCTSSRC 0x00000020
200 #define UARTMODIR_TXCTSC 0x00000010
201 #define UARTMODIR_RXRTSE 0x00000008
202 #define UARTMODIR_TXRTSPOL 0x00000004
203 #define UARTMODIR_TXRTSE 0x00000002
204 #define UARTMODIR_TXCTSE 0x00000001
206 #define UARTFIFO_TXEMPT 0x00800000
207 #define UARTFIFO_RXEMPT 0x00400000
208 #define UARTFIFO_TXOF 0x00020000
209 #define UARTFIFO_RXUF 0x00010000
210 #define UARTFIFO_TXFLUSH 0x00008000
211 #define UARTFIFO_RXFLUSH 0x00004000
212 #define UARTFIFO_TXOFE 0x00000200
213 #define UARTFIFO_RXUFE 0x00000100
214 #define UARTFIFO_TXFE 0x00000080
215 #define UARTFIFO_FIFOSIZE_MASK 0x7
216 #define UARTFIFO_TXSIZE_OFF 4
217 #define UARTFIFO_RXFE 0x00000008
218 #define UARTFIFO_RXSIZE_OFF 0
220 #define UARTWATER_COUNT_MASK 0xff
221 #define UARTWATER_TXCNT_OFF 8
222 #define UARTWATER_RXCNT_OFF 24
223 #define UARTWATER_WATER_MASK 0xff
224 #define UARTWATER_TXWATER_OFF 0
225 #define UARTWATER_RXWATER_OFF 16
227 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
228 #define DMA_RX_TIMEOUT (10)
230 #define DRIVER_NAME "fsl-lpuart"
231 #define DEV_NAME "ttyLP"
235 struct uart_port port
;
237 unsigned int txfifo_size
;
238 unsigned int rxfifo_size
;
241 bool lpuart_dma_tx_use
;
242 bool lpuart_dma_rx_use
;
243 struct dma_chan
*dma_tx_chan
;
244 struct dma_chan
*dma_rx_chan
;
245 struct dma_async_tx_descriptor
*dma_tx_desc
;
246 struct dma_async_tx_descriptor
*dma_rx_desc
;
247 dma_cookie_t dma_tx_cookie
;
248 dma_cookie_t dma_rx_cookie
;
249 unsigned int dma_tx_bytes
;
250 unsigned int dma_rx_bytes
;
251 bool dma_tx_in_progress
;
252 unsigned int dma_rx_timeout
;
253 struct timer_list lpuart_timer
;
254 struct scatterlist rx_sgl
, tx_sgl
[2];
255 struct circ_buf rx_ring
;
256 int rx_dma_rng_buf_len
;
257 unsigned int dma_tx_nents
;
258 wait_queue_head_t dma_wait
;
261 static const struct of_device_id lpuart_dt_ids
[] = {
263 .compatible
= "fsl,vf610-lpuart",
266 .compatible
= "fsl,ls1021a-lpuart",
270 MODULE_DEVICE_TABLE(of
, lpuart_dt_ids
);
272 /* Forward declare this for the dma callbacks*/
273 static void lpuart_dma_tx_complete(void *arg
);
275 static u32
lpuart32_read(void __iomem
*addr
)
277 return ioread32be(addr
);
280 static void lpuart32_write(u32 val
, void __iomem
*addr
)
282 iowrite32be(val
, addr
);
285 static void lpuart_stop_tx(struct uart_port
*port
)
289 temp
= readb(port
->membase
+ UARTCR2
);
290 temp
&= ~(UARTCR2_TIE
| UARTCR2_TCIE
);
291 writeb(temp
, port
->membase
+ UARTCR2
);
294 static void lpuart32_stop_tx(struct uart_port
*port
)
298 temp
= lpuart32_read(port
->membase
+ UARTCTRL
);
299 temp
&= ~(UARTCTRL_TIE
| UARTCTRL_TCIE
);
300 lpuart32_write(temp
, port
->membase
+ UARTCTRL
);
303 static void lpuart_stop_rx(struct uart_port
*port
)
307 temp
= readb(port
->membase
+ UARTCR2
);
308 writeb(temp
& ~UARTCR2_RE
, port
->membase
+ UARTCR2
);
311 static void lpuart32_stop_rx(struct uart_port
*port
)
315 temp
= lpuart32_read(port
->membase
+ UARTCTRL
);
316 lpuart32_write(temp
& ~UARTCTRL_RE
, port
->membase
+ UARTCTRL
);
319 static void lpuart_dma_tx(struct lpuart_port
*sport
)
321 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
322 struct scatterlist
*sgl
= sport
->tx_sgl
;
323 struct device
*dev
= sport
->port
.dev
;
326 if (sport
->dma_tx_in_progress
)
329 sport
->dma_tx_bytes
= uart_circ_chars_pending(xmit
);
331 if (xmit
->tail
< xmit
->head
) {
332 sport
->dma_tx_nents
= 1;
333 sg_init_one(sgl
, xmit
->buf
+ xmit
->tail
, sport
->dma_tx_bytes
);
335 sport
->dma_tx_nents
= 2;
336 sg_init_table(sgl
, 2);
337 sg_set_buf(sgl
, xmit
->buf
+ xmit
->tail
,
338 UART_XMIT_SIZE
- xmit
->tail
);
339 sg_set_buf(sgl
+ 1, xmit
->buf
, xmit
->head
);
342 ret
= dma_map_sg(dev
, sgl
, sport
->dma_tx_nents
, DMA_TO_DEVICE
);
344 dev_err(dev
, "DMA mapping error for TX.\n");
348 sport
->dma_tx_desc
= dmaengine_prep_slave_sg(sport
->dma_tx_chan
, sgl
,
350 DMA_MEM_TO_DEV
, DMA_PREP_INTERRUPT
);
351 if (!sport
->dma_tx_desc
) {
352 dma_unmap_sg(dev
, sgl
, sport
->dma_tx_nents
, DMA_TO_DEVICE
);
353 dev_err(dev
, "Cannot prepare TX slave DMA!\n");
357 sport
->dma_tx_desc
->callback
= lpuart_dma_tx_complete
;
358 sport
->dma_tx_desc
->callback_param
= sport
;
359 sport
->dma_tx_in_progress
= true;
360 sport
->dma_tx_cookie
= dmaengine_submit(sport
->dma_tx_desc
);
361 dma_async_issue_pending(sport
->dma_tx_chan
);
365 static void lpuart_dma_tx_complete(void *arg
)
367 struct lpuart_port
*sport
= arg
;
368 struct scatterlist
*sgl
= &sport
->tx_sgl
[0];
369 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
372 spin_lock_irqsave(&sport
->port
.lock
, flags
);
374 dma_unmap_sg(sport
->port
.dev
, sgl
, sport
->dma_tx_nents
, DMA_TO_DEVICE
);
376 xmit
->tail
= (xmit
->tail
+ sport
->dma_tx_bytes
) & (UART_XMIT_SIZE
- 1);
378 sport
->port
.icount
.tx
+= sport
->dma_tx_bytes
;
379 sport
->dma_tx_in_progress
= false;
380 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
382 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
383 uart_write_wakeup(&sport
->port
);
385 if (waitqueue_active(&sport
->dma_wait
)) {
386 wake_up(&sport
->dma_wait
);
390 spin_lock_irqsave(&sport
->port
.lock
, flags
);
392 if (!uart_circ_empty(xmit
) && !uart_tx_stopped(&sport
->port
))
393 lpuart_dma_tx(sport
);
395 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
398 static int lpuart_dma_tx_request(struct uart_port
*port
)
400 struct lpuart_port
*sport
= container_of(port
,
401 struct lpuart_port
, port
);
402 struct dma_slave_config dma_tx_sconfig
= {};
405 dma_tx_sconfig
.dst_addr
= sport
->port
.mapbase
+ UARTDR
;
406 dma_tx_sconfig
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
407 dma_tx_sconfig
.dst_maxburst
= 1;
408 dma_tx_sconfig
.direction
= DMA_MEM_TO_DEV
;
409 ret
= dmaengine_slave_config(sport
->dma_tx_chan
, &dma_tx_sconfig
);
412 dev_err(sport
->port
.dev
,
413 "DMA slave config failed, err = %d\n", ret
);
420 static void lpuart_flush_buffer(struct uart_port
*port
)
422 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
424 if (sport
->lpuart_dma_tx_use
) {
425 if (sport
->dma_tx_in_progress
) {
426 dma_unmap_sg(sport
->port
.dev
, &sport
->tx_sgl
[0],
427 sport
->dma_tx_nents
, DMA_TO_DEVICE
);
428 sport
->dma_tx_in_progress
= false;
430 dmaengine_terminate_all(sport
->dma_tx_chan
);
434 static inline void lpuart_transmit_buffer(struct lpuart_port
*sport
)
436 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
438 while (!uart_circ_empty(xmit
) &&
439 (readb(sport
->port
.membase
+ UARTTCFIFO
) < sport
->txfifo_size
)) {
440 writeb(xmit
->buf
[xmit
->tail
], sport
->port
.membase
+ UARTDR
);
441 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
442 sport
->port
.icount
.tx
++;
445 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
446 uart_write_wakeup(&sport
->port
);
448 if (uart_circ_empty(xmit
))
449 lpuart_stop_tx(&sport
->port
);
452 static inline void lpuart32_transmit_buffer(struct lpuart_port
*sport
)
454 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
457 txcnt
= lpuart32_read(sport
->port
.membase
+ UARTWATER
);
458 txcnt
= txcnt
>> UARTWATER_TXCNT_OFF
;
459 txcnt
&= UARTWATER_COUNT_MASK
;
460 while (!uart_circ_empty(xmit
) && (txcnt
< sport
->txfifo_size
)) {
461 lpuart32_write(xmit
->buf
[xmit
->tail
], sport
->port
.membase
+ UARTDATA
);
462 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
463 sport
->port
.icount
.tx
++;
464 txcnt
= lpuart32_read(sport
->port
.membase
+ UARTWATER
);
465 txcnt
= txcnt
>> UARTWATER_TXCNT_OFF
;
466 txcnt
&= UARTWATER_COUNT_MASK
;
469 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
470 uart_write_wakeup(&sport
->port
);
472 if (uart_circ_empty(xmit
))
473 lpuart32_stop_tx(&sport
->port
);
476 static void lpuart_start_tx(struct uart_port
*port
)
478 struct lpuart_port
*sport
= container_of(port
,
479 struct lpuart_port
, port
);
480 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
483 temp
= readb(port
->membase
+ UARTCR2
);
484 writeb(temp
| UARTCR2_TIE
, port
->membase
+ UARTCR2
);
486 if (sport
->lpuart_dma_tx_use
) {
487 if (!uart_circ_empty(xmit
) && !uart_tx_stopped(port
))
488 lpuart_dma_tx(sport
);
490 if (readb(port
->membase
+ UARTSR1
) & UARTSR1_TDRE
)
491 lpuart_transmit_buffer(sport
);
495 static void lpuart32_start_tx(struct uart_port
*port
)
497 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
500 temp
= lpuart32_read(port
->membase
+ UARTCTRL
);
501 lpuart32_write(temp
| UARTCTRL_TIE
, port
->membase
+ UARTCTRL
);
503 if (lpuart32_read(port
->membase
+ UARTSTAT
) & UARTSTAT_TDRE
)
504 lpuart32_transmit_buffer(sport
);
507 /* return TIOCSER_TEMT when transmitter is not busy */
508 static unsigned int lpuart_tx_empty(struct uart_port
*port
)
510 struct lpuart_port
*sport
= container_of(port
,
511 struct lpuart_port
, port
);
512 unsigned char sr1
= readb(port
->membase
+ UARTSR1
);
513 unsigned char sfifo
= readb(port
->membase
+ UARTSFIFO
);
515 if (sport
->dma_tx_in_progress
)
518 if (sr1
& UARTSR1_TC
&& sfifo
& UARTSFIFO_TXEMPT
)
524 static unsigned int lpuart32_tx_empty(struct uart_port
*port
)
526 return (lpuart32_read(port
->membase
+ UARTSTAT
) & UARTSTAT_TC
) ?
530 static irqreturn_t
lpuart_txint(int irq
, void *dev_id
)
532 struct lpuart_port
*sport
= dev_id
;
533 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
536 spin_lock_irqsave(&sport
->port
.lock
, flags
);
537 if (sport
->port
.x_char
) {
539 lpuart32_write(sport
->port
.x_char
, sport
->port
.membase
+ UARTDATA
);
541 writeb(sport
->port
.x_char
, sport
->port
.membase
+ UARTDR
);
545 if (uart_circ_empty(xmit
) || uart_tx_stopped(&sport
->port
)) {
547 lpuart32_stop_tx(&sport
->port
);
549 lpuart_stop_tx(&sport
->port
);
554 lpuart32_transmit_buffer(sport
);
556 lpuart_transmit_buffer(sport
);
558 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
559 uart_write_wakeup(&sport
->port
);
562 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
566 static irqreturn_t
lpuart_rxint(int irq
, void *dev_id
)
568 struct lpuart_port
*sport
= dev_id
;
569 unsigned int flg
, ignored
= 0;
570 struct tty_port
*port
= &sport
->port
.state
->port
;
572 unsigned char rx
, sr
;
574 spin_lock_irqsave(&sport
->port
.lock
, flags
);
576 while (!(readb(sport
->port
.membase
+ UARTSFIFO
) & UARTSFIFO_RXEMPT
)) {
578 sport
->port
.icount
.rx
++;
580 * to clear the FE, OR, NF, FE, PE flags,
581 * read SR1 then read DR
583 sr
= readb(sport
->port
.membase
+ UARTSR1
);
584 rx
= readb(sport
->port
.membase
+ UARTDR
);
586 if (uart_handle_sysrq_char(&sport
->port
, (unsigned char)rx
))
589 if (sr
& (UARTSR1_PE
| UARTSR1_OR
| UARTSR1_FE
)) {
591 sport
->port
.icount
.parity
++;
592 else if (sr
& UARTSR1_FE
)
593 sport
->port
.icount
.frame
++;
596 sport
->port
.icount
.overrun
++;
598 if (sr
& sport
->port
.ignore_status_mask
) {
604 sr
&= sport
->port
.read_status_mask
;
608 else if (sr
& UARTSR1_FE
)
615 sport
->port
.sysrq
= 0;
619 tty_insert_flip_char(port
, rx
, flg
);
623 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
625 tty_flip_buffer_push(port
);
629 static irqreturn_t
lpuart32_rxint(int irq
, void *dev_id
)
631 struct lpuart_port
*sport
= dev_id
;
632 unsigned int flg
, ignored
= 0;
633 struct tty_port
*port
= &sport
->port
.state
->port
;
635 unsigned long rx
, sr
;
637 spin_lock_irqsave(&sport
->port
.lock
, flags
);
639 while (!(lpuart32_read(sport
->port
.membase
+ UARTFIFO
) & UARTFIFO_RXEMPT
)) {
641 sport
->port
.icount
.rx
++;
643 * to clear the FE, OR, NF, FE, PE flags,
644 * read STAT then read DATA reg
646 sr
= lpuart32_read(sport
->port
.membase
+ UARTSTAT
);
647 rx
= lpuart32_read(sport
->port
.membase
+ UARTDATA
);
650 if (uart_handle_sysrq_char(&sport
->port
, (unsigned char)rx
))
653 if (sr
& (UARTSTAT_PE
| UARTSTAT_OR
| UARTSTAT_FE
)) {
654 if (sr
& UARTSTAT_PE
)
655 sport
->port
.icount
.parity
++;
656 else if (sr
& UARTSTAT_FE
)
657 sport
->port
.icount
.frame
++;
659 if (sr
& UARTSTAT_OR
)
660 sport
->port
.icount
.overrun
++;
662 if (sr
& sport
->port
.ignore_status_mask
) {
668 sr
&= sport
->port
.read_status_mask
;
670 if (sr
& UARTSTAT_PE
)
672 else if (sr
& UARTSTAT_FE
)
675 if (sr
& UARTSTAT_OR
)
679 sport
->port
.sysrq
= 0;
683 tty_insert_flip_char(port
, rx
, flg
);
687 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
689 tty_flip_buffer_push(port
);
693 static irqreturn_t
lpuart_int(int irq
, void *dev_id
)
695 struct lpuart_port
*sport
= dev_id
;
698 sts
= readb(sport
->port
.membase
+ UARTSR1
);
700 if (sts
& UARTSR1_RDRF
)
701 lpuart_rxint(irq
, dev_id
);
703 if (sts
& UARTSR1_TDRE
)
704 lpuart_txint(irq
, dev_id
);
709 static irqreturn_t
lpuart32_int(int irq
, void *dev_id
)
711 struct lpuart_port
*sport
= dev_id
;
712 unsigned long sts
, rxcount
;
714 sts
= lpuart32_read(sport
->port
.membase
+ UARTSTAT
);
715 rxcount
= lpuart32_read(sport
->port
.membase
+ UARTWATER
);
716 rxcount
= rxcount
>> UARTWATER_RXCNT_OFF
;
718 if (sts
& UARTSTAT_RDRF
|| rxcount
> 0)
719 lpuart32_rxint(irq
, dev_id
);
721 if ((sts
& UARTSTAT_TDRE
) &&
722 !(lpuart32_read(sport
->port
.membase
+ UARTBAUD
) & UARTBAUD_TDMAE
))
723 lpuart_txint(irq
, dev_id
);
725 lpuart32_write(sts
, sport
->port
.membase
+ UARTSTAT
);
729 static void lpuart_copy_rx_to_tty(struct lpuart_port
*sport
)
731 struct tty_port
*port
= &sport
->port
.state
->port
;
732 struct dma_tx_state state
;
733 enum dma_status dmastat
;
734 struct circ_buf
*ring
= &sport
->rx_ring
;
739 sr
= readb(sport
->port
.membase
+ UARTSR1
);
741 if (sr
& (UARTSR1_PE
| UARTSR1_FE
)) {
742 /* Read DR to clear the error flags */
743 readb(sport
->port
.membase
+ UARTDR
);
746 sport
->port
.icount
.parity
++;
747 else if (sr
& UARTSR1_FE
)
748 sport
->port
.icount
.frame
++;
751 async_tx_ack(sport
->dma_rx_desc
);
753 spin_lock_irqsave(&sport
->port
.lock
, flags
);
755 dmastat
= dmaengine_tx_status(sport
->dma_rx_chan
,
756 sport
->dma_rx_cookie
,
759 if (dmastat
== DMA_ERROR
) {
760 dev_err(sport
->port
.dev
, "Rx DMA transfer failed!\n");
761 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
765 /* CPU claims ownership of RX DMA buffer */
766 dma_sync_sg_for_cpu(sport
->port
.dev
, &sport
->rx_sgl
, 1, DMA_FROM_DEVICE
);
769 * ring->head points to the end of data already written by the DMA.
770 * ring->tail points to the beginning of data to be read by the
772 * The current transfer size should not be larger than the dma buffer
775 ring
->head
= sport
->rx_sgl
.length
- state
.residue
;
776 BUG_ON(ring
->head
> sport
->rx_sgl
.length
);
778 * At this point ring->head may point to the first byte right after the
779 * last byte of the dma buffer:
780 * 0 <= ring->head <= sport->rx_sgl.length
782 * However ring->tail must always points inside the dma buffer:
783 * 0 <= ring->tail <= sport->rx_sgl.length - 1
785 * Since we use a ring buffer, we have to handle the case
786 * where head is lower than tail. In such a case, we first read from
787 * tail to the end of the buffer then reset tail.
789 if (ring
->head
< ring
->tail
) {
790 count
= sport
->rx_sgl
.length
- ring
->tail
;
792 tty_insert_flip_string(port
, ring
->buf
+ ring
->tail
, count
);
794 sport
->port
.icount
.rx
+= count
;
797 /* Finally we read data from tail to head */
798 if (ring
->tail
< ring
->head
) {
799 count
= ring
->head
- ring
->tail
;
800 tty_insert_flip_string(port
, ring
->buf
+ ring
->tail
, count
);
801 /* Wrap ring->head if needed */
802 if (ring
->head
>= sport
->rx_sgl
.length
)
804 ring
->tail
= ring
->head
;
805 sport
->port
.icount
.rx
+= count
;
808 dma_sync_sg_for_device(sport
->port
.dev
, &sport
->rx_sgl
, 1,
811 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
813 tty_flip_buffer_push(port
);
814 mod_timer(&sport
->lpuart_timer
, jiffies
+ sport
->dma_rx_timeout
);
817 static void lpuart_dma_rx_complete(void *arg
)
819 struct lpuart_port
*sport
= arg
;
821 lpuart_copy_rx_to_tty(sport
);
824 static void lpuart_timer_func(unsigned long data
)
826 struct lpuart_port
*sport
= (struct lpuart_port
*)data
;
828 lpuart_copy_rx_to_tty(sport
);
831 static inline int lpuart_start_rx_dma(struct lpuart_port
*sport
)
833 struct dma_slave_config dma_rx_sconfig
= {};
834 struct circ_buf
*ring
= &sport
->rx_ring
;
837 struct tty_struct
*tty
= tty_port_tty_get(&sport
->port
.state
->port
);
838 struct ktermios
*termios
= &tty
->termios
;
840 baud
= tty_get_baud_rate(tty
);
842 bits
= (termios
->c_cflag
& CSIZE
) == CS7
? 9 : 10;
843 if (termios
->c_cflag
& PARENB
)
847 * Calculate length of one DMA buffer size to keep latency below
848 * 10ms at any baud rate.
850 sport
->rx_dma_rng_buf_len
= (DMA_RX_TIMEOUT
* baud
/ bits
/ 1000) * 2;
851 sport
->rx_dma_rng_buf_len
= (1 << (fls(sport
->rx_dma_rng_buf_len
) - 1));
852 if (sport
->rx_dma_rng_buf_len
< 16)
853 sport
->rx_dma_rng_buf_len
= 16;
855 ring
->buf
= kmalloc(sport
->rx_dma_rng_buf_len
, GFP_KERNEL
);
857 dev_err(sport
->port
.dev
, "Ring buf alloc failed\n");
861 sg_init_one(&sport
->rx_sgl
, ring
->buf
, sport
->rx_dma_rng_buf_len
);
862 sg_set_buf(&sport
->rx_sgl
, ring
->buf
, sport
->rx_dma_rng_buf_len
);
863 nent
= dma_map_sg(sport
->port
.dev
, &sport
->rx_sgl
, 1, DMA_FROM_DEVICE
);
866 dev_err(sport
->port
.dev
, "DMA Rx mapping error\n");
870 dma_rx_sconfig
.src_addr
= sport
->port
.mapbase
+ UARTDR
;
871 dma_rx_sconfig
.src_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
872 dma_rx_sconfig
.src_maxburst
= 1;
873 dma_rx_sconfig
.direction
= DMA_DEV_TO_MEM
;
874 ret
= dmaengine_slave_config(sport
->dma_rx_chan
, &dma_rx_sconfig
);
877 dev_err(sport
->port
.dev
,
878 "DMA Rx slave config failed, err = %d\n", ret
);
882 sport
->dma_rx_desc
= dmaengine_prep_dma_cyclic(sport
->dma_rx_chan
,
883 sg_dma_address(&sport
->rx_sgl
),
884 sport
->rx_sgl
.length
,
885 sport
->rx_sgl
.length
/ 2,
888 if (!sport
->dma_rx_desc
) {
889 dev_err(sport
->port
.dev
, "Cannot prepare cyclic DMA\n");
893 sport
->dma_rx_desc
->callback
= lpuart_dma_rx_complete
;
894 sport
->dma_rx_desc
->callback_param
= sport
;
895 sport
->dma_rx_cookie
= dmaengine_submit(sport
->dma_rx_desc
);
896 dma_async_issue_pending(sport
->dma_rx_chan
);
898 writeb(readb(sport
->port
.membase
+ UARTCR5
) | UARTCR5_RDMAS
,
899 sport
->port
.membase
+ UARTCR5
);
904 static void lpuart_dma_rx_free(struct uart_port
*port
)
906 struct lpuart_port
*sport
= container_of(port
,
907 struct lpuart_port
, port
);
909 if (sport
->dma_rx_chan
)
910 dmaengine_terminate_all(sport
->dma_rx_chan
);
912 dma_unmap_sg(sport
->port
.dev
, &sport
->rx_sgl
, 1, DMA_FROM_DEVICE
);
913 kfree(sport
->rx_ring
.buf
);
914 sport
->rx_ring
.tail
= 0;
915 sport
->rx_ring
.head
= 0;
916 sport
->dma_rx_desc
= NULL
;
917 sport
->dma_rx_cookie
= -EINVAL
;
920 static int lpuart_config_rs485(struct uart_port
*port
,
921 struct serial_rs485
*rs485
)
923 struct lpuart_port
*sport
= container_of(port
,
924 struct lpuart_port
, port
);
926 u8 modem
= readb(sport
->port
.membase
+ UARTMODEM
) &
927 ~(UARTMODEM_TXRTSPOL
| UARTMODEM_TXRTSE
);
928 writeb(modem
, sport
->port
.membase
+ UARTMODEM
);
930 if (rs485
->flags
& SER_RS485_ENABLED
) {
931 /* Enable auto RS-485 RTS mode */
932 modem
|= UARTMODEM_TXRTSE
;
935 * RTS needs to be logic HIGH either during transer _or_ after
936 * transfer, other variants are not supported by the hardware.
939 if (!(rs485
->flags
& (SER_RS485_RTS_ON_SEND
|
940 SER_RS485_RTS_AFTER_SEND
)))
941 rs485
->flags
|= SER_RS485_RTS_ON_SEND
;
943 if (rs485
->flags
& SER_RS485_RTS_ON_SEND
&&
944 rs485
->flags
& SER_RS485_RTS_AFTER_SEND
)
945 rs485
->flags
&= ~SER_RS485_RTS_AFTER_SEND
;
948 * The hardware defaults to RTS logic HIGH while transfer.
949 * Switch polarity in case RTS shall be logic HIGH
951 * Note: UART is assumed to be active high.
953 if (rs485
->flags
& SER_RS485_RTS_ON_SEND
)
954 modem
&= ~UARTMODEM_TXRTSPOL
;
955 else if (rs485
->flags
& SER_RS485_RTS_AFTER_SEND
)
956 modem
|= UARTMODEM_TXRTSPOL
;
959 /* Store the new configuration */
960 sport
->port
.rs485
= *rs485
;
962 writeb(modem
, sport
->port
.membase
+ UARTMODEM
);
966 static unsigned int lpuart_get_mctrl(struct uart_port
*port
)
968 unsigned int temp
= 0;
971 reg
= readb(port
->membase
+ UARTMODEM
);
972 if (reg
& UARTMODEM_TXCTSE
)
975 if (reg
& UARTMODEM_RXRTSE
)
981 static unsigned int lpuart32_get_mctrl(struct uart_port
*port
)
983 unsigned int temp
= 0;
986 reg
= lpuart32_read(port
->membase
+ UARTMODIR
);
987 if (reg
& UARTMODIR_TXCTSE
)
990 if (reg
& UARTMODIR_RXRTSE
)
996 static void lpuart_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
999 struct lpuart_port
*sport
= container_of(port
,
1000 struct lpuart_port
, port
);
1002 /* Make sure RXRTSE bit is not set when RS485 is enabled */
1003 if (!(sport
->port
.rs485
.flags
& SER_RS485_ENABLED
)) {
1004 temp
= readb(sport
->port
.membase
+ UARTMODEM
) &
1005 ~(UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1007 if (mctrl
& TIOCM_RTS
)
1008 temp
|= UARTMODEM_RXRTSE
;
1010 if (mctrl
& TIOCM_CTS
)
1011 temp
|= UARTMODEM_TXCTSE
;
1013 writeb(temp
, port
->membase
+ UARTMODEM
);
1017 static void lpuart32_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
1021 temp
= lpuart32_read(port
->membase
+ UARTMODIR
) &
1022 ~(UARTMODIR_RXRTSE
| UARTMODIR_TXCTSE
);
1024 if (mctrl
& TIOCM_RTS
)
1025 temp
|= UARTMODIR_RXRTSE
;
1027 if (mctrl
& TIOCM_CTS
)
1028 temp
|= UARTMODIR_TXCTSE
;
1030 lpuart32_write(temp
, port
->membase
+ UARTMODIR
);
1033 static void lpuart_break_ctl(struct uart_port
*port
, int break_state
)
1037 temp
= readb(port
->membase
+ UARTCR2
) & ~UARTCR2_SBK
;
1039 if (break_state
!= 0)
1040 temp
|= UARTCR2_SBK
;
1042 writeb(temp
, port
->membase
+ UARTCR2
);
1045 static void lpuart32_break_ctl(struct uart_port
*port
, int break_state
)
1049 temp
= lpuart32_read(port
->membase
+ UARTCTRL
) & ~UARTCTRL_SBK
;
1051 if (break_state
!= 0)
1052 temp
|= UARTCTRL_SBK
;
1054 lpuart32_write(temp
, port
->membase
+ UARTCTRL
);
1057 static void lpuart_setup_watermark(struct lpuart_port
*sport
)
1059 unsigned char val
, cr2
;
1060 unsigned char cr2_saved
;
1062 cr2
= readb(sport
->port
.membase
+ UARTCR2
);
1064 cr2
&= ~(UARTCR2_TIE
| UARTCR2_TCIE
| UARTCR2_TE
|
1065 UARTCR2_RIE
| UARTCR2_RE
);
1066 writeb(cr2
, sport
->port
.membase
+ UARTCR2
);
1068 val
= readb(sport
->port
.membase
+ UARTPFIFO
);
1069 writeb(val
| UARTPFIFO_TXFE
| UARTPFIFO_RXFE
,
1070 sport
->port
.membase
+ UARTPFIFO
);
1072 /* flush Tx and Rx FIFO */
1073 writeb(UARTCFIFO_TXFLUSH
| UARTCFIFO_RXFLUSH
,
1074 sport
->port
.membase
+ UARTCFIFO
);
1076 /* explicitly clear RDRF */
1077 if (readb(sport
->port
.membase
+ UARTSR1
) & UARTSR1_RDRF
) {
1078 readb(sport
->port
.membase
+ UARTDR
);
1079 writeb(UARTSFIFO_RXUF
, sport
->port
.membase
+ UARTSFIFO
);
1082 writeb(0, sport
->port
.membase
+ UARTTWFIFO
);
1083 writeb(1, sport
->port
.membase
+ UARTRWFIFO
);
1086 writeb(cr2_saved
, sport
->port
.membase
+ UARTCR2
);
1089 static void lpuart32_setup_watermark(struct lpuart_port
*sport
)
1091 unsigned long val
, ctrl
;
1092 unsigned long ctrl_saved
;
1094 ctrl
= lpuart32_read(sport
->port
.membase
+ UARTCTRL
);
1096 ctrl
&= ~(UARTCTRL_TIE
| UARTCTRL_TCIE
| UARTCTRL_TE
|
1097 UARTCTRL_RIE
| UARTCTRL_RE
);
1098 lpuart32_write(ctrl
, sport
->port
.membase
+ UARTCTRL
);
1100 /* enable FIFO mode */
1101 val
= lpuart32_read(sport
->port
.membase
+ UARTFIFO
);
1102 val
|= UARTFIFO_TXFE
| UARTFIFO_RXFE
;
1103 val
|= UARTFIFO_TXFLUSH
| UARTFIFO_RXFLUSH
;
1104 lpuart32_write(val
, sport
->port
.membase
+ UARTFIFO
);
1106 /* set the watermark */
1107 val
= (0x1 << UARTWATER_RXWATER_OFF
) | (0x0 << UARTWATER_TXWATER_OFF
);
1108 lpuart32_write(val
, sport
->port
.membase
+ UARTWATER
);
1111 lpuart32_write(ctrl_saved
, sport
->port
.membase
+ UARTCTRL
);
1114 static void rx_dma_timer_init(struct lpuart_port
*sport
)
1116 setup_timer(&sport
->lpuart_timer
, lpuart_timer_func
,
1117 (unsigned long)sport
);
1118 sport
->lpuart_timer
.expires
= jiffies
+ sport
->dma_rx_timeout
;
1119 add_timer(&sport
->lpuart_timer
);
1122 static int lpuart_startup(struct uart_port
*port
)
1124 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1126 unsigned long flags
;
1129 /* determine FIFO size and enable FIFO mode */
1130 temp
= readb(sport
->port
.membase
+ UARTPFIFO
);
1132 sport
->txfifo_size
= 0x1 << (((temp
>> UARTPFIFO_TXSIZE_OFF
) &
1133 UARTPFIFO_FIFOSIZE_MASK
) + 1);
1135 sport
->port
.fifosize
= sport
->txfifo_size
;
1137 sport
->rxfifo_size
= 0x1 << (((temp
>> UARTPFIFO_RXSIZE_OFF
) &
1138 UARTPFIFO_FIFOSIZE_MASK
) + 1);
1140 ret
= devm_request_irq(port
->dev
, port
->irq
, lpuart_int
, 0,
1141 DRIVER_NAME
, sport
);
1145 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1147 lpuart_setup_watermark(sport
);
1149 temp
= readb(sport
->port
.membase
+ UARTCR2
);
1150 temp
|= (UARTCR2_RIE
| UARTCR2_TIE
| UARTCR2_RE
| UARTCR2_TE
);
1151 writeb(temp
, sport
->port
.membase
+ UARTCR2
);
1153 if (sport
->dma_rx_chan
&& !lpuart_start_rx_dma(sport
)) {
1154 /* set Rx DMA timeout */
1155 sport
->dma_rx_timeout
= msecs_to_jiffies(DMA_RX_TIMEOUT
);
1156 if (!sport
->dma_rx_timeout
)
1157 sport
->dma_rx_timeout
= 1;
1159 sport
->lpuart_dma_rx_use
= true;
1160 rx_dma_timer_init(sport
);
1162 sport
->lpuart_dma_rx_use
= false;
1165 if (sport
->dma_tx_chan
&& !lpuart_dma_tx_request(port
)) {
1166 init_waitqueue_head(&sport
->dma_wait
);
1167 sport
->lpuart_dma_tx_use
= true;
1168 temp
= readb(port
->membase
+ UARTCR5
);
1169 writeb(temp
| UARTCR5_TDMAS
, port
->membase
+ UARTCR5
);
1171 sport
->lpuart_dma_tx_use
= false;
1174 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1179 static int lpuart32_startup(struct uart_port
*port
)
1181 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1183 unsigned long flags
;
1186 /* determine FIFO size */
1187 temp
= lpuart32_read(sport
->port
.membase
+ UARTFIFO
);
1189 sport
->txfifo_size
= 0x1 << (((temp
>> UARTFIFO_TXSIZE_OFF
) &
1190 UARTFIFO_FIFOSIZE_MASK
) - 1);
1192 sport
->rxfifo_size
= 0x1 << (((temp
>> UARTFIFO_RXSIZE_OFF
) &
1193 UARTFIFO_FIFOSIZE_MASK
) - 1);
1195 ret
= devm_request_irq(port
->dev
, port
->irq
, lpuart32_int
, 0,
1196 DRIVER_NAME
, sport
);
1200 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1202 lpuart32_setup_watermark(sport
);
1204 temp
= lpuart32_read(sport
->port
.membase
+ UARTCTRL
);
1205 temp
|= (UARTCTRL_RIE
| UARTCTRL_TIE
| UARTCTRL_RE
| UARTCTRL_TE
);
1206 temp
|= UARTCTRL_ILIE
;
1207 lpuart32_write(temp
, sport
->port
.membase
+ UARTCTRL
);
1209 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1213 static void lpuart_shutdown(struct uart_port
*port
)
1215 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1217 unsigned long flags
;
1219 spin_lock_irqsave(&port
->lock
, flags
);
1221 /* disable Rx/Tx and interrupts */
1222 temp
= readb(port
->membase
+ UARTCR2
);
1223 temp
&= ~(UARTCR2_TE
| UARTCR2_RE
|
1224 UARTCR2_TIE
| UARTCR2_TCIE
| UARTCR2_RIE
);
1225 writeb(temp
, port
->membase
+ UARTCR2
);
1227 spin_unlock_irqrestore(&port
->lock
, flags
);
1229 devm_free_irq(port
->dev
, port
->irq
, sport
);
1231 if (sport
->lpuart_dma_rx_use
) {
1232 del_timer_sync(&sport
->lpuart_timer
);
1233 lpuart_dma_rx_free(&sport
->port
);
1236 if (sport
->lpuart_dma_tx_use
) {
1237 if (wait_event_interruptible(sport
->dma_wait
,
1238 !sport
->dma_tx_in_progress
) != false) {
1239 sport
->dma_tx_in_progress
= false;
1240 dmaengine_terminate_all(sport
->dma_tx_chan
);
1243 lpuart_stop_tx(port
);
1247 static void lpuart32_shutdown(struct uart_port
*port
)
1249 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1251 unsigned long flags
;
1253 spin_lock_irqsave(&port
->lock
, flags
);
1255 /* disable Rx/Tx and interrupts */
1256 temp
= lpuart32_read(port
->membase
+ UARTCTRL
);
1257 temp
&= ~(UARTCTRL_TE
| UARTCTRL_RE
|
1258 UARTCTRL_TIE
| UARTCTRL_TCIE
| UARTCTRL_RIE
);
1259 lpuart32_write(temp
, port
->membase
+ UARTCTRL
);
1261 spin_unlock_irqrestore(&port
->lock
, flags
);
1263 devm_free_irq(port
->dev
, port
->irq
, sport
);
1267 lpuart_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
1268 struct ktermios
*old
)
1270 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1271 unsigned long flags
;
1272 unsigned char cr1
, old_cr1
, old_cr2
, cr3
, cr4
, bdh
, modem
;
1274 unsigned int old_csize
= old
? old
->c_cflag
& CSIZE
: CS8
;
1275 unsigned int sbr
, brfa
;
1277 cr1
= old_cr1
= readb(sport
->port
.membase
+ UARTCR1
);
1278 old_cr2
= readb(sport
->port
.membase
+ UARTCR2
);
1279 cr3
= readb(sport
->port
.membase
+ UARTCR3
);
1280 cr4
= readb(sport
->port
.membase
+ UARTCR4
);
1281 bdh
= readb(sport
->port
.membase
+ UARTBDH
);
1282 modem
= readb(sport
->port
.membase
+ UARTMODEM
);
1284 * only support CS8 and CS7, and for CS7 must enable PE.
1291 while ((termios
->c_cflag
& CSIZE
) != CS8
&&
1292 (termios
->c_cflag
& CSIZE
) != CS7
) {
1293 termios
->c_cflag
&= ~CSIZE
;
1294 termios
->c_cflag
|= old_csize
;
1298 if ((termios
->c_cflag
& CSIZE
) == CS8
||
1299 (termios
->c_cflag
& CSIZE
) == CS7
)
1300 cr1
= old_cr1
& ~UARTCR1_M
;
1302 if (termios
->c_cflag
& CMSPAR
) {
1303 if ((termios
->c_cflag
& CSIZE
) != CS8
) {
1304 termios
->c_cflag
&= ~CSIZE
;
1305 termios
->c_cflag
|= CS8
;
1311 * When auto RS-485 RTS mode is enabled,
1312 * hardware flow control need to be disabled.
1314 if (sport
->port
.rs485
.flags
& SER_RS485_ENABLED
)
1315 termios
->c_cflag
&= ~CRTSCTS
;
1317 if (termios
->c_cflag
& CRTSCTS
) {
1318 modem
|= (UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1320 termios
->c_cflag
&= ~CRTSCTS
;
1321 modem
&= ~(UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1324 if (termios
->c_cflag
& CSTOPB
)
1325 termios
->c_cflag
&= ~CSTOPB
;
1327 /* parity must be enabled when CS7 to match 8-bits format */
1328 if ((termios
->c_cflag
& CSIZE
) == CS7
)
1329 termios
->c_cflag
|= PARENB
;
1331 if ((termios
->c_cflag
& PARENB
)) {
1332 if (termios
->c_cflag
& CMSPAR
) {
1334 if (termios
->c_cflag
& PARODD
)
1340 if ((termios
->c_cflag
& CSIZE
) == CS8
)
1342 if (termios
->c_cflag
& PARODD
)
1349 /* ask the core to calculate the divisor */
1350 baud
= uart_get_baud_rate(port
, termios
, old
, 50, port
->uartclk
/ 16);
1352 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1354 sport
->port
.read_status_mask
= 0;
1355 if (termios
->c_iflag
& INPCK
)
1356 sport
->port
.read_status_mask
|= (UARTSR1_FE
| UARTSR1_PE
);
1357 if (termios
->c_iflag
& (IGNBRK
| BRKINT
| PARMRK
))
1358 sport
->port
.read_status_mask
|= UARTSR1_FE
;
1360 /* characters to ignore */
1361 sport
->port
.ignore_status_mask
= 0;
1362 if (termios
->c_iflag
& IGNPAR
)
1363 sport
->port
.ignore_status_mask
|= UARTSR1_PE
;
1364 if (termios
->c_iflag
& IGNBRK
) {
1365 sport
->port
.ignore_status_mask
|= UARTSR1_FE
;
1367 * if we're ignoring parity and break indicators,
1368 * ignore overruns too (for real raw support).
1370 if (termios
->c_iflag
& IGNPAR
)
1371 sport
->port
.ignore_status_mask
|= UARTSR1_OR
;
1374 /* update the per-port timeout */
1375 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1377 /* wait transmit engin complete */
1378 while (!(readb(sport
->port
.membase
+ UARTSR1
) & UARTSR1_TC
))
1381 /* disable transmit and receive */
1382 writeb(old_cr2
& ~(UARTCR2_TE
| UARTCR2_RE
),
1383 sport
->port
.membase
+ UARTCR2
);
1385 sbr
= sport
->port
.uartclk
/ (16 * baud
);
1386 brfa
= ((sport
->port
.uartclk
- (16 * sbr
* baud
)) * 2) / baud
;
1387 bdh
&= ~UARTBDH_SBR_MASK
;
1388 bdh
|= (sbr
>> 8) & 0x1F;
1389 cr4
&= ~UARTCR4_BRFA_MASK
;
1390 brfa
&= UARTCR4_BRFA_MASK
;
1391 writeb(cr4
| brfa
, sport
->port
.membase
+ UARTCR4
);
1392 writeb(bdh
, sport
->port
.membase
+ UARTBDH
);
1393 writeb(sbr
& 0xFF, sport
->port
.membase
+ UARTBDL
);
1394 writeb(cr3
, sport
->port
.membase
+ UARTCR3
);
1395 writeb(cr1
, sport
->port
.membase
+ UARTCR1
);
1396 writeb(modem
, sport
->port
.membase
+ UARTMODEM
);
1398 /* restore control register */
1399 writeb(old_cr2
, sport
->port
.membase
+ UARTCR2
);
1402 * If new baud rate is set, we will also need to update the Ring buffer
1403 * length according to the selected baud rate and restart Rx DMA path.
1406 if (sport
->lpuart_dma_rx_use
) {
1407 del_timer_sync(&sport
->lpuart_timer
);
1408 lpuart_dma_rx_free(&sport
->port
);
1411 if (sport
->dma_rx_chan
&& !lpuart_start_rx_dma(sport
)) {
1412 sport
->lpuart_dma_rx_use
= true;
1413 rx_dma_timer_init(sport
);
1415 sport
->lpuart_dma_rx_use
= false;
1419 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1423 lpuart32_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
1424 struct ktermios
*old
)
1426 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1427 unsigned long flags
;
1428 unsigned long ctrl
, old_ctrl
, bd
, modem
;
1430 unsigned int old_csize
= old
? old
->c_cflag
& CSIZE
: CS8
;
1433 ctrl
= old_ctrl
= lpuart32_read(sport
->port
.membase
+ UARTCTRL
);
1434 bd
= lpuart32_read(sport
->port
.membase
+ UARTBAUD
);
1435 modem
= lpuart32_read(sport
->port
.membase
+ UARTMODIR
);
1437 * only support CS8 and CS7, and for CS7 must enable PE.
1444 while ((termios
->c_cflag
& CSIZE
) != CS8
&&
1445 (termios
->c_cflag
& CSIZE
) != CS7
) {
1446 termios
->c_cflag
&= ~CSIZE
;
1447 termios
->c_cflag
|= old_csize
;
1451 if ((termios
->c_cflag
& CSIZE
) == CS8
||
1452 (termios
->c_cflag
& CSIZE
) == CS7
)
1453 ctrl
= old_ctrl
& ~UARTCTRL_M
;
1455 if (termios
->c_cflag
& CMSPAR
) {
1456 if ((termios
->c_cflag
& CSIZE
) != CS8
) {
1457 termios
->c_cflag
&= ~CSIZE
;
1458 termios
->c_cflag
|= CS8
;
1463 if (termios
->c_cflag
& CRTSCTS
) {
1464 modem
|= (UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1466 termios
->c_cflag
&= ~CRTSCTS
;
1467 modem
&= ~(UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1470 if (termios
->c_cflag
& CSTOPB
)
1471 termios
->c_cflag
&= ~CSTOPB
;
1473 /* parity must be enabled when CS7 to match 8-bits format */
1474 if ((termios
->c_cflag
& CSIZE
) == CS7
)
1475 termios
->c_cflag
|= PARENB
;
1477 if ((termios
->c_cflag
& PARENB
)) {
1478 if (termios
->c_cflag
& CMSPAR
) {
1479 ctrl
&= ~UARTCTRL_PE
;
1483 if ((termios
->c_cflag
& CSIZE
) == CS8
)
1485 if (termios
->c_cflag
& PARODD
)
1486 ctrl
|= UARTCTRL_PT
;
1488 ctrl
&= ~UARTCTRL_PT
;
1492 /* ask the core to calculate the divisor */
1493 baud
= uart_get_baud_rate(port
, termios
, old
, 50, port
->uartclk
/ 16);
1495 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1497 sport
->port
.read_status_mask
= 0;
1498 if (termios
->c_iflag
& INPCK
)
1499 sport
->port
.read_status_mask
|= (UARTSTAT_FE
| UARTSTAT_PE
);
1500 if (termios
->c_iflag
& (IGNBRK
| BRKINT
| PARMRK
))
1501 sport
->port
.read_status_mask
|= UARTSTAT_FE
;
1503 /* characters to ignore */
1504 sport
->port
.ignore_status_mask
= 0;
1505 if (termios
->c_iflag
& IGNPAR
)
1506 sport
->port
.ignore_status_mask
|= UARTSTAT_PE
;
1507 if (termios
->c_iflag
& IGNBRK
) {
1508 sport
->port
.ignore_status_mask
|= UARTSTAT_FE
;
1510 * if we're ignoring parity and break indicators,
1511 * ignore overruns too (for real raw support).
1513 if (termios
->c_iflag
& IGNPAR
)
1514 sport
->port
.ignore_status_mask
|= UARTSTAT_OR
;
1517 /* update the per-port timeout */
1518 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1520 /* wait transmit engin complete */
1521 while (!(lpuart32_read(sport
->port
.membase
+ UARTSTAT
) & UARTSTAT_TC
))
1524 /* disable transmit and receive */
1525 lpuart32_write(old_ctrl
& ~(UARTCTRL_TE
| UARTCTRL_RE
),
1526 sport
->port
.membase
+ UARTCTRL
);
1528 sbr
= sport
->port
.uartclk
/ (16 * baud
);
1529 bd
&= ~UARTBAUD_SBR_MASK
;
1530 bd
|= sbr
& UARTBAUD_SBR_MASK
;
1531 bd
|= UARTBAUD_BOTHEDGE
;
1532 bd
&= ~(UARTBAUD_TDMAE
| UARTBAUD_RDMAE
);
1533 lpuart32_write(bd
, sport
->port
.membase
+ UARTBAUD
);
1534 lpuart32_write(modem
, sport
->port
.membase
+ UARTMODIR
);
1535 lpuart32_write(ctrl
, sport
->port
.membase
+ UARTCTRL
);
1536 /* restore control register */
1538 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1541 static const char *lpuart_type(struct uart_port
*port
)
1543 return "FSL_LPUART";
1546 static void lpuart_release_port(struct uart_port
*port
)
1551 static int lpuart_request_port(struct uart_port
*port
)
1556 /* configure/autoconfigure the port */
1557 static void lpuart_config_port(struct uart_port
*port
, int flags
)
1559 if (flags
& UART_CONFIG_TYPE
)
1560 port
->type
= PORT_LPUART
;
1563 static int lpuart_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
1567 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_LPUART
)
1569 if (port
->irq
!= ser
->irq
)
1571 if (ser
->io_type
!= UPIO_MEM
)
1573 if (port
->uartclk
/ 16 != ser
->baud_base
)
1575 if (port
->iobase
!= ser
->port
)
1582 static struct uart_ops lpuart_pops
= {
1583 .tx_empty
= lpuart_tx_empty
,
1584 .set_mctrl
= lpuart_set_mctrl
,
1585 .get_mctrl
= lpuart_get_mctrl
,
1586 .stop_tx
= lpuart_stop_tx
,
1587 .start_tx
= lpuart_start_tx
,
1588 .stop_rx
= lpuart_stop_rx
,
1589 .break_ctl
= lpuart_break_ctl
,
1590 .startup
= lpuart_startup
,
1591 .shutdown
= lpuart_shutdown
,
1592 .set_termios
= lpuart_set_termios
,
1593 .type
= lpuart_type
,
1594 .request_port
= lpuart_request_port
,
1595 .release_port
= lpuart_release_port
,
1596 .config_port
= lpuart_config_port
,
1597 .verify_port
= lpuart_verify_port
,
1598 .flush_buffer
= lpuart_flush_buffer
,
1601 static struct uart_ops lpuart32_pops
= {
1602 .tx_empty
= lpuart32_tx_empty
,
1603 .set_mctrl
= lpuart32_set_mctrl
,
1604 .get_mctrl
= lpuart32_get_mctrl
,
1605 .stop_tx
= lpuart32_stop_tx
,
1606 .start_tx
= lpuart32_start_tx
,
1607 .stop_rx
= lpuart32_stop_rx
,
1608 .break_ctl
= lpuart32_break_ctl
,
1609 .startup
= lpuart32_startup
,
1610 .shutdown
= lpuart32_shutdown
,
1611 .set_termios
= lpuart32_set_termios
,
1612 .type
= lpuart_type
,
1613 .request_port
= lpuart_request_port
,
1614 .release_port
= lpuart_release_port
,
1615 .config_port
= lpuart_config_port
,
1616 .verify_port
= lpuart_verify_port
,
1617 .flush_buffer
= lpuart_flush_buffer
,
1620 static struct lpuart_port
*lpuart_ports
[UART_NR
];
1622 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1623 static void lpuart_console_putchar(struct uart_port
*port
, int ch
)
1625 while (!(readb(port
->membase
+ UARTSR1
) & UARTSR1_TDRE
))
1628 writeb(ch
, port
->membase
+ UARTDR
);
1631 static void lpuart32_console_putchar(struct uart_port
*port
, int ch
)
1633 while (!(lpuart32_read(port
->membase
+ UARTSTAT
) & UARTSTAT_TDRE
))
1636 lpuart32_write(ch
, port
->membase
+ UARTDATA
);
1640 lpuart_console_write(struct console
*co
, const char *s
, unsigned int count
)
1642 struct lpuart_port
*sport
= lpuart_ports
[co
->index
];
1643 unsigned char old_cr2
, cr2
;
1645 /* first save CR2 and then disable interrupts */
1646 cr2
= old_cr2
= readb(sport
->port
.membase
+ UARTCR2
);
1647 cr2
|= (UARTCR2_TE
| UARTCR2_RE
);
1648 cr2
&= ~(UARTCR2_TIE
| UARTCR2_TCIE
| UARTCR2_RIE
);
1649 writeb(cr2
, sport
->port
.membase
+ UARTCR2
);
1651 uart_console_write(&sport
->port
, s
, count
, lpuart_console_putchar
);
1653 /* wait for transmitter finish complete and restore CR2 */
1654 while (!(readb(sport
->port
.membase
+ UARTSR1
) & UARTSR1_TC
))
1657 writeb(old_cr2
, sport
->port
.membase
+ UARTCR2
);
1661 lpuart32_console_write(struct console
*co
, const char *s
, unsigned int count
)
1663 struct lpuart_port
*sport
= lpuart_ports
[co
->index
];
1664 unsigned long old_cr
, cr
;
1666 /* first save CR2 and then disable interrupts */
1667 cr
= old_cr
= lpuart32_read(sport
->port
.membase
+ UARTCTRL
);
1668 cr
|= (UARTCTRL_TE
| UARTCTRL_RE
);
1669 cr
&= ~(UARTCTRL_TIE
| UARTCTRL_TCIE
| UARTCTRL_RIE
);
1670 lpuart32_write(cr
, sport
->port
.membase
+ UARTCTRL
);
1672 uart_console_write(&sport
->port
, s
, count
, lpuart32_console_putchar
);
1674 /* wait for transmitter finish complete and restore CR2 */
1675 while (!(lpuart32_read(sport
->port
.membase
+ UARTSTAT
) & UARTSTAT_TC
))
1678 lpuart32_write(old_cr
, sport
->port
.membase
+ UARTCTRL
);
1682 * if the port was already initialised (eg, by a boot loader),
1683 * try to determine the current setup.
1686 lpuart_console_get_options(struct lpuart_port
*sport
, int *baud
,
1687 int *parity
, int *bits
)
1689 unsigned char cr
, bdh
, bdl
, brfa
;
1690 unsigned int sbr
, uartclk
, baud_raw
;
1692 cr
= readb(sport
->port
.membase
+ UARTCR2
);
1693 cr
&= UARTCR2_TE
| UARTCR2_RE
;
1697 /* ok, the port was enabled */
1699 cr
= readb(sport
->port
.membase
+ UARTCR1
);
1702 if (cr
& UARTCR1_PE
) {
1703 if (cr
& UARTCR1_PT
)
1714 bdh
= readb(sport
->port
.membase
+ UARTBDH
);
1715 bdh
&= UARTBDH_SBR_MASK
;
1716 bdl
= readb(sport
->port
.membase
+ UARTBDL
);
1720 brfa
= readb(sport
->port
.membase
+ UARTCR4
);
1721 brfa
&= UARTCR4_BRFA_MASK
;
1723 uartclk
= clk_get_rate(sport
->clk
);
1725 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1727 baud_raw
= uartclk
/ (16 * (sbr
+ brfa
/ 32));
1729 if (*baud
!= baud_raw
)
1730 printk(KERN_INFO
"Serial: Console lpuart rounded baud rate"
1731 "from %d to %d\n", baud_raw
, *baud
);
1735 lpuart32_console_get_options(struct lpuart_port
*sport
, int *baud
,
1736 int *parity
, int *bits
)
1738 unsigned long cr
, bd
;
1739 unsigned int sbr
, uartclk
, baud_raw
;
1741 cr
= lpuart32_read(sport
->port
.membase
+ UARTCTRL
);
1742 cr
&= UARTCTRL_TE
| UARTCTRL_RE
;
1746 /* ok, the port was enabled */
1748 cr
= lpuart32_read(sport
->port
.membase
+ UARTCTRL
);
1751 if (cr
& UARTCTRL_PE
) {
1752 if (cr
& UARTCTRL_PT
)
1758 if (cr
& UARTCTRL_M
)
1763 bd
= lpuart32_read(sport
->port
.membase
+ UARTBAUD
);
1764 bd
&= UARTBAUD_SBR_MASK
;
1766 uartclk
= clk_get_rate(sport
->clk
);
1768 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1770 baud_raw
= uartclk
/ (16 * sbr
);
1772 if (*baud
!= baud_raw
)
1773 printk(KERN_INFO
"Serial: Console lpuart rounded baud rate"
1774 "from %d to %d\n", baud_raw
, *baud
);
1777 static int __init
lpuart_console_setup(struct console
*co
, char *options
)
1779 struct lpuart_port
*sport
;
1786 * check whether an invalid uart number has been specified, and
1787 * if so, search for the first available port that does have
1790 if (co
->index
== -1 || co
->index
>= ARRAY_SIZE(lpuart_ports
))
1793 sport
= lpuart_ports
[co
->index
];
1798 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1800 if (sport
->lpuart32
)
1801 lpuart32_console_get_options(sport
, &baud
, &parity
, &bits
);
1803 lpuart_console_get_options(sport
, &baud
, &parity
, &bits
);
1805 if (sport
->lpuart32
)
1806 lpuart32_setup_watermark(sport
);
1808 lpuart_setup_watermark(sport
);
1810 return uart_set_options(&sport
->port
, co
, baud
, parity
, bits
, flow
);
1813 static struct uart_driver lpuart_reg
;
1814 static struct console lpuart_console
= {
1816 .write
= lpuart_console_write
,
1817 .device
= uart_console_device
,
1818 .setup
= lpuart_console_setup
,
1819 .flags
= CON_PRINTBUFFER
,
1821 .data
= &lpuart_reg
,
1824 static struct console lpuart32_console
= {
1826 .write
= lpuart32_console_write
,
1827 .device
= uart_console_device
,
1828 .setup
= lpuart_console_setup
,
1829 .flags
= CON_PRINTBUFFER
,
1831 .data
= &lpuart_reg
,
1834 static void lpuart_early_write(struct console
*con
, const char *s
, unsigned n
)
1836 struct earlycon_device
*dev
= con
->data
;
1838 uart_console_write(&dev
->port
, s
, n
, lpuart_console_putchar
);
1841 static void lpuart32_early_write(struct console
*con
, const char *s
, unsigned n
)
1843 struct earlycon_device
*dev
= con
->data
;
1845 uart_console_write(&dev
->port
, s
, n
, lpuart32_console_putchar
);
1848 static int __init
lpuart_early_console_setup(struct earlycon_device
*device
,
1851 if (!device
->port
.membase
)
1854 device
->con
->write
= lpuart_early_write
;
1858 static int __init
lpuart32_early_console_setup(struct earlycon_device
*device
,
1861 if (!device
->port
.membase
)
1864 device
->con
->write
= lpuart32_early_write
;
1868 OF_EARLYCON_DECLARE(lpuart
, "fsl,vf610-lpuart", lpuart_early_console_setup
);
1869 OF_EARLYCON_DECLARE(lpuart32
, "fsl,ls1021a-lpuart", lpuart32_early_console_setup
);
1870 EARLYCON_DECLARE(lpuart
, lpuart_early_console_setup
);
1871 EARLYCON_DECLARE(lpuart32
, lpuart32_early_console_setup
);
1873 #define LPUART_CONSOLE (&lpuart_console)
1874 #define LPUART32_CONSOLE (&lpuart32_console)
1876 #define LPUART_CONSOLE NULL
1877 #define LPUART32_CONSOLE NULL
1880 static struct uart_driver lpuart_reg
= {
1881 .owner
= THIS_MODULE
,
1882 .driver_name
= DRIVER_NAME
,
1883 .dev_name
= DEV_NAME
,
1884 .nr
= ARRAY_SIZE(lpuart_ports
),
1885 .cons
= LPUART_CONSOLE
,
1888 static int lpuart_probe(struct platform_device
*pdev
)
1890 struct device_node
*np
= pdev
->dev
.of_node
;
1891 struct lpuart_port
*sport
;
1892 struct resource
*res
;
1895 sport
= devm_kzalloc(&pdev
->dev
, sizeof(*sport
), GFP_KERNEL
);
1899 pdev
->dev
.coherent_dma_mask
= 0;
1901 ret
= of_alias_get_id(np
, "serial");
1903 dev_err(&pdev
->dev
, "failed to get alias id, errno %d\n", ret
);
1906 sport
->port
.line
= ret
;
1907 sport
->lpuart32
= of_device_is_compatible(np
, "fsl,ls1021a-lpuart");
1909 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1910 sport
->port
.membase
= devm_ioremap_resource(&pdev
->dev
, res
);
1911 if (IS_ERR(sport
->port
.membase
))
1912 return PTR_ERR(sport
->port
.membase
);
1914 sport
->port
.mapbase
= res
->start
;
1915 sport
->port
.dev
= &pdev
->dev
;
1916 sport
->port
.type
= PORT_LPUART
;
1917 sport
->port
.iotype
= UPIO_MEM
;
1918 ret
= platform_get_irq(pdev
, 0);
1920 dev_err(&pdev
->dev
, "cannot obtain irq\n");
1923 sport
->port
.irq
= ret
;
1925 if (sport
->lpuart32
)
1926 sport
->port
.ops
= &lpuart32_pops
;
1928 sport
->port
.ops
= &lpuart_pops
;
1929 sport
->port
.flags
= UPF_BOOT_AUTOCONF
;
1931 sport
->port
.rs485_config
= lpuart_config_rs485
;
1933 sport
->clk
= devm_clk_get(&pdev
->dev
, "ipg");
1934 if (IS_ERR(sport
->clk
)) {
1935 ret
= PTR_ERR(sport
->clk
);
1936 dev_err(&pdev
->dev
, "failed to get uart clk: %d\n", ret
);
1940 ret
= clk_prepare_enable(sport
->clk
);
1942 dev_err(&pdev
->dev
, "failed to enable uart clk: %d\n", ret
);
1946 sport
->port
.uartclk
= clk_get_rate(sport
->clk
);
1948 lpuart_ports
[sport
->port
.line
] = sport
;
1950 platform_set_drvdata(pdev
, &sport
->port
);
1952 if (sport
->lpuart32
)
1953 lpuart_reg
.cons
= LPUART32_CONSOLE
;
1955 lpuart_reg
.cons
= LPUART_CONSOLE
;
1957 ret
= uart_add_one_port(&lpuart_reg
, &sport
->port
);
1959 clk_disable_unprepare(sport
->clk
);
1963 sport
->dma_tx_chan
= dma_request_slave_channel(sport
->port
.dev
, "tx");
1964 if (!sport
->dma_tx_chan
)
1965 dev_info(sport
->port
.dev
, "DMA tx channel request failed, "
1966 "operating without tx DMA\n");
1968 sport
->dma_rx_chan
= dma_request_slave_channel(sport
->port
.dev
, "rx");
1969 if (!sport
->dma_rx_chan
)
1970 dev_info(sport
->port
.dev
, "DMA rx channel request failed, "
1971 "operating without rx DMA\n");
1973 if (of_property_read_bool(np
, "linux,rs485-enabled-at-boot-time")) {
1974 sport
->port
.rs485
.flags
|= SER_RS485_ENABLED
;
1975 sport
->port
.rs485
.flags
|= SER_RS485_RTS_ON_SEND
;
1976 writeb(UARTMODEM_TXRTSE
, sport
->port
.membase
+ UARTMODEM
);
1982 static int lpuart_remove(struct platform_device
*pdev
)
1984 struct lpuart_port
*sport
= platform_get_drvdata(pdev
);
1986 uart_remove_one_port(&lpuart_reg
, &sport
->port
);
1988 clk_disable_unprepare(sport
->clk
);
1990 if (sport
->dma_tx_chan
)
1991 dma_release_channel(sport
->dma_tx_chan
);
1993 if (sport
->dma_rx_chan
)
1994 dma_release_channel(sport
->dma_rx_chan
);
1999 #ifdef CONFIG_PM_SLEEP
2000 static int lpuart_suspend(struct device
*dev
)
2002 struct lpuart_port
*sport
= dev_get_drvdata(dev
);
2005 if (sport
->lpuart32
) {
2006 /* disable Rx/Tx and interrupts */
2007 temp
= lpuart32_read(sport
->port
.membase
+ UARTCTRL
);
2008 temp
&= ~(UARTCTRL_TE
| UARTCTRL_TIE
| UARTCTRL_TCIE
);
2009 lpuart32_write(temp
, sport
->port
.membase
+ UARTCTRL
);
2011 /* disable Rx/Tx and interrupts */
2012 temp
= readb(sport
->port
.membase
+ UARTCR2
);
2013 temp
&= ~(UARTCR2_TE
| UARTCR2_TIE
| UARTCR2_TCIE
);
2014 writeb(temp
, sport
->port
.membase
+ UARTCR2
);
2017 uart_suspend_port(&lpuart_reg
, &sport
->port
);
2019 if (sport
->lpuart_dma_rx_use
) {
2021 * EDMA driver during suspend will forcefully release any
2022 * non-idle DMA channels. If port wakeup is enabled or if port
2023 * is console port or 'no_console_suspend' is set the Rx DMA
2024 * cannot resume as as expected, hence gracefully release the
2025 * Rx DMA path before suspend and start Rx DMA path on resume.
2027 if (sport
->port
.irq_wake
) {
2028 del_timer_sync(&sport
->lpuart_timer
);
2029 lpuart_dma_rx_free(&sport
->port
);
2032 /* Disable Rx DMA to use UART port as wakeup source */
2033 writeb(readb(sport
->port
.membase
+ UARTCR5
) & ~UARTCR5_RDMAS
,
2034 sport
->port
.membase
+ UARTCR5
);
2037 if (sport
->lpuart_dma_tx_use
) {
2038 sport
->dma_tx_in_progress
= false;
2039 dmaengine_terminate_all(sport
->dma_tx_chan
);
2042 if (sport
->port
.suspended
&& !sport
->port
.irq_wake
)
2043 clk_disable_unprepare(sport
->clk
);
2048 static int lpuart_resume(struct device
*dev
)
2050 struct lpuart_port
*sport
= dev_get_drvdata(dev
);
2053 if (sport
->port
.suspended
&& !sport
->port
.irq_wake
)
2054 clk_prepare_enable(sport
->clk
);
2056 if (sport
->lpuart32
) {
2057 lpuart32_setup_watermark(sport
);
2058 temp
= lpuart32_read(sport
->port
.membase
+ UARTCTRL
);
2059 temp
|= (UARTCTRL_RIE
| UARTCTRL_TIE
| UARTCTRL_RE
|
2060 UARTCTRL_TE
| UARTCTRL_ILIE
);
2061 lpuart32_write(temp
, sport
->port
.membase
+ UARTCTRL
);
2063 lpuart_setup_watermark(sport
);
2064 temp
= readb(sport
->port
.membase
+ UARTCR2
);
2065 temp
|= (UARTCR2_RIE
| UARTCR2_TIE
| UARTCR2_RE
| UARTCR2_TE
);
2066 writeb(temp
, sport
->port
.membase
+ UARTCR2
);
2069 if (sport
->lpuart_dma_rx_use
) {
2070 if (sport
->port
.irq_wake
) {
2071 if (!lpuart_start_rx_dma(sport
)) {
2072 sport
->lpuart_dma_rx_use
= true;
2073 rx_dma_timer_init(sport
);
2075 sport
->lpuart_dma_rx_use
= false;
2080 if (sport
->dma_tx_chan
&& !lpuart_dma_tx_request(&sport
->port
)) {
2081 init_waitqueue_head(&sport
->dma_wait
);
2082 sport
->lpuart_dma_tx_use
= true;
2083 writeb(readb(sport
->port
.membase
+ UARTCR5
) |
2084 UARTCR5_TDMAS
, sport
->port
.membase
+ UARTCR5
);
2086 sport
->lpuart_dma_tx_use
= false;
2089 uart_resume_port(&lpuart_reg
, &sport
->port
);
2095 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops
, lpuart_suspend
, lpuart_resume
);
2097 static struct platform_driver lpuart_driver
= {
2098 .probe
= lpuart_probe
,
2099 .remove
= lpuart_remove
,
2101 .name
= "fsl-lpuart",
2102 .of_match_table
= lpuart_dt_ids
,
2103 .pm
= &lpuart_pm_ops
,
2107 static int __init
lpuart_serial_init(void)
2109 int ret
= uart_register_driver(&lpuart_reg
);
2114 ret
= platform_driver_register(&lpuart_driver
);
2116 uart_unregister_driver(&lpuart_reg
);
2121 static void __exit
lpuart_serial_exit(void)
2123 platform_driver_unregister(&lpuart_driver
);
2124 uart_unregister_driver(&lpuart_reg
);
2127 module_init(lpuart_serial_init
);
2128 module_exit(lpuart_serial_exit
);
2130 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2131 MODULE_LICENSE("GPL v2");