2 * Freescale lpuart serial port driver
4 * Copyright 2012-2014 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
16 #include <linux/clk.h>
17 #include <linux/console.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/dmaengine.h>
20 #include <linux/dmapool.h>
22 #include <linux/irq.h>
23 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/of_dma.h>
27 #include <linux/serial_core.h>
28 #include <linux/slab.h>
29 #include <linux/tty_flip.h>
31 /* All registers are 8-bit width */
41 #define UARTMODEM 0x0d
42 #define UARTPFIFO 0x10
43 #define UARTCFIFO 0x11
44 #define UARTSFIFO 0x12
45 #define UARTTWFIFO 0x13
46 #define UARTTCFIFO 0x14
47 #define UARTRWFIFO 0x15
49 #define UARTBDH_LBKDIE 0x80
50 #define UARTBDH_RXEDGIE 0x40
51 #define UARTBDH_SBR_MASK 0x1f
53 #define UARTCR1_LOOPS 0x80
54 #define UARTCR1_RSRC 0x20
55 #define UARTCR1_M 0x10
56 #define UARTCR1_WAKE 0x08
57 #define UARTCR1_ILT 0x04
58 #define UARTCR1_PE 0x02
59 #define UARTCR1_PT 0x01
61 #define UARTCR2_TIE 0x80
62 #define UARTCR2_TCIE 0x40
63 #define UARTCR2_RIE 0x20
64 #define UARTCR2_ILIE 0x10
65 #define UARTCR2_TE 0x08
66 #define UARTCR2_RE 0x04
67 #define UARTCR2_RWU 0x02
68 #define UARTCR2_SBK 0x01
70 #define UARTSR1_TDRE 0x80
71 #define UARTSR1_TC 0x40
72 #define UARTSR1_RDRF 0x20
73 #define UARTSR1_IDLE 0x10
74 #define UARTSR1_OR 0x08
75 #define UARTSR1_NF 0x04
76 #define UARTSR1_FE 0x02
77 #define UARTSR1_PE 0x01
79 #define UARTCR3_R8 0x80
80 #define UARTCR3_T8 0x40
81 #define UARTCR3_TXDIR 0x20
82 #define UARTCR3_TXINV 0x10
83 #define UARTCR3_ORIE 0x08
84 #define UARTCR3_NEIE 0x04
85 #define UARTCR3_FEIE 0x02
86 #define UARTCR3_PEIE 0x01
88 #define UARTCR4_MAEN1 0x80
89 #define UARTCR4_MAEN2 0x40
90 #define UARTCR4_M10 0x20
91 #define UARTCR4_BRFA_MASK 0x1f
92 #define UARTCR4_BRFA_OFF 0
94 #define UARTCR5_TDMAS 0x80
95 #define UARTCR5_RDMAS 0x20
97 #define UARTMODEM_RXRTSE 0x08
98 #define UARTMODEM_TXRTSPOL 0x04
99 #define UARTMODEM_TXRTSE 0x02
100 #define UARTMODEM_TXCTSE 0x01
102 #define UARTPFIFO_TXFE 0x80
103 #define UARTPFIFO_FIFOSIZE_MASK 0x7
104 #define UARTPFIFO_TXSIZE_OFF 4
105 #define UARTPFIFO_RXFE 0x08
106 #define UARTPFIFO_RXSIZE_OFF 0
108 #define UARTCFIFO_TXFLUSH 0x80
109 #define UARTCFIFO_RXFLUSH 0x40
110 #define UARTCFIFO_RXOFE 0x04
111 #define UARTCFIFO_TXOFE 0x02
112 #define UARTCFIFO_RXUFE 0x01
114 #define UARTSFIFO_TXEMPT 0x80
115 #define UARTSFIFO_RXEMPT 0x40
116 #define UARTSFIFO_RXOF 0x04
117 #define UARTSFIFO_TXOF 0x02
118 #define UARTSFIFO_RXUF 0x01
120 /* 32-bit register definition */
121 #define UARTBAUD 0x00
122 #define UARTSTAT 0x04
123 #define UARTCTRL 0x08
124 #define UARTDATA 0x0C
125 #define UARTMATCH 0x10
126 #define UARTMODIR 0x14
127 #define UARTFIFO 0x18
128 #define UARTWATER 0x1c
130 #define UARTBAUD_MAEN1 0x80000000
131 #define UARTBAUD_MAEN2 0x40000000
132 #define UARTBAUD_M10 0x20000000
133 #define UARTBAUD_TDMAE 0x00800000
134 #define UARTBAUD_RDMAE 0x00200000
135 #define UARTBAUD_MATCFG 0x00400000
136 #define UARTBAUD_BOTHEDGE 0x00020000
137 #define UARTBAUD_RESYNCDIS 0x00010000
138 #define UARTBAUD_LBKDIE 0x00008000
139 #define UARTBAUD_RXEDGIE 0x00004000
140 #define UARTBAUD_SBNS 0x00002000
141 #define UARTBAUD_SBR 0x00000000
142 #define UARTBAUD_SBR_MASK 0x1fff
143 #define UARTBAUD_OSR_MASK 0x1f
144 #define UARTBAUD_OSR_SHIFT 24
146 #define UARTSTAT_LBKDIF 0x80000000
147 #define UARTSTAT_RXEDGIF 0x40000000
148 #define UARTSTAT_MSBF 0x20000000
149 #define UARTSTAT_RXINV 0x10000000
150 #define UARTSTAT_RWUID 0x08000000
151 #define UARTSTAT_BRK13 0x04000000
152 #define UARTSTAT_LBKDE 0x02000000
153 #define UARTSTAT_RAF 0x01000000
154 #define UARTSTAT_TDRE 0x00800000
155 #define UARTSTAT_TC 0x00400000
156 #define UARTSTAT_RDRF 0x00200000
157 #define UARTSTAT_IDLE 0x00100000
158 #define UARTSTAT_OR 0x00080000
159 #define UARTSTAT_NF 0x00040000
160 #define UARTSTAT_FE 0x00020000
161 #define UARTSTAT_PE 0x00010000
162 #define UARTSTAT_MA1F 0x00008000
163 #define UARTSTAT_M21F 0x00004000
165 #define UARTCTRL_R8T9 0x80000000
166 #define UARTCTRL_R9T8 0x40000000
167 #define UARTCTRL_TXDIR 0x20000000
168 #define UARTCTRL_TXINV 0x10000000
169 #define UARTCTRL_ORIE 0x08000000
170 #define UARTCTRL_NEIE 0x04000000
171 #define UARTCTRL_FEIE 0x02000000
172 #define UARTCTRL_PEIE 0x01000000
173 #define UARTCTRL_TIE 0x00800000
174 #define UARTCTRL_TCIE 0x00400000
175 #define UARTCTRL_RIE 0x00200000
176 #define UARTCTRL_ILIE 0x00100000
177 #define UARTCTRL_TE 0x00080000
178 #define UARTCTRL_RE 0x00040000
179 #define UARTCTRL_RWU 0x00020000
180 #define UARTCTRL_SBK 0x00010000
181 #define UARTCTRL_MA1IE 0x00008000
182 #define UARTCTRL_MA2IE 0x00004000
183 #define UARTCTRL_IDLECFG 0x00000100
184 #define UARTCTRL_LOOPS 0x00000080
185 #define UARTCTRL_DOZEEN 0x00000040
186 #define UARTCTRL_RSRC 0x00000020
187 #define UARTCTRL_M 0x00000010
188 #define UARTCTRL_WAKE 0x00000008
189 #define UARTCTRL_ILT 0x00000004
190 #define UARTCTRL_PE 0x00000002
191 #define UARTCTRL_PT 0x00000001
193 #define UARTDATA_NOISY 0x00008000
194 #define UARTDATA_PARITYE 0x00004000
195 #define UARTDATA_FRETSC 0x00002000
196 #define UARTDATA_RXEMPT 0x00001000
197 #define UARTDATA_IDLINE 0x00000800
198 #define UARTDATA_MASK 0x3ff
200 #define UARTMODIR_IREN 0x00020000
201 #define UARTMODIR_TXCTSSRC 0x00000020
202 #define UARTMODIR_TXCTSC 0x00000010
203 #define UARTMODIR_RXRTSE 0x00000008
204 #define UARTMODIR_TXRTSPOL 0x00000004
205 #define UARTMODIR_TXRTSE 0x00000002
206 #define UARTMODIR_TXCTSE 0x00000001
208 #define UARTFIFO_TXEMPT 0x00800000
209 #define UARTFIFO_RXEMPT 0x00400000
210 #define UARTFIFO_TXOF 0x00020000
211 #define UARTFIFO_RXUF 0x00010000
212 #define UARTFIFO_TXFLUSH 0x00008000
213 #define UARTFIFO_RXFLUSH 0x00004000
214 #define UARTFIFO_TXOFE 0x00000200
215 #define UARTFIFO_RXUFE 0x00000100
216 #define UARTFIFO_TXFE 0x00000080
217 #define UARTFIFO_FIFOSIZE_MASK 0x7
218 #define UARTFIFO_TXSIZE_OFF 4
219 #define UARTFIFO_RXFE 0x00000008
220 #define UARTFIFO_RXSIZE_OFF 0
222 #define UARTWATER_COUNT_MASK 0xff
223 #define UARTWATER_TXCNT_OFF 8
224 #define UARTWATER_RXCNT_OFF 24
225 #define UARTWATER_WATER_MASK 0xff
226 #define UARTWATER_TXWATER_OFF 0
227 #define UARTWATER_RXWATER_OFF 16
229 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
230 #define DMA_RX_TIMEOUT (10)
232 #define DRIVER_NAME "fsl-lpuart"
233 #define DEV_NAME "ttyLP"
236 /* IMX lpuart has four extra unused regs located at the beginning */
237 #define IMX_REG_OFF 0x10
240 struct uart_port port
;
242 unsigned int txfifo_size
;
243 unsigned int rxfifo_size
;
245 bool lpuart_dma_tx_use
;
246 bool lpuart_dma_rx_use
;
247 struct dma_chan
*dma_tx_chan
;
248 struct dma_chan
*dma_rx_chan
;
249 struct dma_async_tx_descriptor
*dma_tx_desc
;
250 struct dma_async_tx_descriptor
*dma_rx_desc
;
251 dma_cookie_t dma_tx_cookie
;
252 dma_cookie_t dma_rx_cookie
;
253 unsigned int dma_tx_bytes
;
254 unsigned int dma_rx_bytes
;
255 bool dma_tx_in_progress
;
256 unsigned int dma_rx_timeout
;
257 struct timer_list lpuart_timer
;
258 struct scatterlist rx_sgl
, tx_sgl
[2];
259 struct circ_buf rx_ring
;
260 int rx_dma_rng_buf_len
;
261 unsigned int dma_tx_nents
;
262 wait_queue_head_t dma_wait
;
265 struct lpuart_soc_data
{
270 static const struct lpuart_soc_data vf_data
= {
274 static const struct lpuart_soc_data ls_data
= {
275 .iotype
= UPIO_MEM32BE
,
278 static struct lpuart_soc_data imx_data
= {
279 .iotype
= UPIO_MEM32
,
280 .reg_off
= IMX_REG_OFF
,
283 static const struct of_device_id lpuart_dt_ids
[] = {
284 { .compatible
= "fsl,vf610-lpuart", .data
= &vf_data
, },
285 { .compatible
= "fsl,ls1021a-lpuart", .data
= &ls_data
, },
286 { .compatible
= "fsl,imx7ulp-lpuart", .data
= &imx_data
, },
289 MODULE_DEVICE_TABLE(of
, lpuart_dt_ids
);
291 /* Forward declare this for the dma callbacks*/
292 static void lpuart_dma_tx_complete(void *arg
);
294 static inline u32
lpuart32_read(struct uart_port
*port
, u32 off
)
296 switch (port
->iotype
) {
298 return readl(port
->membase
+ off
);
300 return ioread32be(port
->membase
+ off
);
306 static inline void lpuart32_write(struct uart_port
*port
, u32 val
,
309 switch (port
->iotype
) {
311 writel(val
, port
->membase
+ off
);
314 iowrite32be(val
, port
->membase
+ off
);
319 static void lpuart_stop_tx(struct uart_port
*port
)
323 temp
= readb(port
->membase
+ UARTCR2
);
324 temp
&= ~(UARTCR2_TIE
| UARTCR2_TCIE
);
325 writeb(temp
, port
->membase
+ UARTCR2
);
328 static void lpuart32_stop_tx(struct uart_port
*port
)
332 temp
= lpuart32_read(port
, UARTCTRL
);
333 temp
&= ~(UARTCTRL_TIE
| UARTCTRL_TCIE
);
334 lpuart32_write(port
, temp
, UARTCTRL
);
337 static void lpuart_stop_rx(struct uart_port
*port
)
341 temp
= readb(port
->membase
+ UARTCR2
);
342 writeb(temp
& ~UARTCR2_RE
, port
->membase
+ UARTCR2
);
345 static void lpuart32_stop_rx(struct uart_port
*port
)
349 temp
= lpuart32_read(port
, UARTCTRL
);
350 lpuart32_write(port
, temp
& ~UARTCTRL_RE
, UARTCTRL
);
353 static void lpuart_dma_tx(struct lpuart_port
*sport
)
355 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
356 struct scatterlist
*sgl
= sport
->tx_sgl
;
357 struct device
*dev
= sport
->port
.dev
;
360 if (sport
->dma_tx_in_progress
)
363 sport
->dma_tx_bytes
= uart_circ_chars_pending(xmit
);
365 if (xmit
->tail
< xmit
->head
|| xmit
->head
== 0) {
366 sport
->dma_tx_nents
= 1;
367 sg_init_one(sgl
, xmit
->buf
+ xmit
->tail
, sport
->dma_tx_bytes
);
369 sport
->dma_tx_nents
= 2;
370 sg_init_table(sgl
, 2);
371 sg_set_buf(sgl
, xmit
->buf
+ xmit
->tail
,
372 UART_XMIT_SIZE
- xmit
->tail
);
373 sg_set_buf(sgl
+ 1, xmit
->buf
, xmit
->head
);
376 ret
= dma_map_sg(dev
, sgl
, sport
->dma_tx_nents
, DMA_TO_DEVICE
);
378 dev_err(dev
, "DMA mapping error for TX.\n");
382 sport
->dma_tx_desc
= dmaengine_prep_slave_sg(sport
->dma_tx_chan
, sgl
,
384 DMA_MEM_TO_DEV
, DMA_PREP_INTERRUPT
);
385 if (!sport
->dma_tx_desc
) {
386 dma_unmap_sg(dev
, sgl
, sport
->dma_tx_nents
, DMA_TO_DEVICE
);
387 dev_err(dev
, "Cannot prepare TX slave DMA!\n");
391 sport
->dma_tx_desc
->callback
= lpuart_dma_tx_complete
;
392 sport
->dma_tx_desc
->callback_param
= sport
;
393 sport
->dma_tx_in_progress
= true;
394 sport
->dma_tx_cookie
= dmaengine_submit(sport
->dma_tx_desc
);
395 dma_async_issue_pending(sport
->dma_tx_chan
);
398 static void lpuart_dma_tx_complete(void *arg
)
400 struct lpuart_port
*sport
= arg
;
401 struct scatterlist
*sgl
= &sport
->tx_sgl
[0];
402 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
405 spin_lock_irqsave(&sport
->port
.lock
, flags
);
407 dma_unmap_sg(sport
->port
.dev
, sgl
, sport
->dma_tx_nents
, DMA_TO_DEVICE
);
409 xmit
->tail
= (xmit
->tail
+ sport
->dma_tx_bytes
) & (UART_XMIT_SIZE
- 1);
411 sport
->port
.icount
.tx
+= sport
->dma_tx_bytes
;
412 sport
->dma_tx_in_progress
= false;
413 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
415 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
416 uart_write_wakeup(&sport
->port
);
418 if (waitqueue_active(&sport
->dma_wait
)) {
419 wake_up(&sport
->dma_wait
);
423 spin_lock_irqsave(&sport
->port
.lock
, flags
);
425 if (!uart_circ_empty(xmit
) && !uart_tx_stopped(&sport
->port
))
426 lpuart_dma_tx(sport
);
428 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
431 static int lpuart_dma_tx_request(struct uart_port
*port
)
433 struct lpuart_port
*sport
= container_of(port
,
434 struct lpuart_port
, port
);
435 struct dma_slave_config dma_tx_sconfig
= {};
438 dma_tx_sconfig
.dst_addr
= sport
->port
.mapbase
+ UARTDR
;
439 dma_tx_sconfig
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
440 dma_tx_sconfig
.dst_maxburst
= 1;
441 dma_tx_sconfig
.direction
= DMA_MEM_TO_DEV
;
442 ret
= dmaengine_slave_config(sport
->dma_tx_chan
, &dma_tx_sconfig
);
445 dev_err(sport
->port
.dev
,
446 "DMA slave config failed, err = %d\n", ret
);
453 static void lpuart_flush_buffer(struct uart_port
*port
)
455 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
457 if (sport
->lpuart_dma_tx_use
) {
458 if (sport
->dma_tx_in_progress
) {
459 dma_unmap_sg(sport
->port
.dev
, &sport
->tx_sgl
[0],
460 sport
->dma_tx_nents
, DMA_TO_DEVICE
);
461 sport
->dma_tx_in_progress
= false;
463 dmaengine_terminate_all(sport
->dma_tx_chan
);
467 #if defined(CONFIG_CONSOLE_POLL)
469 static int lpuart_poll_init(struct uart_port
*port
)
471 struct lpuart_port
*sport
= container_of(port
,
472 struct lpuart_port
, port
);
476 sport
->port
.fifosize
= 0;
478 spin_lock_irqsave(&sport
->port
.lock
, flags
);
479 /* Disable Rx & Tx */
480 writeb(0, sport
->port
.membase
+ UARTCR2
);
482 temp
= readb(sport
->port
.membase
+ UARTPFIFO
);
483 /* Enable Rx and Tx FIFO */
484 writeb(temp
| UARTPFIFO_RXFE
| UARTPFIFO_TXFE
,
485 sport
->port
.membase
+ UARTPFIFO
);
487 /* flush Tx and Rx FIFO */
488 writeb(UARTCFIFO_TXFLUSH
| UARTCFIFO_RXFLUSH
,
489 sport
->port
.membase
+ UARTCFIFO
);
491 /* explicitly clear RDRF */
492 if (readb(sport
->port
.membase
+ UARTSR1
) & UARTSR1_RDRF
) {
493 readb(sport
->port
.membase
+ UARTDR
);
494 writeb(UARTSFIFO_RXUF
, sport
->port
.membase
+ UARTSFIFO
);
497 writeb(0, sport
->port
.membase
+ UARTTWFIFO
);
498 writeb(1, sport
->port
.membase
+ UARTRWFIFO
);
500 /* Enable Rx and Tx */
501 writeb(UARTCR2_RE
| UARTCR2_TE
, sport
->port
.membase
+ UARTCR2
);
502 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
507 static void lpuart_poll_put_char(struct uart_port
*port
, unsigned char c
)
510 while (!(readb(port
->membase
+ UARTSR1
) & UARTSR1_TDRE
))
513 writeb(c
, port
->membase
+ UARTDR
);
516 static int lpuart_poll_get_char(struct uart_port
*port
)
518 if (!(readb(port
->membase
+ UARTSR1
) & UARTSR1_RDRF
))
521 return readb(port
->membase
+ UARTDR
);
524 static int lpuart32_poll_init(struct uart_port
*port
)
527 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
530 sport
->port
.fifosize
= 0;
532 spin_lock_irqsave(&sport
->port
.lock
, flags
);
534 /* Disable Rx & Tx */
535 writel(0, sport
->port
.membase
+ UARTCTRL
);
537 temp
= readl(sport
->port
.membase
+ UARTFIFO
);
539 /* Enable Rx and Tx FIFO */
540 writel(temp
| UARTFIFO_RXFE
| UARTFIFO_TXFE
,
541 sport
->port
.membase
+ UARTFIFO
);
543 /* flush Tx and Rx FIFO */
544 writel(UARTFIFO_TXFLUSH
| UARTFIFO_RXFLUSH
,
545 sport
->port
.membase
+ UARTFIFO
);
547 /* explicitly clear RDRF */
548 if (readl(sport
->port
.membase
+ UARTSTAT
) & UARTSTAT_RDRF
) {
549 readl(sport
->port
.membase
+ UARTDATA
);
550 writel(UARTFIFO_RXUF
, sport
->port
.membase
+ UARTFIFO
);
553 /* Enable Rx and Tx */
554 writel(UARTCTRL_RE
| UARTCTRL_TE
, sport
->port
.membase
+ UARTCTRL
);
555 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
560 static void lpuart32_poll_put_char(struct uart_port
*port
, unsigned char c
)
562 while (!(readl(port
->membase
+ UARTSTAT
) & UARTSTAT_TDRE
))
565 writel(c
, port
->membase
+ UARTDATA
);
568 static int lpuart32_poll_get_char(struct uart_port
*port
)
570 if (!(readl(port
->membase
+ UARTSTAT
) & UARTSTAT_RDRF
))
573 return readl(port
->membase
+ UARTDATA
);
577 static inline void lpuart_transmit_buffer(struct lpuart_port
*sport
)
579 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
581 while (!uart_circ_empty(xmit
) &&
582 (readb(sport
->port
.membase
+ UARTTCFIFO
) < sport
->txfifo_size
)) {
583 writeb(xmit
->buf
[xmit
->tail
], sport
->port
.membase
+ UARTDR
);
584 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
585 sport
->port
.icount
.tx
++;
588 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
589 uart_write_wakeup(&sport
->port
);
591 if (uart_circ_empty(xmit
))
592 lpuart_stop_tx(&sport
->port
);
595 static inline void lpuart32_transmit_buffer(struct lpuart_port
*sport
)
597 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
600 txcnt
= lpuart32_read(&sport
->port
, UARTWATER
);
601 txcnt
= txcnt
>> UARTWATER_TXCNT_OFF
;
602 txcnt
&= UARTWATER_COUNT_MASK
;
603 while (!uart_circ_empty(xmit
) && (txcnt
< sport
->txfifo_size
)) {
604 lpuart32_write(&sport
->port
, xmit
->buf
[xmit
->tail
], UARTDATA
);
605 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
606 sport
->port
.icount
.tx
++;
607 txcnt
= lpuart32_read(&sport
->port
, UARTWATER
);
608 txcnt
= txcnt
>> UARTWATER_TXCNT_OFF
;
609 txcnt
&= UARTWATER_COUNT_MASK
;
612 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
613 uart_write_wakeup(&sport
->port
);
615 if (uart_circ_empty(xmit
))
616 lpuart32_stop_tx(&sport
->port
);
619 static void lpuart_start_tx(struct uart_port
*port
)
621 struct lpuart_port
*sport
= container_of(port
,
622 struct lpuart_port
, port
);
623 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
626 temp
= readb(port
->membase
+ UARTCR2
);
627 writeb(temp
| UARTCR2_TIE
, port
->membase
+ UARTCR2
);
629 if (sport
->lpuart_dma_tx_use
) {
630 if (!uart_circ_empty(xmit
) && !uart_tx_stopped(port
))
631 lpuart_dma_tx(sport
);
633 if (readb(port
->membase
+ UARTSR1
) & UARTSR1_TDRE
)
634 lpuart_transmit_buffer(sport
);
638 static void lpuart32_start_tx(struct uart_port
*port
)
640 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
643 temp
= lpuart32_read(port
, UARTCTRL
);
644 lpuart32_write(port
, temp
| UARTCTRL_TIE
, UARTCTRL
);
646 if (lpuart32_read(port
, UARTSTAT
) & UARTSTAT_TDRE
)
647 lpuart32_transmit_buffer(sport
);
650 /* return TIOCSER_TEMT when transmitter is not busy */
651 static unsigned int lpuart_tx_empty(struct uart_port
*port
)
653 struct lpuart_port
*sport
= container_of(port
,
654 struct lpuart_port
, port
);
655 unsigned char sr1
= readb(port
->membase
+ UARTSR1
);
656 unsigned char sfifo
= readb(port
->membase
+ UARTSFIFO
);
658 if (sport
->dma_tx_in_progress
)
661 if (sr1
& UARTSR1_TC
&& sfifo
& UARTSFIFO_TXEMPT
)
667 static unsigned int lpuart32_tx_empty(struct uart_port
*port
)
669 return (lpuart32_read(port
, UARTSTAT
) & UARTSTAT_TC
) ?
673 static bool lpuart_is_32(struct lpuart_port
*sport
)
675 return sport
->port
.iotype
== UPIO_MEM32
||
676 sport
->port
.iotype
== UPIO_MEM32BE
;
679 static irqreturn_t
lpuart_txint(int irq
, void *dev_id
)
681 struct lpuart_port
*sport
= dev_id
;
682 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
685 spin_lock_irqsave(&sport
->port
.lock
, flags
);
686 if (sport
->port
.x_char
) {
687 if (lpuart_is_32(sport
))
688 lpuart32_write(&sport
->port
, sport
->port
.x_char
, UARTDATA
);
690 writeb(sport
->port
.x_char
, sport
->port
.membase
+ UARTDR
);
694 if (uart_circ_empty(xmit
) || uart_tx_stopped(&sport
->port
)) {
695 if (lpuart_is_32(sport
))
696 lpuart32_stop_tx(&sport
->port
);
698 lpuart_stop_tx(&sport
->port
);
702 if (lpuart_is_32(sport
))
703 lpuart32_transmit_buffer(sport
);
705 lpuart_transmit_buffer(sport
);
707 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
708 uart_write_wakeup(&sport
->port
);
711 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
715 static irqreturn_t
lpuart_rxint(int irq
, void *dev_id
)
717 struct lpuart_port
*sport
= dev_id
;
718 unsigned int flg
, ignored
= 0;
719 struct tty_port
*port
= &sport
->port
.state
->port
;
721 unsigned char rx
, sr
;
723 spin_lock_irqsave(&sport
->port
.lock
, flags
);
725 while (!(readb(sport
->port
.membase
+ UARTSFIFO
) & UARTSFIFO_RXEMPT
)) {
727 sport
->port
.icount
.rx
++;
729 * to clear the FE, OR, NF, FE, PE flags,
730 * read SR1 then read DR
732 sr
= readb(sport
->port
.membase
+ UARTSR1
);
733 rx
= readb(sport
->port
.membase
+ UARTDR
);
735 if (uart_handle_sysrq_char(&sport
->port
, (unsigned char)rx
))
738 if (sr
& (UARTSR1_PE
| UARTSR1_OR
| UARTSR1_FE
)) {
740 sport
->port
.icount
.parity
++;
741 else if (sr
& UARTSR1_FE
)
742 sport
->port
.icount
.frame
++;
745 sport
->port
.icount
.overrun
++;
747 if (sr
& sport
->port
.ignore_status_mask
) {
753 sr
&= sport
->port
.read_status_mask
;
757 else if (sr
& UARTSR1_FE
)
764 sport
->port
.sysrq
= 0;
768 tty_insert_flip_char(port
, rx
, flg
);
772 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
774 tty_flip_buffer_push(port
);
778 static irqreturn_t
lpuart32_rxint(int irq
, void *dev_id
)
780 struct lpuart_port
*sport
= dev_id
;
781 unsigned int flg
, ignored
= 0;
782 struct tty_port
*port
= &sport
->port
.state
->port
;
784 unsigned long rx
, sr
;
786 spin_lock_irqsave(&sport
->port
.lock
, flags
);
788 while (!(lpuart32_read(&sport
->port
, UARTFIFO
) & UARTFIFO_RXEMPT
)) {
790 sport
->port
.icount
.rx
++;
792 * to clear the FE, OR, NF, FE, PE flags,
793 * read STAT then read DATA reg
795 sr
= lpuart32_read(&sport
->port
, UARTSTAT
);
796 rx
= lpuart32_read(&sport
->port
, UARTDATA
);
799 if (uart_handle_sysrq_char(&sport
->port
, (unsigned char)rx
))
802 if (sr
& (UARTSTAT_PE
| UARTSTAT_OR
| UARTSTAT_FE
)) {
803 if (sr
& UARTSTAT_PE
)
804 sport
->port
.icount
.parity
++;
805 else if (sr
& UARTSTAT_FE
)
806 sport
->port
.icount
.frame
++;
808 if (sr
& UARTSTAT_OR
)
809 sport
->port
.icount
.overrun
++;
811 if (sr
& sport
->port
.ignore_status_mask
) {
817 sr
&= sport
->port
.read_status_mask
;
819 if (sr
& UARTSTAT_PE
)
821 else if (sr
& UARTSTAT_FE
)
824 if (sr
& UARTSTAT_OR
)
828 sport
->port
.sysrq
= 0;
832 tty_insert_flip_char(port
, rx
, flg
);
836 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
838 tty_flip_buffer_push(port
);
842 static irqreturn_t
lpuart_int(int irq
, void *dev_id
)
844 struct lpuart_port
*sport
= dev_id
;
847 sts
= readb(sport
->port
.membase
+ UARTSR1
);
849 if (sts
& UARTSR1_RDRF
)
850 lpuart_rxint(irq
, dev_id
);
852 if (sts
& UARTSR1_TDRE
)
853 lpuart_txint(irq
, dev_id
);
858 static irqreturn_t
lpuart32_int(int irq
, void *dev_id
)
860 struct lpuart_port
*sport
= dev_id
;
861 unsigned long sts
, rxcount
;
863 sts
= lpuart32_read(&sport
->port
, UARTSTAT
);
864 rxcount
= lpuart32_read(&sport
->port
, UARTWATER
);
865 rxcount
= rxcount
>> UARTWATER_RXCNT_OFF
;
867 if (sts
& UARTSTAT_RDRF
|| rxcount
> 0)
868 lpuart32_rxint(irq
, dev_id
);
870 if ((sts
& UARTSTAT_TDRE
) &&
871 !(lpuart32_read(&sport
->port
, UARTBAUD
) & UARTBAUD_TDMAE
))
872 lpuart_txint(irq
, dev_id
);
874 lpuart32_write(&sport
->port
, sts
, UARTSTAT
);
878 static void lpuart_copy_rx_to_tty(struct lpuart_port
*sport
)
880 struct tty_port
*port
= &sport
->port
.state
->port
;
881 struct dma_tx_state state
;
882 enum dma_status dmastat
;
883 struct circ_buf
*ring
= &sport
->rx_ring
;
888 sr
= readb(sport
->port
.membase
+ UARTSR1
);
890 if (sr
& (UARTSR1_PE
| UARTSR1_FE
)) {
891 /* Read DR to clear the error flags */
892 readb(sport
->port
.membase
+ UARTDR
);
895 sport
->port
.icount
.parity
++;
896 else if (sr
& UARTSR1_FE
)
897 sport
->port
.icount
.frame
++;
900 async_tx_ack(sport
->dma_rx_desc
);
902 spin_lock_irqsave(&sport
->port
.lock
, flags
);
904 dmastat
= dmaengine_tx_status(sport
->dma_rx_chan
,
905 sport
->dma_rx_cookie
,
908 if (dmastat
== DMA_ERROR
) {
909 dev_err(sport
->port
.dev
, "Rx DMA transfer failed!\n");
910 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
914 /* CPU claims ownership of RX DMA buffer */
915 dma_sync_sg_for_cpu(sport
->port
.dev
, &sport
->rx_sgl
, 1, DMA_FROM_DEVICE
);
918 * ring->head points to the end of data already written by the DMA.
919 * ring->tail points to the beginning of data to be read by the
921 * The current transfer size should not be larger than the dma buffer
924 ring
->head
= sport
->rx_sgl
.length
- state
.residue
;
925 BUG_ON(ring
->head
> sport
->rx_sgl
.length
);
927 * At this point ring->head may point to the first byte right after the
928 * last byte of the dma buffer:
929 * 0 <= ring->head <= sport->rx_sgl.length
931 * However ring->tail must always points inside the dma buffer:
932 * 0 <= ring->tail <= sport->rx_sgl.length - 1
934 * Since we use a ring buffer, we have to handle the case
935 * where head is lower than tail. In such a case, we first read from
936 * tail to the end of the buffer then reset tail.
938 if (ring
->head
< ring
->tail
) {
939 count
= sport
->rx_sgl
.length
- ring
->tail
;
941 tty_insert_flip_string(port
, ring
->buf
+ ring
->tail
, count
);
943 sport
->port
.icount
.rx
+= count
;
946 /* Finally we read data from tail to head */
947 if (ring
->tail
< ring
->head
) {
948 count
= ring
->head
- ring
->tail
;
949 tty_insert_flip_string(port
, ring
->buf
+ ring
->tail
, count
);
950 /* Wrap ring->head if needed */
951 if (ring
->head
>= sport
->rx_sgl
.length
)
953 ring
->tail
= ring
->head
;
954 sport
->port
.icount
.rx
+= count
;
957 dma_sync_sg_for_device(sport
->port
.dev
, &sport
->rx_sgl
, 1,
960 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
962 tty_flip_buffer_push(port
);
963 mod_timer(&sport
->lpuart_timer
, jiffies
+ sport
->dma_rx_timeout
);
966 static void lpuart_dma_rx_complete(void *arg
)
968 struct lpuart_port
*sport
= arg
;
970 lpuart_copy_rx_to_tty(sport
);
973 static void lpuart_timer_func(unsigned long data
)
975 struct lpuart_port
*sport
= (struct lpuart_port
*)data
;
977 lpuart_copy_rx_to_tty(sport
);
980 static inline int lpuart_start_rx_dma(struct lpuart_port
*sport
)
982 struct dma_slave_config dma_rx_sconfig
= {};
983 struct circ_buf
*ring
= &sport
->rx_ring
;
986 struct tty_struct
*tty
= tty_port_tty_get(&sport
->port
.state
->port
);
987 struct ktermios
*termios
= &tty
->termios
;
989 baud
= tty_get_baud_rate(tty
);
991 bits
= (termios
->c_cflag
& CSIZE
) == CS7
? 9 : 10;
992 if (termios
->c_cflag
& PARENB
)
996 * Calculate length of one DMA buffer size to keep latency below
997 * 10ms at any baud rate.
999 sport
->rx_dma_rng_buf_len
= (DMA_RX_TIMEOUT
* baud
/ bits
/ 1000) * 2;
1000 sport
->rx_dma_rng_buf_len
= (1 << (fls(sport
->rx_dma_rng_buf_len
) - 1));
1001 if (sport
->rx_dma_rng_buf_len
< 16)
1002 sport
->rx_dma_rng_buf_len
= 16;
1004 ring
->buf
= kmalloc(sport
->rx_dma_rng_buf_len
, GFP_ATOMIC
);
1006 dev_err(sport
->port
.dev
, "Ring buf alloc failed\n");
1010 sg_init_one(&sport
->rx_sgl
, ring
->buf
, sport
->rx_dma_rng_buf_len
);
1011 sg_set_buf(&sport
->rx_sgl
, ring
->buf
, sport
->rx_dma_rng_buf_len
);
1012 nent
= dma_map_sg(sport
->port
.dev
, &sport
->rx_sgl
, 1, DMA_FROM_DEVICE
);
1015 dev_err(sport
->port
.dev
, "DMA Rx mapping error\n");
1019 dma_rx_sconfig
.src_addr
= sport
->port
.mapbase
+ UARTDR
;
1020 dma_rx_sconfig
.src_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
1021 dma_rx_sconfig
.src_maxburst
= 1;
1022 dma_rx_sconfig
.direction
= DMA_DEV_TO_MEM
;
1023 ret
= dmaengine_slave_config(sport
->dma_rx_chan
, &dma_rx_sconfig
);
1026 dev_err(sport
->port
.dev
,
1027 "DMA Rx slave config failed, err = %d\n", ret
);
1031 sport
->dma_rx_desc
= dmaengine_prep_dma_cyclic(sport
->dma_rx_chan
,
1032 sg_dma_address(&sport
->rx_sgl
),
1033 sport
->rx_sgl
.length
,
1034 sport
->rx_sgl
.length
/ 2,
1036 DMA_PREP_INTERRUPT
);
1037 if (!sport
->dma_rx_desc
) {
1038 dev_err(sport
->port
.dev
, "Cannot prepare cyclic DMA\n");
1042 sport
->dma_rx_desc
->callback
= lpuart_dma_rx_complete
;
1043 sport
->dma_rx_desc
->callback_param
= sport
;
1044 sport
->dma_rx_cookie
= dmaengine_submit(sport
->dma_rx_desc
);
1045 dma_async_issue_pending(sport
->dma_rx_chan
);
1047 writeb(readb(sport
->port
.membase
+ UARTCR5
) | UARTCR5_RDMAS
,
1048 sport
->port
.membase
+ UARTCR5
);
1053 static void lpuart_dma_rx_free(struct uart_port
*port
)
1055 struct lpuart_port
*sport
= container_of(port
,
1056 struct lpuart_port
, port
);
1058 if (sport
->dma_rx_chan
)
1059 dmaengine_terminate_all(sport
->dma_rx_chan
);
1061 dma_unmap_sg(sport
->port
.dev
, &sport
->rx_sgl
, 1, DMA_FROM_DEVICE
);
1062 kfree(sport
->rx_ring
.buf
);
1063 sport
->rx_ring
.tail
= 0;
1064 sport
->rx_ring
.head
= 0;
1065 sport
->dma_rx_desc
= NULL
;
1066 sport
->dma_rx_cookie
= -EINVAL
;
1069 static int lpuart_config_rs485(struct uart_port
*port
,
1070 struct serial_rs485
*rs485
)
1072 struct lpuart_port
*sport
= container_of(port
,
1073 struct lpuart_port
, port
);
1075 u8 modem
= readb(sport
->port
.membase
+ UARTMODEM
) &
1076 ~(UARTMODEM_TXRTSPOL
| UARTMODEM_TXRTSE
);
1077 writeb(modem
, sport
->port
.membase
+ UARTMODEM
);
1079 /* clear unsupported configurations */
1080 rs485
->delay_rts_before_send
= 0;
1081 rs485
->delay_rts_after_send
= 0;
1082 rs485
->flags
&= ~SER_RS485_RX_DURING_TX
;
1084 if (rs485
->flags
& SER_RS485_ENABLED
) {
1085 /* Enable auto RS-485 RTS mode */
1086 modem
|= UARTMODEM_TXRTSE
;
1089 * RTS needs to be logic HIGH either during transer _or_ after
1090 * transfer, other variants are not supported by the hardware.
1093 if (!(rs485
->flags
& (SER_RS485_RTS_ON_SEND
|
1094 SER_RS485_RTS_AFTER_SEND
)))
1095 rs485
->flags
|= SER_RS485_RTS_ON_SEND
;
1097 if (rs485
->flags
& SER_RS485_RTS_ON_SEND
&&
1098 rs485
->flags
& SER_RS485_RTS_AFTER_SEND
)
1099 rs485
->flags
&= ~SER_RS485_RTS_AFTER_SEND
;
1102 * The hardware defaults to RTS logic HIGH while transfer.
1103 * Switch polarity in case RTS shall be logic HIGH
1105 * Note: UART is assumed to be active high.
1107 if (rs485
->flags
& SER_RS485_RTS_ON_SEND
)
1108 modem
&= ~UARTMODEM_TXRTSPOL
;
1109 else if (rs485
->flags
& SER_RS485_RTS_AFTER_SEND
)
1110 modem
|= UARTMODEM_TXRTSPOL
;
1113 /* Store the new configuration */
1114 sport
->port
.rs485
= *rs485
;
1116 writeb(modem
, sport
->port
.membase
+ UARTMODEM
);
1120 static unsigned int lpuart_get_mctrl(struct uart_port
*port
)
1122 unsigned int temp
= 0;
1125 reg
= readb(port
->membase
+ UARTMODEM
);
1126 if (reg
& UARTMODEM_TXCTSE
)
1129 if (reg
& UARTMODEM_RXRTSE
)
1135 static unsigned int lpuart32_get_mctrl(struct uart_port
*port
)
1137 unsigned int temp
= 0;
1140 reg
= lpuart32_read(port
, UARTMODIR
);
1141 if (reg
& UARTMODIR_TXCTSE
)
1144 if (reg
& UARTMODIR_RXRTSE
)
1150 static void lpuart_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
1153 struct lpuart_port
*sport
= container_of(port
,
1154 struct lpuart_port
, port
);
1156 /* Make sure RXRTSE bit is not set when RS485 is enabled */
1157 if (!(sport
->port
.rs485
.flags
& SER_RS485_ENABLED
)) {
1158 temp
= readb(sport
->port
.membase
+ UARTMODEM
) &
1159 ~(UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1161 if (mctrl
& TIOCM_RTS
)
1162 temp
|= UARTMODEM_RXRTSE
;
1164 if (mctrl
& TIOCM_CTS
)
1165 temp
|= UARTMODEM_TXCTSE
;
1167 writeb(temp
, port
->membase
+ UARTMODEM
);
1171 static void lpuart32_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
1175 temp
= lpuart32_read(port
, UARTMODIR
) &
1176 ~(UARTMODIR_RXRTSE
| UARTMODIR_TXCTSE
);
1178 if (mctrl
& TIOCM_RTS
)
1179 temp
|= UARTMODIR_RXRTSE
;
1181 if (mctrl
& TIOCM_CTS
)
1182 temp
|= UARTMODIR_TXCTSE
;
1184 lpuart32_write(port
, temp
, UARTMODIR
);
1187 static void lpuart_break_ctl(struct uart_port
*port
, int break_state
)
1191 temp
= readb(port
->membase
+ UARTCR2
) & ~UARTCR2_SBK
;
1193 if (break_state
!= 0)
1194 temp
|= UARTCR2_SBK
;
1196 writeb(temp
, port
->membase
+ UARTCR2
);
1199 static void lpuart32_break_ctl(struct uart_port
*port
, int break_state
)
1203 temp
= lpuart32_read(port
, UARTCTRL
) & ~UARTCTRL_SBK
;
1205 if (break_state
!= 0)
1206 temp
|= UARTCTRL_SBK
;
1208 lpuart32_write(port
, temp
, UARTCTRL
);
1211 static void lpuart_setup_watermark(struct lpuart_port
*sport
)
1213 unsigned char val
, cr2
;
1214 unsigned char cr2_saved
;
1216 cr2
= readb(sport
->port
.membase
+ UARTCR2
);
1218 cr2
&= ~(UARTCR2_TIE
| UARTCR2_TCIE
| UARTCR2_TE
|
1219 UARTCR2_RIE
| UARTCR2_RE
);
1220 writeb(cr2
, sport
->port
.membase
+ UARTCR2
);
1222 val
= readb(sport
->port
.membase
+ UARTPFIFO
);
1223 writeb(val
| UARTPFIFO_TXFE
| UARTPFIFO_RXFE
,
1224 sport
->port
.membase
+ UARTPFIFO
);
1226 /* flush Tx and Rx FIFO */
1227 writeb(UARTCFIFO_TXFLUSH
| UARTCFIFO_RXFLUSH
,
1228 sport
->port
.membase
+ UARTCFIFO
);
1230 /* explicitly clear RDRF */
1231 if (readb(sport
->port
.membase
+ UARTSR1
) & UARTSR1_RDRF
) {
1232 readb(sport
->port
.membase
+ UARTDR
);
1233 writeb(UARTSFIFO_RXUF
, sport
->port
.membase
+ UARTSFIFO
);
1236 writeb(0, sport
->port
.membase
+ UARTTWFIFO
);
1237 writeb(1, sport
->port
.membase
+ UARTRWFIFO
);
1240 writeb(cr2_saved
, sport
->port
.membase
+ UARTCR2
);
1243 static void lpuart32_setup_watermark(struct lpuart_port
*sport
)
1245 unsigned long val
, ctrl
;
1246 unsigned long ctrl_saved
;
1248 ctrl
= lpuart32_read(&sport
->port
, UARTCTRL
);
1250 ctrl
&= ~(UARTCTRL_TIE
| UARTCTRL_TCIE
| UARTCTRL_TE
|
1251 UARTCTRL_RIE
| UARTCTRL_RE
);
1252 lpuart32_write(&sport
->port
, ctrl
, UARTCTRL
);
1254 /* enable FIFO mode */
1255 val
= lpuart32_read(&sport
->port
, UARTFIFO
);
1256 val
|= UARTFIFO_TXFE
| UARTFIFO_RXFE
;
1257 val
|= UARTFIFO_TXFLUSH
| UARTFIFO_RXFLUSH
;
1258 lpuart32_write(&sport
->port
, val
, UARTFIFO
);
1260 /* set the watermark */
1261 val
= (0x1 << UARTWATER_RXWATER_OFF
) | (0x0 << UARTWATER_TXWATER_OFF
);
1262 lpuart32_write(&sport
->port
, val
, UARTWATER
);
1265 lpuart32_write(&sport
->port
, ctrl_saved
, UARTCTRL
);
1268 static void rx_dma_timer_init(struct lpuart_port
*sport
)
1270 setup_timer(&sport
->lpuart_timer
, lpuart_timer_func
,
1271 (unsigned long)sport
);
1272 sport
->lpuart_timer
.expires
= jiffies
+ sport
->dma_rx_timeout
;
1273 add_timer(&sport
->lpuart_timer
);
1276 static int lpuart_startup(struct uart_port
*port
)
1278 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1280 unsigned long flags
;
1283 /* determine FIFO size and enable FIFO mode */
1284 temp
= readb(sport
->port
.membase
+ UARTPFIFO
);
1286 sport
->txfifo_size
= 0x1 << (((temp
>> UARTPFIFO_TXSIZE_OFF
) &
1287 UARTPFIFO_FIFOSIZE_MASK
) + 1);
1289 sport
->port
.fifosize
= sport
->txfifo_size
;
1291 sport
->rxfifo_size
= 0x1 << (((temp
>> UARTPFIFO_RXSIZE_OFF
) &
1292 UARTPFIFO_FIFOSIZE_MASK
) + 1);
1294 ret
= devm_request_irq(port
->dev
, port
->irq
, lpuart_int
, 0,
1295 DRIVER_NAME
, sport
);
1299 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1301 lpuart_setup_watermark(sport
);
1303 temp
= readb(sport
->port
.membase
+ UARTCR2
);
1304 temp
|= (UARTCR2_RIE
| UARTCR2_TIE
| UARTCR2_RE
| UARTCR2_TE
);
1305 writeb(temp
, sport
->port
.membase
+ UARTCR2
);
1307 if (sport
->dma_rx_chan
&& !lpuart_start_rx_dma(sport
)) {
1308 /* set Rx DMA timeout */
1309 sport
->dma_rx_timeout
= msecs_to_jiffies(DMA_RX_TIMEOUT
);
1310 if (!sport
->dma_rx_timeout
)
1311 sport
->dma_rx_timeout
= 1;
1313 sport
->lpuart_dma_rx_use
= true;
1314 rx_dma_timer_init(sport
);
1316 sport
->lpuart_dma_rx_use
= false;
1319 if (sport
->dma_tx_chan
&& !lpuart_dma_tx_request(port
)) {
1320 init_waitqueue_head(&sport
->dma_wait
);
1321 sport
->lpuart_dma_tx_use
= true;
1322 temp
= readb(port
->membase
+ UARTCR5
);
1323 writeb(temp
| UARTCR5_TDMAS
, port
->membase
+ UARTCR5
);
1325 sport
->lpuart_dma_tx_use
= false;
1328 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1333 static int lpuart32_startup(struct uart_port
*port
)
1335 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1337 unsigned long flags
;
1340 /* determine FIFO size */
1341 temp
= lpuart32_read(&sport
->port
, UARTFIFO
);
1343 sport
->txfifo_size
= 0x1 << (((temp
>> UARTFIFO_TXSIZE_OFF
) &
1344 UARTFIFO_FIFOSIZE_MASK
) - 1);
1346 sport
->rxfifo_size
= 0x1 << (((temp
>> UARTFIFO_RXSIZE_OFF
) &
1347 UARTFIFO_FIFOSIZE_MASK
) - 1);
1349 ret
= devm_request_irq(port
->dev
, port
->irq
, lpuart32_int
, 0,
1350 DRIVER_NAME
, sport
);
1354 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1356 lpuart32_setup_watermark(sport
);
1358 temp
= lpuart32_read(&sport
->port
, UARTCTRL
);
1359 temp
|= (UARTCTRL_RIE
| UARTCTRL_TIE
| UARTCTRL_RE
| UARTCTRL_TE
);
1360 temp
|= UARTCTRL_ILIE
;
1361 lpuart32_write(&sport
->port
, temp
, UARTCTRL
);
1363 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1367 static void lpuart_shutdown(struct uart_port
*port
)
1369 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1371 unsigned long flags
;
1373 spin_lock_irqsave(&port
->lock
, flags
);
1375 /* disable Rx/Tx and interrupts */
1376 temp
= readb(port
->membase
+ UARTCR2
);
1377 temp
&= ~(UARTCR2_TE
| UARTCR2_RE
|
1378 UARTCR2_TIE
| UARTCR2_TCIE
| UARTCR2_RIE
);
1379 writeb(temp
, port
->membase
+ UARTCR2
);
1381 spin_unlock_irqrestore(&port
->lock
, flags
);
1383 devm_free_irq(port
->dev
, port
->irq
, sport
);
1385 if (sport
->lpuart_dma_rx_use
) {
1386 del_timer_sync(&sport
->lpuart_timer
);
1387 lpuart_dma_rx_free(&sport
->port
);
1390 if (sport
->lpuart_dma_tx_use
) {
1391 if (wait_event_interruptible(sport
->dma_wait
,
1392 !sport
->dma_tx_in_progress
) != false) {
1393 sport
->dma_tx_in_progress
= false;
1394 dmaengine_terminate_all(sport
->dma_tx_chan
);
1397 lpuart_stop_tx(port
);
1401 static void lpuart32_shutdown(struct uart_port
*port
)
1403 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1405 unsigned long flags
;
1407 spin_lock_irqsave(&port
->lock
, flags
);
1409 /* disable Rx/Tx and interrupts */
1410 temp
= lpuart32_read(port
, UARTCTRL
);
1411 temp
&= ~(UARTCTRL_TE
| UARTCTRL_RE
|
1412 UARTCTRL_TIE
| UARTCTRL_TCIE
| UARTCTRL_RIE
);
1413 lpuart32_write(port
, temp
, UARTCTRL
);
1415 spin_unlock_irqrestore(&port
->lock
, flags
);
1417 devm_free_irq(port
->dev
, port
->irq
, sport
);
1421 lpuart_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
1422 struct ktermios
*old
)
1424 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1425 unsigned long flags
;
1426 unsigned char cr1
, old_cr1
, old_cr2
, cr3
, cr4
, bdh
, modem
;
1428 unsigned int old_csize
= old
? old
->c_cflag
& CSIZE
: CS8
;
1429 unsigned int sbr
, brfa
;
1431 cr1
= old_cr1
= readb(sport
->port
.membase
+ UARTCR1
);
1432 old_cr2
= readb(sport
->port
.membase
+ UARTCR2
);
1433 cr3
= readb(sport
->port
.membase
+ UARTCR3
);
1434 cr4
= readb(sport
->port
.membase
+ UARTCR4
);
1435 bdh
= readb(sport
->port
.membase
+ UARTBDH
);
1436 modem
= readb(sport
->port
.membase
+ UARTMODEM
);
1438 * only support CS8 and CS7, and for CS7 must enable PE.
1445 while ((termios
->c_cflag
& CSIZE
) != CS8
&&
1446 (termios
->c_cflag
& CSIZE
) != CS7
) {
1447 termios
->c_cflag
&= ~CSIZE
;
1448 termios
->c_cflag
|= old_csize
;
1452 if ((termios
->c_cflag
& CSIZE
) == CS8
||
1453 (termios
->c_cflag
& CSIZE
) == CS7
)
1454 cr1
= old_cr1
& ~UARTCR1_M
;
1456 if (termios
->c_cflag
& CMSPAR
) {
1457 if ((termios
->c_cflag
& CSIZE
) != CS8
) {
1458 termios
->c_cflag
&= ~CSIZE
;
1459 termios
->c_cflag
|= CS8
;
1465 * When auto RS-485 RTS mode is enabled,
1466 * hardware flow control need to be disabled.
1468 if (sport
->port
.rs485
.flags
& SER_RS485_ENABLED
)
1469 termios
->c_cflag
&= ~CRTSCTS
;
1471 if (termios
->c_cflag
& CRTSCTS
) {
1472 modem
|= (UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1474 termios
->c_cflag
&= ~CRTSCTS
;
1475 modem
&= ~(UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1478 if (termios
->c_cflag
& CSTOPB
)
1479 termios
->c_cflag
&= ~CSTOPB
;
1481 /* parity must be enabled when CS7 to match 8-bits format */
1482 if ((termios
->c_cflag
& CSIZE
) == CS7
)
1483 termios
->c_cflag
|= PARENB
;
1485 if ((termios
->c_cflag
& PARENB
)) {
1486 if (termios
->c_cflag
& CMSPAR
) {
1488 if (termios
->c_cflag
& PARODD
)
1494 if ((termios
->c_cflag
& CSIZE
) == CS8
)
1496 if (termios
->c_cflag
& PARODD
)
1503 /* ask the core to calculate the divisor */
1504 baud
= uart_get_baud_rate(port
, termios
, old
, 50, port
->uartclk
/ 16);
1507 * Need to update the Ring buffer length according to the selected
1508 * baud rate and restart Rx DMA path.
1510 * Since timer function acqures sport->port.lock, need to stop before
1511 * acquring same lock because otherwise del_timer_sync() can deadlock.
1513 if (old
&& sport
->lpuart_dma_rx_use
) {
1514 del_timer_sync(&sport
->lpuart_timer
);
1515 lpuart_dma_rx_free(&sport
->port
);
1518 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1520 sport
->port
.read_status_mask
= 0;
1521 if (termios
->c_iflag
& INPCK
)
1522 sport
->port
.read_status_mask
|= (UARTSR1_FE
| UARTSR1_PE
);
1523 if (termios
->c_iflag
& (IGNBRK
| BRKINT
| PARMRK
))
1524 sport
->port
.read_status_mask
|= UARTSR1_FE
;
1526 /* characters to ignore */
1527 sport
->port
.ignore_status_mask
= 0;
1528 if (termios
->c_iflag
& IGNPAR
)
1529 sport
->port
.ignore_status_mask
|= UARTSR1_PE
;
1530 if (termios
->c_iflag
& IGNBRK
) {
1531 sport
->port
.ignore_status_mask
|= UARTSR1_FE
;
1533 * if we're ignoring parity and break indicators,
1534 * ignore overruns too (for real raw support).
1536 if (termios
->c_iflag
& IGNPAR
)
1537 sport
->port
.ignore_status_mask
|= UARTSR1_OR
;
1540 /* update the per-port timeout */
1541 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1543 /* wait transmit engin complete */
1544 while (!(readb(sport
->port
.membase
+ UARTSR1
) & UARTSR1_TC
))
1547 /* disable transmit and receive */
1548 writeb(old_cr2
& ~(UARTCR2_TE
| UARTCR2_RE
),
1549 sport
->port
.membase
+ UARTCR2
);
1551 sbr
= sport
->port
.uartclk
/ (16 * baud
);
1552 brfa
= ((sport
->port
.uartclk
- (16 * sbr
* baud
)) * 2) / baud
;
1553 bdh
&= ~UARTBDH_SBR_MASK
;
1554 bdh
|= (sbr
>> 8) & 0x1F;
1555 cr4
&= ~UARTCR4_BRFA_MASK
;
1556 brfa
&= UARTCR4_BRFA_MASK
;
1557 writeb(cr4
| brfa
, sport
->port
.membase
+ UARTCR4
);
1558 writeb(bdh
, sport
->port
.membase
+ UARTBDH
);
1559 writeb(sbr
& 0xFF, sport
->port
.membase
+ UARTBDL
);
1560 writeb(cr3
, sport
->port
.membase
+ UARTCR3
);
1561 writeb(cr1
, sport
->port
.membase
+ UARTCR1
);
1562 writeb(modem
, sport
->port
.membase
+ UARTMODEM
);
1564 /* restore control register */
1565 writeb(old_cr2
, sport
->port
.membase
+ UARTCR2
);
1567 if (old
&& sport
->lpuart_dma_rx_use
) {
1568 if (!lpuart_start_rx_dma(sport
))
1569 rx_dma_timer_init(sport
);
1571 sport
->lpuart_dma_rx_use
= false;
1574 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1578 lpuart32_serial_setbrg(struct lpuart_port
*sport
, unsigned int baudrate
)
1580 u32 sbr
, osr
, baud_diff
, tmp_osr
, tmp_sbr
, tmp_diff
, tmp
;
1581 u32 clk
= sport
->port
.uartclk
;
1584 * The idea is to use the best OSR (over-sampling rate) possible.
1585 * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
1586 * Loop to find the best OSR value possible, one that generates minimum
1587 * baud_diff iterate through the rest of the supported values of OSR.
1589 * Calculation Formula:
1590 * Baud Rate = baud clock / ((OSR+1) × SBR)
1592 baud_diff
= baudrate
;
1596 for (tmp_osr
= 4; tmp_osr
<= 32; tmp_osr
++) {
1597 /* calculate the temporary sbr value */
1598 tmp_sbr
= (clk
/ (baudrate
* tmp_osr
));
1603 * calculate the baud rate difference based on the temporary
1604 * osr and sbr values
1606 tmp_diff
= clk
/ (tmp_osr
* tmp_sbr
) - baudrate
;
1608 /* select best values between sbr and sbr+1 */
1609 tmp
= clk
/ (tmp_osr
* (tmp_sbr
+ 1));
1610 if (tmp_diff
> (baudrate
- tmp
)) {
1611 tmp_diff
= baudrate
- tmp
;
1615 if (tmp_diff
<= baud_diff
) {
1616 baud_diff
= tmp_diff
;
1625 /* handle buadrate outside acceptable rate */
1626 if (baud_diff
> ((baudrate
/ 100) * 3))
1627 dev_warn(sport
->port
.dev
,
1628 "unacceptable baud rate difference of more than 3%%\n");
1630 tmp
= lpuart32_read(&sport
->port
, UARTBAUD
);
1632 if ((osr
> 3) && (osr
< 8))
1633 tmp
|= UARTBAUD_BOTHEDGE
;
1635 tmp
&= ~(UARTBAUD_OSR_MASK
<< UARTBAUD_OSR_SHIFT
);
1636 tmp
|= (((osr
-1) & UARTBAUD_OSR_MASK
) << UARTBAUD_OSR_SHIFT
);
1638 tmp
&= ~UARTBAUD_SBR_MASK
;
1639 tmp
|= sbr
& UARTBAUD_SBR_MASK
;
1641 tmp
&= ~(UARTBAUD_TDMAE
| UARTBAUD_RDMAE
);
1643 lpuart32_write(&sport
->port
, tmp
, UARTBAUD
);
1647 lpuart32_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
1648 struct ktermios
*old
)
1650 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1651 unsigned long flags
;
1652 unsigned long ctrl
, old_ctrl
, bd
, modem
;
1654 unsigned int old_csize
= old
? old
->c_cflag
& CSIZE
: CS8
;
1656 ctrl
= old_ctrl
= lpuart32_read(&sport
->port
, UARTCTRL
);
1657 bd
= lpuart32_read(&sport
->port
, UARTBAUD
);
1658 modem
= lpuart32_read(&sport
->port
, UARTMODIR
);
1660 * only support CS8 and CS7, and for CS7 must enable PE.
1667 while ((termios
->c_cflag
& CSIZE
) != CS8
&&
1668 (termios
->c_cflag
& CSIZE
) != CS7
) {
1669 termios
->c_cflag
&= ~CSIZE
;
1670 termios
->c_cflag
|= old_csize
;
1674 if ((termios
->c_cflag
& CSIZE
) == CS8
||
1675 (termios
->c_cflag
& CSIZE
) == CS7
)
1676 ctrl
= old_ctrl
& ~UARTCTRL_M
;
1678 if (termios
->c_cflag
& CMSPAR
) {
1679 if ((termios
->c_cflag
& CSIZE
) != CS8
) {
1680 termios
->c_cflag
&= ~CSIZE
;
1681 termios
->c_cflag
|= CS8
;
1686 if (termios
->c_cflag
& CRTSCTS
) {
1687 modem
|= (UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1689 termios
->c_cflag
&= ~CRTSCTS
;
1690 modem
&= ~(UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1693 if (termios
->c_cflag
& CSTOPB
)
1694 termios
->c_cflag
&= ~CSTOPB
;
1696 /* parity must be enabled when CS7 to match 8-bits format */
1697 if ((termios
->c_cflag
& CSIZE
) == CS7
)
1698 termios
->c_cflag
|= PARENB
;
1700 if ((termios
->c_cflag
& PARENB
)) {
1701 if (termios
->c_cflag
& CMSPAR
) {
1702 ctrl
&= ~UARTCTRL_PE
;
1706 if ((termios
->c_cflag
& CSIZE
) == CS8
)
1708 if (termios
->c_cflag
& PARODD
)
1709 ctrl
|= UARTCTRL_PT
;
1711 ctrl
&= ~UARTCTRL_PT
;
1715 /* ask the core to calculate the divisor */
1716 baud
= uart_get_baud_rate(port
, termios
, old
, 50, port
->uartclk
/ 16);
1718 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1720 sport
->port
.read_status_mask
= 0;
1721 if (termios
->c_iflag
& INPCK
)
1722 sport
->port
.read_status_mask
|= (UARTSTAT_FE
| UARTSTAT_PE
);
1723 if (termios
->c_iflag
& (IGNBRK
| BRKINT
| PARMRK
))
1724 sport
->port
.read_status_mask
|= UARTSTAT_FE
;
1726 /* characters to ignore */
1727 sport
->port
.ignore_status_mask
= 0;
1728 if (termios
->c_iflag
& IGNPAR
)
1729 sport
->port
.ignore_status_mask
|= UARTSTAT_PE
;
1730 if (termios
->c_iflag
& IGNBRK
) {
1731 sport
->port
.ignore_status_mask
|= UARTSTAT_FE
;
1733 * if we're ignoring parity and break indicators,
1734 * ignore overruns too (for real raw support).
1736 if (termios
->c_iflag
& IGNPAR
)
1737 sport
->port
.ignore_status_mask
|= UARTSTAT_OR
;
1740 /* update the per-port timeout */
1741 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1743 /* wait transmit engin complete */
1744 while (!(lpuart32_read(&sport
->port
, UARTSTAT
) & UARTSTAT_TC
))
1747 /* disable transmit and receive */
1748 lpuart32_write(&sport
->port
, old_ctrl
& ~(UARTCTRL_TE
| UARTCTRL_RE
),
1751 lpuart32_serial_setbrg(sport
, baud
);
1752 lpuart32_write(&sport
->port
, modem
, UARTMODIR
);
1753 lpuart32_write(&sport
->port
, ctrl
, UARTCTRL
);
1754 /* restore control register */
1756 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1759 static const char *lpuart_type(struct uart_port
*port
)
1761 return "FSL_LPUART";
1764 static void lpuart_release_port(struct uart_port
*port
)
1769 static int lpuart_request_port(struct uart_port
*port
)
1774 /* configure/autoconfigure the port */
1775 static void lpuart_config_port(struct uart_port
*port
, int flags
)
1777 if (flags
& UART_CONFIG_TYPE
)
1778 port
->type
= PORT_LPUART
;
1781 static int lpuart_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
1785 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_LPUART
)
1787 if (port
->irq
!= ser
->irq
)
1789 if (ser
->io_type
!= UPIO_MEM
)
1791 if (port
->uartclk
/ 16 != ser
->baud_base
)
1793 if (port
->iobase
!= ser
->port
)
1800 static const struct uart_ops lpuart_pops
= {
1801 .tx_empty
= lpuart_tx_empty
,
1802 .set_mctrl
= lpuart_set_mctrl
,
1803 .get_mctrl
= lpuart_get_mctrl
,
1804 .stop_tx
= lpuart_stop_tx
,
1805 .start_tx
= lpuart_start_tx
,
1806 .stop_rx
= lpuart_stop_rx
,
1807 .break_ctl
= lpuart_break_ctl
,
1808 .startup
= lpuart_startup
,
1809 .shutdown
= lpuart_shutdown
,
1810 .set_termios
= lpuart_set_termios
,
1811 .type
= lpuart_type
,
1812 .request_port
= lpuart_request_port
,
1813 .release_port
= lpuart_release_port
,
1814 .config_port
= lpuart_config_port
,
1815 .verify_port
= lpuart_verify_port
,
1816 .flush_buffer
= lpuart_flush_buffer
,
1817 #if defined(CONFIG_CONSOLE_POLL)
1818 .poll_init
= lpuart_poll_init
,
1819 .poll_get_char
= lpuart_poll_get_char
,
1820 .poll_put_char
= lpuart_poll_put_char
,
1824 static const struct uart_ops lpuart32_pops
= {
1825 .tx_empty
= lpuart32_tx_empty
,
1826 .set_mctrl
= lpuart32_set_mctrl
,
1827 .get_mctrl
= lpuart32_get_mctrl
,
1828 .stop_tx
= lpuart32_stop_tx
,
1829 .start_tx
= lpuart32_start_tx
,
1830 .stop_rx
= lpuart32_stop_rx
,
1831 .break_ctl
= lpuart32_break_ctl
,
1832 .startup
= lpuart32_startup
,
1833 .shutdown
= lpuart32_shutdown
,
1834 .set_termios
= lpuart32_set_termios
,
1835 .type
= lpuart_type
,
1836 .request_port
= lpuart_request_port
,
1837 .release_port
= lpuart_release_port
,
1838 .config_port
= lpuart_config_port
,
1839 .verify_port
= lpuart_verify_port
,
1840 .flush_buffer
= lpuart_flush_buffer
,
1841 #if defined(CONFIG_CONSOLE_POLL)
1842 .poll_init
= lpuart32_poll_init
,
1843 .poll_get_char
= lpuart32_poll_get_char
,
1844 .poll_put_char
= lpuart32_poll_put_char
,
1848 static struct lpuart_port
*lpuart_ports
[UART_NR
];
1850 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1851 static void lpuart_console_putchar(struct uart_port
*port
, int ch
)
1853 while (!(readb(port
->membase
+ UARTSR1
) & UARTSR1_TDRE
))
1856 writeb(ch
, port
->membase
+ UARTDR
);
1859 static void lpuart32_console_putchar(struct uart_port
*port
, int ch
)
1861 while (!(lpuart32_read(port
, UARTSTAT
) & UARTSTAT_TDRE
))
1864 lpuart32_write(port
, ch
, UARTDATA
);
1868 lpuart_console_write(struct console
*co
, const char *s
, unsigned int count
)
1870 struct lpuart_port
*sport
= lpuart_ports
[co
->index
];
1871 unsigned char old_cr2
, cr2
;
1872 unsigned long flags
;
1875 if (sport
->port
.sysrq
|| oops_in_progress
)
1876 locked
= spin_trylock_irqsave(&sport
->port
.lock
, flags
);
1878 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1880 /* first save CR2 and then disable interrupts */
1881 cr2
= old_cr2
= readb(sport
->port
.membase
+ UARTCR2
);
1882 cr2
|= (UARTCR2_TE
| UARTCR2_RE
);
1883 cr2
&= ~(UARTCR2_TIE
| UARTCR2_TCIE
| UARTCR2_RIE
);
1884 writeb(cr2
, sport
->port
.membase
+ UARTCR2
);
1886 uart_console_write(&sport
->port
, s
, count
, lpuart_console_putchar
);
1888 /* wait for transmitter finish complete and restore CR2 */
1889 while (!(readb(sport
->port
.membase
+ UARTSR1
) & UARTSR1_TC
))
1892 writeb(old_cr2
, sport
->port
.membase
+ UARTCR2
);
1895 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1899 lpuart32_console_write(struct console
*co
, const char *s
, unsigned int count
)
1901 struct lpuart_port
*sport
= lpuart_ports
[co
->index
];
1902 unsigned long old_cr
, cr
;
1903 unsigned long flags
;
1906 if (sport
->port
.sysrq
|| oops_in_progress
)
1907 locked
= spin_trylock_irqsave(&sport
->port
.lock
, flags
);
1909 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1911 /* first save CR2 and then disable interrupts */
1912 cr
= old_cr
= lpuart32_read(&sport
->port
, UARTCTRL
);
1913 cr
|= (UARTCTRL_TE
| UARTCTRL_RE
);
1914 cr
&= ~(UARTCTRL_TIE
| UARTCTRL_TCIE
| UARTCTRL_RIE
);
1915 lpuart32_write(&sport
->port
, cr
, UARTCTRL
);
1917 uart_console_write(&sport
->port
, s
, count
, lpuart32_console_putchar
);
1919 /* wait for transmitter finish complete and restore CR2 */
1920 while (!(lpuart32_read(&sport
->port
, UARTSTAT
) & UARTSTAT_TC
))
1923 lpuart32_write(&sport
->port
, old_cr
, UARTCTRL
);
1926 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1930 * if the port was already initialised (eg, by a boot loader),
1931 * try to determine the current setup.
1934 lpuart_console_get_options(struct lpuart_port
*sport
, int *baud
,
1935 int *parity
, int *bits
)
1937 unsigned char cr
, bdh
, bdl
, brfa
;
1938 unsigned int sbr
, uartclk
, baud_raw
;
1940 cr
= readb(sport
->port
.membase
+ UARTCR2
);
1941 cr
&= UARTCR2_TE
| UARTCR2_RE
;
1945 /* ok, the port was enabled */
1947 cr
= readb(sport
->port
.membase
+ UARTCR1
);
1950 if (cr
& UARTCR1_PE
) {
1951 if (cr
& UARTCR1_PT
)
1962 bdh
= readb(sport
->port
.membase
+ UARTBDH
);
1963 bdh
&= UARTBDH_SBR_MASK
;
1964 bdl
= readb(sport
->port
.membase
+ UARTBDL
);
1968 brfa
= readb(sport
->port
.membase
+ UARTCR4
);
1969 brfa
&= UARTCR4_BRFA_MASK
;
1971 uartclk
= clk_get_rate(sport
->clk
);
1973 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1975 baud_raw
= uartclk
/ (16 * (sbr
+ brfa
/ 32));
1977 if (*baud
!= baud_raw
)
1978 printk(KERN_INFO
"Serial: Console lpuart rounded baud rate"
1979 "from %d to %d\n", baud_raw
, *baud
);
1983 lpuart32_console_get_options(struct lpuart_port
*sport
, int *baud
,
1984 int *parity
, int *bits
)
1986 unsigned long cr
, bd
;
1987 unsigned int sbr
, uartclk
, baud_raw
;
1989 cr
= lpuart32_read(&sport
->port
, UARTCTRL
);
1990 cr
&= UARTCTRL_TE
| UARTCTRL_RE
;
1994 /* ok, the port was enabled */
1996 cr
= lpuart32_read(&sport
->port
, UARTCTRL
);
1999 if (cr
& UARTCTRL_PE
) {
2000 if (cr
& UARTCTRL_PT
)
2006 if (cr
& UARTCTRL_M
)
2011 bd
= lpuart32_read(&sport
->port
, UARTBAUD
);
2012 bd
&= UARTBAUD_SBR_MASK
;
2014 uartclk
= clk_get_rate(sport
->clk
);
2016 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2018 baud_raw
= uartclk
/ (16 * sbr
);
2020 if (*baud
!= baud_raw
)
2021 printk(KERN_INFO
"Serial: Console lpuart rounded baud rate"
2022 "from %d to %d\n", baud_raw
, *baud
);
2025 static int __init
lpuart_console_setup(struct console
*co
, char *options
)
2027 struct lpuart_port
*sport
;
2034 * check whether an invalid uart number has been specified, and
2035 * if so, search for the first available port that does have
2038 if (co
->index
== -1 || co
->index
>= ARRAY_SIZE(lpuart_ports
))
2041 sport
= lpuart_ports
[co
->index
];
2046 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
2048 if (lpuart_is_32(sport
))
2049 lpuart32_console_get_options(sport
, &baud
, &parity
, &bits
);
2051 lpuart_console_get_options(sport
, &baud
, &parity
, &bits
);
2053 if (lpuart_is_32(sport
))
2054 lpuart32_setup_watermark(sport
);
2056 lpuart_setup_watermark(sport
);
2058 return uart_set_options(&sport
->port
, co
, baud
, parity
, bits
, flow
);
2061 static struct uart_driver lpuart_reg
;
2062 static struct console lpuart_console
= {
2064 .write
= lpuart_console_write
,
2065 .device
= uart_console_device
,
2066 .setup
= lpuart_console_setup
,
2067 .flags
= CON_PRINTBUFFER
,
2069 .data
= &lpuart_reg
,
2072 static struct console lpuart32_console
= {
2074 .write
= lpuart32_console_write
,
2075 .device
= uart_console_device
,
2076 .setup
= lpuart_console_setup
,
2077 .flags
= CON_PRINTBUFFER
,
2079 .data
= &lpuart_reg
,
2082 static void lpuart_early_write(struct console
*con
, const char *s
, unsigned n
)
2084 struct earlycon_device
*dev
= con
->data
;
2086 uart_console_write(&dev
->port
, s
, n
, lpuart_console_putchar
);
2089 static void lpuart32_early_write(struct console
*con
, const char *s
, unsigned n
)
2091 struct earlycon_device
*dev
= con
->data
;
2093 uart_console_write(&dev
->port
, s
, n
, lpuart32_console_putchar
);
2096 static int __init
lpuart_early_console_setup(struct earlycon_device
*device
,
2099 if (!device
->port
.membase
)
2102 device
->con
->write
= lpuart_early_write
;
2106 static int __init
lpuart32_early_console_setup(struct earlycon_device
*device
,
2109 if (!device
->port
.membase
)
2112 device
->port
.iotype
= UPIO_MEM32BE
;
2113 device
->con
->write
= lpuart32_early_write
;
2117 static int __init
lpuart32_imx_early_console_setup(struct earlycon_device
*device
,
2120 if (!device
->port
.membase
)
2123 device
->port
.iotype
= UPIO_MEM32
;
2124 device
->port
.membase
+= IMX_REG_OFF
;
2125 device
->con
->write
= lpuart32_early_write
;
2129 OF_EARLYCON_DECLARE(lpuart
, "fsl,vf610-lpuart", lpuart_early_console_setup
);
2130 OF_EARLYCON_DECLARE(lpuart32
, "fsl,ls1021a-lpuart", lpuart32_early_console_setup
);
2131 OF_EARLYCON_DECLARE(lpuart32
, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup
);
2132 EARLYCON_DECLARE(lpuart
, lpuart_early_console_setup
);
2133 EARLYCON_DECLARE(lpuart32
, lpuart32_early_console_setup
);
2135 #define LPUART_CONSOLE (&lpuart_console)
2136 #define LPUART32_CONSOLE (&lpuart32_console)
2138 #define LPUART_CONSOLE NULL
2139 #define LPUART32_CONSOLE NULL
2142 static struct uart_driver lpuart_reg
= {
2143 .owner
= THIS_MODULE
,
2144 .driver_name
= DRIVER_NAME
,
2145 .dev_name
= DEV_NAME
,
2146 .nr
= ARRAY_SIZE(lpuart_ports
),
2147 .cons
= LPUART_CONSOLE
,
2150 static int lpuart_probe(struct platform_device
*pdev
)
2152 const struct of_device_id
*of_id
= of_match_device(lpuart_dt_ids
,
2154 const struct lpuart_soc_data
*sdata
= of_id
->data
;
2155 struct device_node
*np
= pdev
->dev
.of_node
;
2156 struct lpuart_port
*sport
;
2157 struct resource
*res
;
2160 sport
= devm_kzalloc(&pdev
->dev
, sizeof(*sport
), GFP_KERNEL
);
2164 pdev
->dev
.coherent_dma_mask
= 0;
2166 ret
= of_alias_get_id(np
, "serial");
2168 dev_err(&pdev
->dev
, "failed to get alias id, errno %d\n", ret
);
2171 sport
->port
.line
= ret
;
2172 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2173 sport
->port
.membase
= devm_ioremap_resource(&pdev
->dev
, res
);
2174 if (IS_ERR(sport
->port
.membase
))
2175 return PTR_ERR(sport
->port
.membase
);
2177 sport
->port
.membase
+= sdata
->reg_off
;
2178 sport
->port
.mapbase
= res
->start
;
2179 sport
->port
.dev
= &pdev
->dev
;
2180 sport
->port
.type
= PORT_LPUART
;
2181 ret
= platform_get_irq(pdev
, 0);
2183 dev_err(&pdev
->dev
, "cannot obtain irq\n");
2186 sport
->port
.irq
= ret
;
2187 sport
->port
.iotype
= sdata
->iotype
;
2188 if (lpuart_is_32(sport
))
2189 sport
->port
.ops
= &lpuart32_pops
;
2191 sport
->port
.ops
= &lpuart_pops
;
2192 sport
->port
.flags
= UPF_BOOT_AUTOCONF
;
2194 sport
->port
.rs485_config
= lpuart_config_rs485
;
2196 sport
->clk
= devm_clk_get(&pdev
->dev
, "ipg");
2197 if (IS_ERR(sport
->clk
)) {
2198 ret
= PTR_ERR(sport
->clk
);
2199 dev_err(&pdev
->dev
, "failed to get uart clk: %d\n", ret
);
2203 ret
= clk_prepare_enable(sport
->clk
);
2205 dev_err(&pdev
->dev
, "failed to enable uart clk: %d\n", ret
);
2209 sport
->port
.uartclk
= clk_get_rate(sport
->clk
);
2211 lpuart_ports
[sport
->port
.line
] = sport
;
2213 platform_set_drvdata(pdev
, &sport
->port
);
2215 if (lpuart_is_32(sport
))
2216 lpuart_reg
.cons
= LPUART32_CONSOLE
;
2218 lpuart_reg
.cons
= LPUART_CONSOLE
;
2220 ret
= uart_add_one_port(&lpuart_reg
, &sport
->port
);
2222 clk_disable_unprepare(sport
->clk
);
2226 sport
->dma_tx_chan
= dma_request_slave_channel(sport
->port
.dev
, "tx");
2227 if (!sport
->dma_tx_chan
)
2228 dev_info(sport
->port
.dev
, "DMA tx channel request failed, "
2229 "operating without tx DMA\n");
2231 sport
->dma_rx_chan
= dma_request_slave_channel(sport
->port
.dev
, "rx");
2232 if (!sport
->dma_rx_chan
)
2233 dev_info(sport
->port
.dev
, "DMA rx channel request failed, "
2234 "operating without rx DMA\n");
2236 if (of_property_read_bool(np
, "linux,rs485-enabled-at-boot-time")) {
2237 sport
->port
.rs485
.flags
|= SER_RS485_ENABLED
;
2238 sport
->port
.rs485
.flags
|= SER_RS485_RTS_ON_SEND
;
2239 writeb(UARTMODEM_TXRTSE
, sport
->port
.membase
+ UARTMODEM
);
2245 static int lpuart_remove(struct platform_device
*pdev
)
2247 struct lpuart_port
*sport
= platform_get_drvdata(pdev
);
2249 uart_remove_one_port(&lpuart_reg
, &sport
->port
);
2251 clk_disable_unprepare(sport
->clk
);
2253 if (sport
->dma_tx_chan
)
2254 dma_release_channel(sport
->dma_tx_chan
);
2256 if (sport
->dma_rx_chan
)
2257 dma_release_channel(sport
->dma_rx_chan
);
2262 #ifdef CONFIG_PM_SLEEP
2263 static int lpuart_suspend(struct device
*dev
)
2265 struct lpuart_port
*sport
= dev_get_drvdata(dev
);
2269 if (lpuart_is_32(sport
)) {
2270 /* disable Rx/Tx and interrupts */
2271 temp
= lpuart32_read(&sport
->port
, UARTCTRL
);
2272 temp
&= ~(UARTCTRL_TE
| UARTCTRL_TIE
| UARTCTRL_TCIE
);
2273 lpuart32_write(&sport
->port
, temp
, UARTCTRL
);
2275 /* disable Rx/Tx and interrupts */
2276 temp
= readb(sport
->port
.membase
+ UARTCR2
);
2277 temp
&= ~(UARTCR2_TE
| UARTCR2_TIE
| UARTCR2_TCIE
);
2278 writeb(temp
, sport
->port
.membase
+ UARTCR2
);
2281 uart_suspend_port(&lpuart_reg
, &sport
->port
);
2283 /* uart_suspend_port() might set wakeup flag */
2284 irq_wake
= irqd_is_wakeup_set(irq_get_irq_data(sport
->port
.irq
));
2286 if (sport
->lpuart_dma_rx_use
) {
2288 * EDMA driver during suspend will forcefully release any
2289 * non-idle DMA channels. If port wakeup is enabled or if port
2290 * is console port or 'no_console_suspend' is set the Rx DMA
2291 * cannot resume as as expected, hence gracefully release the
2292 * Rx DMA path before suspend and start Rx DMA path on resume.
2295 del_timer_sync(&sport
->lpuart_timer
);
2296 lpuart_dma_rx_free(&sport
->port
);
2299 /* Disable Rx DMA to use UART port as wakeup source */
2300 writeb(readb(sport
->port
.membase
+ UARTCR5
) & ~UARTCR5_RDMAS
,
2301 sport
->port
.membase
+ UARTCR5
);
2304 if (sport
->lpuart_dma_tx_use
) {
2305 sport
->dma_tx_in_progress
= false;
2306 dmaengine_terminate_all(sport
->dma_tx_chan
);
2309 if (sport
->port
.suspended
&& !irq_wake
)
2310 clk_disable_unprepare(sport
->clk
);
2315 static int lpuart_resume(struct device
*dev
)
2317 struct lpuart_port
*sport
= dev_get_drvdata(dev
);
2318 bool irq_wake
= irqd_is_wakeup_set(irq_get_irq_data(sport
->port
.irq
));
2321 if (sport
->port
.suspended
&& !irq_wake
)
2322 clk_prepare_enable(sport
->clk
);
2324 if (lpuart_is_32(sport
)) {
2325 lpuart32_setup_watermark(sport
);
2326 temp
= lpuart32_read(&sport
->port
, UARTCTRL
);
2327 temp
|= (UARTCTRL_RIE
| UARTCTRL_TIE
| UARTCTRL_RE
|
2328 UARTCTRL_TE
| UARTCTRL_ILIE
);
2329 lpuart32_write(&sport
->port
, temp
, UARTCTRL
);
2331 lpuart_setup_watermark(sport
);
2332 temp
= readb(sport
->port
.membase
+ UARTCR2
);
2333 temp
|= (UARTCR2_RIE
| UARTCR2_TIE
| UARTCR2_RE
| UARTCR2_TE
);
2334 writeb(temp
, sport
->port
.membase
+ UARTCR2
);
2337 if (sport
->lpuart_dma_rx_use
) {
2339 if (!lpuart_start_rx_dma(sport
))
2340 rx_dma_timer_init(sport
);
2342 sport
->lpuart_dma_rx_use
= false;
2346 if (sport
->dma_tx_chan
&& !lpuart_dma_tx_request(&sport
->port
)) {
2347 init_waitqueue_head(&sport
->dma_wait
);
2348 sport
->lpuart_dma_tx_use
= true;
2349 writeb(readb(sport
->port
.membase
+ UARTCR5
) |
2350 UARTCR5_TDMAS
, sport
->port
.membase
+ UARTCR5
);
2352 sport
->lpuart_dma_tx_use
= false;
2355 uart_resume_port(&lpuart_reg
, &sport
->port
);
2361 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops
, lpuart_suspend
, lpuart_resume
);
2363 static struct platform_driver lpuart_driver
= {
2364 .probe
= lpuart_probe
,
2365 .remove
= lpuart_remove
,
2367 .name
= "fsl-lpuart",
2368 .of_match_table
= lpuart_dt_ids
,
2369 .pm
= &lpuart_pm_ops
,
2373 static int __init
lpuart_serial_init(void)
2375 int ret
= uart_register_driver(&lpuart_reg
);
2380 ret
= platform_driver_register(&lpuart_driver
);
2382 uart_unregister_driver(&lpuart_reg
);
2387 static void __exit
lpuart_serial_exit(void)
2389 platform_driver_unregister(&lpuart_driver
);
2390 uart_unregister_driver(&lpuart_reg
);
2393 module_init(lpuart_serial_init
);
2394 module_exit(lpuart_serial_exit
);
2396 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2397 MODULE_LICENSE("GPL v2");