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serial: imx: reset the uart port all the time
[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / imx.c
1 /*
2 * Driver for Motorola IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
28 */
29
30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #define SUPPORT_SYSRQ
32 #endif
33
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/console.h>
38 #include <linux/sysrq.h>
39 #include <linux/platform_device.h>
40 #include <linux/tty.h>
41 #include <linux/tty_flip.h>
42 #include <linux/serial_core.h>
43 #include <linux/serial.h>
44 #include <linux/clk.h>
45 #include <linux/delay.h>
46 #include <linux/rational.h>
47 #include <linux/slab.h>
48 #include <linux/of.h>
49 #include <linux/of_device.h>
50 #include <linux/io.h>
51 #include <linux/dma-mapping.h>
52
53 #include <asm/irq.h>
54 #include <linux/platform_data/serial-imx.h>
55 #include <linux/platform_data/dma-imx.h>
56
57 /* Register definitions */
58 #define URXD0 0x0 /* Receiver Register */
59 #define URTX0 0x40 /* Transmitter Register */
60 #define UCR1 0x80 /* Control Register 1 */
61 #define UCR2 0x84 /* Control Register 2 */
62 #define UCR3 0x88 /* Control Register 3 */
63 #define UCR4 0x8c /* Control Register 4 */
64 #define UFCR 0x90 /* FIFO Control Register */
65 #define USR1 0x94 /* Status Register 1 */
66 #define USR2 0x98 /* Status Register 2 */
67 #define UESC 0x9c /* Escape Character Register */
68 #define UTIM 0xa0 /* Escape Timer Register */
69 #define UBIR 0xa4 /* BRM Incremental Register */
70 #define UBMR 0xa8 /* BRM Modulator Register */
71 #define UBRC 0xac /* Baud Rate Count Register */
72 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
73 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
74 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
75
76 /* UART Control Register Bit Fields.*/
77 #define URXD_CHARRDY (1<<15)
78 #define URXD_ERR (1<<14)
79 #define URXD_OVRRUN (1<<13)
80 #define URXD_FRMERR (1<<12)
81 #define URXD_BRK (1<<11)
82 #define URXD_PRERR (1<<10)
83 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
84 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
85 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
86 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
87 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
88 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
89 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
90 #define UCR1_IREN (1<<7) /* Infrared interface enable */
91 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
92 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
93 #define UCR1_SNDBRK (1<<4) /* Send break */
94 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
95 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
96 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
97 #define UCR1_DOZE (1<<1) /* Doze */
98 #define UCR1_UARTEN (1<<0) /* UART enabled */
99 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
100 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
101 #define UCR2_CTSC (1<<13) /* CTS pin control */
102 #define UCR2_CTS (1<<12) /* Clear to send */
103 #define UCR2_ESCEN (1<<11) /* Escape enable */
104 #define UCR2_PREN (1<<8) /* Parity enable */
105 #define UCR2_PROE (1<<7) /* Parity odd/even */
106 #define UCR2_STPB (1<<6) /* Stop */
107 #define UCR2_WS (1<<5) /* Word size */
108 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
109 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
110 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
111 #define UCR2_RXEN (1<<1) /* Receiver enabled */
112 #define UCR2_SRST (1<<0) /* SW reset */
113 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
114 #define UCR3_PARERREN (1<<12) /* Parity enable */
115 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
116 #define UCR3_DSR (1<<10) /* Data set ready */
117 #define UCR3_DCD (1<<9) /* Data carrier detect */
118 #define UCR3_RI (1<<8) /* Ring indicator */
119 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
120 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
121 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
122 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
123 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
124 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
125 #define UCR3_BPEN (1<<0) /* Preset registers enable */
126 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
127 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
128 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
129 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
130 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
131 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
132 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
133 #define UCR4_IRSC (1<<5) /* IR special case */
134 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
135 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
136 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
137 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
138 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
139 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
140 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
141 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
142 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
143 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
144 #define USR1_RTSS (1<<14) /* RTS pin status */
145 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
146 #define USR1_RTSD (1<<12) /* RTS delta */
147 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
148 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
149 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
150 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
151 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
152 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
153 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
154 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
155 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
156 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
157 #define USR2_IDLE (1<<12) /* Idle condition */
158 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
159 #define USR2_WAKE (1<<7) /* Wake */
160 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
161 #define USR2_TXDC (1<<3) /* Transmitter complete */
162 #define USR2_BRCD (1<<2) /* Break condition */
163 #define USR2_ORE (1<<1) /* Overrun error */
164 #define USR2_RDR (1<<0) /* Recv data ready */
165 #define UTS_FRCPERR (1<<13) /* Force parity error */
166 #define UTS_LOOP (1<<12) /* Loop tx and rx */
167 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
168 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
169 #define UTS_TXFULL (1<<4) /* TxFIFO full */
170 #define UTS_RXFULL (1<<3) /* RxFIFO full */
171 #define UTS_SOFTRST (1<<0) /* Software reset */
172
173 /* We've been assigned a range on the "Low-density serial ports" major */
174 #define SERIAL_IMX_MAJOR 207
175 #define MINOR_START 16
176 #define DEV_NAME "ttymxc"
177
178 /*
179 * This determines how often we check the modem status signals
180 * for any change. They generally aren't connected to an IRQ
181 * so we have to poll them. We also check immediately before
182 * filling the TX fifo incase CTS has been dropped.
183 */
184 #define MCTRL_TIMEOUT (250*HZ/1000)
185
186 #define DRIVER_NAME "IMX-uart"
187
188 #define UART_NR 8
189
190 /* i.mx21 type uart runs on all i.mx except i.mx1 */
191 enum imx_uart_type {
192 IMX1_UART,
193 IMX21_UART,
194 IMX6Q_UART,
195 };
196
197 /* device type dependent stuff */
198 struct imx_uart_data {
199 unsigned uts_reg;
200 enum imx_uart_type devtype;
201 };
202
203 struct imx_port {
204 struct uart_port port;
205 struct timer_list timer;
206 unsigned int old_status;
207 int txirq, rxirq, rtsirq;
208 unsigned int have_rtscts:1;
209 unsigned int dte_mode:1;
210 unsigned int use_irda:1;
211 unsigned int irda_inv_rx:1;
212 unsigned int irda_inv_tx:1;
213 unsigned short trcv_delay; /* transceiver delay */
214 struct clk *clk_ipg;
215 struct clk *clk_per;
216 const struct imx_uart_data *devdata;
217
218 /* DMA fields */
219 unsigned int dma_is_inited:1;
220 unsigned int dma_is_enabled:1;
221 unsigned int dma_is_rxing:1;
222 unsigned int dma_is_txing:1;
223 struct dma_chan *dma_chan_rx, *dma_chan_tx;
224 struct scatterlist rx_sgl, tx_sgl[2];
225 void *rx_buf;
226 unsigned int tx_bytes;
227 unsigned int dma_tx_nents;
228 wait_queue_head_t dma_wait;
229 };
230
231 struct imx_port_ucrs {
232 unsigned int ucr1;
233 unsigned int ucr2;
234 unsigned int ucr3;
235 };
236
237 #ifdef CONFIG_IRDA
238 #define USE_IRDA(sport) ((sport)->use_irda)
239 #else
240 #define USE_IRDA(sport) (0)
241 #endif
242
243 static struct imx_uart_data imx_uart_devdata[] = {
244 [IMX1_UART] = {
245 .uts_reg = IMX1_UTS,
246 .devtype = IMX1_UART,
247 },
248 [IMX21_UART] = {
249 .uts_reg = IMX21_UTS,
250 .devtype = IMX21_UART,
251 },
252 [IMX6Q_UART] = {
253 .uts_reg = IMX21_UTS,
254 .devtype = IMX6Q_UART,
255 },
256 };
257
258 static struct platform_device_id imx_uart_devtype[] = {
259 {
260 .name = "imx1-uart",
261 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
262 }, {
263 .name = "imx21-uart",
264 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
265 }, {
266 .name = "imx6q-uart",
267 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
268 }, {
269 /* sentinel */
270 }
271 };
272 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
273
274 static struct of_device_id imx_uart_dt_ids[] = {
275 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
276 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
277 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
278 { /* sentinel */ }
279 };
280 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
281
282 static inline unsigned uts_reg(struct imx_port *sport)
283 {
284 return sport->devdata->uts_reg;
285 }
286
287 static inline int is_imx1_uart(struct imx_port *sport)
288 {
289 return sport->devdata->devtype == IMX1_UART;
290 }
291
292 static inline int is_imx21_uart(struct imx_port *sport)
293 {
294 return sport->devdata->devtype == IMX21_UART;
295 }
296
297 static inline int is_imx6q_uart(struct imx_port *sport)
298 {
299 return sport->devdata->devtype == IMX6Q_UART;
300 }
301 /*
302 * Save and restore functions for UCR1, UCR2 and UCR3 registers
303 */
304 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_IMX_CONSOLE)
305 static void imx_port_ucrs_save(struct uart_port *port,
306 struct imx_port_ucrs *ucr)
307 {
308 /* save control registers */
309 ucr->ucr1 = readl(port->membase + UCR1);
310 ucr->ucr2 = readl(port->membase + UCR2);
311 ucr->ucr3 = readl(port->membase + UCR3);
312 }
313
314 static void imx_port_ucrs_restore(struct uart_port *port,
315 struct imx_port_ucrs *ucr)
316 {
317 /* restore control registers */
318 writel(ucr->ucr1, port->membase + UCR1);
319 writel(ucr->ucr2, port->membase + UCR2);
320 writel(ucr->ucr3, port->membase + UCR3);
321 }
322 #endif
323
324 /*
325 * Handle any change of modem status signal since we were last called.
326 */
327 static void imx_mctrl_check(struct imx_port *sport)
328 {
329 unsigned int status, changed;
330
331 status = sport->port.ops->get_mctrl(&sport->port);
332 changed = status ^ sport->old_status;
333
334 if (changed == 0)
335 return;
336
337 sport->old_status = status;
338
339 if (changed & TIOCM_RI)
340 sport->port.icount.rng++;
341 if (changed & TIOCM_DSR)
342 sport->port.icount.dsr++;
343 if (changed & TIOCM_CAR)
344 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
345 if (changed & TIOCM_CTS)
346 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
347
348 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
349 }
350
351 /*
352 * This is our per-port timeout handler, for checking the
353 * modem status signals.
354 */
355 static void imx_timeout(unsigned long data)
356 {
357 struct imx_port *sport = (struct imx_port *)data;
358 unsigned long flags;
359
360 if (sport->port.state) {
361 spin_lock_irqsave(&sport->port.lock, flags);
362 imx_mctrl_check(sport);
363 spin_unlock_irqrestore(&sport->port.lock, flags);
364
365 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
366 }
367 }
368
369 /*
370 * interrupts disabled on entry
371 */
372 static void imx_stop_tx(struct uart_port *port)
373 {
374 struct imx_port *sport = (struct imx_port *)port;
375 unsigned long temp;
376
377 if (USE_IRDA(sport)) {
378 /* half duplex - wait for end of transmission */
379 int n = 256;
380 while ((--n > 0) &&
381 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
382 udelay(5);
383 barrier();
384 }
385 /*
386 * irda transceiver - wait a bit more to avoid
387 * cutoff, hardware dependent
388 */
389 udelay(sport->trcv_delay);
390
391 /*
392 * half duplex - reactivate receive mode,
393 * flush receive pipe echo crap
394 */
395 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
396 temp = readl(sport->port.membase + UCR1);
397 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
398 writel(temp, sport->port.membase + UCR1);
399
400 temp = readl(sport->port.membase + UCR4);
401 temp &= ~(UCR4_TCEN);
402 writel(temp, sport->port.membase + UCR4);
403
404 while (readl(sport->port.membase + URXD0) &
405 URXD_CHARRDY)
406 barrier();
407
408 temp = readl(sport->port.membase + UCR1);
409 temp |= UCR1_RRDYEN;
410 writel(temp, sport->port.membase + UCR1);
411
412 temp = readl(sport->port.membase + UCR4);
413 temp |= UCR4_DREN;
414 writel(temp, sport->port.membase + UCR4);
415 }
416 return;
417 }
418
419 /*
420 * We are maybe in the SMP context, so if the DMA TX thread is running
421 * on other cpu, we have to wait for it to finish.
422 */
423 if (sport->dma_is_enabled && sport->dma_is_txing)
424 return;
425
426 temp = readl(sport->port.membase + UCR1);
427 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
428 }
429
430 /*
431 * interrupts disabled on entry
432 */
433 static void imx_stop_rx(struct uart_port *port)
434 {
435 struct imx_port *sport = (struct imx_port *)port;
436 unsigned long temp;
437
438 /*
439 * We are maybe in the SMP context, so if the DMA TX thread is running
440 * on other cpu, we have to wait for it to finish.
441 */
442 if (sport->dma_is_enabled && sport->dma_is_rxing)
443 return;
444
445 temp = readl(sport->port.membase + UCR2);
446 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
447 }
448
449 /*
450 * Set the modem control timer to fire immediately.
451 */
452 static void imx_enable_ms(struct uart_port *port)
453 {
454 struct imx_port *sport = (struct imx_port *)port;
455
456 mod_timer(&sport->timer, jiffies);
457 }
458
459 static inline void imx_transmit_buffer(struct imx_port *sport)
460 {
461 struct circ_buf *xmit = &sport->port.state->xmit;
462
463 while (!uart_circ_empty(xmit) &&
464 !(readl(sport->port.membase + uts_reg(sport))
465 & UTS_TXFULL)) {
466 /* send xmit->buf[xmit->tail]
467 * out the port here */
468 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
469 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
470 sport->port.icount.tx++;
471 }
472
473 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
474 uart_write_wakeup(&sport->port);
475
476 if (uart_circ_empty(xmit))
477 imx_stop_tx(&sport->port);
478 }
479
480 static void dma_tx_callback(void *data)
481 {
482 struct imx_port *sport = data;
483 struct scatterlist *sgl = &sport->tx_sgl[0];
484 struct circ_buf *xmit = &sport->port.state->xmit;
485 unsigned long flags;
486
487 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
488
489 sport->dma_is_txing = 0;
490
491 /* update the stat */
492 spin_lock_irqsave(&sport->port.lock, flags);
493 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
494 sport->port.icount.tx += sport->tx_bytes;
495 spin_unlock_irqrestore(&sport->port.lock, flags);
496
497 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
498
499 uart_write_wakeup(&sport->port);
500
501 if (waitqueue_active(&sport->dma_wait)) {
502 wake_up(&sport->dma_wait);
503 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
504 return;
505 }
506 }
507
508 static void imx_dma_tx(struct imx_port *sport)
509 {
510 struct circ_buf *xmit = &sport->port.state->xmit;
511 struct scatterlist *sgl = sport->tx_sgl;
512 struct dma_async_tx_descriptor *desc;
513 struct dma_chan *chan = sport->dma_chan_tx;
514 struct device *dev = sport->port.dev;
515 enum dma_status status;
516 int ret;
517
518 status = dmaengine_tx_status(chan, (dma_cookie_t)0, NULL);
519 if (DMA_IN_PROGRESS == status)
520 return;
521
522 sport->tx_bytes = uart_circ_chars_pending(xmit);
523
524 if (xmit->tail > xmit->head && xmit->head > 0) {
525 sport->dma_tx_nents = 2;
526 sg_init_table(sgl, 2);
527 sg_set_buf(sgl, xmit->buf + xmit->tail,
528 UART_XMIT_SIZE - xmit->tail);
529 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
530 } else {
531 sport->dma_tx_nents = 1;
532 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
533 }
534
535 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
536 if (ret == 0) {
537 dev_err(dev, "DMA mapping error for TX.\n");
538 return;
539 }
540 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
541 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
542 if (!desc) {
543 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
544 return;
545 }
546 desc->callback = dma_tx_callback;
547 desc->callback_param = sport;
548
549 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
550 uart_circ_chars_pending(xmit));
551 /* fire it */
552 sport->dma_is_txing = 1;
553 dmaengine_submit(desc);
554 dma_async_issue_pending(chan);
555 return;
556 }
557
558 /*
559 * interrupts disabled on entry
560 */
561 static void imx_start_tx(struct uart_port *port)
562 {
563 struct imx_port *sport = (struct imx_port *)port;
564 unsigned long temp;
565
566 if (USE_IRDA(sport)) {
567 /* half duplex in IrDA mode; have to disable receive mode */
568 temp = readl(sport->port.membase + UCR4);
569 temp &= ~(UCR4_DREN);
570 writel(temp, sport->port.membase + UCR4);
571
572 temp = readl(sport->port.membase + UCR1);
573 temp &= ~(UCR1_RRDYEN);
574 writel(temp, sport->port.membase + UCR1);
575 }
576 /* Clear any pending ORE flag before enabling interrupt */
577 temp = readl(sport->port.membase + USR2);
578 writel(temp | USR2_ORE, sport->port.membase + USR2);
579
580 temp = readl(sport->port.membase + UCR4);
581 temp |= UCR4_OREN;
582 writel(temp, sport->port.membase + UCR4);
583
584 if (!sport->dma_is_enabled) {
585 temp = readl(sport->port.membase + UCR1);
586 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
587 }
588
589 if (USE_IRDA(sport)) {
590 temp = readl(sport->port.membase + UCR1);
591 temp |= UCR1_TRDYEN;
592 writel(temp, sport->port.membase + UCR1);
593
594 temp = readl(sport->port.membase + UCR4);
595 temp |= UCR4_TCEN;
596 writel(temp, sport->port.membase + UCR4);
597 }
598
599 if (sport->dma_is_enabled) {
600 imx_dma_tx(sport);
601 return;
602 }
603
604 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
605 imx_transmit_buffer(sport);
606 }
607
608 static irqreturn_t imx_rtsint(int irq, void *dev_id)
609 {
610 struct imx_port *sport = dev_id;
611 unsigned int val;
612 unsigned long flags;
613
614 spin_lock_irqsave(&sport->port.lock, flags);
615
616 writel(USR1_RTSD, sport->port.membase + USR1);
617 val = readl(sport->port.membase + USR1) & USR1_RTSS;
618 uart_handle_cts_change(&sport->port, !!val);
619 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
620
621 spin_unlock_irqrestore(&sport->port.lock, flags);
622 return IRQ_HANDLED;
623 }
624
625 static irqreturn_t imx_txint(int irq, void *dev_id)
626 {
627 struct imx_port *sport = dev_id;
628 struct circ_buf *xmit = &sport->port.state->xmit;
629 unsigned long flags;
630
631 spin_lock_irqsave(&sport->port.lock, flags);
632 if (sport->port.x_char) {
633 /* Send next char */
634 writel(sport->port.x_char, sport->port.membase + URTX0);
635 goto out;
636 }
637
638 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
639 imx_stop_tx(&sport->port);
640 goto out;
641 }
642
643 imx_transmit_buffer(sport);
644
645 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
646 uart_write_wakeup(&sport->port);
647
648 out:
649 spin_unlock_irqrestore(&sport->port.lock, flags);
650 return IRQ_HANDLED;
651 }
652
653 static irqreturn_t imx_rxint(int irq, void *dev_id)
654 {
655 struct imx_port *sport = dev_id;
656 unsigned int rx, flg, ignored = 0;
657 struct tty_port *port = &sport->port.state->port;
658 unsigned long flags, temp;
659
660 spin_lock_irqsave(&sport->port.lock, flags);
661
662 while (readl(sport->port.membase + USR2) & USR2_RDR) {
663 flg = TTY_NORMAL;
664 sport->port.icount.rx++;
665
666 rx = readl(sport->port.membase + URXD0);
667
668 temp = readl(sport->port.membase + USR2);
669 if (temp & USR2_BRCD) {
670 writel(USR2_BRCD, sport->port.membase + USR2);
671 if (uart_handle_break(&sport->port))
672 continue;
673 }
674
675 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
676 continue;
677
678 if (unlikely(rx & URXD_ERR)) {
679 if (rx & URXD_BRK)
680 sport->port.icount.brk++;
681 else if (rx & URXD_PRERR)
682 sport->port.icount.parity++;
683 else if (rx & URXD_FRMERR)
684 sport->port.icount.frame++;
685 if (rx & URXD_OVRRUN)
686 sport->port.icount.overrun++;
687
688 if (rx & sport->port.ignore_status_mask) {
689 if (++ignored > 100)
690 goto out;
691 continue;
692 }
693
694 rx &= sport->port.read_status_mask;
695
696 if (rx & URXD_BRK)
697 flg = TTY_BREAK;
698 else if (rx & URXD_PRERR)
699 flg = TTY_PARITY;
700 else if (rx & URXD_FRMERR)
701 flg = TTY_FRAME;
702 if (rx & URXD_OVRRUN)
703 flg = TTY_OVERRUN;
704
705 #ifdef SUPPORT_SYSRQ
706 sport->port.sysrq = 0;
707 #endif
708 }
709
710 tty_insert_flip_char(port, rx, flg);
711 }
712
713 out:
714 spin_unlock_irqrestore(&sport->port.lock, flags);
715 tty_flip_buffer_push(port);
716 return IRQ_HANDLED;
717 }
718
719 static int start_rx_dma(struct imx_port *sport);
720 /*
721 * If the RXFIFO is filled with some data, and then we
722 * arise a DMA operation to receive them.
723 */
724 static void imx_dma_rxint(struct imx_port *sport)
725 {
726 unsigned long temp;
727
728 temp = readl(sport->port.membase + USR2);
729 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
730 sport->dma_is_rxing = 1;
731
732 /* disable the `Recerver Ready Interrrupt` */
733 temp = readl(sport->port.membase + UCR1);
734 temp &= ~(UCR1_RRDYEN);
735 writel(temp, sport->port.membase + UCR1);
736
737 /* tell the DMA to receive the data. */
738 start_rx_dma(sport);
739 }
740 }
741
742 static irqreturn_t imx_int(int irq, void *dev_id)
743 {
744 struct imx_port *sport = dev_id;
745 unsigned int sts;
746 unsigned int sts2;
747
748 sts = readl(sport->port.membase + USR1);
749
750 if (sts & USR1_RRDY) {
751 if (sport->dma_is_enabled)
752 imx_dma_rxint(sport);
753 else
754 imx_rxint(irq, dev_id);
755 }
756
757 if (sts & USR1_TRDY &&
758 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
759 imx_txint(irq, dev_id);
760
761 if (sts & USR1_RTSD)
762 imx_rtsint(irq, dev_id);
763
764 if (sts & USR1_AWAKE)
765 writel(USR1_AWAKE, sport->port.membase + USR1);
766
767 sts2 = readl(sport->port.membase + USR2);
768 if (sts2 & USR2_ORE) {
769 dev_err(sport->port.dev, "Rx FIFO overrun\n");
770 sport->port.icount.overrun++;
771 writel(sts2 | USR2_ORE, sport->port.membase + USR2);
772 }
773
774 return IRQ_HANDLED;
775 }
776
777 /*
778 * Return TIOCSER_TEMT when transmitter is not busy.
779 */
780 static unsigned int imx_tx_empty(struct uart_port *port)
781 {
782 struct imx_port *sport = (struct imx_port *)port;
783 unsigned int ret;
784
785 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
786
787 /* If the TX DMA is working, return 0. */
788 if (sport->dma_is_enabled && sport->dma_is_txing)
789 ret = 0;
790
791 return ret;
792 }
793
794 /*
795 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
796 */
797 static unsigned int imx_get_mctrl(struct uart_port *port)
798 {
799 struct imx_port *sport = (struct imx_port *)port;
800 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
801
802 if (readl(sport->port.membase + USR1) & USR1_RTSS)
803 tmp |= TIOCM_CTS;
804
805 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
806 tmp |= TIOCM_RTS;
807
808 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
809 tmp |= TIOCM_LOOP;
810
811 return tmp;
812 }
813
814 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
815 {
816 struct imx_port *sport = (struct imx_port *)port;
817 unsigned long temp;
818
819 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
820
821 if (mctrl & TIOCM_RTS)
822 if (!sport->dma_is_enabled)
823 temp |= UCR2_CTS;
824
825 writel(temp, sport->port.membase + UCR2);
826
827 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
828 if (mctrl & TIOCM_LOOP)
829 temp |= UTS_LOOP;
830 writel(temp, sport->port.membase + uts_reg(sport));
831 }
832
833 /*
834 * Interrupts always disabled.
835 */
836 static void imx_break_ctl(struct uart_port *port, int break_state)
837 {
838 struct imx_port *sport = (struct imx_port *)port;
839 unsigned long flags, temp;
840
841 spin_lock_irqsave(&sport->port.lock, flags);
842
843 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
844
845 if (break_state != 0)
846 temp |= UCR1_SNDBRK;
847
848 writel(temp, sport->port.membase + UCR1);
849
850 spin_unlock_irqrestore(&sport->port.lock, flags);
851 }
852
853 #define TXTL 2 /* reset default */
854 #define RXTL 1 /* reset default */
855
856 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
857 {
858 unsigned int val;
859
860 /* set receiver / transmitter trigger level */
861 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
862 val |= TXTL << UFCR_TXTL_SHF | RXTL;
863 writel(val, sport->port.membase + UFCR);
864 return 0;
865 }
866
867 #define RX_BUF_SIZE (PAGE_SIZE)
868 static void imx_rx_dma_done(struct imx_port *sport)
869 {
870 unsigned long temp;
871
872 /* Enable this interrupt when the RXFIFO is empty. */
873 temp = readl(sport->port.membase + UCR1);
874 temp |= UCR1_RRDYEN;
875 writel(temp, sport->port.membase + UCR1);
876
877 sport->dma_is_rxing = 0;
878
879 /* Is the shutdown waiting for us? */
880 if (waitqueue_active(&sport->dma_wait))
881 wake_up(&sport->dma_wait);
882 }
883
884 /*
885 * There are three kinds of RX DMA interrupts(such as in the MX6Q):
886 * [1] the RX DMA buffer is full.
887 * [2] the Aging timer expires(wait for 8 bytes long)
888 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
889 *
890 * The [2] is trigger when a character was been sitting in the FIFO
891 * meanwhile [3] can wait for 32 bytes long when the RX line is
892 * on IDLE state and RxFIFO is empty.
893 */
894 static void dma_rx_callback(void *data)
895 {
896 struct imx_port *sport = data;
897 struct dma_chan *chan = sport->dma_chan_rx;
898 struct scatterlist *sgl = &sport->rx_sgl;
899 struct tty_port *port = &sport->port.state->port;
900 struct dma_tx_state state;
901 enum dma_status status;
902 unsigned int count;
903
904 /* unmap it first */
905 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
906
907 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
908 count = RX_BUF_SIZE - state.residue;
909 dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
910
911 if (count) {
912 tty_insert_flip_string(port, sport->rx_buf, count);
913 tty_flip_buffer_push(port);
914
915 start_rx_dma(sport);
916 } else
917 imx_rx_dma_done(sport);
918 }
919
920 static int start_rx_dma(struct imx_port *sport)
921 {
922 struct scatterlist *sgl = &sport->rx_sgl;
923 struct dma_chan *chan = sport->dma_chan_rx;
924 struct device *dev = sport->port.dev;
925 struct dma_async_tx_descriptor *desc;
926 int ret;
927
928 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
929 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
930 if (ret == 0) {
931 dev_err(dev, "DMA mapping error for RX.\n");
932 return -EINVAL;
933 }
934 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
935 DMA_PREP_INTERRUPT);
936 if (!desc) {
937 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
938 return -EINVAL;
939 }
940 desc->callback = dma_rx_callback;
941 desc->callback_param = sport;
942
943 dev_dbg(dev, "RX: prepare for the DMA.\n");
944 dmaengine_submit(desc);
945 dma_async_issue_pending(chan);
946 return 0;
947 }
948
949 static void imx_uart_dma_exit(struct imx_port *sport)
950 {
951 if (sport->dma_chan_rx) {
952 dma_release_channel(sport->dma_chan_rx);
953 sport->dma_chan_rx = NULL;
954
955 kfree(sport->rx_buf);
956 sport->rx_buf = NULL;
957 }
958
959 if (sport->dma_chan_tx) {
960 dma_release_channel(sport->dma_chan_tx);
961 sport->dma_chan_tx = NULL;
962 }
963
964 sport->dma_is_inited = 0;
965 }
966
967 static int imx_uart_dma_init(struct imx_port *sport)
968 {
969 struct dma_slave_config slave_config = {};
970 struct device *dev = sport->port.dev;
971 int ret;
972
973 /* Prepare for RX : */
974 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
975 if (!sport->dma_chan_rx) {
976 dev_dbg(dev, "cannot get the DMA channel.\n");
977 ret = -EINVAL;
978 goto err;
979 }
980
981 slave_config.direction = DMA_DEV_TO_MEM;
982 slave_config.src_addr = sport->port.mapbase + URXD0;
983 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
984 slave_config.src_maxburst = RXTL;
985 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
986 if (ret) {
987 dev_err(dev, "error in RX dma configuration.\n");
988 goto err;
989 }
990
991 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
992 if (!sport->rx_buf) {
993 dev_err(dev, "cannot alloc DMA buffer.\n");
994 ret = -ENOMEM;
995 goto err;
996 }
997
998 /* Prepare for TX : */
999 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1000 if (!sport->dma_chan_tx) {
1001 dev_err(dev, "cannot get the TX DMA channel!\n");
1002 ret = -EINVAL;
1003 goto err;
1004 }
1005
1006 slave_config.direction = DMA_MEM_TO_DEV;
1007 slave_config.dst_addr = sport->port.mapbase + URTX0;
1008 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1009 slave_config.dst_maxburst = TXTL;
1010 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1011 if (ret) {
1012 dev_err(dev, "error in TX dma configuration.");
1013 goto err;
1014 }
1015
1016 sport->dma_is_inited = 1;
1017
1018 return 0;
1019 err:
1020 imx_uart_dma_exit(sport);
1021 return ret;
1022 }
1023
1024 static void imx_enable_dma(struct imx_port *sport)
1025 {
1026 unsigned long temp;
1027
1028 init_waitqueue_head(&sport->dma_wait);
1029
1030 /* set UCR1 */
1031 temp = readl(sport->port.membase + UCR1);
1032 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
1033 /* wait for 32 idle frames for IDDMA interrupt */
1034 UCR1_ICD_REG(3);
1035 writel(temp, sport->port.membase + UCR1);
1036
1037 /* set UCR4 */
1038 temp = readl(sport->port.membase + UCR4);
1039 temp |= UCR4_IDDMAEN;
1040 writel(temp, sport->port.membase + UCR4);
1041
1042 sport->dma_is_enabled = 1;
1043 }
1044
1045 static void imx_disable_dma(struct imx_port *sport)
1046 {
1047 unsigned long temp;
1048
1049 /* clear UCR1 */
1050 temp = readl(sport->port.membase + UCR1);
1051 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1052 writel(temp, sport->port.membase + UCR1);
1053
1054 /* clear UCR2 */
1055 temp = readl(sport->port.membase + UCR2);
1056 temp &= ~(UCR2_CTSC | UCR2_CTS);
1057 writel(temp, sport->port.membase + UCR2);
1058
1059 /* clear UCR4 */
1060 temp = readl(sport->port.membase + UCR4);
1061 temp &= ~UCR4_IDDMAEN;
1062 writel(temp, sport->port.membase + UCR4);
1063
1064 sport->dma_is_enabled = 0;
1065 }
1066
1067 /* half the RX buffer size */
1068 #define CTSTL 16
1069
1070 static int imx_startup(struct uart_port *port)
1071 {
1072 struct imx_port *sport = (struct imx_port *)port;
1073 int retval, i;
1074 unsigned long flags, temp;
1075
1076 retval = clk_prepare_enable(sport->clk_per);
1077 if (retval)
1078 goto error_out1;
1079 retval = clk_prepare_enable(sport->clk_ipg);
1080 if (retval) {
1081 clk_disable_unprepare(sport->clk_per);
1082 goto error_out1;
1083 }
1084
1085 imx_setup_ufcr(sport, 0);
1086
1087 /* disable the DREN bit (Data Ready interrupt enable) before
1088 * requesting IRQs
1089 */
1090 temp = readl(sport->port.membase + UCR4);
1091
1092 if (USE_IRDA(sport))
1093 temp |= UCR4_IRSC;
1094
1095 /* set the trigger level for CTS */
1096 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1097 temp |= CTSTL << UCR4_CTSTL_SHF;
1098
1099 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1100
1101 /* Reset fifo's and state machines */
1102 i = 100;
1103
1104 temp = readl(sport->port.membase + UCR2);
1105 temp &= ~UCR2_SRST;
1106 writel(temp, sport->port.membase + UCR2);
1107
1108 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1109 udelay(1);
1110
1111 /*
1112 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
1113 * chips only have one interrupt.
1114 */
1115 if (sport->txirq > 0) {
1116 retval = request_irq(sport->rxirq, imx_rxint, 0,
1117 dev_name(port->dev), sport);
1118 if (retval)
1119 goto error_out1;
1120
1121 retval = request_irq(sport->txirq, imx_txint, 0,
1122 dev_name(port->dev), sport);
1123 if (retval)
1124 goto error_out2;
1125
1126 /* do not use RTS IRQ on IrDA */
1127 if (!USE_IRDA(sport)) {
1128 retval = request_irq(sport->rtsirq, imx_rtsint, 0,
1129 dev_name(port->dev), sport);
1130 if (retval)
1131 goto error_out3;
1132 }
1133 } else {
1134 retval = request_irq(sport->port.irq, imx_int, 0,
1135 dev_name(port->dev), sport);
1136 if (retval) {
1137 free_irq(sport->port.irq, sport);
1138 goto error_out1;
1139 }
1140 }
1141
1142 spin_lock_irqsave(&sport->port.lock, flags);
1143 /*
1144 * Finally, clear and enable interrupts
1145 */
1146 writel(USR1_RTSD, sport->port.membase + USR1);
1147
1148 temp = readl(sport->port.membase + UCR1);
1149 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
1150
1151 if (USE_IRDA(sport)) {
1152 temp |= UCR1_IREN;
1153 temp &= ~(UCR1_RTSDEN);
1154 }
1155
1156 writel(temp, sport->port.membase + UCR1);
1157
1158 temp = readl(sport->port.membase + UCR2);
1159 temp |= (UCR2_RXEN | UCR2_TXEN);
1160 if (!sport->have_rtscts)
1161 temp |= UCR2_IRTS;
1162 writel(temp, sport->port.membase + UCR2);
1163
1164 if (USE_IRDA(sport)) {
1165 /* clear RX-FIFO */
1166 int i = 64;
1167 while ((--i > 0) &&
1168 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
1169 barrier();
1170 }
1171 }
1172
1173 if (!is_imx1_uart(sport)) {
1174 temp = readl(sport->port.membase + UCR3);
1175 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
1176 writel(temp, sport->port.membase + UCR3);
1177 }
1178
1179 if (USE_IRDA(sport)) {
1180 temp = readl(sport->port.membase + UCR4);
1181 if (sport->irda_inv_rx)
1182 temp |= UCR4_INVR;
1183 else
1184 temp &= ~(UCR4_INVR);
1185 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
1186
1187 temp = readl(sport->port.membase + UCR3);
1188 if (sport->irda_inv_tx)
1189 temp |= UCR3_INVT;
1190 else
1191 temp &= ~(UCR3_INVT);
1192 writel(temp, sport->port.membase + UCR3);
1193 }
1194
1195 /*
1196 * Enable modem status interrupts
1197 */
1198 imx_enable_ms(&sport->port);
1199 spin_unlock_irqrestore(&sport->port.lock, flags);
1200
1201 if (USE_IRDA(sport)) {
1202 struct imxuart_platform_data *pdata;
1203 pdata = dev_get_platdata(sport->port.dev);
1204 sport->irda_inv_rx = pdata->irda_inv_rx;
1205 sport->irda_inv_tx = pdata->irda_inv_tx;
1206 sport->trcv_delay = pdata->transceiver_delay;
1207 if (pdata->irda_enable)
1208 pdata->irda_enable(1);
1209 }
1210
1211 return 0;
1212
1213 error_out3:
1214 if (sport->txirq)
1215 free_irq(sport->txirq, sport);
1216 error_out2:
1217 if (sport->rxirq)
1218 free_irq(sport->rxirq, sport);
1219 error_out1:
1220 return retval;
1221 }
1222
1223 static void imx_shutdown(struct uart_port *port)
1224 {
1225 struct imx_port *sport = (struct imx_port *)port;
1226 unsigned long temp;
1227 unsigned long flags;
1228
1229 if (sport->dma_is_enabled) {
1230 /* We have to wait for the DMA to finish. */
1231 wait_event(sport->dma_wait,
1232 !sport->dma_is_rxing && !sport->dma_is_txing);
1233 imx_stop_rx(port);
1234 imx_disable_dma(sport);
1235 imx_uart_dma_exit(sport);
1236 }
1237
1238 spin_lock_irqsave(&sport->port.lock, flags);
1239 temp = readl(sport->port.membase + UCR2);
1240 temp &= ~(UCR2_TXEN);
1241 writel(temp, sport->port.membase + UCR2);
1242 spin_unlock_irqrestore(&sport->port.lock, flags);
1243
1244 if (USE_IRDA(sport)) {
1245 struct imxuart_platform_data *pdata;
1246 pdata = dev_get_platdata(sport->port.dev);
1247 if (pdata->irda_enable)
1248 pdata->irda_enable(0);
1249 }
1250
1251 /*
1252 * Stop our timer.
1253 */
1254 del_timer_sync(&sport->timer);
1255
1256 /*
1257 * Free the interrupts
1258 */
1259 if (sport->txirq > 0) {
1260 if (!USE_IRDA(sport))
1261 free_irq(sport->rtsirq, sport);
1262 free_irq(sport->txirq, sport);
1263 free_irq(sport->rxirq, sport);
1264 } else
1265 free_irq(sport->port.irq, sport);
1266
1267 /*
1268 * Disable all interrupts, port and break condition.
1269 */
1270
1271 spin_lock_irqsave(&sport->port.lock, flags);
1272 temp = readl(sport->port.membase + UCR1);
1273 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1274 if (USE_IRDA(sport))
1275 temp &= ~(UCR1_IREN);
1276
1277 writel(temp, sport->port.membase + UCR1);
1278 spin_unlock_irqrestore(&sport->port.lock, flags);
1279
1280 clk_disable_unprepare(sport->clk_per);
1281 clk_disable_unprepare(sport->clk_ipg);
1282 }
1283
1284 static void imx_flush_buffer(struct uart_port *port)
1285 {
1286 struct imx_port *sport = (struct imx_port *)port;
1287
1288 if (sport->dma_is_enabled) {
1289 sport->tx_bytes = 0;
1290 dmaengine_terminate_all(sport->dma_chan_tx);
1291 }
1292 }
1293
1294 static void
1295 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1296 struct ktermios *old)
1297 {
1298 struct imx_port *sport = (struct imx_port *)port;
1299 unsigned long flags;
1300 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
1301 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1302 unsigned int div, ufcr;
1303 unsigned long num, denom;
1304 uint64_t tdiv64;
1305
1306 /*
1307 * If we don't support modem control lines, don't allow
1308 * these to be set.
1309 */
1310 if (0) {
1311 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
1312 termios->c_cflag |= CLOCAL;
1313 }
1314
1315 /*
1316 * We only support CS7 and CS8.
1317 */
1318 while ((termios->c_cflag & CSIZE) != CS7 &&
1319 (termios->c_cflag & CSIZE) != CS8) {
1320 termios->c_cflag &= ~CSIZE;
1321 termios->c_cflag |= old_csize;
1322 old_csize = CS8;
1323 }
1324
1325 if ((termios->c_cflag & CSIZE) == CS8)
1326 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1327 else
1328 ucr2 = UCR2_SRST | UCR2_IRTS;
1329
1330 if (termios->c_cflag & CRTSCTS) {
1331 if (sport->have_rtscts) {
1332 ucr2 &= ~UCR2_IRTS;
1333 ucr2 |= UCR2_CTSC;
1334
1335 /* Can we enable the DMA support? */
1336 if (is_imx6q_uart(sport) && !uart_console(port)
1337 && !sport->dma_is_inited)
1338 imx_uart_dma_init(sport);
1339 } else {
1340 termios->c_cflag &= ~CRTSCTS;
1341 }
1342 }
1343
1344 if (termios->c_cflag & CSTOPB)
1345 ucr2 |= UCR2_STPB;
1346 if (termios->c_cflag & PARENB) {
1347 ucr2 |= UCR2_PREN;
1348 if (termios->c_cflag & PARODD)
1349 ucr2 |= UCR2_PROE;
1350 }
1351
1352 del_timer_sync(&sport->timer);
1353
1354 /*
1355 * Ask the core to calculate the divisor for us.
1356 */
1357 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1358 quot = uart_get_divisor(port, baud);
1359
1360 spin_lock_irqsave(&sport->port.lock, flags);
1361
1362 sport->port.read_status_mask = 0;
1363 if (termios->c_iflag & INPCK)
1364 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1365 if (termios->c_iflag & (BRKINT | PARMRK))
1366 sport->port.read_status_mask |= URXD_BRK;
1367
1368 /*
1369 * Characters to ignore
1370 */
1371 sport->port.ignore_status_mask = 0;
1372 if (termios->c_iflag & IGNPAR)
1373 sport->port.ignore_status_mask |= URXD_PRERR;
1374 if (termios->c_iflag & IGNBRK) {
1375 sport->port.ignore_status_mask |= URXD_BRK;
1376 /*
1377 * If we're ignoring parity and break indicators,
1378 * ignore overruns too (for real raw support).
1379 */
1380 if (termios->c_iflag & IGNPAR)
1381 sport->port.ignore_status_mask |= URXD_OVRRUN;
1382 }
1383
1384 /*
1385 * Update the per-port timeout.
1386 */
1387 uart_update_timeout(port, termios->c_cflag, baud);
1388
1389 /*
1390 * disable interrupts and drain transmitter
1391 */
1392 old_ucr1 = readl(sport->port.membase + UCR1);
1393 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1394 sport->port.membase + UCR1);
1395
1396 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1397 barrier();
1398
1399 /* then, disable everything */
1400 old_txrxen = readl(sport->port.membase + UCR2);
1401 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
1402 sport->port.membase + UCR2);
1403 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1404
1405 if (USE_IRDA(sport)) {
1406 /*
1407 * use maximum available submodule frequency to
1408 * avoid missing short pulses due to low sampling rate
1409 */
1410 div = 1;
1411 } else {
1412 /* custom-baudrate handling */
1413 div = sport->port.uartclk / (baud * 16);
1414 if (baud == 38400 && quot != div)
1415 baud = sport->port.uartclk / (quot * 16);
1416
1417 div = sport->port.uartclk / (baud * 16);
1418 if (div > 7)
1419 div = 7;
1420 if (!div)
1421 div = 1;
1422 }
1423
1424 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1425 1 << 16, 1 << 16, &num, &denom);
1426
1427 tdiv64 = sport->port.uartclk;
1428 tdiv64 *= num;
1429 do_div(tdiv64, denom * 16 * div);
1430 tty_termios_encode_baud_rate(termios,
1431 (speed_t)tdiv64, (speed_t)tdiv64);
1432
1433 num -= 1;
1434 denom -= 1;
1435
1436 ufcr = readl(sport->port.membase + UFCR);
1437 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1438 if (sport->dte_mode)
1439 ufcr |= UFCR_DCEDTE;
1440 writel(ufcr, sport->port.membase + UFCR);
1441
1442 writel(num, sport->port.membase + UBIR);
1443 writel(denom, sport->port.membase + UBMR);
1444
1445 if (!is_imx1_uart(sport))
1446 writel(sport->port.uartclk / div / 1000,
1447 sport->port.membase + IMX21_ONEMS);
1448
1449 writel(old_ucr1, sport->port.membase + UCR1);
1450
1451 /* set the parity, stop bits and data size */
1452 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1453
1454 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1455 imx_enable_ms(&sport->port);
1456
1457 if (sport->dma_is_inited && !sport->dma_is_enabled)
1458 imx_enable_dma(sport);
1459 spin_unlock_irqrestore(&sport->port.lock, flags);
1460 }
1461
1462 static const char *imx_type(struct uart_port *port)
1463 {
1464 struct imx_port *sport = (struct imx_port *)port;
1465
1466 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1467 }
1468
1469 /*
1470 * Configure/autoconfigure the port.
1471 */
1472 static void imx_config_port(struct uart_port *port, int flags)
1473 {
1474 struct imx_port *sport = (struct imx_port *)port;
1475
1476 if (flags & UART_CONFIG_TYPE)
1477 sport->port.type = PORT_IMX;
1478 }
1479
1480 /*
1481 * Verify the new serial_struct (for TIOCSSERIAL).
1482 * The only change we allow are to the flags and type, and
1483 * even then only between PORT_IMX and PORT_UNKNOWN
1484 */
1485 static int
1486 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1487 {
1488 struct imx_port *sport = (struct imx_port *)port;
1489 int ret = 0;
1490
1491 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1492 ret = -EINVAL;
1493 if (sport->port.irq != ser->irq)
1494 ret = -EINVAL;
1495 if (ser->io_type != UPIO_MEM)
1496 ret = -EINVAL;
1497 if (sport->port.uartclk / 16 != ser->baud_base)
1498 ret = -EINVAL;
1499 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1500 ret = -EINVAL;
1501 if (sport->port.iobase != ser->port)
1502 ret = -EINVAL;
1503 if (ser->hub6 != 0)
1504 ret = -EINVAL;
1505 return ret;
1506 }
1507
1508 #if defined(CONFIG_CONSOLE_POLL)
1509 static int imx_poll_get_char(struct uart_port *port)
1510 {
1511 struct imx_port_ucrs old_ucr;
1512 unsigned int status;
1513 unsigned char c;
1514
1515 /* save control registers */
1516 imx_port_ucrs_save(port, &old_ucr);
1517
1518 /* disable interrupts */
1519 writel(UCR1_UARTEN, port->membase + UCR1);
1520 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1521 port->membase + UCR2);
1522 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1523 port->membase + UCR3);
1524
1525 /* poll */
1526 do {
1527 status = readl(port->membase + USR2);
1528 } while (~status & USR2_RDR);
1529
1530 /* read */
1531 c = readl(port->membase + URXD0);
1532
1533 /* restore control registers */
1534 imx_port_ucrs_restore(port, &old_ucr);
1535
1536 return c;
1537 }
1538
1539 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1540 {
1541 struct imx_port_ucrs old_ucr;
1542 unsigned int status;
1543
1544 /* save control registers */
1545 imx_port_ucrs_save(port, &old_ucr);
1546
1547 /* disable interrupts */
1548 writel(UCR1_UARTEN, port->membase + UCR1);
1549 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1550 port->membase + UCR2);
1551 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1552 port->membase + UCR3);
1553
1554 /* drain */
1555 do {
1556 status = readl(port->membase + USR1);
1557 } while (~status & USR1_TRDY);
1558
1559 /* write */
1560 writel(c, port->membase + URTX0);
1561
1562 /* flush */
1563 do {
1564 status = readl(port->membase + USR2);
1565 } while (~status & USR2_TXDC);
1566
1567 /* restore control registers */
1568 imx_port_ucrs_restore(port, &old_ucr);
1569 }
1570 #endif
1571
1572 static struct uart_ops imx_pops = {
1573 .tx_empty = imx_tx_empty,
1574 .set_mctrl = imx_set_mctrl,
1575 .get_mctrl = imx_get_mctrl,
1576 .stop_tx = imx_stop_tx,
1577 .start_tx = imx_start_tx,
1578 .stop_rx = imx_stop_rx,
1579 .enable_ms = imx_enable_ms,
1580 .break_ctl = imx_break_ctl,
1581 .startup = imx_startup,
1582 .shutdown = imx_shutdown,
1583 .flush_buffer = imx_flush_buffer,
1584 .set_termios = imx_set_termios,
1585 .type = imx_type,
1586 .config_port = imx_config_port,
1587 .verify_port = imx_verify_port,
1588 #if defined(CONFIG_CONSOLE_POLL)
1589 .poll_get_char = imx_poll_get_char,
1590 .poll_put_char = imx_poll_put_char,
1591 #endif
1592 };
1593
1594 static struct imx_port *imx_ports[UART_NR];
1595
1596 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1597 static void imx_console_putchar(struct uart_port *port, int ch)
1598 {
1599 struct imx_port *sport = (struct imx_port *)port;
1600
1601 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1602 barrier();
1603
1604 writel(ch, sport->port.membase + URTX0);
1605 }
1606
1607 /*
1608 * Interrupts are disabled on entering
1609 */
1610 static void
1611 imx_console_write(struct console *co, const char *s, unsigned int count)
1612 {
1613 struct imx_port *sport = imx_ports[co->index];
1614 struct imx_port_ucrs old_ucr;
1615 unsigned int ucr1;
1616 unsigned long flags = 0;
1617 int locked = 1;
1618 int retval;
1619
1620 retval = clk_enable(sport->clk_per);
1621 if (retval)
1622 return;
1623 retval = clk_enable(sport->clk_ipg);
1624 if (retval) {
1625 clk_disable(sport->clk_per);
1626 return;
1627 }
1628
1629 if (sport->port.sysrq)
1630 locked = 0;
1631 else if (oops_in_progress)
1632 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1633 else
1634 spin_lock_irqsave(&sport->port.lock, flags);
1635
1636 /*
1637 * First, save UCR1/2/3 and then disable interrupts
1638 */
1639 imx_port_ucrs_save(&sport->port, &old_ucr);
1640 ucr1 = old_ucr.ucr1;
1641
1642 if (is_imx1_uart(sport))
1643 ucr1 |= IMX1_UCR1_UARTCLKEN;
1644 ucr1 |= UCR1_UARTEN;
1645 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1646
1647 writel(ucr1, sport->port.membase + UCR1);
1648
1649 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1650
1651 uart_console_write(&sport->port, s, count, imx_console_putchar);
1652
1653 /*
1654 * Finally, wait for transmitter to become empty
1655 * and restore UCR1/2/3
1656 */
1657 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1658
1659 imx_port_ucrs_restore(&sport->port, &old_ucr);
1660
1661 if (locked)
1662 spin_unlock_irqrestore(&sport->port.lock, flags);
1663
1664 clk_disable(sport->clk_ipg);
1665 clk_disable(sport->clk_per);
1666 }
1667
1668 /*
1669 * If the port was already initialised (eg, by a boot loader),
1670 * try to determine the current setup.
1671 */
1672 static void __init
1673 imx_console_get_options(struct imx_port *sport, int *baud,
1674 int *parity, int *bits)
1675 {
1676
1677 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1678 /* ok, the port was enabled */
1679 unsigned int ucr2, ubir, ubmr, uartclk;
1680 unsigned int baud_raw;
1681 unsigned int ucfr_rfdiv;
1682
1683 ucr2 = readl(sport->port.membase + UCR2);
1684
1685 *parity = 'n';
1686 if (ucr2 & UCR2_PREN) {
1687 if (ucr2 & UCR2_PROE)
1688 *parity = 'o';
1689 else
1690 *parity = 'e';
1691 }
1692
1693 if (ucr2 & UCR2_WS)
1694 *bits = 8;
1695 else
1696 *bits = 7;
1697
1698 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1699 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1700
1701 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1702 if (ucfr_rfdiv == 6)
1703 ucfr_rfdiv = 7;
1704 else
1705 ucfr_rfdiv = 6 - ucfr_rfdiv;
1706
1707 uartclk = clk_get_rate(sport->clk_per);
1708 uartclk /= ucfr_rfdiv;
1709
1710 { /*
1711 * The next code provides exact computation of
1712 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1713 * without need of float support or long long division,
1714 * which would be required to prevent 32bit arithmetic overflow
1715 */
1716 unsigned int mul = ubir + 1;
1717 unsigned int div = 16 * (ubmr + 1);
1718 unsigned int rem = uartclk % div;
1719
1720 baud_raw = (uartclk / div) * mul;
1721 baud_raw += (rem * mul + div / 2) / div;
1722 *baud = (baud_raw + 50) / 100 * 100;
1723 }
1724
1725 if (*baud != baud_raw)
1726 pr_info("Console IMX rounded baud rate from %d to %d\n",
1727 baud_raw, *baud);
1728 }
1729 }
1730
1731 static int __init
1732 imx_console_setup(struct console *co, char *options)
1733 {
1734 struct imx_port *sport;
1735 int baud = 9600;
1736 int bits = 8;
1737 int parity = 'n';
1738 int flow = 'n';
1739 int retval;
1740
1741 /*
1742 * Check whether an invalid uart number has been specified, and
1743 * if so, search for the first available port that does have
1744 * console support.
1745 */
1746 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1747 co->index = 0;
1748 sport = imx_ports[co->index];
1749 if (sport == NULL)
1750 return -ENODEV;
1751
1752 /* For setting the registers, we only need to enable the ipg clock. */
1753 retval = clk_prepare_enable(sport->clk_ipg);
1754 if (retval)
1755 goto error_console;
1756
1757 if (options)
1758 uart_parse_options(options, &baud, &parity, &bits, &flow);
1759 else
1760 imx_console_get_options(sport, &baud, &parity, &bits);
1761
1762 imx_setup_ufcr(sport, 0);
1763
1764 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1765
1766 clk_disable(sport->clk_ipg);
1767 if (retval) {
1768 clk_unprepare(sport->clk_ipg);
1769 goto error_console;
1770 }
1771
1772 retval = clk_prepare(sport->clk_per);
1773 if (retval)
1774 clk_disable_unprepare(sport->clk_ipg);
1775
1776 error_console:
1777 return retval;
1778 }
1779
1780 static struct uart_driver imx_reg;
1781 static struct console imx_console = {
1782 .name = DEV_NAME,
1783 .write = imx_console_write,
1784 .device = uart_console_device,
1785 .setup = imx_console_setup,
1786 .flags = CON_PRINTBUFFER,
1787 .index = -1,
1788 .data = &imx_reg,
1789 };
1790
1791 #define IMX_CONSOLE &imx_console
1792 #else
1793 #define IMX_CONSOLE NULL
1794 #endif
1795
1796 static struct uart_driver imx_reg = {
1797 .owner = THIS_MODULE,
1798 .driver_name = DRIVER_NAME,
1799 .dev_name = DEV_NAME,
1800 .major = SERIAL_IMX_MAJOR,
1801 .minor = MINOR_START,
1802 .nr = ARRAY_SIZE(imx_ports),
1803 .cons = IMX_CONSOLE,
1804 };
1805
1806 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1807 {
1808 struct imx_port *sport = platform_get_drvdata(dev);
1809 unsigned int val;
1810
1811 /* enable wakeup from i.MX UART */
1812 val = readl(sport->port.membase + UCR3);
1813 val |= UCR3_AWAKEN;
1814 writel(val, sport->port.membase + UCR3);
1815
1816 uart_suspend_port(&imx_reg, &sport->port);
1817
1818 return 0;
1819 }
1820
1821 static int serial_imx_resume(struct platform_device *dev)
1822 {
1823 struct imx_port *sport = platform_get_drvdata(dev);
1824 unsigned int val;
1825
1826 /* disable wakeup from i.MX UART */
1827 val = readl(sport->port.membase + UCR3);
1828 val &= ~UCR3_AWAKEN;
1829 writel(val, sport->port.membase + UCR3);
1830
1831 uart_resume_port(&imx_reg, &sport->port);
1832
1833 return 0;
1834 }
1835
1836 #ifdef CONFIG_OF
1837 /*
1838 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1839 * could successfully get all information from dt or a negative errno.
1840 */
1841 static int serial_imx_probe_dt(struct imx_port *sport,
1842 struct platform_device *pdev)
1843 {
1844 struct device_node *np = pdev->dev.of_node;
1845 const struct of_device_id *of_id =
1846 of_match_device(imx_uart_dt_ids, &pdev->dev);
1847 int ret;
1848
1849 if (!np)
1850 /* no device tree device */
1851 return 1;
1852
1853 ret = of_alias_get_id(np, "serial");
1854 if (ret < 0) {
1855 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1856 return ret;
1857 }
1858 sport->port.line = ret;
1859
1860 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1861 sport->have_rtscts = 1;
1862
1863 if (of_get_property(np, "fsl,irda-mode", NULL))
1864 sport->use_irda = 1;
1865
1866 if (of_get_property(np, "fsl,dte-mode", NULL))
1867 sport->dte_mode = 1;
1868
1869 sport->devdata = of_id->data;
1870
1871 return 0;
1872 }
1873 #else
1874 static inline int serial_imx_probe_dt(struct imx_port *sport,
1875 struct platform_device *pdev)
1876 {
1877 return 1;
1878 }
1879 #endif
1880
1881 static void serial_imx_probe_pdata(struct imx_port *sport,
1882 struct platform_device *pdev)
1883 {
1884 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
1885
1886 sport->port.line = pdev->id;
1887 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1888
1889 if (!pdata)
1890 return;
1891
1892 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1893 sport->have_rtscts = 1;
1894
1895 if (pdata->flags & IMXUART_IRDA)
1896 sport->use_irda = 1;
1897 }
1898
1899 static int serial_imx_probe(struct platform_device *pdev)
1900 {
1901 struct imx_port *sport;
1902 void __iomem *base;
1903 int ret = 0;
1904 struct resource *res;
1905
1906 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1907 if (!sport)
1908 return -ENOMEM;
1909
1910 ret = serial_imx_probe_dt(sport, pdev);
1911 if (ret > 0)
1912 serial_imx_probe_pdata(sport, pdev);
1913 else if (ret < 0)
1914 return ret;
1915
1916 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1917 base = devm_ioremap_resource(&pdev->dev, res);
1918 if (IS_ERR(base))
1919 return PTR_ERR(base);
1920
1921 sport->port.dev = &pdev->dev;
1922 sport->port.mapbase = res->start;
1923 sport->port.membase = base;
1924 sport->port.type = PORT_IMX,
1925 sport->port.iotype = UPIO_MEM;
1926 sport->port.irq = platform_get_irq(pdev, 0);
1927 sport->rxirq = platform_get_irq(pdev, 0);
1928 sport->txirq = platform_get_irq(pdev, 1);
1929 sport->rtsirq = platform_get_irq(pdev, 2);
1930 sport->port.fifosize = 32;
1931 sport->port.ops = &imx_pops;
1932 sport->port.flags = UPF_BOOT_AUTOCONF;
1933 init_timer(&sport->timer);
1934 sport->timer.function = imx_timeout;
1935 sport->timer.data = (unsigned long)sport;
1936
1937 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1938 if (IS_ERR(sport->clk_ipg)) {
1939 ret = PTR_ERR(sport->clk_ipg);
1940 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
1941 return ret;
1942 }
1943
1944 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1945 if (IS_ERR(sport->clk_per)) {
1946 ret = PTR_ERR(sport->clk_per);
1947 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
1948 return ret;
1949 }
1950
1951 sport->port.uartclk = clk_get_rate(sport->clk_per);
1952
1953 imx_ports[sport->port.line] = sport;
1954
1955 platform_set_drvdata(pdev, sport);
1956
1957 return uart_add_one_port(&imx_reg, &sport->port);
1958 }
1959
1960 static int serial_imx_remove(struct platform_device *pdev)
1961 {
1962 struct imx_port *sport = platform_get_drvdata(pdev);
1963
1964 return uart_remove_one_port(&imx_reg, &sport->port);
1965 }
1966
1967 static struct platform_driver serial_imx_driver = {
1968 .probe = serial_imx_probe,
1969 .remove = serial_imx_remove,
1970
1971 .suspend = serial_imx_suspend,
1972 .resume = serial_imx_resume,
1973 .id_table = imx_uart_devtype,
1974 .driver = {
1975 .name = "imx-uart",
1976 .owner = THIS_MODULE,
1977 .of_match_table = imx_uart_dt_ids,
1978 },
1979 };
1980
1981 static int __init imx_serial_init(void)
1982 {
1983 int ret;
1984
1985 pr_info("Serial: IMX driver\n");
1986
1987 ret = uart_register_driver(&imx_reg);
1988 if (ret)
1989 return ret;
1990
1991 ret = platform_driver_register(&serial_imx_driver);
1992 if (ret != 0)
1993 uart_unregister_driver(&imx_reg);
1994
1995 return ret;
1996 }
1997
1998 static void __exit imx_serial_exit(void)
1999 {
2000 platform_driver_unregister(&serial_imx_driver);
2001 uart_unregister_driver(&imx_reg);
2002 }
2003
2004 module_init(imx_serial_init);
2005 module_exit(imx_serial_exit);
2006
2007 MODULE_AUTHOR("Sascha Hauer");
2008 MODULE_DESCRIPTION("IMX generic serial port driver");
2009 MODULE_LICENSE("GPL");
2010 MODULE_ALIAS("platform:imx-uart");
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