2 * Driver for Motorola/Freescale IMX serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24 #include <linux/module.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial.h>
34 #include <linux/clk.h>
35 #include <linux/delay.h>
36 #include <linux/rational.h>
37 #include <linux/slab.h>
39 #include <linux/of_device.h>
41 #include <linux/dma-mapping.h>
44 #include <linux/platform_data/serial-imx.h>
45 #include <linux/platform_data/dma-imx.h>
47 #include "serial_mctrl_gpio.h"
49 /* Register definitions */
50 #define URXD0 0x0 /* Receiver Register */
51 #define URTX0 0x40 /* Transmitter Register */
52 #define UCR1 0x80 /* Control Register 1 */
53 #define UCR2 0x84 /* Control Register 2 */
54 #define UCR3 0x88 /* Control Register 3 */
55 #define UCR4 0x8c /* Control Register 4 */
56 #define UFCR 0x90 /* FIFO Control Register */
57 #define USR1 0x94 /* Status Register 1 */
58 #define USR2 0x98 /* Status Register 2 */
59 #define UESC 0x9c /* Escape Character Register */
60 #define UTIM 0xa0 /* Escape Timer Register */
61 #define UBIR 0xa4 /* BRM Incremental Register */
62 #define UBMR 0xa8 /* BRM Modulator Register */
63 #define UBRC 0xac /* Baud Rate Count Register */
64 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
65 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
66 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
68 /* UART Control Register Bit Fields.*/
69 #define URXD_DUMMY_READ (1<<16)
70 #define URXD_CHARRDY (1<<15)
71 #define URXD_ERR (1<<14)
72 #define URXD_OVRRUN (1<<13)
73 #define URXD_FRMERR (1<<12)
74 #define URXD_BRK (1<<11)
75 #define URXD_PRERR (1<<10)
76 #define URXD_RX_DATA (0xFF<<0)
77 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
78 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
79 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
80 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
81 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
82 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
83 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
84 #define UCR1_IREN (1<<7) /* Infrared interface enable */
85 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
86 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
87 #define UCR1_SNDBRK (1<<4) /* Send break */
88 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
89 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
90 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
91 #define UCR1_DOZE (1<<1) /* Doze */
92 #define UCR1_UARTEN (1<<0) /* UART enabled */
93 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
94 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
95 #define UCR2_CTSC (1<<13) /* CTS pin control */
96 #define UCR2_CTS (1<<12) /* Clear to send */
97 #define UCR2_ESCEN (1<<11) /* Escape enable */
98 #define UCR2_PREN (1<<8) /* Parity enable */
99 #define UCR2_PROE (1<<7) /* Parity odd/even */
100 #define UCR2_STPB (1<<6) /* Stop */
101 #define UCR2_WS (1<<5) /* Word size */
102 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
103 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
104 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
105 #define UCR2_RXEN (1<<1) /* Receiver enabled */
106 #define UCR2_SRST (1<<0) /* SW reset */
107 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
108 #define UCR3_PARERREN (1<<12) /* Parity enable */
109 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
110 #define UCR3_DSR (1<<10) /* Data set ready */
111 #define UCR3_DCD (1<<9) /* Data carrier detect */
112 #define UCR3_RI (1<<8) /* Ring indicator */
113 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
114 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
115 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
116 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
117 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
118 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
119 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
120 #define UCR3_BPEN (1<<0) /* Preset registers enable */
121 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
122 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
123 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
124 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
125 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
126 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
127 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
128 #define UCR4_IRSC (1<<5) /* IR special case */
129 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
130 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
131 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
132 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
133 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
134 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
135 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
136 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
137 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
138 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
139 #define USR1_RTSS (1<<14) /* RTS pin status */
140 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
141 #define USR1_RTSD (1<<12) /* RTS delta */
142 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
143 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
144 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
145 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
146 #define USR1_DTRD (1<<7) /* DTR Delta */
147 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
148 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
149 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
150 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
151 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
152 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
153 #define USR2_IDLE (1<<12) /* Idle condition */
154 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
155 #define USR2_RIIN (1<<9) /* Ring Indicator Input */
156 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
157 #define USR2_WAKE (1<<7) /* Wake */
158 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
159 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
160 #define USR2_TXDC (1<<3) /* Transmitter complete */
161 #define USR2_BRCD (1<<2) /* Break condition */
162 #define USR2_ORE (1<<1) /* Overrun error */
163 #define USR2_RDR (1<<0) /* Recv data ready */
164 #define UTS_FRCPERR (1<<13) /* Force parity error */
165 #define UTS_LOOP (1<<12) /* Loop tx and rx */
166 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
167 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
168 #define UTS_TXFULL (1<<4) /* TxFIFO full */
169 #define UTS_RXFULL (1<<3) /* RxFIFO full */
170 #define UTS_SOFTRST (1<<0) /* Software reset */
172 /* We've been assigned a range on the "Low-density serial ports" major */
173 #define SERIAL_IMX_MAJOR 207
174 #define MINOR_START 16
175 #define DEV_NAME "ttymxc"
178 * This determines how often we check the modem status signals
179 * for any change. They generally aren't connected to an IRQ
180 * so we have to poll them. We also check immediately before
181 * filling the TX fifo incase CTS has been dropped.
183 #define MCTRL_TIMEOUT (250*HZ/1000)
185 #define DRIVER_NAME "IMX-uart"
189 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
196 /* device type dependent stuff */
197 struct imx_uart_data
{
199 enum imx_uart_type devtype
;
203 struct uart_port port
;
204 struct timer_list timer
;
205 unsigned int old_status
;
206 unsigned int have_rtscts
:1;
207 unsigned int dte_mode
:1;
208 unsigned int irda_inv_rx
:1;
209 unsigned int irda_inv_tx
:1;
210 unsigned short trcv_delay
; /* transceiver delay */
213 const struct imx_uart_data
*devdata
;
215 struct mctrl_gpios
*gpios
;
218 unsigned int dma_is_inited
:1;
219 unsigned int dma_is_enabled
:1;
220 unsigned int dma_is_rxing
:1;
221 unsigned int dma_is_txing
:1;
222 struct dma_chan
*dma_chan_rx
, *dma_chan_tx
;
223 struct scatterlist rx_sgl
, tx_sgl
[2];
225 struct circ_buf rx_ring
;
226 unsigned int rx_periods
;
227 dma_cookie_t rx_cookie
;
228 unsigned int tx_bytes
;
229 unsigned int dma_tx_nents
;
230 wait_queue_head_t dma_wait
;
231 unsigned int saved_reg
[10];
235 struct imx_port_ucrs
{
241 static struct imx_uart_data imx_uart_devdata
[] = {
244 .devtype
= IMX1_UART
,
247 .uts_reg
= IMX21_UTS
,
248 .devtype
= IMX21_UART
,
251 .uts_reg
= IMX21_UTS
,
252 .devtype
= IMX6Q_UART
,
256 static const struct platform_device_id imx_uart_devtype
[] = {
259 .driver_data
= (kernel_ulong_t
) &imx_uart_devdata
[IMX1_UART
],
261 .name
= "imx21-uart",
262 .driver_data
= (kernel_ulong_t
) &imx_uart_devdata
[IMX21_UART
],
264 .name
= "imx6q-uart",
265 .driver_data
= (kernel_ulong_t
) &imx_uart_devdata
[IMX6Q_UART
],
270 MODULE_DEVICE_TABLE(platform
, imx_uart_devtype
);
272 static const struct of_device_id imx_uart_dt_ids
[] = {
273 { .compatible
= "fsl,imx6q-uart", .data
= &imx_uart_devdata
[IMX6Q_UART
], },
274 { .compatible
= "fsl,imx1-uart", .data
= &imx_uart_devdata
[IMX1_UART
], },
275 { .compatible
= "fsl,imx21-uart", .data
= &imx_uart_devdata
[IMX21_UART
], },
278 MODULE_DEVICE_TABLE(of
, imx_uart_dt_ids
);
280 static inline unsigned uts_reg(struct imx_port
*sport
)
282 return sport
->devdata
->uts_reg
;
285 static inline int is_imx1_uart(struct imx_port
*sport
)
287 return sport
->devdata
->devtype
== IMX1_UART
;
290 static inline int is_imx21_uart(struct imx_port
*sport
)
292 return sport
->devdata
->devtype
== IMX21_UART
;
295 static inline int is_imx6q_uart(struct imx_port
*sport
)
297 return sport
->devdata
->devtype
== IMX6Q_UART
;
300 * Save and restore functions for UCR1, UCR2 and UCR3 registers
302 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
303 static void imx_port_ucrs_save(struct uart_port
*port
,
304 struct imx_port_ucrs
*ucr
)
306 /* save control registers */
307 ucr
->ucr1
= readl(port
->membase
+ UCR1
);
308 ucr
->ucr2
= readl(port
->membase
+ UCR2
);
309 ucr
->ucr3
= readl(port
->membase
+ UCR3
);
312 static void imx_port_ucrs_restore(struct uart_port
*port
,
313 struct imx_port_ucrs
*ucr
)
315 /* restore control registers */
316 writel(ucr
->ucr1
, port
->membase
+ UCR1
);
317 writel(ucr
->ucr2
, port
->membase
+ UCR2
);
318 writel(ucr
->ucr3
, port
->membase
+ UCR3
);
322 static void imx_port_rts_active(struct imx_port
*sport
, unsigned long *ucr2
)
327 mctrl_gpio_set(sport
->gpios
, sport
->port
.mctrl
| TIOCM_RTS
);
330 static void imx_port_rts_inactive(struct imx_port
*sport
, unsigned long *ucr2
)
332 *ucr2
&= ~(UCR2_CTSC
| UCR2_CTS
);
334 mctrl_gpio_set(sport
->gpios
, sport
->port
.mctrl
& ~TIOCM_RTS
);
337 static void imx_port_rts_auto(struct imx_port
*sport
, unsigned long *ucr2
)
343 * interrupts disabled on entry
345 static void imx_stop_tx(struct uart_port
*port
)
347 struct imx_port
*sport
= (struct imx_port
*)port
;
351 * We are maybe in the SMP context, so if the DMA TX thread is running
352 * on other cpu, we have to wait for it to finish.
354 if (sport
->dma_is_enabled
&& sport
->dma_is_txing
)
357 temp
= readl(port
->membase
+ UCR1
);
358 writel(temp
& ~UCR1_TXMPTYEN
, port
->membase
+ UCR1
);
360 /* in rs485 mode disable transmitter if shifter is empty */
361 if (port
->rs485
.flags
& SER_RS485_ENABLED
&&
362 readl(port
->membase
+ USR2
) & USR2_TXDC
) {
363 temp
= readl(port
->membase
+ UCR2
);
364 if (port
->rs485
.flags
& SER_RS485_RTS_AFTER_SEND
)
365 imx_port_rts_inactive(sport
, &temp
);
367 imx_port_rts_active(sport
, &temp
);
369 writel(temp
, port
->membase
+ UCR2
);
371 temp
= readl(port
->membase
+ UCR4
);
373 writel(temp
, port
->membase
+ UCR4
);
378 * interrupts disabled on entry
380 static void imx_stop_rx(struct uart_port
*port
)
382 struct imx_port
*sport
= (struct imx_port
*)port
;
385 if (sport
->dma_is_enabled
&& sport
->dma_is_rxing
) {
386 if (sport
->port
.suspended
) {
387 dmaengine_terminate_all(sport
->dma_chan_rx
);
388 sport
->dma_is_rxing
= 0;
394 temp
= readl(sport
->port
.membase
+ UCR2
);
395 writel(temp
& ~UCR2_RXEN
, sport
->port
.membase
+ UCR2
);
397 /* disable the `Receiver Ready Interrrupt` */
398 temp
= readl(sport
->port
.membase
+ UCR1
);
399 writel(temp
& ~UCR1_RRDYEN
, sport
->port
.membase
+ UCR1
);
403 * Set the modem control timer to fire immediately.
405 static void imx_enable_ms(struct uart_port
*port
)
407 struct imx_port
*sport
= (struct imx_port
*)port
;
409 mod_timer(&sport
->timer
, jiffies
);
411 mctrl_gpio_enable_ms(sport
->gpios
);
414 static void imx_dma_tx(struct imx_port
*sport
);
415 static inline void imx_transmit_buffer(struct imx_port
*sport
)
417 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
420 if (sport
->port
.x_char
) {
422 writel(sport
->port
.x_char
, sport
->port
.membase
+ URTX0
);
423 sport
->port
.icount
.tx
++;
424 sport
->port
.x_char
= 0;
428 if (uart_circ_empty(xmit
) || uart_tx_stopped(&sport
->port
)) {
429 imx_stop_tx(&sport
->port
);
433 if (sport
->dma_is_enabled
) {
435 * We've just sent a X-char Ensure the TX DMA is enabled
436 * and the TX IRQ is disabled.
438 temp
= readl(sport
->port
.membase
+ UCR1
);
439 temp
&= ~UCR1_TXMPTYEN
;
440 if (sport
->dma_is_txing
) {
442 writel(temp
, sport
->port
.membase
+ UCR1
);
444 writel(temp
, sport
->port
.membase
+ UCR1
);
449 while (!uart_circ_empty(xmit
) &&
450 !(readl(sport
->port
.membase
+ uts_reg(sport
)) & UTS_TXFULL
)) {
451 /* send xmit->buf[xmit->tail]
452 * out the port here */
453 writel(xmit
->buf
[xmit
->tail
], sport
->port
.membase
+ URTX0
);
454 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
455 sport
->port
.icount
.tx
++;
458 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
459 uart_write_wakeup(&sport
->port
);
461 if (uart_circ_empty(xmit
))
462 imx_stop_tx(&sport
->port
);
465 static void dma_tx_callback(void *data
)
467 struct imx_port
*sport
= data
;
468 struct scatterlist
*sgl
= &sport
->tx_sgl
[0];
469 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
473 spin_lock_irqsave(&sport
->port
.lock
, flags
);
475 dma_unmap_sg(sport
->port
.dev
, sgl
, sport
->dma_tx_nents
, DMA_TO_DEVICE
);
477 temp
= readl(sport
->port
.membase
+ UCR1
);
478 temp
&= ~UCR1_TDMAEN
;
479 writel(temp
, sport
->port
.membase
+ UCR1
);
481 /* update the stat */
482 xmit
->tail
= (xmit
->tail
+ sport
->tx_bytes
) & (UART_XMIT_SIZE
- 1);
483 sport
->port
.icount
.tx
+= sport
->tx_bytes
;
485 dev_dbg(sport
->port
.dev
, "we finish the TX DMA.\n");
487 sport
->dma_is_txing
= 0;
489 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
491 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
492 uart_write_wakeup(&sport
->port
);
494 if (waitqueue_active(&sport
->dma_wait
)) {
495 wake_up(&sport
->dma_wait
);
496 dev_dbg(sport
->port
.dev
, "exit in %s.\n", __func__
);
500 spin_lock_irqsave(&sport
->port
.lock
, flags
);
501 if (!uart_circ_empty(xmit
) && !uart_tx_stopped(&sport
->port
))
503 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
506 static void imx_dma_tx(struct imx_port
*sport
)
508 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
509 struct scatterlist
*sgl
= sport
->tx_sgl
;
510 struct dma_async_tx_descriptor
*desc
;
511 struct dma_chan
*chan
= sport
->dma_chan_tx
;
512 struct device
*dev
= sport
->port
.dev
;
516 if (sport
->dma_is_txing
)
519 sport
->tx_bytes
= uart_circ_chars_pending(xmit
);
521 if (xmit
->tail
< xmit
->head
) {
522 sport
->dma_tx_nents
= 1;
523 sg_init_one(sgl
, xmit
->buf
+ xmit
->tail
, sport
->tx_bytes
);
525 sport
->dma_tx_nents
= 2;
526 sg_init_table(sgl
, 2);
527 sg_set_buf(sgl
, xmit
->buf
+ xmit
->tail
,
528 UART_XMIT_SIZE
- xmit
->tail
);
529 sg_set_buf(sgl
+ 1, xmit
->buf
, xmit
->head
);
532 ret
= dma_map_sg(dev
, sgl
, sport
->dma_tx_nents
, DMA_TO_DEVICE
);
534 dev_err(dev
, "DMA mapping error for TX.\n");
537 desc
= dmaengine_prep_slave_sg(chan
, sgl
, sport
->dma_tx_nents
,
538 DMA_MEM_TO_DEV
, DMA_PREP_INTERRUPT
);
540 dma_unmap_sg(dev
, sgl
, sport
->dma_tx_nents
,
542 dev_err(dev
, "We cannot prepare for the TX slave dma!\n");
545 desc
->callback
= dma_tx_callback
;
546 desc
->callback_param
= sport
;
548 dev_dbg(dev
, "TX: prepare to send %lu bytes by DMA.\n",
549 uart_circ_chars_pending(xmit
));
551 temp
= readl(sport
->port
.membase
+ UCR1
);
553 writel(temp
, sport
->port
.membase
+ UCR1
);
556 sport
->dma_is_txing
= 1;
557 dmaengine_submit(desc
);
558 dma_async_issue_pending(chan
);
563 * interrupts disabled on entry
565 static void imx_start_tx(struct uart_port
*port
)
567 struct imx_port
*sport
= (struct imx_port
*)port
;
570 if (port
->rs485
.flags
& SER_RS485_ENABLED
) {
571 temp
= readl(port
->membase
+ UCR2
);
572 if (port
->rs485
.flags
& SER_RS485_RTS_ON_SEND
)
573 imx_port_rts_inactive(sport
, &temp
);
575 imx_port_rts_active(sport
, &temp
);
576 if (!(port
->rs485
.flags
& SER_RS485_RX_DURING_TX
))
578 writel(temp
, port
->membase
+ UCR2
);
580 /* enable transmitter and shifter empty irq */
581 temp
= readl(port
->membase
+ UCR4
);
583 writel(temp
, port
->membase
+ UCR4
);
586 if (!sport
->dma_is_enabled
) {
587 temp
= readl(sport
->port
.membase
+ UCR1
);
588 writel(temp
| UCR1_TXMPTYEN
, sport
->port
.membase
+ UCR1
);
591 if (sport
->dma_is_enabled
) {
592 if (sport
->port
.x_char
) {
593 /* We have X-char to send, so enable TX IRQ and
594 * disable TX DMA to let TX interrupt to send X-char */
595 temp
= readl(sport
->port
.membase
+ UCR1
);
596 temp
&= ~UCR1_TDMAEN
;
597 temp
|= UCR1_TXMPTYEN
;
598 writel(temp
, sport
->port
.membase
+ UCR1
);
602 if (!uart_circ_empty(&port
->state
->xmit
) &&
603 !uart_tx_stopped(port
))
609 static irqreturn_t
imx_rtsint(int irq
, void *dev_id
)
611 struct imx_port
*sport
= dev_id
;
615 spin_lock_irqsave(&sport
->port
.lock
, flags
);
617 writel(USR1_RTSD
, sport
->port
.membase
+ USR1
);
618 val
= readl(sport
->port
.membase
+ USR1
) & USR1_RTSS
;
619 uart_handle_cts_change(&sport
->port
, !!val
);
620 wake_up_interruptible(&sport
->port
.state
->port
.delta_msr_wait
);
622 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
626 static irqreturn_t
imx_txint(int irq
, void *dev_id
)
628 struct imx_port
*sport
= dev_id
;
631 spin_lock_irqsave(&sport
->port
.lock
, flags
);
632 imx_transmit_buffer(sport
);
633 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
637 static irqreturn_t
imx_rxint(int irq
, void *dev_id
)
639 struct imx_port
*sport
= dev_id
;
640 unsigned int rx
, flg
, ignored
= 0;
641 struct tty_port
*port
= &sport
->port
.state
->port
;
642 unsigned long flags
, temp
;
644 spin_lock_irqsave(&sport
->port
.lock
, flags
);
646 while (readl(sport
->port
.membase
+ USR2
) & USR2_RDR
) {
648 sport
->port
.icount
.rx
++;
650 rx
= readl(sport
->port
.membase
+ URXD0
);
652 temp
= readl(sport
->port
.membase
+ USR2
);
653 if (temp
& USR2_BRCD
) {
654 writel(USR2_BRCD
, sport
->port
.membase
+ USR2
);
655 if (uart_handle_break(&sport
->port
))
659 if (uart_handle_sysrq_char(&sport
->port
, (unsigned char)rx
))
662 if (unlikely(rx
& URXD_ERR
)) {
664 sport
->port
.icount
.brk
++;
665 else if (rx
& URXD_PRERR
)
666 sport
->port
.icount
.parity
++;
667 else if (rx
& URXD_FRMERR
)
668 sport
->port
.icount
.frame
++;
669 if (rx
& URXD_OVRRUN
)
670 sport
->port
.icount
.overrun
++;
672 if (rx
& sport
->port
.ignore_status_mask
) {
678 rx
&= (sport
->port
.read_status_mask
| 0xFF);
682 else if (rx
& URXD_PRERR
)
684 else if (rx
& URXD_FRMERR
)
686 if (rx
& URXD_OVRRUN
)
690 sport
->port
.sysrq
= 0;
694 if (sport
->port
.ignore_status_mask
& URXD_DUMMY_READ
)
697 if (tty_insert_flip_char(port
, rx
, flg
) == 0)
698 sport
->port
.icount
.buf_overrun
++;
702 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
703 tty_flip_buffer_push(port
);
707 static void clear_rx_errors(struct imx_port
*sport
);
708 static int start_rx_dma(struct imx_port
*sport
);
710 * If the RXFIFO is filled with some data, and then we
711 * arise a DMA operation to receive them.
713 static void imx_dma_rxint(struct imx_port
*sport
)
718 spin_lock_irqsave(&sport
->port
.lock
, flags
);
720 temp
= readl(sport
->port
.membase
+ USR2
);
721 if ((temp
& USR2_RDR
) && !sport
->dma_is_rxing
) {
722 sport
->dma_is_rxing
= 1;
724 /* disable the receiver ready and aging timer interrupts */
725 temp
= readl(sport
->port
.membase
+ UCR1
);
726 temp
&= ~(UCR1_RRDYEN
);
727 writel(temp
, sport
->port
.membase
+ UCR1
);
729 temp
= readl(sport
->port
.membase
+ UCR2
);
730 temp
&= ~(UCR2_ATEN
);
731 writel(temp
, sport
->port
.membase
+ UCR2
);
733 /* disable the rx errors interrupts */
734 temp
= readl(sport
->port
.membase
+ UCR4
);
736 writel(temp
, sport
->port
.membase
+ UCR4
);
738 /* tell the DMA to receive the data. */
742 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
746 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
748 static unsigned int imx_get_hwmctrl(struct imx_port
*sport
)
750 unsigned int tmp
= TIOCM_DSR
;
751 unsigned usr1
= readl(sport
->port
.membase
+ USR1
);
753 if (usr1
& USR1_RTSS
)
756 /* in DCE mode DCDIN is always 0 */
757 if (!(usr1
& USR2_DCDIN
))
761 if (!(readl(sport
->port
.membase
+ USR2
) & USR2_RIIN
))
768 * Handle any change of modem status signal since we were last called.
770 static void imx_mctrl_check(struct imx_port
*sport
)
772 unsigned int status
, changed
;
774 status
= imx_get_hwmctrl(sport
);
775 changed
= status
^ sport
->old_status
;
780 sport
->old_status
= status
;
782 if (changed
& TIOCM_RI
&& status
& TIOCM_RI
)
783 sport
->port
.icount
.rng
++;
784 if (changed
& TIOCM_DSR
)
785 sport
->port
.icount
.dsr
++;
786 if (changed
& TIOCM_CAR
)
787 uart_handle_dcd_change(&sport
->port
, status
& TIOCM_CAR
);
788 if (changed
& TIOCM_CTS
)
789 uart_handle_cts_change(&sport
->port
, status
& TIOCM_CTS
);
791 wake_up_interruptible(&sport
->port
.state
->port
.delta_msr_wait
);
794 static irqreturn_t
imx_int(int irq
, void *dev_id
)
796 struct imx_port
*sport
= dev_id
;
799 irqreturn_t ret
= IRQ_NONE
;
801 sts
= readl(sport
->port
.membase
+ USR1
);
802 sts2
= readl(sport
->port
.membase
+ USR2
);
804 if (sts
& (USR1_RRDY
| USR1_AGTIM
)) {
805 if (sport
->dma_is_enabled
)
806 imx_dma_rxint(sport
);
808 imx_rxint(irq
, dev_id
);
812 if ((sts
& USR1_TRDY
&&
813 readl(sport
->port
.membase
+ UCR1
) & UCR1_TXMPTYEN
) ||
815 readl(sport
->port
.membase
+ UCR4
) & UCR4_TCEN
)) {
816 imx_txint(irq
, dev_id
);
820 if (sts
& USR1_DTRD
) {
824 writel(USR1_DTRD
, sport
->port
.membase
+ USR1
);
826 spin_lock_irqsave(&sport
->port
.lock
, flags
);
827 imx_mctrl_check(sport
);
828 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
833 if (sts
& USR1_RTSD
) {
834 imx_rtsint(irq
, dev_id
);
838 if (sts
& USR1_AWAKE
) {
839 writel(USR1_AWAKE
, sport
->port
.membase
+ USR1
);
843 if (sts2
& USR2_ORE
) {
844 sport
->port
.icount
.overrun
++;
845 writel(USR2_ORE
, sport
->port
.membase
+ USR2
);
853 * Return TIOCSER_TEMT when transmitter is not busy.
855 static unsigned int imx_tx_empty(struct uart_port
*port
)
857 struct imx_port
*sport
= (struct imx_port
*)port
;
860 ret
= (readl(sport
->port
.membase
+ USR2
) & USR2_TXDC
) ? TIOCSER_TEMT
: 0;
862 /* If the TX DMA is working, return 0. */
863 if (sport
->dma_is_enabled
&& sport
->dma_is_txing
)
869 static unsigned int imx_get_mctrl(struct uart_port
*port
)
871 struct imx_port
*sport
= (struct imx_port
*)port
;
872 unsigned int ret
= imx_get_hwmctrl(sport
);
874 mctrl_gpio_get(sport
->gpios
, &ret
);
879 static void imx_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
881 struct imx_port
*sport
= (struct imx_port
*)port
;
884 if (!(port
->rs485
.flags
& SER_RS485_ENABLED
)) {
885 temp
= readl(sport
->port
.membase
+ UCR2
);
886 temp
&= ~(UCR2_CTS
| UCR2_CTSC
);
887 if (mctrl
& TIOCM_RTS
)
888 temp
|= UCR2_CTS
| UCR2_CTSC
;
889 writel(temp
, sport
->port
.membase
+ UCR2
);
892 temp
= readl(sport
->port
.membase
+ UCR3
) & ~UCR3_DSR
;
893 if (!(mctrl
& TIOCM_DTR
))
895 writel(temp
, sport
->port
.membase
+ UCR3
);
897 temp
= readl(sport
->port
.membase
+ uts_reg(sport
)) & ~UTS_LOOP
;
898 if (mctrl
& TIOCM_LOOP
)
900 writel(temp
, sport
->port
.membase
+ uts_reg(sport
));
902 mctrl_gpio_set(sport
->gpios
, mctrl
);
906 * Interrupts always disabled.
908 static void imx_break_ctl(struct uart_port
*port
, int break_state
)
910 struct imx_port
*sport
= (struct imx_port
*)port
;
911 unsigned long flags
, temp
;
913 spin_lock_irqsave(&sport
->port
.lock
, flags
);
915 temp
= readl(sport
->port
.membase
+ UCR1
) & ~UCR1_SNDBRK
;
917 if (break_state
!= 0)
920 writel(temp
, sport
->port
.membase
+ UCR1
);
922 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
926 * This is our per-port timeout handler, for checking the
927 * modem status signals.
929 static void imx_timeout(unsigned long data
)
931 struct imx_port
*sport
= (struct imx_port
*)data
;
934 if (sport
->port
.state
) {
935 spin_lock_irqsave(&sport
->port
.lock
, flags
);
936 imx_mctrl_check(sport
);
937 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
939 mod_timer(&sport
->timer
, jiffies
+ MCTRL_TIMEOUT
);
943 #define RX_BUF_SIZE (PAGE_SIZE)
946 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
947 * [1] the RX DMA buffer is full.
948 * [2] the aging timer expires
950 * Condition [2] is triggered when a character has been sitting in the FIFO
951 * for at least 8 byte durations.
953 static void dma_rx_callback(void *data
)
955 struct imx_port
*sport
= data
;
956 struct dma_chan
*chan
= sport
->dma_chan_rx
;
957 struct scatterlist
*sgl
= &sport
->rx_sgl
;
958 struct tty_port
*port
= &sport
->port
.state
->port
;
959 struct dma_tx_state state
;
960 struct circ_buf
*rx_ring
= &sport
->rx_ring
;
961 enum dma_status status
;
962 unsigned int w_bytes
= 0;
963 unsigned int r_bytes
;
964 unsigned int bd_size
;
966 status
= dmaengine_tx_status(chan
, (dma_cookie_t
)0, &state
);
968 if (status
== DMA_ERROR
) {
969 dev_err(sport
->port
.dev
, "DMA transaction error.\n");
970 clear_rx_errors(sport
);
974 if (!(sport
->port
.ignore_status_mask
& URXD_DUMMY_READ
)) {
977 * The state-residue variable represents the empty space
978 * relative to the entire buffer. Taking this in consideration
979 * the head is always calculated base on the buffer total
980 * length - DMA transaction residue. The UART script from the
981 * SDMA firmware will jump to the next buffer descriptor,
982 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
983 * Taking this in consideration the tail is always at the
984 * beginning of the buffer descriptor that contains the head.
987 /* Calculate the head */
988 rx_ring
->head
= sg_dma_len(sgl
) - state
.residue
;
990 /* Calculate the tail. */
991 bd_size
= sg_dma_len(sgl
) / sport
->rx_periods
;
992 rx_ring
->tail
= ((rx_ring
->head
-1) / bd_size
) * bd_size
;
994 if (rx_ring
->head
<= sg_dma_len(sgl
) &&
995 rx_ring
->head
> rx_ring
->tail
) {
997 /* Move data from tail to head */
998 r_bytes
= rx_ring
->head
- rx_ring
->tail
;
1000 /* CPU claims ownership of RX DMA buffer */
1001 dma_sync_sg_for_cpu(sport
->port
.dev
, sgl
, 1,
1004 w_bytes
= tty_insert_flip_string(port
,
1005 sport
->rx_buf
+ rx_ring
->tail
, r_bytes
);
1007 /* UART retrieves ownership of RX DMA buffer */
1008 dma_sync_sg_for_device(sport
->port
.dev
, sgl
, 1,
1011 if (w_bytes
!= r_bytes
)
1012 sport
->port
.icount
.buf_overrun
++;
1014 sport
->port
.icount
.rx
+= w_bytes
;
1016 WARN_ON(rx_ring
->head
> sg_dma_len(sgl
));
1017 WARN_ON(rx_ring
->head
<= rx_ring
->tail
);
1022 tty_flip_buffer_push(port
);
1023 dev_dbg(sport
->port
.dev
, "We get %d bytes.\n", w_bytes
);
1027 /* RX DMA buffer periods */
1028 #define RX_DMA_PERIODS 4
1030 static int start_rx_dma(struct imx_port
*sport
)
1032 struct scatterlist
*sgl
= &sport
->rx_sgl
;
1033 struct dma_chan
*chan
= sport
->dma_chan_rx
;
1034 struct device
*dev
= sport
->port
.dev
;
1035 struct dma_async_tx_descriptor
*desc
;
1038 sport
->rx_ring
.head
= 0;
1039 sport
->rx_ring
.tail
= 0;
1040 sport
->rx_periods
= RX_DMA_PERIODS
;
1042 sg_init_one(sgl
, sport
->rx_buf
, RX_BUF_SIZE
);
1043 ret
= dma_map_sg(dev
, sgl
, 1, DMA_FROM_DEVICE
);
1045 dev_err(dev
, "DMA mapping error for RX.\n");
1049 desc
= dmaengine_prep_dma_cyclic(chan
, sg_dma_address(sgl
),
1050 sg_dma_len(sgl
), sg_dma_len(sgl
) / sport
->rx_periods
,
1051 DMA_DEV_TO_MEM
, DMA_PREP_INTERRUPT
);
1054 dma_unmap_sg(dev
, sgl
, 1, DMA_FROM_DEVICE
);
1055 dev_err(dev
, "We cannot prepare for the RX slave dma!\n");
1058 desc
->callback
= dma_rx_callback
;
1059 desc
->callback_param
= sport
;
1061 dev_dbg(dev
, "RX: prepare for the DMA.\n");
1062 sport
->rx_cookie
= dmaengine_submit(desc
);
1063 dma_async_issue_pending(chan
);
1067 static void clear_rx_errors(struct imx_port
*sport
)
1069 unsigned int status_usr1
, status_usr2
;
1071 status_usr1
= readl(sport
->port
.membase
+ USR1
);
1072 status_usr2
= readl(sport
->port
.membase
+ USR2
);
1074 if (status_usr2
& USR2_BRCD
) {
1075 sport
->port
.icount
.brk
++;
1076 writel(USR2_BRCD
, sport
->port
.membase
+ USR2
);
1077 } else if (status_usr1
& USR1_FRAMERR
) {
1078 sport
->port
.icount
.frame
++;
1079 writel(USR1_FRAMERR
, sport
->port
.membase
+ USR1
);
1080 } else if (status_usr1
& USR1_PARITYERR
) {
1081 sport
->port
.icount
.parity
++;
1082 writel(USR1_PARITYERR
, sport
->port
.membase
+ USR1
);
1085 if (status_usr2
& USR2_ORE
) {
1086 sport
->port
.icount
.overrun
++;
1087 writel(USR2_ORE
, sport
->port
.membase
+ USR2
);
1092 #define TXTL_DEFAULT 2 /* reset default */
1093 #define RXTL_DEFAULT 1 /* reset default */
1094 #define TXTL_DMA 8 /* DMA burst setting */
1095 #define RXTL_DMA 9 /* DMA burst setting */
1097 static void imx_setup_ufcr(struct imx_port
*sport
,
1098 unsigned char txwl
, unsigned char rxwl
)
1102 /* set receiver / transmitter trigger level */
1103 val
= readl(sport
->port
.membase
+ UFCR
) & (UFCR_RFDIV
| UFCR_DCEDTE
);
1104 val
|= txwl
<< UFCR_TXTL_SHF
| rxwl
;
1105 writel(val
, sport
->port
.membase
+ UFCR
);
1108 static void imx_uart_dma_exit(struct imx_port
*sport
)
1110 if (sport
->dma_chan_rx
) {
1111 dmaengine_terminate_all(sport
->dma_chan_rx
);
1112 dma_release_channel(sport
->dma_chan_rx
);
1113 sport
->dma_chan_rx
= NULL
;
1114 sport
->rx_cookie
= -EINVAL
;
1115 kfree(sport
->rx_buf
);
1116 sport
->rx_buf
= NULL
;
1119 if (sport
->dma_chan_tx
) {
1120 dmaengine_terminate_all(sport
->dma_chan_tx
);
1121 dma_release_channel(sport
->dma_chan_tx
);
1122 sport
->dma_chan_tx
= NULL
;
1125 sport
->dma_is_inited
= 0;
1128 static int imx_uart_dma_init(struct imx_port
*sport
)
1130 struct dma_slave_config slave_config
= {};
1131 struct device
*dev
= sport
->port
.dev
;
1134 /* Prepare for RX : */
1135 sport
->dma_chan_rx
= dma_request_slave_channel(dev
, "rx");
1136 if (!sport
->dma_chan_rx
) {
1137 dev_dbg(dev
, "cannot get the DMA channel.\n");
1142 slave_config
.direction
= DMA_DEV_TO_MEM
;
1143 slave_config
.src_addr
= sport
->port
.mapbase
+ URXD0
;
1144 slave_config
.src_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
1145 /* one byte less than the watermark level to enable the aging timer */
1146 slave_config
.src_maxburst
= RXTL_DMA
- 1;
1147 ret
= dmaengine_slave_config(sport
->dma_chan_rx
, &slave_config
);
1149 dev_err(dev
, "error in RX dma configuration.\n");
1153 sport
->rx_buf
= kzalloc(PAGE_SIZE
, GFP_KERNEL
);
1154 if (!sport
->rx_buf
) {
1158 sport
->rx_ring
.buf
= sport
->rx_buf
;
1160 /* Prepare for TX : */
1161 sport
->dma_chan_tx
= dma_request_slave_channel(dev
, "tx");
1162 if (!sport
->dma_chan_tx
) {
1163 dev_err(dev
, "cannot get the TX DMA channel!\n");
1168 slave_config
.direction
= DMA_MEM_TO_DEV
;
1169 slave_config
.dst_addr
= sport
->port
.mapbase
+ URTX0
;
1170 slave_config
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
1171 slave_config
.dst_maxburst
= TXTL_DMA
;
1172 ret
= dmaengine_slave_config(sport
->dma_chan_tx
, &slave_config
);
1174 dev_err(dev
, "error in TX dma configuration.");
1178 sport
->dma_is_inited
= 1;
1182 imx_uart_dma_exit(sport
);
1186 static void imx_enable_dma(struct imx_port
*sport
)
1190 init_waitqueue_head(&sport
->dma_wait
);
1193 temp
= readl(sport
->port
.membase
+ UCR1
);
1194 temp
|= UCR1_RDMAEN
| UCR1_TDMAEN
| UCR1_ATDMAEN
;
1195 writel(temp
, sport
->port
.membase
+ UCR1
);
1197 temp
= readl(sport
->port
.membase
+ UCR2
);
1199 writel(temp
, sport
->port
.membase
+ UCR2
);
1201 imx_setup_ufcr(sport
, TXTL_DMA
, RXTL_DMA
);
1203 sport
->dma_is_enabled
= 1;
1206 static void imx_disable_dma(struct imx_port
*sport
)
1211 temp
= readl(sport
->port
.membase
+ UCR1
);
1212 temp
&= ~(UCR1_RDMAEN
| UCR1_TDMAEN
| UCR1_ATDMAEN
);
1213 writel(temp
, sport
->port
.membase
+ UCR1
);
1216 temp
= readl(sport
->port
.membase
+ UCR2
);
1217 temp
&= ~(UCR2_CTSC
| UCR2_CTS
| UCR2_ATEN
);
1218 writel(temp
, sport
->port
.membase
+ UCR2
);
1220 imx_setup_ufcr(sport
, TXTL_DEFAULT
, RXTL_DEFAULT
);
1222 sport
->dma_is_enabled
= 0;
1225 /* half the RX buffer size */
1228 static int imx_startup(struct uart_port
*port
)
1230 struct imx_port
*sport
= (struct imx_port
*)port
;
1232 unsigned long flags
, temp
;
1234 retval
= clk_prepare_enable(sport
->clk_per
);
1237 retval
= clk_prepare_enable(sport
->clk_ipg
);
1239 clk_disable_unprepare(sport
->clk_per
);
1243 imx_setup_ufcr(sport
, TXTL_DEFAULT
, RXTL_DEFAULT
);
1245 /* disable the DREN bit (Data Ready interrupt enable) before
1248 temp
= readl(sport
->port
.membase
+ UCR4
);
1250 /* set the trigger level for CTS */
1251 temp
&= ~(UCR4_CTSTL_MASK
<< UCR4_CTSTL_SHF
);
1252 temp
|= CTSTL
<< UCR4_CTSTL_SHF
;
1254 writel(temp
& ~UCR4_DREN
, sport
->port
.membase
+ UCR4
);
1256 /* Can we enable the DMA support? */
1257 if (is_imx6q_uart(sport
) && !uart_console(port
) &&
1258 !sport
->dma_is_inited
)
1259 imx_uart_dma_init(sport
);
1261 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1262 /* Reset fifo's and state machines */
1265 temp
= readl(sport
->port
.membase
+ UCR2
);
1267 writel(temp
, sport
->port
.membase
+ UCR2
);
1269 while (!(readl(sport
->port
.membase
+ UCR2
) & UCR2_SRST
) && (--i
> 0))
1273 * Finally, clear and enable interrupts
1275 writel(USR1_RTSD
| USR1_DTRD
, sport
->port
.membase
+ USR1
);
1276 writel(USR2_ORE
, sport
->port
.membase
+ USR2
);
1278 if (sport
->dma_is_inited
&& !sport
->dma_is_enabled
)
1279 imx_enable_dma(sport
);
1281 temp
= readl(sport
->port
.membase
+ UCR1
);
1282 temp
|= UCR1_RRDYEN
| UCR1_RTSDEN
| UCR1_UARTEN
;
1284 writel(temp
, sport
->port
.membase
+ UCR1
);
1286 temp
= readl(sport
->port
.membase
+ UCR4
);
1288 writel(temp
, sport
->port
.membase
+ UCR4
);
1290 temp
= readl(sport
->port
.membase
+ UCR2
);
1291 temp
|= (UCR2_RXEN
| UCR2_TXEN
);
1292 if (!sport
->have_rtscts
)
1295 * make sure the edge sensitive RTS-irq is disabled,
1296 * we're using RTSD instead.
1298 if (!is_imx1_uart(sport
))
1299 temp
&= ~UCR2_RTSEN
;
1300 writel(temp
, sport
->port
.membase
+ UCR2
);
1302 if (!is_imx1_uart(sport
)) {
1303 temp
= readl(sport
->port
.membase
+ UCR3
);
1306 * The effect of RI and DCD differs depending on the UFCR_DCEDTE
1307 * bit. In DCE mode they control the outputs, in DTE mode they
1308 * enable the respective irqs. At least the DCD irq cannot be
1309 * cleared on i.MX25 at least, so it's not usable and must be
1310 * disabled. I don't have test hardware to check if RI has the
1311 * same problem but I consider this likely so it's disabled for
1314 temp
|= IMX21_UCR3_RXDMUXSEL
| UCR3_ADNIMP
|
1315 UCR3_DTRDEN
| UCR3_RI
| UCR3_DCD
;
1317 if (sport
->dte_mode
)
1318 temp
&= ~(UCR3_RI
| UCR3_DCD
);
1320 writel(temp
, sport
->port
.membase
+ UCR3
);
1324 * Enable modem status interrupts
1326 imx_enable_ms(&sport
->port
);
1327 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1332 static void imx_shutdown(struct uart_port
*port
)
1334 struct imx_port
*sport
= (struct imx_port
*)port
;
1336 unsigned long flags
;
1338 if (sport
->dma_is_enabled
) {
1339 sport
->dma_is_rxing
= 0;
1340 sport
->dma_is_txing
= 0;
1341 dmaengine_terminate_all(sport
->dma_chan_tx
);
1342 dmaengine_terminate_all(sport
->dma_chan_rx
);
1344 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1347 imx_disable_dma(sport
);
1348 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1349 imx_uart_dma_exit(sport
);
1352 mctrl_gpio_disable_ms(sport
->gpios
);
1354 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1355 temp
= readl(sport
->port
.membase
+ UCR2
);
1356 temp
&= ~(UCR2_TXEN
);
1357 writel(temp
, sport
->port
.membase
+ UCR2
);
1358 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1363 del_timer_sync(&sport
->timer
);
1366 * Disable all interrupts, port and break condition.
1369 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1370 temp
= readl(sport
->port
.membase
+ UCR1
);
1371 temp
&= ~(UCR1_TXMPTYEN
| UCR1_RRDYEN
| UCR1_RTSDEN
| UCR1_UARTEN
);
1373 writel(temp
, sport
->port
.membase
+ UCR1
);
1374 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1376 clk_disable_unprepare(sport
->clk_per
);
1377 clk_disable_unprepare(sport
->clk_ipg
);
1380 static void imx_flush_buffer(struct uart_port
*port
)
1382 struct imx_port
*sport
= (struct imx_port
*)port
;
1383 struct scatterlist
*sgl
= &sport
->tx_sgl
[0];
1385 int i
= 100, ubir
, ubmr
, uts
;
1387 if (!sport
->dma_chan_tx
)
1390 sport
->tx_bytes
= 0;
1391 dmaengine_terminate_all(sport
->dma_chan_tx
);
1392 if (sport
->dma_is_txing
) {
1393 dma_unmap_sg(sport
->port
.dev
, sgl
, sport
->dma_tx_nents
,
1395 temp
= readl(sport
->port
.membase
+ UCR1
);
1396 temp
&= ~UCR1_TDMAEN
;
1397 writel(temp
, sport
->port
.membase
+ UCR1
);
1398 sport
->dma_is_txing
= false;
1402 * According to the Reference Manual description of the UART SRST bit:
1403 * "Reset the transmit and receive state machines,
1404 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1405 * and UTS[6-3]". As we don't need to restore the old values from
1406 * USR1, USR2, URXD, UTXD, only save/restore the other four registers
1408 ubir
= readl(sport
->port
.membase
+ UBIR
);
1409 ubmr
= readl(sport
->port
.membase
+ UBMR
);
1410 uts
= readl(sport
->port
.membase
+ IMX21_UTS
);
1412 temp
= readl(sport
->port
.membase
+ UCR2
);
1414 writel(temp
, sport
->port
.membase
+ UCR2
);
1416 while (!(readl(sport
->port
.membase
+ UCR2
) & UCR2_SRST
) && (--i
> 0))
1419 /* Restore the registers */
1420 writel(ubir
, sport
->port
.membase
+ UBIR
);
1421 writel(ubmr
, sport
->port
.membase
+ UBMR
);
1422 writel(uts
, sport
->port
.membase
+ IMX21_UTS
);
1426 imx_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
1427 struct ktermios
*old
)
1429 struct imx_port
*sport
= (struct imx_port
*)port
;
1430 unsigned long flags
;
1431 unsigned long ucr2
, old_ucr1
, old_ucr2
;
1432 unsigned int baud
, quot
;
1433 unsigned int old_csize
= old
? old
->c_cflag
& CSIZE
: CS8
;
1434 unsigned long div
, ufcr
;
1435 unsigned long num
, denom
;
1439 * We only support CS7 and CS8.
1441 while ((termios
->c_cflag
& CSIZE
) != CS7
&&
1442 (termios
->c_cflag
& CSIZE
) != CS8
) {
1443 termios
->c_cflag
&= ~CSIZE
;
1444 termios
->c_cflag
|= old_csize
;
1448 if ((termios
->c_cflag
& CSIZE
) == CS8
)
1449 ucr2
= UCR2_WS
| UCR2_SRST
| UCR2_IRTS
;
1451 ucr2
= UCR2_SRST
| UCR2_IRTS
;
1453 if (termios
->c_cflag
& CRTSCTS
) {
1454 if (sport
->have_rtscts
) {
1457 if (port
->rs485
.flags
& SER_RS485_ENABLED
) {
1459 * RTS is mandatory for rs485 operation, so keep
1460 * it under manual control and keep transmitter
1463 if (port
->rs485
.flags
&
1464 SER_RS485_RTS_AFTER_SEND
)
1465 imx_port_rts_inactive(sport
, &ucr2
);
1467 imx_port_rts_active(sport
, &ucr2
);
1469 imx_port_rts_auto(sport
, &ucr2
);
1472 termios
->c_cflag
&= ~CRTSCTS
;
1474 } else if (port
->rs485
.flags
& SER_RS485_ENABLED
) {
1475 /* disable transmitter */
1476 if (port
->rs485
.flags
& SER_RS485_RTS_AFTER_SEND
)
1477 imx_port_rts_inactive(sport
, &ucr2
);
1479 imx_port_rts_active(sport
, &ucr2
);
1483 if (termios
->c_cflag
& CSTOPB
)
1485 if (termios
->c_cflag
& PARENB
) {
1487 if (termios
->c_cflag
& PARODD
)
1491 del_timer_sync(&sport
->timer
);
1494 * Ask the core to calculate the divisor for us.
1496 baud
= uart_get_baud_rate(port
, termios
, old
, 50, port
->uartclk
/ 16);
1497 quot
= uart_get_divisor(port
, baud
);
1499 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1501 sport
->port
.read_status_mask
= 0;
1502 if (termios
->c_iflag
& INPCK
)
1503 sport
->port
.read_status_mask
|= (URXD_FRMERR
| URXD_PRERR
);
1504 if (termios
->c_iflag
& (BRKINT
| PARMRK
))
1505 sport
->port
.read_status_mask
|= URXD_BRK
;
1508 * Characters to ignore
1510 sport
->port
.ignore_status_mask
= 0;
1511 if (termios
->c_iflag
& IGNPAR
)
1512 sport
->port
.ignore_status_mask
|= URXD_PRERR
| URXD_FRMERR
;
1513 if (termios
->c_iflag
& IGNBRK
) {
1514 sport
->port
.ignore_status_mask
|= URXD_BRK
;
1516 * If we're ignoring parity and break indicators,
1517 * ignore overruns too (for real raw support).
1519 if (termios
->c_iflag
& IGNPAR
)
1520 sport
->port
.ignore_status_mask
|= URXD_OVRRUN
;
1523 if ((termios
->c_cflag
& CREAD
) == 0)
1524 sport
->port
.ignore_status_mask
|= URXD_DUMMY_READ
;
1527 * Update the per-port timeout.
1529 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1532 * disable interrupts and drain transmitter
1534 old_ucr1
= readl(sport
->port
.membase
+ UCR1
);
1535 writel(old_ucr1
& ~(UCR1_TXMPTYEN
| UCR1_RRDYEN
| UCR1_RTSDEN
),
1536 sport
->port
.membase
+ UCR1
);
1538 while (!(readl(sport
->port
.membase
+ USR2
) & USR2_TXDC
))
1541 /* then, disable everything */
1542 old_ucr2
= readl(sport
->port
.membase
+ UCR2
);
1543 writel(old_ucr2
& ~(UCR2_TXEN
| UCR2_RXEN
),
1544 sport
->port
.membase
+ UCR2
);
1545 old_ucr2
&= (UCR2_TXEN
| UCR2_RXEN
| UCR2_ATEN
);
1547 /* custom-baudrate handling */
1548 div
= sport
->port
.uartclk
/ (baud
* 16);
1549 if (baud
== 38400 && quot
!= div
)
1550 baud
= sport
->port
.uartclk
/ (quot
* 16);
1552 div
= sport
->port
.uartclk
/ (baud
* 16);
1558 rational_best_approximation(16 * div
* baud
, sport
->port
.uartclk
,
1559 1 << 16, 1 << 16, &num
, &denom
);
1561 tdiv64
= sport
->port
.uartclk
;
1563 do_div(tdiv64
, denom
* 16 * div
);
1564 tty_termios_encode_baud_rate(termios
,
1565 (speed_t
)tdiv64
, (speed_t
)tdiv64
);
1570 ufcr
= readl(sport
->port
.membase
+ UFCR
);
1571 ufcr
= (ufcr
& (~UFCR_RFDIV
)) | UFCR_RFDIV_REG(div
);
1572 if (sport
->dte_mode
)
1573 ufcr
|= UFCR_DCEDTE
;
1574 writel(ufcr
, sport
->port
.membase
+ UFCR
);
1576 writel(num
, sport
->port
.membase
+ UBIR
);
1577 writel(denom
, sport
->port
.membase
+ UBMR
);
1579 if (!is_imx1_uart(sport
))
1580 writel(sport
->port
.uartclk
/ div
/ 1000,
1581 sport
->port
.membase
+ IMX21_ONEMS
);
1583 writel(old_ucr1
, sport
->port
.membase
+ UCR1
);
1585 /* set the parity, stop bits and data size */
1586 writel(ucr2
| old_ucr2
, sport
->port
.membase
+ UCR2
);
1588 if (UART_ENABLE_MS(&sport
->port
, termios
->c_cflag
))
1589 imx_enable_ms(&sport
->port
);
1591 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1594 static const char *imx_type(struct uart_port
*port
)
1596 struct imx_port
*sport
= (struct imx_port
*)port
;
1598 return sport
->port
.type
== PORT_IMX
? "IMX" : NULL
;
1602 * Configure/autoconfigure the port.
1604 static void imx_config_port(struct uart_port
*port
, int flags
)
1606 struct imx_port
*sport
= (struct imx_port
*)port
;
1608 if (flags
& UART_CONFIG_TYPE
)
1609 sport
->port
.type
= PORT_IMX
;
1613 * Verify the new serial_struct (for TIOCSSERIAL).
1614 * The only change we allow are to the flags and type, and
1615 * even then only between PORT_IMX and PORT_UNKNOWN
1618 imx_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
1620 struct imx_port
*sport
= (struct imx_port
*)port
;
1623 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_IMX
)
1625 if (sport
->port
.irq
!= ser
->irq
)
1627 if (ser
->io_type
!= UPIO_MEM
)
1629 if (sport
->port
.uartclk
/ 16 != ser
->baud_base
)
1631 if (sport
->port
.mapbase
!= (unsigned long)ser
->iomem_base
)
1633 if (sport
->port
.iobase
!= ser
->port
)
1640 #if defined(CONFIG_CONSOLE_POLL)
1642 static int imx_poll_init(struct uart_port
*port
)
1644 struct imx_port
*sport
= (struct imx_port
*)port
;
1645 unsigned long flags
;
1649 retval
= clk_prepare_enable(sport
->clk_ipg
);
1652 retval
= clk_prepare_enable(sport
->clk_per
);
1654 clk_disable_unprepare(sport
->clk_ipg
);
1656 imx_setup_ufcr(sport
, TXTL_DEFAULT
, RXTL_DEFAULT
);
1658 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1660 temp
= readl(sport
->port
.membase
+ UCR1
);
1661 if (is_imx1_uart(sport
))
1662 temp
|= IMX1_UCR1_UARTCLKEN
;
1663 temp
|= UCR1_UARTEN
| UCR1_RRDYEN
;
1664 temp
&= ~(UCR1_TXMPTYEN
| UCR1_RTSDEN
);
1665 writel(temp
, sport
->port
.membase
+ UCR1
);
1667 temp
= readl(sport
->port
.membase
+ UCR2
);
1669 writel(temp
, sport
->port
.membase
+ UCR2
);
1671 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1676 static int imx_poll_get_char(struct uart_port
*port
)
1678 if (!(readl_relaxed(port
->membase
+ USR2
) & USR2_RDR
))
1679 return NO_POLL_CHAR
;
1681 return readl_relaxed(port
->membase
+ URXD0
) & URXD_RX_DATA
;
1684 static void imx_poll_put_char(struct uart_port
*port
, unsigned char c
)
1686 unsigned int status
;
1690 status
= readl_relaxed(port
->membase
+ USR1
);
1691 } while (~status
& USR1_TRDY
);
1694 writel_relaxed(c
, port
->membase
+ URTX0
);
1698 status
= readl_relaxed(port
->membase
+ USR2
);
1699 } while (~status
& USR2_TXDC
);
1703 static int imx_rs485_config(struct uart_port
*port
,
1704 struct serial_rs485
*rs485conf
)
1706 struct imx_port
*sport
= (struct imx_port
*)port
;
1710 rs485conf
->delay_rts_before_send
= 0;
1711 rs485conf
->delay_rts_after_send
= 0;
1713 /* RTS is required to control the transmitter */
1714 if (!sport
->have_rtscts
)
1715 rs485conf
->flags
&= ~SER_RS485_ENABLED
;
1717 if (rs485conf
->flags
& SER_RS485_ENABLED
) {
1718 /* disable transmitter */
1719 temp
= readl(sport
->port
.membase
+ UCR2
);
1720 if (rs485conf
->flags
& SER_RS485_RTS_AFTER_SEND
)
1721 imx_port_rts_inactive(sport
, &temp
);
1723 imx_port_rts_active(sport
, &temp
);
1724 writel(temp
, sport
->port
.membase
+ UCR2
);
1727 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1728 if (!(rs485conf
->flags
& SER_RS485_ENABLED
) ||
1729 rs485conf
->flags
& SER_RS485_RX_DURING_TX
) {
1730 temp
= readl(sport
->port
.membase
+ UCR2
);
1732 writel(temp
, sport
->port
.membase
+ UCR2
);
1735 port
->rs485
= *rs485conf
;
1740 static struct uart_ops imx_pops
= {
1741 .tx_empty
= imx_tx_empty
,
1742 .set_mctrl
= imx_set_mctrl
,
1743 .get_mctrl
= imx_get_mctrl
,
1744 .stop_tx
= imx_stop_tx
,
1745 .start_tx
= imx_start_tx
,
1746 .stop_rx
= imx_stop_rx
,
1747 .enable_ms
= imx_enable_ms
,
1748 .break_ctl
= imx_break_ctl
,
1749 .startup
= imx_startup
,
1750 .shutdown
= imx_shutdown
,
1751 .flush_buffer
= imx_flush_buffer
,
1752 .set_termios
= imx_set_termios
,
1754 .config_port
= imx_config_port
,
1755 .verify_port
= imx_verify_port
,
1756 #if defined(CONFIG_CONSOLE_POLL)
1757 .poll_init
= imx_poll_init
,
1758 .poll_get_char
= imx_poll_get_char
,
1759 .poll_put_char
= imx_poll_put_char
,
1763 static struct imx_port
*imx_ports
[UART_NR
];
1765 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1766 static void imx_console_putchar(struct uart_port
*port
, int ch
)
1768 struct imx_port
*sport
= (struct imx_port
*)port
;
1770 while (readl(sport
->port
.membase
+ uts_reg(sport
)) & UTS_TXFULL
)
1773 writel(ch
, sport
->port
.membase
+ URTX0
);
1777 * Interrupts are disabled on entering
1780 imx_console_write(struct console
*co
, const char *s
, unsigned int count
)
1782 struct imx_port
*sport
= imx_ports
[co
->index
];
1783 struct imx_port_ucrs old_ucr
;
1785 unsigned long flags
= 0;
1789 retval
= clk_enable(sport
->clk_per
);
1792 retval
= clk_enable(sport
->clk_ipg
);
1794 clk_disable(sport
->clk_per
);
1798 if (sport
->port
.sysrq
)
1800 else if (oops_in_progress
)
1801 locked
= spin_trylock_irqsave(&sport
->port
.lock
, flags
);
1803 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1806 * First, save UCR1/2/3 and then disable interrupts
1808 imx_port_ucrs_save(&sport
->port
, &old_ucr
);
1809 ucr1
= old_ucr
.ucr1
;
1811 if (is_imx1_uart(sport
))
1812 ucr1
|= IMX1_UCR1_UARTCLKEN
;
1813 ucr1
|= UCR1_UARTEN
;
1814 ucr1
&= ~(UCR1_TXMPTYEN
| UCR1_RRDYEN
| UCR1_RTSDEN
);
1816 writel(ucr1
, sport
->port
.membase
+ UCR1
);
1818 writel(old_ucr
.ucr2
| UCR2_TXEN
, sport
->port
.membase
+ UCR2
);
1820 uart_console_write(&sport
->port
, s
, count
, imx_console_putchar
);
1823 * Finally, wait for transmitter to become empty
1824 * and restore UCR1/2/3
1826 while (!(readl(sport
->port
.membase
+ USR2
) & USR2_TXDC
));
1828 imx_port_ucrs_restore(&sport
->port
, &old_ucr
);
1831 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1833 clk_disable(sport
->clk_ipg
);
1834 clk_disable(sport
->clk_per
);
1838 * If the port was already initialised (eg, by a boot loader),
1839 * try to determine the current setup.
1842 imx_console_get_options(struct imx_port
*sport
, int *baud
,
1843 int *parity
, int *bits
)
1846 if (readl(sport
->port
.membase
+ UCR1
) & UCR1_UARTEN
) {
1847 /* ok, the port was enabled */
1848 unsigned int ucr2
, ubir
, ubmr
, uartclk
;
1849 unsigned int baud_raw
;
1850 unsigned int ucfr_rfdiv
;
1852 ucr2
= readl(sport
->port
.membase
+ UCR2
);
1855 if (ucr2
& UCR2_PREN
) {
1856 if (ucr2
& UCR2_PROE
)
1867 ubir
= readl(sport
->port
.membase
+ UBIR
) & 0xffff;
1868 ubmr
= readl(sport
->port
.membase
+ UBMR
) & 0xffff;
1870 ucfr_rfdiv
= (readl(sport
->port
.membase
+ UFCR
) & UFCR_RFDIV
) >> 7;
1871 if (ucfr_rfdiv
== 6)
1874 ucfr_rfdiv
= 6 - ucfr_rfdiv
;
1876 uartclk
= clk_get_rate(sport
->clk_per
);
1877 uartclk
/= ucfr_rfdiv
;
1880 * The next code provides exact computation of
1881 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1882 * without need of float support or long long division,
1883 * which would be required to prevent 32bit arithmetic overflow
1885 unsigned int mul
= ubir
+ 1;
1886 unsigned int div
= 16 * (ubmr
+ 1);
1887 unsigned int rem
= uartclk
% div
;
1889 baud_raw
= (uartclk
/ div
) * mul
;
1890 baud_raw
+= (rem
* mul
+ div
/ 2) / div
;
1891 *baud
= (baud_raw
+ 50) / 100 * 100;
1894 if (*baud
!= baud_raw
)
1895 pr_info("Console IMX rounded baud rate from %d to %d\n",
1901 imx_console_setup(struct console
*co
, char *options
)
1903 struct imx_port
*sport
;
1911 * Check whether an invalid uart number has been specified, and
1912 * if so, search for the first available port that does have
1915 if (co
->index
== -1 || co
->index
>= ARRAY_SIZE(imx_ports
))
1917 sport
= imx_ports
[co
->index
];
1921 /* For setting the registers, we only need to enable the ipg clock. */
1922 retval
= clk_prepare_enable(sport
->clk_ipg
);
1927 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1929 imx_console_get_options(sport
, &baud
, &parity
, &bits
);
1931 imx_setup_ufcr(sport
, TXTL_DEFAULT
, RXTL_DEFAULT
);
1933 retval
= uart_set_options(&sport
->port
, co
, baud
, parity
, bits
, flow
);
1935 clk_disable(sport
->clk_ipg
);
1937 clk_unprepare(sport
->clk_ipg
);
1941 retval
= clk_prepare(sport
->clk_per
);
1943 clk_disable_unprepare(sport
->clk_ipg
);
1949 static struct uart_driver imx_reg
;
1950 static struct console imx_console
= {
1952 .write
= imx_console_write
,
1953 .device
= uart_console_device
,
1954 .setup
= imx_console_setup
,
1955 .flags
= CON_PRINTBUFFER
,
1960 #define IMX_CONSOLE &imx_console
1963 static void imx_console_early_putchar(struct uart_port
*port
, int ch
)
1965 while (readl_relaxed(port
->membase
+ IMX21_UTS
) & UTS_TXFULL
)
1968 writel_relaxed(ch
, port
->membase
+ URTX0
);
1971 static void imx_console_early_write(struct console
*con
, const char *s
,
1974 struct earlycon_device
*dev
= con
->data
;
1976 uart_console_write(&dev
->port
, s
, count
, imx_console_early_putchar
);
1980 imx_console_early_setup(struct earlycon_device
*dev
, const char *opt
)
1982 if (!dev
->port
.membase
)
1985 dev
->con
->write
= imx_console_early_write
;
1989 OF_EARLYCON_DECLARE(ec_imx6q
, "fsl,imx6q-uart", imx_console_early_setup
);
1990 OF_EARLYCON_DECLARE(ec_imx21
, "fsl,imx21-uart", imx_console_early_setup
);
1994 #define IMX_CONSOLE NULL
1997 static struct uart_driver imx_reg
= {
1998 .owner
= THIS_MODULE
,
1999 .driver_name
= DRIVER_NAME
,
2000 .dev_name
= DEV_NAME
,
2001 .major
= SERIAL_IMX_MAJOR
,
2002 .minor
= MINOR_START
,
2003 .nr
= ARRAY_SIZE(imx_ports
),
2004 .cons
= IMX_CONSOLE
,
2009 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
2010 * could successfully get all information from dt or a negative errno.
2012 static int serial_imx_probe_dt(struct imx_port
*sport
,
2013 struct platform_device
*pdev
)
2015 struct device_node
*np
= pdev
->dev
.of_node
;
2018 sport
->devdata
= of_device_get_match_data(&pdev
->dev
);
2019 if (!sport
->devdata
)
2020 /* no device tree device */
2023 ret
= of_alias_get_id(np
, "serial");
2025 dev_err(&pdev
->dev
, "failed to get alias id, errno %d\n", ret
);
2028 sport
->port
.line
= ret
;
2030 if (of_get_property(np
, "uart-has-rtscts", NULL
) ||
2031 of_get_property(np
, "fsl,uart-has-rtscts", NULL
) /* deprecated */)
2032 sport
->have_rtscts
= 1;
2034 if (of_get_property(np
, "fsl,dte-mode", NULL
))
2035 sport
->dte_mode
= 1;
2040 static inline int serial_imx_probe_dt(struct imx_port
*sport
,
2041 struct platform_device
*pdev
)
2047 static void serial_imx_probe_pdata(struct imx_port
*sport
,
2048 struct platform_device
*pdev
)
2050 struct imxuart_platform_data
*pdata
= dev_get_platdata(&pdev
->dev
);
2052 sport
->port
.line
= pdev
->id
;
2053 sport
->devdata
= (struct imx_uart_data
*) pdev
->id_entry
->driver_data
;
2058 if (pdata
->flags
& IMXUART_HAVE_RTSCTS
)
2059 sport
->have_rtscts
= 1;
2062 static int serial_imx_probe(struct platform_device
*pdev
)
2064 struct imx_port
*sport
;
2067 struct resource
*res
;
2068 int txirq
, rxirq
, rtsirq
;
2070 sport
= devm_kzalloc(&pdev
->dev
, sizeof(*sport
), GFP_KERNEL
);
2074 ret
= serial_imx_probe_dt(sport
, pdev
);
2076 serial_imx_probe_pdata(sport
, pdev
);
2080 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2081 base
= devm_ioremap_resource(&pdev
->dev
, res
);
2083 return PTR_ERR(base
);
2085 rxirq
= platform_get_irq(pdev
, 0);
2086 txirq
= platform_get_irq(pdev
, 1);
2087 rtsirq
= platform_get_irq(pdev
, 2);
2089 sport
->port
.dev
= &pdev
->dev
;
2090 sport
->port
.mapbase
= res
->start
;
2091 sport
->port
.membase
= base
;
2092 sport
->port
.type
= PORT_IMX
,
2093 sport
->port
.iotype
= UPIO_MEM
;
2094 sport
->port
.irq
= rxirq
;
2095 sport
->port
.fifosize
= 32;
2096 sport
->port
.ops
= &imx_pops
;
2097 sport
->port
.rs485_config
= imx_rs485_config
;
2098 sport
->port
.rs485
.flags
=
2099 SER_RS485_RTS_ON_SEND
| SER_RS485_RX_DURING_TX
;
2100 sport
->port
.flags
= UPF_BOOT_AUTOCONF
;
2101 init_timer(&sport
->timer
);
2102 sport
->timer
.function
= imx_timeout
;
2103 sport
->timer
.data
= (unsigned long)sport
;
2105 sport
->gpios
= mctrl_gpio_init(&sport
->port
, 0);
2106 if (IS_ERR(sport
->gpios
))
2107 return PTR_ERR(sport
->gpios
);
2109 sport
->clk_ipg
= devm_clk_get(&pdev
->dev
, "ipg");
2110 if (IS_ERR(sport
->clk_ipg
)) {
2111 ret
= PTR_ERR(sport
->clk_ipg
);
2112 dev_err(&pdev
->dev
, "failed to get ipg clk: %d\n", ret
);
2116 sport
->clk_per
= devm_clk_get(&pdev
->dev
, "per");
2117 if (IS_ERR(sport
->clk_per
)) {
2118 ret
= PTR_ERR(sport
->clk_per
);
2119 dev_err(&pdev
->dev
, "failed to get per clk: %d\n", ret
);
2123 sport
->port
.uartclk
= clk_get_rate(sport
->clk_per
);
2125 /* For register access, we only need to enable the ipg clock. */
2126 ret
= clk_prepare_enable(sport
->clk_ipg
);
2130 /* Disable interrupts before requesting them */
2131 reg
= readl_relaxed(sport
->port
.membase
+ UCR1
);
2132 reg
&= ~(UCR1_ADEN
| UCR1_TRDYEN
| UCR1_IDEN
| UCR1_RRDYEN
|
2133 UCR1_TXMPTYEN
| UCR1_RTSDEN
);
2134 writel_relaxed(reg
, sport
->port
.membase
+ UCR1
);
2136 clk_disable_unprepare(sport
->clk_ipg
);
2139 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2140 * chips only have one interrupt.
2143 ret
= devm_request_irq(&pdev
->dev
, rxirq
, imx_rxint
, 0,
2144 dev_name(&pdev
->dev
), sport
);
2148 ret
= devm_request_irq(&pdev
->dev
, txirq
, imx_txint
, 0,
2149 dev_name(&pdev
->dev
), sport
);
2153 ret
= devm_request_irq(&pdev
->dev
, rxirq
, imx_int
, 0,
2154 dev_name(&pdev
->dev
), sport
);
2159 imx_ports
[sport
->port
.line
] = sport
;
2161 platform_set_drvdata(pdev
, sport
);
2163 return uart_add_one_port(&imx_reg
, &sport
->port
);
2166 static int serial_imx_remove(struct platform_device
*pdev
)
2168 struct imx_port
*sport
= platform_get_drvdata(pdev
);
2170 return uart_remove_one_port(&imx_reg
, &sport
->port
);
2173 static void serial_imx_restore_context(struct imx_port
*sport
)
2175 if (!sport
->context_saved
)
2178 writel(sport
->saved_reg
[4], sport
->port
.membase
+ UFCR
);
2179 writel(sport
->saved_reg
[5], sport
->port
.membase
+ UESC
);
2180 writel(sport
->saved_reg
[6], sport
->port
.membase
+ UTIM
);
2181 writel(sport
->saved_reg
[7], sport
->port
.membase
+ UBIR
);
2182 writel(sport
->saved_reg
[8], sport
->port
.membase
+ UBMR
);
2183 writel(sport
->saved_reg
[9], sport
->port
.membase
+ IMX21_UTS
);
2184 writel(sport
->saved_reg
[0], sport
->port
.membase
+ UCR1
);
2185 writel(sport
->saved_reg
[1] | UCR2_SRST
, sport
->port
.membase
+ UCR2
);
2186 writel(sport
->saved_reg
[2], sport
->port
.membase
+ UCR3
);
2187 writel(sport
->saved_reg
[3], sport
->port
.membase
+ UCR4
);
2188 sport
->context_saved
= false;
2191 static void serial_imx_save_context(struct imx_port
*sport
)
2193 /* Save necessary regs */
2194 sport
->saved_reg
[0] = readl(sport
->port
.membase
+ UCR1
);
2195 sport
->saved_reg
[1] = readl(sport
->port
.membase
+ UCR2
);
2196 sport
->saved_reg
[2] = readl(sport
->port
.membase
+ UCR3
);
2197 sport
->saved_reg
[3] = readl(sport
->port
.membase
+ UCR4
);
2198 sport
->saved_reg
[4] = readl(sport
->port
.membase
+ UFCR
);
2199 sport
->saved_reg
[5] = readl(sport
->port
.membase
+ UESC
);
2200 sport
->saved_reg
[6] = readl(sport
->port
.membase
+ UTIM
);
2201 sport
->saved_reg
[7] = readl(sport
->port
.membase
+ UBIR
);
2202 sport
->saved_reg
[8] = readl(sport
->port
.membase
+ UBMR
);
2203 sport
->saved_reg
[9] = readl(sport
->port
.membase
+ IMX21_UTS
);
2204 sport
->context_saved
= true;
2207 static void serial_imx_enable_wakeup(struct imx_port
*sport
, bool on
)
2211 val
= readl(sport
->port
.membase
+ UCR3
);
2215 val
&= ~UCR3_AWAKEN
;
2216 writel(val
, sport
->port
.membase
+ UCR3
);
2218 val
= readl(sport
->port
.membase
+ UCR1
);
2222 val
&= ~UCR1_RTSDEN
;
2223 writel(val
, sport
->port
.membase
+ UCR1
);
2226 static int imx_serial_port_suspend_noirq(struct device
*dev
)
2228 struct platform_device
*pdev
= to_platform_device(dev
);
2229 struct imx_port
*sport
= platform_get_drvdata(pdev
);
2232 ret
= clk_enable(sport
->clk_ipg
);
2236 serial_imx_save_context(sport
);
2238 clk_disable(sport
->clk_ipg
);
2243 static int imx_serial_port_resume_noirq(struct device
*dev
)
2245 struct platform_device
*pdev
= to_platform_device(dev
);
2246 struct imx_port
*sport
= platform_get_drvdata(pdev
);
2249 ret
= clk_enable(sport
->clk_ipg
);
2253 serial_imx_restore_context(sport
);
2255 clk_disable(sport
->clk_ipg
);
2260 static int imx_serial_port_suspend(struct device
*dev
)
2262 struct platform_device
*pdev
= to_platform_device(dev
);
2263 struct imx_port
*sport
= platform_get_drvdata(pdev
);
2265 /* enable wakeup from i.MX UART */
2266 serial_imx_enable_wakeup(sport
, true);
2268 uart_suspend_port(&imx_reg
, &sport
->port
);
2270 /* Needed to enable clock in suspend_noirq */
2271 return clk_prepare(sport
->clk_ipg
);
2274 static int imx_serial_port_resume(struct device
*dev
)
2276 struct platform_device
*pdev
= to_platform_device(dev
);
2277 struct imx_port
*sport
= platform_get_drvdata(pdev
);
2279 /* disable wakeup from i.MX UART */
2280 serial_imx_enable_wakeup(sport
, false);
2282 uart_resume_port(&imx_reg
, &sport
->port
);
2284 clk_unprepare(sport
->clk_ipg
);
2289 static const struct dev_pm_ops imx_serial_port_pm_ops
= {
2290 .suspend_noirq
= imx_serial_port_suspend_noirq
,
2291 .resume_noirq
= imx_serial_port_resume_noirq
,
2292 .suspend
= imx_serial_port_suspend
,
2293 .resume
= imx_serial_port_resume
,
2296 static struct platform_driver serial_imx_driver
= {
2297 .probe
= serial_imx_probe
,
2298 .remove
= serial_imx_remove
,
2300 .id_table
= imx_uart_devtype
,
2303 .of_match_table
= imx_uart_dt_ids
,
2304 .pm
= &imx_serial_port_pm_ops
,
2308 static int __init
imx_serial_init(void)
2310 int ret
= uart_register_driver(&imx_reg
);
2315 ret
= platform_driver_register(&serial_imx_driver
);
2317 uart_unregister_driver(&imx_reg
);
2322 static void __exit
imx_serial_exit(void)
2324 platform_driver_unregister(&serial_imx_driver
);
2325 uart_unregister_driver(&imx_reg
);
2328 module_init(imx_serial_init
);
2329 module_exit(imx_serial_exit
);
2331 MODULE_AUTHOR("Sascha Hauer");
2332 MODULE_DESCRIPTION("IMX generic serial port driver");
2333 MODULE_LICENSE("GPL");
2334 MODULE_ALIAS("platform:imx-uart");