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tty: serial: imx: clear Ageing Timer Interrupt in handler
[mirror_ubuntu-jammy-kernel.git] / drivers / tty / serial / imx.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11 #include <linux/module.h>
12 #include <linux/ioport.h>
13 #include <linux/init.h>
14 #include <linux/console.h>
15 #include <linux/sysrq.h>
16 #include <linux/platform_device.h>
17 #include <linux/tty.h>
18 #include <linux/tty_flip.h>
19 #include <linux/serial_core.h>
20 #include <linux/serial.h>
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/rational.h>
25 #include <linux/slab.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28 #include <linux/io.h>
29 #include <linux/dma-mapping.h>
30
31 #include <asm/irq.h>
32 #include <linux/platform_data/serial-imx.h>
33 #include <linux/platform_data/dma-imx.h>
34
35 #include "serial_mctrl_gpio.h"
36
37 /* Register definitions */
38 #define URXD0 0x0 /* Receiver Register */
39 #define URTX0 0x40 /* Transmitter Register */
40 #define UCR1 0x80 /* Control Register 1 */
41 #define UCR2 0x84 /* Control Register 2 */
42 #define UCR3 0x88 /* Control Register 3 */
43 #define UCR4 0x8c /* Control Register 4 */
44 #define UFCR 0x90 /* FIFO Control Register */
45 #define USR1 0x94 /* Status Register 1 */
46 #define USR2 0x98 /* Status Register 2 */
47 #define UESC 0x9c /* Escape Character Register */
48 #define UTIM 0xa0 /* Escape Timer Register */
49 #define UBIR 0xa4 /* BRM Incremental Register */
50 #define UBMR 0xa8 /* BRM Modulator Register */
51 #define UBRC 0xac /* Baud Rate Count Register */
52 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
53 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
54 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
55
56 /* UART Control Register Bit Fields.*/
57 #define URXD_DUMMY_READ (1<<16)
58 #define URXD_CHARRDY (1<<15)
59 #define URXD_ERR (1<<14)
60 #define URXD_OVRRUN (1<<13)
61 #define URXD_FRMERR (1<<12)
62 #define URXD_BRK (1<<11)
63 #define URXD_PRERR (1<<10)
64 #define URXD_RX_DATA (0xFF<<0)
65 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
66 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
67 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
68 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
69 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
70 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
71 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
72 #define UCR1_IREN (1<<7) /* Infrared interface enable */
73 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
74 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
75 #define UCR1_SNDBRK (1<<4) /* Send break */
76 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
77 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
78 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
79 #define UCR1_DOZE (1<<1) /* Doze */
80 #define UCR1_UARTEN (1<<0) /* UART enabled */
81 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
82 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
83 #define UCR2_CTSC (1<<13) /* CTS pin control */
84 #define UCR2_CTS (1<<12) /* Clear to send */
85 #define UCR2_ESCEN (1<<11) /* Escape enable */
86 #define UCR2_PREN (1<<8) /* Parity enable */
87 #define UCR2_PROE (1<<7) /* Parity odd/even */
88 #define UCR2_STPB (1<<6) /* Stop */
89 #define UCR2_WS (1<<5) /* Word size */
90 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
91 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
92 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
93 #define UCR2_RXEN (1<<1) /* Receiver enabled */
94 #define UCR2_SRST (1<<0) /* SW reset */
95 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
96 #define UCR3_PARERREN (1<<12) /* Parity enable */
97 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
98 #define UCR3_DSR (1<<10) /* Data set ready */
99 #define UCR3_DCD (1<<9) /* Data carrier detect */
100 #define UCR3_RI (1<<8) /* Ring indicator */
101 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
102 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
103 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
104 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
105 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
106 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
107 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
108 #define UCR3_BPEN (1<<0) /* Preset registers enable */
109 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
110 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
111 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
112 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
113 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
114 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
115 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
116 #define UCR4_IRSC (1<<5) /* IR special case */
117 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
118 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
119 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
120 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
121 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
122 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
123 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
124 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
125 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
126 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
127 #define USR1_RTSS (1<<14) /* RTS pin status */
128 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
129 #define USR1_RTSD (1<<12) /* RTS delta */
130 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
131 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
132 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
133 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
134 #define USR1_DTRD (1<<7) /* DTR Delta */
135 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
136 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
137 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
138 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
139 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
140 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
141 #define USR2_IDLE (1<<12) /* Idle condition */
142 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
143 #define USR2_RIIN (1<<9) /* Ring Indicator Input */
144 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
145 #define USR2_WAKE (1<<7) /* Wake */
146 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
147 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
148 #define USR2_TXDC (1<<3) /* Transmitter complete */
149 #define USR2_BRCD (1<<2) /* Break condition */
150 #define USR2_ORE (1<<1) /* Overrun error */
151 #define USR2_RDR (1<<0) /* Recv data ready */
152 #define UTS_FRCPERR (1<<13) /* Force parity error */
153 #define UTS_LOOP (1<<12) /* Loop tx and rx */
154 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
155 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
156 #define UTS_TXFULL (1<<4) /* TxFIFO full */
157 #define UTS_RXFULL (1<<3) /* RxFIFO full */
158 #define UTS_SOFTRST (1<<0) /* Software reset */
159
160 /* We've been assigned a range on the "Low-density serial ports" major */
161 #define SERIAL_IMX_MAJOR 207
162 #define MINOR_START 16
163 #define DEV_NAME "ttymxc"
164
165 /*
166 * This determines how often we check the modem status signals
167 * for any change. They generally aren't connected to an IRQ
168 * so we have to poll them. We also check immediately before
169 * filling the TX fifo incase CTS has been dropped.
170 */
171 #define MCTRL_TIMEOUT (250*HZ/1000)
172
173 #define DRIVER_NAME "IMX-uart"
174
175 #define UART_NR 8
176
177 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
178 enum imx_uart_type {
179 IMX1_UART,
180 IMX21_UART,
181 IMX53_UART,
182 IMX6Q_UART,
183 };
184
185 /* device type dependent stuff */
186 struct imx_uart_data {
187 unsigned uts_reg;
188 enum imx_uart_type devtype;
189 };
190
191 struct imx_port {
192 struct uart_port port;
193 struct timer_list timer;
194 unsigned int old_status;
195 unsigned int have_rtscts:1;
196 unsigned int have_rtsgpio:1;
197 unsigned int dte_mode:1;
198 unsigned int inverted_tx:1;
199 unsigned int inverted_rx:1;
200 struct clk *clk_ipg;
201 struct clk *clk_per;
202 const struct imx_uart_data *devdata;
203
204 struct mctrl_gpios *gpios;
205
206 /* shadow registers */
207 unsigned int ucr1;
208 unsigned int ucr2;
209 unsigned int ucr3;
210 unsigned int ucr4;
211 unsigned int ufcr;
212
213 /* DMA fields */
214 unsigned int dma_is_enabled:1;
215 unsigned int dma_is_rxing:1;
216 unsigned int dma_is_txing:1;
217 struct dma_chan *dma_chan_rx, *dma_chan_tx;
218 struct scatterlist rx_sgl, tx_sgl[2];
219 void *rx_buf;
220 struct circ_buf rx_ring;
221 unsigned int rx_periods;
222 dma_cookie_t rx_cookie;
223 unsigned int tx_bytes;
224 unsigned int dma_tx_nents;
225 unsigned int saved_reg[10];
226 bool context_saved;
227 };
228
229 struct imx_port_ucrs {
230 unsigned int ucr1;
231 unsigned int ucr2;
232 unsigned int ucr3;
233 };
234
235 static struct imx_uart_data imx_uart_devdata[] = {
236 [IMX1_UART] = {
237 .uts_reg = IMX1_UTS,
238 .devtype = IMX1_UART,
239 },
240 [IMX21_UART] = {
241 .uts_reg = IMX21_UTS,
242 .devtype = IMX21_UART,
243 },
244 [IMX53_UART] = {
245 .uts_reg = IMX21_UTS,
246 .devtype = IMX53_UART,
247 },
248 [IMX6Q_UART] = {
249 .uts_reg = IMX21_UTS,
250 .devtype = IMX6Q_UART,
251 },
252 };
253
254 static const struct platform_device_id imx_uart_devtype[] = {
255 {
256 .name = "imx1-uart",
257 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
258 }, {
259 .name = "imx21-uart",
260 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
261 }, {
262 .name = "imx53-uart",
263 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART],
264 }, {
265 .name = "imx6q-uart",
266 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
267 }, {
268 /* sentinel */
269 }
270 };
271 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
272
273 static const struct of_device_id imx_uart_dt_ids[] = {
274 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
275 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
276 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
277 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
278 { /* sentinel */ }
279 };
280 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
281
282 static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
283 {
284 switch (offset) {
285 case UCR1:
286 sport->ucr1 = val;
287 break;
288 case UCR2:
289 sport->ucr2 = val;
290 break;
291 case UCR3:
292 sport->ucr3 = val;
293 break;
294 case UCR4:
295 sport->ucr4 = val;
296 break;
297 case UFCR:
298 sport->ufcr = val;
299 break;
300 default:
301 break;
302 }
303 writel(val, sport->port.membase + offset);
304 }
305
306 static u32 imx_uart_readl(struct imx_port *sport, u32 offset)
307 {
308 switch (offset) {
309 case UCR1:
310 return sport->ucr1;
311 break;
312 case UCR2:
313 /*
314 * UCR2_SRST is the only bit in the cached registers that might
315 * differ from the value that was last written. As it only
316 * automatically becomes one after being cleared, reread
317 * conditionally.
318 */
319 if (!(sport->ucr2 & UCR2_SRST))
320 sport->ucr2 = readl(sport->port.membase + offset);
321 return sport->ucr2;
322 break;
323 case UCR3:
324 return sport->ucr3;
325 break;
326 case UCR4:
327 return sport->ucr4;
328 break;
329 case UFCR:
330 return sport->ufcr;
331 break;
332 default:
333 return readl(sport->port.membase + offset);
334 }
335 }
336
337 static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
338 {
339 return sport->devdata->uts_reg;
340 }
341
342 static inline int imx_uart_is_imx1(struct imx_port *sport)
343 {
344 return sport->devdata->devtype == IMX1_UART;
345 }
346
347 static inline int imx_uart_is_imx21(struct imx_port *sport)
348 {
349 return sport->devdata->devtype == IMX21_UART;
350 }
351
352 static inline int imx_uart_is_imx53(struct imx_port *sport)
353 {
354 return sport->devdata->devtype == IMX53_UART;
355 }
356
357 static inline int imx_uart_is_imx6q(struct imx_port *sport)
358 {
359 return sport->devdata->devtype == IMX6Q_UART;
360 }
361 /*
362 * Save and restore functions for UCR1, UCR2 and UCR3 registers
363 */
364 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
365 static void imx_uart_ucrs_save(struct imx_port *sport,
366 struct imx_port_ucrs *ucr)
367 {
368 /* save control registers */
369 ucr->ucr1 = imx_uart_readl(sport, UCR1);
370 ucr->ucr2 = imx_uart_readl(sport, UCR2);
371 ucr->ucr3 = imx_uart_readl(sport, UCR3);
372 }
373
374 static void imx_uart_ucrs_restore(struct imx_port *sport,
375 struct imx_port_ucrs *ucr)
376 {
377 /* restore control registers */
378 imx_uart_writel(sport, ucr->ucr1, UCR1);
379 imx_uart_writel(sport, ucr->ucr2, UCR2);
380 imx_uart_writel(sport, ucr->ucr3, UCR3);
381 }
382 #endif
383
384 /* called with port.lock taken and irqs caller dependent */
385 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
386 {
387 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
388
389 sport->port.mctrl |= TIOCM_RTS;
390 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
391 }
392
393 /* called with port.lock taken and irqs caller dependent */
394 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
395 {
396 *ucr2 &= ~UCR2_CTSC;
397 *ucr2 |= UCR2_CTS;
398
399 sport->port.mctrl &= ~TIOCM_RTS;
400 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
401 }
402
403 /* called with port.lock taken and irqs off */
404 static void imx_uart_start_rx(struct uart_port *port)
405 {
406 struct imx_port *sport = (struct imx_port *)port;
407 unsigned int ucr1, ucr2;
408
409 ucr1 = imx_uart_readl(sport, UCR1);
410 ucr2 = imx_uart_readl(sport, UCR2);
411
412 ucr2 |= UCR2_RXEN;
413
414 if (sport->dma_is_enabled) {
415 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
416 } else {
417 ucr1 |= UCR1_RRDYEN;
418 ucr2 |= UCR2_ATEN;
419 }
420
421 /* Write UCR2 first as it includes RXEN */
422 imx_uart_writel(sport, ucr2, UCR2);
423 imx_uart_writel(sport, ucr1, UCR1);
424 }
425
426 /* called with port.lock taken and irqs off */
427 static void imx_uart_stop_tx(struct uart_port *port)
428 {
429 struct imx_port *sport = (struct imx_port *)port;
430 u32 ucr1;
431
432 /*
433 * We are maybe in the SMP context, so if the DMA TX thread is running
434 * on other cpu, we have to wait for it to finish.
435 */
436 if (sport->dma_is_txing)
437 return;
438
439 ucr1 = imx_uart_readl(sport, UCR1);
440 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
441
442 /* in rs485 mode disable transmitter if shifter is empty */
443 if (port->rs485.flags & SER_RS485_ENABLED &&
444 imx_uart_readl(sport, USR2) & USR2_TXDC) {
445 u32 ucr2 = imx_uart_readl(sport, UCR2), ucr4;
446 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
447 imx_uart_rts_active(sport, &ucr2);
448 else
449 imx_uart_rts_inactive(sport, &ucr2);
450 imx_uart_writel(sport, ucr2, UCR2);
451
452 imx_uart_start_rx(port);
453
454 ucr4 = imx_uart_readl(sport, UCR4);
455 ucr4 &= ~UCR4_TCEN;
456 imx_uart_writel(sport, ucr4, UCR4);
457 }
458 }
459
460 /* called with port.lock taken and irqs off */
461 static void imx_uart_stop_rx(struct uart_port *port)
462 {
463 struct imx_port *sport = (struct imx_port *)port;
464 u32 ucr1, ucr2;
465
466 ucr1 = imx_uart_readl(sport, UCR1);
467 ucr2 = imx_uart_readl(sport, UCR2);
468
469 if (sport->dma_is_enabled) {
470 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
471 } else {
472 ucr1 &= ~UCR1_RRDYEN;
473 ucr2 &= ~UCR2_ATEN;
474 }
475 imx_uart_writel(sport, ucr1, UCR1);
476
477 ucr2 &= ~UCR2_RXEN;
478 imx_uart_writel(sport, ucr2, UCR2);
479 }
480
481 /* called with port.lock taken and irqs off */
482 static void imx_uart_enable_ms(struct uart_port *port)
483 {
484 struct imx_port *sport = (struct imx_port *)port;
485
486 mod_timer(&sport->timer, jiffies);
487
488 mctrl_gpio_enable_ms(sport->gpios);
489 }
490
491 static void imx_uart_dma_tx(struct imx_port *sport);
492
493 /* called with port.lock taken and irqs off */
494 static inline void imx_uart_transmit_buffer(struct imx_port *sport)
495 {
496 struct circ_buf *xmit = &sport->port.state->xmit;
497
498 if (sport->port.x_char) {
499 /* Send next char */
500 imx_uart_writel(sport, sport->port.x_char, URTX0);
501 sport->port.icount.tx++;
502 sport->port.x_char = 0;
503 return;
504 }
505
506 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
507 imx_uart_stop_tx(&sport->port);
508 return;
509 }
510
511 if (sport->dma_is_enabled) {
512 u32 ucr1;
513 /*
514 * We've just sent a X-char Ensure the TX DMA is enabled
515 * and the TX IRQ is disabled.
516 **/
517 ucr1 = imx_uart_readl(sport, UCR1);
518 ucr1 &= ~UCR1_TRDYEN;
519 if (sport->dma_is_txing) {
520 ucr1 |= UCR1_TXDMAEN;
521 imx_uart_writel(sport, ucr1, UCR1);
522 } else {
523 imx_uart_writel(sport, ucr1, UCR1);
524 imx_uart_dma_tx(sport);
525 }
526
527 return;
528 }
529
530 while (!uart_circ_empty(xmit) &&
531 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
532 /* send xmit->buf[xmit->tail]
533 * out the port here */
534 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
535 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
536 sport->port.icount.tx++;
537 }
538
539 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
540 uart_write_wakeup(&sport->port);
541
542 if (uart_circ_empty(xmit))
543 imx_uart_stop_tx(&sport->port);
544 }
545
546 static void imx_uart_dma_tx_callback(void *data)
547 {
548 struct imx_port *sport = data;
549 struct scatterlist *sgl = &sport->tx_sgl[0];
550 struct circ_buf *xmit = &sport->port.state->xmit;
551 unsigned long flags;
552 u32 ucr1;
553
554 spin_lock_irqsave(&sport->port.lock, flags);
555
556 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
557
558 ucr1 = imx_uart_readl(sport, UCR1);
559 ucr1 &= ~UCR1_TXDMAEN;
560 imx_uart_writel(sport, ucr1, UCR1);
561
562 /* update the stat */
563 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
564 sport->port.icount.tx += sport->tx_bytes;
565
566 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
567
568 sport->dma_is_txing = 0;
569
570 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
571 uart_write_wakeup(&sport->port);
572
573 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
574 imx_uart_dma_tx(sport);
575 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
576 u32 ucr4 = imx_uart_readl(sport, UCR4);
577 ucr4 |= UCR4_TCEN;
578 imx_uart_writel(sport, ucr4, UCR4);
579 }
580
581 spin_unlock_irqrestore(&sport->port.lock, flags);
582 }
583
584 /* called with port.lock taken and irqs off */
585 static void imx_uart_dma_tx(struct imx_port *sport)
586 {
587 struct circ_buf *xmit = &sport->port.state->xmit;
588 struct scatterlist *sgl = sport->tx_sgl;
589 struct dma_async_tx_descriptor *desc;
590 struct dma_chan *chan = sport->dma_chan_tx;
591 struct device *dev = sport->port.dev;
592 u32 ucr1, ucr4;
593 int ret;
594
595 if (sport->dma_is_txing)
596 return;
597
598 ucr4 = imx_uart_readl(sport, UCR4);
599 ucr4 &= ~UCR4_TCEN;
600 imx_uart_writel(sport, ucr4, UCR4);
601
602 sport->tx_bytes = uart_circ_chars_pending(xmit);
603
604 if (xmit->tail < xmit->head || xmit->head == 0) {
605 sport->dma_tx_nents = 1;
606 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
607 } else {
608 sport->dma_tx_nents = 2;
609 sg_init_table(sgl, 2);
610 sg_set_buf(sgl, xmit->buf + xmit->tail,
611 UART_XMIT_SIZE - xmit->tail);
612 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
613 }
614
615 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
616 if (ret == 0) {
617 dev_err(dev, "DMA mapping error for TX.\n");
618 return;
619 }
620 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
621 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
622 if (!desc) {
623 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
624 DMA_TO_DEVICE);
625 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
626 return;
627 }
628 desc->callback = imx_uart_dma_tx_callback;
629 desc->callback_param = sport;
630
631 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
632 uart_circ_chars_pending(xmit));
633
634 ucr1 = imx_uart_readl(sport, UCR1);
635 ucr1 |= UCR1_TXDMAEN;
636 imx_uart_writel(sport, ucr1, UCR1);
637
638 /* fire it */
639 sport->dma_is_txing = 1;
640 dmaengine_submit(desc);
641 dma_async_issue_pending(chan);
642 return;
643 }
644
645 /* called with port.lock taken and irqs off */
646 static void imx_uart_start_tx(struct uart_port *port)
647 {
648 struct imx_port *sport = (struct imx_port *)port;
649 u32 ucr1;
650
651 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
652 return;
653
654 if (port->rs485.flags & SER_RS485_ENABLED) {
655 u32 ucr2;
656
657 ucr2 = imx_uart_readl(sport, UCR2);
658 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
659 imx_uart_rts_active(sport, &ucr2);
660 else
661 imx_uart_rts_inactive(sport, &ucr2);
662 imx_uart_writel(sport, ucr2, UCR2);
663
664 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
665 imx_uart_stop_rx(port);
666
667 /*
668 * Enable transmitter and shifter empty irq only if DMA is off.
669 * In the DMA case this is done in the tx-callback.
670 */
671 if (!sport->dma_is_enabled) {
672 u32 ucr4 = imx_uart_readl(sport, UCR4);
673 ucr4 |= UCR4_TCEN;
674 imx_uart_writel(sport, ucr4, UCR4);
675 }
676 }
677
678 if (!sport->dma_is_enabled) {
679 ucr1 = imx_uart_readl(sport, UCR1);
680 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
681 }
682
683 if (sport->dma_is_enabled) {
684 if (sport->port.x_char) {
685 /* We have X-char to send, so enable TX IRQ and
686 * disable TX DMA to let TX interrupt to send X-char */
687 ucr1 = imx_uart_readl(sport, UCR1);
688 ucr1 &= ~UCR1_TXDMAEN;
689 ucr1 |= UCR1_TRDYEN;
690 imx_uart_writel(sport, ucr1, UCR1);
691 return;
692 }
693
694 if (!uart_circ_empty(&port->state->xmit) &&
695 !uart_tx_stopped(port))
696 imx_uart_dma_tx(sport);
697 return;
698 }
699 }
700
701 static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
702 {
703 struct imx_port *sport = dev_id;
704 u32 usr1;
705
706 imx_uart_writel(sport, USR1_RTSD, USR1);
707 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
708 uart_handle_cts_change(&sport->port, !!usr1);
709 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
710
711 return IRQ_HANDLED;
712 }
713
714 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
715 {
716 struct imx_port *sport = dev_id;
717 irqreturn_t ret;
718
719 spin_lock(&sport->port.lock);
720
721 ret = __imx_uart_rtsint(irq, dev_id);
722
723 spin_unlock(&sport->port.lock);
724
725 return ret;
726 }
727
728 static irqreturn_t imx_uart_txint(int irq, void *dev_id)
729 {
730 struct imx_port *sport = dev_id;
731
732 spin_lock(&sport->port.lock);
733 imx_uart_transmit_buffer(sport);
734 spin_unlock(&sport->port.lock);
735 return IRQ_HANDLED;
736 }
737
738 static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
739 {
740 struct imx_port *sport = dev_id;
741 unsigned int rx, flg, ignored = 0;
742 struct tty_port *port = &sport->port.state->port;
743
744 while (imx_uart_readl(sport, USR2) & USR2_RDR) {
745 u32 usr2;
746
747 flg = TTY_NORMAL;
748 sport->port.icount.rx++;
749
750 rx = imx_uart_readl(sport, URXD0);
751
752 usr2 = imx_uart_readl(sport, USR2);
753 if (usr2 & USR2_BRCD) {
754 imx_uart_writel(sport, USR2_BRCD, USR2);
755 if (uart_handle_break(&sport->port))
756 continue;
757 }
758
759 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
760 continue;
761
762 if (unlikely(rx & URXD_ERR)) {
763 if (rx & URXD_BRK)
764 sport->port.icount.brk++;
765 else if (rx & URXD_PRERR)
766 sport->port.icount.parity++;
767 else if (rx & URXD_FRMERR)
768 sport->port.icount.frame++;
769 if (rx & URXD_OVRRUN)
770 sport->port.icount.overrun++;
771
772 if (rx & sport->port.ignore_status_mask) {
773 if (++ignored > 100)
774 goto out;
775 continue;
776 }
777
778 rx &= (sport->port.read_status_mask | 0xFF);
779
780 if (rx & URXD_BRK)
781 flg = TTY_BREAK;
782 else if (rx & URXD_PRERR)
783 flg = TTY_PARITY;
784 else if (rx & URXD_FRMERR)
785 flg = TTY_FRAME;
786 if (rx & URXD_OVRRUN)
787 flg = TTY_OVERRUN;
788
789 sport->port.sysrq = 0;
790 }
791
792 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
793 goto out;
794
795 if (tty_insert_flip_char(port, rx, flg) == 0)
796 sport->port.icount.buf_overrun++;
797 }
798
799 out:
800 tty_flip_buffer_push(port);
801
802 return IRQ_HANDLED;
803 }
804
805 static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
806 {
807 struct imx_port *sport = dev_id;
808 irqreturn_t ret;
809
810 spin_lock(&sport->port.lock);
811
812 ret = __imx_uart_rxint(irq, dev_id);
813
814 spin_unlock(&sport->port.lock);
815
816 return ret;
817 }
818
819 static void imx_uart_clear_rx_errors(struct imx_port *sport);
820
821 /*
822 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
823 */
824 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
825 {
826 unsigned int tmp = TIOCM_DSR;
827 unsigned usr1 = imx_uart_readl(sport, USR1);
828 unsigned usr2 = imx_uart_readl(sport, USR2);
829
830 if (usr1 & USR1_RTSS)
831 tmp |= TIOCM_CTS;
832
833 /* in DCE mode DCDIN is always 0 */
834 if (!(usr2 & USR2_DCDIN))
835 tmp |= TIOCM_CAR;
836
837 if (sport->dte_mode)
838 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
839 tmp |= TIOCM_RI;
840
841 return tmp;
842 }
843
844 /*
845 * Handle any change of modem status signal since we were last called.
846 */
847 static void imx_uart_mctrl_check(struct imx_port *sport)
848 {
849 unsigned int status, changed;
850
851 status = imx_uart_get_hwmctrl(sport);
852 changed = status ^ sport->old_status;
853
854 if (changed == 0)
855 return;
856
857 sport->old_status = status;
858
859 if (changed & TIOCM_RI && status & TIOCM_RI)
860 sport->port.icount.rng++;
861 if (changed & TIOCM_DSR)
862 sport->port.icount.dsr++;
863 if (changed & TIOCM_CAR)
864 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
865 if (changed & TIOCM_CTS)
866 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
867
868 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
869 }
870
871 static irqreturn_t imx_uart_int(int irq, void *dev_id)
872 {
873 struct imx_port *sport = dev_id;
874 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
875 irqreturn_t ret = IRQ_NONE;
876
877 spin_lock(&sport->port.lock);
878
879 usr1 = imx_uart_readl(sport, USR1);
880 usr2 = imx_uart_readl(sport, USR2);
881 ucr1 = imx_uart_readl(sport, UCR1);
882 ucr2 = imx_uart_readl(sport, UCR2);
883 ucr3 = imx_uart_readl(sport, UCR3);
884 ucr4 = imx_uart_readl(sport, UCR4);
885
886 /*
887 * Even if a condition is true that can trigger an irq only handle it if
888 * the respective irq source is enabled. This prevents some undesired
889 * actions, for example if a character that sits in the RX FIFO and that
890 * should be fetched via DMA is tried to be fetched using PIO. Or the
891 * receiver is currently off and so reading from URXD0 results in an
892 * exception. So just mask the (raw) status bits for disabled irqs.
893 */
894 if ((ucr1 & UCR1_RRDYEN) == 0)
895 usr1 &= ~USR1_RRDY;
896 if ((ucr2 & UCR2_ATEN) == 0)
897 usr1 &= ~USR1_AGTIM;
898 if ((ucr1 & UCR1_TRDYEN) == 0)
899 usr1 &= ~USR1_TRDY;
900 if ((ucr4 & UCR4_TCEN) == 0)
901 usr2 &= ~USR2_TXDC;
902 if ((ucr3 & UCR3_DTRDEN) == 0)
903 usr1 &= ~USR1_DTRD;
904 if ((ucr1 & UCR1_RTSDEN) == 0)
905 usr1 &= ~USR1_RTSD;
906 if ((ucr3 & UCR3_AWAKEN) == 0)
907 usr1 &= ~USR1_AWAKE;
908 if ((ucr4 & UCR4_OREN) == 0)
909 usr2 &= ~USR2_ORE;
910
911 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
912 imx_uart_writel(sport, USR1_AGTIM, USR1);
913
914 __imx_uart_rxint(irq, dev_id);
915 ret = IRQ_HANDLED;
916 }
917
918 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
919 imx_uart_transmit_buffer(sport);
920 ret = IRQ_HANDLED;
921 }
922
923 if (usr1 & USR1_DTRD) {
924 imx_uart_writel(sport, USR1_DTRD, USR1);
925
926 imx_uart_mctrl_check(sport);
927
928 ret = IRQ_HANDLED;
929 }
930
931 if (usr1 & USR1_RTSD) {
932 __imx_uart_rtsint(irq, dev_id);
933 ret = IRQ_HANDLED;
934 }
935
936 if (usr1 & USR1_AWAKE) {
937 imx_uart_writel(sport, USR1_AWAKE, USR1);
938 ret = IRQ_HANDLED;
939 }
940
941 if (usr2 & USR2_ORE) {
942 sport->port.icount.overrun++;
943 imx_uart_writel(sport, USR2_ORE, USR2);
944 ret = IRQ_HANDLED;
945 }
946
947 spin_unlock(&sport->port.lock);
948
949 return ret;
950 }
951
952 /*
953 * Return TIOCSER_TEMT when transmitter is not busy.
954 */
955 static unsigned int imx_uart_tx_empty(struct uart_port *port)
956 {
957 struct imx_port *sport = (struct imx_port *)port;
958 unsigned int ret;
959
960 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
961
962 /* If the TX DMA is working, return 0. */
963 if (sport->dma_is_txing)
964 ret = 0;
965
966 return ret;
967 }
968
969 /* called with port.lock taken and irqs off */
970 static unsigned int imx_uart_get_mctrl(struct uart_port *port)
971 {
972 struct imx_port *sport = (struct imx_port *)port;
973 unsigned int ret = imx_uart_get_hwmctrl(sport);
974
975 mctrl_gpio_get(sport->gpios, &ret);
976
977 return ret;
978 }
979
980 /* called with port.lock taken and irqs off */
981 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
982 {
983 struct imx_port *sport = (struct imx_port *)port;
984 u32 ucr3, uts;
985
986 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
987 u32 ucr2;
988
989 /*
990 * Turn off autoRTS if RTS is lowered and restore autoRTS
991 * setting if RTS is raised.
992 */
993 ucr2 = imx_uart_readl(sport, UCR2);
994 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
995 if (mctrl & TIOCM_RTS) {
996 ucr2 |= UCR2_CTS;
997 /*
998 * UCR2_IRTS is unset if and only if the port is
999 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1000 * to get the state to restore to.
1001 */
1002 if (!(ucr2 & UCR2_IRTS))
1003 ucr2 |= UCR2_CTSC;
1004 }
1005 imx_uart_writel(sport, ucr2, UCR2);
1006 }
1007
1008 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1009 if (!(mctrl & TIOCM_DTR))
1010 ucr3 |= UCR3_DSR;
1011 imx_uart_writel(sport, ucr3, UCR3);
1012
1013 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1014 if (mctrl & TIOCM_LOOP)
1015 uts |= UTS_LOOP;
1016 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1017
1018 mctrl_gpio_set(sport->gpios, mctrl);
1019 }
1020
1021 /*
1022 * Interrupts always disabled.
1023 */
1024 static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1025 {
1026 struct imx_port *sport = (struct imx_port *)port;
1027 unsigned long flags;
1028 u32 ucr1;
1029
1030 spin_lock_irqsave(&sport->port.lock, flags);
1031
1032 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1033
1034 if (break_state != 0)
1035 ucr1 |= UCR1_SNDBRK;
1036
1037 imx_uart_writel(sport, ucr1, UCR1);
1038
1039 spin_unlock_irqrestore(&sport->port.lock, flags);
1040 }
1041
1042 /*
1043 * This is our per-port timeout handler, for checking the
1044 * modem status signals.
1045 */
1046 static void imx_uart_timeout(struct timer_list *t)
1047 {
1048 struct imx_port *sport = from_timer(sport, t, timer);
1049 unsigned long flags;
1050
1051 if (sport->port.state) {
1052 spin_lock_irqsave(&sport->port.lock, flags);
1053 imx_uart_mctrl_check(sport);
1054 spin_unlock_irqrestore(&sport->port.lock, flags);
1055
1056 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1057 }
1058 }
1059
1060 /*
1061 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1062 * [1] the RX DMA buffer is full.
1063 * [2] the aging timer expires
1064 *
1065 * Condition [2] is triggered when a character has been sitting in the FIFO
1066 * for at least 8 byte durations.
1067 */
1068 static void imx_uart_dma_rx_callback(void *data)
1069 {
1070 struct imx_port *sport = data;
1071 struct dma_chan *chan = sport->dma_chan_rx;
1072 struct scatterlist *sgl = &sport->rx_sgl;
1073 struct tty_port *port = &sport->port.state->port;
1074 struct dma_tx_state state;
1075 struct circ_buf *rx_ring = &sport->rx_ring;
1076 enum dma_status status;
1077 unsigned int w_bytes = 0;
1078 unsigned int r_bytes;
1079 unsigned int bd_size;
1080
1081 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1082
1083 if (status == DMA_ERROR) {
1084 imx_uart_clear_rx_errors(sport);
1085 return;
1086 }
1087
1088 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1089
1090 /*
1091 * The state-residue variable represents the empty space
1092 * relative to the entire buffer. Taking this in consideration
1093 * the head is always calculated base on the buffer total
1094 * length - DMA transaction residue. The UART script from the
1095 * SDMA firmware will jump to the next buffer descriptor,
1096 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1097 * Taking this in consideration the tail is always at the
1098 * beginning of the buffer descriptor that contains the head.
1099 */
1100
1101 /* Calculate the head */
1102 rx_ring->head = sg_dma_len(sgl) - state.residue;
1103
1104 /* Calculate the tail. */
1105 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1106 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1107
1108 if (rx_ring->head <= sg_dma_len(sgl) &&
1109 rx_ring->head > rx_ring->tail) {
1110
1111 /* Move data from tail to head */
1112 r_bytes = rx_ring->head - rx_ring->tail;
1113
1114 /* CPU claims ownership of RX DMA buffer */
1115 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1116 DMA_FROM_DEVICE);
1117
1118 w_bytes = tty_insert_flip_string(port,
1119 sport->rx_buf + rx_ring->tail, r_bytes);
1120
1121 /* UART retrieves ownership of RX DMA buffer */
1122 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1123 DMA_FROM_DEVICE);
1124
1125 if (w_bytes != r_bytes)
1126 sport->port.icount.buf_overrun++;
1127
1128 sport->port.icount.rx += w_bytes;
1129 } else {
1130 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1131 WARN_ON(rx_ring->head <= rx_ring->tail);
1132 }
1133 }
1134
1135 if (w_bytes) {
1136 tty_flip_buffer_push(port);
1137 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1138 }
1139 }
1140
1141 /* RX DMA buffer periods */
1142 #define RX_DMA_PERIODS 16
1143 #define RX_BUF_SIZE (RX_DMA_PERIODS * PAGE_SIZE / 4)
1144
1145 static int imx_uart_start_rx_dma(struct imx_port *sport)
1146 {
1147 struct scatterlist *sgl = &sport->rx_sgl;
1148 struct dma_chan *chan = sport->dma_chan_rx;
1149 struct device *dev = sport->port.dev;
1150 struct dma_async_tx_descriptor *desc;
1151 int ret;
1152
1153 sport->rx_ring.head = 0;
1154 sport->rx_ring.tail = 0;
1155 sport->rx_periods = RX_DMA_PERIODS;
1156
1157 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
1158 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1159 if (ret == 0) {
1160 dev_err(dev, "DMA mapping error for RX.\n");
1161 return -EINVAL;
1162 }
1163
1164 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1165 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1166 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1167
1168 if (!desc) {
1169 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1170 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1171 return -EINVAL;
1172 }
1173 desc->callback = imx_uart_dma_rx_callback;
1174 desc->callback_param = sport;
1175
1176 dev_dbg(dev, "RX: prepare for the DMA.\n");
1177 sport->dma_is_rxing = 1;
1178 sport->rx_cookie = dmaengine_submit(desc);
1179 dma_async_issue_pending(chan);
1180 return 0;
1181 }
1182
1183 static void imx_uart_clear_rx_errors(struct imx_port *sport)
1184 {
1185 struct tty_port *port = &sport->port.state->port;
1186 u32 usr1, usr2;
1187
1188 usr1 = imx_uart_readl(sport, USR1);
1189 usr2 = imx_uart_readl(sport, USR2);
1190
1191 if (usr2 & USR2_BRCD) {
1192 sport->port.icount.brk++;
1193 imx_uart_writel(sport, USR2_BRCD, USR2);
1194 uart_handle_break(&sport->port);
1195 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1196 sport->port.icount.buf_overrun++;
1197 tty_flip_buffer_push(port);
1198 } else {
1199 if (usr1 & USR1_FRAMERR) {
1200 sport->port.icount.frame++;
1201 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1202 } else if (usr1 & USR1_PARITYERR) {
1203 sport->port.icount.parity++;
1204 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1205 }
1206 }
1207
1208 if (usr2 & USR2_ORE) {
1209 sport->port.icount.overrun++;
1210 imx_uart_writel(sport, USR2_ORE, USR2);
1211 }
1212
1213 }
1214
1215 #define TXTL_DEFAULT 2 /* reset default */
1216 #define RXTL_DEFAULT 1 /* reset default */
1217 #define TXTL_DMA 8 /* DMA burst setting */
1218 #define RXTL_DMA 9 /* DMA burst setting */
1219
1220 static void imx_uart_setup_ufcr(struct imx_port *sport,
1221 unsigned char txwl, unsigned char rxwl)
1222 {
1223 unsigned int val;
1224
1225 /* set receiver / transmitter trigger level */
1226 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1227 val |= txwl << UFCR_TXTL_SHF | rxwl;
1228 imx_uart_writel(sport, val, UFCR);
1229 }
1230
1231 static void imx_uart_dma_exit(struct imx_port *sport)
1232 {
1233 if (sport->dma_chan_rx) {
1234 dmaengine_terminate_sync(sport->dma_chan_rx);
1235 dma_release_channel(sport->dma_chan_rx);
1236 sport->dma_chan_rx = NULL;
1237 sport->rx_cookie = -EINVAL;
1238 kfree(sport->rx_buf);
1239 sport->rx_buf = NULL;
1240 }
1241
1242 if (sport->dma_chan_tx) {
1243 dmaengine_terminate_sync(sport->dma_chan_tx);
1244 dma_release_channel(sport->dma_chan_tx);
1245 sport->dma_chan_tx = NULL;
1246 }
1247 }
1248
1249 static int imx_uart_dma_init(struct imx_port *sport)
1250 {
1251 struct dma_slave_config slave_config = {};
1252 struct device *dev = sport->port.dev;
1253 int ret;
1254
1255 /* Prepare for RX : */
1256 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1257 if (!sport->dma_chan_rx) {
1258 dev_dbg(dev, "cannot get the DMA channel.\n");
1259 ret = -EINVAL;
1260 goto err;
1261 }
1262
1263 slave_config.direction = DMA_DEV_TO_MEM;
1264 slave_config.src_addr = sport->port.mapbase + URXD0;
1265 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1266 /* one byte less than the watermark level to enable the aging timer */
1267 slave_config.src_maxburst = RXTL_DMA - 1;
1268 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1269 if (ret) {
1270 dev_err(dev, "error in RX dma configuration.\n");
1271 goto err;
1272 }
1273
1274 sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL);
1275 if (!sport->rx_buf) {
1276 ret = -ENOMEM;
1277 goto err;
1278 }
1279 sport->rx_ring.buf = sport->rx_buf;
1280
1281 /* Prepare for TX : */
1282 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1283 if (!sport->dma_chan_tx) {
1284 dev_err(dev, "cannot get the TX DMA channel!\n");
1285 ret = -EINVAL;
1286 goto err;
1287 }
1288
1289 slave_config.direction = DMA_MEM_TO_DEV;
1290 slave_config.dst_addr = sport->port.mapbase + URTX0;
1291 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1292 slave_config.dst_maxburst = TXTL_DMA;
1293 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1294 if (ret) {
1295 dev_err(dev, "error in TX dma configuration.");
1296 goto err;
1297 }
1298
1299 return 0;
1300 err:
1301 imx_uart_dma_exit(sport);
1302 return ret;
1303 }
1304
1305 static void imx_uart_enable_dma(struct imx_port *sport)
1306 {
1307 u32 ucr1;
1308
1309 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1310
1311 /* set UCR1 */
1312 ucr1 = imx_uart_readl(sport, UCR1);
1313 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1314 imx_uart_writel(sport, ucr1, UCR1);
1315
1316 sport->dma_is_enabled = 1;
1317 }
1318
1319 static void imx_uart_disable_dma(struct imx_port *sport)
1320 {
1321 u32 ucr1;
1322
1323 /* clear UCR1 */
1324 ucr1 = imx_uart_readl(sport, UCR1);
1325 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1326 imx_uart_writel(sport, ucr1, UCR1);
1327
1328 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1329
1330 sport->dma_is_enabled = 0;
1331 }
1332
1333 /* half the RX buffer size */
1334 #define CTSTL 16
1335
1336 static int imx_uart_startup(struct uart_port *port)
1337 {
1338 struct imx_port *sport = (struct imx_port *)port;
1339 int retval, i;
1340 unsigned long flags;
1341 int dma_is_inited = 0;
1342 u32 ucr1, ucr2, ucr3, ucr4;
1343
1344 retval = clk_prepare_enable(sport->clk_per);
1345 if (retval)
1346 return retval;
1347 retval = clk_prepare_enable(sport->clk_ipg);
1348 if (retval) {
1349 clk_disable_unprepare(sport->clk_per);
1350 return retval;
1351 }
1352
1353 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1354
1355 /* disable the DREN bit (Data Ready interrupt enable) before
1356 * requesting IRQs
1357 */
1358 ucr4 = imx_uart_readl(sport, UCR4);
1359
1360 /* set the trigger level for CTS */
1361 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1362 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1363
1364 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1365
1366 /* Can we enable the DMA support? */
1367 if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
1368 dma_is_inited = 1;
1369
1370 spin_lock_irqsave(&sport->port.lock, flags);
1371 /* Reset fifo's and state machines */
1372 i = 100;
1373
1374 ucr2 = imx_uart_readl(sport, UCR2);
1375 ucr2 &= ~UCR2_SRST;
1376 imx_uart_writel(sport, ucr2, UCR2);
1377
1378 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1379 udelay(1);
1380
1381 /*
1382 * Finally, clear and enable interrupts
1383 */
1384 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1385 imx_uart_writel(sport, USR2_ORE, USR2);
1386
1387 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1388 ucr1 |= UCR1_UARTEN;
1389 if (sport->have_rtscts)
1390 ucr1 |= UCR1_RTSDEN;
1391
1392 imx_uart_writel(sport, ucr1, UCR1);
1393
1394 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1395 if (!sport->dma_is_enabled)
1396 ucr4 |= UCR4_OREN;
1397 if (sport->inverted_rx)
1398 ucr4 |= UCR4_INVR;
1399 imx_uart_writel(sport, ucr4, UCR4);
1400
1401 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1402 /*
1403 * configure tx polarity before enabling tx
1404 */
1405 if (sport->inverted_tx)
1406 ucr3 |= UCR3_INVT;
1407
1408 if (!imx_uart_is_imx1(sport)) {
1409 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1410
1411 if (sport->dte_mode)
1412 /* disable broken interrupts */
1413 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1414 }
1415 imx_uart_writel(sport, ucr3, UCR3);
1416
1417 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1418 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1419 if (!sport->have_rtscts)
1420 ucr2 |= UCR2_IRTS;
1421 /*
1422 * make sure the edge sensitive RTS-irq is disabled,
1423 * we're using RTSD instead.
1424 */
1425 if (!imx_uart_is_imx1(sport))
1426 ucr2 &= ~UCR2_RTSEN;
1427 imx_uart_writel(sport, ucr2, UCR2);
1428
1429 /*
1430 * Enable modem status interrupts
1431 */
1432 imx_uart_enable_ms(&sport->port);
1433
1434 if (dma_is_inited) {
1435 imx_uart_enable_dma(sport);
1436 imx_uart_start_rx_dma(sport);
1437 } else {
1438 ucr1 = imx_uart_readl(sport, UCR1);
1439 ucr1 |= UCR1_RRDYEN;
1440 imx_uart_writel(sport, ucr1, UCR1);
1441
1442 ucr2 = imx_uart_readl(sport, UCR2);
1443 ucr2 |= UCR2_ATEN;
1444 imx_uart_writel(sport, ucr2, UCR2);
1445 }
1446
1447 spin_unlock_irqrestore(&sport->port.lock, flags);
1448
1449 return 0;
1450 }
1451
1452 static void imx_uart_shutdown(struct uart_port *port)
1453 {
1454 struct imx_port *sport = (struct imx_port *)port;
1455 unsigned long flags;
1456 u32 ucr1, ucr2, ucr4;
1457
1458 if (sport->dma_is_enabled) {
1459 dmaengine_terminate_sync(sport->dma_chan_tx);
1460 if (sport->dma_is_txing) {
1461 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1462 sport->dma_tx_nents, DMA_TO_DEVICE);
1463 sport->dma_is_txing = 0;
1464 }
1465 dmaengine_terminate_sync(sport->dma_chan_rx);
1466 if (sport->dma_is_rxing) {
1467 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1468 1, DMA_FROM_DEVICE);
1469 sport->dma_is_rxing = 0;
1470 }
1471
1472 spin_lock_irqsave(&sport->port.lock, flags);
1473 imx_uart_stop_tx(port);
1474 imx_uart_stop_rx(port);
1475 imx_uart_disable_dma(sport);
1476 spin_unlock_irqrestore(&sport->port.lock, flags);
1477 imx_uart_dma_exit(sport);
1478 }
1479
1480 mctrl_gpio_disable_ms(sport->gpios);
1481
1482 spin_lock_irqsave(&sport->port.lock, flags);
1483 ucr2 = imx_uart_readl(sport, UCR2);
1484 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1485 imx_uart_writel(sport, ucr2, UCR2);
1486
1487 ucr4 = imx_uart_readl(sport, UCR4);
1488 ucr4 &= ~UCR4_OREN;
1489 imx_uart_writel(sport, ucr4, UCR4);
1490 spin_unlock_irqrestore(&sport->port.lock, flags);
1491
1492 /*
1493 * Stop our timer.
1494 */
1495 del_timer_sync(&sport->timer);
1496
1497 /*
1498 * Disable all interrupts, port and break condition.
1499 */
1500
1501 spin_lock_irqsave(&sport->port.lock, flags);
1502 ucr1 = imx_uart_readl(sport, UCR1);
1503 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN);
1504
1505 imx_uart_writel(sport, ucr1, UCR1);
1506 spin_unlock_irqrestore(&sport->port.lock, flags);
1507
1508 clk_disable_unprepare(sport->clk_per);
1509 clk_disable_unprepare(sport->clk_ipg);
1510 }
1511
1512 /* called with port.lock taken and irqs off */
1513 static void imx_uart_flush_buffer(struct uart_port *port)
1514 {
1515 struct imx_port *sport = (struct imx_port *)port;
1516 struct scatterlist *sgl = &sport->tx_sgl[0];
1517 u32 ucr2;
1518 int i = 100, ubir, ubmr, uts;
1519
1520 if (!sport->dma_chan_tx)
1521 return;
1522
1523 sport->tx_bytes = 0;
1524 dmaengine_terminate_all(sport->dma_chan_tx);
1525 if (sport->dma_is_txing) {
1526 u32 ucr1;
1527
1528 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1529 DMA_TO_DEVICE);
1530 ucr1 = imx_uart_readl(sport, UCR1);
1531 ucr1 &= ~UCR1_TXDMAEN;
1532 imx_uart_writel(sport, ucr1, UCR1);
1533 sport->dma_is_txing = 0;
1534 }
1535
1536 /*
1537 * According to the Reference Manual description of the UART SRST bit:
1538 *
1539 * "Reset the transmit and receive state machines,
1540 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1541 * and UTS[6-3]".
1542 *
1543 * We don't need to restore the old values from USR1, USR2, URXD and
1544 * UTXD. UBRC is read only, so only save/restore the other three
1545 * registers.
1546 */
1547 ubir = imx_uart_readl(sport, UBIR);
1548 ubmr = imx_uart_readl(sport, UBMR);
1549 uts = imx_uart_readl(sport, IMX21_UTS);
1550
1551 ucr2 = imx_uart_readl(sport, UCR2);
1552 ucr2 &= ~UCR2_SRST;
1553 imx_uart_writel(sport, ucr2, UCR2);
1554
1555 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1556 udelay(1);
1557
1558 /* Restore the registers */
1559 imx_uart_writel(sport, ubir, UBIR);
1560 imx_uart_writel(sport, ubmr, UBMR);
1561 imx_uart_writel(sport, uts, IMX21_UTS);
1562 }
1563
1564 static void
1565 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1566 struct ktermios *old)
1567 {
1568 struct imx_port *sport = (struct imx_port *)port;
1569 unsigned long flags;
1570 u32 ucr2, old_ucr2, ufcr;
1571 unsigned int baud, quot;
1572 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1573 unsigned long div;
1574 unsigned long num, denom, old_ubir, old_ubmr;
1575 uint64_t tdiv64;
1576
1577 /*
1578 * We only support CS7 and CS8.
1579 */
1580 while ((termios->c_cflag & CSIZE) != CS7 &&
1581 (termios->c_cflag & CSIZE) != CS8) {
1582 termios->c_cflag &= ~CSIZE;
1583 termios->c_cflag |= old_csize;
1584 old_csize = CS8;
1585 }
1586
1587 del_timer_sync(&sport->timer);
1588
1589 /*
1590 * Ask the core to calculate the divisor for us.
1591 */
1592 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1593 quot = uart_get_divisor(port, baud);
1594
1595 spin_lock_irqsave(&sport->port.lock, flags);
1596
1597 /*
1598 * Read current UCR2 and save it for future use, then clear all the bits
1599 * except those we will or may need to preserve.
1600 */
1601 old_ucr2 = imx_uart_readl(sport, UCR2);
1602 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1603
1604 ucr2 |= UCR2_SRST | UCR2_IRTS;
1605 if ((termios->c_cflag & CSIZE) == CS8)
1606 ucr2 |= UCR2_WS;
1607
1608 if (!sport->have_rtscts)
1609 termios->c_cflag &= ~CRTSCTS;
1610
1611 if (port->rs485.flags & SER_RS485_ENABLED) {
1612 /*
1613 * RTS is mandatory for rs485 operation, so keep
1614 * it under manual control and keep transmitter
1615 * disabled.
1616 */
1617 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1618 imx_uart_rts_active(sport, &ucr2);
1619 else
1620 imx_uart_rts_inactive(sport, &ucr2);
1621
1622 } else if (termios->c_cflag & CRTSCTS) {
1623 /*
1624 * Only let receiver control RTS output if we were not requested
1625 * to have RTS inactive (which then should take precedence).
1626 */
1627 if (ucr2 & UCR2_CTS)
1628 ucr2 |= UCR2_CTSC;
1629 }
1630
1631 if (termios->c_cflag & CRTSCTS)
1632 ucr2 &= ~UCR2_IRTS;
1633
1634 if (termios->c_cflag & CSTOPB)
1635 ucr2 |= UCR2_STPB;
1636 if (termios->c_cflag & PARENB) {
1637 ucr2 |= UCR2_PREN;
1638 if (termios->c_cflag & PARODD)
1639 ucr2 |= UCR2_PROE;
1640 }
1641
1642 sport->port.read_status_mask = 0;
1643 if (termios->c_iflag & INPCK)
1644 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1645 if (termios->c_iflag & (BRKINT | PARMRK))
1646 sport->port.read_status_mask |= URXD_BRK;
1647
1648 /*
1649 * Characters to ignore
1650 */
1651 sport->port.ignore_status_mask = 0;
1652 if (termios->c_iflag & IGNPAR)
1653 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1654 if (termios->c_iflag & IGNBRK) {
1655 sport->port.ignore_status_mask |= URXD_BRK;
1656 /*
1657 * If we're ignoring parity and break indicators,
1658 * ignore overruns too (for real raw support).
1659 */
1660 if (termios->c_iflag & IGNPAR)
1661 sport->port.ignore_status_mask |= URXD_OVRRUN;
1662 }
1663
1664 if ((termios->c_cflag & CREAD) == 0)
1665 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1666
1667 /*
1668 * Update the per-port timeout.
1669 */
1670 uart_update_timeout(port, termios->c_cflag, baud);
1671
1672 /* custom-baudrate handling */
1673 div = sport->port.uartclk / (baud * 16);
1674 if (baud == 38400 && quot != div)
1675 baud = sport->port.uartclk / (quot * 16);
1676
1677 div = sport->port.uartclk / (baud * 16);
1678 if (div > 7)
1679 div = 7;
1680 if (!div)
1681 div = 1;
1682
1683 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1684 1 << 16, 1 << 16, &num, &denom);
1685
1686 tdiv64 = sport->port.uartclk;
1687 tdiv64 *= num;
1688 do_div(tdiv64, denom * 16 * div);
1689 tty_termios_encode_baud_rate(termios,
1690 (speed_t)tdiv64, (speed_t)tdiv64);
1691
1692 num -= 1;
1693 denom -= 1;
1694
1695 ufcr = imx_uart_readl(sport, UFCR);
1696 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1697 imx_uart_writel(sport, ufcr, UFCR);
1698
1699 /*
1700 * Two registers below should always be written both and in this
1701 * particular order. One consequence is that we need to check if any of
1702 * them changes and then update both. We do need the check for change
1703 * as even writing the same values seem to "restart"
1704 * transmission/receiving logic in the hardware, that leads to data
1705 * breakage even when rate doesn't in fact change. E.g., user switches
1706 * RTS/CTS handshake and suddenly gets broken bytes.
1707 */
1708 old_ubir = imx_uart_readl(sport, UBIR);
1709 old_ubmr = imx_uart_readl(sport, UBMR);
1710 if (old_ubir != num || old_ubmr != denom) {
1711 imx_uart_writel(sport, num, UBIR);
1712 imx_uart_writel(sport, denom, UBMR);
1713 }
1714
1715 if (!imx_uart_is_imx1(sport))
1716 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1717 IMX21_ONEMS);
1718
1719 imx_uart_writel(sport, ucr2, UCR2);
1720
1721 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1722 imx_uart_enable_ms(&sport->port);
1723
1724 spin_unlock_irqrestore(&sport->port.lock, flags);
1725 }
1726
1727 static const char *imx_uart_type(struct uart_port *port)
1728 {
1729 struct imx_port *sport = (struct imx_port *)port;
1730
1731 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1732 }
1733
1734 /*
1735 * Configure/autoconfigure the port.
1736 */
1737 static void imx_uart_config_port(struct uart_port *port, int flags)
1738 {
1739 struct imx_port *sport = (struct imx_port *)port;
1740
1741 if (flags & UART_CONFIG_TYPE)
1742 sport->port.type = PORT_IMX;
1743 }
1744
1745 /*
1746 * Verify the new serial_struct (for TIOCSSERIAL).
1747 * The only change we allow are to the flags and type, and
1748 * even then only between PORT_IMX and PORT_UNKNOWN
1749 */
1750 static int
1751 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1752 {
1753 struct imx_port *sport = (struct imx_port *)port;
1754 int ret = 0;
1755
1756 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1757 ret = -EINVAL;
1758 if (sport->port.irq != ser->irq)
1759 ret = -EINVAL;
1760 if (ser->io_type != UPIO_MEM)
1761 ret = -EINVAL;
1762 if (sport->port.uartclk / 16 != ser->baud_base)
1763 ret = -EINVAL;
1764 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1765 ret = -EINVAL;
1766 if (sport->port.iobase != ser->port)
1767 ret = -EINVAL;
1768 if (ser->hub6 != 0)
1769 ret = -EINVAL;
1770 return ret;
1771 }
1772
1773 #if defined(CONFIG_CONSOLE_POLL)
1774
1775 static int imx_uart_poll_init(struct uart_port *port)
1776 {
1777 struct imx_port *sport = (struct imx_port *)port;
1778 unsigned long flags;
1779 u32 ucr1, ucr2;
1780 int retval;
1781
1782 retval = clk_prepare_enable(sport->clk_ipg);
1783 if (retval)
1784 return retval;
1785 retval = clk_prepare_enable(sport->clk_per);
1786 if (retval)
1787 clk_disable_unprepare(sport->clk_ipg);
1788
1789 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1790
1791 spin_lock_irqsave(&sport->port.lock, flags);
1792
1793 /*
1794 * Be careful about the order of enabling bits here. First enable the
1795 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1796 * This prevents that a character that already sits in the RX fifo is
1797 * triggering an irq but the try to fetch it from there results in an
1798 * exception because UARTEN or RXEN is still off.
1799 */
1800 ucr1 = imx_uart_readl(sport, UCR1);
1801 ucr2 = imx_uart_readl(sport, UCR2);
1802
1803 if (imx_uart_is_imx1(sport))
1804 ucr1 |= IMX1_UCR1_UARTCLKEN;
1805
1806 ucr1 |= UCR1_UARTEN;
1807 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1808
1809 ucr2 |= UCR2_RXEN;
1810 ucr2 &= ~UCR2_ATEN;
1811
1812 imx_uart_writel(sport, ucr1, UCR1);
1813 imx_uart_writel(sport, ucr2, UCR2);
1814
1815 /* now enable irqs */
1816 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1817 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1818
1819 spin_unlock_irqrestore(&sport->port.lock, flags);
1820
1821 return 0;
1822 }
1823
1824 static int imx_uart_poll_get_char(struct uart_port *port)
1825 {
1826 struct imx_port *sport = (struct imx_port *)port;
1827 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1828 return NO_POLL_CHAR;
1829
1830 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1831 }
1832
1833 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1834 {
1835 struct imx_port *sport = (struct imx_port *)port;
1836 unsigned int status;
1837
1838 /* drain */
1839 do {
1840 status = imx_uart_readl(sport, USR1);
1841 } while (~status & USR1_TRDY);
1842
1843 /* write */
1844 imx_uart_writel(sport, c, URTX0);
1845
1846 /* flush */
1847 do {
1848 status = imx_uart_readl(sport, USR2);
1849 } while (~status & USR2_TXDC);
1850 }
1851 #endif
1852
1853 /* called with port.lock taken and irqs off or from .probe without locking */
1854 static int imx_uart_rs485_config(struct uart_port *port,
1855 struct serial_rs485 *rs485conf)
1856 {
1857 struct imx_port *sport = (struct imx_port *)port;
1858 u32 ucr2;
1859
1860 /* unimplemented */
1861 rs485conf->delay_rts_before_send = 0;
1862 rs485conf->delay_rts_after_send = 0;
1863
1864 /* RTS is required to control the transmitter */
1865 if (!sport->have_rtscts && !sport->have_rtsgpio)
1866 rs485conf->flags &= ~SER_RS485_ENABLED;
1867
1868 if (rs485conf->flags & SER_RS485_ENABLED) {
1869 /* Enable receiver if low-active RTS signal is requested */
1870 if (sport->have_rtscts && !sport->have_rtsgpio &&
1871 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1872 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1873
1874 /* disable transmitter */
1875 ucr2 = imx_uart_readl(sport, UCR2);
1876 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1877 imx_uart_rts_active(sport, &ucr2);
1878 else
1879 imx_uart_rts_inactive(sport, &ucr2);
1880 imx_uart_writel(sport, ucr2, UCR2);
1881 }
1882
1883 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1884 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1885 rs485conf->flags & SER_RS485_RX_DURING_TX)
1886 imx_uart_start_rx(port);
1887
1888 port->rs485 = *rs485conf;
1889
1890 return 0;
1891 }
1892
1893 static const struct uart_ops imx_uart_pops = {
1894 .tx_empty = imx_uart_tx_empty,
1895 .set_mctrl = imx_uart_set_mctrl,
1896 .get_mctrl = imx_uart_get_mctrl,
1897 .stop_tx = imx_uart_stop_tx,
1898 .start_tx = imx_uart_start_tx,
1899 .stop_rx = imx_uart_stop_rx,
1900 .enable_ms = imx_uart_enable_ms,
1901 .break_ctl = imx_uart_break_ctl,
1902 .startup = imx_uart_startup,
1903 .shutdown = imx_uart_shutdown,
1904 .flush_buffer = imx_uart_flush_buffer,
1905 .set_termios = imx_uart_set_termios,
1906 .type = imx_uart_type,
1907 .config_port = imx_uart_config_port,
1908 .verify_port = imx_uart_verify_port,
1909 #if defined(CONFIG_CONSOLE_POLL)
1910 .poll_init = imx_uart_poll_init,
1911 .poll_get_char = imx_uart_poll_get_char,
1912 .poll_put_char = imx_uart_poll_put_char,
1913 #endif
1914 };
1915
1916 static struct imx_port *imx_uart_ports[UART_NR];
1917
1918 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1919 static void imx_uart_console_putchar(struct uart_port *port, int ch)
1920 {
1921 struct imx_port *sport = (struct imx_port *)port;
1922
1923 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
1924 barrier();
1925
1926 imx_uart_writel(sport, ch, URTX0);
1927 }
1928
1929 /*
1930 * Interrupts are disabled on entering
1931 */
1932 static void
1933 imx_uart_console_write(struct console *co, const char *s, unsigned int count)
1934 {
1935 struct imx_port *sport = imx_uart_ports[co->index];
1936 struct imx_port_ucrs old_ucr;
1937 unsigned int ucr1;
1938 unsigned long flags = 0;
1939 int locked = 1;
1940 int retval;
1941
1942 retval = clk_enable(sport->clk_per);
1943 if (retval)
1944 return;
1945 retval = clk_enable(sport->clk_ipg);
1946 if (retval) {
1947 clk_disable(sport->clk_per);
1948 return;
1949 }
1950
1951 if (sport->port.sysrq)
1952 locked = 0;
1953 else if (oops_in_progress)
1954 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1955 else
1956 spin_lock_irqsave(&sport->port.lock, flags);
1957
1958 /*
1959 * First, save UCR1/2/3 and then disable interrupts
1960 */
1961 imx_uart_ucrs_save(sport, &old_ucr);
1962 ucr1 = old_ucr.ucr1;
1963
1964 if (imx_uart_is_imx1(sport))
1965 ucr1 |= IMX1_UCR1_UARTCLKEN;
1966 ucr1 |= UCR1_UARTEN;
1967 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1968
1969 imx_uart_writel(sport, ucr1, UCR1);
1970
1971 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
1972
1973 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
1974
1975 /*
1976 * Finally, wait for transmitter to become empty
1977 * and restore UCR1/2/3
1978 */
1979 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC));
1980
1981 imx_uart_ucrs_restore(sport, &old_ucr);
1982
1983 if (locked)
1984 spin_unlock_irqrestore(&sport->port.lock, flags);
1985
1986 clk_disable(sport->clk_ipg);
1987 clk_disable(sport->clk_per);
1988 }
1989
1990 /*
1991 * If the port was already initialised (eg, by a boot loader),
1992 * try to determine the current setup.
1993 */
1994 static void __init
1995 imx_uart_console_get_options(struct imx_port *sport, int *baud,
1996 int *parity, int *bits)
1997 {
1998
1999 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2000 /* ok, the port was enabled */
2001 unsigned int ucr2, ubir, ubmr, uartclk;
2002 unsigned int baud_raw;
2003 unsigned int ucfr_rfdiv;
2004
2005 ucr2 = imx_uart_readl(sport, UCR2);
2006
2007 *parity = 'n';
2008 if (ucr2 & UCR2_PREN) {
2009 if (ucr2 & UCR2_PROE)
2010 *parity = 'o';
2011 else
2012 *parity = 'e';
2013 }
2014
2015 if (ucr2 & UCR2_WS)
2016 *bits = 8;
2017 else
2018 *bits = 7;
2019
2020 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2021 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2022
2023 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2024 if (ucfr_rfdiv == 6)
2025 ucfr_rfdiv = 7;
2026 else
2027 ucfr_rfdiv = 6 - ucfr_rfdiv;
2028
2029 uartclk = clk_get_rate(sport->clk_per);
2030 uartclk /= ucfr_rfdiv;
2031
2032 { /*
2033 * The next code provides exact computation of
2034 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2035 * without need of float support or long long division,
2036 * which would be required to prevent 32bit arithmetic overflow
2037 */
2038 unsigned int mul = ubir + 1;
2039 unsigned int div = 16 * (ubmr + 1);
2040 unsigned int rem = uartclk % div;
2041
2042 baud_raw = (uartclk / div) * mul;
2043 baud_raw += (rem * mul + div / 2) / div;
2044 *baud = (baud_raw + 50) / 100 * 100;
2045 }
2046
2047 if (*baud != baud_raw)
2048 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2049 baud_raw, *baud);
2050 }
2051 }
2052
2053 static int __init
2054 imx_uart_console_setup(struct console *co, char *options)
2055 {
2056 struct imx_port *sport;
2057 int baud = 9600;
2058 int bits = 8;
2059 int parity = 'n';
2060 int flow = 'n';
2061 int retval;
2062
2063 /*
2064 * Check whether an invalid uart number has been specified, and
2065 * if so, search for the first available port that does have
2066 * console support.
2067 */
2068 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2069 co->index = 0;
2070 sport = imx_uart_ports[co->index];
2071 if (sport == NULL)
2072 return -ENODEV;
2073
2074 /* For setting the registers, we only need to enable the ipg clock. */
2075 retval = clk_prepare_enable(sport->clk_ipg);
2076 if (retval)
2077 goto error_console;
2078
2079 if (options)
2080 uart_parse_options(options, &baud, &parity, &bits, &flow);
2081 else
2082 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2083
2084 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2085
2086 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2087
2088 clk_disable(sport->clk_ipg);
2089 if (retval) {
2090 clk_unprepare(sport->clk_ipg);
2091 goto error_console;
2092 }
2093
2094 retval = clk_prepare(sport->clk_per);
2095 if (retval)
2096 clk_unprepare(sport->clk_ipg);
2097
2098 error_console:
2099 return retval;
2100 }
2101
2102 static struct uart_driver imx_uart_uart_driver;
2103 static struct console imx_uart_console = {
2104 .name = DEV_NAME,
2105 .write = imx_uart_console_write,
2106 .device = uart_console_device,
2107 .setup = imx_uart_console_setup,
2108 .flags = CON_PRINTBUFFER,
2109 .index = -1,
2110 .data = &imx_uart_uart_driver,
2111 };
2112
2113 #define IMX_CONSOLE &imx_uart_console
2114
2115 #ifdef CONFIG_OF
2116 static void imx_uart_console_early_putchar(struct uart_port *port, int ch)
2117 {
2118 struct imx_port *sport = (struct imx_port *)port;
2119
2120 while (imx_uart_readl(sport, IMX21_UTS) & UTS_TXFULL)
2121 cpu_relax();
2122
2123 imx_uart_writel(sport, ch, URTX0);
2124 }
2125
2126 static void imx_uart_console_early_write(struct console *con, const char *s,
2127 unsigned count)
2128 {
2129 struct earlycon_device *dev = con->data;
2130
2131 uart_console_write(&dev->port, s, count, imx_uart_console_early_putchar);
2132 }
2133
2134 static int __init
2135 imx_console_early_setup(struct earlycon_device *dev, const char *opt)
2136 {
2137 if (!dev->port.membase)
2138 return -ENODEV;
2139
2140 dev->con->write = imx_uart_console_early_write;
2141
2142 return 0;
2143 }
2144 OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
2145 OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
2146 #endif
2147
2148 #else
2149 #define IMX_CONSOLE NULL
2150 #endif
2151
2152 static struct uart_driver imx_uart_uart_driver = {
2153 .owner = THIS_MODULE,
2154 .driver_name = DRIVER_NAME,
2155 .dev_name = DEV_NAME,
2156 .major = SERIAL_IMX_MAJOR,
2157 .minor = MINOR_START,
2158 .nr = ARRAY_SIZE(imx_uart_ports),
2159 .cons = IMX_CONSOLE,
2160 };
2161
2162 #ifdef CONFIG_OF
2163 /*
2164 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
2165 * could successfully get all information from dt or a negative errno.
2166 */
2167 static int imx_uart_probe_dt(struct imx_port *sport,
2168 struct platform_device *pdev)
2169 {
2170 struct device_node *np = pdev->dev.of_node;
2171 int ret;
2172
2173 sport->devdata = of_device_get_match_data(&pdev->dev);
2174 if (!sport->devdata)
2175 /* no device tree device */
2176 return 1;
2177
2178 ret = of_alias_get_id(np, "serial");
2179 if (ret < 0) {
2180 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2181 return ret;
2182 }
2183 sport->port.line = ret;
2184
2185 if (of_get_property(np, "uart-has-rtscts", NULL) ||
2186 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
2187 sport->have_rtscts = 1;
2188
2189 if (of_get_property(np, "fsl,dte-mode", NULL))
2190 sport->dte_mode = 1;
2191
2192 if (of_get_property(np, "rts-gpios", NULL))
2193 sport->have_rtsgpio = 1;
2194
2195 if (of_get_property(np, "fsl,inverted-tx", NULL))
2196 sport->inverted_tx = 1;
2197
2198 if (of_get_property(np, "fsl,inverted-rx", NULL))
2199 sport->inverted_rx = 1;
2200
2201 return 0;
2202 }
2203 #else
2204 static inline int imx_uart_probe_dt(struct imx_port *sport,
2205 struct platform_device *pdev)
2206 {
2207 return 1;
2208 }
2209 #endif
2210
2211 static void imx_uart_probe_pdata(struct imx_port *sport,
2212 struct platform_device *pdev)
2213 {
2214 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
2215
2216 sport->port.line = pdev->id;
2217 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
2218
2219 if (!pdata)
2220 return;
2221
2222 if (pdata->flags & IMXUART_HAVE_RTSCTS)
2223 sport->have_rtscts = 1;
2224 }
2225
2226 static int imx_uart_probe(struct platform_device *pdev)
2227 {
2228 struct imx_port *sport;
2229 void __iomem *base;
2230 int ret = 0;
2231 u32 ucr1;
2232 struct resource *res;
2233 int txirq, rxirq, rtsirq;
2234
2235 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2236 if (!sport)
2237 return -ENOMEM;
2238
2239 ret = imx_uart_probe_dt(sport, pdev);
2240 if (ret > 0)
2241 imx_uart_probe_pdata(sport, pdev);
2242 else if (ret < 0)
2243 return ret;
2244
2245 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2246 dev_err(&pdev->dev, "serial%d out of range\n",
2247 sport->port.line);
2248 return -EINVAL;
2249 }
2250
2251 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2252 base = devm_ioremap_resource(&pdev->dev, res);
2253 if (IS_ERR(base))
2254 return PTR_ERR(base);
2255
2256 rxirq = platform_get_irq(pdev, 0);
2257 if (rxirq < 0)
2258 return rxirq;
2259 txirq = platform_get_irq_optional(pdev, 1);
2260 rtsirq = platform_get_irq_optional(pdev, 2);
2261
2262 sport->port.dev = &pdev->dev;
2263 sport->port.mapbase = res->start;
2264 sport->port.membase = base;
2265 sport->port.type = PORT_IMX,
2266 sport->port.iotype = UPIO_MEM;
2267 sport->port.irq = rxirq;
2268 sport->port.fifosize = 32;
2269 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2270 sport->port.ops = &imx_uart_pops;
2271 sport->port.rs485_config = imx_uart_rs485_config;
2272 sport->port.flags = UPF_BOOT_AUTOCONF;
2273 timer_setup(&sport->timer, imx_uart_timeout, 0);
2274
2275 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2276 if (IS_ERR(sport->gpios))
2277 return PTR_ERR(sport->gpios);
2278
2279 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2280 if (IS_ERR(sport->clk_ipg)) {
2281 ret = PTR_ERR(sport->clk_ipg);
2282 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2283 return ret;
2284 }
2285
2286 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2287 if (IS_ERR(sport->clk_per)) {
2288 ret = PTR_ERR(sport->clk_per);
2289 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2290 return ret;
2291 }
2292
2293 sport->port.uartclk = clk_get_rate(sport->clk_per);
2294
2295 /* For register access, we only need to enable the ipg clock. */
2296 ret = clk_prepare_enable(sport->clk_ipg);
2297 if (ret) {
2298 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
2299 return ret;
2300 }
2301
2302 /* initialize shadow register values */
2303 sport->ucr1 = readl(sport->port.membase + UCR1);
2304 sport->ucr2 = readl(sport->port.membase + UCR2);
2305 sport->ucr3 = readl(sport->port.membase + UCR3);
2306 sport->ucr4 = readl(sport->port.membase + UCR4);
2307 sport->ufcr = readl(sport->port.membase + UFCR);
2308
2309 ret = uart_get_rs485_mode(&sport->port);
2310 if (ret) {
2311 clk_disable_unprepare(sport->clk_ipg);
2312 return ret;
2313 }
2314
2315 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2316 (!sport->have_rtscts && !sport->have_rtsgpio))
2317 dev_err(&pdev->dev, "no RTS control, disabling rs485\n");
2318
2319 /*
2320 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2321 * signal cannot be set low during transmission in case the
2322 * receiver is off (limitation of the i.MX UART IP).
2323 */
2324 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2325 sport->have_rtscts && !sport->have_rtsgpio &&
2326 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2327 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2328 dev_err(&pdev->dev,
2329 "low-active RTS not possible when receiver is off, enabling receiver\n");
2330
2331 imx_uart_rs485_config(&sport->port, &sport->port.rs485);
2332
2333 /* Disable interrupts before requesting them */
2334 ucr1 = imx_uart_readl(sport, UCR1);
2335 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
2336 UCR1_TRDYEN | UCR1_RTSDEN);
2337 imx_uart_writel(sport, ucr1, UCR1);
2338
2339 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2340 /*
2341 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2342 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2343 * and DCD (when they are outputs) or enables the respective
2344 * irqs. So set this bit early, i.e. before requesting irqs.
2345 */
2346 u32 ufcr = imx_uart_readl(sport, UFCR);
2347 if (!(ufcr & UFCR_DCEDTE))
2348 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2349
2350 /*
2351 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2352 * enabled later because they cannot be cleared
2353 * (confirmed on i.MX25) which makes them unusable.
2354 */
2355 imx_uart_writel(sport,
2356 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2357 UCR3);
2358
2359 } else {
2360 u32 ucr3 = UCR3_DSR;
2361 u32 ufcr = imx_uart_readl(sport, UFCR);
2362 if (ufcr & UFCR_DCEDTE)
2363 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2364
2365 if (!imx_uart_is_imx1(sport))
2366 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2367 imx_uart_writel(sport, ucr3, UCR3);
2368 }
2369
2370 clk_disable_unprepare(sport->clk_ipg);
2371
2372 /*
2373 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2374 * chips only have one interrupt.
2375 */
2376 if (txirq > 0) {
2377 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2378 dev_name(&pdev->dev), sport);
2379 if (ret) {
2380 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2381 ret);
2382 return ret;
2383 }
2384
2385 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2386 dev_name(&pdev->dev), sport);
2387 if (ret) {
2388 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2389 ret);
2390 return ret;
2391 }
2392
2393 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2394 dev_name(&pdev->dev), sport);
2395 if (ret) {
2396 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2397 ret);
2398 return ret;
2399 }
2400 } else {
2401 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2402 dev_name(&pdev->dev), sport);
2403 if (ret) {
2404 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2405 return ret;
2406 }
2407 }
2408
2409 /* We need to initialize lock even for non-registered console */
2410 spin_lock_init(&sport->port.lock);
2411
2412 imx_uart_ports[sport->port.line] = sport;
2413
2414 platform_set_drvdata(pdev, sport);
2415
2416 return uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2417 }
2418
2419 static int imx_uart_remove(struct platform_device *pdev)
2420 {
2421 struct imx_port *sport = platform_get_drvdata(pdev);
2422
2423 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2424 }
2425
2426 static void imx_uart_restore_context(struct imx_port *sport)
2427 {
2428 unsigned long flags;
2429
2430 spin_lock_irqsave(&sport->port.lock, flags);
2431 if (!sport->context_saved) {
2432 spin_unlock_irqrestore(&sport->port.lock, flags);
2433 return;
2434 }
2435
2436 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2437 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2438 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2439 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2440 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2441 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2442 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2443 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2444 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2445 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2446 sport->context_saved = false;
2447 spin_unlock_irqrestore(&sport->port.lock, flags);
2448 }
2449
2450 static void imx_uart_save_context(struct imx_port *sport)
2451 {
2452 unsigned long flags;
2453
2454 /* Save necessary regs */
2455 spin_lock_irqsave(&sport->port.lock, flags);
2456 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2457 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2458 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2459 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2460 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2461 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2462 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2463 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2464 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2465 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2466 sport->context_saved = true;
2467 spin_unlock_irqrestore(&sport->port.lock, flags);
2468 }
2469
2470 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2471 {
2472 u32 ucr3;
2473
2474 ucr3 = imx_uart_readl(sport, UCR3);
2475 if (on) {
2476 imx_uart_writel(sport, USR1_AWAKE, USR1);
2477 ucr3 |= UCR3_AWAKEN;
2478 } else {
2479 ucr3 &= ~UCR3_AWAKEN;
2480 }
2481 imx_uart_writel(sport, ucr3, UCR3);
2482
2483 if (sport->have_rtscts) {
2484 u32 ucr1 = imx_uart_readl(sport, UCR1);
2485 if (on)
2486 ucr1 |= UCR1_RTSDEN;
2487 else
2488 ucr1 &= ~UCR1_RTSDEN;
2489 imx_uart_writel(sport, ucr1, UCR1);
2490 }
2491 }
2492
2493 static int imx_uart_suspend_noirq(struct device *dev)
2494 {
2495 struct imx_port *sport = dev_get_drvdata(dev);
2496
2497 imx_uart_save_context(sport);
2498
2499 clk_disable(sport->clk_ipg);
2500
2501 pinctrl_pm_select_sleep_state(dev);
2502
2503 return 0;
2504 }
2505
2506 static int imx_uart_resume_noirq(struct device *dev)
2507 {
2508 struct imx_port *sport = dev_get_drvdata(dev);
2509 int ret;
2510
2511 pinctrl_pm_select_default_state(dev);
2512
2513 ret = clk_enable(sport->clk_ipg);
2514 if (ret)
2515 return ret;
2516
2517 imx_uart_restore_context(sport);
2518
2519 return 0;
2520 }
2521
2522 static int imx_uart_suspend(struct device *dev)
2523 {
2524 struct imx_port *sport = dev_get_drvdata(dev);
2525 int ret;
2526
2527 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2528 disable_irq(sport->port.irq);
2529
2530 ret = clk_prepare_enable(sport->clk_ipg);
2531 if (ret)
2532 return ret;
2533
2534 /* enable wakeup from i.MX UART */
2535 imx_uart_enable_wakeup(sport, true);
2536
2537 return 0;
2538 }
2539
2540 static int imx_uart_resume(struct device *dev)
2541 {
2542 struct imx_port *sport = dev_get_drvdata(dev);
2543
2544 /* disable wakeup from i.MX UART */
2545 imx_uart_enable_wakeup(sport, false);
2546
2547 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2548 enable_irq(sport->port.irq);
2549
2550 clk_disable_unprepare(sport->clk_ipg);
2551
2552 return 0;
2553 }
2554
2555 static int imx_uart_freeze(struct device *dev)
2556 {
2557 struct imx_port *sport = dev_get_drvdata(dev);
2558
2559 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2560
2561 return clk_prepare_enable(sport->clk_ipg);
2562 }
2563
2564 static int imx_uart_thaw(struct device *dev)
2565 {
2566 struct imx_port *sport = dev_get_drvdata(dev);
2567
2568 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2569
2570 clk_disable_unprepare(sport->clk_ipg);
2571
2572 return 0;
2573 }
2574
2575 static const struct dev_pm_ops imx_uart_pm_ops = {
2576 .suspend_noirq = imx_uart_suspend_noirq,
2577 .resume_noirq = imx_uart_resume_noirq,
2578 .freeze_noirq = imx_uart_suspend_noirq,
2579 .restore_noirq = imx_uart_resume_noirq,
2580 .suspend = imx_uart_suspend,
2581 .resume = imx_uart_resume,
2582 .freeze = imx_uart_freeze,
2583 .thaw = imx_uart_thaw,
2584 .restore = imx_uart_thaw,
2585 };
2586
2587 static struct platform_driver imx_uart_platform_driver = {
2588 .probe = imx_uart_probe,
2589 .remove = imx_uart_remove,
2590
2591 .id_table = imx_uart_devtype,
2592 .driver = {
2593 .name = "imx-uart",
2594 .of_match_table = imx_uart_dt_ids,
2595 .pm = &imx_uart_pm_ops,
2596 },
2597 };
2598
2599 static int __init imx_uart_init(void)
2600 {
2601 int ret = uart_register_driver(&imx_uart_uart_driver);
2602
2603 if (ret)
2604 return ret;
2605
2606 ret = platform_driver_register(&imx_uart_platform_driver);
2607 if (ret != 0)
2608 uart_unregister_driver(&imx_uart_uart_driver);
2609
2610 return ret;
2611 }
2612
2613 static void __exit imx_uart_exit(void)
2614 {
2615 platform_driver_unregister(&imx_uart_platform_driver);
2616 uart_unregister_driver(&imx_uart_uart_driver);
2617 }
2618
2619 module_init(imx_uart_init);
2620 module_exit(imx_uart_exit);
2621
2622 MODULE_AUTHOR("Sascha Hauer");
2623 MODULE_DESCRIPTION("IMX generic serial port driver");
2624 MODULE_LICENSE("GPL");
2625 MODULE_ALIAS("platform:imx-uart");
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