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serial: imx: make sure unhandled irqs are disabled
[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / imx.c
1 /*
2 * Driver for Motorola/Freescale IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #define SUPPORT_SYSRQ
22 #endif
23
24 #include <linux/module.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial.h>
34 #include <linux/clk.h>
35 #include <linux/delay.h>
36 #include <linux/rational.h>
37 #include <linux/slab.h>
38 #include <linux/of.h>
39 #include <linux/of_device.h>
40 #include <linux/io.h>
41 #include <linux/dma-mapping.h>
42
43 #include <asm/irq.h>
44 #include <linux/platform_data/serial-imx.h>
45 #include <linux/platform_data/dma-imx.h>
46
47 #include "serial_mctrl_gpio.h"
48
49 /* Register definitions */
50 #define URXD0 0x0 /* Receiver Register */
51 #define URTX0 0x40 /* Transmitter Register */
52 #define UCR1 0x80 /* Control Register 1 */
53 #define UCR2 0x84 /* Control Register 2 */
54 #define UCR3 0x88 /* Control Register 3 */
55 #define UCR4 0x8c /* Control Register 4 */
56 #define UFCR 0x90 /* FIFO Control Register */
57 #define USR1 0x94 /* Status Register 1 */
58 #define USR2 0x98 /* Status Register 2 */
59 #define UESC 0x9c /* Escape Character Register */
60 #define UTIM 0xa0 /* Escape Timer Register */
61 #define UBIR 0xa4 /* BRM Incremental Register */
62 #define UBMR 0xa8 /* BRM Modulator Register */
63 #define UBRC 0xac /* Baud Rate Count Register */
64 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
65 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
66 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
67
68 /* UART Control Register Bit Fields.*/
69 #define URXD_DUMMY_READ (1<<16)
70 #define URXD_CHARRDY (1<<15)
71 #define URXD_ERR (1<<14)
72 #define URXD_OVRRUN (1<<13)
73 #define URXD_FRMERR (1<<12)
74 #define URXD_BRK (1<<11)
75 #define URXD_PRERR (1<<10)
76 #define URXD_RX_DATA (0xFF<<0)
77 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
78 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
79 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
80 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
81 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
82 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
83 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
84 #define UCR1_IREN (1<<7) /* Infrared interface enable */
85 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
86 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
87 #define UCR1_SNDBRK (1<<4) /* Send break */
88 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
89 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
90 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
91 #define UCR1_DOZE (1<<1) /* Doze */
92 #define UCR1_UARTEN (1<<0) /* UART enabled */
93 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
94 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
95 #define UCR2_CTSC (1<<13) /* CTS pin control */
96 #define UCR2_CTS (1<<12) /* Clear to send */
97 #define UCR2_ESCEN (1<<11) /* Escape enable */
98 #define UCR2_PREN (1<<8) /* Parity enable */
99 #define UCR2_PROE (1<<7) /* Parity odd/even */
100 #define UCR2_STPB (1<<6) /* Stop */
101 #define UCR2_WS (1<<5) /* Word size */
102 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
103 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
104 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
105 #define UCR2_RXEN (1<<1) /* Receiver enabled */
106 #define UCR2_SRST (1<<0) /* SW reset */
107 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
108 #define UCR3_PARERREN (1<<12) /* Parity enable */
109 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
110 #define UCR3_DSR (1<<10) /* Data set ready */
111 #define UCR3_DCD (1<<9) /* Data carrier detect */
112 #define UCR3_RI (1<<8) /* Ring indicator */
113 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
114 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
115 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
116 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
117 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
118 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
119 #define UCR3_BPEN (1<<0) /* Preset registers enable */
120 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
121 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
122 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
123 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
124 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
125 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
126 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
127 #define UCR4_IRSC (1<<5) /* IR special case */
128 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
129 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
130 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
131 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
132 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
133 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
134 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
135 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
136 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
137 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
138 #define USR1_RTSS (1<<14) /* RTS pin status */
139 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
140 #define USR1_RTSD (1<<12) /* RTS delta */
141 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
142 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
143 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
144 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
145 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
146 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
147 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
148 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
149 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
150 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
151 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
152 #define USR2_IDLE (1<<12) /* Idle condition */
153 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
154 #define USR2_RIIN (1<<9) /* Ring Indicator Input */
155 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
156 #define USR2_WAKE (1<<7) /* Wake */
157 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
158 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
159 #define USR2_TXDC (1<<3) /* Transmitter complete */
160 #define USR2_BRCD (1<<2) /* Break condition */
161 #define USR2_ORE (1<<1) /* Overrun error */
162 #define USR2_RDR (1<<0) /* Recv data ready */
163 #define UTS_FRCPERR (1<<13) /* Force parity error */
164 #define UTS_LOOP (1<<12) /* Loop tx and rx */
165 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
166 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
167 #define UTS_TXFULL (1<<4) /* TxFIFO full */
168 #define UTS_RXFULL (1<<3) /* RxFIFO full */
169 #define UTS_SOFTRST (1<<0) /* Software reset */
170
171 /* We've been assigned a range on the "Low-density serial ports" major */
172 #define SERIAL_IMX_MAJOR 207
173 #define MINOR_START 16
174 #define DEV_NAME "ttymxc"
175
176 /*
177 * This determines how often we check the modem status signals
178 * for any change. They generally aren't connected to an IRQ
179 * so we have to poll them. We also check immediately before
180 * filling the TX fifo incase CTS has been dropped.
181 */
182 #define MCTRL_TIMEOUT (250*HZ/1000)
183
184 #define DRIVER_NAME "IMX-uart"
185
186 #define UART_NR 8
187
188 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
189 enum imx_uart_type {
190 IMX1_UART,
191 IMX21_UART,
192 IMX6Q_UART,
193 };
194
195 /* device type dependent stuff */
196 struct imx_uart_data {
197 unsigned uts_reg;
198 enum imx_uart_type devtype;
199 };
200
201 struct imx_port {
202 struct uart_port port;
203 struct timer_list timer;
204 unsigned int old_status;
205 unsigned int have_rtscts:1;
206 unsigned int dte_mode:1;
207 unsigned int irda_inv_rx:1;
208 unsigned int irda_inv_tx:1;
209 unsigned short trcv_delay; /* transceiver delay */
210 struct clk *clk_ipg;
211 struct clk *clk_per;
212 const struct imx_uart_data *devdata;
213
214 struct mctrl_gpios *gpios;
215
216 /* DMA fields */
217 unsigned int dma_is_inited:1;
218 unsigned int dma_is_enabled:1;
219 unsigned int dma_is_rxing:1;
220 unsigned int dma_is_txing:1;
221 struct dma_chan *dma_chan_rx, *dma_chan_tx;
222 struct scatterlist rx_sgl, tx_sgl[2];
223 void *rx_buf;
224 unsigned int tx_bytes;
225 unsigned int dma_tx_nents;
226 wait_queue_head_t dma_wait;
227 unsigned int saved_reg[10];
228 bool context_saved;
229 };
230
231 struct imx_port_ucrs {
232 unsigned int ucr1;
233 unsigned int ucr2;
234 unsigned int ucr3;
235 };
236
237 static struct imx_uart_data imx_uart_devdata[] = {
238 [IMX1_UART] = {
239 .uts_reg = IMX1_UTS,
240 .devtype = IMX1_UART,
241 },
242 [IMX21_UART] = {
243 .uts_reg = IMX21_UTS,
244 .devtype = IMX21_UART,
245 },
246 [IMX6Q_UART] = {
247 .uts_reg = IMX21_UTS,
248 .devtype = IMX6Q_UART,
249 },
250 };
251
252 static const struct platform_device_id imx_uart_devtype[] = {
253 {
254 .name = "imx1-uart",
255 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
256 }, {
257 .name = "imx21-uart",
258 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
259 }, {
260 .name = "imx6q-uart",
261 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
262 }, {
263 /* sentinel */
264 }
265 };
266 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
267
268 static const struct of_device_id imx_uart_dt_ids[] = {
269 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
270 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
271 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
272 { /* sentinel */ }
273 };
274 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
275
276 static inline unsigned uts_reg(struct imx_port *sport)
277 {
278 return sport->devdata->uts_reg;
279 }
280
281 static inline int is_imx1_uart(struct imx_port *sport)
282 {
283 return sport->devdata->devtype == IMX1_UART;
284 }
285
286 static inline int is_imx21_uart(struct imx_port *sport)
287 {
288 return sport->devdata->devtype == IMX21_UART;
289 }
290
291 static inline int is_imx6q_uart(struct imx_port *sport)
292 {
293 return sport->devdata->devtype == IMX6Q_UART;
294 }
295 /*
296 * Save and restore functions for UCR1, UCR2 and UCR3 registers
297 */
298 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
299 static void imx_port_ucrs_save(struct uart_port *port,
300 struct imx_port_ucrs *ucr)
301 {
302 /* save control registers */
303 ucr->ucr1 = readl(port->membase + UCR1);
304 ucr->ucr2 = readl(port->membase + UCR2);
305 ucr->ucr3 = readl(port->membase + UCR3);
306 }
307
308 static void imx_port_ucrs_restore(struct uart_port *port,
309 struct imx_port_ucrs *ucr)
310 {
311 /* restore control registers */
312 writel(ucr->ucr1, port->membase + UCR1);
313 writel(ucr->ucr2, port->membase + UCR2);
314 writel(ucr->ucr3, port->membase + UCR3);
315 }
316 #endif
317
318 static void imx_port_rts_active(struct imx_port *sport, unsigned long *ucr2)
319 {
320 *ucr2 &= ~UCR2_CTSC;
321 *ucr2 |= UCR2_CTS;
322
323 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
324 }
325
326 static void imx_port_rts_inactive(struct imx_port *sport, unsigned long *ucr2)
327 {
328 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
329
330 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
331 }
332
333 static void imx_port_rts_auto(struct imx_port *sport, unsigned long *ucr2)
334 {
335 *ucr2 |= UCR2_CTSC;
336 }
337
338 /*
339 * interrupts disabled on entry
340 */
341 static void imx_stop_tx(struct uart_port *port)
342 {
343 struct imx_port *sport = (struct imx_port *)port;
344 unsigned long temp;
345
346 /*
347 * We are maybe in the SMP context, so if the DMA TX thread is running
348 * on other cpu, we have to wait for it to finish.
349 */
350 if (sport->dma_is_enabled && sport->dma_is_txing)
351 return;
352
353 temp = readl(port->membase + UCR1);
354 writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1);
355
356 /* in rs485 mode disable transmitter if shifter is empty */
357 if (port->rs485.flags & SER_RS485_ENABLED &&
358 readl(port->membase + USR2) & USR2_TXDC) {
359 temp = readl(port->membase + UCR2);
360 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
361 imx_port_rts_inactive(sport, &temp);
362 else
363 imx_port_rts_active(sport, &temp);
364 temp |= UCR2_RXEN;
365 writel(temp, port->membase + UCR2);
366
367 temp = readl(port->membase + UCR4);
368 temp &= ~UCR4_TCEN;
369 writel(temp, port->membase + UCR4);
370 }
371 }
372
373 /*
374 * interrupts disabled on entry
375 */
376 static void imx_stop_rx(struct uart_port *port)
377 {
378 struct imx_port *sport = (struct imx_port *)port;
379 unsigned long temp;
380
381 if (sport->dma_is_enabled && sport->dma_is_rxing) {
382 if (sport->port.suspended) {
383 dmaengine_terminate_all(sport->dma_chan_rx);
384 sport->dma_is_rxing = 0;
385 } else {
386 return;
387 }
388 }
389
390 temp = readl(sport->port.membase + UCR2);
391 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
392
393 /* disable the `Receiver Ready Interrrupt` */
394 temp = readl(sport->port.membase + UCR1);
395 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
396 }
397
398 /*
399 * Set the modem control timer to fire immediately.
400 */
401 static void imx_enable_ms(struct uart_port *port)
402 {
403 struct imx_port *sport = (struct imx_port *)port;
404
405 mod_timer(&sport->timer, jiffies);
406
407 mctrl_gpio_enable_ms(sport->gpios);
408 }
409
410 static void imx_dma_tx(struct imx_port *sport);
411 static inline void imx_transmit_buffer(struct imx_port *sport)
412 {
413 struct circ_buf *xmit = &sport->port.state->xmit;
414 unsigned long temp;
415
416 if (sport->port.x_char) {
417 /* Send next char */
418 writel(sport->port.x_char, sport->port.membase + URTX0);
419 sport->port.icount.tx++;
420 sport->port.x_char = 0;
421 return;
422 }
423
424 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
425 imx_stop_tx(&sport->port);
426 return;
427 }
428
429 if (sport->dma_is_enabled) {
430 /*
431 * We've just sent a X-char Ensure the TX DMA is enabled
432 * and the TX IRQ is disabled.
433 **/
434 temp = readl(sport->port.membase + UCR1);
435 temp &= ~UCR1_TXMPTYEN;
436 if (sport->dma_is_txing) {
437 temp |= UCR1_TDMAEN;
438 writel(temp, sport->port.membase + UCR1);
439 } else {
440 writel(temp, sport->port.membase + UCR1);
441 imx_dma_tx(sport);
442 }
443 }
444
445 while (!uart_circ_empty(xmit) &&
446 !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
447 /* send xmit->buf[xmit->tail]
448 * out the port here */
449 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
450 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
451 sport->port.icount.tx++;
452 }
453
454 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
455 uart_write_wakeup(&sport->port);
456
457 if (uart_circ_empty(xmit))
458 imx_stop_tx(&sport->port);
459 }
460
461 static void dma_tx_callback(void *data)
462 {
463 struct imx_port *sport = data;
464 struct scatterlist *sgl = &sport->tx_sgl[0];
465 struct circ_buf *xmit = &sport->port.state->xmit;
466 unsigned long flags;
467 unsigned long temp;
468
469 spin_lock_irqsave(&sport->port.lock, flags);
470
471 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
472
473 temp = readl(sport->port.membase + UCR1);
474 temp &= ~UCR1_TDMAEN;
475 writel(temp, sport->port.membase + UCR1);
476
477 /* update the stat */
478 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
479 sport->port.icount.tx += sport->tx_bytes;
480
481 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
482
483 sport->dma_is_txing = 0;
484
485 spin_unlock_irqrestore(&sport->port.lock, flags);
486
487 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
488 uart_write_wakeup(&sport->port);
489
490 if (waitqueue_active(&sport->dma_wait)) {
491 wake_up(&sport->dma_wait);
492 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
493 return;
494 }
495
496 spin_lock_irqsave(&sport->port.lock, flags);
497 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
498 imx_dma_tx(sport);
499 spin_unlock_irqrestore(&sport->port.lock, flags);
500 }
501
502 static void imx_dma_tx(struct imx_port *sport)
503 {
504 struct circ_buf *xmit = &sport->port.state->xmit;
505 struct scatterlist *sgl = sport->tx_sgl;
506 struct dma_async_tx_descriptor *desc;
507 struct dma_chan *chan = sport->dma_chan_tx;
508 struct device *dev = sport->port.dev;
509 unsigned long temp;
510 int ret;
511
512 if (sport->dma_is_txing)
513 return;
514
515 sport->tx_bytes = uart_circ_chars_pending(xmit);
516
517 if (xmit->tail < xmit->head) {
518 sport->dma_tx_nents = 1;
519 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
520 } else {
521 sport->dma_tx_nents = 2;
522 sg_init_table(sgl, 2);
523 sg_set_buf(sgl, xmit->buf + xmit->tail,
524 UART_XMIT_SIZE - xmit->tail);
525 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
526 }
527
528 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
529 if (ret == 0) {
530 dev_err(dev, "DMA mapping error for TX.\n");
531 return;
532 }
533 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
534 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
535 if (!desc) {
536 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
537 DMA_TO_DEVICE);
538 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
539 return;
540 }
541 desc->callback = dma_tx_callback;
542 desc->callback_param = sport;
543
544 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
545 uart_circ_chars_pending(xmit));
546
547 temp = readl(sport->port.membase + UCR1);
548 temp |= UCR1_TDMAEN;
549 writel(temp, sport->port.membase + UCR1);
550
551 /* fire it */
552 sport->dma_is_txing = 1;
553 dmaengine_submit(desc);
554 dma_async_issue_pending(chan);
555 return;
556 }
557
558 /*
559 * interrupts disabled on entry
560 */
561 static void imx_start_tx(struct uart_port *port)
562 {
563 struct imx_port *sport = (struct imx_port *)port;
564 unsigned long temp;
565
566 if (port->rs485.flags & SER_RS485_ENABLED) {
567 temp = readl(port->membase + UCR2);
568 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
569 imx_port_rts_inactive(sport, &temp);
570 else
571 imx_port_rts_active(sport, &temp);
572 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
573 temp &= ~UCR2_RXEN;
574 writel(temp, port->membase + UCR2);
575
576 /* enable transmitter and shifter empty irq */
577 temp = readl(port->membase + UCR4);
578 temp |= UCR4_TCEN;
579 writel(temp, port->membase + UCR4);
580 }
581
582 if (!sport->dma_is_enabled) {
583 temp = readl(sport->port.membase + UCR1);
584 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
585 }
586
587 if (sport->dma_is_enabled) {
588 if (sport->port.x_char) {
589 /* We have X-char to send, so enable TX IRQ and
590 * disable TX DMA to let TX interrupt to send X-char */
591 temp = readl(sport->port.membase + UCR1);
592 temp &= ~UCR1_TDMAEN;
593 temp |= UCR1_TXMPTYEN;
594 writel(temp, sport->port.membase + UCR1);
595 return;
596 }
597
598 if (!uart_circ_empty(&port->state->xmit) &&
599 !uart_tx_stopped(port))
600 imx_dma_tx(sport);
601 return;
602 }
603 }
604
605 static irqreturn_t imx_rtsint(int irq, void *dev_id)
606 {
607 struct imx_port *sport = dev_id;
608 unsigned int val;
609 unsigned long flags;
610
611 spin_lock_irqsave(&sport->port.lock, flags);
612
613 writel(USR1_RTSD, sport->port.membase + USR1);
614 val = readl(sport->port.membase + USR1) & USR1_RTSS;
615 uart_handle_cts_change(&sport->port, !!val);
616 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
617
618 spin_unlock_irqrestore(&sport->port.lock, flags);
619 return IRQ_HANDLED;
620 }
621
622 static irqreturn_t imx_txint(int irq, void *dev_id)
623 {
624 struct imx_port *sport = dev_id;
625 unsigned long flags;
626
627 spin_lock_irqsave(&sport->port.lock, flags);
628 imx_transmit_buffer(sport);
629 spin_unlock_irqrestore(&sport->port.lock, flags);
630 return IRQ_HANDLED;
631 }
632
633 static irqreturn_t imx_rxint(int irq, void *dev_id)
634 {
635 struct imx_port *sport = dev_id;
636 unsigned int rx, flg, ignored = 0;
637 struct tty_port *port = &sport->port.state->port;
638 unsigned long flags, temp;
639
640 spin_lock_irqsave(&sport->port.lock, flags);
641
642 while (readl(sport->port.membase + USR2) & USR2_RDR) {
643 flg = TTY_NORMAL;
644 sport->port.icount.rx++;
645
646 rx = readl(sport->port.membase + URXD0);
647
648 temp = readl(sport->port.membase + USR2);
649 if (temp & USR2_BRCD) {
650 writel(USR2_BRCD, sport->port.membase + USR2);
651 if (uart_handle_break(&sport->port))
652 continue;
653 }
654
655 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
656 continue;
657
658 if (unlikely(rx & URXD_ERR)) {
659 if (rx & URXD_BRK)
660 sport->port.icount.brk++;
661 else if (rx & URXD_PRERR)
662 sport->port.icount.parity++;
663 else if (rx & URXD_FRMERR)
664 sport->port.icount.frame++;
665 if (rx & URXD_OVRRUN)
666 sport->port.icount.overrun++;
667
668 if (rx & sport->port.ignore_status_mask) {
669 if (++ignored > 100)
670 goto out;
671 continue;
672 }
673
674 rx &= (sport->port.read_status_mask | 0xFF);
675
676 if (rx & URXD_BRK)
677 flg = TTY_BREAK;
678 else if (rx & URXD_PRERR)
679 flg = TTY_PARITY;
680 else if (rx & URXD_FRMERR)
681 flg = TTY_FRAME;
682 if (rx & URXD_OVRRUN)
683 flg = TTY_OVERRUN;
684
685 #ifdef SUPPORT_SYSRQ
686 sport->port.sysrq = 0;
687 #endif
688 }
689
690 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
691 goto out;
692
693 if (tty_insert_flip_char(port, rx, flg) == 0)
694 sport->port.icount.buf_overrun++;
695 }
696
697 out:
698 spin_unlock_irqrestore(&sport->port.lock, flags);
699 tty_flip_buffer_push(port);
700 return IRQ_HANDLED;
701 }
702
703 static int start_rx_dma(struct imx_port *sport);
704 /*
705 * If the RXFIFO is filled with some data, and then we
706 * arise a DMA operation to receive them.
707 */
708 static void imx_dma_rxint(struct imx_port *sport)
709 {
710 unsigned long temp;
711 unsigned long flags;
712
713 spin_lock_irqsave(&sport->port.lock, flags);
714
715 temp = readl(sport->port.membase + USR2);
716 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
717 sport->dma_is_rxing = 1;
718
719 /* disable the receiver ready and aging timer interrupts */
720 temp = readl(sport->port.membase + UCR1);
721 temp &= ~(UCR1_RRDYEN);
722 writel(temp, sport->port.membase + UCR1);
723
724 temp = readl(sport->port.membase + UCR2);
725 temp &= ~(UCR2_ATEN);
726 writel(temp, sport->port.membase + UCR2);
727
728 /* tell the DMA to receive the data. */
729 start_rx_dma(sport);
730 }
731
732 spin_unlock_irqrestore(&sport->port.lock, flags);
733 }
734
735 static irqreturn_t imx_int(int irq, void *dev_id)
736 {
737 struct imx_port *sport = dev_id;
738 unsigned int sts;
739 unsigned int sts2;
740 irqreturn_t ret = IRQ_NONE;
741
742 sts = readl(sport->port.membase + USR1);
743 sts2 = readl(sport->port.membase + USR2);
744
745 if (sts & (USR1_RRDY | USR1_AGTIM)) {
746 if (sport->dma_is_enabled)
747 imx_dma_rxint(sport);
748 else
749 imx_rxint(irq, dev_id);
750 ret = IRQ_HANDLED;
751 }
752
753 if ((sts & USR1_TRDY &&
754 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) ||
755 (sts2 & USR2_TXDC &&
756 readl(sport->port.membase + UCR4) & UCR4_TCEN)) {
757 imx_txint(irq, dev_id);
758 ret = IRQ_HANDLED;
759 }
760
761 if (sts & USR1_RTSD) {
762 imx_rtsint(irq, dev_id);
763 ret = IRQ_HANDLED;
764 }
765
766 if (sts & USR1_AWAKE) {
767 writel(USR1_AWAKE, sport->port.membase + USR1);
768 ret = IRQ_HANDLED;
769 }
770
771 if (sts2 & USR2_ORE) {
772 sport->port.icount.overrun++;
773 writel(USR2_ORE, sport->port.membase + USR2);
774 ret = IRQ_HANDLED;
775 }
776
777 return ret;
778 }
779
780 /*
781 * Return TIOCSER_TEMT when transmitter is not busy.
782 */
783 static unsigned int imx_tx_empty(struct uart_port *port)
784 {
785 struct imx_port *sport = (struct imx_port *)port;
786 unsigned int ret;
787
788 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
789
790 /* If the TX DMA is working, return 0. */
791 if (sport->dma_is_enabled && sport->dma_is_txing)
792 ret = 0;
793
794 return ret;
795 }
796
797 /*
798 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
799 */
800 static unsigned int imx_get_hwmctrl(struct imx_port *sport)
801 {
802 unsigned int tmp = TIOCM_DSR;
803 unsigned usr1 = readl(sport->port.membase + USR1);
804
805 if (usr1 & USR1_RTSS)
806 tmp |= TIOCM_CTS;
807
808 /* in DCE mode DCDIN is always 0 */
809 if (!(usr1 & USR2_DCDIN))
810 tmp |= TIOCM_CAR;
811
812 if (sport->dte_mode)
813 if (!(readl(sport->port.membase + USR2) & USR2_RIIN))
814 tmp |= TIOCM_RI;
815
816 return tmp;
817 }
818
819 static unsigned int imx_get_mctrl(struct uart_port *port)
820 {
821 struct imx_port *sport = (struct imx_port *)port;
822 unsigned int ret = imx_get_hwmctrl(sport);
823
824 mctrl_gpio_get(sport->gpios, &ret);
825
826 return ret;
827 }
828
829 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
830 {
831 struct imx_port *sport = (struct imx_port *)port;
832 unsigned long temp;
833
834 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
835 temp = readl(sport->port.membase + UCR2);
836 temp &= ~(UCR2_CTS | UCR2_CTSC);
837 if (mctrl & TIOCM_RTS)
838 temp |= UCR2_CTS | UCR2_CTSC;
839 writel(temp, sport->port.membase + UCR2);
840 }
841
842 temp = readl(sport->port.membase + UCR3) & ~UCR3_DSR;
843 if (!(mctrl & TIOCM_DTR))
844 temp |= UCR3_DSR;
845 writel(temp, sport->port.membase + UCR3);
846
847 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
848 if (mctrl & TIOCM_LOOP)
849 temp |= UTS_LOOP;
850 writel(temp, sport->port.membase + uts_reg(sport));
851
852 mctrl_gpio_set(sport->gpios, mctrl);
853 }
854
855 /*
856 * Interrupts always disabled.
857 */
858 static void imx_break_ctl(struct uart_port *port, int break_state)
859 {
860 struct imx_port *sport = (struct imx_port *)port;
861 unsigned long flags, temp;
862
863 spin_lock_irqsave(&sport->port.lock, flags);
864
865 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
866
867 if (break_state != 0)
868 temp |= UCR1_SNDBRK;
869
870 writel(temp, sport->port.membase + UCR1);
871
872 spin_unlock_irqrestore(&sport->port.lock, flags);
873 }
874
875 /*
876 * Handle any change of modem status signal since we were last called.
877 */
878 static void imx_mctrl_check(struct imx_port *sport)
879 {
880 unsigned int status, changed;
881
882 status = imx_get_hwmctrl(sport);
883 changed = status ^ sport->old_status;
884
885 if (changed == 0)
886 return;
887
888 sport->old_status = status;
889
890 if (changed & TIOCM_RI)
891 sport->port.icount.rng++;
892 if (changed & TIOCM_DSR)
893 sport->port.icount.dsr++;
894 if (changed & TIOCM_CAR)
895 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
896 if (changed & TIOCM_CTS)
897 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
898
899 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
900 }
901
902 /*
903 * This is our per-port timeout handler, for checking the
904 * modem status signals.
905 */
906 static void imx_timeout(unsigned long data)
907 {
908 struct imx_port *sport = (struct imx_port *)data;
909 unsigned long flags;
910
911 if (sport->port.state) {
912 spin_lock_irqsave(&sport->port.lock, flags);
913 imx_mctrl_check(sport);
914 spin_unlock_irqrestore(&sport->port.lock, flags);
915
916 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
917 }
918 }
919
920 #define RX_BUF_SIZE (PAGE_SIZE)
921 static void imx_rx_dma_done(struct imx_port *sport)
922 {
923 unsigned long temp;
924 unsigned long flags;
925
926 spin_lock_irqsave(&sport->port.lock, flags);
927
928 /* re-enable interrupts to get notified when new symbols are incoming */
929 temp = readl(sport->port.membase + UCR1);
930 temp |= UCR1_RRDYEN;
931 writel(temp, sport->port.membase + UCR1);
932
933 temp = readl(sport->port.membase + UCR2);
934 temp |= UCR2_ATEN;
935 writel(temp, sport->port.membase + UCR2);
936
937 sport->dma_is_rxing = 0;
938
939 /* Is the shutdown waiting for us? */
940 if (waitqueue_active(&sport->dma_wait))
941 wake_up(&sport->dma_wait);
942
943 spin_unlock_irqrestore(&sport->port.lock, flags);
944 }
945
946 /*
947 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
948 * [1] the RX DMA buffer is full.
949 * [2] the aging timer expires
950 *
951 * Condition [2] is triggered when a character has been sitting in the FIFO
952 * for at least 8 byte durations.
953 */
954 static void dma_rx_callback(void *data)
955 {
956 struct imx_port *sport = data;
957 struct dma_chan *chan = sport->dma_chan_rx;
958 struct scatterlist *sgl = &sport->rx_sgl;
959 struct tty_port *port = &sport->port.state->port;
960 struct dma_tx_state state;
961 enum dma_status status;
962 unsigned int count;
963
964 /* unmap it first */
965 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
966
967 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
968 count = RX_BUF_SIZE - state.residue;
969
970 dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
971
972 if (count) {
973 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
974 int bytes = tty_insert_flip_string(port, sport->rx_buf,
975 count);
976
977 if (bytes != count)
978 sport->port.icount.buf_overrun++;
979 }
980 tty_flip_buffer_push(port);
981 sport->port.icount.rx += count;
982 }
983
984 /*
985 * Restart RX DMA directly if more data is available in order to skip
986 * the roundtrip through the IRQ handler. If there is some data already
987 * in the FIFO, DMA needs to be restarted soon anyways.
988 *
989 * Otherwise stop the DMA and reactivate FIFO IRQs to restart DMA once
990 * data starts to arrive again.
991 */
992 if (readl(sport->port.membase + USR2) & USR2_RDR)
993 start_rx_dma(sport);
994 else
995 imx_rx_dma_done(sport);
996 }
997
998 static int start_rx_dma(struct imx_port *sport)
999 {
1000 struct scatterlist *sgl = &sport->rx_sgl;
1001 struct dma_chan *chan = sport->dma_chan_rx;
1002 struct device *dev = sport->port.dev;
1003 struct dma_async_tx_descriptor *desc;
1004 int ret;
1005
1006 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
1007 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1008 if (ret == 0) {
1009 dev_err(dev, "DMA mapping error for RX.\n");
1010 return -EINVAL;
1011 }
1012 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
1013 DMA_PREP_INTERRUPT);
1014 if (!desc) {
1015 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1016 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1017 return -EINVAL;
1018 }
1019 desc->callback = dma_rx_callback;
1020 desc->callback_param = sport;
1021
1022 dev_dbg(dev, "RX: prepare for the DMA.\n");
1023 dmaengine_submit(desc);
1024 dma_async_issue_pending(chan);
1025 return 0;
1026 }
1027
1028 #define TXTL_DEFAULT 2 /* reset default */
1029 #define RXTL_DEFAULT 1 /* reset default */
1030 #define TXTL_DMA 8 /* DMA burst setting */
1031 #define RXTL_DMA 9 /* DMA burst setting */
1032
1033 static void imx_setup_ufcr(struct imx_port *sport,
1034 unsigned char txwl, unsigned char rxwl)
1035 {
1036 unsigned int val;
1037
1038 /* set receiver / transmitter trigger level */
1039 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1040 val |= txwl << UFCR_TXTL_SHF | rxwl;
1041 writel(val, sport->port.membase + UFCR);
1042 }
1043
1044 static void imx_uart_dma_exit(struct imx_port *sport)
1045 {
1046 if (sport->dma_chan_rx) {
1047 dma_release_channel(sport->dma_chan_rx);
1048 sport->dma_chan_rx = NULL;
1049
1050 kfree(sport->rx_buf);
1051 sport->rx_buf = NULL;
1052 }
1053
1054 if (sport->dma_chan_tx) {
1055 dma_release_channel(sport->dma_chan_tx);
1056 sport->dma_chan_tx = NULL;
1057 }
1058
1059 sport->dma_is_inited = 0;
1060 }
1061
1062 static int imx_uart_dma_init(struct imx_port *sport)
1063 {
1064 struct dma_slave_config slave_config = {};
1065 struct device *dev = sport->port.dev;
1066 int ret;
1067
1068 /* Prepare for RX : */
1069 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1070 if (!sport->dma_chan_rx) {
1071 dev_dbg(dev, "cannot get the DMA channel.\n");
1072 ret = -EINVAL;
1073 goto err;
1074 }
1075
1076 slave_config.direction = DMA_DEV_TO_MEM;
1077 slave_config.src_addr = sport->port.mapbase + URXD0;
1078 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1079 /* one byte less than the watermark level to enable the aging timer */
1080 slave_config.src_maxburst = RXTL_DMA - 1;
1081 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1082 if (ret) {
1083 dev_err(dev, "error in RX dma configuration.\n");
1084 goto err;
1085 }
1086
1087 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1088 if (!sport->rx_buf) {
1089 ret = -ENOMEM;
1090 goto err;
1091 }
1092
1093 /* Prepare for TX : */
1094 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1095 if (!sport->dma_chan_tx) {
1096 dev_err(dev, "cannot get the TX DMA channel!\n");
1097 ret = -EINVAL;
1098 goto err;
1099 }
1100
1101 slave_config.direction = DMA_MEM_TO_DEV;
1102 slave_config.dst_addr = sport->port.mapbase + URTX0;
1103 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1104 slave_config.dst_maxburst = TXTL_DMA;
1105 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1106 if (ret) {
1107 dev_err(dev, "error in TX dma configuration.");
1108 goto err;
1109 }
1110
1111 sport->dma_is_inited = 1;
1112
1113 return 0;
1114 err:
1115 imx_uart_dma_exit(sport);
1116 return ret;
1117 }
1118
1119 static void imx_enable_dma(struct imx_port *sport)
1120 {
1121 unsigned long temp;
1122
1123 init_waitqueue_head(&sport->dma_wait);
1124
1125 /* set UCR1 */
1126 temp = readl(sport->port.membase + UCR1);
1127 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN;
1128 writel(temp, sport->port.membase + UCR1);
1129
1130 temp = readl(sport->port.membase + UCR2);
1131 temp |= UCR2_ATEN;
1132 writel(temp, sport->port.membase + UCR2);
1133
1134 imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1135
1136 sport->dma_is_enabled = 1;
1137 }
1138
1139 static void imx_disable_dma(struct imx_port *sport)
1140 {
1141 unsigned long temp;
1142
1143 /* clear UCR1 */
1144 temp = readl(sport->port.membase + UCR1);
1145 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1146 writel(temp, sport->port.membase + UCR1);
1147
1148 /* clear UCR2 */
1149 temp = readl(sport->port.membase + UCR2);
1150 temp &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN);
1151 writel(temp, sport->port.membase + UCR2);
1152
1153 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1154
1155 sport->dma_is_enabled = 0;
1156 }
1157
1158 /* half the RX buffer size */
1159 #define CTSTL 16
1160
1161 static int imx_startup(struct uart_port *port)
1162 {
1163 struct imx_port *sport = (struct imx_port *)port;
1164 int retval, i;
1165 unsigned long flags, temp;
1166
1167 retval = clk_prepare_enable(sport->clk_per);
1168 if (retval)
1169 return retval;
1170 retval = clk_prepare_enable(sport->clk_ipg);
1171 if (retval) {
1172 clk_disable_unprepare(sport->clk_per);
1173 return retval;
1174 }
1175
1176 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1177
1178 /* disable the DREN bit (Data Ready interrupt enable) before
1179 * requesting IRQs
1180 */
1181 temp = readl(sport->port.membase + UCR4);
1182
1183 /* set the trigger level for CTS */
1184 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1185 temp |= CTSTL << UCR4_CTSTL_SHF;
1186
1187 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1188
1189 /* Can we enable the DMA support? */
1190 if (is_imx6q_uart(sport) && !uart_console(port) &&
1191 !sport->dma_is_inited)
1192 imx_uart_dma_init(sport);
1193
1194 spin_lock_irqsave(&sport->port.lock, flags);
1195 /* Reset fifo's and state machines */
1196 i = 100;
1197
1198 temp = readl(sport->port.membase + UCR2);
1199 temp &= ~UCR2_SRST;
1200 writel(temp, sport->port.membase + UCR2);
1201
1202 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1203 udelay(1);
1204
1205 /*
1206 * Finally, clear and enable interrupts
1207 */
1208 writel(USR1_RTSD, sport->port.membase + USR1);
1209 writel(USR2_ORE, sport->port.membase + USR2);
1210
1211 if (sport->dma_is_inited && !sport->dma_is_enabled)
1212 imx_enable_dma(sport);
1213
1214 temp = readl(sport->port.membase + UCR1);
1215 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
1216
1217 writel(temp, sport->port.membase + UCR1);
1218
1219 temp = readl(sport->port.membase + UCR4);
1220 temp |= UCR4_OREN;
1221 writel(temp, sport->port.membase + UCR4);
1222
1223 temp = readl(sport->port.membase + UCR2);
1224 temp |= (UCR2_RXEN | UCR2_TXEN);
1225 if (!sport->have_rtscts)
1226 temp |= UCR2_IRTS;
1227 /*
1228 * make sure the edge sensitive RTS-irq is disabled,
1229 * we're using RTSD instead.
1230 */
1231 if (!is_imx1_uart(sport))
1232 temp &= ~UCR2_RTSEN;
1233 writel(temp, sport->port.membase + UCR2);
1234
1235 if (!is_imx1_uart(sport)) {
1236 temp = readl(sport->port.membase + UCR3);
1237
1238 /*
1239 * The effect of RI and DCD differs depending on the UFCR_DCEDTE
1240 * bit. In DCE mode they control the outputs, in DTE mode they
1241 * enable the respective irqs. At least the DCD irq cannot be
1242 * cleared on i.MX25 at least, so it's not usable and must be
1243 * disabled. I don't have test hardware to check if RI has the
1244 * same problem but I consider this likely so it's disabled for
1245 * now, too.
1246 */
1247 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP |
1248 UCR3_RI | UCR3_DCD;
1249
1250 if (sport->dte_mode)
1251 temp &= ~(UCR3_RI | UCR3_DCD);
1252
1253 writel(temp, sport->port.membase + UCR3);
1254 }
1255
1256 /*
1257 * Enable modem status interrupts
1258 */
1259 imx_enable_ms(&sport->port);
1260 spin_unlock_irqrestore(&sport->port.lock, flags);
1261
1262 return 0;
1263 }
1264
1265 static void imx_shutdown(struct uart_port *port)
1266 {
1267 struct imx_port *sport = (struct imx_port *)port;
1268 unsigned long temp;
1269 unsigned long flags;
1270
1271 if (sport->dma_is_enabled) {
1272 int ret;
1273
1274 /* We have to wait for the DMA to finish. */
1275 ret = wait_event_interruptible(sport->dma_wait,
1276 !sport->dma_is_rxing && !sport->dma_is_txing);
1277 if (ret != 0) {
1278 sport->dma_is_rxing = 0;
1279 sport->dma_is_txing = 0;
1280 dmaengine_terminate_all(sport->dma_chan_tx);
1281 dmaengine_terminate_all(sport->dma_chan_rx);
1282 }
1283 spin_lock_irqsave(&sport->port.lock, flags);
1284 imx_stop_tx(port);
1285 imx_stop_rx(port);
1286 imx_disable_dma(sport);
1287 spin_unlock_irqrestore(&sport->port.lock, flags);
1288 imx_uart_dma_exit(sport);
1289 }
1290
1291 mctrl_gpio_disable_ms(sport->gpios);
1292
1293 spin_lock_irqsave(&sport->port.lock, flags);
1294 temp = readl(sport->port.membase + UCR2);
1295 temp &= ~(UCR2_TXEN);
1296 writel(temp, sport->port.membase + UCR2);
1297 spin_unlock_irqrestore(&sport->port.lock, flags);
1298
1299 /*
1300 * Stop our timer.
1301 */
1302 del_timer_sync(&sport->timer);
1303
1304 /*
1305 * Disable all interrupts, port and break condition.
1306 */
1307
1308 spin_lock_irqsave(&sport->port.lock, flags);
1309 temp = readl(sport->port.membase + UCR1);
1310 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1311
1312 writel(temp, sport->port.membase + UCR1);
1313 spin_unlock_irqrestore(&sport->port.lock, flags);
1314
1315 clk_disable_unprepare(sport->clk_per);
1316 clk_disable_unprepare(sport->clk_ipg);
1317 }
1318
1319 static void imx_flush_buffer(struct uart_port *port)
1320 {
1321 struct imx_port *sport = (struct imx_port *)port;
1322 struct scatterlist *sgl = &sport->tx_sgl[0];
1323 unsigned long temp;
1324 int i = 100, ubir, ubmr, uts;
1325
1326 if (!sport->dma_chan_tx)
1327 return;
1328
1329 sport->tx_bytes = 0;
1330 dmaengine_terminate_all(sport->dma_chan_tx);
1331 if (sport->dma_is_txing) {
1332 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1333 DMA_TO_DEVICE);
1334 temp = readl(sport->port.membase + UCR1);
1335 temp &= ~UCR1_TDMAEN;
1336 writel(temp, sport->port.membase + UCR1);
1337 sport->dma_is_txing = false;
1338 }
1339
1340 /*
1341 * According to the Reference Manual description of the UART SRST bit:
1342 * "Reset the transmit and receive state machines,
1343 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1344 * and UTS[6-3]". As we don't need to restore the old values from
1345 * USR1, USR2, URXD, UTXD, only save/restore the other four registers
1346 */
1347 ubir = readl(sport->port.membase + UBIR);
1348 ubmr = readl(sport->port.membase + UBMR);
1349 uts = readl(sport->port.membase + IMX21_UTS);
1350
1351 temp = readl(sport->port.membase + UCR2);
1352 temp &= ~UCR2_SRST;
1353 writel(temp, sport->port.membase + UCR2);
1354
1355 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1356 udelay(1);
1357
1358 /* Restore the registers */
1359 writel(ubir, sport->port.membase + UBIR);
1360 writel(ubmr, sport->port.membase + UBMR);
1361 writel(uts, sport->port.membase + IMX21_UTS);
1362 }
1363
1364 static void
1365 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1366 struct ktermios *old)
1367 {
1368 struct imx_port *sport = (struct imx_port *)port;
1369 unsigned long flags;
1370 unsigned long ucr2, old_ucr1, old_ucr2;
1371 unsigned int baud, quot;
1372 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1373 unsigned long div, ufcr;
1374 unsigned long num, denom;
1375 uint64_t tdiv64;
1376
1377 /*
1378 * We only support CS7 and CS8.
1379 */
1380 while ((termios->c_cflag & CSIZE) != CS7 &&
1381 (termios->c_cflag & CSIZE) != CS8) {
1382 termios->c_cflag &= ~CSIZE;
1383 termios->c_cflag |= old_csize;
1384 old_csize = CS8;
1385 }
1386
1387 if ((termios->c_cflag & CSIZE) == CS8)
1388 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1389 else
1390 ucr2 = UCR2_SRST | UCR2_IRTS;
1391
1392 if (termios->c_cflag & CRTSCTS) {
1393 if (sport->have_rtscts) {
1394 ucr2 &= ~UCR2_IRTS;
1395
1396 if (port->rs485.flags & SER_RS485_ENABLED) {
1397 /*
1398 * RTS is mandatory for rs485 operation, so keep
1399 * it under manual control and keep transmitter
1400 * disabled.
1401 */
1402 if (port->rs485.flags &
1403 SER_RS485_RTS_AFTER_SEND)
1404 imx_port_rts_inactive(sport, &ucr2);
1405 else
1406 imx_port_rts_active(sport, &ucr2);
1407 } else {
1408 imx_port_rts_auto(sport, &ucr2);
1409 }
1410 } else {
1411 termios->c_cflag &= ~CRTSCTS;
1412 }
1413 } else if (port->rs485.flags & SER_RS485_ENABLED) {
1414 /* disable transmitter */
1415 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1416 imx_port_rts_inactive(sport, &ucr2);
1417 else
1418 imx_port_rts_active(sport, &ucr2);
1419 }
1420
1421
1422 if (termios->c_cflag & CSTOPB)
1423 ucr2 |= UCR2_STPB;
1424 if (termios->c_cflag & PARENB) {
1425 ucr2 |= UCR2_PREN;
1426 if (termios->c_cflag & PARODD)
1427 ucr2 |= UCR2_PROE;
1428 }
1429
1430 del_timer_sync(&sport->timer);
1431
1432 /*
1433 * Ask the core to calculate the divisor for us.
1434 */
1435 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1436 quot = uart_get_divisor(port, baud);
1437
1438 spin_lock_irqsave(&sport->port.lock, flags);
1439
1440 sport->port.read_status_mask = 0;
1441 if (termios->c_iflag & INPCK)
1442 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1443 if (termios->c_iflag & (BRKINT | PARMRK))
1444 sport->port.read_status_mask |= URXD_BRK;
1445
1446 /*
1447 * Characters to ignore
1448 */
1449 sport->port.ignore_status_mask = 0;
1450 if (termios->c_iflag & IGNPAR)
1451 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1452 if (termios->c_iflag & IGNBRK) {
1453 sport->port.ignore_status_mask |= URXD_BRK;
1454 /*
1455 * If we're ignoring parity and break indicators,
1456 * ignore overruns too (for real raw support).
1457 */
1458 if (termios->c_iflag & IGNPAR)
1459 sport->port.ignore_status_mask |= URXD_OVRRUN;
1460 }
1461
1462 if ((termios->c_cflag & CREAD) == 0)
1463 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1464
1465 /*
1466 * Update the per-port timeout.
1467 */
1468 uart_update_timeout(port, termios->c_cflag, baud);
1469
1470 /*
1471 * disable interrupts and drain transmitter
1472 */
1473 old_ucr1 = readl(sport->port.membase + UCR1);
1474 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1475 sport->port.membase + UCR1);
1476
1477 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1478 barrier();
1479
1480 /* then, disable everything */
1481 old_ucr2 = readl(sport->port.membase + UCR2);
1482 writel(old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN),
1483 sport->port.membase + UCR2);
1484 old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN);
1485
1486 /* custom-baudrate handling */
1487 div = sport->port.uartclk / (baud * 16);
1488 if (baud == 38400 && quot != div)
1489 baud = sport->port.uartclk / (quot * 16);
1490
1491 div = sport->port.uartclk / (baud * 16);
1492 if (div > 7)
1493 div = 7;
1494 if (!div)
1495 div = 1;
1496
1497 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1498 1 << 16, 1 << 16, &num, &denom);
1499
1500 tdiv64 = sport->port.uartclk;
1501 tdiv64 *= num;
1502 do_div(tdiv64, denom * 16 * div);
1503 tty_termios_encode_baud_rate(termios,
1504 (speed_t)tdiv64, (speed_t)tdiv64);
1505
1506 num -= 1;
1507 denom -= 1;
1508
1509 ufcr = readl(sport->port.membase + UFCR);
1510 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1511 if (sport->dte_mode)
1512 ufcr |= UFCR_DCEDTE;
1513 writel(ufcr, sport->port.membase + UFCR);
1514
1515 writel(num, sport->port.membase + UBIR);
1516 writel(denom, sport->port.membase + UBMR);
1517
1518 if (!is_imx1_uart(sport))
1519 writel(sport->port.uartclk / div / 1000,
1520 sport->port.membase + IMX21_ONEMS);
1521
1522 writel(old_ucr1, sport->port.membase + UCR1);
1523
1524 /* set the parity, stop bits and data size */
1525 writel(ucr2 | old_ucr2, sport->port.membase + UCR2);
1526
1527 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1528 imx_enable_ms(&sport->port);
1529
1530 spin_unlock_irqrestore(&sport->port.lock, flags);
1531 }
1532
1533 static const char *imx_type(struct uart_port *port)
1534 {
1535 struct imx_port *sport = (struct imx_port *)port;
1536
1537 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1538 }
1539
1540 /*
1541 * Configure/autoconfigure the port.
1542 */
1543 static void imx_config_port(struct uart_port *port, int flags)
1544 {
1545 struct imx_port *sport = (struct imx_port *)port;
1546
1547 if (flags & UART_CONFIG_TYPE)
1548 sport->port.type = PORT_IMX;
1549 }
1550
1551 /*
1552 * Verify the new serial_struct (for TIOCSSERIAL).
1553 * The only change we allow are to the flags and type, and
1554 * even then only between PORT_IMX and PORT_UNKNOWN
1555 */
1556 static int
1557 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1558 {
1559 struct imx_port *sport = (struct imx_port *)port;
1560 int ret = 0;
1561
1562 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1563 ret = -EINVAL;
1564 if (sport->port.irq != ser->irq)
1565 ret = -EINVAL;
1566 if (ser->io_type != UPIO_MEM)
1567 ret = -EINVAL;
1568 if (sport->port.uartclk / 16 != ser->baud_base)
1569 ret = -EINVAL;
1570 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1571 ret = -EINVAL;
1572 if (sport->port.iobase != ser->port)
1573 ret = -EINVAL;
1574 if (ser->hub6 != 0)
1575 ret = -EINVAL;
1576 return ret;
1577 }
1578
1579 #if defined(CONFIG_CONSOLE_POLL)
1580
1581 static int imx_poll_init(struct uart_port *port)
1582 {
1583 struct imx_port *sport = (struct imx_port *)port;
1584 unsigned long flags;
1585 unsigned long temp;
1586 int retval;
1587
1588 retval = clk_prepare_enable(sport->clk_ipg);
1589 if (retval)
1590 return retval;
1591 retval = clk_prepare_enable(sport->clk_per);
1592 if (retval)
1593 clk_disable_unprepare(sport->clk_ipg);
1594
1595 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1596
1597 spin_lock_irqsave(&sport->port.lock, flags);
1598
1599 temp = readl(sport->port.membase + UCR1);
1600 if (is_imx1_uart(sport))
1601 temp |= IMX1_UCR1_UARTCLKEN;
1602 temp |= UCR1_UARTEN | UCR1_RRDYEN;
1603 temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1604 writel(temp, sport->port.membase + UCR1);
1605
1606 temp = readl(sport->port.membase + UCR2);
1607 temp |= UCR2_RXEN;
1608 writel(temp, sport->port.membase + UCR2);
1609
1610 spin_unlock_irqrestore(&sport->port.lock, flags);
1611
1612 return 0;
1613 }
1614
1615 static int imx_poll_get_char(struct uart_port *port)
1616 {
1617 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
1618 return NO_POLL_CHAR;
1619
1620 return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
1621 }
1622
1623 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1624 {
1625 unsigned int status;
1626
1627 /* drain */
1628 do {
1629 status = readl_relaxed(port->membase + USR1);
1630 } while (~status & USR1_TRDY);
1631
1632 /* write */
1633 writel_relaxed(c, port->membase + URTX0);
1634
1635 /* flush */
1636 do {
1637 status = readl_relaxed(port->membase + USR2);
1638 } while (~status & USR2_TXDC);
1639 }
1640 #endif
1641
1642 static int imx_rs485_config(struct uart_port *port,
1643 struct serial_rs485 *rs485conf)
1644 {
1645 struct imx_port *sport = (struct imx_port *)port;
1646 unsigned long temp;
1647
1648 /* unimplemented */
1649 rs485conf->delay_rts_before_send = 0;
1650 rs485conf->delay_rts_after_send = 0;
1651
1652 /* RTS is required to control the transmitter */
1653 if (!sport->have_rtscts)
1654 rs485conf->flags &= ~SER_RS485_ENABLED;
1655
1656 if (rs485conf->flags & SER_RS485_ENABLED) {
1657 /* disable transmitter */
1658 temp = readl(sport->port.membase + UCR2);
1659 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1660 imx_port_rts_inactive(sport, &temp);
1661 else
1662 imx_port_rts_active(sport, &temp);
1663 writel(temp, sport->port.membase + UCR2);
1664 }
1665
1666 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1667 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1668 rs485conf->flags & SER_RS485_RX_DURING_TX) {
1669 temp = readl(sport->port.membase + UCR2);
1670 temp |= UCR2_RXEN;
1671 writel(temp, sport->port.membase + UCR2);
1672 }
1673
1674 port->rs485 = *rs485conf;
1675
1676 return 0;
1677 }
1678
1679 static struct uart_ops imx_pops = {
1680 .tx_empty = imx_tx_empty,
1681 .set_mctrl = imx_set_mctrl,
1682 .get_mctrl = imx_get_mctrl,
1683 .stop_tx = imx_stop_tx,
1684 .start_tx = imx_start_tx,
1685 .stop_rx = imx_stop_rx,
1686 .enable_ms = imx_enable_ms,
1687 .break_ctl = imx_break_ctl,
1688 .startup = imx_startup,
1689 .shutdown = imx_shutdown,
1690 .flush_buffer = imx_flush_buffer,
1691 .set_termios = imx_set_termios,
1692 .type = imx_type,
1693 .config_port = imx_config_port,
1694 .verify_port = imx_verify_port,
1695 #if defined(CONFIG_CONSOLE_POLL)
1696 .poll_init = imx_poll_init,
1697 .poll_get_char = imx_poll_get_char,
1698 .poll_put_char = imx_poll_put_char,
1699 #endif
1700 };
1701
1702 static struct imx_port *imx_ports[UART_NR];
1703
1704 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1705 static void imx_console_putchar(struct uart_port *port, int ch)
1706 {
1707 struct imx_port *sport = (struct imx_port *)port;
1708
1709 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1710 barrier();
1711
1712 writel(ch, sport->port.membase + URTX0);
1713 }
1714
1715 /*
1716 * Interrupts are disabled on entering
1717 */
1718 static void
1719 imx_console_write(struct console *co, const char *s, unsigned int count)
1720 {
1721 struct imx_port *sport = imx_ports[co->index];
1722 struct imx_port_ucrs old_ucr;
1723 unsigned int ucr1;
1724 unsigned long flags = 0;
1725 int locked = 1;
1726 int retval;
1727
1728 retval = clk_enable(sport->clk_per);
1729 if (retval)
1730 return;
1731 retval = clk_enable(sport->clk_ipg);
1732 if (retval) {
1733 clk_disable(sport->clk_per);
1734 return;
1735 }
1736
1737 if (sport->port.sysrq)
1738 locked = 0;
1739 else if (oops_in_progress)
1740 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1741 else
1742 spin_lock_irqsave(&sport->port.lock, flags);
1743
1744 /*
1745 * First, save UCR1/2/3 and then disable interrupts
1746 */
1747 imx_port_ucrs_save(&sport->port, &old_ucr);
1748 ucr1 = old_ucr.ucr1;
1749
1750 if (is_imx1_uart(sport))
1751 ucr1 |= IMX1_UCR1_UARTCLKEN;
1752 ucr1 |= UCR1_UARTEN;
1753 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1754
1755 writel(ucr1, sport->port.membase + UCR1);
1756
1757 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1758
1759 uart_console_write(&sport->port, s, count, imx_console_putchar);
1760
1761 /*
1762 * Finally, wait for transmitter to become empty
1763 * and restore UCR1/2/3
1764 */
1765 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1766
1767 imx_port_ucrs_restore(&sport->port, &old_ucr);
1768
1769 if (locked)
1770 spin_unlock_irqrestore(&sport->port.lock, flags);
1771
1772 clk_disable(sport->clk_ipg);
1773 clk_disable(sport->clk_per);
1774 }
1775
1776 /*
1777 * If the port was already initialised (eg, by a boot loader),
1778 * try to determine the current setup.
1779 */
1780 static void __init
1781 imx_console_get_options(struct imx_port *sport, int *baud,
1782 int *parity, int *bits)
1783 {
1784
1785 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1786 /* ok, the port was enabled */
1787 unsigned int ucr2, ubir, ubmr, uartclk;
1788 unsigned int baud_raw;
1789 unsigned int ucfr_rfdiv;
1790
1791 ucr2 = readl(sport->port.membase + UCR2);
1792
1793 *parity = 'n';
1794 if (ucr2 & UCR2_PREN) {
1795 if (ucr2 & UCR2_PROE)
1796 *parity = 'o';
1797 else
1798 *parity = 'e';
1799 }
1800
1801 if (ucr2 & UCR2_WS)
1802 *bits = 8;
1803 else
1804 *bits = 7;
1805
1806 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1807 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1808
1809 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1810 if (ucfr_rfdiv == 6)
1811 ucfr_rfdiv = 7;
1812 else
1813 ucfr_rfdiv = 6 - ucfr_rfdiv;
1814
1815 uartclk = clk_get_rate(sport->clk_per);
1816 uartclk /= ucfr_rfdiv;
1817
1818 { /*
1819 * The next code provides exact computation of
1820 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1821 * without need of float support or long long division,
1822 * which would be required to prevent 32bit arithmetic overflow
1823 */
1824 unsigned int mul = ubir + 1;
1825 unsigned int div = 16 * (ubmr + 1);
1826 unsigned int rem = uartclk % div;
1827
1828 baud_raw = (uartclk / div) * mul;
1829 baud_raw += (rem * mul + div / 2) / div;
1830 *baud = (baud_raw + 50) / 100 * 100;
1831 }
1832
1833 if (*baud != baud_raw)
1834 pr_info("Console IMX rounded baud rate from %d to %d\n",
1835 baud_raw, *baud);
1836 }
1837 }
1838
1839 static int __init
1840 imx_console_setup(struct console *co, char *options)
1841 {
1842 struct imx_port *sport;
1843 int baud = 9600;
1844 int bits = 8;
1845 int parity = 'n';
1846 int flow = 'n';
1847 int retval;
1848
1849 /*
1850 * Check whether an invalid uart number has been specified, and
1851 * if so, search for the first available port that does have
1852 * console support.
1853 */
1854 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1855 co->index = 0;
1856 sport = imx_ports[co->index];
1857 if (sport == NULL)
1858 return -ENODEV;
1859
1860 /* For setting the registers, we only need to enable the ipg clock. */
1861 retval = clk_prepare_enable(sport->clk_ipg);
1862 if (retval)
1863 goto error_console;
1864
1865 if (options)
1866 uart_parse_options(options, &baud, &parity, &bits, &flow);
1867 else
1868 imx_console_get_options(sport, &baud, &parity, &bits);
1869
1870 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1871
1872 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1873
1874 clk_disable(sport->clk_ipg);
1875 if (retval) {
1876 clk_unprepare(sport->clk_ipg);
1877 goto error_console;
1878 }
1879
1880 retval = clk_prepare(sport->clk_per);
1881 if (retval)
1882 clk_disable_unprepare(sport->clk_ipg);
1883
1884 error_console:
1885 return retval;
1886 }
1887
1888 static struct uart_driver imx_reg;
1889 static struct console imx_console = {
1890 .name = DEV_NAME,
1891 .write = imx_console_write,
1892 .device = uart_console_device,
1893 .setup = imx_console_setup,
1894 .flags = CON_PRINTBUFFER,
1895 .index = -1,
1896 .data = &imx_reg,
1897 };
1898
1899 #define IMX_CONSOLE &imx_console
1900
1901 #ifdef CONFIG_OF
1902 static void imx_console_early_putchar(struct uart_port *port, int ch)
1903 {
1904 while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL)
1905 cpu_relax();
1906
1907 writel_relaxed(ch, port->membase + URTX0);
1908 }
1909
1910 static void imx_console_early_write(struct console *con, const char *s,
1911 unsigned count)
1912 {
1913 struct earlycon_device *dev = con->data;
1914
1915 uart_console_write(&dev->port, s, count, imx_console_early_putchar);
1916 }
1917
1918 static int __init
1919 imx_console_early_setup(struct earlycon_device *dev, const char *opt)
1920 {
1921 if (!dev->port.membase)
1922 return -ENODEV;
1923
1924 dev->con->write = imx_console_early_write;
1925
1926 return 0;
1927 }
1928 OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
1929 OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
1930 #endif
1931
1932 #else
1933 #define IMX_CONSOLE NULL
1934 #endif
1935
1936 static struct uart_driver imx_reg = {
1937 .owner = THIS_MODULE,
1938 .driver_name = DRIVER_NAME,
1939 .dev_name = DEV_NAME,
1940 .major = SERIAL_IMX_MAJOR,
1941 .minor = MINOR_START,
1942 .nr = ARRAY_SIZE(imx_ports),
1943 .cons = IMX_CONSOLE,
1944 };
1945
1946 #ifdef CONFIG_OF
1947 /*
1948 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1949 * could successfully get all information from dt or a negative errno.
1950 */
1951 static int serial_imx_probe_dt(struct imx_port *sport,
1952 struct platform_device *pdev)
1953 {
1954 struct device_node *np = pdev->dev.of_node;
1955 int ret;
1956
1957 sport->devdata = of_device_get_match_data(&pdev->dev);
1958 if (!sport->devdata)
1959 /* no device tree device */
1960 return 1;
1961
1962 ret = of_alias_get_id(np, "serial");
1963 if (ret < 0) {
1964 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1965 return ret;
1966 }
1967 sport->port.line = ret;
1968
1969 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1970 sport->have_rtscts = 1;
1971
1972 if (of_get_property(np, "fsl,dte-mode", NULL))
1973 sport->dte_mode = 1;
1974
1975 return 0;
1976 }
1977 #else
1978 static inline int serial_imx_probe_dt(struct imx_port *sport,
1979 struct platform_device *pdev)
1980 {
1981 return 1;
1982 }
1983 #endif
1984
1985 static void serial_imx_probe_pdata(struct imx_port *sport,
1986 struct platform_device *pdev)
1987 {
1988 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
1989
1990 sport->port.line = pdev->id;
1991 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1992
1993 if (!pdata)
1994 return;
1995
1996 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1997 sport->have_rtscts = 1;
1998 }
1999
2000 static int serial_imx_probe(struct platform_device *pdev)
2001 {
2002 struct imx_port *sport;
2003 void __iomem *base;
2004 int ret = 0, reg;
2005 struct resource *res;
2006 int txirq, rxirq, rtsirq;
2007
2008 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2009 if (!sport)
2010 return -ENOMEM;
2011
2012 ret = serial_imx_probe_dt(sport, pdev);
2013 if (ret > 0)
2014 serial_imx_probe_pdata(sport, pdev);
2015 else if (ret < 0)
2016 return ret;
2017
2018 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2019 base = devm_ioremap_resource(&pdev->dev, res);
2020 if (IS_ERR(base))
2021 return PTR_ERR(base);
2022
2023 rxirq = platform_get_irq(pdev, 0);
2024 txirq = platform_get_irq(pdev, 1);
2025 rtsirq = platform_get_irq(pdev, 2);
2026
2027 sport->port.dev = &pdev->dev;
2028 sport->port.mapbase = res->start;
2029 sport->port.membase = base;
2030 sport->port.type = PORT_IMX,
2031 sport->port.iotype = UPIO_MEM;
2032 sport->port.irq = rxirq;
2033 sport->port.fifosize = 32;
2034 sport->port.ops = &imx_pops;
2035 sport->port.rs485_config = imx_rs485_config;
2036 sport->port.rs485.flags =
2037 SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX;
2038 sport->port.flags = UPF_BOOT_AUTOCONF;
2039 init_timer(&sport->timer);
2040 sport->timer.function = imx_timeout;
2041 sport->timer.data = (unsigned long)sport;
2042
2043 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2044 if (IS_ERR(sport->gpios))
2045 return PTR_ERR(sport->gpios);
2046
2047 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2048 if (IS_ERR(sport->clk_ipg)) {
2049 ret = PTR_ERR(sport->clk_ipg);
2050 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2051 return ret;
2052 }
2053
2054 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2055 if (IS_ERR(sport->clk_per)) {
2056 ret = PTR_ERR(sport->clk_per);
2057 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2058 return ret;
2059 }
2060
2061 sport->port.uartclk = clk_get_rate(sport->clk_per);
2062
2063 /* For register access, we only need to enable the ipg clock. */
2064 ret = clk_prepare_enable(sport->clk_ipg);
2065 if (ret)
2066 return ret;
2067
2068 /* Disable interrupts before requesting them */
2069 reg = readl_relaxed(sport->port.membase + UCR1);
2070 reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
2071 UCR1_TXMPTYEN | UCR1_RTSDEN);
2072 writel_relaxed(reg, sport->port.membase + UCR1);
2073
2074 clk_disable_unprepare(sport->clk_ipg);
2075
2076 /*
2077 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2078 * chips only have one interrupt.
2079 */
2080 if (txirq > 0) {
2081 ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0,
2082 dev_name(&pdev->dev), sport);
2083 if (ret)
2084 return ret;
2085
2086 ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0,
2087 dev_name(&pdev->dev), sport);
2088 if (ret)
2089 return ret;
2090 } else {
2091 ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0,
2092 dev_name(&pdev->dev), sport);
2093 if (ret)
2094 return ret;
2095 }
2096
2097 imx_ports[sport->port.line] = sport;
2098
2099 platform_set_drvdata(pdev, sport);
2100
2101 return uart_add_one_port(&imx_reg, &sport->port);
2102 }
2103
2104 static int serial_imx_remove(struct platform_device *pdev)
2105 {
2106 struct imx_port *sport = platform_get_drvdata(pdev);
2107
2108 return uart_remove_one_port(&imx_reg, &sport->port);
2109 }
2110
2111 static void serial_imx_restore_context(struct imx_port *sport)
2112 {
2113 if (!sport->context_saved)
2114 return;
2115
2116 writel(sport->saved_reg[4], sport->port.membase + UFCR);
2117 writel(sport->saved_reg[5], sport->port.membase + UESC);
2118 writel(sport->saved_reg[6], sport->port.membase + UTIM);
2119 writel(sport->saved_reg[7], sport->port.membase + UBIR);
2120 writel(sport->saved_reg[8], sport->port.membase + UBMR);
2121 writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS);
2122 writel(sport->saved_reg[0], sport->port.membase + UCR1);
2123 writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2);
2124 writel(sport->saved_reg[2], sport->port.membase + UCR3);
2125 writel(sport->saved_reg[3], sport->port.membase + UCR4);
2126 sport->context_saved = false;
2127 }
2128
2129 static void serial_imx_save_context(struct imx_port *sport)
2130 {
2131 /* Save necessary regs */
2132 sport->saved_reg[0] = readl(sport->port.membase + UCR1);
2133 sport->saved_reg[1] = readl(sport->port.membase + UCR2);
2134 sport->saved_reg[2] = readl(sport->port.membase + UCR3);
2135 sport->saved_reg[3] = readl(sport->port.membase + UCR4);
2136 sport->saved_reg[4] = readl(sport->port.membase + UFCR);
2137 sport->saved_reg[5] = readl(sport->port.membase + UESC);
2138 sport->saved_reg[6] = readl(sport->port.membase + UTIM);
2139 sport->saved_reg[7] = readl(sport->port.membase + UBIR);
2140 sport->saved_reg[8] = readl(sport->port.membase + UBMR);
2141 sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS);
2142 sport->context_saved = true;
2143 }
2144
2145 static void serial_imx_enable_wakeup(struct imx_port *sport, bool on)
2146 {
2147 unsigned int val;
2148
2149 val = readl(sport->port.membase + UCR3);
2150 if (on)
2151 val |= UCR3_AWAKEN;
2152 else
2153 val &= ~UCR3_AWAKEN;
2154 writel(val, sport->port.membase + UCR3);
2155
2156 val = readl(sport->port.membase + UCR1);
2157 if (on)
2158 val |= UCR1_RTSDEN;
2159 else
2160 val &= ~UCR1_RTSDEN;
2161 writel(val, sport->port.membase + UCR1);
2162 }
2163
2164 static int imx_serial_port_suspend_noirq(struct device *dev)
2165 {
2166 struct platform_device *pdev = to_platform_device(dev);
2167 struct imx_port *sport = platform_get_drvdata(pdev);
2168 int ret;
2169
2170 ret = clk_enable(sport->clk_ipg);
2171 if (ret)
2172 return ret;
2173
2174 serial_imx_save_context(sport);
2175
2176 clk_disable(sport->clk_ipg);
2177
2178 return 0;
2179 }
2180
2181 static int imx_serial_port_resume_noirq(struct device *dev)
2182 {
2183 struct platform_device *pdev = to_platform_device(dev);
2184 struct imx_port *sport = platform_get_drvdata(pdev);
2185 int ret;
2186
2187 ret = clk_enable(sport->clk_ipg);
2188 if (ret)
2189 return ret;
2190
2191 serial_imx_restore_context(sport);
2192
2193 clk_disable(sport->clk_ipg);
2194
2195 return 0;
2196 }
2197
2198 static int imx_serial_port_suspend(struct device *dev)
2199 {
2200 struct platform_device *pdev = to_platform_device(dev);
2201 struct imx_port *sport = platform_get_drvdata(pdev);
2202
2203 /* enable wakeup from i.MX UART */
2204 serial_imx_enable_wakeup(sport, true);
2205
2206 uart_suspend_port(&imx_reg, &sport->port);
2207
2208 /* Needed to enable clock in suspend_noirq */
2209 return clk_prepare(sport->clk_ipg);
2210 }
2211
2212 static int imx_serial_port_resume(struct device *dev)
2213 {
2214 struct platform_device *pdev = to_platform_device(dev);
2215 struct imx_port *sport = platform_get_drvdata(pdev);
2216
2217 /* disable wakeup from i.MX UART */
2218 serial_imx_enable_wakeup(sport, false);
2219
2220 uart_resume_port(&imx_reg, &sport->port);
2221
2222 clk_unprepare(sport->clk_ipg);
2223
2224 return 0;
2225 }
2226
2227 static const struct dev_pm_ops imx_serial_port_pm_ops = {
2228 .suspend_noirq = imx_serial_port_suspend_noirq,
2229 .resume_noirq = imx_serial_port_resume_noirq,
2230 .suspend = imx_serial_port_suspend,
2231 .resume = imx_serial_port_resume,
2232 };
2233
2234 static struct platform_driver serial_imx_driver = {
2235 .probe = serial_imx_probe,
2236 .remove = serial_imx_remove,
2237
2238 .id_table = imx_uart_devtype,
2239 .driver = {
2240 .name = "imx-uart",
2241 .of_match_table = imx_uart_dt_ids,
2242 .pm = &imx_serial_port_pm_ops,
2243 },
2244 };
2245
2246 static int __init imx_serial_init(void)
2247 {
2248 int ret = uart_register_driver(&imx_reg);
2249
2250 if (ret)
2251 return ret;
2252
2253 ret = platform_driver_register(&serial_imx_driver);
2254 if (ret != 0)
2255 uart_unregister_driver(&imx_reg);
2256
2257 return ret;
2258 }
2259
2260 static void __exit imx_serial_exit(void)
2261 {
2262 platform_driver_unregister(&serial_imx_driver);
2263 uart_unregister_driver(&imx_reg);
2264 }
2265
2266 module_init(imx_serial_init);
2267 module_exit(imx_serial_exit);
2268
2269 MODULE_AUTHOR("Sascha Hauer");
2270 MODULE_DESCRIPTION("IMX generic serial port driver");
2271 MODULE_LICENSE("GPL");
2272 MODULE_ALIAS("platform:imx-uart");
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