2 * Driver for Motorola/Freescale IMX serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24 #include <linux/module.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial.h>
34 #include <linux/clk.h>
35 #include <linux/delay.h>
36 #include <linux/rational.h>
37 #include <linux/slab.h>
39 #include <linux/of_device.h>
41 #include <linux/dma-mapping.h>
44 #include <linux/platform_data/serial-imx.h>
45 #include <linux/platform_data/dma-imx.h>
47 #include "serial_mctrl_gpio.h"
49 /* Register definitions */
50 #define URXD0 0x0 /* Receiver Register */
51 #define URTX0 0x40 /* Transmitter Register */
52 #define UCR1 0x80 /* Control Register 1 */
53 #define UCR2 0x84 /* Control Register 2 */
54 #define UCR3 0x88 /* Control Register 3 */
55 #define UCR4 0x8c /* Control Register 4 */
56 #define UFCR 0x90 /* FIFO Control Register */
57 #define USR1 0x94 /* Status Register 1 */
58 #define USR2 0x98 /* Status Register 2 */
59 #define UESC 0x9c /* Escape Character Register */
60 #define UTIM 0xa0 /* Escape Timer Register */
61 #define UBIR 0xa4 /* BRM Incremental Register */
62 #define UBMR 0xa8 /* BRM Modulator Register */
63 #define UBRC 0xac /* Baud Rate Count Register */
64 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
65 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
66 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
68 /* UART Control Register Bit Fields.*/
69 #define URXD_DUMMY_READ (1<<16)
70 #define URXD_CHARRDY (1<<15)
71 #define URXD_ERR (1<<14)
72 #define URXD_OVRRUN (1<<13)
73 #define URXD_FRMERR (1<<12)
74 #define URXD_BRK (1<<11)
75 #define URXD_PRERR (1<<10)
76 #define URXD_RX_DATA (0xFF<<0)
77 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
78 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
79 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
80 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
81 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
82 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
83 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
84 #define UCR1_IREN (1<<7) /* Infrared interface enable */
85 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
86 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
87 #define UCR1_SNDBRK (1<<4) /* Send break */
88 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
89 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
90 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
91 #define UCR1_DOZE (1<<1) /* Doze */
92 #define UCR1_UARTEN (1<<0) /* UART enabled */
93 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
94 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
95 #define UCR2_CTSC (1<<13) /* CTS pin control */
96 #define UCR2_CTS (1<<12) /* Clear to send */
97 #define UCR2_ESCEN (1<<11) /* Escape enable */
98 #define UCR2_PREN (1<<8) /* Parity enable */
99 #define UCR2_PROE (1<<7) /* Parity odd/even */
100 #define UCR2_STPB (1<<6) /* Stop */
101 #define UCR2_WS (1<<5) /* Word size */
102 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
103 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
104 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
105 #define UCR2_RXEN (1<<1) /* Receiver enabled */
106 #define UCR2_SRST (1<<0) /* SW reset */
107 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
108 #define UCR3_PARERREN (1<<12) /* Parity enable */
109 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
110 #define UCR3_DSR (1<<10) /* Data set ready */
111 #define UCR3_DCD (1<<9) /* Data carrier detect */
112 #define UCR3_RI (1<<8) /* Ring indicator */
113 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
114 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
115 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
116 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
117 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
118 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
119 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
120 #define UCR3_BPEN (1<<0) /* Preset registers enable */
121 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
122 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
123 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
124 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
125 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
126 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
127 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
128 #define UCR4_IRSC (1<<5) /* IR special case */
129 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
130 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
131 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
132 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
133 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
134 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
135 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
136 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
137 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
138 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
139 #define USR1_RTSS (1<<14) /* RTS pin status */
140 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
141 #define USR1_RTSD (1<<12) /* RTS delta */
142 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
143 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
144 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
145 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
146 #define USR1_DTRD (1<<7) /* DTR Delta */
147 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
148 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
149 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
150 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
151 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
152 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
153 #define USR2_IDLE (1<<12) /* Idle condition */
154 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
155 #define USR2_RIIN (1<<9) /* Ring Indicator Input */
156 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
157 #define USR2_WAKE (1<<7) /* Wake */
158 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
159 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
160 #define USR2_TXDC (1<<3) /* Transmitter complete */
161 #define USR2_BRCD (1<<2) /* Break condition */
162 #define USR2_ORE (1<<1) /* Overrun error */
163 #define USR2_RDR (1<<0) /* Recv data ready */
164 #define UTS_FRCPERR (1<<13) /* Force parity error */
165 #define UTS_LOOP (1<<12) /* Loop tx and rx */
166 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
167 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
168 #define UTS_TXFULL (1<<4) /* TxFIFO full */
169 #define UTS_RXFULL (1<<3) /* RxFIFO full */
170 #define UTS_SOFTRST (1<<0) /* Software reset */
172 /* We've been assigned a range on the "Low-density serial ports" major */
173 #define SERIAL_IMX_MAJOR 207
174 #define MINOR_START 16
175 #define DEV_NAME "ttymxc"
178 * This determines how often we check the modem status signals
179 * for any change. They generally aren't connected to an IRQ
180 * so we have to poll them. We also check immediately before
181 * filling the TX fifo incase CTS has been dropped.
183 #define MCTRL_TIMEOUT (250*HZ/1000)
185 #define DRIVER_NAME "IMX-uart"
189 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
197 /* device type dependent stuff */
198 struct imx_uart_data
{
200 enum imx_uart_type devtype
;
204 struct uart_port port
;
205 struct timer_list timer
;
206 unsigned int old_status
;
207 unsigned int have_rtscts
:1;
208 unsigned int have_rtsgpio
:1;
209 unsigned int dte_mode
:1;
210 unsigned int irda_inv_rx
:1;
211 unsigned int irda_inv_tx
:1;
212 unsigned short trcv_delay
; /* transceiver delay */
215 const struct imx_uart_data
*devdata
;
217 struct mctrl_gpios
*gpios
;
220 unsigned int dma_is_inited
:1;
221 unsigned int dma_is_enabled
:1;
222 unsigned int dma_is_rxing
:1;
223 unsigned int dma_is_txing
:1;
224 struct dma_chan
*dma_chan_rx
, *dma_chan_tx
;
225 struct scatterlist rx_sgl
, tx_sgl
[2];
227 struct circ_buf rx_ring
;
228 unsigned int rx_periods
;
229 dma_cookie_t rx_cookie
;
230 unsigned int tx_bytes
;
231 unsigned int dma_tx_nents
;
232 wait_queue_head_t dma_wait
;
233 unsigned int saved_reg
[10];
237 struct imx_port_ucrs
{
243 static struct imx_uart_data imx_uart_devdata
[] = {
246 .devtype
= IMX1_UART
,
249 .uts_reg
= IMX21_UTS
,
250 .devtype
= IMX21_UART
,
253 .uts_reg
= IMX21_UTS
,
254 .devtype
= IMX53_UART
,
257 .uts_reg
= IMX21_UTS
,
258 .devtype
= IMX6Q_UART
,
262 static const struct platform_device_id imx_uart_devtype
[] = {
265 .driver_data
= (kernel_ulong_t
) &imx_uart_devdata
[IMX1_UART
],
267 .name
= "imx21-uart",
268 .driver_data
= (kernel_ulong_t
) &imx_uart_devdata
[IMX21_UART
],
270 .name
= "imx53-uart",
271 .driver_data
= (kernel_ulong_t
) &imx_uart_devdata
[IMX53_UART
],
273 .name
= "imx6q-uart",
274 .driver_data
= (kernel_ulong_t
) &imx_uart_devdata
[IMX6Q_UART
],
279 MODULE_DEVICE_TABLE(platform
, imx_uart_devtype
);
281 static const struct of_device_id imx_uart_dt_ids
[] = {
282 { .compatible
= "fsl,imx6q-uart", .data
= &imx_uart_devdata
[IMX6Q_UART
], },
283 { .compatible
= "fsl,imx53-uart", .data
= &imx_uart_devdata
[IMX53_UART
], },
284 { .compatible
= "fsl,imx1-uart", .data
= &imx_uart_devdata
[IMX1_UART
], },
285 { .compatible
= "fsl,imx21-uart", .data
= &imx_uart_devdata
[IMX21_UART
], },
288 MODULE_DEVICE_TABLE(of
, imx_uart_dt_ids
);
290 static inline unsigned uts_reg(struct imx_port
*sport
)
292 return sport
->devdata
->uts_reg
;
295 static inline int is_imx1_uart(struct imx_port
*sport
)
297 return sport
->devdata
->devtype
== IMX1_UART
;
300 static inline int is_imx21_uart(struct imx_port
*sport
)
302 return sport
->devdata
->devtype
== IMX21_UART
;
305 static inline int is_imx53_uart(struct imx_port
*sport
)
307 return sport
->devdata
->devtype
== IMX53_UART
;
310 static inline int is_imx6q_uart(struct imx_port
*sport
)
312 return sport
->devdata
->devtype
== IMX6Q_UART
;
315 * Save and restore functions for UCR1, UCR2 and UCR3 registers
317 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
318 static void imx_port_ucrs_save(struct uart_port
*port
,
319 struct imx_port_ucrs
*ucr
)
321 /* save control registers */
322 ucr
->ucr1
= readl(port
->membase
+ UCR1
);
323 ucr
->ucr2
= readl(port
->membase
+ UCR2
);
324 ucr
->ucr3
= readl(port
->membase
+ UCR3
);
327 static void imx_port_ucrs_restore(struct uart_port
*port
,
328 struct imx_port_ucrs
*ucr
)
330 /* restore control registers */
331 writel(ucr
->ucr1
, port
->membase
+ UCR1
);
332 writel(ucr
->ucr2
, port
->membase
+ UCR2
);
333 writel(ucr
->ucr3
, port
->membase
+ UCR3
);
337 static void imx_port_rts_active(struct imx_port
*sport
, unsigned long *ucr2
)
339 *ucr2
&= ~(UCR2_CTSC
| UCR2_CTS
);
341 mctrl_gpio_set(sport
->gpios
, sport
->port
.mctrl
| TIOCM_RTS
);
344 static void imx_port_rts_inactive(struct imx_port
*sport
, unsigned long *ucr2
)
349 mctrl_gpio_set(sport
->gpios
, sport
->port
.mctrl
& ~TIOCM_RTS
);
352 static void imx_port_rts_auto(struct imx_port
*sport
, unsigned long *ucr2
)
358 * interrupts disabled on entry
360 static void imx_stop_tx(struct uart_port
*port
)
362 struct imx_port
*sport
= (struct imx_port
*)port
;
366 * We are maybe in the SMP context, so if the DMA TX thread is running
367 * on other cpu, we have to wait for it to finish.
369 if (sport
->dma_is_enabled
&& sport
->dma_is_txing
)
372 temp
= readl(port
->membase
+ UCR1
);
373 writel(temp
& ~UCR1_TXMPTYEN
, port
->membase
+ UCR1
);
375 /* in rs485 mode disable transmitter if shifter is empty */
376 if (port
->rs485
.flags
& SER_RS485_ENABLED
&&
377 readl(port
->membase
+ USR2
) & USR2_TXDC
) {
378 temp
= readl(port
->membase
+ UCR2
);
379 if (port
->rs485
.flags
& SER_RS485_RTS_AFTER_SEND
)
380 imx_port_rts_active(sport
, &temp
);
382 imx_port_rts_inactive(sport
, &temp
);
384 writel(temp
, port
->membase
+ UCR2
);
386 temp
= readl(port
->membase
+ UCR4
);
388 writel(temp
, port
->membase
+ UCR4
);
393 * interrupts disabled on entry
395 static void imx_stop_rx(struct uart_port
*port
)
397 struct imx_port
*sport
= (struct imx_port
*)port
;
400 if (sport
->dma_is_enabled
&& sport
->dma_is_rxing
) {
401 if (sport
->port
.suspended
) {
402 dmaengine_terminate_all(sport
->dma_chan_rx
);
403 sport
->dma_is_rxing
= 0;
409 temp
= readl(sport
->port
.membase
+ UCR2
);
410 writel(temp
& ~UCR2_RXEN
, sport
->port
.membase
+ UCR2
);
412 /* disable the `Receiver Ready Interrrupt` */
413 temp
= readl(sport
->port
.membase
+ UCR1
);
414 writel(temp
& ~UCR1_RRDYEN
, sport
->port
.membase
+ UCR1
);
418 * Set the modem control timer to fire immediately.
420 static void imx_enable_ms(struct uart_port
*port
)
422 struct imx_port
*sport
= (struct imx_port
*)port
;
424 mod_timer(&sport
->timer
, jiffies
);
426 mctrl_gpio_enable_ms(sport
->gpios
);
429 static void imx_dma_tx(struct imx_port
*sport
);
430 static inline void imx_transmit_buffer(struct imx_port
*sport
)
432 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
435 if (sport
->port
.x_char
) {
437 writel(sport
->port
.x_char
, sport
->port
.membase
+ URTX0
);
438 sport
->port
.icount
.tx
++;
439 sport
->port
.x_char
= 0;
443 if (uart_circ_empty(xmit
) || uart_tx_stopped(&sport
->port
)) {
444 imx_stop_tx(&sport
->port
);
448 if (sport
->dma_is_enabled
) {
450 * We've just sent a X-char Ensure the TX DMA is enabled
451 * and the TX IRQ is disabled.
453 temp
= readl(sport
->port
.membase
+ UCR1
);
454 temp
&= ~UCR1_TXMPTYEN
;
455 if (sport
->dma_is_txing
) {
457 writel(temp
, sport
->port
.membase
+ UCR1
);
459 writel(temp
, sport
->port
.membase
+ UCR1
);
464 while (!uart_circ_empty(xmit
) &&
465 !(readl(sport
->port
.membase
+ uts_reg(sport
)) & UTS_TXFULL
)) {
466 /* send xmit->buf[xmit->tail]
467 * out the port here */
468 writel(xmit
->buf
[xmit
->tail
], sport
->port
.membase
+ URTX0
);
469 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
470 sport
->port
.icount
.tx
++;
473 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
474 uart_write_wakeup(&sport
->port
);
476 if (uart_circ_empty(xmit
))
477 imx_stop_tx(&sport
->port
);
480 static void dma_tx_callback(void *data
)
482 struct imx_port
*sport
= data
;
483 struct scatterlist
*sgl
= &sport
->tx_sgl
[0];
484 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
488 spin_lock_irqsave(&sport
->port
.lock
, flags
);
490 dma_unmap_sg(sport
->port
.dev
, sgl
, sport
->dma_tx_nents
, DMA_TO_DEVICE
);
492 temp
= readl(sport
->port
.membase
+ UCR1
);
493 temp
&= ~UCR1_TDMAEN
;
494 writel(temp
, sport
->port
.membase
+ UCR1
);
496 /* update the stat */
497 xmit
->tail
= (xmit
->tail
+ sport
->tx_bytes
) & (UART_XMIT_SIZE
- 1);
498 sport
->port
.icount
.tx
+= sport
->tx_bytes
;
500 dev_dbg(sport
->port
.dev
, "we finish the TX DMA.\n");
502 sport
->dma_is_txing
= 0;
504 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
506 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
507 uart_write_wakeup(&sport
->port
);
509 if (waitqueue_active(&sport
->dma_wait
)) {
510 wake_up(&sport
->dma_wait
);
511 dev_dbg(sport
->port
.dev
, "exit in %s.\n", __func__
);
515 spin_lock_irqsave(&sport
->port
.lock
, flags
);
516 if (!uart_circ_empty(xmit
) && !uart_tx_stopped(&sport
->port
))
518 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
521 static void imx_dma_tx(struct imx_port
*sport
)
523 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
524 struct scatterlist
*sgl
= sport
->tx_sgl
;
525 struct dma_async_tx_descriptor
*desc
;
526 struct dma_chan
*chan
= sport
->dma_chan_tx
;
527 struct device
*dev
= sport
->port
.dev
;
531 if (sport
->dma_is_txing
)
534 sport
->tx_bytes
= uart_circ_chars_pending(xmit
);
536 if (xmit
->tail
< xmit
->head
) {
537 sport
->dma_tx_nents
= 1;
538 sg_init_one(sgl
, xmit
->buf
+ xmit
->tail
, sport
->tx_bytes
);
540 sport
->dma_tx_nents
= 2;
541 sg_init_table(sgl
, 2);
542 sg_set_buf(sgl
, xmit
->buf
+ xmit
->tail
,
543 UART_XMIT_SIZE
- xmit
->tail
);
544 sg_set_buf(sgl
+ 1, xmit
->buf
, xmit
->head
);
547 ret
= dma_map_sg(dev
, sgl
, sport
->dma_tx_nents
, DMA_TO_DEVICE
);
549 dev_err(dev
, "DMA mapping error for TX.\n");
552 desc
= dmaengine_prep_slave_sg(chan
, sgl
, sport
->dma_tx_nents
,
553 DMA_MEM_TO_DEV
, DMA_PREP_INTERRUPT
);
555 dma_unmap_sg(dev
, sgl
, sport
->dma_tx_nents
,
557 dev_err(dev
, "We cannot prepare for the TX slave dma!\n");
560 desc
->callback
= dma_tx_callback
;
561 desc
->callback_param
= sport
;
563 dev_dbg(dev
, "TX: prepare to send %lu bytes by DMA.\n",
564 uart_circ_chars_pending(xmit
));
566 temp
= readl(sport
->port
.membase
+ UCR1
);
568 writel(temp
, sport
->port
.membase
+ UCR1
);
571 sport
->dma_is_txing
= 1;
572 dmaengine_submit(desc
);
573 dma_async_issue_pending(chan
);
578 * interrupts disabled on entry
580 static void imx_start_tx(struct uart_port
*port
)
582 struct imx_port
*sport
= (struct imx_port
*)port
;
585 if (port
->rs485
.flags
& SER_RS485_ENABLED
) {
586 temp
= readl(port
->membase
+ UCR2
);
587 if (port
->rs485
.flags
& SER_RS485_RTS_ON_SEND
)
588 imx_port_rts_active(sport
, &temp
);
590 imx_port_rts_inactive(sport
, &temp
);
591 if (!(port
->rs485
.flags
& SER_RS485_RX_DURING_TX
))
593 writel(temp
, port
->membase
+ UCR2
);
595 /* enable transmitter and shifter empty irq */
596 temp
= readl(port
->membase
+ UCR4
);
598 writel(temp
, port
->membase
+ UCR4
);
601 if (!sport
->dma_is_enabled
) {
602 temp
= readl(sport
->port
.membase
+ UCR1
);
603 writel(temp
| UCR1_TXMPTYEN
, sport
->port
.membase
+ UCR1
);
606 if (sport
->dma_is_enabled
) {
607 if (sport
->port
.x_char
) {
608 /* We have X-char to send, so enable TX IRQ and
609 * disable TX DMA to let TX interrupt to send X-char */
610 temp
= readl(sport
->port
.membase
+ UCR1
);
611 temp
&= ~UCR1_TDMAEN
;
612 temp
|= UCR1_TXMPTYEN
;
613 writel(temp
, sport
->port
.membase
+ UCR1
);
617 if (!uart_circ_empty(&port
->state
->xmit
) &&
618 !uart_tx_stopped(port
))
624 static irqreturn_t
imx_rtsint(int irq
, void *dev_id
)
626 struct imx_port
*sport
= dev_id
;
630 spin_lock_irqsave(&sport
->port
.lock
, flags
);
632 writel(USR1_RTSD
, sport
->port
.membase
+ USR1
);
633 val
= readl(sport
->port
.membase
+ USR1
) & USR1_RTSS
;
634 uart_handle_cts_change(&sport
->port
, !!val
);
635 wake_up_interruptible(&sport
->port
.state
->port
.delta_msr_wait
);
637 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
641 static irqreturn_t
imx_txint(int irq
, void *dev_id
)
643 struct imx_port
*sport
= dev_id
;
646 spin_lock_irqsave(&sport
->port
.lock
, flags
);
647 imx_transmit_buffer(sport
);
648 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
652 static irqreturn_t
imx_rxint(int irq
, void *dev_id
)
654 struct imx_port
*sport
= dev_id
;
655 unsigned int rx
, flg
, ignored
= 0;
656 struct tty_port
*port
= &sport
->port
.state
->port
;
657 unsigned long flags
, temp
;
659 spin_lock_irqsave(&sport
->port
.lock
, flags
);
661 while (readl(sport
->port
.membase
+ USR2
) & USR2_RDR
) {
663 sport
->port
.icount
.rx
++;
665 rx
= readl(sport
->port
.membase
+ URXD0
);
667 temp
= readl(sport
->port
.membase
+ USR2
);
668 if (temp
& USR2_BRCD
) {
669 writel(USR2_BRCD
, sport
->port
.membase
+ USR2
);
670 if (uart_handle_break(&sport
->port
))
674 if (uart_handle_sysrq_char(&sport
->port
, (unsigned char)rx
))
677 if (unlikely(rx
& URXD_ERR
)) {
679 sport
->port
.icount
.brk
++;
680 else if (rx
& URXD_PRERR
)
681 sport
->port
.icount
.parity
++;
682 else if (rx
& URXD_FRMERR
)
683 sport
->port
.icount
.frame
++;
684 if (rx
& URXD_OVRRUN
)
685 sport
->port
.icount
.overrun
++;
687 if (rx
& sport
->port
.ignore_status_mask
) {
693 rx
&= (sport
->port
.read_status_mask
| 0xFF);
697 else if (rx
& URXD_PRERR
)
699 else if (rx
& URXD_FRMERR
)
701 if (rx
& URXD_OVRRUN
)
705 sport
->port
.sysrq
= 0;
709 if (sport
->port
.ignore_status_mask
& URXD_DUMMY_READ
)
712 if (tty_insert_flip_char(port
, rx
, flg
) == 0)
713 sport
->port
.icount
.buf_overrun
++;
717 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
718 tty_flip_buffer_push(port
);
722 static void imx_disable_rx_int(struct imx_port
*sport
)
726 sport
->dma_is_rxing
= 1;
728 /* disable the receiver ready and aging timer interrupts */
729 temp
= readl(sport
->port
.membase
+ UCR1
);
730 temp
&= ~(UCR1_RRDYEN
);
731 writel(temp
, sport
->port
.membase
+ UCR1
);
733 temp
= readl(sport
->port
.membase
+ UCR2
);
734 temp
&= ~(UCR2_ATEN
);
735 writel(temp
, sport
->port
.membase
+ UCR2
);
737 /* disable the rx errors interrupts */
738 temp
= readl(sport
->port
.membase
+ UCR4
);
740 writel(temp
, sport
->port
.membase
+ UCR4
);
743 static void clear_rx_errors(struct imx_port
*sport
);
744 static int start_rx_dma(struct imx_port
*sport
);
746 * If the RXFIFO is filled with some data, and then we
747 * arise a DMA operation to receive them.
749 static void imx_dma_rxint(struct imx_port
*sport
)
754 spin_lock_irqsave(&sport
->port
.lock
, flags
);
756 temp
= readl(sport
->port
.membase
+ USR2
);
757 if ((temp
& USR2_RDR
) && !sport
->dma_is_rxing
) {
759 imx_disable_rx_int(sport
);
761 /* tell the DMA to receive the data. */
765 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
769 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
771 static unsigned int imx_get_hwmctrl(struct imx_port
*sport
)
773 unsigned int tmp
= TIOCM_DSR
;
774 unsigned usr1
= readl(sport
->port
.membase
+ USR1
);
775 unsigned usr2
= readl(sport
->port
.membase
+ USR2
);
777 if (usr1
& USR1_RTSS
)
780 /* in DCE mode DCDIN is always 0 */
781 if (!(usr2
& USR2_DCDIN
))
785 if (!(readl(sport
->port
.membase
+ USR2
) & USR2_RIIN
))
792 * Handle any change of modem status signal since we were last called.
794 static void imx_mctrl_check(struct imx_port
*sport
)
796 unsigned int status
, changed
;
798 status
= imx_get_hwmctrl(sport
);
799 changed
= status
^ sport
->old_status
;
804 sport
->old_status
= status
;
806 if (changed
& TIOCM_RI
&& status
& TIOCM_RI
)
807 sport
->port
.icount
.rng
++;
808 if (changed
& TIOCM_DSR
)
809 sport
->port
.icount
.dsr
++;
810 if (changed
& TIOCM_CAR
)
811 uart_handle_dcd_change(&sport
->port
, status
& TIOCM_CAR
);
812 if (changed
& TIOCM_CTS
)
813 uart_handle_cts_change(&sport
->port
, status
& TIOCM_CTS
);
815 wake_up_interruptible(&sport
->port
.state
->port
.delta_msr_wait
);
818 static irqreturn_t
imx_int(int irq
, void *dev_id
)
820 struct imx_port
*sport
= dev_id
;
823 irqreturn_t ret
= IRQ_NONE
;
825 sts
= readl(sport
->port
.membase
+ USR1
);
826 sts2
= readl(sport
->port
.membase
+ USR2
);
828 if (sts
& (USR1_RRDY
| USR1_AGTIM
)) {
829 if (sport
->dma_is_enabled
)
830 imx_dma_rxint(sport
);
832 imx_rxint(irq
, dev_id
);
836 if ((sts
& USR1_TRDY
&&
837 readl(sport
->port
.membase
+ UCR1
) & UCR1_TXMPTYEN
) ||
839 readl(sport
->port
.membase
+ UCR4
) & UCR4_TCEN
)) {
840 imx_txint(irq
, dev_id
);
844 if (sts
& USR1_DTRD
) {
848 writel(USR1_DTRD
, sport
->port
.membase
+ USR1
);
850 spin_lock_irqsave(&sport
->port
.lock
, flags
);
851 imx_mctrl_check(sport
);
852 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
857 if (sts
& USR1_RTSD
) {
858 imx_rtsint(irq
, dev_id
);
862 if (sts
& USR1_AWAKE
) {
863 writel(USR1_AWAKE
, sport
->port
.membase
+ USR1
);
867 if (sts2
& USR2_ORE
) {
868 sport
->port
.icount
.overrun
++;
869 writel(USR2_ORE
, sport
->port
.membase
+ USR2
);
877 * Return TIOCSER_TEMT when transmitter is not busy.
879 static unsigned int imx_tx_empty(struct uart_port
*port
)
881 struct imx_port
*sport
= (struct imx_port
*)port
;
884 ret
= (readl(sport
->port
.membase
+ USR2
) & USR2_TXDC
) ? TIOCSER_TEMT
: 0;
886 /* If the TX DMA is working, return 0. */
887 if (sport
->dma_is_enabled
&& sport
->dma_is_txing
)
893 static unsigned int imx_get_mctrl(struct uart_port
*port
)
895 struct imx_port
*sport
= (struct imx_port
*)port
;
896 unsigned int ret
= imx_get_hwmctrl(sport
);
898 mctrl_gpio_get(sport
->gpios
, &ret
);
903 static void imx_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
905 struct imx_port
*sport
= (struct imx_port
*)port
;
908 if (!(port
->rs485
.flags
& SER_RS485_ENABLED
)) {
909 temp
= readl(sport
->port
.membase
+ UCR2
);
910 temp
&= ~(UCR2_CTS
| UCR2_CTSC
);
911 if (mctrl
& TIOCM_RTS
)
912 temp
|= UCR2_CTS
| UCR2_CTSC
;
913 writel(temp
, sport
->port
.membase
+ UCR2
);
916 temp
= readl(sport
->port
.membase
+ UCR3
) & ~UCR3_DSR
;
917 if (!(mctrl
& TIOCM_DTR
))
919 writel(temp
, sport
->port
.membase
+ UCR3
);
921 temp
= readl(sport
->port
.membase
+ uts_reg(sport
)) & ~UTS_LOOP
;
922 if (mctrl
& TIOCM_LOOP
)
924 writel(temp
, sport
->port
.membase
+ uts_reg(sport
));
926 mctrl_gpio_set(sport
->gpios
, mctrl
);
930 * Interrupts always disabled.
932 static void imx_break_ctl(struct uart_port
*port
, int break_state
)
934 struct imx_port
*sport
= (struct imx_port
*)port
;
935 unsigned long flags
, temp
;
937 spin_lock_irqsave(&sport
->port
.lock
, flags
);
939 temp
= readl(sport
->port
.membase
+ UCR1
) & ~UCR1_SNDBRK
;
941 if (break_state
!= 0)
944 writel(temp
, sport
->port
.membase
+ UCR1
);
946 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
950 * This is our per-port timeout handler, for checking the
951 * modem status signals.
953 static void imx_timeout(unsigned long data
)
955 struct imx_port
*sport
= (struct imx_port
*)data
;
958 if (sport
->port
.state
) {
959 spin_lock_irqsave(&sport
->port
.lock
, flags
);
960 imx_mctrl_check(sport
);
961 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
963 mod_timer(&sport
->timer
, jiffies
+ MCTRL_TIMEOUT
);
967 #define RX_BUF_SIZE (PAGE_SIZE)
970 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
971 * [1] the RX DMA buffer is full.
972 * [2] the aging timer expires
974 * Condition [2] is triggered when a character has been sitting in the FIFO
975 * for at least 8 byte durations.
977 static void dma_rx_callback(void *data
)
979 struct imx_port
*sport
= data
;
980 struct dma_chan
*chan
= sport
->dma_chan_rx
;
981 struct scatterlist
*sgl
= &sport
->rx_sgl
;
982 struct tty_port
*port
= &sport
->port
.state
->port
;
983 struct dma_tx_state state
;
984 struct circ_buf
*rx_ring
= &sport
->rx_ring
;
985 enum dma_status status
;
986 unsigned int w_bytes
= 0;
987 unsigned int r_bytes
;
988 unsigned int bd_size
;
990 status
= dmaengine_tx_status(chan
, (dma_cookie_t
)0, &state
);
992 if (status
== DMA_ERROR
) {
993 dev_err(sport
->port
.dev
, "DMA transaction error.\n");
994 clear_rx_errors(sport
);
998 if (!(sport
->port
.ignore_status_mask
& URXD_DUMMY_READ
)) {
1001 * The state-residue variable represents the empty space
1002 * relative to the entire buffer. Taking this in consideration
1003 * the head is always calculated base on the buffer total
1004 * length - DMA transaction residue. The UART script from the
1005 * SDMA firmware will jump to the next buffer descriptor,
1006 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1007 * Taking this in consideration the tail is always at the
1008 * beginning of the buffer descriptor that contains the head.
1011 /* Calculate the head */
1012 rx_ring
->head
= sg_dma_len(sgl
) - state
.residue
;
1014 /* Calculate the tail. */
1015 bd_size
= sg_dma_len(sgl
) / sport
->rx_periods
;
1016 rx_ring
->tail
= ((rx_ring
->head
-1) / bd_size
) * bd_size
;
1018 if (rx_ring
->head
<= sg_dma_len(sgl
) &&
1019 rx_ring
->head
> rx_ring
->tail
) {
1021 /* Move data from tail to head */
1022 r_bytes
= rx_ring
->head
- rx_ring
->tail
;
1024 /* CPU claims ownership of RX DMA buffer */
1025 dma_sync_sg_for_cpu(sport
->port
.dev
, sgl
, 1,
1028 w_bytes
= tty_insert_flip_string(port
,
1029 sport
->rx_buf
+ rx_ring
->tail
, r_bytes
);
1031 /* UART retrieves ownership of RX DMA buffer */
1032 dma_sync_sg_for_device(sport
->port
.dev
, sgl
, 1,
1035 if (w_bytes
!= r_bytes
)
1036 sport
->port
.icount
.buf_overrun
++;
1038 sport
->port
.icount
.rx
+= w_bytes
;
1040 WARN_ON(rx_ring
->head
> sg_dma_len(sgl
));
1041 WARN_ON(rx_ring
->head
<= rx_ring
->tail
);
1046 tty_flip_buffer_push(port
);
1047 dev_dbg(sport
->port
.dev
, "We get %d bytes.\n", w_bytes
);
1051 /* RX DMA buffer periods */
1052 #define RX_DMA_PERIODS 4
1054 static int start_rx_dma(struct imx_port
*sport
)
1056 struct scatterlist
*sgl
= &sport
->rx_sgl
;
1057 struct dma_chan
*chan
= sport
->dma_chan_rx
;
1058 struct device
*dev
= sport
->port
.dev
;
1059 struct dma_async_tx_descriptor
*desc
;
1062 sport
->rx_ring
.head
= 0;
1063 sport
->rx_ring
.tail
= 0;
1064 sport
->rx_periods
= RX_DMA_PERIODS
;
1066 sg_init_one(sgl
, sport
->rx_buf
, RX_BUF_SIZE
);
1067 ret
= dma_map_sg(dev
, sgl
, 1, DMA_FROM_DEVICE
);
1069 dev_err(dev
, "DMA mapping error for RX.\n");
1073 desc
= dmaengine_prep_dma_cyclic(chan
, sg_dma_address(sgl
),
1074 sg_dma_len(sgl
), sg_dma_len(sgl
) / sport
->rx_periods
,
1075 DMA_DEV_TO_MEM
, DMA_PREP_INTERRUPT
);
1078 dma_unmap_sg(dev
, sgl
, 1, DMA_FROM_DEVICE
);
1079 dev_err(dev
, "We cannot prepare for the RX slave dma!\n");
1082 desc
->callback
= dma_rx_callback
;
1083 desc
->callback_param
= sport
;
1085 dev_dbg(dev
, "RX: prepare for the DMA.\n");
1086 sport
->rx_cookie
= dmaengine_submit(desc
);
1087 dma_async_issue_pending(chan
);
1091 static void clear_rx_errors(struct imx_port
*sport
)
1093 unsigned int status_usr1
, status_usr2
;
1095 status_usr1
= readl(sport
->port
.membase
+ USR1
);
1096 status_usr2
= readl(sport
->port
.membase
+ USR2
);
1098 if (status_usr2
& USR2_BRCD
) {
1099 sport
->port
.icount
.brk
++;
1100 writel(USR2_BRCD
, sport
->port
.membase
+ USR2
);
1101 } else if (status_usr1
& USR1_FRAMERR
) {
1102 sport
->port
.icount
.frame
++;
1103 writel(USR1_FRAMERR
, sport
->port
.membase
+ USR1
);
1104 } else if (status_usr1
& USR1_PARITYERR
) {
1105 sport
->port
.icount
.parity
++;
1106 writel(USR1_PARITYERR
, sport
->port
.membase
+ USR1
);
1109 if (status_usr2
& USR2_ORE
) {
1110 sport
->port
.icount
.overrun
++;
1111 writel(USR2_ORE
, sport
->port
.membase
+ USR2
);
1116 #define TXTL_DEFAULT 2 /* reset default */
1117 #define RXTL_DEFAULT 1 /* reset default */
1118 #define TXTL_DMA 8 /* DMA burst setting */
1119 #define RXTL_DMA 9 /* DMA burst setting */
1121 static void imx_setup_ufcr(struct imx_port
*sport
,
1122 unsigned char txwl
, unsigned char rxwl
)
1126 /* set receiver / transmitter trigger level */
1127 val
= readl(sport
->port
.membase
+ UFCR
) & (UFCR_RFDIV
| UFCR_DCEDTE
);
1128 val
|= txwl
<< UFCR_TXTL_SHF
| rxwl
;
1129 writel(val
, sport
->port
.membase
+ UFCR
);
1132 static void imx_uart_dma_exit(struct imx_port
*sport
)
1134 if (sport
->dma_chan_rx
) {
1135 dmaengine_terminate_sync(sport
->dma_chan_rx
);
1136 dma_release_channel(sport
->dma_chan_rx
);
1137 sport
->dma_chan_rx
= NULL
;
1138 sport
->rx_cookie
= -EINVAL
;
1139 kfree(sport
->rx_buf
);
1140 sport
->rx_buf
= NULL
;
1143 if (sport
->dma_chan_tx
) {
1144 dmaengine_terminate_sync(sport
->dma_chan_tx
);
1145 dma_release_channel(sport
->dma_chan_tx
);
1146 sport
->dma_chan_tx
= NULL
;
1149 sport
->dma_is_inited
= 0;
1152 static int imx_uart_dma_init(struct imx_port
*sport
)
1154 struct dma_slave_config slave_config
= {};
1155 struct device
*dev
= sport
->port
.dev
;
1158 /* Prepare for RX : */
1159 sport
->dma_chan_rx
= dma_request_slave_channel(dev
, "rx");
1160 if (!sport
->dma_chan_rx
) {
1161 dev_dbg(dev
, "cannot get the DMA channel.\n");
1166 slave_config
.direction
= DMA_DEV_TO_MEM
;
1167 slave_config
.src_addr
= sport
->port
.mapbase
+ URXD0
;
1168 slave_config
.src_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
1169 /* one byte less than the watermark level to enable the aging timer */
1170 slave_config
.src_maxburst
= RXTL_DMA
- 1;
1171 ret
= dmaengine_slave_config(sport
->dma_chan_rx
, &slave_config
);
1173 dev_err(dev
, "error in RX dma configuration.\n");
1177 sport
->rx_buf
= kzalloc(PAGE_SIZE
, GFP_KERNEL
);
1178 if (!sport
->rx_buf
) {
1182 sport
->rx_ring
.buf
= sport
->rx_buf
;
1184 /* Prepare for TX : */
1185 sport
->dma_chan_tx
= dma_request_slave_channel(dev
, "tx");
1186 if (!sport
->dma_chan_tx
) {
1187 dev_err(dev
, "cannot get the TX DMA channel!\n");
1192 slave_config
.direction
= DMA_MEM_TO_DEV
;
1193 slave_config
.dst_addr
= sport
->port
.mapbase
+ URTX0
;
1194 slave_config
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
1195 slave_config
.dst_maxburst
= TXTL_DMA
;
1196 ret
= dmaengine_slave_config(sport
->dma_chan_tx
, &slave_config
);
1198 dev_err(dev
, "error in TX dma configuration.");
1202 sport
->dma_is_inited
= 1;
1206 imx_uart_dma_exit(sport
);
1210 static void imx_enable_dma(struct imx_port
*sport
)
1214 init_waitqueue_head(&sport
->dma_wait
);
1217 temp
= readl(sport
->port
.membase
+ UCR1
);
1218 temp
|= UCR1_RDMAEN
| UCR1_TDMAEN
| UCR1_ATDMAEN
;
1219 writel(temp
, sport
->port
.membase
+ UCR1
);
1221 temp
= readl(sport
->port
.membase
+ UCR2
);
1223 writel(temp
, sport
->port
.membase
+ UCR2
);
1225 imx_setup_ufcr(sport
, TXTL_DMA
, RXTL_DMA
);
1227 sport
->dma_is_enabled
= 1;
1230 static void imx_disable_dma(struct imx_port
*sport
)
1235 temp
= readl(sport
->port
.membase
+ UCR1
);
1236 temp
&= ~(UCR1_RDMAEN
| UCR1_TDMAEN
| UCR1_ATDMAEN
);
1237 writel(temp
, sport
->port
.membase
+ UCR1
);
1240 temp
= readl(sport
->port
.membase
+ UCR2
);
1241 temp
&= ~(UCR2_CTSC
| UCR2_CTS
| UCR2_ATEN
);
1242 writel(temp
, sport
->port
.membase
+ UCR2
);
1244 imx_setup_ufcr(sport
, TXTL_DEFAULT
, RXTL_DEFAULT
);
1246 sport
->dma_is_enabled
= 0;
1249 /* half the RX buffer size */
1252 static int imx_startup(struct uart_port
*port
)
1254 struct imx_port
*sport
= (struct imx_port
*)port
;
1256 unsigned long flags
, temp
;
1258 retval
= clk_prepare_enable(sport
->clk_per
);
1261 retval
= clk_prepare_enable(sport
->clk_ipg
);
1263 clk_disable_unprepare(sport
->clk_per
);
1267 imx_setup_ufcr(sport
, TXTL_DEFAULT
, RXTL_DEFAULT
);
1269 /* disable the DREN bit (Data Ready interrupt enable) before
1272 temp
= readl(sport
->port
.membase
+ UCR4
);
1274 /* set the trigger level for CTS */
1275 temp
&= ~(UCR4_CTSTL_MASK
<< UCR4_CTSTL_SHF
);
1276 temp
|= CTSTL
<< UCR4_CTSTL_SHF
;
1278 writel(temp
& ~UCR4_DREN
, sport
->port
.membase
+ UCR4
);
1280 /* Can we enable the DMA support? */
1281 if (!uart_console(port
) && !sport
->dma_is_inited
)
1282 imx_uart_dma_init(sport
);
1284 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1285 /* Reset fifo's and state machines */
1288 temp
= readl(sport
->port
.membase
+ UCR2
);
1290 writel(temp
, sport
->port
.membase
+ UCR2
);
1292 while (!(readl(sport
->port
.membase
+ UCR2
) & UCR2_SRST
) && (--i
> 0))
1296 * Finally, clear and enable interrupts
1298 writel(USR1_RTSD
| USR1_DTRD
, sport
->port
.membase
+ USR1
);
1299 writel(USR2_ORE
, sport
->port
.membase
+ USR2
);
1301 if (sport
->dma_is_inited
&& !sport
->dma_is_enabled
)
1302 imx_enable_dma(sport
);
1304 temp
= readl(sport
->port
.membase
+ UCR1
);
1305 temp
|= UCR1_RRDYEN
| UCR1_RTSDEN
| UCR1_UARTEN
;
1307 writel(temp
, sport
->port
.membase
+ UCR1
);
1309 temp
= readl(sport
->port
.membase
+ UCR4
);
1311 writel(temp
, sport
->port
.membase
+ UCR4
);
1313 temp
= readl(sport
->port
.membase
+ UCR2
);
1314 temp
|= (UCR2_RXEN
| UCR2_TXEN
);
1315 if (!sport
->have_rtscts
)
1318 * make sure the edge sensitive RTS-irq is disabled,
1319 * we're using RTSD instead.
1321 if (!is_imx1_uart(sport
))
1322 temp
&= ~UCR2_RTSEN
;
1323 writel(temp
, sport
->port
.membase
+ UCR2
);
1325 if (!is_imx1_uart(sport
)) {
1326 temp
= readl(sport
->port
.membase
+ UCR3
);
1328 temp
|= UCR3_DTRDEN
| UCR3_RI
| UCR3_DCD
;
1330 if (sport
->dte_mode
)
1331 /* disable broken interrupts */
1332 temp
&= ~(UCR3_RI
| UCR3_DCD
);
1334 writel(temp
, sport
->port
.membase
+ UCR3
);
1338 * Enable modem status interrupts
1340 imx_enable_ms(&sport
->port
);
1343 * If the serial port is opened for reading start RX DMA immediately
1344 * instead of waiting for RX FIFO interrupts. In our iMX53 the average
1345 * delay for the first reception dropped from approximately 35000
1346 * microseconds to 1000 microseconds.
1348 if (sport
->dma_is_enabled
) {
1349 struct tty_struct
*tty
= sport
->port
.state
->port
.tty
;
1350 struct tty_file_private
*file_priv
;
1353 spin_lock(&tty
->files_lock
);
1355 if (!list_empty(&tty
->tty_files
))
1356 list_for_each_entry(file_priv
, &tty
->tty_files
, list
)
1357 if (!(file_priv
->file
->f_flags
& O_WRONLY
))
1360 spin_unlock(&tty
->files_lock
);
1363 imx_disable_rx_int(sport
);
1364 start_rx_dma(sport
);
1368 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1373 static void imx_shutdown(struct uart_port
*port
)
1375 struct imx_port
*sport
= (struct imx_port
*)port
;
1377 unsigned long flags
;
1379 if (sport
->dma_is_enabled
) {
1380 sport
->dma_is_rxing
= 0;
1381 sport
->dma_is_txing
= 0;
1382 dmaengine_terminate_sync(sport
->dma_chan_tx
);
1383 dmaengine_terminate_sync(sport
->dma_chan_rx
);
1385 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1388 imx_disable_dma(sport
);
1389 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1390 imx_uart_dma_exit(sport
);
1393 mctrl_gpio_disable_ms(sport
->gpios
);
1395 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1396 temp
= readl(sport
->port
.membase
+ UCR2
);
1397 temp
&= ~(UCR2_TXEN
);
1398 writel(temp
, sport
->port
.membase
+ UCR2
);
1399 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1404 del_timer_sync(&sport
->timer
);
1407 * Disable all interrupts, port and break condition.
1410 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1411 temp
= readl(sport
->port
.membase
+ UCR1
);
1412 temp
&= ~(UCR1_TXMPTYEN
| UCR1_RRDYEN
| UCR1_RTSDEN
| UCR1_UARTEN
);
1414 writel(temp
, sport
->port
.membase
+ UCR1
);
1415 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1417 clk_disable_unprepare(sport
->clk_per
);
1418 clk_disable_unprepare(sport
->clk_ipg
);
1421 static void imx_flush_buffer(struct uart_port
*port
)
1423 struct imx_port
*sport
= (struct imx_port
*)port
;
1424 struct scatterlist
*sgl
= &sport
->tx_sgl
[0];
1426 int i
= 100, ubir
, ubmr
, uts
;
1428 if (!sport
->dma_chan_tx
)
1431 sport
->tx_bytes
= 0;
1432 dmaengine_terminate_all(sport
->dma_chan_tx
);
1433 if (sport
->dma_is_txing
) {
1434 dma_unmap_sg(sport
->port
.dev
, sgl
, sport
->dma_tx_nents
,
1436 temp
= readl(sport
->port
.membase
+ UCR1
);
1437 temp
&= ~UCR1_TDMAEN
;
1438 writel(temp
, sport
->port
.membase
+ UCR1
);
1439 sport
->dma_is_txing
= false;
1443 * According to the Reference Manual description of the UART SRST bit:
1444 * "Reset the transmit and receive state machines,
1445 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1446 * and UTS[6-3]". As we don't need to restore the old values from
1447 * USR1, USR2, URXD, UTXD, only save/restore the other four registers
1449 ubir
= readl(sport
->port
.membase
+ UBIR
);
1450 ubmr
= readl(sport
->port
.membase
+ UBMR
);
1451 uts
= readl(sport
->port
.membase
+ IMX21_UTS
);
1453 temp
= readl(sport
->port
.membase
+ UCR2
);
1455 writel(temp
, sport
->port
.membase
+ UCR2
);
1457 while (!(readl(sport
->port
.membase
+ UCR2
) & UCR2_SRST
) && (--i
> 0))
1460 /* Restore the registers */
1461 writel(ubir
, sport
->port
.membase
+ UBIR
);
1462 writel(ubmr
, sport
->port
.membase
+ UBMR
);
1463 writel(uts
, sport
->port
.membase
+ IMX21_UTS
);
1467 imx_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
1468 struct ktermios
*old
)
1470 struct imx_port
*sport
= (struct imx_port
*)port
;
1471 unsigned long flags
;
1472 unsigned long ucr2
, old_ucr1
, old_ucr2
;
1473 unsigned int baud
, quot
;
1474 unsigned int old_csize
= old
? old
->c_cflag
& CSIZE
: CS8
;
1475 unsigned long div
, ufcr
;
1476 unsigned long num
, denom
;
1480 * We only support CS7 and CS8.
1482 while ((termios
->c_cflag
& CSIZE
) != CS7
&&
1483 (termios
->c_cflag
& CSIZE
) != CS8
) {
1484 termios
->c_cflag
&= ~CSIZE
;
1485 termios
->c_cflag
|= old_csize
;
1489 if ((termios
->c_cflag
& CSIZE
) == CS8
)
1490 ucr2
= UCR2_WS
| UCR2_SRST
| UCR2_IRTS
;
1492 ucr2
= UCR2_SRST
| UCR2_IRTS
;
1494 if (termios
->c_cflag
& CRTSCTS
) {
1495 if (sport
->have_rtscts
) {
1498 if (port
->rs485
.flags
& SER_RS485_ENABLED
) {
1500 * RTS is mandatory for rs485 operation, so keep
1501 * it under manual control and keep transmitter
1504 if (port
->rs485
.flags
&
1505 SER_RS485_RTS_AFTER_SEND
)
1506 imx_port_rts_active(sport
, &ucr2
);
1508 imx_port_rts_inactive(sport
, &ucr2
);
1510 imx_port_rts_auto(sport
, &ucr2
);
1513 termios
->c_cflag
&= ~CRTSCTS
;
1515 } else if (port
->rs485
.flags
& SER_RS485_ENABLED
) {
1516 /* disable transmitter */
1517 if (port
->rs485
.flags
& SER_RS485_RTS_AFTER_SEND
)
1518 imx_port_rts_active(sport
, &ucr2
);
1520 imx_port_rts_inactive(sport
, &ucr2
);
1524 if (termios
->c_cflag
& CSTOPB
)
1526 if (termios
->c_cflag
& PARENB
) {
1528 if (termios
->c_cflag
& PARODD
)
1532 del_timer_sync(&sport
->timer
);
1535 * Ask the core to calculate the divisor for us.
1537 baud
= uart_get_baud_rate(port
, termios
, old
, 50, port
->uartclk
/ 16);
1538 quot
= uart_get_divisor(port
, baud
);
1540 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1542 sport
->port
.read_status_mask
= 0;
1543 if (termios
->c_iflag
& INPCK
)
1544 sport
->port
.read_status_mask
|= (URXD_FRMERR
| URXD_PRERR
);
1545 if (termios
->c_iflag
& (BRKINT
| PARMRK
))
1546 sport
->port
.read_status_mask
|= URXD_BRK
;
1549 * Characters to ignore
1551 sport
->port
.ignore_status_mask
= 0;
1552 if (termios
->c_iflag
& IGNPAR
)
1553 sport
->port
.ignore_status_mask
|= URXD_PRERR
| URXD_FRMERR
;
1554 if (termios
->c_iflag
& IGNBRK
) {
1555 sport
->port
.ignore_status_mask
|= URXD_BRK
;
1557 * If we're ignoring parity and break indicators,
1558 * ignore overruns too (for real raw support).
1560 if (termios
->c_iflag
& IGNPAR
)
1561 sport
->port
.ignore_status_mask
|= URXD_OVRRUN
;
1564 if ((termios
->c_cflag
& CREAD
) == 0)
1565 sport
->port
.ignore_status_mask
|= URXD_DUMMY_READ
;
1568 * Update the per-port timeout.
1570 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1573 * disable interrupts and drain transmitter
1575 old_ucr1
= readl(sport
->port
.membase
+ UCR1
);
1576 writel(old_ucr1
& ~(UCR1_TXMPTYEN
| UCR1_RRDYEN
| UCR1_RTSDEN
),
1577 sport
->port
.membase
+ UCR1
);
1579 while (!(readl(sport
->port
.membase
+ USR2
) & USR2_TXDC
))
1582 /* then, disable everything */
1583 old_ucr2
= readl(sport
->port
.membase
+ UCR2
);
1584 writel(old_ucr2
& ~(UCR2_TXEN
| UCR2_RXEN
),
1585 sport
->port
.membase
+ UCR2
);
1586 old_ucr2
&= (UCR2_TXEN
| UCR2_RXEN
| UCR2_ATEN
);
1588 /* custom-baudrate handling */
1589 div
= sport
->port
.uartclk
/ (baud
* 16);
1590 if (baud
== 38400 && quot
!= div
)
1591 baud
= sport
->port
.uartclk
/ (quot
* 16);
1593 div
= sport
->port
.uartclk
/ (baud
* 16);
1599 rational_best_approximation(16 * div
* baud
, sport
->port
.uartclk
,
1600 1 << 16, 1 << 16, &num
, &denom
);
1602 tdiv64
= sport
->port
.uartclk
;
1604 do_div(tdiv64
, denom
* 16 * div
);
1605 tty_termios_encode_baud_rate(termios
,
1606 (speed_t
)tdiv64
, (speed_t
)tdiv64
);
1611 ufcr
= readl(sport
->port
.membase
+ UFCR
);
1612 ufcr
= (ufcr
& (~UFCR_RFDIV
)) | UFCR_RFDIV_REG(div
);
1613 writel(ufcr
, sport
->port
.membase
+ UFCR
);
1615 writel(num
, sport
->port
.membase
+ UBIR
);
1616 writel(denom
, sport
->port
.membase
+ UBMR
);
1618 if (!is_imx1_uart(sport
))
1619 writel(sport
->port
.uartclk
/ div
/ 1000,
1620 sport
->port
.membase
+ IMX21_ONEMS
);
1622 writel(old_ucr1
, sport
->port
.membase
+ UCR1
);
1624 /* set the parity, stop bits and data size */
1625 writel(ucr2
| old_ucr2
, sport
->port
.membase
+ UCR2
);
1627 if (UART_ENABLE_MS(&sport
->port
, termios
->c_cflag
))
1628 imx_enable_ms(&sport
->port
);
1630 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1633 static const char *imx_type(struct uart_port
*port
)
1635 struct imx_port
*sport
= (struct imx_port
*)port
;
1637 return sport
->port
.type
== PORT_IMX
? "IMX" : NULL
;
1641 * Configure/autoconfigure the port.
1643 static void imx_config_port(struct uart_port
*port
, int flags
)
1645 struct imx_port
*sport
= (struct imx_port
*)port
;
1647 if (flags
& UART_CONFIG_TYPE
)
1648 sport
->port
.type
= PORT_IMX
;
1652 * Verify the new serial_struct (for TIOCSSERIAL).
1653 * The only change we allow are to the flags and type, and
1654 * even then only between PORT_IMX and PORT_UNKNOWN
1657 imx_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
1659 struct imx_port
*sport
= (struct imx_port
*)port
;
1662 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_IMX
)
1664 if (sport
->port
.irq
!= ser
->irq
)
1666 if (ser
->io_type
!= UPIO_MEM
)
1668 if (sport
->port
.uartclk
/ 16 != ser
->baud_base
)
1670 if (sport
->port
.mapbase
!= (unsigned long)ser
->iomem_base
)
1672 if (sport
->port
.iobase
!= ser
->port
)
1679 #if defined(CONFIG_CONSOLE_POLL)
1681 static int imx_poll_init(struct uart_port
*port
)
1683 struct imx_port
*sport
= (struct imx_port
*)port
;
1684 unsigned long flags
;
1688 retval
= clk_prepare_enable(sport
->clk_ipg
);
1691 retval
= clk_prepare_enable(sport
->clk_per
);
1693 clk_disable_unprepare(sport
->clk_ipg
);
1695 imx_setup_ufcr(sport
, TXTL_DEFAULT
, RXTL_DEFAULT
);
1697 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1699 temp
= readl(sport
->port
.membase
+ UCR1
);
1700 if (is_imx1_uart(sport
))
1701 temp
|= IMX1_UCR1_UARTCLKEN
;
1702 temp
|= UCR1_UARTEN
| UCR1_RRDYEN
;
1703 temp
&= ~(UCR1_TXMPTYEN
| UCR1_RTSDEN
);
1704 writel(temp
, sport
->port
.membase
+ UCR1
);
1706 temp
= readl(sport
->port
.membase
+ UCR2
);
1708 writel(temp
, sport
->port
.membase
+ UCR2
);
1710 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1715 static int imx_poll_get_char(struct uart_port
*port
)
1717 if (!(readl_relaxed(port
->membase
+ USR2
) & USR2_RDR
))
1718 return NO_POLL_CHAR
;
1720 return readl_relaxed(port
->membase
+ URXD0
) & URXD_RX_DATA
;
1723 static void imx_poll_put_char(struct uart_port
*port
, unsigned char c
)
1725 unsigned int status
;
1729 status
= readl_relaxed(port
->membase
+ USR1
);
1730 } while (~status
& USR1_TRDY
);
1733 writel_relaxed(c
, port
->membase
+ URTX0
);
1737 status
= readl_relaxed(port
->membase
+ USR2
);
1738 } while (~status
& USR2_TXDC
);
1742 static int imx_rs485_config(struct uart_port
*port
,
1743 struct serial_rs485
*rs485conf
)
1745 struct imx_port
*sport
= (struct imx_port
*)port
;
1749 rs485conf
->delay_rts_before_send
= 0;
1750 rs485conf
->delay_rts_after_send
= 0;
1752 /* RTS is required to control the transmitter */
1753 if (!sport
->have_rtscts
&& !sport
->have_rtsgpio
)
1754 rs485conf
->flags
&= ~SER_RS485_ENABLED
;
1756 if (rs485conf
->flags
& SER_RS485_ENABLED
) {
1757 /* disable transmitter */
1758 temp
= readl(sport
->port
.membase
+ UCR2
);
1759 if (rs485conf
->flags
& SER_RS485_RTS_AFTER_SEND
)
1760 imx_port_rts_active(sport
, &temp
);
1762 imx_port_rts_inactive(sport
, &temp
);
1763 writel(temp
, sport
->port
.membase
+ UCR2
);
1766 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1767 if (!(rs485conf
->flags
& SER_RS485_ENABLED
) ||
1768 rs485conf
->flags
& SER_RS485_RX_DURING_TX
) {
1769 temp
= readl(sport
->port
.membase
+ UCR2
);
1771 writel(temp
, sport
->port
.membase
+ UCR2
);
1774 port
->rs485
= *rs485conf
;
1779 static const struct uart_ops imx_pops
= {
1780 .tx_empty
= imx_tx_empty
,
1781 .set_mctrl
= imx_set_mctrl
,
1782 .get_mctrl
= imx_get_mctrl
,
1783 .stop_tx
= imx_stop_tx
,
1784 .start_tx
= imx_start_tx
,
1785 .stop_rx
= imx_stop_rx
,
1786 .enable_ms
= imx_enable_ms
,
1787 .break_ctl
= imx_break_ctl
,
1788 .startup
= imx_startup
,
1789 .shutdown
= imx_shutdown
,
1790 .flush_buffer
= imx_flush_buffer
,
1791 .set_termios
= imx_set_termios
,
1793 .config_port
= imx_config_port
,
1794 .verify_port
= imx_verify_port
,
1795 #if defined(CONFIG_CONSOLE_POLL)
1796 .poll_init
= imx_poll_init
,
1797 .poll_get_char
= imx_poll_get_char
,
1798 .poll_put_char
= imx_poll_put_char
,
1802 static struct imx_port
*imx_ports
[UART_NR
];
1804 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1805 static void imx_console_putchar(struct uart_port
*port
, int ch
)
1807 struct imx_port
*sport
= (struct imx_port
*)port
;
1809 while (readl(sport
->port
.membase
+ uts_reg(sport
)) & UTS_TXFULL
)
1812 writel(ch
, sport
->port
.membase
+ URTX0
);
1816 * Interrupts are disabled on entering
1819 imx_console_write(struct console
*co
, const char *s
, unsigned int count
)
1821 struct imx_port
*sport
= imx_ports
[co
->index
];
1822 struct imx_port_ucrs old_ucr
;
1824 unsigned long flags
= 0;
1828 retval
= clk_enable(sport
->clk_per
);
1831 retval
= clk_enable(sport
->clk_ipg
);
1833 clk_disable(sport
->clk_per
);
1837 if (sport
->port
.sysrq
)
1839 else if (oops_in_progress
)
1840 locked
= spin_trylock_irqsave(&sport
->port
.lock
, flags
);
1842 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1845 * First, save UCR1/2/3 and then disable interrupts
1847 imx_port_ucrs_save(&sport
->port
, &old_ucr
);
1848 ucr1
= old_ucr
.ucr1
;
1850 if (is_imx1_uart(sport
))
1851 ucr1
|= IMX1_UCR1_UARTCLKEN
;
1852 ucr1
|= UCR1_UARTEN
;
1853 ucr1
&= ~(UCR1_TXMPTYEN
| UCR1_RRDYEN
| UCR1_RTSDEN
);
1855 writel(ucr1
, sport
->port
.membase
+ UCR1
);
1857 writel(old_ucr
.ucr2
| UCR2_TXEN
, sport
->port
.membase
+ UCR2
);
1859 uart_console_write(&sport
->port
, s
, count
, imx_console_putchar
);
1862 * Finally, wait for transmitter to become empty
1863 * and restore UCR1/2/3
1865 while (!(readl(sport
->port
.membase
+ USR2
) & USR2_TXDC
));
1867 imx_port_ucrs_restore(&sport
->port
, &old_ucr
);
1870 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1872 clk_disable(sport
->clk_ipg
);
1873 clk_disable(sport
->clk_per
);
1877 * If the port was already initialised (eg, by a boot loader),
1878 * try to determine the current setup.
1881 imx_console_get_options(struct imx_port
*sport
, int *baud
,
1882 int *parity
, int *bits
)
1885 if (readl(sport
->port
.membase
+ UCR1
) & UCR1_UARTEN
) {
1886 /* ok, the port was enabled */
1887 unsigned int ucr2
, ubir
, ubmr
, uartclk
;
1888 unsigned int baud_raw
;
1889 unsigned int ucfr_rfdiv
;
1891 ucr2
= readl(sport
->port
.membase
+ UCR2
);
1894 if (ucr2
& UCR2_PREN
) {
1895 if (ucr2
& UCR2_PROE
)
1906 ubir
= readl(sport
->port
.membase
+ UBIR
) & 0xffff;
1907 ubmr
= readl(sport
->port
.membase
+ UBMR
) & 0xffff;
1909 ucfr_rfdiv
= (readl(sport
->port
.membase
+ UFCR
) & UFCR_RFDIV
) >> 7;
1910 if (ucfr_rfdiv
== 6)
1913 ucfr_rfdiv
= 6 - ucfr_rfdiv
;
1915 uartclk
= clk_get_rate(sport
->clk_per
);
1916 uartclk
/= ucfr_rfdiv
;
1919 * The next code provides exact computation of
1920 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1921 * without need of float support or long long division,
1922 * which would be required to prevent 32bit arithmetic overflow
1924 unsigned int mul
= ubir
+ 1;
1925 unsigned int div
= 16 * (ubmr
+ 1);
1926 unsigned int rem
= uartclk
% div
;
1928 baud_raw
= (uartclk
/ div
) * mul
;
1929 baud_raw
+= (rem
* mul
+ div
/ 2) / div
;
1930 *baud
= (baud_raw
+ 50) / 100 * 100;
1933 if (*baud
!= baud_raw
)
1934 pr_info("Console IMX rounded baud rate from %d to %d\n",
1940 imx_console_setup(struct console
*co
, char *options
)
1942 struct imx_port
*sport
;
1950 * Check whether an invalid uart number has been specified, and
1951 * if so, search for the first available port that does have
1954 if (co
->index
== -1 || co
->index
>= ARRAY_SIZE(imx_ports
))
1956 sport
= imx_ports
[co
->index
];
1960 /* For setting the registers, we only need to enable the ipg clock. */
1961 retval
= clk_prepare_enable(sport
->clk_ipg
);
1966 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1968 imx_console_get_options(sport
, &baud
, &parity
, &bits
);
1970 imx_setup_ufcr(sport
, TXTL_DEFAULT
, RXTL_DEFAULT
);
1972 retval
= uart_set_options(&sport
->port
, co
, baud
, parity
, bits
, flow
);
1974 clk_disable(sport
->clk_ipg
);
1976 clk_unprepare(sport
->clk_ipg
);
1980 retval
= clk_prepare(sport
->clk_per
);
1982 clk_disable_unprepare(sport
->clk_ipg
);
1988 static struct uart_driver imx_reg
;
1989 static struct console imx_console
= {
1991 .write
= imx_console_write
,
1992 .device
= uart_console_device
,
1993 .setup
= imx_console_setup
,
1994 .flags
= CON_PRINTBUFFER
,
1999 #define IMX_CONSOLE &imx_console
2002 static void imx_console_early_putchar(struct uart_port
*port
, int ch
)
2004 while (readl_relaxed(port
->membase
+ IMX21_UTS
) & UTS_TXFULL
)
2007 writel_relaxed(ch
, port
->membase
+ URTX0
);
2010 static void imx_console_early_write(struct console
*con
, const char *s
,
2013 struct earlycon_device
*dev
= con
->data
;
2015 uart_console_write(&dev
->port
, s
, count
, imx_console_early_putchar
);
2019 imx_console_early_setup(struct earlycon_device
*dev
, const char *opt
)
2021 if (!dev
->port
.membase
)
2024 dev
->con
->write
= imx_console_early_write
;
2028 OF_EARLYCON_DECLARE(ec_imx6q
, "fsl,imx6q-uart", imx_console_early_setup
);
2029 OF_EARLYCON_DECLARE(ec_imx21
, "fsl,imx21-uart", imx_console_early_setup
);
2033 #define IMX_CONSOLE NULL
2036 static struct uart_driver imx_reg
= {
2037 .owner
= THIS_MODULE
,
2038 .driver_name
= DRIVER_NAME
,
2039 .dev_name
= DEV_NAME
,
2040 .major
= SERIAL_IMX_MAJOR
,
2041 .minor
= MINOR_START
,
2042 .nr
= ARRAY_SIZE(imx_ports
),
2043 .cons
= IMX_CONSOLE
,
2048 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
2049 * could successfully get all information from dt or a negative errno.
2051 static int serial_imx_probe_dt(struct imx_port
*sport
,
2052 struct platform_device
*pdev
)
2054 struct device_node
*np
= pdev
->dev
.of_node
;
2057 sport
->devdata
= of_device_get_match_data(&pdev
->dev
);
2058 if (!sport
->devdata
)
2059 /* no device tree device */
2062 ret
= of_alias_get_id(np
, "serial");
2064 dev_err(&pdev
->dev
, "failed to get alias id, errno %d\n", ret
);
2067 sport
->port
.line
= ret
;
2069 if (of_get_property(np
, "uart-has-rtscts", NULL
) ||
2070 of_get_property(np
, "fsl,uart-has-rtscts", NULL
) /* deprecated */)
2071 sport
->have_rtscts
= 1;
2073 if (of_get_property(np
, "fsl,dte-mode", NULL
))
2074 sport
->dte_mode
= 1;
2076 if (of_get_property(np
, "rts-gpios", NULL
))
2077 sport
->have_rtsgpio
= 1;
2082 static inline int serial_imx_probe_dt(struct imx_port
*sport
,
2083 struct platform_device
*pdev
)
2089 static void serial_imx_probe_pdata(struct imx_port
*sport
,
2090 struct platform_device
*pdev
)
2092 struct imxuart_platform_data
*pdata
= dev_get_platdata(&pdev
->dev
);
2094 sport
->port
.line
= pdev
->id
;
2095 sport
->devdata
= (struct imx_uart_data
*) pdev
->id_entry
->driver_data
;
2100 if (pdata
->flags
& IMXUART_HAVE_RTSCTS
)
2101 sport
->have_rtscts
= 1;
2104 static int serial_imx_probe(struct platform_device
*pdev
)
2106 struct imx_port
*sport
;
2109 struct resource
*res
;
2110 int txirq
, rxirq
, rtsirq
;
2112 sport
= devm_kzalloc(&pdev
->dev
, sizeof(*sport
), GFP_KERNEL
);
2116 ret
= serial_imx_probe_dt(sport
, pdev
);
2118 serial_imx_probe_pdata(sport
, pdev
);
2122 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2123 base
= devm_ioremap_resource(&pdev
->dev
, res
);
2125 return PTR_ERR(base
);
2127 rxirq
= platform_get_irq(pdev
, 0);
2128 txirq
= platform_get_irq(pdev
, 1);
2129 rtsirq
= platform_get_irq(pdev
, 2);
2131 sport
->port
.dev
= &pdev
->dev
;
2132 sport
->port
.mapbase
= res
->start
;
2133 sport
->port
.membase
= base
;
2134 sport
->port
.type
= PORT_IMX
,
2135 sport
->port
.iotype
= UPIO_MEM
;
2136 sport
->port
.irq
= rxirq
;
2137 sport
->port
.fifosize
= 32;
2138 sport
->port
.ops
= &imx_pops
;
2139 sport
->port
.rs485_config
= imx_rs485_config
;
2140 sport
->port
.rs485
.flags
=
2141 SER_RS485_RTS_ON_SEND
| SER_RS485_RX_DURING_TX
;
2142 sport
->port
.flags
= UPF_BOOT_AUTOCONF
;
2143 init_timer(&sport
->timer
);
2144 sport
->timer
.function
= imx_timeout
;
2145 sport
->timer
.data
= (unsigned long)sport
;
2147 sport
->gpios
= mctrl_gpio_init(&sport
->port
, 0);
2148 if (IS_ERR(sport
->gpios
))
2149 return PTR_ERR(sport
->gpios
);
2151 sport
->clk_ipg
= devm_clk_get(&pdev
->dev
, "ipg");
2152 if (IS_ERR(sport
->clk_ipg
)) {
2153 ret
= PTR_ERR(sport
->clk_ipg
);
2154 dev_err(&pdev
->dev
, "failed to get ipg clk: %d\n", ret
);
2158 sport
->clk_per
= devm_clk_get(&pdev
->dev
, "per");
2159 if (IS_ERR(sport
->clk_per
)) {
2160 ret
= PTR_ERR(sport
->clk_per
);
2161 dev_err(&pdev
->dev
, "failed to get per clk: %d\n", ret
);
2165 sport
->port
.uartclk
= clk_get_rate(sport
->clk_per
);
2167 /* For register access, we only need to enable the ipg clock. */
2168 ret
= clk_prepare_enable(sport
->clk_ipg
);
2170 dev_err(&pdev
->dev
, "failed to enable per clk: %d\n", ret
);
2174 /* Disable interrupts before requesting them */
2175 reg
= readl_relaxed(sport
->port
.membase
+ UCR1
);
2176 reg
&= ~(UCR1_ADEN
| UCR1_TRDYEN
| UCR1_IDEN
| UCR1_RRDYEN
|
2177 UCR1_TXMPTYEN
| UCR1_RTSDEN
);
2178 writel_relaxed(reg
, sport
->port
.membase
+ UCR1
);
2180 if (!is_imx1_uart(sport
) && sport
->dte_mode
) {
2182 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2183 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2184 * and DCD (when they are outputs) or enables the respective
2185 * irqs. So set this bit early, i.e. before requesting irqs.
2187 reg
= readl(sport
->port
.membase
+ UFCR
);
2188 if (!(reg
& UFCR_DCEDTE
))
2189 writel(reg
| UFCR_DCEDTE
, sport
->port
.membase
+ UFCR
);
2192 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2193 * enabled later because they cannot be cleared
2194 * (confirmed on i.MX25) which makes them unusable.
2196 writel(IMX21_UCR3_RXDMUXSEL
| UCR3_ADNIMP
| UCR3_DSR
,
2197 sport
->port
.membase
+ UCR3
);
2200 unsigned long ucr3
= UCR3_DSR
;
2202 reg
= readl(sport
->port
.membase
+ UFCR
);
2203 if (reg
& UFCR_DCEDTE
)
2204 writel(reg
& ~UFCR_DCEDTE
, sport
->port
.membase
+ UFCR
);
2206 if (!is_imx1_uart(sport
))
2207 ucr3
|= IMX21_UCR3_RXDMUXSEL
| UCR3_ADNIMP
;
2208 writel(ucr3
, sport
->port
.membase
+ UCR3
);
2211 clk_disable_unprepare(sport
->clk_ipg
);
2214 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2215 * chips only have one interrupt.
2218 ret
= devm_request_irq(&pdev
->dev
, rxirq
, imx_rxint
, 0,
2219 dev_name(&pdev
->dev
), sport
);
2221 dev_err(&pdev
->dev
, "failed to request rx irq: %d\n",
2226 ret
= devm_request_irq(&pdev
->dev
, txirq
, imx_txint
, 0,
2227 dev_name(&pdev
->dev
), sport
);
2229 dev_err(&pdev
->dev
, "failed to request tx irq: %d\n",
2234 ret
= devm_request_irq(&pdev
->dev
, rxirq
, imx_int
, 0,
2235 dev_name(&pdev
->dev
), sport
);
2237 dev_err(&pdev
->dev
, "failed to request irq: %d\n", ret
);
2242 imx_ports
[sport
->port
.line
] = sport
;
2244 platform_set_drvdata(pdev
, sport
);
2246 return uart_add_one_port(&imx_reg
, &sport
->port
);
2249 static int serial_imx_remove(struct platform_device
*pdev
)
2251 struct imx_port
*sport
= platform_get_drvdata(pdev
);
2253 return uart_remove_one_port(&imx_reg
, &sport
->port
);
2256 static void serial_imx_restore_context(struct imx_port
*sport
)
2258 if (!sport
->context_saved
)
2261 writel(sport
->saved_reg
[4], sport
->port
.membase
+ UFCR
);
2262 writel(sport
->saved_reg
[5], sport
->port
.membase
+ UESC
);
2263 writel(sport
->saved_reg
[6], sport
->port
.membase
+ UTIM
);
2264 writel(sport
->saved_reg
[7], sport
->port
.membase
+ UBIR
);
2265 writel(sport
->saved_reg
[8], sport
->port
.membase
+ UBMR
);
2266 writel(sport
->saved_reg
[9], sport
->port
.membase
+ IMX21_UTS
);
2267 writel(sport
->saved_reg
[0], sport
->port
.membase
+ UCR1
);
2268 writel(sport
->saved_reg
[1] | UCR2_SRST
, sport
->port
.membase
+ UCR2
);
2269 writel(sport
->saved_reg
[2], sport
->port
.membase
+ UCR3
);
2270 writel(sport
->saved_reg
[3], sport
->port
.membase
+ UCR4
);
2271 sport
->context_saved
= false;
2274 static void serial_imx_save_context(struct imx_port
*sport
)
2276 /* Save necessary regs */
2277 sport
->saved_reg
[0] = readl(sport
->port
.membase
+ UCR1
);
2278 sport
->saved_reg
[1] = readl(sport
->port
.membase
+ UCR2
);
2279 sport
->saved_reg
[2] = readl(sport
->port
.membase
+ UCR3
);
2280 sport
->saved_reg
[3] = readl(sport
->port
.membase
+ UCR4
);
2281 sport
->saved_reg
[4] = readl(sport
->port
.membase
+ UFCR
);
2282 sport
->saved_reg
[5] = readl(sport
->port
.membase
+ UESC
);
2283 sport
->saved_reg
[6] = readl(sport
->port
.membase
+ UTIM
);
2284 sport
->saved_reg
[7] = readl(sport
->port
.membase
+ UBIR
);
2285 sport
->saved_reg
[8] = readl(sport
->port
.membase
+ UBMR
);
2286 sport
->saved_reg
[9] = readl(sport
->port
.membase
+ IMX21_UTS
);
2287 sport
->context_saved
= true;
2290 static void serial_imx_enable_wakeup(struct imx_port
*sport
, bool on
)
2294 val
= readl(sport
->port
.membase
+ UCR3
);
2298 val
&= ~UCR3_AWAKEN
;
2299 writel(val
, sport
->port
.membase
+ UCR3
);
2301 val
= readl(sport
->port
.membase
+ UCR1
);
2305 val
&= ~UCR1_RTSDEN
;
2306 writel(val
, sport
->port
.membase
+ UCR1
);
2309 static int imx_serial_port_suspend_noirq(struct device
*dev
)
2311 struct platform_device
*pdev
= to_platform_device(dev
);
2312 struct imx_port
*sport
= platform_get_drvdata(pdev
);
2315 ret
= clk_enable(sport
->clk_ipg
);
2319 serial_imx_save_context(sport
);
2321 clk_disable(sport
->clk_ipg
);
2326 static int imx_serial_port_resume_noirq(struct device
*dev
)
2328 struct platform_device
*pdev
= to_platform_device(dev
);
2329 struct imx_port
*sport
= platform_get_drvdata(pdev
);
2332 ret
= clk_enable(sport
->clk_ipg
);
2336 serial_imx_restore_context(sport
);
2338 clk_disable(sport
->clk_ipg
);
2343 static int imx_serial_port_suspend(struct device
*dev
)
2345 struct platform_device
*pdev
= to_platform_device(dev
);
2346 struct imx_port
*sport
= platform_get_drvdata(pdev
);
2348 /* enable wakeup from i.MX UART */
2349 serial_imx_enable_wakeup(sport
, true);
2351 uart_suspend_port(&imx_reg
, &sport
->port
);
2353 /* Needed to enable clock in suspend_noirq */
2354 return clk_prepare(sport
->clk_ipg
);
2357 static int imx_serial_port_resume(struct device
*dev
)
2359 struct platform_device
*pdev
= to_platform_device(dev
);
2360 struct imx_port
*sport
= platform_get_drvdata(pdev
);
2362 /* disable wakeup from i.MX UART */
2363 serial_imx_enable_wakeup(sport
, false);
2365 uart_resume_port(&imx_reg
, &sport
->port
);
2367 clk_unprepare(sport
->clk_ipg
);
2372 static const struct dev_pm_ops imx_serial_port_pm_ops
= {
2373 .suspend_noirq
= imx_serial_port_suspend_noirq
,
2374 .resume_noirq
= imx_serial_port_resume_noirq
,
2375 .suspend
= imx_serial_port_suspend
,
2376 .resume
= imx_serial_port_resume
,
2379 static struct platform_driver serial_imx_driver
= {
2380 .probe
= serial_imx_probe
,
2381 .remove
= serial_imx_remove
,
2383 .id_table
= imx_uart_devtype
,
2386 .of_match_table
= imx_uart_dt_ids
,
2387 .pm
= &imx_serial_port_pm_ops
,
2391 static int __init
imx_serial_init(void)
2393 int ret
= uart_register_driver(&imx_reg
);
2398 ret
= platform_driver_register(&serial_imx_driver
);
2400 uart_unregister_driver(&imx_reg
);
2405 static void __exit
imx_serial_exit(void)
2407 platform_driver_unregister(&serial_imx_driver
);
2408 uart_unregister_driver(&imx_reg
);
2411 module_init(imx_serial_init
);
2412 module_exit(imx_serial_exit
);
2414 MODULE_AUTHOR("Sascha Hauer");
2415 MODULE_DESCRIPTION("IMX generic serial port driver");
2416 MODULE_LICENSE("GPL");
2417 MODULE_ALIAS("platform:imx-uart");