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[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / imx.c
1 /*
2 * Driver for Motorola IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
28 */
29
30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #define SUPPORT_SYSRQ
32 #endif
33
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/console.h>
38 #include <linux/sysrq.h>
39 #include <linux/platform_device.h>
40 #include <linux/tty.h>
41 #include <linux/tty_flip.h>
42 #include <linux/serial_core.h>
43 #include <linux/serial.h>
44 #include <linux/clk.h>
45 #include <linux/delay.h>
46 #include <linux/rational.h>
47 #include <linux/slab.h>
48 #include <linux/of.h>
49 #include <linux/of_device.h>
50 #include <linux/io.h>
51 #include <linux/dma-mapping.h>
52
53 #include <asm/irq.h>
54 #include <linux/platform_data/serial-imx.h>
55 #include <linux/platform_data/dma-imx.h>
56
57 /* Register definitions */
58 #define URXD0 0x0 /* Receiver Register */
59 #define URTX0 0x40 /* Transmitter Register */
60 #define UCR1 0x80 /* Control Register 1 */
61 #define UCR2 0x84 /* Control Register 2 */
62 #define UCR3 0x88 /* Control Register 3 */
63 #define UCR4 0x8c /* Control Register 4 */
64 #define UFCR 0x90 /* FIFO Control Register */
65 #define USR1 0x94 /* Status Register 1 */
66 #define USR2 0x98 /* Status Register 2 */
67 #define UESC 0x9c /* Escape Character Register */
68 #define UTIM 0xa0 /* Escape Timer Register */
69 #define UBIR 0xa4 /* BRM Incremental Register */
70 #define UBMR 0xa8 /* BRM Modulator Register */
71 #define UBRC 0xac /* Baud Rate Count Register */
72 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
73 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
74 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
75
76 /* UART Control Register Bit Fields.*/
77 #define URXD_CHARRDY (1<<15)
78 #define URXD_ERR (1<<14)
79 #define URXD_OVRRUN (1<<13)
80 #define URXD_FRMERR (1<<12)
81 #define URXD_BRK (1<<11)
82 #define URXD_PRERR (1<<10)
83 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
84 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
85 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
86 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
87 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
88 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
89 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
90 #define UCR1_IREN (1<<7) /* Infrared interface enable */
91 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
92 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
93 #define UCR1_SNDBRK (1<<4) /* Send break */
94 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
95 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
96 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
97 #define UCR1_DOZE (1<<1) /* Doze */
98 #define UCR1_UARTEN (1<<0) /* UART enabled */
99 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
100 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
101 #define UCR2_CTSC (1<<13) /* CTS pin control */
102 #define UCR2_CTS (1<<12) /* Clear to send */
103 #define UCR2_ESCEN (1<<11) /* Escape enable */
104 #define UCR2_PREN (1<<8) /* Parity enable */
105 #define UCR2_PROE (1<<7) /* Parity odd/even */
106 #define UCR2_STPB (1<<6) /* Stop */
107 #define UCR2_WS (1<<5) /* Word size */
108 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
109 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
110 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
111 #define UCR2_RXEN (1<<1) /* Receiver enabled */
112 #define UCR2_SRST (1<<0) /* SW reset */
113 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
114 #define UCR3_PARERREN (1<<12) /* Parity enable */
115 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
116 #define UCR3_DSR (1<<10) /* Data set ready */
117 #define UCR3_DCD (1<<9) /* Data carrier detect */
118 #define UCR3_RI (1<<8) /* Ring indicator */
119 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
120 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
121 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
122 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
123 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
124 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
125 #define UCR3_BPEN (1<<0) /* Preset registers enable */
126 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
127 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
128 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
129 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
130 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
131 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
132 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
133 #define UCR4_IRSC (1<<5) /* IR special case */
134 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
135 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
136 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
137 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
138 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
139 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
140 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
141 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
142 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
143 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
144 #define USR1_RTSS (1<<14) /* RTS pin status */
145 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
146 #define USR1_RTSD (1<<12) /* RTS delta */
147 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
148 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
149 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
150 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
151 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
152 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
153 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
154 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
155 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
156 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
157 #define USR2_IDLE (1<<12) /* Idle condition */
158 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
159 #define USR2_WAKE (1<<7) /* Wake */
160 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
161 #define USR2_TXDC (1<<3) /* Transmitter complete */
162 #define USR2_BRCD (1<<2) /* Break condition */
163 #define USR2_ORE (1<<1) /* Overrun error */
164 #define USR2_RDR (1<<0) /* Recv data ready */
165 #define UTS_FRCPERR (1<<13) /* Force parity error */
166 #define UTS_LOOP (1<<12) /* Loop tx and rx */
167 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
168 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
169 #define UTS_TXFULL (1<<4) /* TxFIFO full */
170 #define UTS_RXFULL (1<<3) /* RxFIFO full */
171 #define UTS_SOFTRST (1<<0) /* Software reset */
172
173 /* We've been assigned a range on the "Low-density serial ports" major */
174 #define SERIAL_IMX_MAJOR 207
175 #define MINOR_START 16
176 #define DEV_NAME "ttymxc"
177
178 /*
179 * This determines how often we check the modem status signals
180 * for any change. They generally aren't connected to an IRQ
181 * so we have to poll them. We also check immediately before
182 * filling the TX fifo incase CTS has been dropped.
183 */
184 #define MCTRL_TIMEOUT (250*HZ/1000)
185
186 #define DRIVER_NAME "IMX-uart"
187
188 #define UART_NR 8
189
190 /* i.mx21 type uart runs on all i.mx except i.mx1 */
191 enum imx_uart_type {
192 IMX1_UART,
193 IMX21_UART,
194 IMX6Q_UART,
195 };
196
197 /* device type dependent stuff */
198 struct imx_uart_data {
199 unsigned uts_reg;
200 enum imx_uart_type devtype;
201 };
202
203 struct imx_port {
204 struct uart_port port;
205 struct timer_list timer;
206 unsigned int old_status;
207 int txirq, rxirq, rtsirq;
208 unsigned int have_rtscts:1;
209 unsigned int dte_mode:1;
210 unsigned int use_irda:1;
211 unsigned int irda_inv_rx:1;
212 unsigned int irda_inv_tx:1;
213 unsigned short trcv_delay; /* transceiver delay */
214 struct clk *clk_ipg;
215 struct clk *clk_per;
216 const struct imx_uart_data *devdata;
217
218 /* DMA fields */
219 unsigned int dma_is_inited:1;
220 unsigned int dma_is_enabled:1;
221 unsigned int dma_is_rxing:1;
222 unsigned int dma_is_txing:1;
223 struct dma_chan *dma_chan_rx, *dma_chan_tx;
224 struct scatterlist rx_sgl, tx_sgl[2];
225 void *rx_buf;
226 unsigned int rx_bytes, tx_bytes;
227 struct work_struct tsk_dma_rx, tsk_dma_tx;
228 unsigned int dma_tx_nents;
229 wait_queue_head_t dma_wait;
230 };
231
232 struct imx_port_ucrs {
233 unsigned int ucr1;
234 unsigned int ucr2;
235 unsigned int ucr3;
236 };
237
238 #ifdef CONFIG_IRDA
239 #define USE_IRDA(sport) ((sport)->use_irda)
240 #else
241 #define USE_IRDA(sport) (0)
242 #endif
243
244 static struct imx_uart_data imx_uart_devdata[] = {
245 [IMX1_UART] = {
246 .uts_reg = IMX1_UTS,
247 .devtype = IMX1_UART,
248 },
249 [IMX21_UART] = {
250 .uts_reg = IMX21_UTS,
251 .devtype = IMX21_UART,
252 },
253 [IMX6Q_UART] = {
254 .uts_reg = IMX21_UTS,
255 .devtype = IMX6Q_UART,
256 },
257 };
258
259 static struct platform_device_id imx_uart_devtype[] = {
260 {
261 .name = "imx1-uart",
262 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
263 }, {
264 .name = "imx21-uart",
265 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
266 }, {
267 .name = "imx6q-uart",
268 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
269 }, {
270 /* sentinel */
271 }
272 };
273 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
274
275 static struct of_device_id imx_uart_dt_ids[] = {
276 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
277 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
278 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
279 { /* sentinel */ }
280 };
281 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
282
283 static inline unsigned uts_reg(struct imx_port *sport)
284 {
285 return sport->devdata->uts_reg;
286 }
287
288 static inline int is_imx1_uart(struct imx_port *sport)
289 {
290 return sport->devdata->devtype == IMX1_UART;
291 }
292
293 static inline int is_imx21_uart(struct imx_port *sport)
294 {
295 return sport->devdata->devtype == IMX21_UART;
296 }
297
298 static inline int is_imx6q_uart(struct imx_port *sport)
299 {
300 return sport->devdata->devtype == IMX6Q_UART;
301 }
302 /*
303 * Save and restore functions for UCR1, UCR2 and UCR3 registers
304 */
305 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_IMX_CONSOLE)
306 static void imx_port_ucrs_save(struct uart_port *port,
307 struct imx_port_ucrs *ucr)
308 {
309 /* save control registers */
310 ucr->ucr1 = readl(port->membase + UCR1);
311 ucr->ucr2 = readl(port->membase + UCR2);
312 ucr->ucr3 = readl(port->membase + UCR3);
313 }
314
315 static void imx_port_ucrs_restore(struct uart_port *port,
316 struct imx_port_ucrs *ucr)
317 {
318 /* restore control registers */
319 writel(ucr->ucr1, port->membase + UCR1);
320 writel(ucr->ucr2, port->membase + UCR2);
321 writel(ucr->ucr3, port->membase + UCR3);
322 }
323 #endif
324
325 /*
326 * Handle any change of modem status signal since we were last called.
327 */
328 static void imx_mctrl_check(struct imx_port *sport)
329 {
330 unsigned int status, changed;
331
332 status = sport->port.ops->get_mctrl(&sport->port);
333 changed = status ^ sport->old_status;
334
335 if (changed == 0)
336 return;
337
338 sport->old_status = status;
339
340 if (changed & TIOCM_RI)
341 sport->port.icount.rng++;
342 if (changed & TIOCM_DSR)
343 sport->port.icount.dsr++;
344 if (changed & TIOCM_CAR)
345 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
346 if (changed & TIOCM_CTS)
347 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
348
349 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
350 }
351
352 /*
353 * This is our per-port timeout handler, for checking the
354 * modem status signals.
355 */
356 static void imx_timeout(unsigned long data)
357 {
358 struct imx_port *sport = (struct imx_port *)data;
359 unsigned long flags;
360
361 if (sport->port.state) {
362 spin_lock_irqsave(&sport->port.lock, flags);
363 imx_mctrl_check(sport);
364 spin_unlock_irqrestore(&sport->port.lock, flags);
365
366 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
367 }
368 }
369
370 /*
371 * interrupts disabled on entry
372 */
373 static void imx_stop_tx(struct uart_port *port)
374 {
375 struct imx_port *sport = (struct imx_port *)port;
376 unsigned long temp;
377
378 if (USE_IRDA(sport)) {
379 /* half duplex - wait for end of transmission */
380 int n = 256;
381 while ((--n > 0) &&
382 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
383 udelay(5);
384 barrier();
385 }
386 /*
387 * irda transceiver - wait a bit more to avoid
388 * cutoff, hardware dependent
389 */
390 udelay(sport->trcv_delay);
391
392 /*
393 * half duplex - reactivate receive mode,
394 * flush receive pipe echo crap
395 */
396 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
397 temp = readl(sport->port.membase + UCR1);
398 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
399 writel(temp, sport->port.membase + UCR1);
400
401 temp = readl(sport->port.membase + UCR4);
402 temp &= ~(UCR4_TCEN);
403 writel(temp, sport->port.membase + UCR4);
404
405 while (readl(sport->port.membase + URXD0) &
406 URXD_CHARRDY)
407 barrier();
408
409 temp = readl(sport->port.membase + UCR1);
410 temp |= UCR1_RRDYEN;
411 writel(temp, sport->port.membase + UCR1);
412
413 temp = readl(sport->port.membase + UCR4);
414 temp |= UCR4_DREN;
415 writel(temp, sport->port.membase + UCR4);
416 }
417 return;
418 }
419
420 /*
421 * We are maybe in the SMP context, so if the DMA TX thread is running
422 * on other cpu, we have to wait for it to finish.
423 */
424 if (sport->dma_is_enabled && sport->dma_is_txing)
425 return;
426
427 temp = readl(sport->port.membase + UCR1);
428 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
429 }
430
431 /*
432 * interrupts disabled on entry
433 */
434 static void imx_stop_rx(struct uart_port *port)
435 {
436 struct imx_port *sport = (struct imx_port *)port;
437 unsigned long temp;
438
439 /*
440 * We are maybe in the SMP context, so if the DMA TX thread is running
441 * on other cpu, we have to wait for it to finish.
442 */
443 if (sport->dma_is_enabled && sport->dma_is_rxing)
444 return;
445
446 temp = readl(sport->port.membase + UCR2);
447 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
448 }
449
450 /*
451 * Set the modem control timer to fire immediately.
452 */
453 static void imx_enable_ms(struct uart_port *port)
454 {
455 struct imx_port *sport = (struct imx_port *)port;
456
457 mod_timer(&sport->timer, jiffies);
458 }
459
460 static inline void imx_transmit_buffer(struct imx_port *sport)
461 {
462 struct circ_buf *xmit = &sport->port.state->xmit;
463
464 while (!uart_circ_empty(xmit) &&
465 !(readl(sport->port.membase + uts_reg(sport))
466 & UTS_TXFULL)) {
467 /* send xmit->buf[xmit->tail]
468 * out the port here */
469 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
470 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
471 sport->port.icount.tx++;
472 }
473
474 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
475 uart_write_wakeup(&sport->port);
476
477 if (uart_circ_empty(xmit))
478 imx_stop_tx(&sport->port);
479 }
480
481 static void dma_tx_callback(void *data)
482 {
483 struct imx_port *sport = data;
484 struct scatterlist *sgl = &sport->tx_sgl[0];
485 struct circ_buf *xmit = &sport->port.state->xmit;
486 unsigned long flags;
487
488 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
489
490 sport->dma_is_txing = 0;
491
492 /* update the stat */
493 spin_lock_irqsave(&sport->port.lock, flags);
494 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
495 sport->port.icount.tx += sport->tx_bytes;
496 spin_unlock_irqrestore(&sport->port.lock, flags);
497
498 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
499
500 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
501 uart_write_wakeup(&sport->port);
502
503 if (waitqueue_active(&sport->dma_wait)) {
504 wake_up(&sport->dma_wait);
505 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
506 return;
507 }
508
509 schedule_work(&sport->tsk_dma_tx);
510 }
511
512 static void dma_tx_work(struct work_struct *w)
513 {
514 struct imx_port *sport = container_of(w, struct imx_port, tsk_dma_tx);
515 struct circ_buf *xmit = &sport->port.state->xmit;
516 struct scatterlist *sgl = sport->tx_sgl;
517 struct dma_async_tx_descriptor *desc;
518 struct dma_chan *chan = sport->dma_chan_tx;
519 struct device *dev = sport->port.dev;
520 enum dma_status status;
521 unsigned long flags;
522 int ret;
523
524 status = chan->device->device_tx_status(chan, (dma_cookie_t)0, NULL);
525 if (DMA_IN_PROGRESS == status)
526 return;
527
528 spin_lock_irqsave(&sport->port.lock, flags);
529 sport->tx_bytes = uart_circ_chars_pending(xmit);
530 if (sport->tx_bytes == 0) {
531 spin_unlock_irqrestore(&sport->port.lock, flags);
532 return;
533 }
534
535 if (xmit->tail > xmit->head) {
536 sport->dma_tx_nents = 2;
537 sg_init_table(sgl, 2);
538 sg_set_buf(sgl, xmit->buf + xmit->tail,
539 UART_XMIT_SIZE - xmit->tail);
540 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
541 } else {
542 sport->dma_tx_nents = 1;
543 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
544 }
545 spin_unlock_irqrestore(&sport->port.lock, flags);
546
547 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
548 if (ret == 0) {
549 dev_err(dev, "DMA mapping error for TX.\n");
550 return;
551 }
552 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
553 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
554 if (!desc) {
555 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
556 return;
557 }
558 desc->callback = dma_tx_callback;
559 desc->callback_param = sport;
560
561 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
562 uart_circ_chars_pending(xmit));
563 /* fire it */
564 sport->dma_is_txing = 1;
565 dmaengine_submit(desc);
566 dma_async_issue_pending(chan);
567 return;
568 }
569
570 /*
571 * interrupts disabled on entry
572 */
573 static void imx_start_tx(struct uart_port *port)
574 {
575 struct imx_port *sport = (struct imx_port *)port;
576 unsigned long temp;
577
578 if (USE_IRDA(sport)) {
579 /* half duplex in IrDA mode; have to disable receive mode */
580 temp = readl(sport->port.membase + UCR4);
581 temp &= ~(UCR4_DREN);
582 writel(temp, sport->port.membase + UCR4);
583
584 temp = readl(sport->port.membase + UCR1);
585 temp &= ~(UCR1_RRDYEN);
586 writel(temp, sport->port.membase + UCR1);
587 }
588 /* Clear any pending ORE flag before enabling interrupt */
589 temp = readl(sport->port.membase + USR2);
590 writel(temp | USR2_ORE, sport->port.membase + USR2);
591
592 temp = readl(sport->port.membase + UCR4);
593 temp |= UCR4_OREN;
594 writel(temp, sport->port.membase + UCR4);
595
596 if (!sport->dma_is_enabled) {
597 temp = readl(sport->port.membase + UCR1);
598 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
599 }
600
601 if (USE_IRDA(sport)) {
602 temp = readl(sport->port.membase + UCR1);
603 temp |= UCR1_TRDYEN;
604 writel(temp, sport->port.membase + UCR1);
605
606 temp = readl(sport->port.membase + UCR4);
607 temp |= UCR4_TCEN;
608 writel(temp, sport->port.membase + UCR4);
609 }
610
611 if (sport->dma_is_enabled) {
612 /*
613 * We may in the interrupt context, so arise a work_struct to
614 * do the real job.
615 */
616 schedule_work(&sport->tsk_dma_tx);
617 return;
618 }
619
620 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
621 imx_transmit_buffer(sport);
622 }
623
624 static irqreturn_t imx_rtsint(int irq, void *dev_id)
625 {
626 struct imx_port *sport = dev_id;
627 unsigned int val;
628 unsigned long flags;
629
630 spin_lock_irqsave(&sport->port.lock, flags);
631
632 writel(USR1_RTSD, sport->port.membase + USR1);
633 val = readl(sport->port.membase + USR1) & USR1_RTSS;
634 uart_handle_cts_change(&sport->port, !!val);
635 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
636
637 spin_unlock_irqrestore(&sport->port.lock, flags);
638 return IRQ_HANDLED;
639 }
640
641 static irqreturn_t imx_txint(int irq, void *dev_id)
642 {
643 struct imx_port *sport = dev_id;
644 struct circ_buf *xmit = &sport->port.state->xmit;
645 unsigned long flags;
646
647 spin_lock_irqsave(&sport->port.lock, flags);
648 if (sport->port.x_char) {
649 /* Send next char */
650 writel(sport->port.x_char, sport->port.membase + URTX0);
651 goto out;
652 }
653
654 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
655 imx_stop_tx(&sport->port);
656 goto out;
657 }
658
659 imx_transmit_buffer(sport);
660
661 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
662 uart_write_wakeup(&sport->port);
663
664 out:
665 spin_unlock_irqrestore(&sport->port.lock, flags);
666 return IRQ_HANDLED;
667 }
668
669 static irqreturn_t imx_rxint(int irq, void *dev_id)
670 {
671 struct imx_port *sport = dev_id;
672 unsigned int rx, flg, ignored = 0;
673 struct tty_port *port = &sport->port.state->port;
674 unsigned long flags, temp;
675
676 spin_lock_irqsave(&sport->port.lock, flags);
677
678 while (readl(sport->port.membase + USR2) & USR2_RDR) {
679 flg = TTY_NORMAL;
680 sport->port.icount.rx++;
681
682 rx = readl(sport->port.membase + URXD0);
683
684 temp = readl(sport->port.membase + USR2);
685 if (temp & USR2_BRCD) {
686 writel(USR2_BRCD, sport->port.membase + USR2);
687 if (uart_handle_break(&sport->port))
688 continue;
689 }
690
691 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
692 continue;
693
694 if (unlikely(rx & URXD_ERR)) {
695 if (rx & URXD_BRK)
696 sport->port.icount.brk++;
697 else if (rx & URXD_PRERR)
698 sport->port.icount.parity++;
699 else if (rx & URXD_FRMERR)
700 sport->port.icount.frame++;
701 if (rx & URXD_OVRRUN)
702 sport->port.icount.overrun++;
703
704 if (rx & sport->port.ignore_status_mask) {
705 if (++ignored > 100)
706 goto out;
707 continue;
708 }
709
710 rx &= sport->port.read_status_mask;
711
712 if (rx & URXD_BRK)
713 flg = TTY_BREAK;
714 else if (rx & URXD_PRERR)
715 flg = TTY_PARITY;
716 else if (rx & URXD_FRMERR)
717 flg = TTY_FRAME;
718 if (rx & URXD_OVRRUN)
719 flg = TTY_OVERRUN;
720
721 #ifdef SUPPORT_SYSRQ
722 sport->port.sysrq = 0;
723 #endif
724 }
725
726 tty_insert_flip_char(port, rx, flg);
727 }
728
729 out:
730 spin_unlock_irqrestore(&sport->port.lock, flags);
731 tty_flip_buffer_push(port);
732 return IRQ_HANDLED;
733 }
734
735 /*
736 * If the RXFIFO is filled with some data, and then we
737 * arise a DMA operation to receive them.
738 */
739 static void imx_dma_rxint(struct imx_port *sport)
740 {
741 unsigned long temp;
742
743 temp = readl(sport->port.membase + USR2);
744 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
745 sport->dma_is_rxing = 1;
746
747 /* disable the `Recerver Ready Interrrupt` */
748 temp = readl(sport->port.membase + UCR1);
749 temp &= ~(UCR1_RRDYEN);
750 writel(temp, sport->port.membase + UCR1);
751
752 /* tell the DMA to receive the data. */
753 schedule_work(&sport->tsk_dma_rx);
754 }
755 }
756
757 static irqreturn_t imx_int(int irq, void *dev_id)
758 {
759 struct imx_port *sport = dev_id;
760 unsigned int sts;
761 unsigned int sts2;
762
763 sts = readl(sport->port.membase + USR1);
764
765 if (sts & USR1_RRDY) {
766 if (sport->dma_is_enabled)
767 imx_dma_rxint(sport);
768 else
769 imx_rxint(irq, dev_id);
770 }
771
772 if (sts & USR1_TRDY &&
773 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
774 imx_txint(irq, dev_id);
775
776 if (sts & USR1_RTSD)
777 imx_rtsint(irq, dev_id);
778
779 if (sts & USR1_AWAKE)
780 writel(USR1_AWAKE, sport->port.membase + USR1);
781
782 sts2 = readl(sport->port.membase + USR2);
783 if (sts2 & USR2_ORE) {
784 dev_err(sport->port.dev, "Rx FIFO overrun\n");
785 sport->port.icount.overrun++;
786 writel(sts2 | USR2_ORE, sport->port.membase + USR2);
787 }
788
789 return IRQ_HANDLED;
790 }
791
792 /*
793 * Return TIOCSER_TEMT when transmitter is not busy.
794 */
795 static unsigned int imx_tx_empty(struct uart_port *port)
796 {
797 struct imx_port *sport = (struct imx_port *)port;
798 unsigned int ret;
799
800 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
801
802 /* If the TX DMA is working, return 0. */
803 if (sport->dma_is_enabled && sport->dma_is_txing)
804 ret = 0;
805
806 return ret;
807 }
808
809 /*
810 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
811 */
812 static unsigned int imx_get_mctrl(struct uart_port *port)
813 {
814 struct imx_port *sport = (struct imx_port *)port;
815 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
816
817 if (readl(sport->port.membase + USR1) & USR1_RTSS)
818 tmp |= TIOCM_CTS;
819
820 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
821 tmp |= TIOCM_RTS;
822
823 return tmp;
824 }
825
826 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
827 {
828 struct imx_port *sport = (struct imx_port *)port;
829 unsigned long temp;
830
831 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
832
833 if (mctrl & TIOCM_RTS)
834 if (!sport->dma_is_enabled)
835 temp |= UCR2_CTS;
836
837 writel(temp, sport->port.membase + UCR2);
838 }
839
840 /*
841 * Interrupts always disabled.
842 */
843 static void imx_break_ctl(struct uart_port *port, int break_state)
844 {
845 struct imx_port *sport = (struct imx_port *)port;
846 unsigned long flags, temp;
847
848 spin_lock_irqsave(&sport->port.lock, flags);
849
850 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
851
852 if (break_state != 0)
853 temp |= UCR1_SNDBRK;
854
855 writel(temp, sport->port.membase + UCR1);
856
857 spin_unlock_irqrestore(&sport->port.lock, flags);
858 }
859
860 #define TXTL 2 /* reset default */
861 #define RXTL 1 /* reset default */
862
863 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
864 {
865 unsigned int val;
866
867 /* set receiver / transmitter trigger level */
868 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
869 val |= TXTL << UFCR_TXTL_SHF | RXTL;
870 writel(val, sport->port.membase + UFCR);
871 return 0;
872 }
873
874 #define RX_BUF_SIZE (PAGE_SIZE)
875 static int start_rx_dma(struct imx_port *sport);
876 static void dma_rx_work(struct work_struct *w)
877 {
878 struct imx_port *sport = container_of(w, struct imx_port, tsk_dma_rx);
879 struct tty_port *port = &sport->port.state->port;
880
881 if (sport->rx_bytes) {
882 tty_insert_flip_string(port, sport->rx_buf, sport->rx_bytes);
883 tty_flip_buffer_push(port);
884 sport->rx_bytes = 0;
885 }
886
887 if (sport->dma_is_rxing)
888 start_rx_dma(sport);
889 }
890
891 static void imx_rx_dma_done(struct imx_port *sport)
892 {
893 unsigned long temp;
894
895 /* Enable this interrupt when the RXFIFO is empty. */
896 temp = readl(sport->port.membase + UCR1);
897 temp |= UCR1_RRDYEN;
898 writel(temp, sport->port.membase + UCR1);
899
900 sport->dma_is_rxing = 0;
901
902 /* Is the shutdown waiting for us? */
903 if (waitqueue_active(&sport->dma_wait))
904 wake_up(&sport->dma_wait);
905 }
906
907 /*
908 * There are three kinds of RX DMA interrupts(such as in the MX6Q):
909 * [1] the RX DMA buffer is full.
910 * [2] the Aging timer expires(wait for 8 bytes long)
911 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
912 *
913 * The [2] is trigger when a character was been sitting in the FIFO
914 * meanwhile [3] can wait for 32 bytes long when the RX line is
915 * on IDLE state and RxFIFO is empty.
916 */
917 static void dma_rx_callback(void *data)
918 {
919 struct imx_port *sport = data;
920 struct dma_chan *chan = sport->dma_chan_rx;
921 struct scatterlist *sgl = &sport->rx_sgl;
922 struct dma_tx_state state;
923 enum dma_status status;
924 unsigned int count;
925
926 /* unmap it first */
927 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
928
929 status = chan->device->device_tx_status(chan, (dma_cookie_t)0, &state);
930 count = RX_BUF_SIZE - state.residue;
931 dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
932
933 if (count) {
934 sport->rx_bytes = count;
935 schedule_work(&sport->tsk_dma_rx);
936 } else
937 imx_rx_dma_done(sport);
938 }
939
940 static int start_rx_dma(struct imx_port *sport)
941 {
942 struct scatterlist *sgl = &sport->rx_sgl;
943 struct dma_chan *chan = sport->dma_chan_rx;
944 struct device *dev = sport->port.dev;
945 struct dma_async_tx_descriptor *desc;
946 int ret;
947
948 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
949 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
950 if (ret == 0) {
951 dev_err(dev, "DMA mapping error for RX.\n");
952 return -EINVAL;
953 }
954 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
955 DMA_PREP_INTERRUPT);
956 if (!desc) {
957 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
958 return -EINVAL;
959 }
960 desc->callback = dma_rx_callback;
961 desc->callback_param = sport;
962
963 dev_dbg(dev, "RX: prepare for the DMA.\n");
964 dmaengine_submit(desc);
965 dma_async_issue_pending(chan);
966 return 0;
967 }
968
969 static void imx_uart_dma_exit(struct imx_port *sport)
970 {
971 if (sport->dma_chan_rx) {
972 dma_release_channel(sport->dma_chan_rx);
973 sport->dma_chan_rx = NULL;
974
975 kfree(sport->rx_buf);
976 sport->rx_buf = NULL;
977 }
978
979 if (sport->dma_chan_tx) {
980 dma_release_channel(sport->dma_chan_tx);
981 sport->dma_chan_tx = NULL;
982 }
983
984 sport->dma_is_inited = 0;
985 }
986
987 static int imx_uart_dma_init(struct imx_port *sport)
988 {
989 struct dma_slave_config slave_config = {};
990 struct device *dev = sport->port.dev;
991 int ret;
992
993 /* Prepare for RX : */
994 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
995 if (!sport->dma_chan_rx) {
996 dev_dbg(dev, "cannot get the DMA channel.\n");
997 ret = -EINVAL;
998 goto err;
999 }
1000
1001 slave_config.direction = DMA_DEV_TO_MEM;
1002 slave_config.src_addr = sport->port.mapbase + URXD0;
1003 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1004 slave_config.src_maxburst = RXTL;
1005 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1006 if (ret) {
1007 dev_err(dev, "error in RX dma configuration.\n");
1008 goto err;
1009 }
1010
1011 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1012 if (!sport->rx_buf) {
1013 dev_err(dev, "cannot alloc DMA buffer.\n");
1014 ret = -ENOMEM;
1015 goto err;
1016 }
1017 sport->rx_bytes = 0;
1018
1019 /* Prepare for TX : */
1020 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1021 if (!sport->dma_chan_tx) {
1022 dev_err(dev, "cannot get the TX DMA channel!\n");
1023 ret = -EINVAL;
1024 goto err;
1025 }
1026
1027 slave_config.direction = DMA_MEM_TO_DEV;
1028 slave_config.dst_addr = sport->port.mapbase + URTX0;
1029 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1030 slave_config.dst_maxburst = TXTL;
1031 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1032 if (ret) {
1033 dev_err(dev, "error in TX dma configuration.");
1034 goto err;
1035 }
1036
1037 sport->dma_is_inited = 1;
1038
1039 return 0;
1040 err:
1041 imx_uart_dma_exit(sport);
1042 return ret;
1043 }
1044
1045 static void imx_enable_dma(struct imx_port *sport)
1046 {
1047 unsigned long temp;
1048 struct tty_port *port = &sport->port.state->port;
1049
1050 port->low_latency = 1;
1051 INIT_WORK(&sport->tsk_dma_tx, dma_tx_work);
1052 INIT_WORK(&sport->tsk_dma_rx, dma_rx_work);
1053 init_waitqueue_head(&sport->dma_wait);
1054
1055 /* set UCR1 */
1056 temp = readl(sport->port.membase + UCR1);
1057 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
1058 /* wait for 32 idle frames for IDDMA interrupt */
1059 UCR1_ICD_REG(3);
1060 writel(temp, sport->port.membase + UCR1);
1061
1062 /* set UCR4 */
1063 temp = readl(sport->port.membase + UCR4);
1064 temp |= UCR4_IDDMAEN;
1065 writel(temp, sport->port.membase + UCR4);
1066
1067 sport->dma_is_enabled = 1;
1068 }
1069
1070 static void imx_disable_dma(struct imx_port *sport)
1071 {
1072 unsigned long temp;
1073 struct tty_port *port = &sport->port.state->port;
1074
1075 /* clear UCR1 */
1076 temp = readl(sport->port.membase + UCR1);
1077 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1078 writel(temp, sport->port.membase + UCR1);
1079
1080 /* clear UCR2 */
1081 temp = readl(sport->port.membase + UCR2);
1082 temp &= ~(UCR2_CTSC | UCR2_CTS);
1083 writel(temp, sport->port.membase + UCR2);
1084
1085 /* clear UCR4 */
1086 temp = readl(sport->port.membase + UCR4);
1087 temp &= ~UCR4_IDDMAEN;
1088 writel(temp, sport->port.membase + UCR4);
1089
1090 sport->dma_is_enabled = 0;
1091 port->low_latency = 0;
1092 }
1093
1094 /* half the RX buffer size */
1095 #define CTSTL 16
1096
1097 static int imx_startup(struct uart_port *port)
1098 {
1099 struct imx_port *sport = (struct imx_port *)port;
1100 int retval;
1101 unsigned long flags, temp;
1102
1103 retval = clk_prepare_enable(sport->clk_per);
1104 if (retval)
1105 goto error_out1;
1106 retval = clk_prepare_enable(sport->clk_ipg);
1107 if (retval) {
1108 clk_disable_unprepare(sport->clk_per);
1109 goto error_out1;
1110 }
1111
1112 imx_setup_ufcr(sport, 0);
1113
1114 /* disable the DREN bit (Data Ready interrupt enable) before
1115 * requesting IRQs
1116 */
1117 temp = readl(sport->port.membase + UCR4);
1118
1119 if (USE_IRDA(sport))
1120 temp |= UCR4_IRSC;
1121
1122 /* set the trigger level for CTS */
1123 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1124 temp |= CTSTL << UCR4_CTSTL_SHF;
1125
1126 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1127
1128 if (USE_IRDA(sport)) {
1129 /* reset fifo's and state machines */
1130 int i = 100;
1131 temp = readl(sport->port.membase + UCR2);
1132 temp &= ~UCR2_SRST;
1133 writel(temp, sport->port.membase + UCR2);
1134 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
1135 (--i > 0)) {
1136 udelay(1);
1137 }
1138 }
1139
1140 /*
1141 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
1142 * chips only have one interrupt.
1143 */
1144 if (sport->txirq > 0) {
1145 retval = request_irq(sport->rxirq, imx_rxint, 0,
1146 DRIVER_NAME, sport);
1147 if (retval)
1148 goto error_out1;
1149
1150 retval = request_irq(sport->txirq, imx_txint, 0,
1151 DRIVER_NAME, sport);
1152 if (retval)
1153 goto error_out2;
1154
1155 /* do not use RTS IRQ on IrDA */
1156 if (!USE_IRDA(sport)) {
1157 retval = request_irq(sport->rtsirq, imx_rtsint, 0,
1158 DRIVER_NAME, sport);
1159 if (retval)
1160 goto error_out3;
1161 }
1162 } else {
1163 retval = request_irq(sport->port.irq, imx_int, 0,
1164 DRIVER_NAME, sport);
1165 if (retval) {
1166 free_irq(sport->port.irq, sport);
1167 goto error_out1;
1168 }
1169 }
1170
1171 spin_lock_irqsave(&sport->port.lock, flags);
1172 /*
1173 * Finally, clear and enable interrupts
1174 */
1175 writel(USR1_RTSD, sport->port.membase + USR1);
1176
1177 temp = readl(sport->port.membase + UCR1);
1178 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
1179
1180 if (USE_IRDA(sport)) {
1181 temp |= UCR1_IREN;
1182 temp &= ~(UCR1_RTSDEN);
1183 }
1184
1185 writel(temp, sport->port.membase + UCR1);
1186
1187 temp = readl(sport->port.membase + UCR2);
1188 temp |= (UCR2_RXEN | UCR2_TXEN);
1189 if (!sport->have_rtscts)
1190 temp |= UCR2_IRTS;
1191 writel(temp, sport->port.membase + UCR2);
1192
1193 if (USE_IRDA(sport)) {
1194 /* clear RX-FIFO */
1195 int i = 64;
1196 while ((--i > 0) &&
1197 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
1198 barrier();
1199 }
1200 }
1201
1202 if (!is_imx1_uart(sport)) {
1203 temp = readl(sport->port.membase + UCR3);
1204 temp |= IMX21_UCR3_RXDMUXSEL;
1205 writel(temp, sport->port.membase + UCR3);
1206 }
1207
1208 if (USE_IRDA(sport)) {
1209 temp = readl(sport->port.membase + UCR4);
1210 if (sport->irda_inv_rx)
1211 temp |= UCR4_INVR;
1212 else
1213 temp &= ~(UCR4_INVR);
1214 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
1215
1216 temp = readl(sport->port.membase + UCR3);
1217 if (sport->irda_inv_tx)
1218 temp |= UCR3_INVT;
1219 else
1220 temp &= ~(UCR3_INVT);
1221 writel(temp, sport->port.membase + UCR3);
1222 }
1223
1224 /*
1225 * Enable modem status interrupts
1226 */
1227 imx_enable_ms(&sport->port);
1228 spin_unlock_irqrestore(&sport->port.lock, flags);
1229
1230 if (USE_IRDA(sport)) {
1231 struct imxuart_platform_data *pdata;
1232 pdata = dev_get_platdata(sport->port.dev);
1233 sport->irda_inv_rx = pdata->irda_inv_rx;
1234 sport->irda_inv_tx = pdata->irda_inv_tx;
1235 sport->trcv_delay = pdata->transceiver_delay;
1236 if (pdata->irda_enable)
1237 pdata->irda_enable(1);
1238 }
1239
1240 return 0;
1241
1242 error_out3:
1243 if (sport->txirq)
1244 free_irq(sport->txirq, sport);
1245 error_out2:
1246 if (sport->rxirq)
1247 free_irq(sport->rxirq, sport);
1248 error_out1:
1249 return retval;
1250 }
1251
1252 static void imx_shutdown(struct uart_port *port)
1253 {
1254 struct imx_port *sport = (struct imx_port *)port;
1255 unsigned long temp;
1256 unsigned long flags;
1257
1258 if (sport->dma_is_enabled) {
1259 /* We have to wait for the DMA to finish. */
1260 wait_event(sport->dma_wait,
1261 !sport->dma_is_rxing && !sport->dma_is_txing);
1262 imx_stop_rx(port);
1263 imx_disable_dma(sport);
1264 imx_uart_dma_exit(sport);
1265 }
1266
1267 spin_lock_irqsave(&sport->port.lock, flags);
1268 temp = readl(sport->port.membase + UCR2);
1269 temp &= ~(UCR2_TXEN);
1270 writel(temp, sport->port.membase + UCR2);
1271 spin_unlock_irqrestore(&sport->port.lock, flags);
1272
1273 if (USE_IRDA(sport)) {
1274 struct imxuart_platform_data *pdata;
1275 pdata = dev_get_platdata(sport->port.dev);
1276 if (pdata->irda_enable)
1277 pdata->irda_enable(0);
1278 }
1279
1280 /*
1281 * Stop our timer.
1282 */
1283 del_timer_sync(&sport->timer);
1284
1285 /*
1286 * Free the interrupts
1287 */
1288 if (sport->txirq > 0) {
1289 if (!USE_IRDA(sport))
1290 free_irq(sport->rtsirq, sport);
1291 free_irq(sport->txirq, sport);
1292 free_irq(sport->rxirq, sport);
1293 } else
1294 free_irq(sport->port.irq, sport);
1295
1296 /*
1297 * Disable all interrupts, port and break condition.
1298 */
1299
1300 spin_lock_irqsave(&sport->port.lock, flags);
1301 temp = readl(sport->port.membase + UCR1);
1302 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1303 if (USE_IRDA(sport))
1304 temp &= ~(UCR1_IREN);
1305
1306 writel(temp, sport->port.membase + UCR1);
1307 spin_unlock_irqrestore(&sport->port.lock, flags);
1308
1309 clk_disable_unprepare(sport->clk_per);
1310 clk_disable_unprepare(sport->clk_ipg);
1311 }
1312
1313 static void imx_flush_buffer(struct uart_port *port)
1314 {
1315 struct imx_port *sport = (struct imx_port *)port;
1316
1317 if (sport->dma_is_enabled) {
1318 sport->tx_bytes = 0;
1319 dmaengine_terminate_all(sport->dma_chan_tx);
1320 }
1321 }
1322
1323 static void
1324 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1325 struct ktermios *old)
1326 {
1327 struct imx_port *sport = (struct imx_port *)port;
1328 unsigned long flags;
1329 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
1330 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1331 unsigned int div, ufcr;
1332 unsigned long num, denom;
1333 uint64_t tdiv64;
1334
1335 /*
1336 * If we don't support modem control lines, don't allow
1337 * these to be set.
1338 */
1339 if (0) {
1340 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
1341 termios->c_cflag |= CLOCAL;
1342 }
1343
1344 /*
1345 * We only support CS7 and CS8.
1346 */
1347 while ((termios->c_cflag & CSIZE) != CS7 &&
1348 (termios->c_cflag & CSIZE) != CS8) {
1349 termios->c_cflag &= ~CSIZE;
1350 termios->c_cflag |= old_csize;
1351 old_csize = CS8;
1352 }
1353
1354 if ((termios->c_cflag & CSIZE) == CS8)
1355 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1356 else
1357 ucr2 = UCR2_SRST | UCR2_IRTS;
1358
1359 if (termios->c_cflag & CRTSCTS) {
1360 if (sport->have_rtscts) {
1361 ucr2 &= ~UCR2_IRTS;
1362 ucr2 |= UCR2_CTSC;
1363
1364 /* Can we enable the DMA support? */
1365 if (is_imx6q_uart(sport) && !uart_console(port)
1366 && !sport->dma_is_inited)
1367 imx_uart_dma_init(sport);
1368 } else {
1369 termios->c_cflag &= ~CRTSCTS;
1370 }
1371 }
1372
1373 if (termios->c_cflag & CSTOPB)
1374 ucr2 |= UCR2_STPB;
1375 if (termios->c_cflag & PARENB) {
1376 ucr2 |= UCR2_PREN;
1377 if (termios->c_cflag & PARODD)
1378 ucr2 |= UCR2_PROE;
1379 }
1380
1381 del_timer_sync(&sport->timer);
1382
1383 /*
1384 * Ask the core to calculate the divisor for us.
1385 */
1386 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1387 quot = uart_get_divisor(port, baud);
1388
1389 spin_lock_irqsave(&sport->port.lock, flags);
1390
1391 sport->port.read_status_mask = 0;
1392 if (termios->c_iflag & INPCK)
1393 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1394 if (termios->c_iflag & (BRKINT | PARMRK))
1395 sport->port.read_status_mask |= URXD_BRK;
1396
1397 /*
1398 * Characters to ignore
1399 */
1400 sport->port.ignore_status_mask = 0;
1401 if (termios->c_iflag & IGNPAR)
1402 sport->port.ignore_status_mask |= URXD_PRERR;
1403 if (termios->c_iflag & IGNBRK) {
1404 sport->port.ignore_status_mask |= URXD_BRK;
1405 /*
1406 * If we're ignoring parity and break indicators,
1407 * ignore overruns too (for real raw support).
1408 */
1409 if (termios->c_iflag & IGNPAR)
1410 sport->port.ignore_status_mask |= URXD_OVRRUN;
1411 }
1412
1413 /*
1414 * Update the per-port timeout.
1415 */
1416 uart_update_timeout(port, termios->c_cflag, baud);
1417
1418 /*
1419 * disable interrupts and drain transmitter
1420 */
1421 old_ucr1 = readl(sport->port.membase + UCR1);
1422 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1423 sport->port.membase + UCR1);
1424
1425 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1426 barrier();
1427
1428 /* then, disable everything */
1429 old_txrxen = readl(sport->port.membase + UCR2);
1430 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
1431 sport->port.membase + UCR2);
1432 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1433
1434 if (USE_IRDA(sport)) {
1435 /*
1436 * use maximum available submodule frequency to
1437 * avoid missing short pulses due to low sampling rate
1438 */
1439 div = 1;
1440 } else {
1441 /* custom-baudrate handling */
1442 div = sport->port.uartclk / (baud * 16);
1443 if (baud == 38400 && quot != div)
1444 baud = sport->port.uartclk / (quot * 16);
1445
1446 div = sport->port.uartclk / (baud * 16);
1447 if (div > 7)
1448 div = 7;
1449 if (!div)
1450 div = 1;
1451 }
1452
1453 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1454 1 << 16, 1 << 16, &num, &denom);
1455
1456 tdiv64 = sport->port.uartclk;
1457 tdiv64 *= num;
1458 do_div(tdiv64, denom * 16 * div);
1459 tty_termios_encode_baud_rate(termios,
1460 (speed_t)tdiv64, (speed_t)tdiv64);
1461
1462 num -= 1;
1463 denom -= 1;
1464
1465 ufcr = readl(sport->port.membase + UFCR);
1466 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1467 if (sport->dte_mode)
1468 ufcr |= UFCR_DCEDTE;
1469 writel(ufcr, sport->port.membase + UFCR);
1470
1471 writel(num, sport->port.membase + UBIR);
1472 writel(denom, sport->port.membase + UBMR);
1473
1474 if (!is_imx1_uart(sport))
1475 writel(sport->port.uartclk / div / 1000,
1476 sport->port.membase + IMX21_ONEMS);
1477
1478 writel(old_ucr1, sport->port.membase + UCR1);
1479
1480 /* set the parity, stop bits and data size */
1481 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1482
1483 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1484 imx_enable_ms(&sport->port);
1485
1486 if (sport->dma_is_inited && !sport->dma_is_enabled)
1487 imx_enable_dma(sport);
1488 spin_unlock_irqrestore(&sport->port.lock, flags);
1489 }
1490
1491 static const char *imx_type(struct uart_port *port)
1492 {
1493 struct imx_port *sport = (struct imx_port *)port;
1494
1495 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1496 }
1497
1498 /*
1499 * Release the memory region(s) being used by 'port'.
1500 */
1501 static void imx_release_port(struct uart_port *port)
1502 {
1503 struct platform_device *pdev = to_platform_device(port->dev);
1504 struct resource *mmres;
1505
1506 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1507 release_mem_region(mmres->start, resource_size(mmres));
1508 }
1509
1510 /*
1511 * Request the memory region(s) being used by 'port'.
1512 */
1513 static int imx_request_port(struct uart_port *port)
1514 {
1515 struct platform_device *pdev = to_platform_device(port->dev);
1516 struct resource *mmres;
1517 void *ret;
1518
1519 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1520 if (!mmres)
1521 return -ENODEV;
1522
1523 ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart");
1524
1525 return ret ? 0 : -EBUSY;
1526 }
1527
1528 /*
1529 * Configure/autoconfigure the port.
1530 */
1531 static void imx_config_port(struct uart_port *port, int flags)
1532 {
1533 struct imx_port *sport = (struct imx_port *)port;
1534
1535 if (flags & UART_CONFIG_TYPE &&
1536 imx_request_port(&sport->port) == 0)
1537 sport->port.type = PORT_IMX;
1538 }
1539
1540 /*
1541 * Verify the new serial_struct (for TIOCSSERIAL).
1542 * The only change we allow are to the flags and type, and
1543 * even then only between PORT_IMX and PORT_UNKNOWN
1544 */
1545 static int
1546 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1547 {
1548 struct imx_port *sport = (struct imx_port *)port;
1549 int ret = 0;
1550
1551 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1552 ret = -EINVAL;
1553 if (sport->port.irq != ser->irq)
1554 ret = -EINVAL;
1555 if (ser->io_type != UPIO_MEM)
1556 ret = -EINVAL;
1557 if (sport->port.uartclk / 16 != ser->baud_base)
1558 ret = -EINVAL;
1559 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1560 ret = -EINVAL;
1561 if (sport->port.iobase != ser->port)
1562 ret = -EINVAL;
1563 if (ser->hub6 != 0)
1564 ret = -EINVAL;
1565 return ret;
1566 }
1567
1568 #if defined(CONFIG_CONSOLE_POLL)
1569 static int imx_poll_get_char(struct uart_port *port)
1570 {
1571 struct imx_port_ucrs old_ucr;
1572 unsigned int status;
1573 unsigned char c;
1574
1575 /* save control registers */
1576 imx_port_ucrs_save(port, &old_ucr);
1577
1578 /* disable interrupts */
1579 writel(UCR1_UARTEN, port->membase + UCR1);
1580 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1581 port->membase + UCR2);
1582 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1583 port->membase + UCR3);
1584
1585 /* poll */
1586 do {
1587 status = readl(port->membase + USR2);
1588 } while (~status & USR2_RDR);
1589
1590 /* read */
1591 c = readl(port->membase + URXD0);
1592
1593 /* restore control registers */
1594 imx_port_ucrs_restore(port, &old_ucr);
1595
1596 return c;
1597 }
1598
1599 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1600 {
1601 struct imx_port_ucrs old_ucr;
1602 unsigned int status;
1603
1604 /* save control registers */
1605 imx_port_ucrs_save(port, &old_ucr);
1606
1607 /* disable interrupts */
1608 writel(UCR1_UARTEN, port->membase + UCR1);
1609 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1610 port->membase + UCR2);
1611 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1612 port->membase + UCR3);
1613
1614 /* drain */
1615 do {
1616 status = readl(port->membase + USR1);
1617 } while (~status & USR1_TRDY);
1618
1619 /* write */
1620 writel(c, port->membase + URTX0);
1621
1622 /* flush */
1623 do {
1624 status = readl(port->membase + USR2);
1625 } while (~status & USR2_TXDC);
1626
1627 /* restore control registers */
1628 imx_port_ucrs_restore(port, &old_ucr);
1629 }
1630 #endif
1631
1632 static struct uart_ops imx_pops = {
1633 .tx_empty = imx_tx_empty,
1634 .set_mctrl = imx_set_mctrl,
1635 .get_mctrl = imx_get_mctrl,
1636 .stop_tx = imx_stop_tx,
1637 .start_tx = imx_start_tx,
1638 .stop_rx = imx_stop_rx,
1639 .enable_ms = imx_enable_ms,
1640 .break_ctl = imx_break_ctl,
1641 .startup = imx_startup,
1642 .shutdown = imx_shutdown,
1643 .flush_buffer = imx_flush_buffer,
1644 .set_termios = imx_set_termios,
1645 .type = imx_type,
1646 .release_port = imx_release_port,
1647 .request_port = imx_request_port,
1648 .config_port = imx_config_port,
1649 .verify_port = imx_verify_port,
1650 #if defined(CONFIG_CONSOLE_POLL)
1651 .poll_get_char = imx_poll_get_char,
1652 .poll_put_char = imx_poll_put_char,
1653 #endif
1654 };
1655
1656 static struct imx_port *imx_ports[UART_NR];
1657
1658 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1659 static void imx_console_putchar(struct uart_port *port, int ch)
1660 {
1661 struct imx_port *sport = (struct imx_port *)port;
1662
1663 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1664 barrier();
1665
1666 writel(ch, sport->port.membase + URTX0);
1667 }
1668
1669 /*
1670 * Interrupts are disabled on entering
1671 */
1672 static void
1673 imx_console_write(struct console *co, const char *s, unsigned int count)
1674 {
1675 struct imx_port *sport = imx_ports[co->index];
1676 struct imx_port_ucrs old_ucr;
1677 unsigned int ucr1;
1678 unsigned long flags = 0;
1679 int locked = 1;
1680 int retval;
1681
1682 retval = clk_enable(sport->clk_per);
1683 if (retval)
1684 return;
1685 retval = clk_enable(sport->clk_ipg);
1686 if (retval) {
1687 clk_disable(sport->clk_per);
1688 return;
1689 }
1690
1691 if (sport->port.sysrq)
1692 locked = 0;
1693 else if (oops_in_progress)
1694 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1695 else
1696 spin_lock_irqsave(&sport->port.lock, flags);
1697
1698 /*
1699 * First, save UCR1/2/3 and then disable interrupts
1700 */
1701 imx_port_ucrs_save(&sport->port, &old_ucr);
1702 ucr1 = old_ucr.ucr1;
1703
1704 if (is_imx1_uart(sport))
1705 ucr1 |= IMX1_UCR1_UARTCLKEN;
1706 ucr1 |= UCR1_UARTEN;
1707 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1708
1709 writel(ucr1, sport->port.membase + UCR1);
1710
1711 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1712
1713 uart_console_write(&sport->port, s, count, imx_console_putchar);
1714
1715 /*
1716 * Finally, wait for transmitter to become empty
1717 * and restore UCR1/2/3
1718 */
1719 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1720
1721 imx_port_ucrs_restore(&sport->port, &old_ucr);
1722
1723 if (locked)
1724 spin_unlock_irqrestore(&sport->port.lock, flags);
1725
1726 clk_disable(sport->clk_ipg);
1727 clk_disable(sport->clk_per);
1728 }
1729
1730 /*
1731 * If the port was already initialised (eg, by a boot loader),
1732 * try to determine the current setup.
1733 */
1734 static void __init
1735 imx_console_get_options(struct imx_port *sport, int *baud,
1736 int *parity, int *bits)
1737 {
1738
1739 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1740 /* ok, the port was enabled */
1741 unsigned int ucr2, ubir, ubmr, uartclk;
1742 unsigned int baud_raw;
1743 unsigned int ucfr_rfdiv;
1744
1745 ucr2 = readl(sport->port.membase + UCR2);
1746
1747 *parity = 'n';
1748 if (ucr2 & UCR2_PREN) {
1749 if (ucr2 & UCR2_PROE)
1750 *parity = 'o';
1751 else
1752 *parity = 'e';
1753 }
1754
1755 if (ucr2 & UCR2_WS)
1756 *bits = 8;
1757 else
1758 *bits = 7;
1759
1760 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1761 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1762
1763 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1764 if (ucfr_rfdiv == 6)
1765 ucfr_rfdiv = 7;
1766 else
1767 ucfr_rfdiv = 6 - ucfr_rfdiv;
1768
1769 uartclk = clk_get_rate(sport->clk_per);
1770 uartclk /= ucfr_rfdiv;
1771
1772 { /*
1773 * The next code provides exact computation of
1774 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1775 * without need of float support or long long division,
1776 * which would be required to prevent 32bit arithmetic overflow
1777 */
1778 unsigned int mul = ubir + 1;
1779 unsigned int div = 16 * (ubmr + 1);
1780 unsigned int rem = uartclk % div;
1781
1782 baud_raw = (uartclk / div) * mul;
1783 baud_raw += (rem * mul + div / 2) / div;
1784 *baud = (baud_raw + 50) / 100 * 100;
1785 }
1786
1787 if (*baud != baud_raw)
1788 pr_info("Console IMX rounded baud rate from %d to %d\n",
1789 baud_raw, *baud);
1790 }
1791 }
1792
1793 static int __init
1794 imx_console_setup(struct console *co, char *options)
1795 {
1796 struct imx_port *sport;
1797 int baud = 9600;
1798 int bits = 8;
1799 int parity = 'n';
1800 int flow = 'n';
1801 int retval;
1802
1803 /*
1804 * Check whether an invalid uart number has been specified, and
1805 * if so, search for the first available port that does have
1806 * console support.
1807 */
1808 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1809 co->index = 0;
1810 sport = imx_ports[co->index];
1811 if (sport == NULL)
1812 return -ENODEV;
1813
1814 /* For setting the registers, we only need to enable the ipg clock. */
1815 retval = clk_prepare_enable(sport->clk_ipg);
1816 if (retval)
1817 goto error_console;
1818
1819 if (options)
1820 uart_parse_options(options, &baud, &parity, &bits, &flow);
1821 else
1822 imx_console_get_options(sport, &baud, &parity, &bits);
1823
1824 imx_setup_ufcr(sport, 0);
1825
1826 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1827
1828 clk_disable(sport->clk_ipg);
1829 if (retval) {
1830 clk_unprepare(sport->clk_ipg);
1831 goto error_console;
1832 }
1833
1834 retval = clk_prepare(sport->clk_per);
1835 if (retval)
1836 clk_disable_unprepare(sport->clk_ipg);
1837
1838 error_console:
1839 return retval;
1840 }
1841
1842 static struct uart_driver imx_reg;
1843 static struct console imx_console = {
1844 .name = DEV_NAME,
1845 .write = imx_console_write,
1846 .device = uart_console_device,
1847 .setup = imx_console_setup,
1848 .flags = CON_PRINTBUFFER,
1849 .index = -1,
1850 .data = &imx_reg,
1851 };
1852
1853 #define IMX_CONSOLE &imx_console
1854 #else
1855 #define IMX_CONSOLE NULL
1856 #endif
1857
1858 static struct uart_driver imx_reg = {
1859 .owner = THIS_MODULE,
1860 .driver_name = DRIVER_NAME,
1861 .dev_name = DEV_NAME,
1862 .major = SERIAL_IMX_MAJOR,
1863 .minor = MINOR_START,
1864 .nr = ARRAY_SIZE(imx_ports),
1865 .cons = IMX_CONSOLE,
1866 };
1867
1868 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1869 {
1870 struct imx_port *sport = platform_get_drvdata(dev);
1871 unsigned int val;
1872
1873 /* enable wakeup from i.MX UART */
1874 val = readl(sport->port.membase + UCR3);
1875 val |= UCR3_AWAKEN;
1876 writel(val, sport->port.membase + UCR3);
1877
1878 uart_suspend_port(&imx_reg, &sport->port);
1879
1880 return 0;
1881 }
1882
1883 static int serial_imx_resume(struct platform_device *dev)
1884 {
1885 struct imx_port *sport = platform_get_drvdata(dev);
1886 unsigned int val;
1887
1888 /* disable wakeup from i.MX UART */
1889 val = readl(sport->port.membase + UCR3);
1890 val &= ~UCR3_AWAKEN;
1891 writel(val, sport->port.membase + UCR3);
1892
1893 uart_resume_port(&imx_reg, &sport->port);
1894
1895 return 0;
1896 }
1897
1898 #ifdef CONFIG_OF
1899 /*
1900 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1901 * could successfully get all information from dt or a negative errno.
1902 */
1903 static int serial_imx_probe_dt(struct imx_port *sport,
1904 struct platform_device *pdev)
1905 {
1906 struct device_node *np = pdev->dev.of_node;
1907 const struct of_device_id *of_id =
1908 of_match_device(imx_uart_dt_ids, &pdev->dev);
1909 int ret;
1910
1911 if (!np)
1912 /* no device tree device */
1913 return 1;
1914
1915 ret = of_alias_get_id(np, "serial");
1916 if (ret < 0) {
1917 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1918 return ret;
1919 }
1920 sport->port.line = ret;
1921
1922 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1923 sport->have_rtscts = 1;
1924
1925 if (of_get_property(np, "fsl,irda-mode", NULL))
1926 sport->use_irda = 1;
1927
1928 if (of_get_property(np, "fsl,dte-mode", NULL))
1929 sport->dte_mode = 1;
1930
1931 sport->devdata = of_id->data;
1932
1933 if (of_device_is_stdout_path(np))
1934 add_preferred_console(imx_reg.cons->name, sport->port.line,
1935 NULL);
1936
1937 return 0;
1938 }
1939 #else
1940 static inline int serial_imx_probe_dt(struct imx_port *sport,
1941 struct platform_device *pdev)
1942 {
1943 return 1;
1944 }
1945 #endif
1946
1947 static void serial_imx_probe_pdata(struct imx_port *sport,
1948 struct platform_device *pdev)
1949 {
1950 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
1951
1952 sport->port.line = pdev->id;
1953 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1954
1955 if (!pdata)
1956 return;
1957
1958 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1959 sport->have_rtscts = 1;
1960
1961 if (pdata->flags & IMXUART_IRDA)
1962 sport->use_irda = 1;
1963 }
1964
1965 static int serial_imx_probe(struct platform_device *pdev)
1966 {
1967 struct imx_port *sport;
1968 struct imxuart_platform_data *pdata;
1969 void __iomem *base;
1970 int ret = 0;
1971 struct resource *res;
1972
1973 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1974 if (!sport)
1975 return -ENOMEM;
1976
1977 ret = serial_imx_probe_dt(sport, pdev);
1978 if (ret > 0)
1979 serial_imx_probe_pdata(sport, pdev);
1980 else if (ret < 0)
1981 return ret;
1982
1983 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1984 if (!res)
1985 return -ENODEV;
1986
1987 base = devm_ioremap(&pdev->dev, res->start, PAGE_SIZE);
1988 if (!base)
1989 return -ENOMEM;
1990
1991 sport->port.dev = &pdev->dev;
1992 sport->port.mapbase = res->start;
1993 sport->port.membase = base;
1994 sport->port.type = PORT_IMX,
1995 sport->port.iotype = UPIO_MEM;
1996 sport->port.irq = platform_get_irq(pdev, 0);
1997 sport->rxirq = platform_get_irq(pdev, 0);
1998 sport->txirq = platform_get_irq(pdev, 1);
1999 sport->rtsirq = platform_get_irq(pdev, 2);
2000 sport->port.fifosize = 32;
2001 sport->port.ops = &imx_pops;
2002 sport->port.flags = UPF_BOOT_AUTOCONF;
2003 init_timer(&sport->timer);
2004 sport->timer.function = imx_timeout;
2005 sport->timer.data = (unsigned long)sport;
2006
2007 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2008 if (IS_ERR(sport->clk_ipg)) {
2009 ret = PTR_ERR(sport->clk_ipg);
2010 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2011 return ret;
2012 }
2013
2014 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2015 if (IS_ERR(sport->clk_per)) {
2016 ret = PTR_ERR(sport->clk_per);
2017 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2018 return ret;
2019 }
2020
2021 sport->port.uartclk = clk_get_rate(sport->clk_per);
2022
2023 imx_ports[sport->port.line] = sport;
2024
2025 pdata = dev_get_platdata(&pdev->dev);
2026 if (pdata && pdata->init) {
2027 ret = pdata->init(pdev);
2028 if (ret)
2029 return ret;
2030 }
2031
2032 ret = uart_add_one_port(&imx_reg, &sport->port);
2033 if (ret)
2034 goto deinit;
2035 platform_set_drvdata(pdev, sport);
2036
2037 return 0;
2038 deinit:
2039 if (pdata && pdata->exit)
2040 pdata->exit(pdev);
2041 return ret;
2042 }
2043
2044 static int serial_imx_remove(struct platform_device *pdev)
2045 {
2046 struct imxuart_platform_data *pdata;
2047 struct imx_port *sport = platform_get_drvdata(pdev);
2048
2049 pdata = dev_get_platdata(&pdev->dev);
2050
2051 uart_remove_one_port(&imx_reg, &sport->port);
2052
2053 if (pdata && pdata->exit)
2054 pdata->exit(pdev);
2055
2056 return 0;
2057 }
2058
2059 static struct platform_driver serial_imx_driver = {
2060 .probe = serial_imx_probe,
2061 .remove = serial_imx_remove,
2062
2063 .suspend = serial_imx_suspend,
2064 .resume = serial_imx_resume,
2065 .id_table = imx_uart_devtype,
2066 .driver = {
2067 .name = "imx-uart",
2068 .owner = THIS_MODULE,
2069 .of_match_table = imx_uart_dt_ids,
2070 },
2071 };
2072
2073 static int __init imx_serial_init(void)
2074 {
2075 int ret;
2076
2077 pr_info("Serial: IMX driver\n");
2078
2079 ret = uart_register_driver(&imx_reg);
2080 if (ret)
2081 return ret;
2082
2083 ret = platform_driver_register(&serial_imx_driver);
2084 if (ret != 0)
2085 uart_unregister_driver(&imx_reg);
2086
2087 return ret;
2088 }
2089
2090 static void __exit imx_serial_exit(void)
2091 {
2092 platform_driver_unregister(&serial_imx_driver);
2093 uart_unregister_driver(&imx_reg);
2094 }
2095
2096 module_init(imx_serial_init);
2097 module_exit(imx_serial_exit);
2098
2099 MODULE_AUTHOR("Sascha Hauer");
2100 MODULE_DESCRIPTION("IMX generic serial port driver");
2101 MODULE_LICENSE("GPL");
2102 MODULE_ALIAS("platform:imx-uart");
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