]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/tty/serial/mpc52xx_uart.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
tty: add SPDX identifiers to all remaining files in drivers/tty/
[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / mpc52xx_uart.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
4 *
5 * FIXME According to the usermanual the status bits in the status register
6 * are only updated when the peripherals access the FIFO and not when the
7 * CPU access them. So since we use this bits to know when we stop writing
8 * and reading, they may not be updated in-time and a race condition may
9 * exists. But I haven't be able to prove this and I don't care. But if
10 * any problem arises, it might worth checking. The TX/RX FIFO Stats
11 * registers should be used in addition.
12 * Update: Actually, they seem updated ... At least the bits we use.
13 *
14 *
15 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
16 *
17 * Some of the code has been inspired/copied from the 2.4 code written
18 * by Dale Farnsworth <dfarnsworth@mvista.com>.
19 *
20 * Copyright (C) 2008 Freescale Semiconductor Inc.
21 * John Rigby <jrigby@gmail.com>
22 * Added support for MPC5121
23 * Copyright (C) 2006 Secret Lab Technologies Ltd.
24 * Grant Likely <grant.likely@secretlab.ca>
25 * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com>
26 * Copyright (C) 2003 MontaVista, Software, Inc.
27 *
28 * This file is licensed under the terms of the GNU General Public License
29 * version 2. This program is licensed "as is" without any warranty of any
30 * kind, whether express or implied.
31 */
32
33 #undef DEBUG
34
35 #include <linux/device.h>
36 #include <linux/module.h>
37 #include <linux/tty.h>
38 #include <linux/tty_flip.h>
39 #include <linux/serial.h>
40 #include <linux/sysrq.h>
41 #include <linux/console.h>
42 #include <linux/delay.h>
43 #include <linux/io.h>
44 #include <linux/of.h>
45 #include <linux/of_platform.h>
46 #include <linux/clk.h>
47
48 #include <asm/mpc52xx.h>
49 #include <asm/mpc52xx_psc.h>
50
51 #if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
52 #define SUPPORT_SYSRQ
53 #endif
54
55 #include <linux/serial_core.h>
56
57
58 /* We've been assigned a range on the "Low-density serial ports" major */
59 #define SERIAL_PSC_MAJOR 204
60 #define SERIAL_PSC_MINOR 148
61
62
63 #define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */
64
65
66 static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM];
67 /* Rem: - We use the read_status_mask as a shadow of
68 * psc->mpc52xx_psc_imr
69 * - It's important that is array is all zero on start as we
70 * use it to know if it's initialized or not ! If it's not sure
71 * it's cleared, then a memset(...,0,...) should be added to
72 * the console_init
73 */
74
75 /* lookup table for matching device nodes to index numbers */
76 static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM];
77
78 static void mpc52xx_uart_of_enumerate(void);
79
80
81 #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
82
83
84 /* Forward declaration of the interruption handling routine */
85 static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id);
86 static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port);
87
88 /* ======================================================================== */
89 /* PSC fifo operations for isolating differences between 52xx and 512x */
90 /* ======================================================================== */
91
92 struct psc_ops {
93 void (*fifo_init)(struct uart_port *port);
94 int (*raw_rx_rdy)(struct uart_port *port);
95 int (*raw_tx_rdy)(struct uart_port *port);
96 int (*rx_rdy)(struct uart_port *port);
97 int (*tx_rdy)(struct uart_port *port);
98 int (*tx_empty)(struct uart_port *port);
99 void (*stop_rx)(struct uart_port *port);
100 void (*start_tx)(struct uart_port *port);
101 void (*stop_tx)(struct uart_port *port);
102 void (*rx_clr_irq)(struct uart_port *port);
103 void (*tx_clr_irq)(struct uart_port *port);
104 void (*write_char)(struct uart_port *port, unsigned char c);
105 unsigned char (*read_char)(struct uart_port *port);
106 void (*cw_disable_ints)(struct uart_port *port);
107 void (*cw_restore_ints)(struct uart_port *port);
108 unsigned int (*set_baudrate)(struct uart_port *port,
109 struct ktermios *new,
110 struct ktermios *old);
111 int (*clock_alloc)(struct uart_port *port);
112 void (*clock_relse)(struct uart_port *port);
113 int (*clock)(struct uart_port *port, int enable);
114 int (*fifoc_init)(void);
115 void (*fifoc_uninit)(void);
116 void (*get_irq)(struct uart_port *, struct device_node *);
117 irqreturn_t (*handle_irq)(struct uart_port *port);
118 u16 (*get_status)(struct uart_port *port);
119 u8 (*get_ipcr)(struct uart_port *port);
120 void (*command)(struct uart_port *port, u8 cmd);
121 void (*set_mode)(struct uart_port *port, u8 mr1, u8 mr2);
122 void (*set_rts)(struct uart_port *port, int state);
123 void (*enable_ms)(struct uart_port *port);
124 void (*set_sicr)(struct uart_port *port, u32 val);
125 void (*set_imr)(struct uart_port *port, u16 val);
126 u8 (*get_mr1)(struct uart_port *port);
127 };
128
129 /* setting the prescaler and divisor reg is common for all chips */
130 static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc,
131 u16 prescaler, unsigned int divisor)
132 {
133 /* select prescaler */
134 out_be16(&psc->mpc52xx_psc_clock_select, prescaler);
135 out_8(&psc->ctur, divisor >> 8);
136 out_8(&psc->ctlr, divisor & 0xff);
137 }
138
139 static u16 mpc52xx_psc_get_status(struct uart_port *port)
140 {
141 return in_be16(&PSC(port)->mpc52xx_psc_status);
142 }
143
144 static u8 mpc52xx_psc_get_ipcr(struct uart_port *port)
145 {
146 return in_8(&PSC(port)->mpc52xx_psc_ipcr);
147 }
148
149 static void mpc52xx_psc_command(struct uart_port *port, u8 cmd)
150 {
151 out_8(&PSC(port)->command, cmd);
152 }
153
154 static void mpc52xx_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
155 {
156 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
157 out_8(&PSC(port)->mode, mr1);
158 out_8(&PSC(port)->mode, mr2);
159 }
160
161 static void mpc52xx_psc_set_rts(struct uart_port *port, int state)
162 {
163 if (state)
164 out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);
165 else
166 out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);
167 }
168
169 static void mpc52xx_psc_enable_ms(struct uart_port *port)
170 {
171 struct mpc52xx_psc __iomem *psc = PSC(port);
172
173 /* clear D_*-bits by reading them */
174 in_8(&psc->mpc52xx_psc_ipcr);
175 /* enable CTS and DCD as IPC interrupts */
176 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
177
178 port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
179 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
180 }
181
182 static void mpc52xx_psc_set_sicr(struct uart_port *port, u32 val)
183 {
184 out_be32(&PSC(port)->sicr, val);
185 }
186
187 static void mpc52xx_psc_set_imr(struct uart_port *port, u16 val)
188 {
189 out_be16(&PSC(port)->mpc52xx_psc_imr, val);
190 }
191
192 static u8 mpc52xx_psc_get_mr1(struct uart_port *port)
193 {
194 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
195 return in_8(&PSC(port)->mode);
196 }
197
198 #ifdef CONFIG_PPC_MPC52xx
199 #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
200 static void mpc52xx_psc_fifo_init(struct uart_port *port)
201 {
202 struct mpc52xx_psc __iomem *psc = PSC(port);
203 struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port);
204
205 out_8(&fifo->rfcntl, 0x00);
206 out_be16(&fifo->rfalarm, 0x1ff);
207 out_8(&fifo->tfcntl, 0x07);
208 out_be16(&fifo->tfalarm, 0x80);
209
210 port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY;
211 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
212 }
213
214 static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port)
215 {
216 return in_be16(&PSC(port)->mpc52xx_psc_status)
217 & MPC52xx_PSC_SR_RXRDY;
218 }
219
220 static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port)
221 {
222 return in_be16(&PSC(port)->mpc52xx_psc_status)
223 & MPC52xx_PSC_SR_TXRDY;
224 }
225
226
227 static int mpc52xx_psc_rx_rdy(struct uart_port *port)
228 {
229 return in_be16(&PSC(port)->mpc52xx_psc_isr)
230 & port->read_status_mask
231 & MPC52xx_PSC_IMR_RXRDY;
232 }
233
234 static int mpc52xx_psc_tx_rdy(struct uart_port *port)
235 {
236 return in_be16(&PSC(port)->mpc52xx_psc_isr)
237 & port->read_status_mask
238 & MPC52xx_PSC_IMR_TXRDY;
239 }
240
241 static int mpc52xx_psc_tx_empty(struct uart_port *port)
242 {
243 u16 sts = in_be16(&PSC(port)->mpc52xx_psc_status);
244
245 return (sts & MPC52xx_PSC_SR_TXEMP) ? TIOCSER_TEMT : 0;
246 }
247
248 static void mpc52xx_psc_start_tx(struct uart_port *port)
249 {
250 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
251 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
252 }
253
254 static void mpc52xx_psc_stop_tx(struct uart_port *port)
255 {
256 port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY;
257 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
258 }
259
260 static void mpc52xx_psc_stop_rx(struct uart_port *port)
261 {
262 port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY;
263 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
264 }
265
266 static void mpc52xx_psc_rx_clr_irq(struct uart_port *port)
267 {
268 }
269
270 static void mpc52xx_psc_tx_clr_irq(struct uart_port *port)
271 {
272 }
273
274 static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c)
275 {
276 out_8(&PSC(port)->mpc52xx_psc_buffer_8, c);
277 }
278
279 static unsigned char mpc52xx_psc_read_char(struct uart_port *port)
280 {
281 return in_8(&PSC(port)->mpc52xx_psc_buffer_8);
282 }
283
284 static void mpc52xx_psc_cw_disable_ints(struct uart_port *port)
285 {
286 out_be16(&PSC(port)->mpc52xx_psc_imr, 0);
287 }
288
289 static void mpc52xx_psc_cw_restore_ints(struct uart_port *port)
290 {
291 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
292 }
293
294 static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port,
295 struct ktermios *new,
296 struct ktermios *old)
297 {
298 unsigned int baud;
299 unsigned int divisor;
300
301 /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */
302 baud = uart_get_baud_rate(port, new, old,
303 port->uartclk / (32 * 0xffff) + 1,
304 port->uartclk / 32);
305 divisor = (port->uartclk + 16 * baud) / (32 * baud);
306
307 /* enable the /32 prescaler and set the divisor */
308 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
309 return baud;
310 }
311
312 static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port,
313 struct ktermios *new,
314 struct ktermios *old)
315 {
316 unsigned int baud;
317 unsigned int divisor;
318 u16 prescaler;
319
320 /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the
321 * ipb freq */
322 baud = uart_get_baud_rate(port, new, old,
323 port->uartclk / (32 * 0xffff) + 1,
324 port->uartclk / 4);
325 divisor = (port->uartclk + 2 * baud) / (4 * baud);
326
327 /* select the proper prescaler and set the divisor
328 * prefer high prescaler for more tolerance on low baudrates */
329 if (divisor > 0xffff || baud <= 115200) {
330 divisor = (divisor + 4) / 8;
331 prescaler = 0xdd00; /* /32 */
332 } else
333 prescaler = 0xff00; /* /4 */
334 mpc52xx_set_divisor(PSC(port), prescaler, divisor);
335 return baud;
336 }
337
338 static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np)
339 {
340 port->irqflags = 0;
341 port->irq = irq_of_parse_and_map(np, 0);
342 }
343
344 /* 52xx specific interrupt handler. The caller holds the port lock */
345 static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port)
346 {
347 return mpc5xxx_uart_process_int(port);
348 }
349
350 static const struct psc_ops mpc52xx_psc_ops = {
351 .fifo_init = mpc52xx_psc_fifo_init,
352 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
353 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
354 .rx_rdy = mpc52xx_psc_rx_rdy,
355 .tx_rdy = mpc52xx_psc_tx_rdy,
356 .tx_empty = mpc52xx_psc_tx_empty,
357 .stop_rx = mpc52xx_psc_stop_rx,
358 .start_tx = mpc52xx_psc_start_tx,
359 .stop_tx = mpc52xx_psc_stop_tx,
360 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
361 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
362 .write_char = mpc52xx_psc_write_char,
363 .read_char = mpc52xx_psc_read_char,
364 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
365 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
366 .set_baudrate = mpc5200_psc_set_baudrate,
367 .get_irq = mpc52xx_psc_get_irq,
368 .handle_irq = mpc52xx_psc_handle_irq,
369 .get_status = mpc52xx_psc_get_status,
370 .get_ipcr = mpc52xx_psc_get_ipcr,
371 .command = mpc52xx_psc_command,
372 .set_mode = mpc52xx_psc_set_mode,
373 .set_rts = mpc52xx_psc_set_rts,
374 .enable_ms = mpc52xx_psc_enable_ms,
375 .set_sicr = mpc52xx_psc_set_sicr,
376 .set_imr = mpc52xx_psc_set_imr,
377 .get_mr1 = mpc52xx_psc_get_mr1,
378 };
379
380 static const struct psc_ops mpc5200b_psc_ops = {
381 .fifo_init = mpc52xx_psc_fifo_init,
382 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
383 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
384 .rx_rdy = mpc52xx_psc_rx_rdy,
385 .tx_rdy = mpc52xx_psc_tx_rdy,
386 .tx_empty = mpc52xx_psc_tx_empty,
387 .stop_rx = mpc52xx_psc_stop_rx,
388 .start_tx = mpc52xx_psc_start_tx,
389 .stop_tx = mpc52xx_psc_stop_tx,
390 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
391 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
392 .write_char = mpc52xx_psc_write_char,
393 .read_char = mpc52xx_psc_read_char,
394 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
395 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
396 .set_baudrate = mpc5200b_psc_set_baudrate,
397 .get_irq = mpc52xx_psc_get_irq,
398 .handle_irq = mpc52xx_psc_handle_irq,
399 .get_status = mpc52xx_psc_get_status,
400 .get_ipcr = mpc52xx_psc_get_ipcr,
401 .command = mpc52xx_psc_command,
402 .set_mode = mpc52xx_psc_set_mode,
403 .set_rts = mpc52xx_psc_set_rts,
404 .enable_ms = mpc52xx_psc_enable_ms,
405 .set_sicr = mpc52xx_psc_set_sicr,
406 .set_imr = mpc52xx_psc_set_imr,
407 .get_mr1 = mpc52xx_psc_get_mr1,
408 };
409
410 #endif /* CONFIG_PPC_MPC52xx */
411
412 #ifdef CONFIG_PPC_MPC512x
413 #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))
414
415 /* PSC FIFO Controller for mpc512x */
416 struct psc_fifoc {
417 u32 fifoc_cmd;
418 u32 fifoc_int;
419 u32 fifoc_dma;
420 u32 fifoc_axe;
421 u32 fifoc_debug;
422 };
423
424 static struct psc_fifoc __iomem *psc_fifoc;
425 static unsigned int psc_fifoc_irq;
426 static struct clk *psc_fifoc_clk;
427
428 static void mpc512x_psc_fifo_init(struct uart_port *port)
429 {
430 /* /32 prescaler */
431 out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00);
432
433 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
434 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
435 out_be32(&FIFO_512x(port)->txalarm, 1);
436 out_be32(&FIFO_512x(port)->tximr, 0);
437
438 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
439 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
440 out_be32(&FIFO_512x(port)->rxalarm, 1);
441 out_be32(&FIFO_512x(port)->rximr, 0);
442
443 out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);
444 out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);
445 }
446
447 static int mpc512x_psc_raw_rx_rdy(struct uart_port *port)
448 {
449 return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
450 }
451
452 static int mpc512x_psc_raw_tx_rdy(struct uart_port *port)
453 {
454 return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL);
455 }
456
457 static int mpc512x_psc_rx_rdy(struct uart_port *port)
458 {
459 return in_be32(&FIFO_512x(port)->rxsr)
460 & in_be32(&FIFO_512x(port)->rximr)
461 & MPC512x_PSC_FIFO_ALARM;
462 }
463
464 static int mpc512x_psc_tx_rdy(struct uart_port *port)
465 {
466 return in_be32(&FIFO_512x(port)->txsr)
467 & in_be32(&FIFO_512x(port)->tximr)
468 & MPC512x_PSC_FIFO_ALARM;
469 }
470
471 static int mpc512x_psc_tx_empty(struct uart_port *port)
472 {
473 return in_be32(&FIFO_512x(port)->txsr)
474 & MPC512x_PSC_FIFO_EMPTY;
475 }
476
477 static void mpc512x_psc_stop_rx(struct uart_port *port)
478 {
479 unsigned long rx_fifo_imr;
480
481 rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr);
482 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
483 out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);
484 }
485
486 static void mpc512x_psc_start_tx(struct uart_port *port)
487 {
488 unsigned long tx_fifo_imr;
489
490 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
491 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
492 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
493 }
494
495 static void mpc512x_psc_stop_tx(struct uart_port *port)
496 {
497 unsigned long tx_fifo_imr;
498
499 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
500 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
501 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
502 }
503
504 static void mpc512x_psc_rx_clr_irq(struct uart_port *port)
505 {
506 out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));
507 }
508
509 static void mpc512x_psc_tx_clr_irq(struct uart_port *port)
510 {
511 out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));
512 }
513
514 static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c)
515 {
516 out_8(&FIFO_512x(port)->txdata_8, c);
517 }
518
519 static unsigned char mpc512x_psc_read_char(struct uart_port *port)
520 {
521 return in_8(&FIFO_512x(port)->rxdata_8);
522 }
523
524 static void mpc512x_psc_cw_disable_ints(struct uart_port *port)
525 {
526 port->read_status_mask =
527 in_be32(&FIFO_512x(port)->tximr) << 16 |
528 in_be32(&FIFO_512x(port)->rximr);
529 out_be32(&FIFO_512x(port)->tximr, 0);
530 out_be32(&FIFO_512x(port)->rximr, 0);
531 }
532
533 static void mpc512x_psc_cw_restore_ints(struct uart_port *port)
534 {
535 out_be32(&FIFO_512x(port)->tximr,
536 (port->read_status_mask >> 16) & 0x7f);
537 out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);
538 }
539
540 static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port,
541 struct ktermios *new,
542 struct ktermios *old)
543 {
544 unsigned int baud;
545 unsigned int divisor;
546
547 /*
548 * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on
549 * pg. 30-10 that the chip supports a /32 and a /10 prescaler.
550 * Furthermore, it states that "After reset, the prescaler by 10
551 * for the UART mode is selected", but the reset register value is
552 * 0x0000 which means a /32 prescaler. This is wrong.
553 *
554 * In reality using /32 prescaler doesn't work, as it is not supported!
555 * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide",
556 * Chapter 4.1 PSC in UART Mode.
557 * Calculate with a /16 prescaler here.
558 */
559
560 /* uartclk contains the ips freq */
561 baud = uart_get_baud_rate(port, new, old,
562 port->uartclk / (16 * 0xffff) + 1,
563 port->uartclk / 16);
564 divisor = (port->uartclk + 8 * baud) / (16 * baud);
565
566 /* enable the /16 prescaler and set the divisor */
567 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
568 return baud;
569 }
570
571 /* Init PSC FIFO Controller */
572 static int __init mpc512x_psc_fifoc_init(void)
573 {
574 int err;
575 struct device_node *np;
576 struct clk *clk;
577
578 /* default error code, potentially overwritten by clock calls */
579 err = -ENODEV;
580
581 np = of_find_compatible_node(NULL, NULL,
582 "fsl,mpc5121-psc-fifo");
583 if (!np) {
584 pr_err("%s: Can't find FIFOC node\n", __func__);
585 goto out_err;
586 }
587
588 clk = of_clk_get(np, 0);
589 if (IS_ERR(clk)) {
590 /* backwards compat with device trees that lack clock specs */
591 clk = clk_get_sys(np->name, "ipg");
592 }
593 if (IS_ERR(clk)) {
594 pr_err("%s: Can't lookup FIFO clock\n", __func__);
595 err = PTR_ERR(clk);
596 goto out_ofnode_put;
597 }
598 if (clk_prepare_enable(clk)) {
599 pr_err("%s: Can't enable FIFO clock\n", __func__);
600 clk_put(clk);
601 goto out_ofnode_put;
602 }
603 psc_fifoc_clk = clk;
604
605 psc_fifoc = of_iomap(np, 0);
606 if (!psc_fifoc) {
607 pr_err("%s: Can't map FIFOC\n", __func__);
608 goto out_clk_disable;
609 }
610
611 psc_fifoc_irq = irq_of_parse_and_map(np, 0);
612 if (psc_fifoc_irq == 0) {
613 pr_err("%s: Can't get FIFOC irq\n", __func__);
614 goto out_unmap;
615 }
616
617 of_node_put(np);
618 return 0;
619
620 out_unmap:
621 iounmap(psc_fifoc);
622 out_clk_disable:
623 clk_disable_unprepare(psc_fifoc_clk);
624 clk_put(psc_fifoc_clk);
625 out_ofnode_put:
626 of_node_put(np);
627 out_err:
628 return err;
629 }
630
631 static void __exit mpc512x_psc_fifoc_uninit(void)
632 {
633 iounmap(psc_fifoc);
634
635 /* disable the clock, errors are not fatal */
636 if (psc_fifoc_clk) {
637 clk_disable_unprepare(psc_fifoc_clk);
638 clk_put(psc_fifoc_clk);
639 psc_fifoc_clk = NULL;
640 }
641 }
642
643 /* 512x specific interrupt handler. The caller holds the port lock */
644 static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
645 {
646 unsigned long fifoc_int;
647 int psc_num;
648
649 /* Read pending PSC FIFOC interrupts */
650 fifoc_int = in_be32(&psc_fifoc->fifoc_int);
651
652 /* Check if it is an interrupt for this port */
653 psc_num = (port->mapbase & 0xf00) >> 8;
654 if (test_bit(psc_num, &fifoc_int) ||
655 test_bit(psc_num + 16, &fifoc_int))
656 return mpc5xxx_uart_process_int(port);
657
658 return IRQ_NONE;
659 }
660
661 static struct clk *psc_mclk_clk[MPC52xx_PSC_MAXNUM];
662 static struct clk *psc_ipg_clk[MPC52xx_PSC_MAXNUM];
663
664 /* called from within the .request_port() callback (allocation) */
665 static int mpc512x_psc_alloc_clock(struct uart_port *port)
666 {
667 int psc_num;
668 struct clk *clk;
669 int err;
670
671 psc_num = (port->mapbase & 0xf00) >> 8;
672
673 clk = devm_clk_get(port->dev, "mclk");
674 if (IS_ERR(clk)) {
675 dev_err(port->dev, "Failed to get MCLK!\n");
676 err = PTR_ERR(clk);
677 goto out_err;
678 }
679 err = clk_prepare_enable(clk);
680 if (err) {
681 dev_err(port->dev, "Failed to enable MCLK!\n");
682 goto out_err;
683 }
684 psc_mclk_clk[psc_num] = clk;
685
686 clk = devm_clk_get(port->dev, "ipg");
687 if (IS_ERR(clk)) {
688 dev_err(port->dev, "Failed to get IPG clock!\n");
689 err = PTR_ERR(clk);
690 goto out_err;
691 }
692 err = clk_prepare_enable(clk);
693 if (err) {
694 dev_err(port->dev, "Failed to enable IPG clock!\n");
695 goto out_err;
696 }
697 psc_ipg_clk[psc_num] = clk;
698
699 return 0;
700
701 out_err:
702 if (psc_mclk_clk[psc_num]) {
703 clk_disable_unprepare(psc_mclk_clk[psc_num]);
704 psc_mclk_clk[psc_num] = NULL;
705 }
706 if (psc_ipg_clk[psc_num]) {
707 clk_disable_unprepare(psc_ipg_clk[psc_num]);
708 psc_ipg_clk[psc_num] = NULL;
709 }
710 return err;
711 }
712
713 /* called from within the .release_port() callback (release) */
714 static void mpc512x_psc_relse_clock(struct uart_port *port)
715 {
716 int psc_num;
717 struct clk *clk;
718
719 psc_num = (port->mapbase & 0xf00) >> 8;
720 clk = psc_mclk_clk[psc_num];
721 if (clk) {
722 clk_disable_unprepare(clk);
723 psc_mclk_clk[psc_num] = NULL;
724 }
725 if (psc_ipg_clk[psc_num]) {
726 clk_disable_unprepare(psc_ipg_clk[psc_num]);
727 psc_ipg_clk[psc_num] = NULL;
728 }
729 }
730
731 /* implementation of the .clock() callback (enable/disable) */
732 static int mpc512x_psc_endis_clock(struct uart_port *port, int enable)
733 {
734 int psc_num;
735 struct clk *psc_clk;
736 int ret;
737
738 if (uart_console(port))
739 return 0;
740
741 psc_num = (port->mapbase & 0xf00) >> 8;
742 psc_clk = psc_mclk_clk[psc_num];
743 if (!psc_clk) {
744 dev_err(port->dev, "Failed to get PSC clock entry!\n");
745 return -ENODEV;
746 }
747
748 dev_dbg(port->dev, "mclk %sable\n", enable ? "en" : "dis");
749 if (enable) {
750 ret = clk_enable(psc_clk);
751 if (ret)
752 dev_err(port->dev, "Failed to enable MCLK!\n");
753 return ret;
754 } else {
755 clk_disable(psc_clk);
756 return 0;
757 }
758 }
759
760 static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np)
761 {
762 port->irqflags = IRQF_SHARED;
763 port->irq = psc_fifoc_irq;
764 }
765 #endif
766
767 #ifdef CONFIG_PPC_MPC512x
768
769 #define PSC_5125(port) ((struct mpc5125_psc __iomem *)((port)->membase))
770 #define FIFO_5125(port) ((struct mpc512x_psc_fifo __iomem *)(PSC_5125(port)+1))
771
772 static void mpc5125_psc_fifo_init(struct uart_port *port)
773 {
774 /* /32 prescaler */
775 out_8(&PSC_5125(port)->mpc52xx_psc_clock_select, 0xdd);
776
777 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
778 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
779 out_be32(&FIFO_5125(port)->txalarm, 1);
780 out_be32(&FIFO_5125(port)->tximr, 0);
781
782 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
783 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
784 out_be32(&FIFO_5125(port)->rxalarm, 1);
785 out_be32(&FIFO_5125(port)->rximr, 0);
786
787 out_be32(&FIFO_5125(port)->tximr, MPC512x_PSC_FIFO_ALARM);
788 out_be32(&FIFO_5125(port)->rximr, MPC512x_PSC_FIFO_ALARM);
789 }
790
791 static int mpc5125_psc_raw_rx_rdy(struct uart_port *port)
792 {
793 return !(in_be32(&FIFO_5125(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
794 }
795
796 static int mpc5125_psc_raw_tx_rdy(struct uart_port *port)
797 {
798 return !(in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_FULL);
799 }
800
801 static int mpc5125_psc_rx_rdy(struct uart_port *port)
802 {
803 return in_be32(&FIFO_5125(port)->rxsr) &
804 in_be32(&FIFO_5125(port)->rximr) & MPC512x_PSC_FIFO_ALARM;
805 }
806
807 static int mpc5125_psc_tx_rdy(struct uart_port *port)
808 {
809 return in_be32(&FIFO_5125(port)->txsr) &
810 in_be32(&FIFO_5125(port)->tximr) & MPC512x_PSC_FIFO_ALARM;
811 }
812
813 static int mpc5125_psc_tx_empty(struct uart_port *port)
814 {
815 return in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_EMPTY;
816 }
817
818 static void mpc5125_psc_stop_rx(struct uart_port *port)
819 {
820 unsigned long rx_fifo_imr;
821
822 rx_fifo_imr = in_be32(&FIFO_5125(port)->rximr);
823 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
824 out_be32(&FIFO_5125(port)->rximr, rx_fifo_imr);
825 }
826
827 static void mpc5125_psc_start_tx(struct uart_port *port)
828 {
829 unsigned long tx_fifo_imr;
830
831 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
832 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
833 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
834 }
835
836 static void mpc5125_psc_stop_tx(struct uart_port *port)
837 {
838 unsigned long tx_fifo_imr;
839
840 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
841 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
842 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
843 }
844
845 static void mpc5125_psc_rx_clr_irq(struct uart_port *port)
846 {
847 out_be32(&FIFO_5125(port)->rxisr, in_be32(&FIFO_5125(port)->rxisr));
848 }
849
850 static void mpc5125_psc_tx_clr_irq(struct uart_port *port)
851 {
852 out_be32(&FIFO_5125(port)->txisr, in_be32(&FIFO_5125(port)->txisr));
853 }
854
855 static void mpc5125_psc_write_char(struct uart_port *port, unsigned char c)
856 {
857 out_8(&FIFO_5125(port)->txdata_8, c);
858 }
859
860 static unsigned char mpc5125_psc_read_char(struct uart_port *port)
861 {
862 return in_8(&FIFO_5125(port)->rxdata_8);
863 }
864
865 static void mpc5125_psc_cw_disable_ints(struct uart_port *port)
866 {
867 port->read_status_mask =
868 in_be32(&FIFO_5125(port)->tximr) << 16 |
869 in_be32(&FIFO_5125(port)->rximr);
870 out_be32(&FIFO_5125(port)->tximr, 0);
871 out_be32(&FIFO_5125(port)->rximr, 0);
872 }
873
874 static void mpc5125_psc_cw_restore_ints(struct uart_port *port)
875 {
876 out_be32(&FIFO_5125(port)->tximr,
877 (port->read_status_mask >> 16) & 0x7f);
878 out_be32(&FIFO_5125(port)->rximr, port->read_status_mask & 0x7f);
879 }
880
881 static inline void mpc5125_set_divisor(struct mpc5125_psc __iomem *psc,
882 u8 prescaler, unsigned int divisor)
883 {
884 /* select prescaler */
885 out_8(&psc->mpc52xx_psc_clock_select, prescaler);
886 out_8(&psc->ctur, divisor >> 8);
887 out_8(&psc->ctlr, divisor & 0xff);
888 }
889
890 static unsigned int mpc5125_psc_set_baudrate(struct uart_port *port,
891 struct ktermios *new,
892 struct ktermios *old)
893 {
894 unsigned int baud;
895 unsigned int divisor;
896
897 /*
898 * Calculate with a /16 prescaler here.
899 */
900
901 /* uartclk contains the ips freq */
902 baud = uart_get_baud_rate(port, new, old,
903 port->uartclk / (16 * 0xffff) + 1,
904 port->uartclk / 16);
905 divisor = (port->uartclk + 8 * baud) / (16 * baud);
906
907 /* enable the /16 prescaler and set the divisor */
908 mpc5125_set_divisor(PSC_5125(port), 0xdd, divisor);
909 return baud;
910 }
911
912 /*
913 * MPC5125 have compatible PSC FIFO Controller.
914 * Special init not needed.
915 */
916 static u16 mpc5125_psc_get_status(struct uart_port *port)
917 {
918 return in_be16(&PSC_5125(port)->mpc52xx_psc_status);
919 }
920
921 static u8 mpc5125_psc_get_ipcr(struct uart_port *port)
922 {
923 return in_8(&PSC_5125(port)->mpc52xx_psc_ipcr);
924 }
925
926 static void mpc5125_psc_command(struct uart_port *port, u8 cmd)
927 {
928 out_8(&PSC_5125(port)->command, cmd);
929 }
930
931 static void mpc5125_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
932 {
933 out_8(&PSC_5125(port)->mr1, mr1);
934 out_8(&PSC_5125(port)->mr2, mr2);
935 }
936
937 static void mpc5125_psc_set_rts(struct uart_port *port, int state)
938 {
939 if (state & TIOCM_RTS)
940 out_8(&PSC_5125(port)->op1, MPC52xx_PSC_OP_RTS);
941 else
942 out_8(&PSC_5125(port)->op0, MPC52xx_PSC_OP_RTS);
943 }
944
945 static void mpc5125_psc_enable_ms(struct uart_port *port)
946 {
947 struct mpc5125_psc __iomem *psc = PSC_5125(port);
948
949 /* clear D_*-bits by reading them */
950 in_8(&psc->mpc52xx_psc_ipcr);
951 /* enable CTS and DCD as IPC interrupts */
952 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
953
954 port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
955 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
956 }
957
958 static void mpc5125_psc_set_sicr(struct uart_port *port, u32 val)
959 {
960 out_be32(&PSC_5125(port)->sicr, val);
961 }
962
963 static void mpc5125_psc_set_imr(struct uart_port *port, u16 val)
964 {
965 out_be16(&PSC_5125(port)->mpc52xx_psc_imr, val);
966 }
967
968 static u8 mpc5125_psc_get_mr1(struct uart_port *port)
969 {
970 return in_8(&PSC_5125(port)->mr1);
971 }
972
973 static const struct psc_ops mpc5125_psc_ops = {
974 .fifo_init = mpc5125_psc_fifo_init,
975 .raw_rx_rdy = mpc5125_psc_raw_rx_rdy,
976 .raw_tx_rdy = mpc5125_psc_raw_tx_rdy,
977 .rx_rdy = mpc5125_psc_rx_rdy,
978 .tx_rdy = mpc5125_psc_tx_rdy,
979 .tx_empty = mpc5125_psc_tx_empty,
980 .stop_rx = mpc5125_psc_stop_rx,
981 .start_tx = mpc5125_psc_start_tx,
982 .stop_tx = mpc5125_psc_stop_tx,
983 .rx_clr_irq = mpc5125_psc_rx_clr_irq,
984 .tx_clr_irq = mpc5125_psc_tx_clr_irq,
985 .write_char = mpc5125_psc_write_char,
986 .read_char = mpc5125_psc_read_char,
987 .cw_disable_ints = mpc5125_psc_cw_disable_ints,
988 .cw_restore_ints = mpc5125_psc_cw_restore_ints,
989 .set_baudrate = mpc5125_psc_set_baudrate,
990 .clock_alloc = mpc512x_psc_alloc_clock,
991 .clock_relse = mpc512x_psc_relse_clock,
992 .clock = mpc512x_psc_endis_clock,
993 .fifoc_init = mpc512x_psc_fifoc_init,
994 .fifoc_uninit = mpc512x_psc_fifoc_uninit,
995 .get_irq = mpc512x_psc_get_irq,
996 .handle_irq = mpc512x_psc_handle_irq,
997 .get_status = mpc5125_psc_get_status,
998 .get_ipcr = mpc5125_psc_get_ipcr,
999 .command = mpc5125_psc_command,
1000 .set_mode = mpc5125_psc_set_mode,
1001 .set_rts = mpc5125_psc_set_rts,
1002 .enable_ms = mpc5125_psc_enable_ms,
1003 .set_sicr = mpc5125_psc_set_sicr,
1004 .set_imr = mpc5125_psc_set_imr,
1005 .get_mr1 = mpc5125_psc_get_mr1,
1006 };
1007
1008 static const struct psc_ops mpc512x_psc_ops = {
1009 .fifo_init = mpc512x_psc_fifo_init,
1010 .raw_rx_rdy = mpc512x_psc_raw_rx_rdy,
1011 .raw_tx_rdy = mpc512x_psc_raw_tx_rdy,
1012 .rx_rdy = mpc512x_psc_rx_rdy,
1013 .tx_rdy = mpc512x_psc_tx_rdy,
1014 .tx_empty = mpc512x_psc_tx_empty,
1015 .stop_rx = mpc512x_psc_stop_rx,
1016 .start_tx = mpc512x_psc_start_tx,
1017 .stop_tx = mpc512x_psc_stop_tx,
1018 .rx_clr_irq = mpc512x_psc_rx_clr_irq,
1019 .tx_clr_irq = mpc512x_psc_tx_clr_irq,
1020 .write_char = mpc512x_psc_write_char,
1021 .read_char = mpc512x_psc_read_char,
1022 .cw_disable_ints = mpc512x_psc_cw_disable_ints,
1023 .cw_restore_ints = mpc512x_psc_cw_restore_ints,
1024 .set_baudrate = mpc512x_psc_set_baudrate,
1025 .clock_alloc = mpc512x_psc_alloc_clock,
1026 .clock_relse = mpc512x_psc_relse_clock,
1027 .clock = mpc512x_psc_endis_clock,
1028 .fifoc_init = mpc512x_psc_fifoc_init,
1029 .fifoc_uninit = mpc512x_psc_fifoc_uninit,
1030 .get_irq = mpc512x_psc_get_irq,
1031 .handle_irq = mpc512x_psc_handle_irq,
1032 .get_status = mpc52xx_psc_get_status,
1033 .get_ipcr = mpc52xx_psc_get_ipcr,
1034 .command = mpc52xx_psc_command,
1035 .set_mode = mpc52xx_psc_set_mode,
1036 .set_rts = mpc52xx_psc_set_rts,
1037 .enable_ms = mpc52xx_psc_enable_ms,
1038 .set_sicr = mpc52xx_psc_set_sicr,
1039 .set_imr = mpc52xx_psc_set_imr,
1040 .get_mr1 = mpc52xx_psc_get_mr1,
1041 };
1042 #endif /* CONFIG_PPC_MPC512x */
1043
1044
1045 static const struct psc_ops *psc_ops;
1046
1047 /* ======================================================================== */
1048 /* UART operations */
1049 /* ======================================================================== */
1050
1051 static unsigned int
1052 mpc52xx_uart_tx_empty(struct uart_port *port)
1053 {
1054 return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0;
1055 }
1056
1057 static void
1058 mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1059 {
1060 psc_ops->set_rts(port, mctrl & TIOCM_RTS);
1061 }
1062
1063 static unsigned int
1064 mpc52xx_uart_get_mctrl(struct uart_port *port)
1065 {
1066 unsigned int ret = TIOCM_DSR;
1067 u8 status = psc_ops->get_ipcr(port);
1068
1069 if (!(status & MPC52xx_PSC_CTS))
1070 ret |= TIOCM_CTS;
1071 if (!(status & MPC52xx_PSC_DCD))
1072 ret |= TIOCM_CAR;
1073
1074 return ret;
1075 }
1076
1077 static void
1078 mpc52xx_uart_stop_tx(struct uart_port *port)
1079 {
1080 /* port->lock taken by caller */
1081 psc_ops->stop_tx(port);
1082 }
1083
1084 static void
1085 mpc52xx_uart_start_tx(struct uart_port *port)
1086 {
1087 /* port->lock taken by caller */
1088 psc_ops->start_tx(port);
1089 }
1090
1091 static void
1092 mpc52xx_uart_stop_rx(struct uart_port *port)
1093 {
1094 /* port->lock taken by caller */
1095 psc_ops->stop_rx(port);
1096 }
1097
1098 static void
1099 mpc52xx_uart_enable_ms(struct uart_port *port)
1100 {
1101 psc_ops->enable_ms(port);
1102 }
1103
1104 static void
1105 mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
1106 {
1107 unsigned long flags;
1108 spin_lock_irqsave(&port->lock, flags);
1109
1110 if (ctl == -1)
1111 psc_ops->command(port, MPC52xx_PSC_START_BRK);
1112 else
1113 psc_ops->command(port, MPC52xx_PSC_STOP_BRK);
1114
1115 spin_unlock_irqrestore(&port->lock, flags);
1116 }
1117
1118 static int
1119 mpc52xx_uart_startup(struct uart_port *port)
1120 {
1121 int ret;
1122
1123 if (psc_ops->clock) {
1124 ret = psc_ops->clock(port, 1);
1125 if (ret)
1126 return ret;
1127 }
1128
1129 /* Request IRQ */
1130 ret = request_irq(port->irq, mpc52xx_uart_int,
1131 port->irqflags, "mpc52xx_psc_uart", port);
1132 if (ret)
1133 return ret;
1134
1135 /* Reset/activate the port, clear and enable interrupts */
1136 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1137 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1138
1139 /*
1140 * According to Freescale's support the RST_TX command can produce a
1141 * spike on the TX pin. So they recommend to delay "for one character".
1142 * One millisecond should be enough for everyone.
1143 */
1144 msleep(1);
1145
1146 psc_ops->set_sicr(port, 0); /* UART mode DCD ignored */
1147
1148 psc_ops->fifo_init(port);
1149
1150 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
1151 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
1152
1153 return 0;
1154 }
1155
1156 static void
1157 mpc52xx_uart_shutdown(struct uart_port *port)
1158 {
1159 /* Shut down the port. Leave TX active if on a console port */
1160 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1161 if (!uart_console(port))
1162 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1163
1164 port->read_status_mask = 0;
1165 psc_ops->set_imr(port, port->read_status_mask);
1166
1167 if (psc_ops->clock)
1168 psc_ops->clock(port, 0);
1169
1170 /* Disable interrupt */
1171 psc_ops->cw_disable_ints(port);
1172
1173 /* Release interrupt */
1174 free_irq(port->irq, port);
1175 }
1176
1177 static void
1178 mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
1179 struct ktermios *old)
1180 {
1181 unsigned long flags;
1182 unsigned char mr1, mr2;
1183 unsigned int j;
1184 unsigned int baud;
1185
1186 /* Prepare what we're gonna write */
1187 mr1 = 0;
1188
1189 switch (new->c_cflag & CSIZE) {
1190 case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS;
1191 break;
1192 case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS;
1193 break;
1194 case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS;
1195 break;
1196 case CS8:
1197 default: mr1 |= MPC52xx_PSC_MODE_8_BITS;
1198 }
1199
1200 if (new->c_cflag & PARENB) {
1201 if (new->c_cflag & CMSPAR)
1202 mr1 |= MPC52xx_PSC_MODE_PARFORCE;
1203
1204 /* With CMSPAR, PARODD also means high parity (same as termios) */
1205 mr1 |= (new->c_cflag & PARODD) ?
1206 MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN;
1207 } else {
1208 mr1 |= MPC52xx_PSC_MODE_PARNONE;
1209 }
1210
1211 mr2 = 0;
1212
1213 if (new->c_cflag & CSTOPB)
1214 mr2 |= MPC52xx_PSC_MODE_TWO_STOP;
1215 else
1216 mr2 |= ((new->c_cflag & CSIZE) == CS5) ?
1217 MPC52xx_PSC_MODE_ONE_STOP_5_BITS :
1218 MPC52xx_PSC_MODE_ONE_STOP;
1219
1220 if (new->c_cflag & CRTSCTS) {
1221 mr1 |= MPC52xx_PSC_MODE_RXRTS;
1222 mr2 |= MPC52xx_PSC_MODE_TXCTS;
1223 }
1224
1225 /* Get the lock */
1226 spin_lock_irqsave(&port->lock, flags);
1227
1228 /* Do our best to flush TX & RX, so we don't lose anything */
1229 /* But we don't wait indefinitely ! */
1230 j = 5000000; /* Maximum wait */
1231 /* FIXME Can't receive chars since set_termios might be called at early
1232 * boot for the console, all stuff is not yet ready to receive at that
1233 * time and that just makes the kernel oops */
1234 /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */
1235 while (!mpc52xx_uart_tx_empty(port) && --j)
1236 udelay(1);
1237
1238 if (!j)
1239 printk(KERN_ERR "mpc52xx_uart.c: "
1240 "Unable to flush RX & TX fifos in-time in set_termios."
1241 "Some chars may have been lost.\n");
1242
1243 /* Reset the TX & RX */
1244 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1245 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1246
1247 /* Send new mode settings */
1248 psc_ops->set_mode(port, mr1, mr2);
1249 baud = psc_ops->set_baudrate(port, new, old);
1250
1251 /* Update the per-port timeout */
1252 uart_update_timeout(port, new->c_cflag, baud);
1253
1254 if (UART_ENABLE_MS(port, new->c_cflag))
1255 mpc52xx_uart_enable_ms(port);
1256
1257 /* Reenable TX & RX */
1258 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
1259 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
1260
1261 /* We're all set, release the lock */
1262 spin_unlock_irqrestore(&port->lock, flags);
1263 }
1264
1265 static const char *
1266 mpc52xx_uart_type(struct uart_port *port)
1267 {
1268 /*
1269 * We keep using PORT_MPC52xx for historic reasons although it applies
1270 * for MPC512x, too, but print "MPC5xxx" to not irritate users
1271 */
1272 return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL;
1273 }
1274
1275 static void
1276 mpc52xx_uart_release_port(struct uart_port *port)
1277 {
1278 if (psc_ops->clock_relse)
1279 psc_ops->clock_relse(port);
1280
1281 /* remapped by us ? */
1282 if (port->flags & UPF_IOREMAP) {
1283 iounmap(port->membase);
1284 port->membase = NULL;
1285 }
1286
1287 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
1288 }
1289
1290 static int
1291 mpc52xx_uart_request_port(struct uart_port *port)
1292 {
1293 int err;
1294
1295 if (port->flags & UPF_IOREMAP) /* Need to remap ? */
1296 port->membase = ioremap(port->mapbase,
1297 sizeof(struct mpc52xx_psc));
1298
1299 if (!port->membase)
1300 return -EINVAL;
1301
1302 err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc),
1303 "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
1304
1305 if (err)
1306 goto out_membase;
1307
1308 if (psc_ops->clock_alloc) {
1309 err = psc_ops->clock_alloc(port);
1310 if (err)
1311 goto out_mapregion;
1312 }
1313
1314 return 0;
1315
1316 out_mapregion:
1317 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
1318 out_membase:
1319 if (port->flags & UPF_IOREMAP) {
1320 iounmap(port->membase);
1321 port->membase = NULL;
1322 }
1323 return err;
1324 }
1325
1326 static void
1327 mpc52xx_uart_config_port(struct uart_port *port, int flags)
1328 {
1329 if ((flags & UART_CONFIG_TYPE)
1330 && (mpc52xx_uart_request_port(port) == 0))
1331 port->type = PORT_MPC52xx;
1332 }
1333
1334 static int
1335 mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1336 {
1337 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx)
1338 return -EINVAL;
1339
1340 if ((ser->irq != port->irq) ||
1341 (ser->io_type != UPIO_MEM) ||
1342 (ser->baud_base != port->uartclk) ||
1343 (ser->iomem_base != (void *)port->mapbase) ||
1344 (ser->hub6 != 0))
1345 return -EINVAL;
1346
1347 return 0;
1348 }
1349
1350
1351 static const struct uart_ops mpc52xx_uart_ops = {
1352 .tx_empty = mpc52xx_uart_tx_empty,
1353 .set_mctrl = mpc52xx_uart_set_mctrl,
1354 .get_mctrl = mpc52xx_uart_get_mctrl,
1355 .stop_tx = mpc52xx_uart_stop_tx,
1356 .start_tx = mpc52xx_uart_start_tx,
1357 .stop_rx = mpc52xx_uart_stop_rx,
1358 .enable_ms = mpc52xx_uart_enable_ms,
1359 .break_ctl = mpc52xx_uart_break_ctl,
1360 .startup = mpc52xx_uart_startup,
1361 .shutdown = mpc52xx_uart_shutdown,
1362 .set_termios = mpc52xx_uart_set_termios,
1363 /* .pm = mpc52xx_uart_pm, Not supported yet */
1364 .type = mpc52xx_uart_type,
1365 .release_port = mpc52xx_uart_release_port,
1366 .request_port = mpc52xx_uart_request_port,
1367 .config_port = mpc52xx_uart_config_port,
1368 .verify_port = mpc52xx_uart_verify_port
1369 };
1370
1371
1372 /* ======================================================================== */
1373 /* Interrupt handling */
1374 /* ======================================================================== */
1375
1376 static inline int
1377 mpc52xx_uart_int_rx_chars(struct uart_port *port)
1378 {
1379 struct tty_port *tport = &port->state->port;
1380 unsigned char ch, flag;
1381 unsigned short status;
1382
1383 /* While we can read, do so ! */
1384 while (psc_ops->raw_rx_rdy(port)) {
1385 /* Get the char */
1386 ch = psc_ops->read_char(port);
1387
1388 /* Handle sysreq char */
1389 #ifdef SUPPORT_SYSRQ
1390 if (uart_handle_sysrq_char(port, ch)) {
1391 port->sysrq = 0;
1392 continue;
1393 }
1394 #endif
1395
1396 /* Store it */
1397
1398 flag = TTY_NORMAL;
1399 port->icount.rx++;
1400
1401 status = psc_ops->get_status(port);
1402
1403 if (status & (MPC52xx_PSC_SR_PE |
1404 MPC52xx_PSC_SR_FE |
1405 MPC52xx_PSC_SR_RB)) {
1406
1407 if (status & MPC52xx_PSC_SR_RB) {
1408 flag = TTY_BREAK;
1409 uart_handle_break(port);
1410 port->icount.brk++;
1411 } else if (status & MPC52xx_PSC_SR_PE) {
1412 flag = TTY_PARITY;
1413 port->icount.parity++;
1414 }
1415 else if (status & MPC52xx_PSC_SR_FE) {
1416 flag = TTY_FRAME;
1417 port->icount.frame++;
1418 }
1419
1420 /* Clear error condition */
1421 psc_ops->command(port, MPC52xx_PSC_RST_ERR_STAT);
1422
1423 }
1424 tty_insert_flip_char(tport, ch, flag);
1425 if (status & MPC52xx_PSC_SR_OE) {
1426 /*
1427 * Overrun is special, since it's
1428 * reported immediately, and doesn't
1429 * affect the current character
1430 */
1431 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1432 port->icount.overrun++;
1433 }
1434 }
1435
1436 spin_unlock(&port->lock);
1437 tty_flip_buffer_push(tport);
1438 spin_lock(&port->lock);
1439
1440 return psc_ops->raw_rx_rdy(port);
1441 }
1442
1443 static inline int
1444 mpc52xx_uart_int_tx_chars(struct uart_port *port)
1445 {
1446 struct circ_buf *xmit = &port->state->xmit;
1447
1448 /* Process out of band chars */
1449 if (port->x_char) {
1450 psc_ops->write_char(port, port->x_char);
1451 port->icount.tx++;
1452 port->x_char = 0;
1453 return 1;
1454 }
1455
1456 /* Nothing to do ? */
1457 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
1458 mpc52xx_uart_stop_tx(port);
1459 return 0;
1460 }
1461
1462 /* Send chars */
1463 while (psc_ops->raw_tx_rdy(port)) {
1464 psc_ops->write_char(port, xmit->buf[xmit->tail]);
1465 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1466 port->icount.tx++;
1467 if (uart_circ_empty(xmit))
1468 break;
1469 }
1470
1471 /* Wake up */
1472 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1473 uart_write_wakeup(port);
1474
1475 /* Maybe we're done after all */
1476 if (uart_circ_empty(xmit)) {
1477 mpc52xx_uart_stop_tx(port);
1478 return 0;
1479 }
1480
1481 return 1;
1482 }
1483
1484 static irqreturn_t
1485 mpc5xxx_uart_process_int(struct uart_port *port)
1486 {
1487 unsigned long pass = ISR_PASS_LIMIT;
1488 unsigned int keepgoing;
1489 u8 status;
1490
1491 /* While we have stuff to do, we continue */
1492 do {
1493 /* If we don't find anything to do, we stop */
1494 keepgoing = 0;
1495
1496 psc_ops->rx_clr_irq(port);
1497 if (psc_ops->rx_rdy(port))
1498 keepgoing |= mpc52xx_uart_int_rx_chars(port);
1499
1500 psc_ops->tx_clr_irq(port);
1501 if (psc_ops->tx_rdy(port))
1502 keepgoing |= mpc52xx_uart_int_tx_chars(port);
1503
1504 status = psc_ops->get_ipcr(port);
1505 if (status & MPC52xx_PSC_D_DCD)
1506 uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD));
1507
1508 if (status & MPC52xx_PSC_D_CTS)
1509 uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS));
1510
1511 /* Limit number of iteration */
1512 if (!(--pass))
1513 keepgoing = 0;
1514
1515 } while (keepgoing);
1516
1517 return IRQ_HANDLED;
1518 }
1519
1520 static irqreturn_t
1521 mpc52xx_uart_int(int irq, void *dev_id)
1522 {
1523 struct uart_port *port = dev_id;
1524 irqreturn_t ret;
1525
1526 spin_lock(&port->lock);
1527
1528 ret = psc_ops->handle_irq(port);
1529
1530 spin_unlock(&port->lock);
1531
1532 return ret;
1533 }
1534
1535 /* ======================================================================== */
1536 /* Console ( if applicable ) */
1537 /* ======================================================================== */
1538
1539 #ifdef CONFIG_SERIAL_MPC52xx_CONSOLE
1540
1541 static void __init
1542 mpc52xx_console_get_options(struct uart_port *port,
1543 int *baud, int *parity, int *bits, int *flow)
1544 {
1545 unsigned char mr1;
1546
1547 pr_debug("mpc52xx_console_get_options(port=%p)\n", port);
1548
1549 /* Read the mode registers */
1550 mr1 = psc_ops->get_mr1(port);
1551
1552 /* CT{U,L}R are write-only ! */
1553 *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1554
1555 /* Parse them */
1556 switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) {
1557 case MPC52xx_PSC_MODE_5_BITS:
1558 *bits = 5;
1559 break;
1560 case MPC52xx_PSC_MODE_6_BITS:
1561 *bits = 6;
1562 break;
1563 case MPC52xx_PSC_MODE_7_BITS:
1564 *bits = 7;
1565 break;
1566 case MPC52xx_PSC_MODE_8_BITS:
1567 default:
1568 *bits = 8;
1569 }
1570
1571 if (mr1 & MPC52xx_PSC_MODE_PARNONE)
1572 *parity = 'n';
1573 else
1574 *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e';
1575 }
1576
1577 static void
1578 mpc52xx_console_write(struct console *co, const char *s, unsigned int count)
1579 {
1580 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1581 unsigned int i, j;
1582
1583 /* Disable interrupts */
1584 psc_ops->cw_disable_ints(port);
1585
1586 /* Wait the TX buffer to be empty */
1587 j = 5000000; /* Maximum wait */
1588 while (!mpc52xx_uart_tx_empty(port) && --j)
1589 udelay(1);
1590
1591 /* Write all the chars */
1592 for (i = 0; i < count; i++, s++) {
1593 /* Line return handling */
1594 if (*s == '\n')
1595 psc_ops->write_char(port, '\r');
1596
1597 /* Send the char */
1598 psc_ops->write_char(port, *s);
1599
1600 /* Wait the TX buffer to be empty */
1601 j = 20000; /* Maximum wait */
1602 while (!mpc52xx_uart_tx_empty(port) && --j)
1603 udelay(1);
1604 }
1605
1606 /* Restore interrupt state */
1607 psc_ops->cw_restore_ints(port);
1608 }
1609
1610
1611 static int __init
1612 mpc52xx_console_setup(struct console *co, char *options)
1613 {
1614 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1615 struct device_node *np = mpc52xx_uart_nodes[co->index];
1616 unsigned int uartclk;
1617 struct resource res;
1618 int ret;
1619
1620 int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1621 int bits = 8;
1622 int parity = 'n';
1623 int flow = 'n';
1624
1625 pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n",
1626 co, co->index, options);
1627
1628 if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) {
1629 pr_debug("PSC%x out of range\n", co->index);
1630 return -EINVAL;
1631 }
1632
1633 if (!np) {
1634 pr_debug("PSC%x not found in device tree\n", co->index);
1635 return -EINVAL;
1636 }
1637
1638 pr_debug("Console on ttyPSC%x is %pOF\n",
1639 co->index, mpc52xx_uart_nodes[co->index]);
1640
1641 /* Fetch register locations */
1642 ret = of_address_to_resource(np, 0, &res);
1643 if (ret) {
1644 pr_debug("Could not get resources for PSC%x\n", co->index);
1645 return ret;
1646 }
1647
1648 uartclk = mpc5xxx_get_bus_frequency(np);
1649 if (uartclk == 0) {
1650 pr_debug("Could not find uart clock frequency!\n");
1651 return -EINVAL;
1652 }
1653
1654 /* Basic port init. Needed since we use some uart_??? func before
1655 * real init for early access */
1656 spin_lock_init(&port->lock);
1657 port->uartclk = uartclk;
1658 port->ops = &mpc52xx_uart_ops;
1659 port->mapbase = res.start;
1660 port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc));
1661 port->irq = irq_of_parse_and_map(np, 0);
1662
1663 if (port->membase == NULL)
1664 return -EINVAL;
1665
1666 pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n",
1667 (void *)port->mapbase, port->membase,
1668 port->irq, port->uartclk);
1669
1670 /* Setup the port parameters accoding to options */
1671 if (options)
1672 uart_parse_options(options, &baud, &parity, &bits, &flow);
1673 else
1674 mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow);
1675
1676 pr_debug("Setting console parameters: %i %i%c1 flow=%c\n",
1677 baud, bits, parity, flow);
1678
1679 return uart_set_options(port, co, baud, parity, bits, flow);
1680 }
1681
1682
1683 static struct uart_driver mpc52xx_uart_driver;
1684
1685 static struct console mpc52xx_console = {
1686 .name = "ttyPSC",
1687 .write = mpc52xx_console_write,
1688 .device = uart_console_device,
1689 .setup = mpc52xx_console_setup,
1690 .flags = CON_PRINTBUFFER,
1691 .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */
1692 .data = &mpc52xx_uart_driver,
1693 };
1694
1695
1696 static int __init
1697 mpc52xx_console_init(void)
1698 {
1699 mpc52xx_uart_of_enumerate();
1700 register_console(&mpc52xx_console);
1701 return 0;
1702 }
1703
1704 console_initcall(mpc52xx_console_init);
1705
1706 #define MPC52xx_PSC_CONSOLE &mpc52xx_console
1707 #else
1708 #define MPC52xx_PSC_CONSOLE NULL
1709 #endif
1710
1711
1712 /* ======================================================================== */
1713 /* UART Driver */
1714 /* ======================================================================== */
1715
1716 static struct uart_driver mpc52xx_uart_driver = {
1717 .driver_name = "mpc52xx_psc_uart",
1718 .dev_name = "ttyPSC",
1719 .major = SERIAL_PSC_MAJOR,
1720 .minor = SERIAL_PSC_MINOR,
1721 .nr = MPC52xx_PSC_MAXNUM,
1722 .cons = MPC52xx_PSC_CONSOLE,
1723 };
1724
1725 /* ======================================================================== */
1726 /* OF Platform Driver */
1727 /* ======================================================================== */
1728
1729 static const struct of_device_id mpc52xx_uart_of_match[] = {
1730 #ifdef CONFIG_PPC_MPC52xx
1731 { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, },
1732 { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1733 /* binding used by old lite5200 device trees: */
1734 { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1735 /* binding used by efika: */
1736 { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, },
1737 #endif
1738 #ifdef CONFIG_PPC_MPC512x
1739 { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, },
1740 { .compatible = "fsl,mpc5125-psc-uart", .data = &mpc5125_psc_ops, },
1741 #endif
1742 {},
1743 };
1744
1745 static int mpc52xx_uart_of_probe(struct platform_device *op)
1746 {
1747 int idx = -1;
1748 unsigned int uartclk;
1749 struct uart_port *port = NULL;
1750 struct resource res;
1751 int ret;
1752
1753 /* Check validity & presence */
1754 for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++)
1755 if (mpc52xx_uart_nodes[idx] == op->dev.of_node)
1756 break;
1757 if (idx >= MPC52xx_PSC_MAXNUM)
1758 return -EINVAL;
1759 pr_debug("Found %pOF assigned to ttyPSC%x\n",
1760 mpc52xx_uart_nodes[idx], idx);
1761
1762 /* set the uart clock to the input clock of the psc, the different
1763 * prescalers are taken into account in the set_baudrate() methods
1764 * of the respective chip */
1765 uartclk = mpc5xxx_get_bus_frequency(op->dev.of_node);
1766 if (uartclk == 0) {
1767 dev_dbg(&op->dev, "Could not find uart clock frequency!\n");
1768 return -EINVAL;
1769 }
1770
1771 /* Init the port structure */
1772 port = &mpc52xx_uart_ports[idx];
1773
1774 spin_lock_init(&port->lock);
1775 port->uartclk = uartclk;
1776 port->fifosize = 512;
1777 port->iotype = UPIO_MEM;
1778 port->flags = UPF_BOOT_AUTOCONF |
1779 (uart_console(port) ? 0 : UPF_IOREMAP);
1780 port->line = idx;
1781 port->ops = &mpc52xx_uart_ops;
1782 port->dev = &op->dev;
1783
1784 /* Search for IRQ and mapbase */
1785 ret = of_address_to_resource(op->dev.of_node, 0, &res);
1786 if (ret)
1787 return ret;
1788
1789 port->mapbase = res.start;
1790 if (!port->mapbase) {
1791 dev_dbg(&op->dev, "Could not allocate resources for PSC\n");
1792 return -EINVAL;
1793 }
1794
1795 psc_ops->get_irq(port, op->dev.of_node);
1796 if (port->irq == 0) {
1797 dev_dbg(&op->dev, "Could not get irq\n");
1798 return -EINVAL;
1799 }
1800
1801 dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n",
1802 (void *)port->mapbase, port->irq, port->uartclk);
1803
1804 /* Add the port to the uart sub-system */
1805 ret = uart_add_one_port(&mpc52xx_uart_driver, port);
1806 if (ret)
1807 return ret;
1808
1809 platform_set_drvdata(op, (void *)port);
1810 return 0;
1811 }
1812
1813 static int
1814 mpc52xx_uart_of_remove(struct platform_device *op)
1815 {
1816 struct uart_port *port = platform_get_drvdata(op);
1817
1818 if (port)
1819 uart_remove_one_port(&mpc52xx_uart_driver, port);
1820
1821 return 0;
1822 }
1823
1824 #ifdef CONFIG_PM
1825 static int
1826 mpc52xx_uart_of_suspend(struct platform_device *op, pm_message_t state)
1827 {
1828 struct uart_port *port = platform_get_drvdata(op);
1829
1830 if (port)
1831 uart_suspend_port(&mpc52xx_uart_driver, port);
1832
1833 return 0;
1834 }
1835
1836 static int
1837 mpc52xx_uart_of_resume(struct platform_device *op)
1838 {
1839 struct uart_port *port = platform_get_drvdata(op);
1840
1841 if (port)
1842 uart_resume_port(&mpc52xx_uart_driver, port);
1843
1844 return 0;
1845 }
1846 #endif
1847
1848 static void
1849 mpc52xx_uart_of_assign(struct device_node *np)
1850 {
1851 int i;
1852
1853 /* Find the first free PSC number */
1854 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1855 if (mpc52xx_uart_nodes[i] == NULL) {
1856 of_node_get(np);
1857 mpc52xx_uart_nodes[i] = np;
1858 return;
1859 }
1860 }
1861 }
1862
1863 static void
1864 mpc52xx_uart_of_enumerate(void)
1865 {
1866 static int enum_done;
1867 struct device_node *np;
1868 const struct of_device_id *match;
1869 int i;
1870
1871 if (enum_done)
1872 return;
1873
1874 /* Assign index to each PSC in device tree */
1875 for_each_matching_node(np, mpc52xx_uart_of_match) {
1876 match = of_match_node(mpc52xx_uart_of_match, np);
1877 psc_ops = match->data;
1878 mpc52xx_uart_of_assign(np);
1879 }
1880
1881 enum_done = 1;
1882
1883 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1884 if (mpc52xx_uart_nodes[i])
1885 pr_debug("%pOF assigned to ttyPSC%x\n",
1886 mpc52xx_uart_nodes[i], i);
1887 }
1888 }
1889
1890 MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match);
1891
1892 static struct platform_driver mpc52xx_uart_of_driver = {
1893 .probe = mpc52xx_uart_of_probe,
1894 .remove = mpc52xx_uart_of_remove,
1895 #ifdef CONFIG_PM
1896 .suspend = mpc52xx_uart_of_suspend,
1897 .resume = mpc52xx_uart_of_resume,
1898 #endif
1899 .driver = {
1900 .name = "mpc52xx-psc-uart",
1901 .of_match_table = mpc52xx_uart_of_match,
1902 },
1903 };
1904
1905
1906 /* ======================================================================== */
1907 /* Module */
1908 /* ======================================================================== */
1909
1910 static int __init
1911 mpc52xx_uart_init(void)
1912 {
1913 int ret;
1914
1915 printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n");
1916
1917 ret = uart_register_driver(&mpc52xx_uart_driver);
1918 if (ret) {
1919 printk(KERN_ERR "%s: uart_register_driver failed (%i)\n",
1920 __FILE__, ret);
1921 return ret;
1922 }
1923
1924 mpc52xx_uart_of_enumerate();
1925
1926 /*
1927 * Map the PSC FIFO Controller and init if on MPC512x.
1928 */
1929 if (psc_ops && psc_ops->fifoc_init) {
1930 ret = psc_ops->fifoc_init();
1931 if (ret)
1932 goto err_init;
1933 }
1934
1935 ret = platform_driver_register(&mpc52xx_uart_of_driver);
1936 if (ret) {
1937 printk(KERN_ERR "%s: platform_driver_register failed (%i)\n",
1938 __FILE__, ret);
1939 goto err_reg;
1940 }
1941
1942 return 0;
1943 err_reg:
1944 if (psc_ops && psc_ops->fifoc_uninit)
1945 psc_ops->fifoc_uninit();
1946 err_init:
1947 uart_unregister_driver(&mpc52xx_uart_driver);
1948 return ret;
1949 }
1950
1951 static void __exit
1952 mpc52xx_uart_exit(void)
1953 {
1954 if (psc_ops->fifoc_uninit)
1955 psc_ops->fifoc_uninit();
1956
1957 platform_driver_unregister(&mpc52xx_uart_of_driver);
1958 uart_unregister_driver(&mpc52xx_uart_driver);
1959 }
1960
1961
1962 module_init(mpc52xx_uart_init);
1963 module_exit(mpc52xx_uart_exit);
1964
1965 MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
1966 MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");
1967 MODULE_LICENSE("GPL");
ubuntu-bionic-kernel mirror