2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 *This program is free software; you can redistribute it and/or modify
5 *it under the terms of the GNU General Public License as published by
6 *the Free Software Foundation; version 2 of the License.
8 *This program is distributed in the hope that it will be useful,
9 *but WITHOUT ANY WARRANTY; without even the implied warranty of
10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 *GNU General Public License for more details.
13 *You should have received a copy of the GNU General Public License
14 *along with this program; if not, write to the Free Software
15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20 #include <linux/kernel.h>
21 #include <linux/serial_reg.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/console.h>
26 #include <linux/serial_core.h>
27 #include <linux/tty.h>
28 #include <linux/tty_flip.h>
29 #include <linux/interrupt.h>
31 #include <linux/dmi.h>
32 #include <linux/nmi.h>
33 #include <linux/delay.h>
35 #include <linux/debugfs.h>
36 #include <linux/dmaengine.h>
37 #include <linux/pch_dma.h>
40 PCH_UART_HANDLED_RX_INT_SHIFT
,
41 PCH_UART_HANDLED_TX_INT_SHIFT
,
42 PCH_UART_HANDLED_RX_ERR_INT_SHIFT
,
43 PCH_UART_HANDLED_RX_TRG_INT_SHIFT
,
44 PCH_UART_HANDLED_MS_INT_SHIFT
,
45 PCH_UART_HANDLED_LS_INT_SHIFT
,
53 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
55 /* Set the max number of UART port
56 * Intel EG20T PCH: 4 port
57 * LAPIS Semiconductor ML7213 IOH: 3 port
58 * LAPIS Semiconductor ML7223 IOH: 2 port
62 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
63 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
64 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
65 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
66 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
67 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
68 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
70 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
72 #define PCH_UART_RBR 0x00
73 #define PCH_UART_THR 0x00
75 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
76 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
77 #define PCH_UART_IER_ERBFI 0x00000001
78 #define PCH_UART_IER_ETBEI 0x00000002
79 #define PCH_UART_IER_ELSI 0x00000004
80 #define PCH_UART_IER_EDSSI 0x00000008
82 #define PCH_UART_IIR_IP 0x00000001
83 #define PCH_UART_IIR_IID 0x00000006
84 #define PCH_UART_IIR_MSI 0x00000000
85 #define PCH_UART_IIR_TRI 0x00000002
86 #define PCH_UART_IIR_RRI 0x00000004
87 #define PCH_UART_IIR_REI 0x00000006
88 #define PCH_UART_IIR_TOI 0x00000008
89 #define PCH_UART_IIR_FIFO256 0x00000020
90 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
91 #define PCH_UART_IIR_FE 0x000000C0
93 #define PCH_UART_FCR_FIFOE 0x00000001
94 #define PCH_UART_FCR_RFR 0x00000002
95 #define PCH_UART_FCR_TFR 0x00000004
96 #define PCH_UART_FCR_DMS 0x00000008
97 #define PCH_UART_FCR_FIFO256 0x00000020
98 #define PCH_UART_FCR_RFTL 0x000000C0
100 #define PCH_UART_FCR_RFTL1 0x00000000
101 #define PCH_UART_FCR_RFTL64 0x00000040
102 #define PCH_UART_FCR_RFTL128 0x00000080
103 #define PCH_UART_FCR_RFTL224 0x000000C0
104 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
105 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
106 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
107 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
108 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
109 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
110 #define PCH_UART_FCR_RFTL_SHIFT 6
112 #define PCH_UART_LCR_WLS 0x00000003
113 #define PCH_UART_LCR_STB 0x00000004
114 #define PCH_UART_LCR_PEN 0x00000008
115 #define PCH_UART_LCR_EPS 0x00000010
116 #define PCH_UART_LCR_SP 0x00000020
117 #define PCH_UART_LCR_SB 0x00000040
118 #define PCH_UART_LCR_DLAB 0x00000080
119 #define PCH_UART_LCR_NP 0x00000000
120 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN
121 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
122 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
123 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
126 #define PCH_UART_LCR_5BIT 0x00000000
127 #define PCH_UART_LCR_6BIT 0x00000001
128 #define PCH_UART_LCR_7BIT 0x00000002
129 #define PCH_UART_LCR_8BIT 0x00000003
131 #define PCH_UART_MCR_DTR 0x00000001
132 #define PCH_UART_MCR_RTS 0x00000002
133 #define PCH_UART_MCR_OUT 0x0000000C
134 #define PCH_UART_MCR_LOOP 0x00000010
135 #define PCH_UART_MCR_AFE 0x00000020
137 #define PCH_UART_LSR_DR 0x00000001
138 #define PCH_UART_LSR_ERR (1<<7)
140 #define PCH_UART_MSR_DCTS 0x00000001
141 #define PCH_UART_MSR_DDSR 0x00000002
142 #define PCH_UART_MSR_TERI 0x00000004
143 #define PCH_UART_MSR_DDCD 0x00000008
144 #define PCH_UART_MSR_CTS 0x00000010
145 #define PCH_UART_MSR_DSR 0x00000020
146 #define PCH_UART_MSR_RI 0x00000040
147 #define PCH_UART_MSR_DCD 0x00000080
148 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
149 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
151 #define PCH_UART_DLL 0x00
152 #define PCH_UART_DLM 0x01
154 #define PCH_UART_BRCSR 0x0E
156 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
157 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
158 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
159 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
160 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
162 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
163 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
164 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
165 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
166 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
167 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
168 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
169 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
170 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
171 #define PCH_UART_HAL_STB1 0
172 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
174 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
175 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
176 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
177 PCH_UART_HAL_CLR_RX_FIFO)
179 #define PCH_UART_HAL_DMA_MODE0 0
180 #define PCH_UART_HAL_FIFO_DIS 0
181 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
182 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
183 PCH_UART_FCR_FIFO256)
184 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
185 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
186 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
187 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
188 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
189 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
190 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
191 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
192 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
193 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
194 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
195 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
196 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
197 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
199 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
200 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
201 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
202 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
203 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
205 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
206 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
207 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
208 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
209 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
211 #define PCI_VENDOR_ID_ROHM 0x10DB
213 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
215 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */
216 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */
217 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */
218 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */
219 #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */
220 #define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */
222 struct pch_uart_buffer
{
228 struct uart_port port
;
230 void __iomem
*membase
;
231 resource_size_t mapbase
;
233 struct pci_dev
*pdev
;
235 unsigned int uartclk
;
241 struct pch_uart_buffer rxbuf
;
245 unsigned int use_dma
;
246 struct dma_async_tx_descriptor
*desc_tx
;
247 struct dma_async_tx_descriptor
*desc_rx
;
248 struct pch_dma_slave param_tx
;
249 struct pch_dma_slave param_rx
;
250 struct dma_chan
*chan_tx
;
251 struct dma_chan
*chan_rx
;
252 struct scatterlist
*sg_tx_p
;
254 struct scatterlist sg_rx
;
257 dma_addr_t rx_buf_dma
;
259 struct dentry
*debugfs
;
261 /* protect the eg20t_port private structure and io access to membase */
266 * struct pch_uart_driver_data - private data structure for UART-DMA
267 * @port_type: The number of DMA channel
268 * @line_no: UART port line number (0, 1, 2...)
270 struct pch_uart_driver_data
{
275 enum pch_uart_num_t
{
289 static struct pch_uart_driver_data drv_dat
[] = {
290 [pch_et20t_uart0
] = {PCH_UART_8LINE
, 0},
291 [pch_et20t_uart1
] = {PCH_UART_2LINE
, 1},
292 [pch_et20t_uart2
] = {PCH_UART_2LINE
, 2},
293 [pch_et20t_uart3
] = {PCH_UART_2LINE
, 3},
294 [pch_ml7213_uart0
] = {PCH_UART_8LINE
, 0},
295 [pch_ml7213_uart1
] = {PCH_UART_2LINE
, 1},
296 [pch_ml7213_uart2
] = {PCH_UART_2LINE
, 2},
297 [pch_ml7223_uart0
] = {PCH_UART_8LINE
, 0},
298 [pch_ml7223_uart1
] = {PCH_UART_2LINE
, 1},
299 [pch_ml7831_uart0
] = {PCH_UART_8LINE
, 0},
300 [pch_ml7831_uart1
] = {PCH_UART_2LINE
, 1},
303 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
304 static struct eg20t_port
*pch_uart_ports
[PCH_UART_NR
];
306 static unsigned int default_baud
= 9600;
307 static unsigned int user_uartclk
= 0;
308 static const int trigger_level_256
[4] = { 1, 64, 128, 224 };
309 static const int trigger_level_64
[4] = { 1, 16, 32, 56 };
310 static const int trigger_level_16
[4] = { 1, 4, 8, 14 };
311 static const int trigger_level_1
[4] = { 1, 1, 1, 1 };
313 #ifdef CONFIG_DEBUG_FS
315 #define PCH_REGS_BUFSIZE 1024
318 static ssize_t
port_show_regs(struct file
*file
, char __user
*user_buf
,
319 size_t count
, loff_t
*ppos
)
321 struct eg20t_port
*priv
= file
->private_data
;
327 buf
= kzalloc(PCH_REGS_BUFSIZE
, GFP_KERNEL
);
331 len
+= snprintf(buf
+ len
, PCH_REGS_BUFSIZE
- len
,
332 "PCH EG20T port[%d] regs:\n", priv
->port
.line
);
334 len
+= snprintf(buf
+ len
, PCH_REGS_BUFSIZE
- len
,
335 "=================================\n");
336 len
+= snprintf(buf
+ len
, PCH_REGS_BUFSIZE
- len
,
337 "IER: \t0x%02x\n", ioread8(priv
->membase
+ UART_IER
));
338 len
+= snprintf(buf
+ len
, PCH_REGS_BUFSIZE
- len
,
339 "IIR: \t0x%02x\n", ioread8(priv
->membase
+ UART_IIR
));
340 len
+= snprintf(buf
+ len
, PCH_REGS_BUFSIZE
- len
,
341 "LCR: \t0x%02x\n", ioread8(priv
->membase
+ UART_LCR
));
342 len
+= snprintf(buf
+ len
, PCH_REGS_BUFSIZE
- len
,
343 "MCR: \t0x%02x\n", ioread8(priv
->membase
+ UART_MCR
));
344 len
+= snprintf(buf
+ len
, PCH_REGS_BUFSIZE
- len
,
345 "LSR: \t0x%02x\n", ioread8(priv
->membase
+ UART_LSR
));
346 len
+= snprintf(buf
+ len
, PCH_REGS_BUFSIZE
- len
,
347 "MSR: \t0x%02x\n", ioread8(priv
->membase
+ UART_MSR
));
348 len
+= snprintf(buf
+ len
, PCH_REGS_BUFSIZE
- len
,
350 ioread8(priv
->membase
+ PCH_UART_BRCSR
));
352 lcr
= ioread8(priv
->membase
+ UART_LCR
);
353 iowrite8(PCH_UART_LCR_DLAB
, priv
->membase
+ UART_LCR
);
354 len
+= snprintf(buf
+ len
, PCH_REGS_BUFSIZE
- len
,
355 "DLL: \t0x%02x\n", ioread8(priv
->membase
+ UART_DLL
));
356 len
+= snprintf(buf
+ len
, PCH_REGS_BUFSIZE
- len
,
357 "DLM: \t0x%02x\n", ioread8(priv
->membase
+ UART_DLM
));
358 iowrite8(lcr
, priv
->membase
+ UART_LCR
);
360 if (len
> PCH_REGS_BUFSIZE
)
361 len
= PCH_REGS_BUFSIZE
;
363 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
368 static const struct file_operations port_regs_ops
= {
369 .owner
= THIS_MODULE
,
371 .read
= port_show_regs
,
372 .llseek
= default_llseek
,
374 #endif /* CONFIG_DEBUG_FS */
376 static struct dmi_system_id pch_uart_dmi_table
[] = {
380 DMI_MATCH(DMI_BOARD_NAME
, "CM-iTC"),
382 (void *)CMITC_UARTCLK
,
387 DMI_MATCH(DMI_BIOS_VERSION
, "FRI2"),
389 (void *)FRI2_64_UARTCLK
,
392 .ident
= "Fish River Island II",
394 DMI_MATCH(DMI_PRODUCT_NAME
, "Fish River Island II"),
396 (void *)FRI2_48_UARTCLK
,
401 DMI_MATCH(DMI_BOARD_NAME
, "COMe-mTT"),
403 (void *)NTC1_UARTCLK
,
406 .ident
= "nanoETXexpress-TT",
408 DMI_MATCH(DMI_BOARD_NAME
, "nanoETXexpress-TT"),
410 (void *)NTC1_UARTCLK
,
413 .ident
= "MinnowBoard",
415 DMI_MATCH(DMI_BOARD_NAME
, "MinnowBoard"),
417 (void *)MINNOW_UARTCLK
,
421 /* Return UART clock, checking for board specific clocks. */
422 static unsigned int pch_uart_get_uartclk(void)
424 const struct dmi_system_id
*d
;
429 d
= dmi_first_match(pch_uart_dmi_table
);
431 return (unsigned long)d
->driver_data
;
433 return DEFAULT_UARTCLK
;
436 static void pch_uart_hal_enable_interrupt(struct eg20t_port
*priv
,
439 u8 ier
= ioread8(priv
->membase
+ UART_IER
);
440 ier
|= flag
& PCH_UART_IER_MASK
;
441 iowrite8(ier
, priv
->membase
+ UART_IER
);
444 static void pch_uart_hal_disable_interrupt(struct eg20t_port
*priv
,
447 u8 ier
= ioread8(priv
->membase
+ UART_IER
);
448 ier
&= ~(flag
& PCH_UART_IER_MASK
);
449 iowrite8(ier
, priv
->membase
+ UART_IER
);
452 static int pch_uart_hal_set_line(struct eg20t_port
*priv
, unsigned int baud
,
453 unsigned int parity
, unsigned int bits
,
456 unsigned int dll
, dlm
, lcr
;
459 div
= DIV_ROUND_CLOSEST(priv
->uartclk
/ 16, baud
);
460 if (div
< 0 || USHRT_MAX
<= div
) {
461 dev_err(priv
->port
.dev
, "Invalid Baud(div=0x%x)\n", div
);
465 dll
= (unsigned int)div
& 0x00FFU
;
466 dlm
= ((unsigned int)div
>> 8) & 0x00FFU
;
468 if (parity
& ~(PCH_UART_LCR_PEN
| PCH_UART_LCR_EPS
| PCH_UART_LCR_SP
)) {
469 dev_err(priv
->port
.dev
, "Invalid parity(0x%x)\n", parity
);
473 if (bits
& ~PCH_UART_LCR_WLS
) {
474 dev_err(priv
->port
.dev
, "Invalid bits(0x%x)\n", bits
);
478 if (stb
& ~PCH_UART_LCR_STB
) {
479 dev_err(priv
->port
.dev
, "Invalid STB(0x%x)\n", stb
);
487 dev_dbg(priv
->port
.dev
, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
488 __func__
, baud
, div
, lcr
, jiffies
);
489 iowrite8(PCH_UART_LCR_DLAB
, priv
->membase
+ UART_LCR
);
490 iowrite8(dll
, priv
->membase
+ PCH_UART_DLL
);
491 iowrite8(dlm
, priv
->membase
+ PCH_UART_DLM
);
492 iowrite8(lcr
, priv
->membase
+ UART_LCR
);
497 static int pch_uart_hal_fifo_reset(struct eg20t_port
*priv
,
500 if (flag
& ~(PCH_UART_FCR_TFR
| PCH_UART_FCR_RFR
)) {
501 dev_err(priv
->port
.dev
, "%s:Invalid flag(0x%x)\n",
506 iowrite8(PCH_UART_FCR_FIFOE
| priv
->fcr
, priv
->membase
+ UART_FCR
);
507 iowrite8(PCH_UART_FCR_FIFOE
| priv
->fcr
| flag
,
508 priv
->membase
+ UART_FCR
);
509 iowrite8(priv
->fcr
, priv
->membase
+ UART_FCR
);
514 static int pch_uart_hal_set_fifo(struct eg20t_port
*priv
,
515 unsigned int dmamode
,
516 unsigned int fifo_size
, unsigned int trigger
)
520 if (dmamode
& ~PCH_UART_FCR_DMS
) {
521 dev_err(priv
->port
.dev
, "%s:Invalid DMA Mode(0x%x)\n",
526 if (fifo_size
& ~(PCH_UART_FCR_FIFOE
| PCH_UART_FCR_FIFO256
)) {
527 dev_err(priv
->port
.dev
, "%s:Invalid FIFO SIZE(0x%x)\n",
528 __func__
, fifo_size
);
532 if (trigger
& ~PCH_UART_FCR_RFTL
) {
533 dev_err(priv
->port
.dev
, "%s:Invalid TRIGGER(0x%x)\n",
538 switch (priv
->fifo_size
) {
540 priv
->trigger_level
=
541 trigger_level_256
[trigger
>> PCH_UART_FCR_RFTL_SHIFT
];
544 priv
->trigger_level
=
545 trigger_level_64
[trigger
>> PCH_UART_FCR_RFTL_SHIFT
];
548 priv
->trigger_level
=
549 trigger_level_16
[trigger
>> PCH_UART_FCR_RFTL_SHIFT
];
552 priv
->trigger_level
=
553 trigger_level_1
[trigger
>> PCH_UART_FCR_RFTL_SHIFT
];
557 dmamode
| fifo_size
| trigger
| PCH_UART_FCR_RFR
| PCH_UART_FCR_TFR
;
558 iowrite8(PCH_UART_FCR_FIFOE
, priv
->membase
+ UART_FCR
);
559 iowrite8(PCH_UART_FCR_FIFOE
| PCH_UART_FCR_RFR
| PCH_UART_FCR_TFR
,
560 priv
->membase
+ UART_FCR
);
561 iowrite8(fcr
, priv
->membase
+ UART_FCR
);
567 static u8
pch_uart_hal_get_modem(struct eg20t_port
*priv
)
569 unsigned int msr
= ioread8(priv
->membase
+ UART_MSR
);
570 priv
->dmsr
= msr
& PCH_UART_MSR_DELTA
;
574 static void pch_uart_hal_write(struct eg20t_port
*priv
,
575 const unsigned char *buf
, int tx_size
)
580 for (i
= 0; i
< tx_size
;) {
582 iowrite8(thr
, priv
->membase
+ PCH_UART_THR
);
586 static int pch_uart_hal_read(struct eg20t_port
*priv
, unsigned char *buf
,
591 struct uart_port
*port
= &priv
->port
;
593 lsr
= ioread8(priv
->membase
+ UART_LSR
);
594 for (i
= 0, lsr
= ioread8(priv
->membase
+ UART_LSR
);
595 i
< rx_size
&& lsr
& (UART_LSR_DR
| UART_LSR_BI
);
596 lsr
= ioread8(priv
->membase
+ UART_LSR
)) {
597 rbr
= ioread8(priv
->membase
+ PCH_UART_RBR
);
599 if (lsr
& UART_LSR_BI
) {
601 if (uart_handle_break(port
))
606 if (uart_handle_sysrq_char(port
, rbr
))
616 static unsigned char pch_uart_hal_get_iid(struct eg20t_port
*priv
)
618 return ioread8(priv
->membase
+ UART_IIR
) &\
619 (PCH_UART_IIR_IID
| PCH_UART_IIR_TOI
| PCH_UART_IIR_IP
);
622 static u8
pch_uart_hal_get_line_status(struct eg20t_port
*priv
)
624 return ioread8(priv
->membase
+ UART_LSR
);
627 static void pch_uart_hal_set_break(struct eg20t_port
*priv
, int on
)
631 lcr
= ioread8(priv
->membase
+ UART_LCR
);
633 lcr
|= PCH_UART_LCR_SB
;
635 lcr
&= ~PCH_UART_LCR_SB
;
637 iowrite8(lcr
, priv
->membase
+ UART_LCR
);
640 static int push_rx(struct eg20t_port
*priv
, const unsigned char *buf
,
643 struct uart_port
*port
= &priv
->port
;
644 struct tty_port
*tport
= &port
->state
->port
;
646 tty_insert_flip_string(tport
, buf
, size
);
647 tty_flip_buffer_push(tport
);
652 static int pop_tx_x(struct eg20t_port
*priv
, unsigned char *buf
)
655 struct uart_port
*port
= &priv
->port
;
658 dev_dbg(priv
->port
.dev
, "%s:X character send %02x (%lu)\n",
659 __func__
, port
->x_char
, jiffies
);
660 buf
[0] = port
->x_char
;
668 static int dma_push_rx(struct eg20t_port
*priv
, int size
)
670 struct tty_struct
*tty
;
672 struct uart_port
*port
= &priv
->port
;
673 struct tty_port
*tport
= &port
->state
->port
;
676 tty
= tty_port_tty_get(tport
);
678 dev_dbg(priv
->port
.dev
, "%s:tty is busy now", __func__
);
682 room
= tty_buffer_request_room(tport
, size
);
685 dev_warn(port
->dev
, "Rx overrun: dropping %u bytes\n",
690 tty_insert_flip_string(tport
, sg_virt(&priv
->sg_rx
), size
);
692 port
->icount
.rx
+= room
;
698 static void pch_free_dma(struct uart_port
*port
)
700 struct eg20t_port
*priv
;
701 priv
= container_of(port
, struct eg20t_port
, port
);
704 dma_release_channel(priv
->chan_tx
);
705 priv
->chan_tx
= NULL
;
708 dma_release_channel(priv
->chan_rx
);
709 priv
->chan_rx
= NULL
;
712 if (priv
->rx_buf_dma
) {
713 dma_free_coherent(port
->dev
, port
->fifosize
, priv
->rx_buf_virt
,
715 priv
->rx_buf_virt
= NULL
;
716 priv
->rx_buf_dma
= 0;
722 static bool filter(struct dma_chan
*chan
, void *slave
)
724 struct pch_dma_slave
*param
= slave
;
726 if ((chan
->chan_id
== param
->chan_id
) && (param
->dma_dev
==
727 chan
->device
->dev
)) {
728 chan
->private = param
;
735 static void pch_request_dma(struct uart_port
*port
)
738 struct dma_chan
*chan
;
739 struct pci_dev
*dma_dev
;
740 struct pch_dma_slave
*param
;
741 struct eg20t_port
*priv
=
742 container_of(port
, struct eg20t_port
, port
);
744 dma_cap_set(DMA_SLAVE
, mask
);
746 dma_dev
= pci_get_bus_and_slot(priv
->pdev
->bus
->number
,
747 PCI_DEVFN(0xa, 0)); /* Get DMA's dev
750 param
= &priv
->param_tx
;
751 param
->dma_dev
= &dma_dev
->dev
;
752 param
->chan_id
= priv
->port
.line
* 2; /* Tx = 0, 2, 4, ... */
754 param
->tx_reg
= port
->mapbase
+ UART_TX
;
755 chan
= dma_request_channel(mask
, filter
, param
);
757 dev_err(priv
->port
.dev
, "%s:dma_request_channel FAILS(Tx)\n",
761 priv
->chan_tx
= chan
;
764 param
= &priv
->param_rx
;
765 param
->dma_dev
= &dma_dev
->dev
;
766 param
->chan_id
= priv
->port
.line
* 2 + 1; /* Rx = Tx + 1 */
768 param
->rx_reg
= port
->mapbase
+ UART_RX
;
769 chan
= dma_request_channel(mask
, filter
, param
);
771 dev_err(priv
->port
.dev
, "%s:dma_request_channel FAILS(Rx)\n",
773 dma_release_channel(priv
->chan_tx
);
774 priv
->chan_tx
= NULL
;
778 /* Get Consistent memory for DMA */
779 priv
->rx_buf_virt
= dma_alloc_coherent(port
->dev
, port
->fifosize
,
780 &priv
->rx_buf_dma
, GFP_KERNEL
);
781 priv
->chan_rx
= chan
;
784 static void pch_dma_rx_complete(void *arg
)
786 struct eg20t_port
*priv
= arg
;
787 struct uart_port
*port
= &priv
->port
;
790 dma_sync_sg_for_cpu(port
->dev
, &priv
->sg_rx
, 1, DMA_FROM_DEVICE
);
791 count
= dma_push_rx(priv
, priv
->trigger_level
);
793 tty_flip_buffer_push(&port
->state
->port
);
794 async_tx_ack(priv
->desc_rx
);
795 pch_uart_hal_enable_interrupt(priv
, PCH_UART_HAL_RX_INT
|
796 PCH_UART_HAL_RX_ERR_INT
);
799 static void pch_dma_tx_complete(void *arg
)
801 struct eg20t_port
*priv
= arg
;
802 struct uart_port
*port
= &priv
->port
;
803 struct circ_buf
*xmit
= &port
->state
->xmit
;
804 struct scatterlist
*sg
= priv
->sg_tx_p
;
807 for (i
= 0; i
< priv
->nent
; i
++, sg
++) {
808 xmit
->tail
+= sg_dma_len(sg
);
809 port
->icount
.tx
+= sg_dma_len(sg
);
811 xmit
->tail
&= UART_XMIT_SIZE
- 1;
812 async_tx_ack(priv
->desc_tx
);
813 dma_unmap_sg(port
->dev
, sg
, priv
->nent
, DMA_TO_DEVICE
);
814 priv
->tx_dma_use
= 0;
816 kfree(priv
->sg_tx_p
);
817 pch_uart_hal_enable_interrupt(priv
, PCH_UART_HAL_TX_INT
);
820 static int pop_tx(struct eg20t_port
*priv
, int size
)
823 struct uart_port
*port
= &priv
->port
;
824 struct circ_buf
*xmit
= &port
->state
->xmit
;
826 if (uart_tx_stopped(port
) || uart_circ_empty(xmit
) || count
>= size
)
831 CIRC_CNT_TO_END(xmit
->head
, xmit
->tail
, UART_XMIT_SIZE
);
832 int sz
= min(size
- count
, cnt_to_end
);
833 pch_uart_hal_write(priv
, &xmit
->buf
[xmit
->tail
], sz
);
834 xmit
->tail
= (xmit
->tail
+ sz
) & (UART_XMIT_SIZE
- 1);
836 } while (!uart_circ_empty(xmit
) && count
< size
);
839 dev_dbg(priv
->port
.dev
, "%d characters. Remained %d characters.(%lu)\n",
840 count
, size
- count
, jiffies
);
845 static int handle_rx_to(struct eg20t_port
*priv
)
847 struct pch_uart_buffer
*buf
;
850 if (!priv
->start_rx
) {
851 pch_uart_hal_disable_interrupt(priv
, PCH_UART_HAL_RX_INT
|
852 PCH_UART_HAL_RX_ERR_INT
);
857 rx_size
= pch_uart_hal_read(priv
, buf
->buf
, buf
->size
);
858 ret
= push_rx(priv
, buf
->buf
, rx_size
);
861 } while (rx_size
== buf
->size
);
863 return PCH_UART_HANDLED_RX_INT
;
866 static int handle_rx(struct eg20t_port
*priv
)
868 return handle_rx_to(priv
);
871 static int dma_handle_rx(struct eg20t_port
*priv
)
873 struct uart_port
*port
= &priv
->port
;
874 struct dma_async_tx_descriptor
*desc
;
875 struct scatterlist
*sg
;
877 priv
= container_of(port
, struct eg20t_port
, port
);
880 sg_init_table(&priv
->sg_rx
, 1); /* Initialize SG table */
882 sg_dma_len(sg
) = priv
->trigger_level
;
884 sg_set_page(&priv
->sg_rx
, virt_to_page(priv
->rx_buf_virt
),
885 sg_dma_len(sg
), (unsigned long)priv
->rx_buf_virt
&
888 sg_dma_address(sg
) = priv
->rx_buf_dma
;
890 desc
= dmaengine_prep_slave_sg(priv
->chan_rx
,
891 sg
, 1, DMA_DEV_TO_MEM
,
892 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
897 priv
->desc_rx
= desc
;
898 desc
->callback
= pch_dma_rx_complete
;
899 desc
->callback_param
= priv
;
900 desc
->tx_submit(desc
);
901 dma_async_issue_pending(priv
->chan_rx
);
903 return PCH_UART_HANDLED_RX_INT
;
906 static unsigned int handle_tx(struct eg20t_port
*priv
)
908 struct uart_port
*port
= &priv
->port
;
909 struct circ_buf
*xmit
= &port
->state
->xmit
;
915 if (!priv
->start_tx
) {
916 dev_info(priv
->port
.dev
, "%s:Tx isn't started. (%lu)\n",
918 pch_uart_hal_disable_interrupt(priv
, PCH_UART_HAL_TX_INT
);
923 fifo_size
= max(priv
->fifo_size
, 1);
925 if (pop_tx_x(priv
, xmit
->buf
)) {
926 pch_uart_hal_write(priv
, xmit
->buf
, 1);
931 size
= min(xmit
->head
- xmit
->tail
, fifo_size
);
935 tx_size
= pop_tx(priv
, size
);
937 port
->icount
.tx
+= tx_size
;
941 priv
->tx_empty
= tx_empty
;
944 pch_uart_hal_disable_interrupt(priv
, PCH_UART_HAL_TX_INT
);
945 uart_write_wakeup(port
);
948 return PCH_UART_HANDLED_TX_INT
;
951 static unsigned int dma_handle_tx(struct eg20t_port
*priv
)
953 struct uart_port
*port
= &priv
->port
;
954 struct circ_buf
*xmit
= &port
->state
->xmit
;
955 struct scatterlist
*sg
;
959 struct dma_async_tx_descriptor
*desc
;
966 if (!priv
->start_tx
) {
967 dev_info(priv
->port
.dev
, "%s:Tx isn't started. (%lu)\n",
969 pch_uart_hal_disable_interrupt(priv
, PCH_UART_HAL_TX_INT
);
974 if (priv
->tx_dma_use
) {
975 dev_dbg(priv
->port
.dev
, "%s:Tx is not completed. (%lu)\n",
977 pch_uart_hal_disable_interrupt(priv
, PCH_UART_HAL_TX_INT
);
982 fifo_size
= max(priv
->fifo_size
, 1);
984 if (pop_tx_x(priv
, xmit
->buf
)) {
985 pch_uart_hal_write(priv
, xmit
->buf
, 1);
991 bytes
= min((int)CIRC_CNT(xmit
->head
, xmit
->tail
,
992 UART_XMIT_SIZE
), CIRC_CNT_TO_END(xmit
->head
,
993 xmit
->tail
, UART_XMIT_SIZE
));
995 dev_dbg(priv
->port
.dev
, "%s 0 bytes return\n", __func__
);
996 pch_uart_hal_disable_interrupt(priv
, PCH_UART_HAL_TX_INT
);
997 uart_write_wakeup(port
);
1001 if (bytes
> fifo_size
) {
1002 num
= bytes
/ fifo_size
+ 1;
1004 rem
= bytes
% fifo_size
;
1011 dev_dbg(priv
->port
.dev
, "%s num=%d size=%d rem=%d\n",
1012 __func__
, num
, size
, rem
);
1014 priv
->tx_dma_use
= 1;
1016 priv
->sg_tx_p
= kzalloc(sizeof(struct scatterlist
)*num
, GFP_ATOMIC
);
1017 if (!priv
->sg_tx_p
) {
1018 dev_err(priv
->port
.dev
, "%s:kzalloc Failed\n", __func__
);
1022 sg_init_table(priv
->sg_tx_p
, num
); /* Initialize SG table */
1025 for (i
= 0; i
< num
; i
++, sg
++) {
1027 sg_set_page(sg
, virt_to_page(xmit
->buf
),
1028 rem
, fifo_size
* i
);
1030 sg_set_page(sg
, virt_to_page(xmit
->buf
),
1031 size
, fifo_size
* i
);
1035 nent
= dma_map_sg(port
->dev
, sg
, num
, DMA_TO_DEVICE
);
1037 dev_err(priv
->port
.dev
, "%s:dma_map_sg Failed\n", __func__
);
1042 for (i
= 0; i
< nent
; i
++, sg
++) {
1043 sg
->offset
= (xmit
->tail
& (UART_XMIT_SIZE
- 1)) +
1045 sg_dma_address(sg
) = (sg_dma_address(sg
) &
1046 ~(UART_XMIT_SIZE
- 1)) + sg
->offset
;
1047 if (i
== (nent
- 1))
1048 sg_dma_len(sg
) = rem
;
1050 sg_dma_len(sg
) = size
;
1053 desc
= dmaengine_prep_slave_sg(priv
->chan_tx
,
1054 priv
->sg_tx_p
, nent
, DMA_MEM_TO_DEV
,
1055 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
1057 dev_err(priv
->port
.dev
, "%s:device_prep_slave_sg Failed\n",
1061 dma_sync_sg_for_device(port
->dev
, priv
->sg_tx_p
, nent
, DMA_TO_DEVICE
);
1062 priv
->desc_tx
= desc
;
1063 desc
->callback
= pch_dma_tx_complete
;
1064 desc
->callback_param
= priv
;
1066 desc
->tx_submit(desc
);
1068 dma_async_issue_pending(priv
->chan_tx
);
1070 return PCH_UART_HANDLED_TX_INT
;
1073 static void pch_uart_err_ir(struct eg20t_port
*priv
, unsigned int lsr
)
1075 struct uart_port
*port
= &priv
->port
;
1076 struct tty_struct
*tty
= tty_port_tty_get(&port
->state
->port
);
1077 char *error_msg
[5] = {};
1080 if (lsr
& PCH_UART_LSR_ERR
)
1081 error_msg
[i
++] = "Error data in FIFO\n";
1083 if (lsr
& UART_LSR_FE
) {
1084 port
->icount
.frame
++;
1085 error_msg
[i
++] = " Framing Error\n";
1088 if (lsr
& UART_LSR_PE
) {
1089 port
->icount
.parity
++;
1090 error_msg
[i
++] = " Parity Error\n";
1093 if (lsr
& UART_LSR_OE
) {
1094 port
->icount
.overrun
++;
1095 error_msg
[i
++] = " Overrun Error\n";
1099 for (i
= 0; error_msg
[i
] != NULL
; i
++)
1100 dev_err(&priv
->pdev
->dev
, error_msg
[i
]);
1104 static irqreturn_t
pch_uart_interrupt(int irq
, void *dev_id
)
1106 struct eg20t_port
*priv
= dev_id
;
1107 unsigned int handled
;
1111 unsigned long flags
;
1115 spin_lock_irqsave(&priv
->lock
, flags
);
1118 iid
= pch_uart_hal_get_iid(priv
);
1119 if (iid
& PCH_UART_IIR_IP
) /* No Interrupt */
1122 case PCH_UART_IID_RLS
: /* Receiver Line Status */
1123 lsr
= pch_uart_hal_get_line_status(priv
);
1124 if (lsr
& (PCH_UART_LSR_ERR
| UART_LSR_FE
|
1125 UART_LSR_PE
| UART_LSR_OE
)) {
1126 pch_uart_err_ir(priv
, lsr
);
1127 ret
= PCH_UART_HANDLED_RX_ERR_INT
;
1129 ret
= PCH_UART_HANDLED_LS_INT
;
1132 case PCH_UART_IID_RDR
: /* Received Data Ready */
1133 if (priv
->use_dma
) {
1134 pch_uart_hal_disable_interrupt(priv
,
1135 PCH_UART_HAL_RX_INT
|
1136 PCH_UART_HAL_RX_ERR_INT
);
1137 ret
= dma_handle_rx(priv
);
1139 pch_uart_hal_enable_interrupt(priv
,
1140 PCH_UART_HAL_RX_INT
|
1141 PCH_UART_HAL_RX_ERR_INT
);
1143 ret
= handle_rx(priv
);
1146 case PCH_UART_IID_RDR_TO
: /* Received Data Ready
1148 ret
= handle_rx_to(priv
);
1150 case PCH_UART_IID_THRE
: /* Transmitter Holding Register
1153 ret
= dma_handle_tx(priv
);
1155 ret
= handle_tx(priv
);
1157 case PCH_UART_IID_MS
: /* Modem Status */
1158 msr
= pch_uart_hal_get_modem(priv
);
1159 next
= 0; /* MS ir prioirty is the lowest. So, MS ir
1160 means final interrupt */
1161 if ((msr
& UART_MSR_ANY_DELTA
) == 0)
1163 ret
|= PCH_UART_HANDLED_MS_INT
;
1165 default: /* Never junp to this label */
1166 dev_err(priv
->port
.dev
, "%s:iid=%02x (%lu)\n", __func__
,
1172 handled
|= (unsigned int)ret
;
1175 spin_unlock_irqrestore(&priv
->lock
, flags
);
1176 return IRQ_RETVAL(handled
);
1179 /* This function tests whether the transmitter fifo and shifter for the port
1180 described by 'port' is empty. */
1181 static unsigned int pch_uart_tx_empty(struct uart_port
*port
)
1183 struct eg20t_port
*priv
;
1185 priv
= container_of(port
, struct eg20t_port
, port
);
1187 return TIOCSER_TEMT
;
1192 /* Returns the current state of modem control inputs. */
1193 static unsigned int pch_uart_get_mctrl(struct uart_port
*port
)
1195 struct eg20t_port
*priv
;
1197 unsigned int ret
= 0;
1199 priv
= container_of(port
, struct eg20t_port
, port
);
1200 modem
= pch_uart_hal_get_modem(priv
);
1202 if (modem
& UART_MSR_DCD
)
1205 if (modem
& UART_MSR_RI
)
1208 if (modem
& UART_MSR_DSR
)
1211 if (modem
& UART_MSR_CTS
)
1217 static void pch_uart_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
1220 struct eg20t_port
*priv
= container_of(port
, struct eg20t_port
, port
);
1222 if (mctrl
& TIOCM_DTR
)
1223 mcr
|= UART_MCR_DTR
;
1224 if (mctrl
& TIOCM_RTS
)
1225 mcr
|= UART_MCR_RTS
;
1226 if (mctrl
& TIOCM_LOOP
)
1227 mcr
|= UART_MCR_LOOP
;
1229 if (priv
->mcr
& UART_MCR_AFE
)
1230 mcr
|= UART_MCR_AFE
;
1233 iowrite8(mcr
, priv
->membase
+ UART_MCR
);
1236 static void pch_uart_stop_tx(struct uart_port
*port
)
1238 struct eg20t_port
*priv
;
1239 priv
= container_of(port
, struct eg20t_port
, port
);
1241 priv
->tx_dma_use
= 0;
1244 static void pch_uart_start_tx(struct uart_port
*port
)
1246 struct eg20t_port
*priv
;
1248 priv
= container_of(port
, struct eg20t_port
, port
);
1250 if (priv
->use_dma
) {
1251 if (priv
->tx_dma_use
) {
1252 dev_dbg(priv
->port
.dev
, "%s : Tx DMA is NOT empty.\n",
1259 pch_uart_hal_enable_interrupt(priv
, PCH_UART_HAL_TX_INT
);
1262 static void pch_uart_stop_rx(struct uart_port
*port
)
1264 struct eg20t_port
*priv
;
1265 priv
= container_of(port
, struct eg20t_port
, port
);
1267 pch_uart_hal_disable_interrupt(priv
, PCH_UART_HAL_RX_INT
|
1268 PCH_UART_HAL_RX_ERR_INT
);
1271 /* Enable the modem status interrupts. */
1272 static void pch_uart_enable_ms(struct uart_port
*port
)
1274 struct eg20t_port
*priv
;
1275 priv
= container_of(port
, struct eg20t_port
, port
);
1276 pch_uart_hal_enable_interrupt(priv
, PCH_UART_HAL_MS_INT
);
1279 /* Control the transmission of a break signal. */
1280 static void pch_uart_break_ctl(struct uart_port
*port
, int ctl
)
1282 struct eg20t_port
*priv
;
1283 unsigned long flags
;
1285 priv
= container_of(port
, struct eg20t_port
, port
);
1286 spin_lock_irqsave(&priv
->lock
, flags
);
1287 pch_uart_hal_set_break(priv
, ctl
);
1288 spin_unlock_irqrestore(&priv
->lock
, flags
);
1291 /* Grab any interrupt resources and initialise any low level driver state. */
1292 static int pch_uart_startup(struct uart_port
*port
)
1294 struct eg20t_port
*priv
;
1299 priv
= container_of(port
, struct eg20t_port
, port
);
1303 priv
->uartclk
= port
->uartclk
;
1305 port
->uartclk
= priv
->uartclk
;
1307 pch_uart_hal_disable_interrupt(priv
, PCH_UART_HAL_ALL_INT
);
1308 ret
= pch_uart_hal_set_line(priv
, default_baud
,
1309 PCH_UART_HAL_PARITY_NONE
, PCH_UART_HAL_8BIT
,
1314 switch (priv
->fifo_size
) {
1316 fifo_size
= PCH_UART_HAL_FIFO256
;
1319 fifo_size
= PCH_UART_HAL_FIFO64
;
1322 fifo_size
= PCH_UART_HAL_FIFO16
;
1326 fifo_size
= PCH_UART_HAL_FIFO_DIS
;
1330 switch (priv
->trigger
) {
1331 case PCH_UART_HAL_TRIGGER1
:
1334 case PCH_UART_HAL_TRIGGER_L
:
1335 trigger_level
= priv
->fifo_size
/ 4;
1337 case PCH_UART_HAL_TRIGGER_M
:
1338 trigger_level
= priv
->fifo_size
/ 2;
1340 case PCH_UART_HAL_TRIGGER_H
:
1342 trigger_level
= priv
->fifo_size
- (priv
->fifo_size
/ 8);
1346 priv
->trigger_level
= trigger_level
;
1347 ret
= pch_uart_hal_set_fifo(priv
, PCH_UART_HAL_DMA_MODE0
,
1348 fifo_size
, priv
->trigger
);
1352 ret
= request_irq(priv
->port
.irq
, pch_uart_interrupt
, IRQF_SHARED
,
1353 KBUILD_MODNAME
, priv
);
1358 pch_request_dma(port
);
1361 pch_uart_hal_enable_interrupt(priv
, PCH_UART_HAL_RX_INT
|
1362 PCH_UART_HAL_RX_ERR_INT
);
1363 uart_update_timeout(port
, CS8
, default_baud
);
1368 static void pch_uart_shutdown(struct uart_port
*port
)
1370 struct eg20t_port
*priv
;
1373 priv
= container_of(port
, struct eg20t_port
, port
);
1374 pch_uart_hal_disable_interrupt(priv
, PCH_UART_HAL_ALL_INT
);
1375 pch_uart_hal_fifo_reset(priv
, PCH_UART_HAL_CLR_ALL_FIFO
);
1376 ret
= pch_uart_hal_set_fifo(priv
, PCH_UART_HAL_DMA_MODE0
,
1377 PCH_UART_HAL_FIFO_DIS
, PCH_UART_HAL_TRIGGER1
);
1379 dev_err(priv
->port
.dev
,
1380 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret
);
1384 free_irq(priv
->port
.irq
, priv
);
1387 /* Change the port parameters, including word length, parity, stop
1388 *bits. Update read_status_mask and ignore_status_mask to indicate
1389 *the types of events we are interested in receiving. */
1390 static void pch_uart_set_termios(struct uart_port
*port
,
1391 struct ktermios
*termios
, struct ktermios
*old
)
1394 unsigned int baud
, parity
, bits
, stb
;
1395 struct eg20t_port
*priv
;
1396 unsigned long flags
;
1398 priv
= container_of(port
, struct eg20t_port
, port
);
1399 switch (termios
->c_cflag
& CSIZE
) {
1401 bits
= PCH_UART_HAL_5BIT
;
1404 bits
= PCH_UART_HAL_6BIT
;
1407 bits
= PCH_UART_HAL_7BIT
;
1410 bits
= PCH_UART_HAL_8BIT
;
1413 if (termios
->c_cflag
& CSTOPB
)
1414 stb
= PCH_UART_HAL_STB2
;
1416 stb
= PCH_UART_HAL_STB1
;
1418 if (termios
->c_cflag
& PARENB
) {
1419 if (termios
->c_cflag
& PARODD
)
1420 parity
= PCH_UART_HAL_PARITY_ODD
;
1422 parity
= PCH_UART_HAL_PARITY_EVEN
;
1425 parity
= PCH_UART_HAL_PARITY_NONE
;
1427 /* Only UART0 has auto hardware flow function */
1428 if ((termios
->c_cflag
& CRTSCTS
) && (priv
->fifo_size
== 256))
1429 priv
->mcr
|= UART_MCR_AFE
;
1431 priv
->mcr
&= ~UART_MCR_AFE
;
1433 termios
->c_cflag
&= ~CMSPAR
; /* Mark/Space parity is not supported */
1435 baud
= uart_get_baud_rate(port
, termios
, old
, 0, port
->uartclk
/ 16);
1437 spin_lock_irqsave(&priv
->lock
, flags
);
1438 spin_lock(&port
->lock
);
1440 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1441 rtn
= pch_uart_hal_set_line(priv
, baud
, parity
, bits
, stb
);
1445 pch_uart_set_mctrl(&priv
->port
, priv
->port
.mctrl
);
1446 /* Don't rewrite B0 */
1447 if (tty_termios_baud_rate(termios
))
1448 tty_termios_encode_baud_rate(termios
, baud
, baud
);
1451 spin_unlock(&port
->lock
);
1452 spin_unlock_irqrestore(&priv
->lock
, flags
);
1455 static const char *pch_uart_type(struct uart_port
*port
)
1457 return KBUILD_MODNAME
;
1460 static void pch_uart_release_port(struct uart_port
*port
)
1462 struct eg20t_port
*priv
;
1464 priv
= container_of(port
, struct eg20t_port
, port
);
1465 pci_iounmap(priv
->pdev
, priv
->membase
);
1466 pci_release_regions(priv
->pdev
);
1469 static int pch_uart_request_port(struct uart_port
*port
)
1471 struct eg20t_port
*priv
;
1473 void __iomem
*membase
;
1475 priv
= container_of(port
, struct eg20t_port
, port
);
1476 ret
= pci_request_regions(priv
->pdev
, KBUILD_MODNAME
);
1480 membase
= pci_iomap(priv
->pdev
, 1, 0);
1482 pci_release_regions(priv
->pdev
);
1485 priv
->membase
= port
->membase
= membase
;
1490 static void pch_uart_config_port(struct uart_port
*port
, int type
)
1492 struct eg20t_port
*priv
;
1494 priv
= container_of(port
, struct eg20t_port
, port
);
1495 if (type
& UART_CONFIG_TYPE
) {
1496 port
->type
= priv
->port_type
;
1497 pch_uart_request_port(port
);
1501 static int pch_uart_verify_port(struct uart_port
*port
,
1502 struct serial_struct
*serinfo
)
1504 struct eg20t_port
*priv
;
1506 priv
= container_of(port
, struct eg20t_port
, port
);
1507 if (serinfo
->flags
& UPF_LOW_LATENCY
) {
1508 dev_info(priv
->port
.dev
,
1509 "PCH UART : Use PIO Mode (without DMA)\n");
1511 serinfo
->flags
&= ~UPF_LOW_LATENCY
;
1513 #ifndef CONFIG_PCH_DMA
1514 dev_err(priv
->port
.dev
, "%s : PCH DMA is not Loaded.\n",
1518 dev_info(priv
->port
.dev
, "PCH UART : Use DMA Mode\n");
1520 pch_request_dma(port
);
1527 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1529 * Wait for transmitter & holding register to empty
1531 static void wait_for_xmitr(struct eg20t_port
*up
, int bits
)
1533 unsigned int status
, tmout
= 10000;
1535 /* Wait up to 10ms for the character(s) to be sent. */
1537 status
= ioread8(up
->membase
+ UART_LSR
);
1539 if ((status
& bits
) == bits
)
1546 /* Wait up to 1s for flow control if necessary */
1547 if (up
->port
.flags
& UPF_CONS_FLOW
) {
1549 for (tmout
= 1000000; tmout
; tmout
--) {
1550 unsigned int msr
= ioread8(up
->membase
+ UART_MSR
);
1551 if (msr
& UART_MSR_CTS
)
1554 touch_nmi_watchdog();
1558 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1560 #ifdef CONFIG_CONSOLE_POLL
1562 * Console polling routines for communicate via uart while
1563 * in an interrupt or debug context.
1565 static int pch_uart_get_poll_char(struct uart_port
*port
)
1567 struct eg20t_port
*priv
=
1568 container_of(port
, struct eg20t_port
, port
);
1569 u8 lsr
= ioread8(priv
->membase
+ UART_LSR
);
1571 if (!(lsr
& UART_LSR_DR
))
1572 return NO_POLL_CHAR
;
1574 return ioread8(priv
->membase
+ PCH_UART_RBR
);
1578 static void pch_uart_put_poll_char(struct uart_port
*port
,
1582 struct eg20t_port
*priv
=
1583 container_of(port
, struct eg20t_port
, port
);
1586 * First save the IER then disable the interrupts
1588 ier
= ioread8(priv
->membase
+ UART_IER
);
1589 pch_uart_hal_disable_interrupt(priv
, PCH_UART_HAL_ALL_INT
);
1591 wait_for_xmitr(priv
, UART_LSR_THRE
);
1593 * Send the character out.
1594 * If a LF, also do CR...
1596 iowrite8(c
, priv
->membase
+ PCH_UART_THR
);
1598 wait_for_xmitr(priv
, UART_LSR_THRE
);
1599 iowrite8(13, priv
->membase
+ PCH_UART_THR
);
1603 * Finally, wait for transmitter to become empty
1604 * and restore the IER
1606 wait_for_xmitr(priv
, BOTH_EMPTY
);
1607 iowrite8(ier
, priv
->membase
+ UART_IER
);
1609 #endif /* CONFIG_CONSOLE_POLL */
1611 static struct uart_ops pch_uart_ops
= {
1612 .tx_empty
= pch_uart_tx_empty
,
1613 .set_mctrl
= pch_uart_set_mctrl
,
1614 .get_mctrl
= pch_uart_get_mctrl
,
1615 .stop_tx
= pch_uart_stop_tx
,
1616 .start_tx
= pch_uart_start_tx
,
1617 .stop_rx
= pch_uart_stop_rx
,
1618 .enable_ms
= pch_uart_enable_ms
,
1619 .break_ctl
= pch_uart_break_ctl
,
1620 .startup
= pch_uart_startup
,
1621 .shutdown
= pch_uart_shutdown
,
1622 .set_termios
= pch_uart_set_termios
,
1623 /* .pm = pch_uart_pm, Not supported yet */
1624 /* .set_wake = pch_uart_set_wake, Not supported yet */
1625 .type
= pch_uart_type
,
1626 .release_port
= pch_uart_release_port
,
1627 .request_port
= pch_uart_request_port
,
1628 .config_port
= pch_uart_config_port
,
1629 .verify_port
= pch_uart_verify_port
,
1630 #ifdef CONFIG_CONSOLE_POLL
1631 .poll_get_char
= pch_uart_get_poll_char
,
1632 .poll_put_char
= pch_uart_put_poll_char
,
1636 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1638 static void pch_console_putchar(struct uart_port
*port
, int ch
)
1640 struct eg20t_port
*priv
=
1641 container_of(port
, struct eg20t_port
, port
);
1643 wait_for_xmitr(priv
, UART_LSR_THRE
);
1644 iowrite8(ch
, priv
->membase
+ PCH_UART_THR
);
1648 * Print a string to the serial port trying not to disturb
1649 * any possible real use of the port...
1651 * The console_lock must be held when we get here.
1654 pch_console_write(struct console
*co
, const char *s
, unsigned int count
)
1656 struct eg20t_port
*priv
;
1657 unsigned long flags
;
1658 int priv_locked
= 1;
1659 int port_locked
= 1;
1662 priv
= pch_uart_ports
[co
->index
];
1664 touch_nmi_watchdog();
1666 local_irq_save(flags
);
1667 if (priv
->port
.sysrq
) {
1668 /* call to uart_handle_sysrq_char already took the priv lock */
1670 /* serial8250_handle_port() already took the port lock */
1672 } else if (oops_in_progress
) {
1673 priv_locked
= spin_trylock(&priv
->lock
);
1674 port_locked
= spin_trylock(&priv
->port
.lock
);
1676 spin_lock(&priv
->lock
);
1677 spin_lock(&priv
->port
.lock
);
1681 * First save the IER then disable the interrupts
1683 ier
= ioread8(priv
->membase
+ UART_IER
);
1685 pch_uart_hal_disable_interrupt(priv
, PCH_UART_HAL_ALL_INT
);
1687 uart_console_write(&priv
->port
, s
, count
, pch_console_putchar
);
1690 * Finally, wait for transmitter to become empty
1691 * and restore the IER
1693 wait_for_xmitr(priv
, BOTH_EMPTY
);
1694 iowrite8(ier
, priv
->membase
+ UART_IER
);
1697 spin_unlock(&priv
->port
.lock
);
1699 spin_unlock(&priv
->lock
);
1700 local_irq_restore(flags
);
1703 static int __init
pch_console_setup(struct console
*co
, char *options
)
1705 struct uart_port
*port
;
1706 int baud
= default_baud
;
1712 * Check whether an invalid uart number has been specified, and
1713 * if so, search for the first available port that does have
1716 if (co
->index
>= PCH_UART_NR
)
1718 port
= &pch_uart_ports
[co
->index
]->port
;
1720 if (!port
|| (!port
->iobase
&& !port
->membase
))
1723 port
->uartclk
= pch_uart_get_uartclk();
1726 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1728 return uart_set_options(port
, co
, baud
, parity
, bits
, flow
);
1731 static struct uart_driver pch_uart_driver
;
1733 static struct console pch_console
= {
1734 .name
= PCH_UART_DRIVER_DEVICE
,
1735 .write
= pch_console_write
,
1736 .device
= uart_console_device
,
1737 .setup
= pch_console_setup
,
1738 .flags
= CON_PRINTBUFFER
| CON_ANYTIME
,
1740 .data
= &pch_uart_driver
,
1743 #define PCH_CONSOLE (&pch_console)
1745 #define PCH_CONSOLE NULL
1746 #endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1748 static struct uart_driver pch_uart_driver
= {
1749 .owner
= THIS_MODULE
,
1750 .driver_name
= KBUILD_MODNAME
,
1751 .dev_name
= PCH_UART_DRIVER_DEVICE
,
1755 .cons
= PCH_CONSOLE
,
1758 static struct eg20t_port
*pch_uart_init_port(struct pci_dev
*pdev
,
1759 const struct pci_device_id
*id
)
1761 struct eg20t_port
*priv
;
1763 unsigned int iobase
;
1764 unsigned int mapbase
;
1765 unsigned char *rxbuf
;
1768 struct pch_uart_driver_data
*board
;
1769 char name
[32]; /* for debugfs file name */
1771 board
= &drv_dat
[id
->driver_data
];
1772 port_type
= board
->port_type
;
1774 priv
= kzalloc(sizeof(struct eg20t_port
), GFP_KERNEL
);
1776 goto init_port_alloc_err
;
1778 rxbuf
= (unsigned char *)__get_free_page(GFP_KERNEL
);
1780 goto init_port_free_txbuf
;
1782 switch (port_type
) {
1784 fifosize
= 256; /* EG20T/ML7213: UART0 */
1787 fifosize
= 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1790 dev_err(&pdev
->dev
, "Invalid Port Type(=%d)\n", port_type
);
1791 goto init_port_hal_free
;
1794 pci_enable_msi(pdev
);
1795 pci_set_master(pdev
);
1797 spin_lock_init(&priv
->lock
);
1799 iobase
= pci_resource_start(pdev
, 0);
1800 mapbase
= pci_resource_start(pdev
, 1);
1801 priv
->mapbase
= mapbase
;
1802 priv
->iobase
= iobase
;
1805 priv
->rxbuf
.buf
= rxbuf
;
1806 priv
->rxbuf
.size
= PAGE_SIZE
;
1808 priv
->fifo_size
= fifosize
;
1809 priv
->uartclk
= pch_uart_get_uartclk();
1810 priv
->port_type
= PORT_MAX_8250
+ port_type
+ 1;
1811 priv
->port
.dev
= &pdev
->dev
;
1812 priv
->port
.iobase
= iobase
;
1813 priv
->port
.membase
= NULL
;
1814 priv
->port
.mapbase
= mapbase
;
1815 priv
->port
.irq
= pdev
->irq
;
1816 priv
->port
.iotype
= UPIO_PORT
;
1817 priv
->port
.ops
= &pch_uart_ops
;
1818 priv
->port
.flags
= UPF_BOOT_AUTOCONF
;
1819 priv
->port
.fifosize
= fifosize
;
1820 priv
->port
.line
= board
->line_no
;
1821 priv
->trigger
= PCH_UART_HAL_TRIGGER_M
;
1823 spin_lock_init(&priv
->port
.lock
);
1825 pci_set_drvdata(pdev
, priv
);
1826 priv
->trigger_level
= 1;
1829 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1830 pch_uart_ports
[board
->line_no
] = priv
;
1832 ret
= uart_add_one_port(&pch_uart_driver
, &priv
->port
);
1834 goto init_port_hal_free
;
1836 #ifdef CONFIG_DEBUG_FS
1837 snprintf(name
, sizeof(name
), "uart%d_regs", board
->line_no
);
1838 priv
->debugfs
= debugfs_create_file(name
, S_IFREG
| S_IRUGO
,
1839 NULL
, priv
, &port_regs_ops
);
1845 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1846 pch_uart_ports
[board
->line_no
] = NULL
;
1848 free_page((unsigned long)rxbuf
);
1849 init_port_free_txbuf
:
1851 init_port_alloc_err
:
1856 static void pch_uart_exit_port(struct eg20t_port
*priv
)
1859 #ifdef CONFIG_DEBUG_FS
1861 debugfs_remove(priv
->debugfs
);
1863 uart_remove_one_port(&pch_uart_driver
, &priv
->port
);
1864 pci_set_drvdata(priv
->pdev
, NULL
);
1865 free_page((unsigned long)priv
->rxbuf
.buf
);
1868 static void pch_uart_pci_remove(struct pci_dev
*pdev
)
1870 struct eg20t_port
*priv
= pci_get_drvdata(pdev
);
1872 pci_disable_msi(pdev
);
1874 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1875 pch_uart_ports
[priv
->port
.line
] = NULL
;
1877 pch_uart_exit_port(priv
);
1878 pci_disable_device(pdev
);
1883 static int pch_uart_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1885 struct eg20t_port
*priv
= pci_get_drvdata(pdev
);
1887 uart_suspend_port(&pch_uart_driver
, &priv
->port
);
1889 pci_save_state(pdev
);
1890 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
1894 static int pch_uart_pci_resume(struct pci_dev
*pdev
)
1896 struct eg20t_port
*priv
= pci_get_drvdata(pdev
);
1899 pci_set_power_state(pdev
, PCI_D0
);
1900 pci_restore_state(pdev
);
1902 ret
= pci_enable_device(pdev
);
1905 "%s-pci_enable_device failed(ret=%d) ", __func__
, ret
);
1909 uart_resume_port(&pch_uart_driver
, &priv
->port
);
1914 #define pch_uart_pci_suspend NULL
1915 #define pch_uart_pci_resume NULL
1918 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id
) = {
1919 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x8811),
1920 .driver_data
= pch_et20t_uart0
},
1921 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x8812),
1922 .driver_data
= pch_et20t_uart1
},
1923 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x8813),
1924 .driver_data
= pch_et20t_uart2
},
1925 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x8814),
1926 .driver_data
= pch_et20t_uart3
},
1927 {PCI_DEVICE(PCI_VENDOR_ID_ROHM
, 0x8027),
1928 .driver_data
= pch_ml7213_uart0
},
1929 {PCI_DEVICE(PCI_VENDOR_ID_ROHM
, 0x8028),
1930 .driver_data
= pch_ml7213_uart1
},
1931 {PCI_DEVICE(PCI_VENDOR_ID_ROHM
, 0x8029),
1932 .driver_data
= pch_ml7213_uart2
},
1933 {PCI_DEVICE(PCI_VENDOR_ID_ROHM
, 0x800C),
1934 .driver_data
= pch_ml7223_uart0
},
1935 {PCI_DEVICE(PCI_VENDOR_ID_ROHM
, 0x800D),
1936 .driver_data
= pch_ml7223_uart1
},
1937 {PCI_DEVICE(PCI_VENDOR_ID_ROHM
, 0x8811),
1938 .driver_data
= pch_ml7831_uart0
},
1939 {PCI_DEVICE(PCI_VENDOR_ID_ROHM
, 0x8812),
1940 .driver_data
= pch_ml7831_uart1
},
1944 static int pch_uart_pci_probe(struct pci_dev
*pdev
,
1945 const struct pci_device_id
*id
)
1948 struct eg20t_port
*priv
;
1950 ret
= pci_enable_device(pdev
);
1954 priv
= pch_uart_init_port(pdev
, id
);
1957 goto probe_disable_device
;
1959 pci_set_drvdata(pdev
, priv
);
1963 probe_disable_device
:
1964 pci_disable_msi(pdev
);
1965 pci_disable_device(pdev
);
1970 static struct pci_driver pch_uart_pci_driver
= {
1972 .id_table
= pch_uart_pci_id
,
1973 .probe
= pch_uart_pci_probe
,
1974 .remove
= pch_uart_pci_remove
,
1975 .suspend
= pch_uart_pci_suspend
,
1976 .resume
= pch_uart_pci_resume
,
1979 static int __init
pch_uart_module_init(void)
1983 /* register as UART driver */
1984 ret
= uart_register_driver(&pch_uart_driver
);
1988 /* register as PCI driver */
1989 ret
= pci_register_driver(&pch_uart_pci_driver
);
1991 uart_unregister_driver(&pch_uart_driver
);
1995 module_init(pch_uart_module_init
);
1997 static void __exit
pch_uart_module_exit(void)
1999 pci_unregister_driver(&pch_uart_pci_driver
);
2000 uart_unregister_driver(&pch_uart_driver
);
2002 module_exit(pch_uart_module_exit
);
2004 MODULE_LICENSE("GPL v2");
2005 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
2006 module_param(default_baud
, uint
, S_IRUGO
);
2007 MODULE_PARM_DESC(default_baud
,
2008 "Default BAUD for initial driver state and console (default 9600)");
2009 module_param(user_uartclk
, uint
, S_IRUGO
);
2010 MODULE_PARM_DESC(user_uartclk
,
2011 "Override UART default or board specific UART clock");