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Merge tag 'random_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso...
[mirror_ubuntu-eoan-kernel.git] / drivers / tty / serial / pch_uart.c
1 /*
2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
3 *
4 *This program is free software; you can redistribute it and/or modify
5 *it under the terms of the GNU General Public License as published by
6 *the Free Software Foundation; version 2 of the License.
7 *
8 *This program is distributed in the hope that it will be useful,
9 *but WITHOUT ANY WARRANTY; without even the implied warranty of
10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 *GNU General Public License for more details.
12 *
13 *You should have received a copy of the GNU General Public License
14 *along with this program; if not, write to the Free Software
15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17 #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18 #define SUPPORT_SYSRQ
19 #endif
20 #include <linux/kernel.h>
21 #include <linux/serial_reg.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/console.h>
26 #include <linux/serial_core.h>
27 #include <linux/tty.h>
28 #include <linux/tty_flip.h>
29 #include <linux/interrupt.h>
30 #include <linux/io.h>
31 #include <linux/dmi.h>
32 #include <linux/nmi.h>
33 #include <linux/delay.h>
34
35 #include <linux/debugfs.h>
36 #include <linux/dmaengine.h>
37 #include <linux/pch_dma.h>
38
39 enum {
40 PCH_UART_HANDLED_RX_INT_SHIFT,
41 PCH_UART_HANDLED_TX_INT_SHIFT,
42 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
43 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
44 PCH_UART_HANDLED_MS_INT_SHIFT,
45 PCH_UART_HANDLED_LS_INT_SHIFT,
46 };
47
48 enum {
49 PCH_UART_8LINE,
50 PCH_UART_2LINE,
51 };
52
53 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
54
55 /* Set the max number of UART port
56 * Intel EG20T PCH: 4 port
57 * LAPIS Semiconductor ML7213 IOH: 3 port
58 * LAPIS Semiconductor ML7223 IOH: 2 port
59 */
60 #define PCH_UART_NR 4
61
62 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
63 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
64 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
65 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
66 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
67 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
68 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
69
70 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
71
72 #define PCH_UART_RBR 0x00
73 #define PCH_UART_THR 0x00
74
75 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
76 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
77 #define PCH_UART_IER_ERBFI 0x00000001
78 #define PCH_UART_IER_ETBEI 0x00000002
79 #define PCH_UART_IER_ELSI 0x00000004
80 #define PCH_UART_IER_EDSSI 0x00000008
81
82 #define PCH_UART_IIR_IP 0x00000001
83 #define PCH_UART_IIR_IID 0x00000006
84 #define PCH_UART_IIR_MSI 0x00000000
85 #define PCH_UART_IIR_TRI 0x00000002
86 #define PCH_UART_IIR_RRI 0x00000004
87 #define PCH_UART_IIR_REI 0x00000006
88 #define PCH_UART_IIR_TOI 0x00000008
89 #define PCH_UART_IIR_FIFO256 0x00000020
90 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
91 #define PCH_UART_IIR_FE 0x000000C0
92
93 #define PCH_UART_FCR_FIFOE 0x00000001
94 #define PCH_UART_FCR_RFR 0x00000002
95 #define PCH_UART_FCR_TFR 0x00000004
96 #define PCH_UART_FCR_DMS 0x00000008
97 #define PCH_UART_FCR_FIFO256 0x00000020
98 #define PCH_UART_FCR_RFTL 0x000000C0
99
100 #define PCH_UART_FCR_RFTL1 0x00000000
101 #define PCH_UART_FCR_RFTL64 0x00000040
102 #define PCH_UART_FCR_RFTL128 0x00000080
103 #define PCH_UART_FCR_RFTL224 0x000000C0
104 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
105 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
106 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
107 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
108 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
109 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
110 #define PCH_UART_FCR_RFTL_SHIFT 6
111
112 #define PCH_UART_LCR_WLS 0x00000003
113 #define PCH_UART_LCR_STB 0x00000004
114 #define PCH_UART_LCR_PEN 0x00000008
115 #define PCH_UART_LCR_EPS 0x00000010
116 #define PCH_UART_LCR_SP 0x00000020
117 #define PCH_UART_LCR_SB 0x00000040
118 #define PCH_UART_LCR_DLAB 0x00000080
119 #define PCH_UART_LCR_NP 0x00000000
120 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN
121 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
122 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
123 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
124 PCH_UART_LCR_SP)
125
126 #define PCH_UART_LCR_5BIT 0x00000000
127 #define PCH_UART_LCR_6BIT 0x00000001
128 #define PCH_UART_LCR_7BIT 0x00000002
129 #define PCH_UART_LCR_8BIT 0x00000003
130
131 #define PCH_UART_MCR_DTR 0x00000001
132 #define PCH_UART_MCR_RTS 0x00000002
133 #define PCH_UART_MCR_OUT 0x0000000C
134 #define PCH_UART_MCR_LOOP 0x00000010
135 #define PCH_UART_MCR_AFE 0x00000020
136
137 #define PCH_UART_LSR_DR 0x00000001
138 #define PCH_UART_LSR_ERR (1<<7)
139
140 #define PCH_UART_MSR_DCTS 0x00000001
141 #define PCH_UART_MSR_DDSR 0x00000002
142 #define PCH_UART_MSR_TERI 0x00000004
143 #define PCH_UART_MSR_DDCD 0x00000008
144 #define PCH_UART_MSR_CTS 0x00000010
145 #define PCH_UART_MSR_DSR 0x00000020
146 #define PCH_UART_MSR_RI 0x00000040
147 #define PCH_UART_MSR_DCD 0x00000080
148 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
149 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
150
151 #define PCH_UART_DLL 0x00
152 #define PCH_UART_DLM 0x01
153
154 #define PCH_UART_BRCSR 0x0E
155
156 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
157 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
158 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
159 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
160 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
161
162 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
163 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
164 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
165 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
166 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
167 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
168 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
169 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
170 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
171 #define PCH_UART_HAL_STB1 0
172 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
173
174 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
175 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
176 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
177 PCH_UART_HAL_CLR_RX_FIFO)
178
179 #define PCH_UART_HAL_DMA_MODE0 0
180 #define PCH_UART_HAL_FIFO_DIS 0
181 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
182 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
183 PCH_UART_FCR_FIFO256)
184 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
185 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
186 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
187 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
188 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
189 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
190 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
191 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
192 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
193 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
194 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
195 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
196 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
197 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
198
199 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
200 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
201 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
202 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
203 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
204
205 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
206 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
207 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
208 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
209 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
210
211 #define PCI_VENDOR_ID_ROHM 0x10DB
212
213 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
214
215 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */
216 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */
217 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */
218 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */
219 #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */
220 #define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */
221
222 struct pch_uart_buffer {
223 unsigned char *buf;
224 int size;
225 };
226
227 struct eg20t_port {
228 struct uart_port port;
229 int port_type;
230 void __iomem *membase;
231 resource_size_t mapbase;
232 unsigned int iobase;
233 struct pci_dev *pdev;
234 int fifo_size;
235 unsigned int uartclk;
236 int start_tx;
237 int start_rx;
238 int tx_empty;
239 int trigger;
240 int trigger_level;
241 struct pch_uart_buffer rxbuf;
242 unsigned int dmsr;
243 unsigned int fcr;
244 unsigned int mcr;
245 unsigned int use_dma;
246 struct dma_async_tx_descriptor *desc_tx;
247 struct dma_async_tx_descriptor *desc_rx;
248 struct pch_dma_slave param_tx;
249 struct pch_dma_slave param_rx;
250 struct dma_chan *chan_tx;
251 struct dma_chan *chan_rx;
252 struct scatterlist *sg_tx_p;
253 int nent;
254 struct scatterlist sg_rx;
255 int tx_dma_use;
256 void *rx_buf_virt;
257 dma_addr_t rx_buf_dma;
258
259 struct dentry *debugfs;
260
261 /* protect the eg20t_port private structure and io access to membase */
262 spinlock_t lock;
263 };
264
265 /**
266 * struct pch_uart_driver_data - private data structure for UART-DMA
267 * @port_type: The number of DMA channel
268 * @line_no: UART port line number (0, 1, 2...)
269 */
270 struct pch_uart_driver_data {
271 int port_type;
272 int line_no;
273 };
274
275 enum pch_uart_num_t {
276 pch_et20t_uart0 = 0,
277 pch_et20t_uart1,
278 pch_et20t_uart2,
279 pch_et20t_uart3,
280 pch_ml7213_uart0,
281 pch_ml7213_uart1,
282 pch_ml7213_uart2,
283 pch_ml7223_uart0,
284 pch_ml7223_uart1,
285 pch_ml7831_uart0,
286 pch_ml7831_uart1,
287 };
288
289 static struct pch_uart_driver_data drv_dat[] = {
290 [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
291 [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
292 [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
293 [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
294 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
295 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
296 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
297 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
298 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
299 [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
300 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
301 };
302
303 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
304 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
305 #endif
306 static unsigned int default_baud = 9600;
307 static unsigned int user_uartclk = 0;
308 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
309 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
310 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
311 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
312
313 #ifdef CONFIG_DEBUG_FS
314
315 #define PCH_REGS_BUFSIZE 1024
316
317
318 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
319 size_t count, loff_t *ppos)
320 {
321 struct eg20t_port *priv = file->private_data;
322 char *buf;
323 u32 len = 0;
324 ssize_t ret;
325 unsigned char lcr;
326
327 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
328 if (!buf)
329 return 0;
330
331 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
332 "PCH EG20T port[%d] regs:\n", priv->port.line);
333
334 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
335 "=================================\n");
336 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
337 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
338 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
339 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
340 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
341 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
342 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
343 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
344 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
345 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
346 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
347 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
348 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
349 "BRCSR: \t0x%02x\n",
350 ioread8(priv->membase + PCH_UART_BRCSR));
351
352 lcr = ioread8(priv->membase + UART_LCR);
353 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
354 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
355 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
356 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
357 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
358 iowrite8(lcr, priv->membase + UART_LCR);
359
360 if (len > PCH_REGS_BUFSIZE)
361 len = PCH_REGS_BUFSIZE;
362
363 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
364 kfree(buf);
365 return ret;
366 }
367
368 static const struct file_operations port_regs_ops = {
369 .owner = THIS_MODULE,
370 .open = simple_open,
371 .read = port_show_regs,
372 .llseek = default_llseek,
373 };
374 #endif /* CONFIG_DEBUG_FS */
375
376 static struct dmi_system_id pch_uart_dmi_table[] = {
377 {
378 .ident = "CM-iTC",
379 {
380 DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
381 },
382 (void *)CMITC_UARTCLK,
383 },
384 {
385 .ident = "FRI2",
386 {
387 DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
388 },
389 (void *)FRI2_64_UARTCLK,
390 },
391 {
392 .ident = "Fish River Island II",
393 {
394 DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
395 },
396 (void *)FRI2_48_UARTCLK,
397 },
398 {
399 .ident = "COMe-mTT",
400 {
401 DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
402 },
403 (void *)NTC1_UARTCLK,
404 },
405 {
406 .ident = "nanoETXexpress-TT",
407 {
408 DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
409 },
410 (void *)NTC1_UARTCLK,
411 },
412 {
413 .ident = "MinnowBoard",
414 {
415 DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
416 },
417 (void *)MINNOW_UARTCLK,
418 },
419 };
420
421 /* Return UART clock, checking for board specific clocks. */
422 static unsigned int pch_uart_get_uartclk(void)
423 {
424 const struct dmi_system_id *d;
425
426 if (user_uartclk)
427 return user_uartclk;
428
429 d = dmi_first_match(pch_uart_dmi_table);
430 if (d)
431 return (unsigned long)d->driver_data;
432
433 return DEFAULT_UARTCLK;
434 }
435
436 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
437 unsigned int flag)
438 {
439 u8 ier = ioread8(priv->membase + UART_IER);
440 ier |= flag & PCH_UART_IER_MASK;
441 iowrite8(ier, priv->membase + UART_IER);
442 }
443
444 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
445 unsigned int flag)
446 {
447 u8 ier = ioread8(priv->membase + UART_IER);
448 ier &= ~(flag & PCH_UART_IER_MASK);
449 iowrite8(ier, priv->membase + UART_IER);
450 }
451
452 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
453 unsigned int parity, unsigned int bits,
454 unsigned int stb)
455 {
456 unsigned int dll, dlm, lcr;
457 int div;
458
459 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
460 if (div < 0 || USHRT_MAX <= div) {
461 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
462 return -EINVAL;
463 }
464
465 dll = (unsigned int)div & 0x00FFU;
466 dlm = ((unsigned int)div >> 8) & 0x00FFU;
467
468 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
469 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
470 return -EINVAL;
471 }
472
473 if (bits & ~PCH_UART_LCR_WLS) {
474 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
475 return -EINVAL;
476 }
477
478 if (stb & ~PCH_UART_LCR_STB) {
479 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
480 return -EINVAL;
481 }
482
483 lcr = parity;
484 lcr |= bits;
485 lcr |= stb;
486
487 dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
488 __func__, baud, div, lcr, jiffies);
489 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
490 iowrite8(dll, priv->membase + PCH_UART_DLL);
491 iowrite8(dlm, priv->membase + PCH_UART_DLM);
492 iowrite8(lcr, priv->membase + UART_LCR);
493
494 return 0;
495 }
496
497 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
498 unsigned int flag)
499 {
500 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
501 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
502 __func__, flag);
503 return -EINVAL;
504 }
505
506 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
507 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
508 priv->membase + UART_FCR);
509 iowrite8(priv->fcr, priv->membase + UART_FCR);
510
511 return 0;
512 }
513
514 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
515 unsigned int dmamode,
516 unsigned int fifo_size, unsigned int trigger)
517 {
518 u8 fcr;
519
520 if (dmamode & ~PCH_UART_FCR_DMS) {
521 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
522 __func__, dmamode);
523 return -EINVAL;
524 }
525
526 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
527 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
528 __func__, fifo_size);
529 return -EINVAL;
530 }
531
532 if (trigger & ~PCH_UART_FCR_RFTL) {
533 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
534 __func__, trigger);
535 return -EINVAL;
536 }
537
538 switch (priv->fifo_size) {
539 case 256:
540 priv->trigger_level =
541 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
542 break;
543 case 64:
544 priv->trigger_level =
545 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
546 break;
547 case 16:
548 priv->trigger_level =
549 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
550 break;
551 default:
552 priv->trigger_level =
553 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
554 break;
555 }
556 fcr =
557 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
558 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
559 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
560 priv->membase + UART_FCR);
561 iowrite8(fcr, priv->membase + UART_FCR);
562 priv->fcr = fcr;
563
564 return 0;
565 }
566
567 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
568 {
569 unsigned int msr = ioread8(priv->membase + UART_MSR);
570 priv->dmsr = msr & PCH_UART_MSR_DELTA;
571 return (u8)msr;
572 }
573
574 static void pch_uart_hal_write(struct eg20t_port *priv,
575 const unsigned char *buf, int tx_size)
576 {
577 int i;
578 unsigned int thr;
579
580 for (i = 0; i < tx_size;) {
581 thr = buf[i++];
582 iowrite8(thr, priv->membase + PCH_UART_THR);
583 }
584 }
585
586 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
587 int rx_size)
588 {
589 int i;
590 u8 rbr, lsr;
591 struct uart_port *port = &priv->port;
592
593 lsr = ioread8(priv->membase + UART_LSR);
594 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
595 i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
596 lsr = ioread8(priv->membase + UART_LSR)) {
597 rbr = ioread8(priv->membase + PCH_UART_RBR);
598
599 if (lsr & UART_LSR_BI) {
600 port->icount.brk++;
601 if (uart_handle_break(port))
602 continue;
603 }
604 #ifdef SUPPORT_SYSRQ
605 if (port->sysrq) {
606 if (uart_handle_sysrq_char(port, rbr))
607 continue;
608 }
609 #endif
610
611 buf[i++] = rbr;
612 }
613 return i;
614 }
615
616 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
617 {
618 return ioread8(priv->membase + UART_IIR) &\
619 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
620 }
621
622 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
623 {
624 return ioread8(priv->membase + UART_LSR);
625 }
626
627 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
628 {
629 unsigned int lcr;
630
631 lcr = ioread8(priv->membase + UART_LCR);
632 if (on)
633 lcr |= PCH_UART_LCR_SB;
634 else
635 lcr &= ~PCH_UART_LCR_SB;
636
637 iowrite8(lcr, priv->membase + UART_LCR);
638 }
639
640 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
641 int size)
642 {
643 struct uart_port *port = &priv->port;
644 struct tty_port *tport = &port->state->port;
645
646 tty_insert_flip_string(tport, buf, size);
647 tty_flip_buffer_push(tport);
648
649 return 0;
650 }
651
652 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
653 {
654 int ret = 0;
655 struct uart_port *port = &priv->port;
656
657 if (port->x_char) {
658 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
659 __func__, port->x_char, jiffies);
660 buf[0] = port->x_char;
661 port->x_char = 0;
662 ret = 1;
663 }
664
665 return ret;
666 }
667
668 static int dma_push_rx(struct eg20t_port *priv, int size)
669 {
670 int room;
671 struct uart_port *port = &priv->port;
672 struct tty_port *tport = &port->state->port;
673
674 room = tty_buffer_request_room(tport, size);
675
676 if (room < size)
677 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
678 size - room);
679 if (!room)
680 return 0;
681
682 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
683
684 port->icount.rx += room;
685
686 return room;
687 }
688
689 static void pch_free_dma(struct uart_port *port)
690 {
691 struct eg20t_port *priv;
692 priv = container_of(port, struct eg20t_port, port);
693
694 if (priv->chan_tx) {
695 dma_release_channel(priv->chan_tx);
696 priv->chan_tx = NULL;
697 }
698 if (priv->chan_rx) {
699 dma_release_channel(priv->chan_rx);
700 priv->chan_rx = NULL;
701 }
702
703 if (priv->rx_buf_dma) {
704 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
705 priv->rx_buf_dma);
706 priv->rx_buf_virt = NULL;
707 priv->rx_buf_dma = 0;
708 }
709
710 return;
711 }
712
713 static bool filter(struct dma_chan *chan, void *slave)
714 {
715 struct pch_dma_slave *param = slave;
716
717 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
718 chan->device->dev)) {
719 chan->private = param;
720 return true;
721 } else {
722 return false;
723 }
724 }
725
726 static void pch_request_dma(struct uart_port *port)
727 {
728 dma_cap_mask_t mask;
729 struct dma_chan *chan;
730 struct pci_dev *dma_dev;
731 struct pch_dma_slave *param;
732 struct eg20t_port *priv =
733 container_of(port, struct eg20t_port, port);
734 dma_cap_zero(mask);
735 dma_cap_set(DMA_SLAVE, mask);
736
737 dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
738 PCI_DEVFN(0xa, 0)); /* Get DMA's dev
739 information */
740 /* Set Tx DMA */
741 param = &priv->param_tx;
742 param->dma_dev = &dma_dev->dev;
743 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
744
745 param->tx_reg = port->mapbase + UART_TX;
746 chan = dma_request_channel(mask, filter, param);
747 if (!chan) {
748 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
749 __func__);
750 return;
751 }
752 priv->chan_tx = chan;
753
754 /* Set Rx DMA */
755 param = &priv->param_rx;
756 param->dma_dev = &dma_dev->dev;
757 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
758
759 param->rx_reg = port->mapbase + UART_RX;
760 chan = dma_request_channel(mask, filter, param);
761 if (!chan) {
762 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
763 __func__);
764 dma_release_channel(priv->chan_tx);
765 priv->chan_tx = NULL;
766 return;
767 }
768
769 /* Get Consistent memory for DMA */
770 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
771 &priv->rx_buf_dma, GFP_KERNEL);
772 priv->chan_rx = chan;
773 }
774
775 static void pch_dma_rx_complete(void *arg)
776 {
777 struct eg20t_port *priv = arg;
778 struct uart_port *port = &priv->port;
779 int count;
780
781 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
782 count = dma_push_rx(priv, priv->trigger_level);
783 if (count)
784 tty_flip_buffer_push(&port->state->port);
785 async_tx_ack(priv->desc_rx);
786 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
787 PCH_UART_HAL_RX_ERR_INT);
788 }
789
790 static void pch_dma_tx_complete(void *arg)
791 {
792 struct eg20t_port *priv = arg;
793 struct uart_port *port = &priv->port;
794 struct circ_buf *xmit = &port->state->xmit;
795 struct scatterlist *sg = priv->sg_tx_p;
796 int i;
797
798 for (i = 0; i < priv->nent; i++, sg++) {
799 xmit->tail += sg_dma_len(sg);
800 port->icount.tx += sg_dma_len(sg);
801 }
802 xmit->tail &= UART_XMIT_SIZE - 1;
803 async_tx_ack(priv->desc_tx);
804 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
805 priv->tx_dma_use = 0;
806 priv->nent = 0;
807 kfree(priv->sg_tx_p);
808 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
809 }
810
811 static int pop_tx(struct eg20t_port *priv, int size)
812 {
813 int count = 0;
814 struct uart_port *port = &priv->port;
815 struct circ_buf *xmit = &port->state->xmit;
816
817 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
818 goto pop_tx_end;
819
820 do {
821 int cnt_to_end =
822 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
823 int sz = min(size - count, cnt_to_end);
824 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
825 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
826 count += sz;
827 } while (!uart_circ_empty(xmit) && count < size);
828
829 pop_tx_end:
830 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
831 count, size - count, jiffies);
832
833 return count;
834 }
835
836 static int handle_rx_to(struct eg20t_port *priv)
837 {
838 struct pch_uart_buffer *buf;
839 int rx_size;
840 int ret;
841 if (!priv->start_rx) {
842 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
843 PCH_UART_HAL_RX_ERR_INT);
844 return 0;
845 }
846 buf = &priv->rxbuf;
847 do {
848 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
849 ret = push_rx(priv, buf->buf, rx_size);
850 if (ret)
851 return 0;
852 } while (rx_size == buf->size);
853
854 return PCH_UART_HANDLED_RX_INT;
855 }
856
857 static int handle_rx(struct eg20t_port *priv)
858 {
859 return handle_rx_to(priv);
860 }
861
862 static int dma_handle_rx(struct eg20t_port *priv)
863 {
864 struct uart_port *port = &priv->port;
865 struct dma_async_tx_descriptor *desc;
866 struct scatterlist *sg;
867
868 priv = container_of(port, struct eg20t_port, port);
869 sg = &priv->sg_rx;
870
871 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
872
873 sg_dma_len(sg) = priv->trigger_level;
874
875 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
876 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
877 ~PAGE_MASK);
878
879 sg_dma_address(sg) = priv->rx_buf_dma;
880
881 desc = dmaengine_prep_slave_sg(priv->chan_rx,
882 sg, 1, DMA_DEV_TO_MEM,
883 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
884
885 if (!desc)
886 return 0;
887
888 priv->desc_rx = desc;
889 desc->callback = pch_dma_rx_complete;
890 desc->callback_param = priv;
891 desc->tx_submit(desc);
892 dma_async_issue_pending(priv->chan_rx);
893
894 return PCH_UART_HANDLED_RX_INT;
895 }
896
897 static unsigned int handle_tx(struct eg20t_port *priv)
898 {
899 struct uart_port *port = &priv->port;
900 struct circ_buf *xmit = &port->state->xmit;
901 int fifo_size;
902 int tx_size;
903 int size;
904 int tx_empty;
905
906 if (!priv->start_tx) {
907 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
908 __func__, jiffies);
909 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
910 priv->tx_empty = 1;
911 return 0;
912 }
913
914 fifo_size = max(priv->fifo_size, 1);
915 tx_empty = 1;
916 if (pop_tx_x(priv, xmit->buf)) {
917 pch_uart_hal_write(priv, xmit->buf, 1);
918 port->icount.tx++;
919 tx_empty = 0;
920 fifo_size--;
921 }
922 size = min(xmit->head - xmit->tail, fifo_size);
923 if (size < 0)
924 size = fifo_size;
925
926 tx_size = pop_tx(priv, size);
927 if (tx_size > 0) {
928 port->icount.tx += tx_size;
929 tx_empty = 0;
930 }
931
932 priv->tx_empty = tx_empty;
933
934 if (tx_empty) {
935 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
936 uart_write_wakeup(port);
937 }
938
939 return PCH_UART_HANDLED_TX_INT;
940 }
941
942 static unsigned int dma_handle_tx(struct eg20t_port *priv)
943 {
944 struct uart_port *port = &priv->port;
945 struct circ_buf *xmit = &port->state->xmit;
946 struct scatterlist *sg;
947 int nent;
948 int fifo_size;
949 int tx_empty;
950 struct dma_async_tx_descriptor *desc;
951 int num;
952 int i;
953 int bytes;
954 int size;
955 int rem;
956
957 if (!priv->start_tx) {
958 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
959 __func__, jiffies);
960 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
961 priv->tx_empty = 1;
962 return 0;
963 }
964
965 if (priv->tx_dma_use) {
966 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
967 __func__, jiffies);
968 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
969 priv->tx_empty = 1;
970 return 0;
971 }
972
973 fifo_size = max(priv->fifo_size, 1);
974 tx_empty = 1;
975 if (pop_tx_x(priv, xmit->buf)) {
976 pch_uart_hal_write(priv, xmit->buf, 1);
977 port->icount.tx++;
978 tx_empty = 0;
979 fifo_size--;
980 }
981
982 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
983 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
984 xmit->tail, UART_XMIT_SIZE));
985 if (!bytes) {
986 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
987 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
988 uart_write_wakeup(port);
989 return 0;
990 }
991
992 if (bytes > fifo_size) {
993 num = bytes / fifo_size + 1;
994 size = fifo_size;
995 rem = bytes % fifo_size;
996 } else {
997 num = 1;
998 size = bytes;
999 rem = bytes;
1000 }
1001
1002 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
1003 __func__, num, size, rem);
1004
1005 priv->tx_dma_use = 1;
1006
1007 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1008 if (!priv->sg_tx_p) {
1009 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
1010 return 0;
1011 }
1012
1013 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
1014 sg = priv->sg_tx_p;
1015
1016 for (i = 0; i < num; i++, sg++) {
1017 if (i == (num - 1))
1018 sg_set_page(sg, virt_to_page(xmit->buf),
1019 rem, fifo_size * i);
1020 else
1021 sg_set_page(sg, virt_to_page(xmit->buf),
1022 size, fifo_size * i);
1023 }
1024
1025 sg = priv->sg_tx_p;
1026 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
1027 if (!nent) {
1028 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
1029 return 0;
1030 }
1031 priv->nent = nent;
1032
1033 for (i = 0; i < nent; i++, sg++) {
1034 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1035 fifo_size * i;
1036 sg_dma_address(sg) = (sg_dma_address(sg) &
1037 ~(UART_XMIT_SIZE - 1)) + sg->offset;
1038 if (i == (nent - 1))
1039 sg_dma_len(sg) = rem;
1040 else
1041 sg_dma_len(sg) = size;
1042 }
1043
1044 desc = dmaengine_prep_slave_sg(priv->chan_tx,
1045 priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1046 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1047 if (!desc) {
1048 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
1049 __func__);
1050 return 0;
1051 }
1052 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1053 priv->desc_tx = desc;
1054 desc->callback = pch_dma_tx_complete;
1055 desc->callback_param = priv;
1056
1057 desc->tx_submit(desc);
1058
1059 dma_async_issue_pending(priv->chan_tx);
1060
1061 return PCH_UART_HANDLED_TX_INT;
1062 }
1063
1064 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1065 {
1066 struct uart_port *port = &priv->port;
1067 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1068 char *error_msg[5] = {};
1069 int i = 0;
1070
1071 if (lsr & PCH_UART_LSR_ERR)
1072 error_msg[i++] = "Error data in FIFO\n";
1073
1074 if (lsr & UART_LSR_FE) {
1075 port->icount.frame++;
1076 error_msg[i++] = " Framing Error\n";
1077 }
1078
1079 if (lsr & UART_LSR_PE) {
1080 port->icount.parity++;
1081 error_msg[i++] = " Parity Error\n";
1082 }
1083
1084 if (lsr & UART_LSR_OE) {
1085 port->icount.overrun++;
1086 error_msg[i++] = " Overrun Error\n";
1087 }
1088
1089 if (tty == NULL) {
1090 for (i = 0; error_msg[i] != NULL; i++)
1091 dev_err(&priv->pdev->dev, error_msg[i]);
1092 } else {
1093 tty_kref_put(tty);
1094 }
1095 }
1096
1097 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1098 {
1099 struct eg20t_port *priv = dev_id;
1100 unsigned int handled;
1101 u8 lsr;
1102 int ret = 0;
1103 unsigned char iid;
1104 unsigned long flags;
1105 int next = 1;
1106 u8 msr;
1107
1108 spin_lock_irqsave(&priv->lock, flags);
1109 handled = 0;
1110 while (next) {
1111 iid = pch_uart_hal_get_iid(priv);
1112 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1113 break;
1114 switch (iid) {
1115 case PCH_UART_IID_RLS: /* Receiver Line Status */
1116 lsr = pch_uart_hal_get_line_status(priv);
1117 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1118 UART_LSR_PE | UART_LSR_OE)) {
1119 pch_uart_err_ir(priv, lsr);
1120 ret = PCH_UART_HANDLED_RX_ERR_INT;
1121 } else {
1122 ret = PCH_UART_HANDLED_LS_INT;
1123 }
1124 break;
1125 case PCH_UART_IID_RDR: /* Received Data Ready */
1126 if (priv->use_dma) {
1127 pch_uart_hal_disable_interrupt(priv,
1128 PCH_UART_HAL_RX_INT |
1129 PCH_UART_HAL_RX_ERR_INT);
1130 ret = dma_handle_rx(priv);
1131 if (!ret)
1132 pch_uart_hal_enable_interrupt(priv,
1133 PCH_UART_HAL_RX_INT |
1134 PCH_UART_HAL_RX_ERR_INT);
1135 } else {
1136 ret = handle_rx(priv);
1137 }
1138 break;
1139 case PCH_UART_IID_RDR_TO: /* Received Data Ready
1140 (FIFO Timeout) */
1141 ret = handle_rx_to(priv);
1142 break;
1143 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1144 Empty */
1145 if (priv->use_dma)
1146 ret = dma_handle_tx(priv);
1147 else
1148 ret = handle_tx(priv);
1149 break;
1150 case PCH_UART_IID_MS: /* Modem Status */
1151 msr = pch_uart_hal_get_modem(priv);
1152 next = 0; /* MS ir prioirty is the lowest. So, MS ir
1153 means final interrupt */
1154 if ((msr & UART_MSR_ANY_DELTA) == 0)
1155 break;
1156 ret |= PCH_UART_HANDLED_MS_INT;
1157 break;
1158 default: /* Never junp to this label */
1159 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1160 iid, jiffies);
1161 ret = -1;
1162 next = 0;
1163 break;
1164 }
1165 handled |= (unsigned int)ret;
1166 }
1167
1168 spin_unlock_irqrestore(&priv->lock, flags);
1169 return IRQ_RETVAL(handled);
1170 }
1171
1172 /* This function tests whether the transmitter fifo and shifter for the port
1173 described by 'port' is empty. */
1174 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1175 {
1176 struct eg20t_port *priv;
1177
1178 priv = container_of(port, struct eg20t_port, port);
1179 if (priv->tx_empty)
1180 return TIOCSER_TEMT;
1181 else
1182 return 0;
1183 }
1184
1185 /* Returns the current state of modem control inputs. */
1186 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1187 {
1188 struct eg20t_port *priv;
1189 u8 modem;
1190 unsigned int ret = 0;
1191
1192 priv = container_of(port, struct eg20t_port, port);
1193 modem = pch_uart_hal_get_modem(priv);
1194
1195 if (modem & UART_MSR_DCD)
1196 ret |= TIOCM_CAR;
1197
1198 if (modem & UART_MSR_RI)
1199 ret |= TIOCM_RNG;
1200
1201 if (modem & UART_MSR_DSR)
1202 ret |= TIOCM_DSR;
1203
1204 if (modem & UART_MSR_CTS)
1205 ret |= TIOCM_CTS;
1206
1207 return ret;
1208 }
1209
1210 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1211 {
1212 u32 mcr = 0;
1213 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1214
1215 if (mctrl & TIOCM_DTR)
1216 mcr |= UART_MCR_DTR;
1217 if (mctrl & TIOCM_RTS)
1218 mcr |= UART_MCR_RTS;
1219 if (mctrl & TIOCM_LOOP)
1220 mcr |= UART_MCR_LOOP;
1221
1222 if (priv->mcr & UART_MCR_AFE)
1223 mcr |= UART_MCR_AFE;
1224
1225 if (mctrl)
1226 iowrite8(mcr, priv->membase + UART_MCR);
1227 }
1228
1229 static void pch_uart_stop_tx(struct uart_port *port)
1230 {
1231 struct eg20t_port *priv;
1232 priv = container_of(port, struct eg20t_port, port);
1233 priv->start_tx = 0;
1234 priv->tx_dma_use = 0;
1235 }
1236
1237 static void pch_uart_start_tx(struct uart_port *port)
1238 {
1239 struct eg20t_port *priv;
1240
1241 priv = container_of(port, struct eg20t_port, port);
1242
1243 if (priv->use_dma) {
1244 if (priv->tx_dma_use) {
1245 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1246 __func__);
1247 return;
1248 }
1249 }
1250
1251 priv->start_tx = 1;
1252 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1253 }
1254
1255 static void pch_uart_stop_rx(struct uart_port *port)
1256 {
1257 struct eg20t_port *priv;
1258 priv = container_of(port, struct eg20t_port, port);
1259 priv->start_rx = 0;
1260 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1261 PCH_UART_HAL_RX_ERR_INT);
1262 }
1263
1264 /* Enable the modem status interrupts. */
1265 static void pch_uart_enable_ms(struct uart_port *port)
1266 {
1267 struct eg20t_port *priv;
1268 priv = container_of(port, struct eg20t_port, port);
1269 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1270 }
1271
1272 /* Control the transmission of a break signal. */
1273 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1274 {
1275 struct eg20t_port *priv;
1276 unsigned long flags;
1277
1278 priv = container_of(port, struct eg20t_port, port);
1279 spin_lock_irqsave(&priv->lock, flags);
1280 pch_uart_hal_set_break(priv, ctl);
1281 spin_unlock_irqrestore(&priv->lock, flags);
1282 }
1283
1284 /* Grab any interrupt resources and initialise any low level driver state. */
1285 static int pch_uart_startup(struct uart_port *port)
1286 {
1287 struct eg20t_port *priv;
1288 int ret;
1289 int fifo_size;
1290 int trigger_level;
1291
1292 priv = container_of(port, struct eg20t_port, port);
1293 priv->tx_empty = 1;
1294
1295 if (port->uartclk)
1296 priv->uartclk = port->uartclk;
1297 else
1298 port->uartclk = priv->uartclk;
1299
1300 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1301 ret = pch_uart_hal_set_line(priv, default_baud,
1302 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1303 PCH_UART_HAL_STB1);
1304 if (ret)
1305 return ret;
1306
1307 switch (priv->fifo_size) {
1308 case 256:
1309 fifo_size = PCH_UART_HAL_FIFO256;
1310 break;
1311 case 64:
1312 fifo_size = PCH_UART_HAL_FIFO64;
1313 break;
1314 case 16:
1315 fifo_size = PCH_UART_HAL_FIFO16;
1316 break;
1317 case 1:
1318 default:
1319 fifo_size = PCH_UART_HAL_FIFO_DIS;
1320 break;
1321 }
1322
1323 switch (priv->trigger) {
1324 case PCH_UART_HAL_TRIGGER1:
1325 trigger_level = 1;
1326 break;
1327 case PCH_UART_HAL_TRIGGER_L:
1328 trigger_level = priv->fifo_size / 4;
1329 break;
1330 case PCH_UART_HAL_TRIGGER_M:
1331 trigger_level = priv->fifo_size / 2;
1332 break;
1333 case PCH_UART_HAL_TRIGGER_H:
1334 default:
1335 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1336 break;
1337 }
1338
1339 priv->trigger_level = trigger_level;
1340 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1341 fifo_size, priv->trigger);
1342 if (ret < 0)
1343 return ret;
1344
1345 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1346 KBUILD_MODNAME, priv);
1347 if (ret < 0)
1348 return ret;
1349
1350 if (priv->use_dma)
1351 pch_request_dma(port);
1352
1353 priv->start_rx = 1;
1354 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1355 PCH_UART_HAL_RX_ERR_INT);
1356 uart_update_timeout(port, CS8, default_baud);
1357
1358 return 0;
1359 }
1360
1361 static void pch_uart_shutdown(struct uart_port *port)
1362 {
1363 struct eg20t_port *priv;
1364 int ret;
1365
1366 priv = container_of(port, struct eg20t_port, port);
1367 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1368 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1369 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1370 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1371 if (ret)
1372 dev_err(priv->port.dev,
1373 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1374
1375 pch_free_dma(port);
1376
1377 free_irq(priv->port.irq, priv);
1378 }
1379
1380 /* Change the port parameters, including word length, parity, stop
1381 *bits. Update read_status_mask and ignore_status_mask to indicate
1382 *the types of events we are interested in receiving. */
1383 static void pch_uart_set_termios(struct uart_port *port,
1384 struct ktermios *termios, struct ktermios *old)
1385 {
1386 int rtn;
1387 unsigned int baud, parity, bits, stb;
1388 struct eg20t_port *priv;
1389 unsigned long flags;
1390
1391 priv = container_of(port, struct eg20t_port, port);
1392 switch (termios->c_cflag & CSIZE) {
1393 case CS5:
1394 bits = PCH_UART_HAL_5BIT;
1395 break;
1396 case CS6:
1397 bits = PCH_UART_HAL_6BIT;
1398 break;
1399 case CS7:
1400 bits = PCH_UART_HAL_7BIT;
1401 break;
1402 default: /* CS8 */
1403 bits = PCH_UART_HAL_8BIT;
1404 break;
1405 }
1406 if (termios->c_cflag & CSTOPB)
1407 stb = PCH_UART_HAL_STB2;
1408 else
1409 stb = PCH_UART_HAL_STB1;
1410
1411 if (termios->c_cflag & PARENB) {
1412 if (termios->c_cflag & PARODD)
1413 parity = PCH_UART_HAL_PARITY_ODD;
1414 else
1415 parity = PCH_UART_HAL_PARITY_EVEN;
1416
1417 } else
1418 parity = PCH_UART_HAL_PARITY_NONE;
1419
1420 /* Only UART0 has auto hardware flow function */
1421 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1422 priv->mcr |= UART_MCR_AFE;
1423 else
1424 priv->mcr &= ~UART_MCR_AFE;
1425
1426 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1427
1428 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1429
1430 spin_lock_irqsave(&priv->lock, flags);
1431 spin_lock(&port->lock);
1432
1433 uart_update_timeout(port, termios->c_cflag, baud);
1434 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1435 if (rtn)
1436 goto out;
1437
1438 pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1439 /* Don't rewrite B0 */
1440 if (tty_termios_baud_rate(termios))
1441 tty_termios_encode_baud_rate(termios, baud, baud);
1442
1443 out:
1444 spin_unlock(&port->lock);
1445 spin_unlock_irqrestore(&priv->lock, flags);
1446 }
1447
1448 static const char *pch_uart_type(struct uart_port *port)
1449 {
1450 return KBUILD_MODNAME;
1451 }
1452
1453 static void pch_uart_release_port(struct uart_port *port)
1454 {
1455 struct eg20t_port *priv;
1456
1457 priv = container_of(port, struct eg20t_port, port);
1458 pci_iounmap(priv->pdev, priv->membase);
1459 pci_release_regions(priv->pdev);
1460 }
1461
1462 static int pch_uart_request_port(struct uart_port *port)
1463 {
1464 struct eg20t_port *priv;
1465 int ret;
1466 void __iomem *membase;
1467
1468 priv = container_of(port, struct eg20t_port, port);
1469 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1470 if (ret < 0)
1471 return -EBUSY;
1472
1473 membase = pci_iomap(priv->pdev, 1, 0);
1474 if (!membase) {
1475 pci_release_regions(priv->pdev);
1476 return -EBUSY;
1477 }
1478 priv->membase = port->membase = membase;
1479
1480 return 0;
1481 }
1482
1483 static void pch_uart_config_port(struct uart_port *port, int type)
1484 {
1485 struct eg20t_port *priv;
1486
1487 priv = container_of(port, struct eg20t_port, port);
1488 if (type & UART_CONFIG_TYPE) {
1489 port->type = priv->port_type;
1490 pch_uart_request_port(port);
1491 }
1492 }
1493
1494 static int pch_uart_verify_port(struct uart_port *port,
1495 struct serial_struct *serinfo)
1496 {
1497 struct eg20t_port *priv;
1498
1499 priv = container_of(port, struct eg20t_port, port);
1500 if (serinfo->flags & UPF_LOW_LATENCY) {
1501 dev_info(priv->port.dev,
1502 "PCH UART : Use PIO Mode (without DMA)\n");
1503 priv->use_dma = 0;
1504 serinfo->flags &= ~UPF_LOW_LATENCY;
1505 } else {
1506 #ifndef CONFIG_PCH_DMA
1507 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1508 __func__);
1509 return -EOPNOTSUPP;
1510 #endif
1511 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1512 if (!priv->use_dma)
1513 pch_request_dma(port);
1514 priv->use_dma = 1;
1515 }
1516
1517 return 0;
1518 }
1519
1520 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1521 /*
1522 * Wait for transmitter & holding register to empty
1523 */
1524 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1525 {
1526 unsigned int status, tmout = 10000;
1527
1528 /* Wait up to 10ms for the character(s) to be sent. */
1529 for (;;) {
1530 status = ioread8(up->membase + UART_LSR);
1531
1532 if ((status & bits) == bits)
1533 break;
1534 if (--tmout == 0)
1535 break;
1536 udelay(1);
1537 }
1538
1539 /* Wait up to 1s for flow control if necessary */
1540 if (up->port.flags & UPF_CONS_FLOW) {
1541 unsigned int tmout;
1542 for (tmout = 1000000; tmout; tmout--) {
1543 unsigned int msr = ioread8(up->membase + UART_MSR);
1544 if (msr & UART_MSR_CTS)
1545 break;
1546 udelay(1);
1547 touch_nmi_watchdog();
1548 }
1549 }
1550 }
1551 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1552
1553 #ifdef CONFIG_CONSOLE_POLL
1554 /*
1555 * Console polling routines for communicate via uart while
1556 * in an interrupt or debug context.
1557 */
1558 static int pch_uart_get_poll_char(struct uart_port *port)
1559 {
1560 struct eg20t_port *priv =
1561 container_of(port, struct eg20t_port, port);
1562 u8 lsr = ioread8(priv->membase + UART_LSR);
1563
1564 if (!(lsr & UART_LSR_DR))
1565 return NO_POLL_CHAR;
1566
1567 return ioread8(priv->membase + PCH_UART_RBR);
1568 }
1569
1570
1571 static void pch_uart_put_poll_char(struct uart_port *port,
1572 unsigned char c)
1573 {
1574 unsigned int ier;
1575 struct eg20t_port *priv =
1576 container_of(port, struct eg20t_port, port);
1577
1578 /*
1579 * First save the IER then disable the interrupts
1580 */
1581 ier = ioread8(priv->membase + UART_IER);
1582 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1583
1584 wait_for_xmitr(priv, UART_LSR_THRE);
1585 /*
1586 * Send the character out.
1587 * If a LF, also do CR...
1588 */
1589 iowrite8(c, priv->membase + PCH_UART_THR);
1590 if (c == 10) {
1591 wait_for_xmitr(priv, UART_LSR_THRE);
1592 iowrite8(13, priv->membase + PCH_UART_THR);
1593 }
1594
1595 /*
1596 * Finally, wait for transmitter to become empty
1597 * and restore the IER
1598 */
1599 wait_for_xmitr(priv, BOTH_EMPTY);
1600 iowrite8(ier, priv->membase + UART_IER);
1601 }
1602 #endif /* CONFIG_CONSOLE_POLL */
1603
1604 static struct uart_ops pch_uart_ops = {
1605 .tx_empty = pch_uart_tx_empty,
1606 .set_mctrl = pch_uart_set_mctrl,
1607 .get_mctrl = pch_uart_get_mctrl,
1608 .stop_tx = pch_uart_stop_tx,
1609 .start_tx = pch_uart_start_tx,
1610 .stop_rx = pch_uart_stop_rx,
1611 .enable_ms = pch_uart_enable_ms,
1612 .break_ctl = pch_uart_break_ctl,
1613 .startup = pch_uart_startup,
1614 .shutdown = pch_uart_shutdown,
1615 .set_termios = pch_uart_set_termios,
1616 /* .pm = pch_uart_pm, Not supported yet */
1617 /* .set_wake = pch_uart_set_wake, Not supported yet */
1618 .type = pch_uart_type,
1619 .release_port = pch_uart_release_port,
1620 .request_port = pch_uart_request_port,
1621 .config_port = pch_uart_config_port,
1622 .verify_port = pch_uart_verify_port,
1623 #ifdef CONFIG_CONSOLE_POLL
1624 .poll_get_char = pch_uart_get_poll_char,
1625 .poll_put_char = pch_uart_put_poll_char,
1626 #endif
1627 };
1628
1629 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1630
1631 static void pch_console_putchar(struct uart_port *port, int ch)
1632 {
1633 struct eg20t_port *priv =
1634 container_of(port, struct eg20t_port, port);
1635
1636 wait_for_xmitr(priv, UART_LSR_THRE);
1637 iowrite8(ch, priv->membase + PCH_UART_THR);
1638 }
1639
1640 /*
1641 * Print a string to the serial port trying not to disturb
1642 * any possible real use of the port...
1643 *
1644 * The console_lock must be held when we get here.
1645 */
1646 static void
1647 pch_console_write(struct console *co, const char *s, unsigned int count)
1648 {
1649 struct eg20t_port *priv;
1650 unsigned long flags;
1651 int priv_locked = 1;
1652 int port_locked = 1;
1653 u8 ier;
1654
1655 priv = pch_uart_ports[co->index];
1656
1657 touch_nmi_watchdog();
1658
1659 local_irq_save(flags);
1660 if (priv->port.sysrq) {
1661 /* call to uart_handle_sysrq_char already took the priv lock */
1662 priv_locked = 0;
1663 /* serial8250_handle_port() already took the port lock */
1664 port_locked = 0;
1665 } else if (oops_in_progress) {
1666 priv_locked = spin_trylock(&priv->lock);
1667 port_locked = spin_trylock(&priv->port.lock);
1668 } else {
1669 spin_lock(&priv->lock);
1670 spin_lock(&priv->port.lock);
1671 }
1672
1673 /*
1674 * First save the IER then disable the interrupts
1675 */
1676 ier = ioread8(priv->membase + UART_IER);
1677
1678 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1679
1680 uart_console_write(&priv->port, s, count, pch_console_putchar);
1681
1682 /*
1683 * Finally, wait for transmitter to become empty
1684 * and restore the IER
1685 */
1686 wait_for_xmitr(priv, BOTH_EMPTY);
1687 iowrite8(ier, priv->membase + UART_IER);
1688
1689 if (port_locked)
1690 spin_unlock(&priv->port.lock);
1691 if (priv_locked)
1692 spin_unlock(&priv->lock);
1693 local_irq_restore(flags);
1694 }
1695
1696 static int __init pch_console_setup(struct console *co, char *options)
1697 {
1698 struct uart_port *port;
1699 int baud = default_baud;
1700 int bits = 8;
1701 int parity = 'n';
1702 int flow = 'n';
1703
1704 /*
1705 * Check whether an invalid uart number has been specified, and
1706 * if so, search for the first available port that does have
1707 * console support.
1708 */
1709 if (co->index >= PCH_UART_NR)
1710 co->index = 0;
1711 port = &pch_uart_ports[co->index]->port;
1712
1713 if (!port || (!port->iobase && !port->membase))
1714 return -ENODEV;
1715
1716 port->uartclk = pch_uart_get_uartclk();
1717
1718 if (options)
1719 uart_parse_options(options, &baud, &parity, &bits, &flow);
1720
1721 return uart_set_options(port, co, baud, parity, bits, flow);
1722 }
1723
1724 static struct uart_driver pch_uart_driver;
1725
1726 static struct console pch_console = {
1727 .name = PCH_UART_DRIVER_DEVICE,
1728 .write = pch_console_write,
1729 .device = uart_console_device,
1730 .setup = pch_console_setup,
1731 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1732 .index = -1,
1733 .data = &pch_uart_driver,
1734 };
1735
1736 #define PCH_CONSOLE (&pch_console)
1737 #else
1738 #define PCH_CONSOLE NULL
1739 #endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1740
1741 static struct uart_driver pch_uart_driver = {
1742 .owner = THIS_MODULE,
1743 .driver_name = KBUILD_MODNAME,
1744 .dev_name = PCH_UART_DRIVER_DEVICE,
1745 .major = 0,
1746 .minor = 0,
1747 .nr = PCH_UART_NR,
1748 .cons = PCH_CONSOLE,
1749 };
1750
1751 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1752 const struct pci_device_id *id)
1753 {
1754 struct eg20t_port *priv;
1755 int ret;
1756 unsigned int iobase;
1757 unsigned int mapbase;
1758 unsigned char *rxbuf;
1759 int fifosize;
1760 int port_type;
1761 struct pch_uart_driver_data *board;
1762 char name[32]; /* for debugfs file name */
1763
1764 board = &drv_dat[id->driver_data];
1765 port_type = board->port_type;
1766
1767 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1768 if (priv == NULL)
1769 goto init_port_alloc_err;
1770
1771 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1772 if (!rxbuf)
1773 goto init_port_free_txbuf;
1774
1775 switch (port_type) {
1776 case PORT_UNKNOWN:
1777 fifosize = 256; /* EG20T/ML7213: UART0 */
1778 break;
1779 case PORT_8250:
1780 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1781 break;
1782 default:
1783 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1784 goto init_port_hal_free;
1785 }
1786
1787 pci_enable_msi(pdev);
1788 pci_set_master(pdev);
1789
1790 spin_lock_init(&priv->lock);
1791
1792 iobase = pci_resource_start(pdev, 0);
1793 mapbase = pci_resource_start(pdev, 1);
1794 priv->mapbase = mapbase;
1795 priv->iobase = iobase;
1796 priv->pdev = pdev;
1797 priv->tx_empty = 1;
1798 priv->rxbuf.buf = rxbuf;
1799 priv->rxbuf.size = PAGE_SIZE;
1800
1801 priv->fifo_size = fifosize;
1802 priv->uartclk = pch_uart_get_uartclk();
1803 priv->port_type = PORT_MAX_8250 + port_type + 1;
1804 priv->port.dev = &pdev->dev;
1805 priv->port.iobase = iobase;
1806 priv->port.membase = NULL;
1807 priv->port.mapbase = mapbase;
1808 priv->port.irq = pdev->irq;
1809 priv->port.iotype = UPIO_PORT;
1810 priv->port.ops = &pch_uart_ops;
1811 priv->port.flags = UPF_BOOT_AUTOCONF;
1812 priv->port.fifosize = fifosize;
1813 priv->port.line = board->line_no;
1814 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1815
1816 spin_lock_init(&priv->port.lock);
1817
1818 pci_set_drvdata(pdev, priv);
1819 priv->trigger_level = 1;
1820 priv->fcr = 0;
1821
1822 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1823 pch_uart_ports[board->line_no] = priv;
1824 #endif
1825 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1826 if (ret < 0)
1827 goto init_port_hal_free;
1828
1829 #ifdef CONFIG_DEBUG_FS
1830 snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1831 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1832 NULL, priv, &port_regs_ops);
1833 #endif
1834
1835 return priv;
1836
1837 init_port_hal_free:
1838 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1839 pch_uart_ports[board->line_no] = NULL;
1840 #endif
1841 free_page((unsigned long)rxbuf);
1842 init_port_free_txbuf:
1843 kfree(priv);
1844 init_port_alloc_err:
1845
1846 return NULL;
1847 }
1848
1849 static void pch_uart_exit_port(struct eg20t_port *priv)
1850 {
1851
1852 #ifdef CONFIG_DEBUG_FS
1853 if (priv->debugfs)
1854 debugfs_remove(priv->debugfs);
1855 #endif
1856 uart_remove_one_port(&pch_uart_driver, &priv->port);
1857 pci_set_drvdata(priv->pdev, NULL);
1858 free_page((unsigned long)priv->rxbuf.buf);
1859 }
1860
1861 static void pch_uart_pci_remove(struct pci_dev *pdev)
1862 {
1863 struct eg20t_port *priv = pci_get_drvdata(pdev);
1864
1865 pci_disable_msi(pdev);
1866
1867 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1868 pch_uart_ports[priv->port.line] = NULL;
1869 #endif
1870 pch_uart_exit_port(priv);
1871 pci_disable_device(pdev);
1872 kfree(priv);
1873 return;
1874 }
1875 #ifdef CONFIG_PM
1876 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1877 {
1878 struct eg20t_port *priv = pci_get_drvdata(pdev);
1879
1880 uart_suspend_port(&pch_uart_driver, &priv->port);
1881
1882 pci_save_state(pdev);
1883 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1884 return 0;
1885 }
1886
1887 static int pch_uart_pci_resume(struct pci_dev *pdev)
1888 {
1889 struct eg20t_port *priv = pci_get_drvdata(pdev);
1890 int ret;
1891
1892 pci_set_power_state(pdev, PCI_D0);
1893 pci_restore_state(pdev);
1894
1895 ret = pci_enable_device(pdev);
1896 if (ret) {
1897 dev_err(&pdev->dev,
1898 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1899 return ret;
1900 }
1901
1902 uart_resume_port(&pch_uart_driver, &priv->port);
1903
1904 return 0;
1905 }
1906 #else
1907 #define pch_uart_pci_suspend NULL
1908 #define pch_uart_pci_resume NULL
1909 #endif
1910
1911 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1912 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1913 .driver_data = pch_et20t_uart0},
1914 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1915 .driver_data = pch_et20t_uart1},
1916 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1917 .driver_data = pch_et20t_uart2},
1918 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1919 .driver_data = pch_et20t_uart3},
1920 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1921 .driver_data = pch_ml7213_uart0},
1922 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1923 .driver_data = pch_ml7213_uart1},
1924 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1925 .driver_data = pch_ml7213_uart2},
1926 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1927 .driver_data = pch_ml7223_uart0},
1928 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1929 .driver_data = pch_ml7223_uart1},
1930 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1931 .driver_data = pch_ml7831_uart0},
1932 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1933 .driver_data = pch_ml7831_uart1},
1934 {0,},
1935 };
1936
1937 static int pch_uart_pci_probe(struct pci_dev *pdev,
1938 const struct pci_device_id *id)
1939 {
1940 int ret;
1941 struct eg20t_port *priv;
1942
1943 ret = pci_enable_device(pdev);
1944 if (ret < 0)
1945 goto probe_error;
1946
1947 priv = pch_uart_init_port(pdev, id);
1948 if (!priv) {
1949 ret = -EBUSY;
1950 goto probe_disable_device;
1951 }
1952 pci_set_drvdata(pdev, priv);
1953
1954 return ret;
1955
1956 probe_disable_device:
1957 pci_disable_msi(pdev);
1958 pci_disable_device(pdev);
1959 probe_error:
1960 return ret;
1961 }
1962
1963 static struct pci_driver pch_uart_pci_driver = {
1964 .name = "pch_uart",
1965 .id_table = pch_uart_pci_id,
1966 .probe = pch_uart_pci_probe,
1967 .remove = pch_uart_pci_remove,
1968 .suspend = pch_uart_pci_suspend,
1969 .resume = pch_uart_pci_resume,
1970 };
1971
1972 static int __init pch_uart_module_init(void)
1973 {
1974 int ret;
1975
1976 /* register as UART driver */
1977 ret = uart_register_driver(&pch_uart_driver);
1978 if (ret < 0)
1979 return ret;
1980
1981 /* register as PCI driver */
1982 ret = pci_register_driver(&pch_uart_pci_driver);
1983 if (ret < 0)
1984 uart_unregister_driver(&pch_uart_driver);
1985
1986 return ret;
1987 }
1988 module_init(pch_uart_module_init);
1989
1990 static void __exit pch_uart_module_exit(void)
1991 {
1992 pci_unregister_driver(&pch_uart_pci_driver);
1993 uart_unregister_driver(&pch_uart_driver);
1994 }
1995 module_exit(pch_uart_module_exit);
1996
1997 MODULE_LICENSE("GPL v2");
1998 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1999 module_param(default_baud, uint, S_IRUGO);
2000 MODULE_PARM_DESC(default_baud,
2001 "Default BAUD for initial driver state and console (default 9600)");
2002 module_param(user_uartclk, uint, S_IRUGO);
2003 MODULE_PARM_DESC(user_uartclk,
2004 "Override UART default or board specific UART clock");
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