drivers/tty/serial/qcom_geni_serial.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
   3
   4 #if defined(CONFIG_SERIAL_QCOM_GENI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
   5 # define SUPPORT_SYSRQ
   6 #endif
   7
   8 #include <linux/clk.h>
   9 #include <linux/console.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/of_device.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/qcom-geni-se.h>
  17 #include <linux/serial.h>
  18 #include <linux/serial_core.h>
  19 #include <linux/slab.h>
  20 #include <linux/tty.h>
  21 #include <linux/tty_flip.h>
  22
  23 /* UART specific GENI registers */
  24 #define SE_UART_LOOPBACK_CFG            0x22c
  25 #define SE_UART_TX_TRANS_CFG            0x25c
  26 #define SE_UART_TX_WORD_LEN             0x268
  27 #define SE_UART_TX_STOP_BIT_LEN         0x26c
  28 #define SE_UART_TX_TRANS_LEN            0x270
  29 #define SE_UART_RX_TRANS_CFG            0x280
  30 #define SE_UART_RX_WORD_LEN             0x28c
  31 #define SE_UART_RX_STALE_CNT            0x294
  32 #define SE_UART_TX_PARITY_CFG           0x2a4
  33 #define SE_UART_RX_PARITY_CFG           0x2a8
  34 #define SE_UART_MANUAL_RFR              0x2ac
  35
  36 /* SE_UART_TRANS_CFG */
  37 #define UART_TX_PAR_EN          BIT(0)
  38 #define UART_CTS_MASK           BIT(1)
  39
  40 /* SE_UART_TX_WORD_LEN */
  41 #define TX_WORD_LEN_MSK         GENMASK(9, 0)
  42
  43 /* SE_UART_TX_STOP_BIT_LEN */
  44 #define TX_STOP_BIT_LEN_MSK     GENMASK(23, 0)
  45 #define TX_STOP_BIT_LEN_1       0
  46 #define TX_STOP_BIT_LEN_1_5     1
  47 #define TX_STOP_BIT_LEN_2       2
  48
  49 /* SE_UART_TX_TRANS_LEN */
  50 #define TX_TRANS_LEN_MSK        GENMASK(23, 0)
  51
  52 /* SE_UART_RX_TRANS_CFG */
  53 #define UART_RX_INS_STATUS_BIT  BIT(2)
  54 #define UART_RX_PAR_EN          BIT(3)
  55
  56 /* SE_UART_RX_WORD_LEN */
  57 #define RX_WORD_LEN_MASK        GENMASK(9, 0)
  58
  59 /* SE_UART_RX_STALE_CNT */
  60 #define RX_STALE_CNT            GENMASK(23, 0)
  61
  62 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
  63 #define PAR_CALC_EN             BIT(0)
  64 #define PAR_MODE_MSK            GENMASK(2, 1)
  65 #define PAR_MODE_SHFT           1
  66 #define PAR_EVEN                0x00
  67 #define PAR_ODD                 0x01
  68 #define PAR_SPACE               0x10
  69 #define PAR_MARK                0x11
  70
  71 /* SE_UART_MANUAL_RFR register fields */
  72 #define UART_MANUAL_RFR_EN      BIT(31)
  73 #define UART_RFR_NOT_READY      BIT(1)
  74 #define UART_RFR_READY          BIT(0)
  75
  76 /* UART M_CMD OP codes */
  77 #define UART_START_TX           0x1
  78 #define UART_START_BREAK        0x4
  79 #define UART_STOP_BREAK         0x5
  80 /* UART S_CMD OP codes */
  81 #define UART_START_READ         0x1
  82 #define UART_PARAM              0x1
  83
  84 #define UART_OVERSAMPLING       32
  85 #define STALE_TIMEOUT           16
  86 #define DEFAULT_BITS_PER_CHAR   10
  87 #define GENI_UART_CONS_PORTS    1
  88 #define GENI_UART_PORTS         3
  89 #define DEF_FIFO_DEPTH_WORDS    16
  90 #define DEF_TX_WM               2
  91 #define DEF_FIFO_WIDTH_BITS     32
  92 #define UART_RX_WM              2
  93 #define MAX_LOOPBACK_CFG        3
  94
  95 #ifdef CONFIG_CONSOLE_POLL
  96 #define CONSOLE_RX_BYTES_PW 1
  97 #else
  98 #define CONSOLE_RX_BYTES_PW 4
  99 #endif
 100
 101 struct qcom_geni_serial_port {
 102         struct uart_port uport;
 103         struct geni_se se;
 104         char name[20];
 105         u32 tx_fifo_depth;
 106         u32 tx_fifo_width;
 107         u32 rx_fifo_depth;
 108         bool setup;
 109         int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
 110         unsigned int baud;
 111         unsigned int tx_bytes_pw;
 112         unsigned int rx_bytes_pw;
 113         u32 *rx_fifo;
 114         u32 loopback;
 115         bool brk;
 116
 117         unsigned int tx_remaining;
 118 };
 119
 120 static const struct uart_ops qcom_geni_console_pops;
 121 static const struct uart_ops qcom_geni_uart_pops;
 122 static struct uart_driver qcom_geni_console_driver;
 123 static struct uart_driver qcom_geni_uart_driver;
 124 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
 125 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
 126 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
 127 static void qcom_geni_serial_stop_rx(struct uart_port *uport);
 128
 129 static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
 130                                         32000000, 48000000, 64000000, 80000000,
 131                                         96000000, 100000000, 102400000,
 132                                         112000000, 120000000, 128000000};
 133
 134 #define to_dev_port(ptr, member) \
 135                 container_of(ptr, struct qcom_geni_serial_port, member)
 136
 137 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
 138         [0] = {
 139                 .uport = {
 140                                 .iotype = UPIO_MEM,
 141                                 .ops = &qcom_geni_uart_pops,
 142                                 .flags = UPF_BOOT_AUTOCONF,
 143                                 .line = 0,
 144                 },
 145         },
 146         [1] = {
 147                 .uport = {
 148                                 .iotype = UPIO_MEM,
 149                                 .ops = &qcom_geni_uart_pops,
 150                                 .flags = UPF_BOOT_AUTOCONF,
 151                                 .line = 1,
 152                 },
 153         },
 154         [2] = {
 155                 .uport = {
 156                                 .iotype = UPIO_MEM,
 157                                 .ops = &qcom_geni_uart_pops,
 158                                 .flags = UPF_BOOT_AUTOCONF,
 159                                 .line = 2,
 160                 },
 161         },
 162 };
 163
 164 static ssize_t loopback_show(struct device *dev,
 165                                 struct device_attribute *attr, char *buf)
 166 {
 167         struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
 168
 169         return snprintf(buf, sizeof(u32), "%d\n", port->loopback);
 170 }
 171
 172 static ssize_t loopback_store(struct device *dev,
 173                                 struct device_attribute *attr, const char *buf,
 174                                 size_t size)
 175 {
 176         struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
 177         u32 loopback;
 178
 179         if (kstrtoint(buf, 0, &loopback) || loopback > MAX_LOOPBACK_CFG) {
 180                 dev_err(dev, "Invalid input\n");
 181                 return -EINVAL;
 182         }
 183         port->loopback = loopback;
 184         return size;
 185 }
 186 static DEVICE_ATTR_RW(loopback);
 187
 188 static struct qcom_geni_serial_port qcom_geni_console_port = {
 189         .uport = {
 190                 .iotype = UPIO_MEM,
 191                 .ops = &qcom_geni_console_pops,
 192                 .flags = UPF_BOOT_AUTOCONF,
 193                 .line = 0,
 194         },
 195 };
 196
 197 static int qcom_geni_serial_request_port(struct uart_port *uport)
 198 {
 199         struct platform_device *pdev = to_platform_device(uport->dev);
 200         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 201         struct resource *res;
 202
 203         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 204         uport->membase = devm_ioremap_resource(&pdev->dev, res);
 205         if (IS_ERR(uport->membase))
 206                 return PTR_ERR(uport->membase);
 207         port->se.base = uport->membase;
 208         return 0;
 209 }
 210
 211 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
 212 {
 213         if (cfg_flags & UART_CONFIG_TYPE) {
 214                 uport->type = PORT_MSM;
 215                 qcom_geni_serial_request_port(uport);
 216         }
 217 }
 218
 219 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
 220 {
 221         unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
 222         u32 geni_ios;
 223
 224         if (uart_console(uport)) {
 225                 mctrl |= TIOCM_CTS;
 226         } else {
 227                 geni_ios = readl(uport->membase + SE_GENI_IOS);
 228                 if (!(geni_ios & IO2_DATA_IN))
 229                         mctrl |= TIOCM_CTS;
 230         }
 231
 232         return mctrl;
 233 }
 234
 235 static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
 236                                                         unsigned int mctrl)
 237 {
 238         u32 uart_manual_rfr = 0;
 239
 240         if (uart_console(uport))
 241                 return;
 242
 243         if (!(mctrl & TIOCM_RTS))
 244                 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
 245         writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
 246 }
 247
 248 static const char *qcom_geni_serial_get_type(struct uart_port *uport)
 249 {
 250         return "MSM";
 251 }
 252
 253 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
 254 {
 255         struct qcom_geni_serial_port *port;
 256         int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
 257
 258         if (line < 0 || line >= nr_ports)
 259                 return ERR_PTR(-ENXIO);
 260
 261         port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
 262         return port;
 263 }
 264
 265 static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
 266                                 int offset, int field, bool set)
 267 {
 268         u32 reg;
 269         struct qcom_geni_serial_port *port;
 270         unsigned int baud;
 271         unsigned int fifo_bits;
 272         unsigned long timeout_us = 20000;
 273
 274         if (uport->private_data) {
 275                 port = to_dev_port(uport, uport);
 276                 baud = port->baud;
 277                 if (!baud)
 278                         baud = 115200;
 279                 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
 280                 /*
 281                  * Total polling iterations based on FIFO worth of bytes to be
 282                  * sent at current baud. Add a little fluff to the wait.
 283                  */
 284                 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
 285         }
 286
 287         /*
 288          * Use custom implementation instead of readl_poll_atomic since ktimer
 289          * is not ready at the time of early console.
 290          */
 291         timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
 292         while (timeout_us) {
 293                 reg = readl(uport->membase + offset);
 294                 if ((bool)(reg & field) == set)
 295                         return true;
 296                 udelay(10);
 297                 timeout_us -= 10;
 298         }
 299         return false;
 300 }
 301
 302 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
 303 {
 304         u32 m_cmd;
 305
 306         writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
 307         m_cmd = UART_START_TX << M_OPCODE_SHFT;
 308         writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
 309 }
 310
 311 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
 312 {
 313         int done;
 314         u32 irq_clear = M_CMD_DONE_EN;
 315
 316         done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 317                                                 M_CMD_DONE_EN, true);
 318         if (!done) {
 319                 writel(M_GENI_CMD_ABORT, uport->membase +
 320                                                 SE_GENI_M_CMD_CTRL_REG);
 321                 irq_clear |= M_CMD_ABORT_EN;
 322                 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 323                                                         M_CMD_ABORT_EN, true);
 324         }
 325         writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
 326 }
 327
 328 static void qcom_geni_serial_abort_rx(struct uart_port *uport)
 329 {
 330         u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
 331
 332         writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
 333         qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
 334                                         S_GENI_CMD_ABORT, false);
 335         writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
 336         writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
 337 }
 338
 339 #ifdef CONFIG_CONSOLE_POLL
 340 static int qcom_geni_serial_get_char(struct uart_port *uport)
 341 {
 342         u32 rx_fifo;
 343         u32 status;
 344
 345         status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
 346         writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
 347
 348         status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
 349         writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 350
 351         status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
 352         if (!(status & RX_FIFO_WC_MSK))
 353                 return NO_POLL_CHAR;
 354
 355         rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn);
 356         return rx_fifo & 0xff;
 357 }
 358
 359 static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
 360                                                         unsigned char c)
 361 {
 362         writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 363         qcom_geni_serial_setup_tx(uport, 1);
 364         WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 365                                                 M_TX_FIFO_WATERMARK_EN, true));
 366         writel(c, uport->membase + SE_GENI_TX_FIFOn);
 367         writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 368         qcom_geni_serial_poll_tx_done(uport);
 369 }
 370 #endif
 371
 372 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
 373 static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
 374 {
 375         writel(ch, uport->membase + SE_GENI_TX_FIFOn);
 376 }
 377
 378 static void
 379 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
 380                                  unsigned int count)
 381 {
 382         int i;
 383         u32 bytes_to_send = count;
 384
 385         for (i = 0; i < count; i++) {
 386                 /*
 387                  * uart_console_write() adds a carriage return for each newline.
 388                  * Account for additional bytes to be written.
 389                  */
 390                 if (s[i] == '\n')
 391                         bytes_to_send++;
 392         }
 393
 394         writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 395         qcom_geni_serial_setup_tx(uport, bytes_to_send);
 396         for (i = 0; i < count; ) {
 397                 size_t chars_to_write = 0;
 398                 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
 399
 400                 /*
 401                  * If the WM bit never set, then the Tx state machine is not
 402                  * in a valid state, so break, cancel/abort any existing
 403                  * command. Unfortunately the current data being written is
 404                  * lost.
 405                  */
 406                 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 407                                                 M_TX_FIFO_WATERMARK_EN, true))
 408                         break;
 409                 chars_to_write = min_t(size_t, count - i, avail / 2);
 410                 uart_console_write(uport, s + i, chars_to_write,
 411                                                 qcom_geni_serial_wr_char);
 412                 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
 413                                                         SE_GENI_M_IRQ_CLEAR);
 414                 i += chars_to_write;
 415         }
 416         qcom_geni_serial_poll_tx_done(uport);
 417 }
 418
 419 static void qcom_geni_serial_console_write(struct console *co, const char *s,
 420                               unsigned int count)
 421 {
 422         struct uart_port *uport;
 423         struct qcom_geni_serial_port *port;
 424         bool locked = true;
 425         unsigned long flags;
 426         u32 geni_status;
 427         u32 irq_en;
 428
 429         WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
 430
 431         port = get_port_from_line(co->index, true);
 432         if (IS_ERR(port))
 433                 return;
 434
 435         uport = &port->uport;
 436         if (oops_in_progress)
 437                 locked = spin_trylock_irqsave(&uport->lock, flags);
 438         else
 439                 spin_lock_irqsave(&uport->lock, flags);
 440
 441         geni_status = readl(uport->membase + SE_GENI_STATUS);
 442
 443         /* Cancel the current write to log the fault */
 444         if (!locked) {
 445                 geni_se_cancel_m_cmd(&port->se);
 446                 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 447                                                 M_CMD_CANCEL_EN, true)) {
 448                         geni_se_abort_m_cmd(&port->se);
 449                         qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 450                                                         M_CMD_ABORT_EN, true);
 451                         writel(M_CMD_ABORT_EN, uport->membase +
 452                                                         SE_GENI_M_IRQ_CLEAR);
 453                 }
 454                 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 455         } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
 456                 /*
 457                  * It seems we can't interrupt existing transfers if all data
 458                  * has been sent, in which case we need to look for done first.
 459                  */
 460                 qcom_geni_serial_poll_tx_done(uport);
 461
 462                 if (uart_circ_chars_pending(&uport->state->xmit)) {
 463                         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 464                         writel(irq_en | M_TX_FIFO_WATERMARK_EN,
 465                                         uport->membase + SE_GENI_M_IRQ_EN);
 466                 }
 467         }
 468
 469         __qcom_geni_serial_console_write(uport, s, count);
 470
 471         if (port->tx_remaining)
 472                 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
 473
 474         if (locked)
 475                 spin_unlock_irqrestore(&uport->lock, flags);
 476 }
 477
 478 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
 479 {
 480         u32 i;
 481         unsigned char buf[sizeof(u32)];
 482         struct tty_port *tport;
 483         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 484
 485         tport = &uport->state->port;
 486         for (i = 0; i < bytes; ) {
 487                 int c;
 488                 int chunk = min_t(int, bytes - i, port->rx_bytes_pw);
 489
 490                 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
 491                 i += chunk;
 492                 if (drop)
 493                         continue;
 494
 495                 for (c = 0; c < chunk; c++) {
 496                         int sysrq;
 497
 498                         uport->icount.rx++;
 499                         if (port->brk && buf[c] == 0) {
 500                                 port->brk = false;
 501                                 if (uart_handle_break(uport))
 502                                         continue;
 503                         }
 504
 505                         sysrq = uart_prepare_sysrq_char(uport, buf[c]);
 506
 507                         if (!sysrq)
 508                                 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
 509                 }
 510         }
 511         if (!drop)
 512                 tty_flip_buffer_push(tport);
 513         return 0;
 514 }
 515 #else
 516 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
 517 {
 518         return -EPERM;
 519 }
 520
 521 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
 522
 523 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
 524 {
 525         unsigned char *buf;
 526         struct tty_port *tport;
 527         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 528         u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
 529         u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
 530         int ret;
 531
 532         tport = &uport->state->port;
 533         ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
 534         if (drop)
 535                 return 0;
 536
 537         buf = (unsigned char *)port->rx_fifo;
 538         ret = tty_insert_flip_string(tport, buf, bytes);
 539         if (ret != bytes) {
 540                 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
 541                                 __func__, ret, bytes);
 542                 WARN_ON_ONCE(1);
 543         }
 544         uport->icount.rx += ret;
 545         tty_flip_buffer_push(tport);
 546         return ret;
 547 }
 548
 549 static void qcom_geni_serial_start_tx(struct uart_port *uport)
 550 {
 551         u32 irq_en;
 552         u32 status;
 553
 554         status = readl(uport->membase + SE_GENI_STATUS);
 555         if (status & M_GENI_CMD_ACTIVE)
 556                 return;
 557
 558         if (!qcom_geni_serial_tx_empty(uport))
 559                 return;
 560
 561         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 562         irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
 563
 564         writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 565         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 566 }
 567
 568 static void qcom_geni_serial_stop_tx(struct uart_port *uport)
 569 {
 570         u32 irq_en;
 571         u32 status;
 572         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 573
 574         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 575         irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
 576         writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
 577         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 578         status = readl(uport->membase + SE_GENI_STATUS);
 579         /* Possible stop tx is called multiple times. */
 580         if (!(status & M_GENI_CMD_ACTIVE))
 581                 return;
 582
 583         geni_se_cancel_m_cmd(&port->se);
 584         if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 585                                                 M_CMD_CANCEL_EN, true)) {
 586                 geni_se_abort_m_cmd(&port->se);
 587                 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 588                                                 M_CMD_ABORT_EN, true);
 589                 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 590         }
 591         writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 592 }
 593
 594 static void qcom_geni_serial_start_rx(struct uart_port *uport)
 595 {
 596         u32 irq_en;
 597         u32 status;
 598         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 599
 600         status = readl(uport->membase + SE_GENI_STATUS);
 601         if (status & S_GENI_CMD_ACTIVE)
 602                 qcom_geni_serial_stop_rx(uport);
 603
 604         geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
 605
 606         irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
 607         irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
 608         writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
 609
 610         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 611         irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
 612         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 613 }
 614
 615 static void qcom_geni_serial_stop_rx(struct uart_port *uport)
 616 {
 617         u32 irq_en;
 618         u32 status;
 619         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 620         u32 irq_clear = S_CMD_DONE_EN;
 621
 622         irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
 623         irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
 624         writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
 625
 626         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 627         irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
 628         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 629
 630         status = readl(uport->membase + SE_GENI_STATUS);
 631         /* Possible stop rx is called multiple times. */
 632         if (!(status & S_GENI_CMD_ACTIVE))
 633                 return;
 634
 635         geni_se_cancel_s_cmd(&port->se);
 636         qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
 637                                         S_GENI_CMD_CANCEL, false);
 638         status = readl(uport->membase + SE_GENI_STATUS);
 639         writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
 640         if (status & S_GENI_CMD_ACTIVE)
 641                 qcom_geni_serial_abort_rx(uport);
 642 }
 643
 644 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
 645 {
 646         u32 status;
 647         u32 word_cnt;
 648         u32 last_word_byte_cnt;
 649         u32 last_word_partial;
 650         u32 total_bytes;
 651         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 652
 653         status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
 654         word_cnt = status & RX_FIFO_WC_MSK;
 655         last_word_partial = status & RX_LAST;
 656         last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
 657                                                 RX_LAST_BYTE_VALID_SHFT;
 658
 659         if (!word_cnt)
 660                 return;
 661         total_bytes = port->rx_bytes_pw * (word_cnt - 1);
 662         if (last_word_partial && last_word_byte_cnt)
 663                 total_bytes += last_word_byte_cnt;
 664         else
 665                 total_bytes += port->rx_bytes_pw;
 666         port->handle_rx(uport, total_bytes, drop);
 667 }
 668
 669 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
 670                 bool active)
 671 {
 672         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 673         struct circ_buf *xmit = &uport->state->xmit;
 674         size_t avail;
 675         size_t remaining;
 676         size_t pending;
 677         int i;
 678         u32 status;
 679         u32 irq_en;
 680         unsigned int chunk;
 681         int tail;
 682
 683         status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
 684
 685         /* Complete the current tx command before taking newly added data */
 686         if (active)
 687                 pending = port->tx_remaining;
 688         else
 689                 pending = uart_circ_chars_pending(xmit);
 690
 691         /* All data has been transmitted and acknowledged as received */
 692         if (!pending && !status && done) {
 693                 qcom_geni_serial_stop_tx(uport);
 694                 goto out_write_wakeup;
 695         }
 696
 697         avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
 698         avail *= port->tx_bytes_pw;
 699
 700         tail = xmit->tail;
 701         chunk = min(avail, pending);
 702         if (!chunk)
 703                 goto out_write_wakeup;
 704
 705         if (!port->tx_remaining) {
 706                 qcom_geni_serial_setup_tx(uport, pending);
 707                 port->tx_remaining = pending;
 708
 709                 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 710                 if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
 711                         writel(irq_en | M_TX_FIFO_WATERMARK_EN,
 712                                         uport->membase + SE_GENI_M_IRQ_EN);
 713         }
 714
 715         remaining = chunk;
 716         for (i = 0; i < chunk; ) {
 717                 unsigned int tx_bytes;
 718                 u8 buf[sizeof(u32)];
 719                 int c;
 720
 721                 memset(buf, 0, ARRAY_SIZE(buf));
 722                 tx_bytes = min_t(size_t, remaining, port->tx_bytes_pw);
 723
 724                 for (c = 0; c < tx_bytes ; c++) {
 725                         buf[c] = xmit->buf[tail++];
 726                         tail &= UART_XMIT_SIZE - 1;
 727                 }
 728
 729                 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
 730
 731                 i += tx_bytes;
 732                 uport->icount.tx += tx_bytes;
 733                 remaining -= tx_bytes;
 734                 port->tx_remaining -= tx_bytes;
 735         }
 736
 737         xmit->tail = tail;
 738
 739         /*
 740          * The tx fifo watermark is level triggered and latched. Though we had
 741          * cleared it in qcom_geni_serial_isr it will have already reasserted
 742          * so we must clear it again here after our writes.
 743          */
 744         writel(M_TX_FIFO_WATERMARK_EN,
 745                         uport->membase + SE_GENI_M_IRQ_CLEAR);
 746
 747 out_write_wakeup:
 748         if (!port->tx_remaining) {
 749                 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 750                 if (irq_en & M_TX_FIFO_WATERMARK_EN)
 751                         writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
 752                                         uport->membase + SE_GENI_M_IRQ_EN);
 753         }
 754
 755         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 756                 uart_write_wakeup(uport);
 757 }
 758
 759 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
 760 {
 761         u32 m_irq_en;
 762         u32 m_irq_status;
 763         u32 s_irq_status;
 764         u32 geni_status;
 765         struct uart_port *uport = dev;
 766         unsigned long flags;
 767         bool drop_rx = false;
 768         struct tty_port *tport = &uport->state->port;
 769         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 770
 771         if (uport->suspended)
 772                 return IRQ_NONE;
 773
 774         spin_lock_irqsave(&uport->lock, flags);
 775         m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
 776         s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
 777         geni_status = readl(uport->membase + SE_GENI_STATUS);
 778         m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 779         writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
 780         writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 781
 782         if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
 783                 goto out_unlock;
 784
 785         if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
 786                 uport->icount.overrun++;
 787                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 788         }
 789
 790         if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
 791                 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
 792                                         geni_status & M_GENI_CMD_ACTIVE);
 793
 794         if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
 795                 if (s_irq_status & S_GP_IRQ_0_EN)
 796                         uport->icount.parity++;
 797                 drop_rx = true;
 798         } else if (s_irq_status & S_GP_IRQ_2_EN ||
 799                                         s_irq_status & S_GP_IRQ_3_EN) {
 800                 uport->icount.brk++;
 801                 port->brk = true;
 802         }
 803
 804         if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
 805                                         s_irq_status & S_RX_FIFO_LAST_EN)
 806                 qcom_geni_serial_handle_rx(uport, drop_rx);
 807
 808 out_unlock:
 809         uart_unlock_and_check_sysrq(uport, flags);
 810
 811         return IRQ_HANDLED;
 812 }
 813
 814 static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
 815 {
 816         struct uart_port *uport;
 817
 818         uport = &port->uport;
 819         port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
 820         port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
 821         port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
 822         uport->fifosize =
 823                 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
 824 }
 825
 826
 827 static void qcom_geni_serial_shutdown(struct uart_port *uport)
 828 {
 829         unsigned long flags;
 830
 831         /* Stop the console before stopping the current tx */
 832         if (uart_console(uport))
 833                 console_stop(uport->cons);
 834
 835         free_irq(uport->irq, uport);
 836         spin_lock_irqsave(&uport->lock, flags);
 837         qcom_geni_serial_stop_tx(uport);
 838         qcom_geni_serial_stop_rx(uport);
 839         spin_unlock_irqrestore(&uport->lock, flags);
 840 }
 841
 842 static int qcom_geni_serial_port_setup(struct uart_port *uport)
 843 {
 844         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 845         u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
 846         u32 proto;
 847
 848         if (uart_console(uport)) {
 849                 port->tx_bytes_pw = 1;
 850                 port->rx_bytes_pw = CONSOLE_RX_BYTES_PW;
 851         } else {
 852                 port->tx_bytes_pw = 4;
 853                 port->rx_bytes_pw = 4;
 854         }
 855
 856         proto = geni_se_read_proto(&port->se);
 857         if (proto != GENI_SE_UART) {
 858                 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
 859                 return -ENXIO;
 860         }
 861
 862         qcom_geni_serial_stop_rx(uport);
 863
 864         get_tx_fifo_size(port);
 865
 866         writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
 867         /*
 868          * Make an unconditional cancel on the main sequencer to reset
 869          * it else we could end up in data loss scenarios.
 870          */
 871         if (uart_console(uport))
 872                 qcom_geni_serial_poll_tx_done(uport);
 873         geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw,
 874                                                 false, true, false);
 875         geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw,
 876                                                 false, false, true);
 877         geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
 878         geni_se_select_mode(&port->se, GENI_SE_FIFO);
 879         if (!uart_console(uport)) {
 880                 port->rx_fifo = devm_kcalloc(uport->dev,
 881                         port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
 882                 if (!port->rx_fifo)
 883                         return -ENOMEM;
 884         }
 885         port->setup = true;
 886
 887         return 0;
 888 }
 889
 890 static int qcom_geni_serial_startup(struct uart_port *uport)
 891 {
 892         int ret;
 893         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 894
 895         scnprintf(port->name, sizeof(port->name),
 896                   "qcom_serial_%s%d",
 897                 (uart_console(uport) ? "console" : "uart"), uport->line);
 898
 899         if (!port->setup) {
 900                 ret = qcom_geni_serial_port_setup(uport);
 901                 if (ret)
 902                         return ret;
 903         }
 904
 905         ret = request_irq(uport->irq, qcom_geni_serial_isr, IRQF_TRIGGER_HIGH,
 906                                                         port->name, uport);
 907         if (ret)
 908                 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
 909         return ret;
 910 }
 911
 912 static unsigned long get_clk_cfg(unsigned long clk_freq)
 913 {
 914         int i;
 915
 916         for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
 917                 if (!(root_freq[i] % clk_freq))
 918                         return root_freq[i];
 919         }
 920         return 0;
 921 }
 922
 923 static unsigned long get_clk_div_rate(unsigned int baud, unsigned int *clk_div)
 924 {
 925         unsigned long ser_clk;
 926         unsigned long desired_clk;
 927
 928         desired_clk = baud * UART_OVERSAMPLING;
 929         ser_clk = get_clk_cfg(desired_clk);
 930         if (!ser_clk) {
 931                 pr_err("%s: Can't find matching DFS entry for baud %d\n",
 932                                                                 __func__, baud);
 933                 return ser_clk;
 934         }
 935
 936         *clk_div = ser_clk / desired_clk;
 937         return ser_clk;
 938 }
 939
 940 static void qcom_geni_serial_set_termios(struct uart_port *uport,
 941                                 struct ktermios *termios, struct ktermios *old)
 942 {
 943         unsigned int baud;
 944         u32 bits_per_char;
 945         u32 tx_trans_cfg;
 946         u32 tx_parity_cfg;
 947         u32 rx_trans_cfg;
 948         u32 rx_parity_cfg;
 949         u32 stop_bit_len;
 950         unsigned int clk_div;
 951         u32 ser_clk_cfg;
 952         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 953         unsigned long clk_rate;
 954
 955         qcom_geni_serial_stop_rx(uport);
 956         /* baud rate */
 957         baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
 958         port->baud = baud;
 959         clk_rate = get_clk_div_rate(baud, &clk_div);
 960         if (!clk_rate)
 961                 goto out_restart_rx;
 962
 963         uport->uartclk = clk_rate;
 964         clk_set_rate(port->se.clk, clk_rate);
 965         ser_clk_cfg = SER_CLK_EN;
 966         ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
 967
 968         /* parity */
 969         tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
 970         tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
 971         rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
 972         rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
 973         if (termios->c_cflag & PARENB) {
 974                 tx_trans_cfg |= UART_TX_PAR_EN;
 975                 rx_trans_cfg |= UART_RX_PAR_EN;
 976                 tx_parity_cfg |= PAR_CALC_EN;
 977                 rx_parity_cfg |= PAR_CALC_EN;
 978                 if (termios->c_cflag & PARODD) {
 979                         tx_parity_cfg |= PAR_ODD;
 980                         rx_parity_cfg |= PAR_ODD;
 981                 } else if (termios->c_cflag & CMSPAR) {
 982                         tx_parity_cfg |= PAR_SPACE;
 983                         rx_parity_cfg |= PAR_SPACE;
 984                 } else {
 985                         tx_parity_cfg |= PAR_EVEN;
 986                         rx_parity_cfg |= PAR_EVEN;
 987                 }
 988         } else {
 989                 tx_trans_cfg &= ~UART_TX_PAR_EN;
 990                 rx_trans_cfg &= ~UART_RX_PAR_EN;
 991                 tx_parity_cfg &= ~PAR_CALC_EN;
 992                 rx_parity_cfg &= ~PAR_CALC_EN;
 993         }
 994
 995         /* bits per char */
 996         switch (termios->c_cflag & CSIZE) {
 997         case CS5:
 998                 bits_per_char = 5;
 999                 break;
1000         case CS6:
1001                 bits_per_char = 6;
1002                 break;
1003         case CS7:
1004                 bits_per_char = 7;
1005                 break;
1006         case CS8:
1007         default:
1008                 bits_per_char = 8;
1009                 break;
1010         }
1011
1012         /* stop bits */
1013         if (termios->c_cflag & CSTOPB)
1014                 stop_bit_len = TX_STOP_BIT_LEN_2;
1015         else
1016                 stop_bit_len = TX_STOP_BIT_LEN_1;
1017
1018         /* flow control, clear the CTS_MASK bit if using flow control. */
1019         if (termios->c_cflag & CRTSCTS)
1020                 tx_trans_cfg &= ~UART_CTS_MASK;
1021         else
1022                 tx_trans_cfg |= UART_CTS_MASK;
1023
1024         if (baud)
1025                 uart_update_timeout(uport, termios->c_cflag, baud);
1026
1027         if (!uart_console(uport))
1028                 writel(port->loopback,
1029                                 uport->membase + SE_UART_LOOPBACK_CFG);
1030         writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1031         writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1032         writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1033         writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1034         writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1035         writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1036         writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1037         writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1038         writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1039 out_restart_rx:
1040         qcom_geni_serial_start_rx(uport);
1041 }
1042
1043 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1044 {
1045         return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1046 }
1047
1048 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
1049 static int __init qcom_geni_console_setup(struct console *co, char *options)
1050 {
1051         struct uart_port *uport;
1052         struct qcom_geni_serial_port *port;
1053         int baud = 9600;
1054         int bits = 8;
1055         int parity = 'n';
1056         int flow = 'n';
1057         int ret;
1058
1059         if (co->index >= GENI_UART_CONS_PORTS  || co->index < 0)
1060                 return -ENXIO;
1061
1062         port = get_port_from_line(co->index, true);
1063         if (IS_ERR(port)) {
1064                 pr_err("Invalid line %d\n", co->index);
1065                 return PTR_ERR(port);
1066         }
1067
1068         uport = &port->uport;
1069
1070         if (unlikely(!uport->membase))
1071                 return -ENXIO;
1072
1073         if (!port->setup) {
1074                 ret = qcom_geni_serial_port_setup(uport);
1075                 if (ret)
1076                         return ret;
1077         }
1078
1079         if (options)
1080                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1081
1082         return uart_set_options(uport, co, baud, parity, bits, flow);
1083 }
1084
1085 static void qcom_geni_serial_earlycon_write(struct console *con,
1086                                         const char *s, unsigned int n)
1087 {
1088         struct earlycon_device *dev = con->data;
1089
1090         __qcom_geni_serial_console_write(&dev->port, s, n);
1091 }
1092
1093 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1094                                                                 const char *opt)
1095 {
1096         struct uart_port *uport = &dev->port;
1097         u32 tx_trans_cfg;
1098         u32 tx_parity_cfg = 0;  /* Disable Tx Parity */
1099         u32 rx_trans_cfg = 0;
1100         u32 rx_parity_cfg = 0;  /* Disable Rx Parity */
1101         u32 stop_bit_len = 0;   /* Default stop bit length - 1 bit */
1102         u32 bits_per_char;
1103         struct geni_se se;
1104
1105         if (!uport->membase)
1106                 return -EINVAL;
1107
1108         memset(&se, 0, sizeof(se));
1109         se.base = uport->membase;
1110         if (geni_se_read_proto(&se) != GENI_SE_UART)
1111                 return -ENXIO;
1112         /*
1113          * Ignore Flow control.
1114          * n = 8.
1115          */
1116         tx_trans_cfg = UART_CTS_MASK;
1117         bits_per_char = BITS_PER_BYTE;
1118
1119         /*
1120          * Make an unconditional cancel on the main sequencer to reset
1121          * it else we could end up in data loss scenarios.
1122          */
1123         qcom_geni_serial_poll_tx_done(uport);
1124         qcom_geni_serial_abort_rx(uport);
1125         geni_se_config_packing(&se, BITS_PER_BYTE, 1, false, true, false);
1126         geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1127         geni_se_select_mode(&se, GENI_SE_FIFO);
1128
1129         writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1130         writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1131         writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1132         writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1133         writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1134         writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1135         writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1136
1137         dev->con->write = qcom_geni_serial_earlycon_write;
1138         dev->con->setup = NULL;
1139         return 0;
1140 }
1141 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1142                                 qcom_geni_serial_earlycon_setup);
1143
1144 static int __init console_register(struct uart_driver *drv)
1145 {
1146         return uart_register_driver(drv);
1147 }
1148
1149 static void console_unregister(struct uart_driver *drv)
1150 {
1151         uart_unregister_driver(drv);
1152 }
1153
1154 static struct console cons_ops = {
1155         .name = "ttyMSM",
1156         .write = qcom_geni_serial_console_write,
1157         .device = uart_console_device,
1158         .setup = qcom_geni_console_setup,
1159         .flags = CON_PRINTBUFFER,
1160         .index = -1,
1161         .data = &qcom_geni_console_driver,
1162 };
1163
1164 static struct uart_driver qcom_geni_console_driver = {
1165         .owner = THIS_MODULE,
1166         .driver_name = "qcom_geni_console",
1167         .dev_name = "ttyMSM",
1168         .nr =  GENI_UART_CONS_PORTS,
1169         .cons = &cons_ops,
1170 };
1171 #else
1172 static int console_register(struct uart_driver *drv)
1173 {
1174         return 0;
1175 }
1176
1177 static void console_unregister(struct uart_driver *drv)
1178 {
1179 }
1180 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1181
1182 static struct uart_driver qcom_geni_uart_driver = {
1183         .owner = THIS_MODULE,
1184         .driver_name = "qcom_geni_uart",
1185         .dev_name = "ttyHS",
1186         .nr =  GENI_UART_PORTS,
1187 };
1188
1189 static void qcom_geni_serial_pm(struct uart_port *uport,
1190                 unsigned int new_state, unsigned int old_state)
1191 {
1192         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1193
1194         /* If we've never been called, treat it as off */
1195         if (old_state == UART_PM_STATE_UNDEFINED)
1196                 old_state = UART_PM_STATE_OFF;
1197
1198         if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
1199                 geni_se_resources_on(&port->se);
1200         else if (new_state == UART_PM_STATE_OFF &&
1201                         old_state == UART_PM_STATE_ON)
1202                 geni_se_resources_off(&port->se);
1203 }
1204
1205 static const struct uart_ops qcom_geni_console_pops = {
1206         .tx_empty = qcom_geni_serial_tx_empty,
1207         .stop_tx = qcom_geni_serial_stop_tx,
1208         .start_tx = qcom_geni_serial_start_tx,
1209         .stop_rx = qcom_geni_serial_stop_rx,
1210         .set_termios = qcom_geni_serial_set_termios,
1211         .startup = qcom_geni_serial_startup,
1212         .request_port = qcom_geni_serial_request_port,
1213         .config_port = qcom_geni_serial_config_port,
1214         .shutdown = qcom_geni_serial_shutdown,
1215         .type = qcom_geni_serial_get_type,
1216         .set_mctrl = qcom_geni_serial_set_mctrl,
1217         .get_mctrl = qcom_geni_serial_get_mctrl,
1218 #ifdef CONFIG_CONSOLE_POLL
1219         .poll_get_char  = qcom_geni_serial_get_char,
1220         .poll_put_char  = qcom_geni_serial_poll_put_char,
1221 #endif
1222         .pm = qcom_geni_serial_pm,
1223 };
1224
1225 static const struct uart_ops qcom_geni_uart_pops = {
1226         .tx_empty = qcom_geni_serial_tx_empty,
1227         .stop_tx = qcom_geni_serial_stop_tx,
1228         .start_tx = qcom_geni_serial_start_tx,
1229         .stop_rx = qcom_geni_serial_stop_rx,
1230         .set_termios = qcom_geni_serial_set_termios,
1231         .startup = qcom_geni_serial_startup,
1232         .request_port = qcom_geni_serial_request_port,
1233         .config_port = qcom_geni_serial_config_port,
1234         .shutdown = qcom_geni_serial_shutdown,
1235         .type = qcom_geni_serial_get_type,
1236         .set_mctrl = qcom_geni_serial_set_mctrl,
1237         .get_mctrl = qcom_geni_serial_get_mctrl,
1238         .pm = qcom_geni_serial_pm,
1239 };
1240
1241 static int qcom_geni_serial_probe(struct platform_device *pdev)
1242 {
1243         int ret = 0;
1244         int line = -1;
1245         struct qcom_geni_serial_port *port;
1246         struct uart_port *uport;
1247         struct resource *res;
1248         int irq;
1249         bool console = false;
1250         struct uart_driver *drv;
1251
1252         if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1253                 console = true;
1254
1255         if (console) {
1256                 drv = &qcom_geni_console_driver;
1257                 line = of_alias_get_id(pdev->dev.of_node, "serial");
1258         } else {
1259                 drv = &qcom_geni_uart_driver;
1260                 line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1261         }
1262
1263         port = get_port_from_line(line, console);
1264         if (IS_ERR(port)) {
1265                 dev_err(&pdev->dev, "Invalid line %d\n", line);
1266                 return PTR_ERR(port);
1267         }
1268
1269         uport = &port->uport;
1270         /* Don't allow 2 drivers to access the same port */
1271         if (uport->private_data)
1272                 return -ENODEV;
1273
1274         uport->dev = &pdev->dev;
1275         port->se.dev = &pdev->dev;
1276         port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1277         port->se.clk = devm_clk_get(&pdev->dev, "se");
1278         if (IS_ERR(port->se.clk)) {
1279                 ret = PTR_ERR(port->se.clk);
1280                 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1281                 return ret;
1282         }
1283
1284         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1285         if (!res)
1286                 return -EINVAL;
1287         uport->mapbase = res->start;
1288
1289         port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1290         port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1291         port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1292
1293         irq = platform_get_irq(pdev, 0);
1294         if (irq < 0) {
1295                 dev_err(&pdev->dev, "Failed to get IRQ %d\n", irq);
1296                 return irq;
1297         }
1298         uport->irq = irq;
1299
1300         uport->private_data = drv;
1301         platform_set_drvdata(pdev, port);
1302         port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1303         if (!console)
1304                 device_create_file(uport->dev, &dev_attr_loopback);
1305         return uart_add_one_port(drv, uport);
1306 }
1307
1308 static int qcom_geni_serial_remove(struct platform_device *pdev)
1309 {
1310         struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1311         struct uart_driver *drv = port->uport.private_data;
1312
1313         uart_remove_one_port(drv, &port->uport);
1314         return 0;
1315 }
1316
1317 static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
1318 {
1319         struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1320         struct uart_port *uport = &port->uport;
1321
1322         return uart_suspend_port(uport->private_data, uport);
1323 }
1324
1325 static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
1326 {
1327         struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1328         struct uart_port *uport = &port->uport;
1329
1330         return uart_resume_port(uport->private_data, uport);
1331 }
1332
1333 static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1334         SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend,
1335                                         qcom_geni_serial_sys_resume)
1336 };
1337
1338 static const struct of_device_id qcom_geni_serial_match_table[] = {
1339         { .compatible = "qcom,geni-debug-uart", },
1340         { .compatible = "qcom,geni-uart", },
1341         {}
1342 };
1343 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1344
1345 static struct platform_driver qcom_geni_serial_platform_driver = {
1346         .remove = qcom_geni_serial_remove,
1347         .probe = qcom_geni_serial_probe,
1348         .driver = {
1349                 .name = "qcom_geni_serial",
1350                 .of_match_table = qcom_geni_serial_match_table,
1351                 .pm = &qcom_geni_serial_pm_ops,
1352         },
1353 };
1354
1355 static int __init qcom_geni_serial_init(void)
1356 {
1357         int ret;
1358
1359         ret = console_register(&qcom_geni_console_driver);
1360         if (ret)
1361                 return ret;
1362
1363         ret = uart_register_driver(&qcom_geni_uart_driver);
1364         if (ret) {
1365                 console_unregister(&qcom_geni_console_driver);
1366                 return ret;
1367         }
1368
1369         ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1370         if (ret) {
1371                 console_unregister(&qcom_geni_console_driver);
1372                 uart_unregister_driver(&qcom_geni_uart_driver);
1373         }
1374         return ret;
1375 }
1376 module_init(qcom_geni_serial_init);
1377
1378 static void __exit qcom_geni_serial_exit(void)
1379 {
1380         platform_driver_unregister(&qcom_geni_serial_platform_driver);
1381         console_unregister(&qcom_geni_console_driver);
1382         uart_unregister_driver(&qcom_geni_uart_driver);
1383 }
1384 module_exit(qcom_geni_serial_exit);
1385
1386 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1387 MODULE_LICENSE("GPL v2");