2 * Driver core for Samsung SoC onboard UARTs.
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 /* Hote on 2410 error handling
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/slab.h>
34 #include <linux/module.h>
35 #include <linux/ioport.h>
37 #include <linux/platform_device.h>
38 #include <linux/init.h>
39 #include <linux/sysrq.h>
40 #include <linux/console.h>
41 #include <linux/tty.h>
42 #include <linux/tty_flip.h>
43 #include <linux/serial_core.h>
44 #include <linux/serial.h>
45 #include <linux/serial_s3c.h>
46 #include <linux/delay.h>
47 #include <linux/clk.h>
48 #include <linux/cpufreq.h>
55 #if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
58 extern void printascii(const char *);
61 static void dbg(const char *fmt
, ...)
67 vscnprintf(buff
, sizeof(buff
), fmt
, va
);
74 #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
77 /* UART name and device definitions */
79 #define S3C24XX_SERIAL_NAME "ttySAC"
80 #define S3C24XX_SERIAL_MAJOR 204
81 #define S3C24XX_SERIAL_MINOR 64
83 #define S3C24XX_TX_PIO 1
84 #define S3C24XX_TX_DMA 2
85 #define S3C24XX_RX_PIO 1
86 #define S3C24XX_RX_DMA 2
87 /* macros to change one thing to another */
89 #define tx_enabled(port) ((port)->unused[0])
90 #define rx_enabled(port) ((port)->unused[1])
92 /* flag to ignore all characters coming in */
93 #define RXSTAT_DUMMY_READ (0x10000000)
95 static inline struct s3c24xx_uart_port
*to_ourport(struct uart_port
*port
)
97 return container_of(port
, struct s3c24xx_uart_port
, port
);
100 /* translate a port to the device name */
102 static inline const char *s3c24xx_serial_portname(struct uart_port
*port
)
104 return to_platform_device(port
->dev
)->name
;
107 static int s3c24xx_serial_txempty_nofifo(struct uart_port
*port
)
109 return rd_regl(port
, S3C2410_UTRSTAT
) & S3C2410_UTRSTAT_TXE
;
113 * s3c64xx and later SoC's include the interrupt mask and status registers in
114 * the controller itself, unlike the s3c24xx SoC's which have these registers
115 * in the interrupt controller. Check if the port type is s3c64xx or higher.
117 static int s3c24xx_serial_has_interrupt_mask(struct uart_port
*port
)
119 return to_ourport(port
)->info
->type
== PORT_S3C6400
;
122 static void s3c24xx_serial_rx_enable(struct uart_port
*port
)
125 unsigned int ucon
, ufcon
;
128 spin_lock_irqsave(&port
->lock
, flags
);
130 while (--count
&& !s3c24xx_serial_txempty_nofifo(port
))
133 ufcon
= rd_regl(port
, S3C2410_UFCON
);
134 ufcon
|= S3C2410_UFCON_RESETRX
;
135 wr_regl(port
, S3C2410_UFCON
, ufcon
);
137 ucon
= rd_regl(port
, S3C2410_UCON
);
138 ucon
|= S3C2410_UCON_RXIRQMODE
;
139 wr_regl(port
, S3C2410_UCON
, ucon
);
141 rx_enabled(port
) = 1;
142 spin_unlock_irqrestore(&port
->lock
, flags
);
145 static void s3c24xx_serial_rx_disable(struct uart_port
*port
)
150 spin_lock_irqsave(&port
->lock
, flags
);
152 ucon
= rd_regl(port
, S3C2410_UCON
);
153 ucon
&= ~S3C2410_UCON_RXIRQMODE
;
154 wr_regl(port
, S3C2410_UCON
, ucon
);
156 rx_enabled(port
) = 0;
157 spin_unlock_irqrestore(&port
->lock
, flags
);
160 static void s3c24xx_serial_stop_tx(struct uart_port
*port
)
162 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
163 struct s3c24xx_uart_dma
*dma
= ourport
->dma
;
164 struct circ_buf
*xmit
= &port
->state
->xmit
;
165 struct dma_tx_state state
;
168 if (!tx_enabled(port
))
171 if (s3c24xx_serial_has_interrupt_mask(port
))
172 __set_bit(S3C64XX_UINTM_TXD
,
173 portaddrl(port
, S3C64XX_UINTM
));
175 disable_irq_nosync(ourport
->tx_irq
);
177 if (dma
&& dma
->tx_chan
&& ourport
->tx_in_progress
== S3C24XX_TX_DMA
) {
178 dmaengine_pause(dma
->tx_chan
);
179 dmaengine_tx_status(dma
->tx_chan
, dma
->tx_cookie
, &state
);
180 dmaengine_terminate_all(dma
->tx_chan
);
181 dma_sync_single_for_cpu(ourport
->port
.dev
,
182 dma
->tx_transfer_addr
, dma
->tx_size
, DMA_TO_DEVICE
);
183 async_tx_ack(dma
->tx_desc
);
184 count
= dma
->tx_bytes_requested
- state
.residue
;
185 xmit
->tail
= (xmit
->tail
+ count
) & (UART_XMIT_SIZE
- 1);
186 port
->icount
.tx
+= count
;
189 tx_enabled(port
) = 0;
190 ourport
->tx_in_progress
= 0;
192 if (port
->flags
& UPF_CONS_FLOW
)
193 s3c24xx_serial_rx_enable(port
);
195 ourport
->tx_mode
= 0;
198 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port
*ourport
);
200 static void s3c24xx_serial_tx_dma_complete(void *args
)
202 struct s3c24xx_uart_port
*ourport
= args
;
203 struct uart_port
*port
= &ourport
->port
;
204 struct circ_buf
*xmit
= &port
->state
->xmit
;
205 struct s3c24xx_uart_dma
*dma
= ourport
->dma
;
206 struct dma_tx_state state
;
211 dmaengine_tx_status(dma
->tx_chan
, dma
->tx_cookie
, &state
);
212 count
= dma
->tx_bytes_requested
- state
.residue
;
213 async_tx_ack(dma
->tx_desc
);
215 dma_sync_single_for_cpu(ourport
->port
.dev
, dma
->tx_transfer_addr
,
216 dma
->tx_size
, DMA_TO_DEVICE
);
218 spin_lock_irqsave(&port
->lock
, flags
);
220 xmit
->tail
= (xmit
->tail
+ count
) & (UART_XMIT_SIZE
- 1);
221 port
->icount
.tx
+= count
;
222 ourport
->tx_in_progress
= 0;
224 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
225 uart_write_wakeup(port
);
227 s3c24xx_serial_start_next_tx(ourport
);
228 spin_unlock_irqrestore(&port
->lock
, flags
);
231 static void enable_tx_dma(struct s3c24xx_uart_port
*ourport
)
233 struct uart_port
*port
= &ourport
->port
;
236 /* Mask Tx interrupt */
237 if (s3c24xx_serial_has_interrupt_mask(port
))
238 __set_bit(S3C64XX_UINTM_TXD
,
239 portaddrl(port
, S3C64XX_UINTM
));
241 disable_irq_nosync(ourport
->tx_irq
);
243 /* Enable tx dma mode */
244 ucon
= rd_regl(port
, S3C2410_UCON
);
245 ucon
&= ~(S3C64XX_UCON_TXBURST_MASK
| S3C64XX_UCON_TXMODE_MASK
);
246 ucon
|= (dma_get_cache_alignment() >= 16) ?
247 S3C64XX_UCON_TXBURST_16
: S3C64XX_UCON_TXBURST_1
;
248 ucon
|= S3C64XX_UCON_TXMODE_DMA
;
249 wr_regl(port
, S3C2410_UCON
, ucon
);
251 ourport
->tx_mode
= S3C24XX_TX_DMA
;
254 static void enable_tx_pio(struct s3c24xx_uart_port
*ourport
)
256 struct uart_port
*port
= &ourport
->port
;
259 /* Set ufcon txtrig */
260 ourport
->tx_in_progress
= S3C24XX_TX_PIO
;
261 ufcon
= rd_regl(port
, S3C2410_UFCON
);
262 wr_regl(port
, S3C2410_UFCON
, ufcon
);
264 /* Enable tx pio mode */
265 ucon
= rd_regl(port
, S3C2410_UCON
);
266 ucon
&= ~(S3C64XX_UCON_TXMODE_MASK
);
267 ucon
|= S3C64XX_UCON_TXMODE_CPU
;
268 wr_regl(port
, S3C2410_UCON
, ucon
);
270 /* Unmask Tx interrupt */
271 if (s3c24xx_serial_has_interrupt_mask(port
))
272 __clear_bit(S3C64XX_UINTM_TXD
,
273 portaddrl(port
, S3C64XX_UINTM
));
275 enable_irq(ourport
->tx_irq
);
277 ourport
->tx_mode
= S3C24XX_TX_PIO
;
280 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port
*ourport
)
282 if (ourport
->tx_mode
!= S3C24XX_TX_PIO
)
283 enable_tx_pio(ourport
);
286 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port
*ourport
,
289 struct uart_port
*port
= &ourport
->port
;
290 struct circ_buf
*xmit
= &port
->state
->xmit
;
291 struct s3c24xx_uart_dma
*dma
= ourport
->dma
;
294 if (ourport
->tx_mode
!= S3C24XX_TX_DMA
)
295 enable_tx_dma(ourport
);
297 dma
->tx_size
= count
& ~(dma_get_cache_alignment() - 1);
298 dma
->tx_transfer_addr
= dma
->tx_addr
+ xmit
->tail
;
300 dma_sync_single_for_device(ourport
->port
.dev
, dma
->tx_transfer_addr
,
301 dma
->tx_size
, DMA_TO_DEVICE
);
303 dma
->tx_desc
= dmaengine_prep_slave_single(dma
->tx_chan
,
304 dma
->tx_transfer_addr
, dma
->tx_size
,
305 DMA_MEM_TO_DEV
, DMA_PREP_INTERRUPT
);
307 dev_err(ourport
->port
.dev
, "Unable to get desc for Tx\n");
311 dma
->tx_desc
->callback
= s3c24xx_serial_tx_dma_complete
;
312 dma
->tx_desc
->callback_param
= ourport
;
313 dma
->tx_bytes_requested
= dma
->tx_size
;
315 ourport
->tx_in_progress
= S3C24XX_TX_DMA
;
316 dma
->tx_cookie
= dmaengine_submit(dma
->tx_desc
);
317 dma_async_issue_pending(dma
->tx_chan
);
321 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port
*ourport
)
323 struct uart_port
*port
= &ourport
->port
;
324 struct circ_buf
*xmit
= &port
->state
->xmit
;
327 /* Get data size up to the end of buffer */
328 count
= CIRC_CNT_TO_END(xmit
->head
, xmit
->tail
, UART_XMIT_SIZE
);
331 s3c24xx_serial_stop_tx(port
);
335 if (!ourport
->dma
|| !ourport
->dma
->tx_chan
||
336 count
< ourport
->min_dma_size
||
337 xmit
->tail
& (dma_get_cache_alignment() - 1))
338 s3c24xx_serial_start_tx_pio(ourport
);
340 s3c24xx_serial_start_tx_dma(ourport
, count
);
343 static void s3c24xx_serial_start_tx(struct uart_port
*port
)
345 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
346 struct circ_buf
*xmit
= &port
->state
->xmit
;
348 if (!tx_enabled(port
)) {
349 if (port
->flags
& UPF_CONS_FLOW
)
350 s3c24xx_serial_rx_disable(port
);
352 tx_enabled(port
) = 1;
353 if (!ourport
->dma
|| !ourport
->dma
->tx_chan
)
354 s3c24xx_serial_start_tx_pio(ourport
);
357 if (ourport
->dma
&& ourport
->dma
->tx_chan
) {
358 if (!uart_circ_empty(xmit
) && !ourport
->tx_in_progress
)
359 s3c24xx_serial_start_next_tx(ourport
);
363 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port
*ourport
,
364 struct tty_port
*tty
, int count
)
366 struct s3c24xx_uart_dma
*dma
= ourport
->dma
;
372 dma_sync_single_for_cpu(ourport
->port
.dev
, dma
->rx_addr
,
373 dma
->rx_size
, DMA_FROM_DEVICE
);
375 ourport
->port
.icount
.rx
+= count
;
377 dev_err(ourport
->port
.dev
, "No tty port\n");
380 copied
= tty_insert_flip_string(tty
,
381 ((unsigned char *)(ourport
->dma
->rx_buf
)), count
);
382 if (copied
!= count
) {
384 dev_err(ourport
->port
.dev
, "RxData copy to tty layer failed\n");
388 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port
*ourport
,
389 unsigned long ufstat
);
391 static void uart_rx_drain_fifo(struct s3c24xx_uart_port
*ourport
)
393 struct uart_port
*port
= &ourport
->port
;
394 struct tty_port
*tty
= &port
->state
->port
;
395 unsigned int ch
, ufstat
;
398 ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
399 count
= s3c24xx_serial_rx_fifocnt(ourport
, ufstat
);
404 while (count
-- > 0) {
405 ch
= rd_regb(port
, S3C2410_URXH
);
407 ourport
->port
.icount
.rx
++;
408 tty_insert_flip_char(tty
, ch
, TTY_NORMAL
);
411 tty_flip_buffer_push(tty
);
414 static void s3c24xx_serial_stop_rx(struct uart_port
*port
)
416 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
417 struct s3c24xx_uart_dma
*dma
= ourport
->dma
;
418 struct tty_port
*t
= &port
->state
->port
;
419 struct dma_tx_state state
;
420 enum dma_status dma_status
;
421 unsigned int received
;
423 if (rx_enabled(port
)) {
424 dbg("s3c24xx_serial_stop_rx: port=%p\n", port
);
425 if (s3c24xx_serial_has_interrupt_mask(port
))
426 __set_bit(S3C64XX_UINTM_RXD
,
427 portaddrl(port
, S3C64XX_UINTM
));
429 disable_irq_nosync(ourport
->rx_irq
);
430 rx_enabled(port
) = 0;
432 if (dma
&& dma
->rx_chan
) {
433 dmaengine_pause(dma
->tx_chan
);
434 dma_status
= dmaengine_tx_status(dma
->rx_chan
,
435 dma
->rx_cookie
, &state
);
436 if (dma_status
== DMA_IN_PROGRESS
||
437 dma_status
== DMA_PAUSED
) {
438 received
= dma
->rx_bytes_requested
- state
.residue
;
439 dmaengine_terminate_all(dma
->rx_chan
);
440 s3c24xx_uart_copy_rx_to_tty(ourport
, t
, received
);
445 static inline struct s3c24xx_uart_info
446 *s3c24xx_port_to_info(struct uart_port
*port
)
448 return to_ourport(port
)->info
;
451 static inline struct s3c2410_uartcfg
452 *s3c24xx_port_to_cfg(struct uart_port
*port
)
454 struct s3c24xx_uart_port
*ourport
;
456 if (port
->dev
== NULL
)
459 ourport
= container_of(port
, struct s3c24xx_uart_port
, port
);
463 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port
*ourport
,
464 unsigned long ufstat
)
466 struct s3c24xx_uart_info
*info
= ourport
->info
;
468 if (ufstat
& info
->rx_fifofull
)
469 return ourport
->port
.fifosize
;
471 return (ufstat
& info
->rx_fifomask
) >> info
->rx_fifoshift
;
474 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port
*ourport
);
475 static void s3c24xx_serial_rx_dma_complete(void *args
)
477 struct s3c24xx_uart_port
*ourport
= args
;
478 struct uart_port
*port
= &ourport
->port
;
480 struct s3c24xx_uart_dma
*dma
= ourport
->dma
;
481 struct tty_port
*t
= &port
->state
->port
;
482 struct tty_struct
*tty
= tty_port_tty_get(&ourport
->port
.state
->port
);
484 struct dma_tx_state state
;
488 dmaengine_tx_status(dma
->rx_chan
, dma
->rx_cookie
, &state
);
489 received
= dma
->rx_bytes_requested
- state
.residue
;
490 async_tx_ack(dma
->rx_desc
);
492 spin_lock_irqsave(&port
->lock
, flags
);
495 s3c24xx_uart_copy_rx_to_tty(ourport
, t
, received
);
498 tty_flip_buffer_push(t
);
502 s3c64xx_start_rx_dma(ourport
);
504 spin_unlock_irqrestore(&port
->lock
, flags
);
507 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port
*ourport
)
509 struct s3c24xx_uart_dma
*dma
= ourport
->dma
;
511 dma_sync_single_for_device(ourport
->port
.dev
, dma
->rx_addr
,
512 dma
->rx_size
, DMA_FROM_DEVICE
);
514 dma
->rx_desc
= dmaengine_prep_slave_single(dma
->rx_chan
,
515 dma
->rx_addr
, dma
->rx_size
, DMA_DEV_TO_MEM
,
518 dev_err(ourport
->port
.dev
, "Unable to get desc for Rx\n");
522 dma
->rx_desc
->callback
= s3c24xx_serial_rx_dma_complete
;
523 dma
->rx_desc
->callback_param
= ourport
;
524 dma
->rx_bytes_requested
= dma
->rx_size
;
526 dma
->rx_cookie
= dmaengine_submit(dma
->rx_desc
);
527 dma_async_issue_pending(dma
->rx_chan
);
530 /* ? - where has parity gone?? */
531 #define S3C2410_UERSTAT_PARITY (0x1000)
533 static void enable_rx_dma(struct s3c24xx_uart_port
*ourport
)
535 struct uart_port
*port
= &ourport
->port
;
538 /* set Rx mode to DMA mode */
539 ucon
= rd_regl(port
, S3C2410_UCON
);
540 ucon
&= ~(S3C64XX_UCON_RXBURST_MASK
|
541 S3C64XX_UCON_TIMEOUT_MASK
|
542 S3C64XX_UCON_EMPTYINT_EN
|
543 S3C64XX_UCON_DMASUS_EN
|
544 S3C64XX_UCON_TIMEOUT_EN
|
545 S3C64XX_UCON_RXMODE_MASK
);
546 ucon
|= S3C64XX_UCON_RXBURST_16
|
547 0xf << S3C64XX_UCON_TIMEOUT_SHIFT
|
548 S3C64XX_UCON_EMPTYINT_EN
|
549 S3C64XX_UCON_TIMEOUT_EN
|
550 S3C64XX_UCON_RXMODE_DMA
;
551 wr_regl(port
, S3C2410_UCON
, ucon
);
553 ourport
->rx_mode
= S3C24XX_RX_DMA
;
556 static void enable_rx_pio(struct s3c24xx_uart_port
*ourport
)
558 struct uart_port
*port
= &ourport
->port
;
561 /* set Rx mode to DMA mode */
562 ucon
= rd_regl(port
, S3C2410_UCON
);
563 ucon
&= ~(S3C64XX_UCON_TIMEOUT_MASK
|
564 S3C64XX_UCON_EMPTYINT_EN
|
565 S3C64XX_UCON_DMASUS_EN
|
566 S3C64XX_UCON_TIMEOUT_EN
|
567 S3C64XX_UCON_RXMODE_MASK
);
568 ucon
|= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT
|
569 S3C64XX_UCON_TIMEOUT_EN
|
570 S3C64XX_UCON_RXMODE_CPU
;
571 wr_regl(port
, S3C2410_UCON
, ucon
);
573 ourport
->rx_mode
= S3C24XX_RX_PIO
;
576 static irqreturn_t
s3c24xx_serial_rx_chars_dma(int irq
, void *dev_id
)
578 unsigned int utrstat
, ufstat
, received
;
579 struct s3c24xx_uart_port
*ourport
= dev_id
;
580 struct uart_port
*port
= &ourport
->port
;
581 struct s3c24xx_uart_dma
*dma
= ourport
->dma
;
582 struct tty_struct
*tty
= tty_port_tty_get(&ourport
->port
.state
->port
);
583 struct tty_port
*t
= &port
->state
->port
;
585 struct dma_tx_state state
;
587 utrstat
= rd_regl(port
, S3C2410_UTRSTAT
);
588 ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
590 spin_lock_irqsave(&port
->lock
, flags
);
592 if (!(utrstat
& S3C2410_UTRSTAT_TIMEOUT
)) {
593 s3c64xx_start_rx_dma(ourport
);
594 if (ourport
->rx_mode
== S3C24XX_RX_PIO
)
595 enable_rx_dma(ourport
);
599 if (ourport
->rx_mode
== S3C24XX_RX_DMA
) {
600 dmaengine_pause(dma
->rx_chan
);
601 dmaengine_tx_status(dma
->rx_chan
, dma
->rx_cookie
, &state
);
602 dmaengine_terminate_all(dma
->rx_chan
);
603 received
= dma
->rx_bytes_requested
- state
.residue
;
604 s3c24xx_uart_copy_rx_to_tty(ourport
, t
, received
);
606 enable_rx_pio(ourport
);
609 uart_rx_drain_fifo(ourport
);
612 tty_flip_buffer_push(t
);
616 wr_regl(port
, S3C2410_UTRSTAT
, S3C2410_UTRSTAT_TIMEOUT
);
619 spin_unlock_irqrestore(&port
->lock
, flags
);
624 static irqreturn_t
s3c24xx_serial_rx_chars_pio(int irq
, void *dev_id
)
626 struct s3c24xx_uart_port
*ourport
= dev_id
;
627 struct uart_port
*port
= &ourport
->port
;
628 unsigned int ufcon
, ch
, flag
, ufstat
, uerstat
;
630 int max_count
= port
->fifosize
;
632 spin_lock_irqsave(&port
->lock
, flags
);
634 while (max_count
-- > 0) {
635 ufcon
= rd_regl(port
, S3C2410_UFCON
);
636 ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
638 if (s3c24xx_serial_rx_fifocnt(ourport
, ufstat
) == 0)
641 uerstat
= rd_regl(port
, S3C2410_UERSTAT
);
642 ch
= rd_regb(port
, S3C2410_URXH
);
644 if (port
->flags
& UPF_CONS_FLOW
) {
645 int txe
= s3c24xx_serial_txempty_nofifo(port
);
647 if (rx_enabled(port
)) {
649 rx_enabled(port
) = 0;
654 ufcon
|= S3C2410_UFCON_RESETRX
;
655 wr_regl(port
, S3C2410_UFCON
, ufcon
);
656 rx_enabled(port
) = 1;
657 spin_unlock_irqrestore(&port
->lock
,
665 /* insert the character into the buffer */
670 if (unlikely(uerstat
& S3C2410_UERSTAT_ANY
)) {
671 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
674 /* check for break */
675 if (uerstat
& S3C2410_UERSTAT_BREAK
) {
678 if (uart_handle_break(port
))
682 if (uerstat
& S3C2410_UERSTAT_FRAME
)
683 port
->icount
.frame
++;
684 if (uerstat
& S3C2410_UERSTAT_OVERRUN
)
685 port
->icount
.overrun
++;
687 uerstat
&= port
->read_status_mask
;
689 if (uerstat
& S3C2410_UERSTAT_BREAK
)
691 else if (uerstat
& S3C2410_UERSTAT_PARITY
)
693 else if (uerstat
& (S3C2410_UERSTAT_FRAME
|
694 S3C2410_UERSTAT_OVERRUN
))
698 if (uart_handle_sysrq_char(port
, ch
))
701 uart_insert_char(port
, uerstat
, S3C2410_UERSTAT_OVERRUN
,
708 spin_unlock_irqrestore(&port
->lock
, flags
);
709 tty_flip_buffer_push(&port
->state
->port
);
716 static irqreturn_t
s3c24xx_serial_rx_chars(int irq
, void *dev_id
)
718 struct s3c24xx_uart_port
*ourport
= dev_id
;
720 if (ourport
->dma
&& ourport
->dma
->rx_chan
)
721 return s3c24xx_serial_rx_chars_dma(irq
, dev_id
);
722 return s3c24xx_serial_rx_chars_pio(irq
, dev_id
);
725 static irqreturn_t
s3c24xx_serial_tx_chars(int irq
, void *id
)
727 struct s3c24xx_uart_port
*ourport
= id
;
728 struct uart_port
*port
= &ourport
->port
;
729 struct circ_buf
*xmit
= &port
->state
->xmit
;
731 int count
, dma_count
= 0;
733 spin_lock_irqsave(&port
->lock
, flags
);
735 count
= CIRC_CNT_TO_END(xmit
->head
, xmit
->tail
, UART_XMIT_SIZE
);
737 if (ourport
->dma
&& ourport
->dma
->tx_chan
&&
738 count
>= ourport
->min_dma_size
) {
739 int align
= dma_get_cache_alignment() -
740 (xmit
->tail
& (dma_get_cache_alignment() - 1));
741 if (count
-align
>= ourport
->min_dma_size
) {
742 dma_count
= count
-align
;
748 wr_regb(port
, S3C2410_UTXH
, port
->x_char
);
754 /* if there isn't anything more to transmit, or the uart is now
755 * stopped, disable the uart and exit
758 if (uart_circ_empty(xmit
) || uart_tx_stopped(port
)) {
759 s3c24xx_serial_stop_tx(port
);
763 /* try and drain the buffer... */
765 if (count
> port
->fifosize
) {
766 count
= port
->fifosize
;
770 while (!uart_circ_empty(xmit
) && count
> 0) {
771 if (rd_regl(port
, S3C2410_UFSTAT
) & ourport
->info
->tx_fifofull
)
774 wr_regb(port
, S3C2410_UTXH
, xmit
->buf
[xmit
->tail
]);
775 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
780 if (!count
&& dma_count
) {
781 s3c24xx_serial_start_tx_dma(ourport
, dma_count
);
785 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
) {
786 spin_unlock(&port
->lock
);
787 uart_write_wakeup(port
);
788 spin_lock(&port
->lock
);
791 if (uart_circ_empty(xmit
))
792 s3c24xx_serial_stop_tx(port
);
795 spin_unlock_irqrestore(&port
->lock
, flags
);
799 /* interrupt handler for s3c64xx and later SoC's.*/
800 static irqreturn_t
s3c64xx_serial_handle_irq(int irq
, void *id
)
802 struct s3c24xx_uart_port
*ourport
= id
;
803 struct uart_port
*port
= &ourport
->port
;
804 unsigned int pend
= rd_regl(port
, S3C64XX_UINTP
);
805 irqreturn_t ret
= IRQ_HANDLED
;
807 if (pend
& S3C64XX_UINTM_RXD_MSK
) {
808 ret
= s3c24xx_serial_rx_chars(irq
, id
);
809 wr_regl(port
, S3C64XX_UINTP
, S3C64XX_UINTM_RXD_MSK
);
811 if (pend
& S3C64XX_UINTM_TXD_MSK
) {
812 ret
= s3c24xx_serial_tx_chars(irq
, id
);
813 wr_regl(port
, S3C64XX_UINTP
, S3C64XX_UINTM_TXD_MSK
);
818 static unsigned int s3c24xx_serial_tx_empty(struct uart_port
*port
)
820 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
821 unsigned long ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
822 unsigned long ufcon
= rd_regl(port
, S3C2410_UFCON
);
824 if (ufcon
& S3C2410_UFCON_FIFOMODE
) {
825 if ((ufstat
& info
->tx_fifomask
) != 0 ||
826 (ufstat
& info
->tx_fifofull
))
832 return s3c24xx_serial_txempty_nofifo(port
);
835 /* no modem control lines */
836 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port
*port
)
838 unsigned int umstat
= rd_regb(port
, S3C2410_UMSTAT
);
840 if (umstat
& S3C2410_UMSTAT_CTS
)
841 return TIOCM_CAR
| TIOCM_DSR
| TIOCM_CTS
;
843 return TIOCM_CAR
| TIOCM_DSR
;
846 static void s3c24xx_serial_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
848 unsigned int umcon
= rd_regl(port
, S3C2410_UMCON
);
850 if (mctrl
& TIOCM_RTS
)
851 umcon
|= S3C2410_UMCOM_RTS_LOW
;
853 umcon
&= ~S3C2410_UMCOM_RTS_LOW
;
855 wr_regl(port
, S3C2410_UMCON
, umcon
);
858 static void s3c24xx_serial_break_ctl(struct uart_port
*port
, int break_state
)
863 spin_lock_irqsave(&port
->lock
, flags
);
865 ucon
= rd_regl(port
, S3C2410_UCON
);
868 ucon
|= S3C2410_UCON_SBREAK
;
870 ucon
&= ~S3C2410_UCON_SBREAK
;
872 wr_regl(port
, S3C2410_UCON
, ucon
);
874 spin_unlock_irqrestore(&port
->lock
, flags
);
877 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port
*p
)
879 struct s3c24xx_uart_dma
*dma
= p
->dma
;
883 /* Default slave configuration parameters */
884 dma
->rx_conf
.direction
= DMA_DEV_TO_MEM
;
885 dma
->rx_conf
.src_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
886 dma
->rx_conf
.src_addr
= p
->port
.mapbase
+ S3C2410_URXH
;
887 dma
->rx_conf
.src_maxburst
= 16;
889 dma
->tx_conf
.direction
= DMA_MEM_TO_DEV
;
890 dma
->tx_conf
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
891 dma
->tx_conf
.dst_addr
= p
->port
.mapbase
+ S3C2410_UTXH
;
892 if (dma_get_cache_alignment() >= 16)
893 dma
->tx_conf
.dst_maxburst
= 16;
895 dma
->tx_conf
.dst_maxburst
= 1;
898 dma_cap_set(DMA_SLAVE
, mask
);
900 dma
->rx_chan
= dma_request_slave_channel_compat(mask
, dma
->fn
,
901 dma
->rx_param
, p
->port
.dev
, "rx");
905 dmaengine_slave_config(dma
->rx_chan
, &dma
->rx_conf
);
907 dma
->tx_chan
= dma_request_slave_channel_compat(mask
, dma
->fn
,
908 dma
->tx_param
, p
->port
.dev
, "tx");
910 dma_release_channel(dma
->rx_chan
);
914 dmaengine_slave_config(dma
->tx_chan
, &dma
->tx_conf
);
917 dma
->rx_size
= PAGE_SIZE
;
919 dma
->rx_buf
= kmalloc(dma
->rx_size
, GFP_KERNEL
);
922 dma_release_channel(dma
->rx_chan
);
923 dma_release_channel(dma
->tx_chan
);
927 dma
->rx_addr
= dma_map_single(dma
->rx_chan
->device
->dev
, dma
->rx_buf
,
928 dma
->rx_size
, DMA_FROM_DEVICE
);
930 spin_lock_irqsave(&p
->port
.lock
, flags
);
933 dma
->tx_addr
= dma_map_single(dma
->tx_chan
->device
->dev
,
934 p
->port
.state
->xmit
.buf
,
935 UART_XMIT_SIZE
, DMA_TO_DEVICE
);
937 spin_unlock_irqrestore(&p
->port
.lock
, flags
);
942 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port
*p
)
944 struct s3c24xx_uart_dma
*dma
= p
->dma
;
947 dmaengine_terminate_all(dma
->rx_chan
);
948 dma_unmap_single(dma
->rx_chan
->device
->dev
, dma
->rx_addr
,
949 dma
->rx_size
, DMA_FROM_DEVICE
);
951 dma_release_channel(dma
->rx_chan
);
956 dmaengine_terminate_all(dma
->tx_chan
);
957 dma_unmap_single(dma
->tx_chan
->device
->dev
, dma
->tx_addr
,
958 UART_XMIT_SIZE
, DMA_TO_DEVICE
);
959 dma_release_channel(dma
->tx_chan
);
964 static void s3c24xx_serial_shutdown(struct uart_port
*port
)
966 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
968 if (ourport
->tx_claimed
) {
969 if (!s3c24xx_serial_has_interrupt_mask(port
))
970 free_irq(ourport
->tx_irq
, ourport
);
971 tx_enabled(port
) = 0;
972 ourport
->tx_claimed
= 0;
973 ourport
->tx_mode
= 0;
976 if (ourport
->rx_claimed
) {
977 if (!s3c24xx_serial_has_interrupt_mask(port
))
978 free_irq(ourport
->rx_irq
, ourport
);
979 ourport
->rx_claimed
= 0;
980 rx_enabled(port
) = 0;
983 /* Clear pending interrupts and mask all interrupts */
984 if (s3c24xx_serial_has_interrupt_mask(port
)) {
985 free_irq(port
->irq
, ourport
);
987 wr_regl(port
, S3C64XX_UINTP
, 0xf);
988 wr_regl(port
, S3C64XX_UINTM
, 0xf);
992 s3c24xx_serial_release_dma(ourport
);
994 ourport
->tx_in_progress
= 0;
997 static int s3c24xx_serial_startup(struct uart_port
*port
)
999 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
1002 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
1003 port
, (unsigned long long)port
->mapbase
, port
->membase
);
1005 rx_enabled(port
) = 1;
1007 ret
= request_irq(ourport
->rx_irq
, s3c24xx_serial_rx_chars
, 0,
1008 s3c24xx_serial_portname(port
), ourport
);
1011 dev_err(port
->dev
, "cannot get irq %d\n", ourport
->rx_irq
);
1015 ourport
->rx_claimed
= 1;
1017 dbg("requesting tx irq...\n");
1019 tx_enabled(port
) = 1;
1021 ret
= request_irq(ourport
->tx_irq
, s3c24xx_serial_tx_chars
, 0,
1022 s3c24xx_serial_portname(port
), ourport
);
1025 dev_err(port
->dev
, "cannot get irq %d\n", ourport
->tx_irq
);
1029 ourport
->tx_claimed
= 1;
1031 dbg("s3c24xx_serial_startup ok\n");
1033 /* the port reset code should have done the correct
1034 * register setup for the port controls */
1039 s3c24xx_serial_shutdown(port
);
1043 static int s3c64xx_serial_startup(struct uart_port
*port
)
1045 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
1046 unsigned long flags
;
1050 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1051 port
, (unsigned long long)port
->mapbase
, port
->membase
);
1053 wr_regl(port
, S3C64XX_UINTM
, 0xf);
1055 ret
= s3c24xx_serial_request_dma(ourport
);
1057 dev_warn(port
->dev
, "DMA request failed\n");
1062 ret
= request_irq(port
->irq
, s3c64xx_serial_handle_irq
, IRQF_SHARED
,
1063 s3c24xx_serial_portname(port
), ourport
);
1065 dev_err(port
->dev
, "cannot get irq %d\n", port
->irq
);
1069 /* For compatibility with s3c24xx Soc's */
1070 rx_enabled(port
) = 1;
1071 ourport
->rx_claimed
= 1;
1072 tx_enabled(port
) = 0;
1073 ourport
->tx_claimed
= 1;
1075 spin_lock_irqsave(&port
->lock
, flags
);
1077 ufcon
= rd_regl(port
, S3C2410_UFCON
);
1078 ufcon
|= S3C2410_UFCON_RESETRX
| S5PV210_UFCON_RXTRIG8
;
1079 if (!uart_console(port
))
1080 ufcon
|= S3C2410_UFCON_RESETTX
;
1081 wr_regl(port
, S3C2410_UFCON
, ufcon
);
1083 enable_rx_pio(ourport
);
1085 spin_unlock_irqrestore(&port
->lock
, flags
);
1087 /* Enable Rx Interrupt */
1088 __clear_bit(S3C64XX_UINTM_RXD
, portaddrl(port
, S3C64XX_UINTM
));
1090 dbg("s3c64xx_serial_startup ok\n");
1094 /* power power management control */
1096 static void s3c24xx_serial_pm(struct uart_port
*port
, unsigned int level
,
1099 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
1100 int timeout
= 10000;
1102 ourport
->pm_level
= level
;
1106 while (--timeout
&& !s3c24xx_serial_txempty_nofifo(port
))
1109 if (!IS_ERR(ourport
->baudclk
))
1110 clk_disable_unprepare(ourport
->baudclk
);
1112 clk_disable_unprepare(ourport
->clk
);
1116 clk_prepare_enable(ourport
->clk
);
1118 if (!IS_ERR(ourport
->baudclk
))
1119 clk_prepare_enable(ourport
->baudclk
);
1123 dev_err(port
->dev
, "s3c24xx_serial: unknown pm %d\n", level
);
1127 /* baud rate calculation
1129 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1130 * of different sources, including the peripheral clock ("pclk") and an
1131 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1132 * with a programmable extra divisor.
1134 * The following code goes through the clock sources, and calculates the
1135 * baud clocks (and the resultant actual baud rates) and then tries to
1136 * pick the closest one and select that.
1140 #define MAX_CLK_NAME_LENGTH 15
1142 static inline int s3c24xx_serial_getsource(struct uart_port
*port
)
1144 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
1147 if (info
->num_clks
== 1)
1150 ucon
= rd_regl(port
, S3C2410_UCON
);
1151 ucon
&= info
->clksel_mask
;
1152 return ucon
>> info
->clksel_shift
;
1155 static void s3c24xx_serial_setsource(struct uart_port
*port
,
1156 unsigned int clk_sel
)
1158 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
1161 if (info
->num_clks
== 1)
1164 ucon
= rd_regl(port
, S3C2410_UCON
);
1165 if ((ucon
& info
->clksel_mask
) >> info
->clksel_shift
== clk_sel
)
1168 ucon
&= ~info
->clksel_mask
;
1169 ucon
|= clk_sel
<< info
->clksel_shift
;
1170 wr_regl(port
, S3C2410_UCON
, ucon
);
1173 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port
*ourport
,
1174 unsigned int req_baud
, struct clk
**best_clk
,
1175 unsigned int *clk_num
)
1177 struct s3c24xx_uart_info
*info
= ourport
->info
;
1180 unsigned int cnt
, baud
, quot
, clk_sel
, best_quot
= 0;
1181 char clkname
[MAX_CLK_NAME_LENGTH
];
1182 int calc_deviation
, deviation
= (1 << 30) - 1;
1184 clk_sel
= (ourport
->cfg
->clk_sel
) ? ourport
->cfg
->clk_sel
:
1185 ourport
->info
->def_clk_sel
;
1186 for (cnt
= 0; cnt
< info
->num_clks
; cnt
++) {
1187 if (!(clk_sel
& (1 << cnt
)))
1190 sprintf(clkname
, "clk_uart_baud%d", cnt
);
1191 clk
= clk_get(ourport
->port
.dev
, clkname
);
1195 rate
= clk_get_rate(clk
);
1199 if (ourport
->info
->has_divslot
) {
1200 unsigned long div
= rate
/ req_baud
;
1202 /* The UDIVSLOT register on the newer UARTs allows us to
1203 * get a divisor adjustment of 1/16th on the baud clock.
1205 * We don't keep the UDIVSLOT value (the 16ths we
1206 * calculated by not multiplying the baud by 16) as it
1207 * is easy enough to recalculate.
1213 quot
= (rate
+ (8 * req_baud
)) / (16 * req_baud
);
1214 baud
= rate
/ (quot
* 16);
1218 calc_deviation
= req_baud
- baud
;
1219 if (calc_deviation
< 0)
1220 calc_deviation
= -calc_deviation
;
1222 if (calc_deviation
< deviation
) {
1226 deviation
= calc_deviation
;
1235 * This table takes the fractional value of the baud divisor and gives
1236 * the recommended setting for the UDIVSLOT register.
1238 static u16 udivslot_table
[16] = {
1257 static void s3c24xx_serial_set_termios(struct uart_port
*port
,
1258 struct ktermios
*termios
,
1259 struct ktermios
*old
)
1261 struct s3c2410_uartcfg
*cfg
= s3c24xx_port_to_cfg(port
);
1262 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
1263 struct clk
*clk
= ERR_PTR(-EINVAL
);
1264 unsigned long flags
;
1265 unsigned int baud
, quot
, clk_sel
= 0;
1268 unsigned int udivslot
= 0;
1271 * We don't support modem control lines.
1273 termios
->c_cflag
&= ~(HUPCL
| CMSPAR
);
1274 termios
->c_cflag
|= CLOCAL
;
1277 * Ask the core to calculate the divisor for us.
1280 baud
= uart_get_baud_rate(port
, termios
, old
, 0, 115200*8);
1281 quot
= s3c24xx_serial_getclk(ourport
, baud
, &clk
, &clk_sel
);
1282 if (baud
== 38400 && (port
->flags
& UPF_SPD_MASK
) == UPF_SPD_CUST
)
1283 quot
= port
->custom_divisor
;
1287 /* check to see if we need to change clock source */
1289 if (ourport
->baudclk
!= clk
) {
1290 s3c24xx_serial_setsource(port
, clk_sel
);
1292 if (!IS_ERR(ourport
->baudclk
)) {
1293 clk_disable_unprepare(ourport
->baudclk
);
1294 ourport
->baudclk
= ERR_PTR(-EINVAL
);
1297 clk_prepare_enable(clk
);
1299 ourport
->baudclk
= clk
;
1300 ourport
->baudclk_rate
= clk
? clk_get_rate(clk
) : 0;
1303 if (ourport
->info
->has_divslot
) {
1304 unsigned int div
= ourport
->baudclk_rate
/ baud
;
1306 if (cfg
->has_fracval
) {
1307 udivslot
= (div
& 15);
1308 dbg("fracval = %04x\n", udivslot
);
1310 udivslot
= udivslot_table
[div
& 15];
1311 dbg("udivslot = %04x (div %d)\n", udivslot
, div
& 15);
1315 switch (termios
->c_cflag
& CSIZE
) {
1317 dbg("config: 5bits/char\n");
1318 ulcon
= S3C2410_LCON_CS5
;
1321 dbg("config: 6bits/char\n");
1322 ulcon
= S3C2410_LCON_CS6
;
1325 dbg("config: 7bits/char\n");
1326 ulcon
= S3C2410_LCON_CS7
;
1330 dbg("config: 8bits/char\n");
1331 ulcon
= S3C2410_LCON_CS8
;
1335 /* preserve original lcon IR settings */
1336 ulcon
|= (cfg
->ulcon
& S3C2410_LCON_IRM
);
1338 if (termios
->c_cflag
& CSTOPB
)
1339 ulcon
|= S3C2410_LCON_STOPB
;
1341 if (termios
->c_cflag
& PARENB
) {
1342 if (termios
->c_cflag
& PARODD
)
1343 ulcon
|= S3C2410_LCON_PODD
;
1345 ulcon
|= S3C2410_LCON_PEVEN
;
1347 ulcon
|= S3C2410_LCON_PNONE
;
1350 spin_lock_irqsave(&port
->lock
, flags
);
1352 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1353 ulcon
, quot
, udivslot
);
1355 wr_regl(port
, S3C2410_ULCON
, ulcon
);
1356 wr_regl(port
, S3C2410_UBRDIV
, quot
);
1358 umcon
= rd_regl(port
, S3C2410_UMCON
);
1359 if (termios
->c_cflag
& CRTSCTS
) {
1360 umcon
|= S3C2410_UMCOM_AFC
;
1361 /* Disable RTS when RX FIFO contains 63 bytes */
1362 umcon
&= ~S3C2412_UMCON_AFC_8
;
1364 umcon
&= ~S3C2410_UMCOM_AFC
;
1366 wr_regl(port
, S3C2410_UMCON
, umcon
);
1368 if (ourport
->info
->has_divslot
)
1369 wr_regl(port
, S3C2443_DIVSLOT
, udivslot
);
1371 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1372 rd_regl(port
, S3C2410_ULCON
),
1373 rd_regl(port
, S3C2410_UCON
),
1374 rd_regl(port
, S3C2410_UFCON
));
1377 * Update the per-port timeout.
1379 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1382 * Which character status flags are we interested in?
1384 port
->read_status_mask
= S3C2410_UERSTAT_OVERRUN
;
1385 if (termios
->c_iflag
& INPCK
)
1386 port
->read_status_mask
|= S3C2410_UERSTAT_FRAME
|
1387 S3C2410_UERSTAT_PARITY
;
1389 * Which character status flags should we ignore?
1391 port
->ignore_status_mask
= 0;
1392 if (termios
->c_iflag
& IGNPAR
)
1393 port
->ignore_status_mask
|= S3C2410_UERSTAT_OVERRUN
;
1394 if (termios
->c_iflag
& IGNBRK
&& termios
->c_iflag
& IGNPAR
)
1395 port
->ignore_status_mask
|= S3C2410_UERSTAT_FRAME
;
1398 * Ignore all characters if CREAD is not set.
1400 if ((termios
->c_cflag
& CREAD
) == 0)
1401 port
->ignore_status_mask
|= RXSTAT_DUMMY_READ
;
1403 spin_unlock_irqrestore(&port
->lock
, flags
);
1406 static const char *s3c24xx_serial_type(struct uart_port
*port
)
1408 switch (port
->type
) {
1416 return "S3C6400/10";
1422 #define MAP_SIZE (0x100)
1424 static void s3c24xx_serial_release_port(struct uart_port
*port
)
1426 release_mem_region(port
->mapbase
, MAP_SIZE
);
1429 static int s3c24xx_serial_request_port(struct uart_port
*port
)
1431 const char *name
= s3c24xx_serial_portname(port
);
1432 return request_mem_region(port
->mapbase
, MAP_SIZE
, name
) ? 0 : -EBUSY
;
1435 static void s3c24xx_serial_config_port(struct uart_port
*port
, int flags
)
1437 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
1439 if (flags
& UART_CONFIG_TYPE
&&
1440 s3c24xx_serial_request_port(port
) == 0)
1441 port
->type
= info
->type
;
1445 * verify the new serial_struct (for TIOCSSERIAL).
1448 s3c24xx_serial_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
1450 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
1452 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= info
->type
)
1459 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1461 static struct console s3c24xx_serial_console
;
1463 static int __init
s3c24xx_serial_console_init(void)
1465 register_console(&s3c24xx_serial_console
);
1468 console_initcall(s3c24xx_serial_console_init
);
1470 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1472 #define S3C24XX_SERIAL_CONSOLE NULL
1475 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1476 static int s3c24xx_serial_get_poll_char(struct uart_port
*port
);
1477 static void s3c24xx_serial_put_poll_char(struct uart_port
*port
,
1481 static struct uart_ops s3c24xx_serial_ops
= {
1482 .pm
= s3c24xx_serial_pm
,
1483 .tx_empty
= s3c24xx_serial_tx_empty
,
1484 .get_mctrl
= s3c24xx_serial_get_mctrl
,
1485 .set_mctrl
= s3c24xx_serial_set_mctrl
,
1486 .stop_tx
= s3c24xx_serial_stop_tx
,
1487 .start_tx
= s3c24xx_serial_start_tx
,
1488 .stop_rx
= s3c24xx_serial_stop_rx
,
1489 .break_ctl
= s3c24xx_serial_break_ctl
,
1490 .startup
= s3c24xx_serial_startup
,
1491 .shutdown
= s3c24xx_serial_shutdown
,
1492 .set_termios
= s3c24xx_serial_set_termios
,
1493 .type
= s3c24xx_serial_type
,
1494 .release_port
= s3c24xx_serial_release_port
,
1495 .request_port
= s3c24xx_serial_request_port
,
1496 .config_port
= s3c24xx_serial_config_port
,
1497 .verify_port
= s3c24xx_serial_verify_port
,
1498 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1499 .poll_get_char
= s3c24xx_serial_get_poll_char
,
1500 .poll_put_char
= s3c24xx_serial_put_poll_char
,
1504 static struct uart_driver s3c24xx_uart_drv
= {
1505 .owner
= THIS_MODULE
,
1506 .driver_name
= "s3c2410_serial",
1507 .nr
= CONFIG_SERIAL_SAMSUNG_UARTS
,
1508 .cons
= S3C24XX_SERIAL_CONSOLE
,
1509 .dev_name
= S3C24XX_SERIAL_NAME
,
1510 .major
= S3C24XX_SERIAL_MAJOR
,
1511 .minor
= S3C24XX_SERIAL_MINOR
,
1514 #define __PORT_LOCK_UNLOCKED(i) \
1515 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1516 static struct s3c24xx_uart_port
1517 s3c24xx_serial_ports
[CONFIG_SERIAL_SAMSUNG_UARTS
] = {
1520 .lock
= __PORT_LOCK_UNLOCKED(0),
1524 .ops
= &s3c24xx_serial_ops
,
1525 .flags
= UPF_BOOT_AUTOCONF
,
1531 .lock
= __PORT_LOCK_UNLOCKED(1),
1535 .ops
= &s3c24xx_serial_ops
,
1536 .flags
= UPF_BOOT_AUTOCONF
,
1540 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1544 .lock
= __PORT_LOCK_UNLOCKED(2),
1548 .ops
= &s3c24xx_serial_ops
,
1549 .flags
= UPF_BOOT_AUTOCONF
,
1554 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1557 .lock
= __PORT_LOCK_UNLOCKED(3),
1561 .ops
= &s3c24xx_serial_ops
,
1562 .flags
= UPF_BOOT_AUTOCONF
,
1568 #undef __PORT_LOCK_UNLOCKED
1570 /* s3c24xx_serial_resetport
1572 * reset the fifos and other the settings.
1575 static void s3c24xx_serial_resetport(struct uart_port
*port
,
1576 struct s3c2410_uartcfg
*cfg
)
1578 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
1579 unsigned long ucon
= rd_regl(port
, S3C2410_UCON
);
1580 unsigned int ucon_mask
;
1582 ucon_mask
= info
->clksel_mask
;
1583 if (info
->type
== PORT_S3C2440
)
1584 ucon_mask
|= S3C2440_UCON0_DIVMASK
;
1587 wr_regl(port
, S3C2410_UCON
, ucon
| cfg
->ucon
);
1589 /* reset both fifos */
1590 wr_regl(port
, S3C2410_UFCON
, cfg
->ufcon
| S3C2410_UFCON_RESETBOTH
);
1591 wr_regl(port
, S3C2410_UFCON
, cfg
->ufcon
);
1593 /* some delay is required after fifo reset */
1598 #ifdef CONFIG_CPU_FREQ
1600 static int s3c24xx_serial_cpufreq_transition(struct notifier_block
*nb
,
1601 unsigned long val
, void *data
)
1603 struct s3c24xx_uart_port
*port
;
1604 struct uart_port
*uport
;
1606 port
= container_of(nb
, struct s3c24xx_uart_port
, freq_transition
);
1607 uport
= &port
->port
;
1609 /* check to see if port is enabled */
1611 if (port
->pm_level
!= 0)
1614 /* try and work out if the baudrate is changing, we can detect
1615 * a change in rate, but we do not have support for detecting
1616 * a disturbance in the clock-rate over the change.
1619 if (IS_ERR(port
->baudclk
))
1622 if (port
->baudclk_rate
== clk_get_rate(port
->baudclk
))
1625 if (val
== CPUFREQ_PRECHANGE
) {
1626 /* we should really shut the port down whilst the
1627 * frequency change is in progress. */
1629 } else if (val
== CPUFREQ_POSTCHANGE
) {
1630 struct ktermios
*termios
;
1631 struct tty_struct
*tty
;
1633 if (uport
->state
== NULL
)
1636 tty
= uport
->state
->port
.tty
;
1641 termios
= &tty
->termios
;
1643 if (termios
== NULL
) {
1644 dev_warn(uport
->dev
, "%s: no termios?\n", __func__
);
1648 s3c24xx_serial_set_termios(uport
, termios
, NULL
);
1656 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port
*port
)
1658 port
->freq_transition
.notifier_call
= s3c24xx_serial_cpufreq_transition
;
1660 return cpufreq_register_notifier(&port
->freq_transition
,
1661 CPUFREQ_TRANSITION_NOTIFIER
);
1665 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port
*port
)
1667 cpufreq_unregister_notifier(&port
->freq_transition
,
1668 CPUFREQ_TRANSITION_NOTIFIER
);
1673 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port
*port
)
1679 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port
*port
)
1684 /* s3c24xx_serial_init_port
1686 * initialise a single serial port from the platform device given
1689 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port
*ourport
,
1690 struct platform_device
*platdev
)
1692 struct uart_port
*port
= &ourport
->port
;
1693 struct s3c2410_uartcfg
*cfg
= ourport
->cfg
;
1694 struct resource
*res
;
1697 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port
, platdev
);
1699 if (platdev
== NULL
)
1702 if (port
->mapbase
!= 0)
1705 /* setup info for port */
1706 port
->dev
= &platdev
->dev
;
1708 /* Startup sequence is different for s3c64xx and higher SoC's */
1709 if (s3c24xx_serial_has_interrupt_mask(port
))
1710 s3c24xx_serial_ops
.startup
= s3c64xx_serial_startup
;
1714 if (cfg
->uart_flags
& UPF_CONS_FLOW
) {
1715 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1716 port
->flags
|= UPF_CONS_FLOW
;
1719 /* sort our the physical and virtual addresses for each UART */
1721 res
= platform_get_resource(platdev
, IORESOURCE_MEM
, 0);
1723 dev_err(port
->dev
, "failed to find memory resource for uart\n");
1727 dbg("resource %pR)\n", res
);
1729 port
->membase
= devm_ioremap(port
->dev
, res
->start
, resource_size(res
));
1730 if (!port
->membase
) {
1731 dev_err(port
->dev
, "failed to remap controller address\n");
1735 port
->mapbase
= res
->start
;
1736 ret
= platform_get_irq(platdev
, 0);
1741 ourport
->rx_irq
= ret
;
1742 ourport
->tx_irq
= ret
+ 1;
1745 ret
= platform_get_irq(platdev
, 1);
1747 ourport
->tx_irq
= ret
;
1749 * DMA is currently supported only on DT platforms, if DMA properties
1752 if (platdev
->dev
.of_node
&& of_find_property(platdev
->dev
.of_node
,
1754 ourport
->dma
= devm_kzalloc(port
->dev
,
1755 sizeof(*ourport
->dma
),
1761 ourport
->clk
= clk_get(&platdev
->dev
, "uart");
1762 if (IS_ERR(ourport
->clk
)) {
1763 pr_err("%s: Controller clock not found\n",
1764 dev_name(&platdev
->dev
));
1765 return PTR_ERR(ourport
->clk
);
1768 ret
= clk_prepare_enable(ourport
->clk
);
1770 pr_err("uart: clock failed to prepare+enable: %d\n", ret
);
1771 clk_put(ourport
->clk
);
1775 /* Keep all interrupts masked and cleared */
1776 if (s3c24xx_serial_has_interrupt_mask(port
)) {
1777 wr_regl(port
, S3C64XX_UINTM
, 0xf);
1778 wr_regl(port
, S3C64XX_UINTP
, 0xf);
1779 wr_regl(port
, S3C64XX_UINTSP
, 0xf);
1782 dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1783 &port
->mapbase
, port
->membase
, port
->irq
,
1784 ourport
->rx_irq
, ourport
->tx_irq
, port
->uartclk
);
1786 /* reset the fifos (and setup the uart) */
1787 s3c24xx_serial_resetport(port
, cfg
);
1791 /* Device driver serial port probe */
1793 static const struct of_device_id s3c24xx_uart_dt_match
[];
1794 static int probe_index
;
1796 static inline struct s3c24xx_serial_drv_data
*s3c24xx_get_driver_data(
1797 struct platform_device
*pdev
)
1800 if (pdev
->dev
.of_node
) {
1801 const struct of_device_id
*match
;
1802 match
= of_match_node(s3c24xx_uart_dt_match
, pdev
->dev
.of_node
);
1803 return (struct s3c24xx_serial_drv_data
*)match
->data
;
1806 return (struct s3c24xx_serial_drv_data
*)
1807 platform_get_device_id(pdev
)->driver_data
;
1810 static int s3c24xx_serial_probe(struct platform_device
*pdev
)
1812 struct device_node
*np
= pdev
->dev
.of_node
;
1813 struct s3c24xx_uart_port
*ourport
;
1814 int index
= probe_index
;
1818 ret
= of_alias_get_id(np
, "serial");
1823 dbg("s3c24xx_serial_probe(%p) %d\n", pdev
, index
);
1825 ourport
= &s3c24xx_serial_ports
[index
];
1827 ourport
->drv_data
= s3c24xx_get_driver_data(pdev
);
1828 if (!ourport
->drv_data
) {
1829 dev_err(&pdev
->dev
, "could not find driver data\n");
1833 ourport
->baudclk
= ERR_PTR(-EINVAL
);
1834 ourport
->info
= ourport
->drv_data
->info
;
1835 ourport
->cfg
= (dev_get_platdata(&pdev
->dev
)) ?
1836 dev_get_platdata(&pdev
->dev
) :
1837 ourport
->drv_data
->def_cfg
;
1840 of_property_read_u32(np
,
1841 "samsung,uart-fifosize", &ourport
->port
.fifosize
);
1843 if (ourport
->drv_data
->fifosize
[index
])
1844 ourport
->port
.fifosize
= ourport
->drv_data
->fifosize
[index
];
1845 else if (ourport
->info
->fifosize
)
1846 ourport
->port
.fifosize
= ourport
->info
->fifosize
;
1849 * DMA transfers must be aligned at least to cache line size,
1850 * so find minimal transfer size suitable for DMA mode
1852 ourport
->min_dma_size
= max_t(int, ourport
->port
.fifosize
,
1853 dma_get_cache_alignment());
1857 dbg("%s: initialising port %p...\n", __func__
, ourport
);
1859 ret
= s3c24xx_serial_init_port(ourport
, pdev
);
1863 if (!s3c24xx_uart_drv
.state
) {
1864 ret
= uart_register_driver(&s3c24xx_uart_drv
);
1866 pr_err("Failed to register Samsung UART driver\n");
1871 dbg("%s: adding port\n", __func__
);
1872 uart_add_one_port(&s3c24xx_uart_drv
, &ourport
->port
);
1873 platform_set_drvdata(pdev
, &ourport
->port
);
1876 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1877 * so that a potential re-enablement through the pm-callback overlaps
1878 * and keeps the clock enabled in this case.
1880 clk_disable_unprepare(ourport
->clk
);
1882 ret
= s3c24xx_serial_cpufreq_register(ourport
);
1884 dev_err(&pdev
->dev
, "failed to add cpufreq notifier\n");
1889 static int s3c24xx_serial_remove(struct platform_device
*dev
)
1891 struct uart_port
*port
= s3c24xx_dev_to_port(&dev
->dev
);
1894 s3c24xx_serial_cpufreq_deregister(to_ourport(port
));
1895 uart_remove_one_port(&s3c24xx_uart_drv
, port
);
1898 uart_unregister_driver(&s3c24xx_uart_drv
);
1903 /* UART power management code */
1904 #ifdef CONFIG_PM_SLEEP
1905 static int s3c24xx_serial_suspend(struct device
*dev
)
1907 struct uart_port
*port
= s3c24xx_dev_to_port(dev
);
1910 uart_suspend_port(&s3c24xx_uart_drv
, port
);
1915 static int s3c24xx_serial_resume(struct device
*dev
)
1917 struct uart_port
*port
= s3c24xx_dev_to_port(dev
);
1918 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
1921 clk_prepare_enable(ourport
->clk
);
1922 s3c24xx_serial_resetport(port
, s3c24xx_port_to_cfg(port
));
1923 clk_disable_unprepare(ourport
->clk
);
1925 uart_resume_port(&s3c24xx_uart_drv
, port
);
1931 static int s3c24xx_serial_resume_noirq(struct device
*dev
)
1933 struct uart_port
*port
= s3c24xx_dev_to_port(dev
);
1936 /* restore IRQ mask */
1937 if (s3c24xx_serial_has_interrupt_mask(port
)) {
1938 unsigned int uintm
= 0xf;
1939 if (tx_enabled(port
))
1940 uintm
&= ~S3C64XX_UINTM_TXD_MSK
;
1941 if (rx_enabled(port
))
1942 uintm
&= ~S3C64XX_UINTM_RXD_MSK
;
1943 wr_regl(port
, S3C64XX_UINTM
, uintm
);
1950 static const struct dev_pm_ops s3c24xx_serial_pm_ops
= {
1951 .suspend
= s3c24xx_serial_suspend
,
1952 .resume
= s3c24xx_serial_resume
,
1953 .resume_noirq
= s3c24xx_serial_resume_noirq
,
1955 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1957 #else /* !CONFIG_PM_SLEEP */
1959 #define SERIAL_SAMSUNG_PM_OPS NULL
1960 #endif /* CONFIG_PM_SLEEP */
1964 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1966 static struct uart_port
*cons_uart
;
1969 s3c24xx_serial_console_txrdy(struct uart_port
*port
, unsigned int ufcon
)
1971 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
1972 unsigned long ufstat
, utrstat
;
1974 if (ufcon
& S3C2410_UFCON_FIFOMODE
) {
1975 /* fifo mode - check amount of data in fifo registers... */
1977 ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
1978 return (ufstat
& info
->tx_fifofull
) ? 0 : 1;
1981 /* in non-fifo mode, we go and use the tx buffer empty */
1983 utrstat
= rd_regl(port
, S3C2410_UTRSTAT
);
1984 return (utrstat
& S3C2410_UTRSTAT_TXE
) ? 1 : 0;
1988 s3c24xx_port_configured(unsigned int ucon
)
1990 /* consider the serial port configured if the tx/rx mode set */
1991 return (ucon
& 0xf) != 0;
1994 #ifdef CONFIG_CONSOLE_POLL
1996 * Console polling routines for writing and reading from the uart while
1997 * in an interrupt or debug context.
2000 static int s3c24xx_serial_get_poll_char(struct uart_port
*port
)
2002 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
2003 unsigned int ufstat
;
2005 ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
2006 if (s3c24xx_serial_rx_fifocnt(ourport
, ufstat
) == 0)
2007 return NO_POLL_CHAR
;
2009 return rd_regb(port
, S3C2410_URXH
);
2012 static void s3c24xx_serial_put_poll_char(struct uart_port
*port
,
2015 unsigned int ufcon
= rd_regl(port
, S3C2410_UFCON
);
2016 unsigned int ucon
= rd_regl(port
, S3C2410_UCON
);
2018 /* not possible to xmit on unconfigured port */
2019 if (!s3c24xx_port_configured(ucon
))
2022 while (!s3c24xx_serial_console_txrdy(port
, ufcon
))
2024 wr_regb(port
, S3C2410_UTXH
, c
);
2027 #endif /* CONFIG_CONSOLE_POLL */
2030 s3c24xx_serial_console_putchar(struct uart_port
*port
, int ch
)
2032 unsigned int ufcon
= rd_regl(port
, S3C2410_UFCON
);
2034 while (!s3c24xx_serial_console_txrdy(port
, ufcon
))
2036 wr_regb(port
, S3C2410_UTXH
, ch
);
2040 s3c24xx_serial_console_write(struct console
*co
, const char *s
,
2043 unsigned int ucon
= rd_regl(cons_uart
, S3C2410_UCON
);
2045 /* not possible to xmit on unconfigured port */
2046 if (!s3c24xx_port_configured(ucon
))
2049 uart_console_write(cons_uart
, s
, count
, s3c24xx_serial_console_putchar
);
2053 s3c24xx_serial_get_options(struct uart_port
*port
, int *baud
,
2054 int *parity
, int *bits
)
2059 unsigned int ubrdiv
;
2061 unsigned int clk_sel
;
2062 char clk_name
[MAX_CLK_NAME_LENGTH
];
2064 ulcon
= rd_regl(port
, S3C2410_ULCON
);
2065 ucon
= rd_regl(port
, S3C2410_UCON
);
2066 ubrdiv
= rd_regl(port
, S3C2410_UBRDIV
);
2068 dbg("s3c24xx_serial_get_options: port=%p\n"
2069 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2070 port
, ulcon
, ucon
, ubrdiv
);
2072 if (s3c24xx_port_configured(ucon
)) {
2073 switch (ulcon
& S3C2410_LCON_CSMASK
) {
2074 case S3C2410_LCON_CS5
:
2077 case S3C2410_LCON_CS6
:
2080 case S3C2410_LCON_CS7
:
2083 case S3C2410_LCON_CS8
:
2089 switch (ulcon
& S3C2410_LCON_PMASK
) {
2090 case S3C2410_LCON_PEVEN
:
2094 case S3C2410_LCON_PODD
:
2098 case S3C2410_LCON_PNONE
:
2103 /* now calculate the baud rate */
2105 clk_sel
= s3c24xx_serial_getsource(port
);
2106 sprintf(clk_name
, "clk_uart_baud%d", clk_sel
);
2108 clk
= clk_get(port
->dev
, clk_name
);
2110 rate
= clk_get_rate(clk
);
2114 *baud
= rate
/ (16 * (ubrdiv
+ 1));
2115 dbg("calculated baud %d\n", *baud
);
2121 s3c24xx_serial_console_setup(struct console
*co
, char *options
)
2123 struct uart_port
*port
;
2129 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2130 co
, co
->index
, options
);
2132 /* is this a valid port */
2134 if (co
->index
== -1 || co
->index
>= CONFIG_SERIAL_SAMSUNG_UARTS
)
2137 port
= &s3c24xx_serial_ports
[co
->index
].port
;
2139 /* is the port configured? */
2141 if (port
->mapbase
== 0x0)
2146 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port
, co
->index
);
2149 * Check whether an invalid uart number has been specified, and
2150 * if so, search for the first available port that does have
2154 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
2156 s3c24xx_serial_get_options(port
, &baud
, &parity
, &bits
);
2158 dbg("s3c24xx_serial_console_setup: baud %d\n", baud
);
2160 return uart_set_options(port
, co
, baud
, parity
, bits
, flow
);
2163 static struct console s3c24xx_serial_console
= {
2164 .name
= S3C24XX_SERIAL_NAME
,
2165 .device
= uart_console_device
,
2166 .flags
= CON_PRINTBUFFER
,
2168 .write
= s3c24xx_serial_console_write
,
2169 .setup
= s3c24xx_serial_console_setup
,
2170 .data
= &s3c24xx_uart_drv
,
2172 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2174 #ifdef CONFIG_CPU_S3C2410
2175 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data
= {
2176 .info
= &(struct s3c24xx_uart_info
) {
2177 .name
= "Samsung S3C2410 UART",
2178 .type
= PORT_S3C2410
,
2180 .rx_fifomask
= S3C2410_UFSTAT_RXMASK
,
2181 .rx_fifoshift
= S3C2410_UFSTAT_RXSHIFT
,
2182 .rx_fifofull
= S3C2410_UFSTAT_RXFULL
,
2183 .tx_fifofull
= S3C2410_UFSTAT_TXFULL
,
2184 .tx_fifomask
= S3C2410_UFSTAT_TXMASK
,
2185 .tx_fifoshift
= S3C2410_UFSTAT_TXSHIFT
,
2186 .def_clk_sel
= S3C2410_UCON_CLKSEL0
,
2188 .clksel_mask
= S3C2410_UCON_CLKMASK
,
2189 .clksel_shift
= S3C2410_UCON_CLKSHIFT
,
2191 .def_cfg
= &(struct s3c2410_uartcfg
) {
2192 .ucon
= S3C2410_UCON_DEFAULT
,
2193 .ufcon
= S3C2410_UFCON_DEFAULT
,
2196 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2198 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2201 #ifdef CONFIG_CPU_S3C2412
2202 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data
= {
2203 .info
= &(struct s3c24xx_uart_info
) {
2204 .name
= "Samsung S3C2412 UART",
2205 .type
= PORT_S3C2412
,
2208 .rx_fifomask
= S3C2440_UFSTAT_RXMASK
,
2209 .rx_fifoshift
= S3C2440_UFSTAT_RXSHIFT
,
2210 .rx_fifofull
= S3C2440_UFSTAT_RXFULL
,
2211 .tx_fifofull
= S3C2440_UFSTAT_TXFULL
,
2212 .tx_fifomask
= S3C2440_UFSTAT_TXMASK
,
2213 .tx_fifoshift
= S3C2440_UFSTAT_TXSHIFT
,
2214 .def_clk_sel
= S3C2410_UCON_CLKSEL2
,
2216 .clksel_mask
= S3C2412_UCON_CLKMASK
,
2217 .clksel_shift
= S3C2412_UCON_CLKSHIFT
,
2219 .def_cfg
= &(struct s3c2410_uartcfg
) {
2220 .ucon
= S3C2410_UCON_DEFAULT
,
2221 .ufcon
= S3C2410_UFCON_DEFAULT
,
2224 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2226 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2229 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2230 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2231 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data
= {
2232 .info
= &(struct s3c24xx_uart_info
) {
2233 .name
= "Samsung S3C2440 UART",
2234 .type
= PORT_S3C2440
,
2237 .rx_fifomask
= S3C2440_UFSTAT_RXMASK
,
2238 .rx_fifoshift
= S3C2440_UFSTAT_RXSHIFT
,
2239 .rx_fifofull
= S3C2440_UFSTAT_RXFULL
,
2240 .tx_fifofull
= S3C2440_UFSTAT_TXFULL
,
2241 .tx_fifomask
= S3C2440_UFSTAT_TXMASK
,
2242 .tx_fifoshift
= S3C2440_UFSTAT_TXSHIFT
,
2243 .def_clk_sel
= S3C2410_UCON_CLKSEL2
,
2245 .clksel_mask
= S3C2412_UCON_CLKMASK
,
2246 .clksel_shift
= S3C2412_UCON_CLKSHIFT
,
2248 .def_cfg
= &(struct s3c2410_uartcfg
) {
2249 .ucon
= S3C2410_UCON_DEFAULT
,
2250 .ufcon
= S3C2410_UFCON_DEFAULT
,
2253 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2255 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2258 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2259 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data
= {
2260 .info
= &(struct s3c24xx_uart_info
) {
2261 .name
= "Samsung S3C6400 UART",
2262 .type
= PORT_S3C6400
,
2265 .rx_fifomask
= S3C2440_UFSTAT_RXMASK
,
2266 .rx_fifoshift
= S3C2440_UFSTAT_RXSHIFT
,
2267 .rx_fifofull
= S3C2440_UFSTAT_RXFULL
,
2268 .tx_fifofull
= S3C2440_UFSTAT_TXFULL
,
2269 .tx_fifomask
= S3C2440_UFSTAT_TXMASK
,
2270 .tx_fifoshift
= S3C2440_UFSTAT_TXSHIFT
,
2271 .def_clk_sel
= S3C2410_UCON_CLKSEL2
,
2273 .clksel_mask
= S3C6400_UCON_CLKMASK
,
2274 .clksel_shift
= S3C6400_UCON_CLKSHIFT
,
2276 .def_cfg
= &(struct s3c2410_uartcfg
) {
2277 .ucon
= S3C2410_UCON_DEFAULT
,
2278 .ufcon
= S3C2410_UFCON_DEFAULT
,
2281 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2283 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2286 #ifdef CONFIG_CPU_S5PV210
2287 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data
= {
2288 .info
= &(struct s3c24xx_uart_info
) {
2289 .name
= "Samsung S5PV210 UART",
2290 .type
= PORT_S3C6400
,
2292 .rx_fifomask
= S5PV210_UFSTAT_RXMASK
,
2293 .rx_fifoshift
= S5PV210_UFSTAT_RXSHIFT
,
2294 .rx_fifofull
= S5PV210_UFSTAT_RXFULL
,
2295 .tx_fifofull
= S5PV210_UFSTAT_TXFULL
,
2296 .tx_fifomask
= S5PV210_UFSTAT_TXMASK
,
2297 .tx_fifoshift
= S5PV210_UFSTAT_TXSHIFT
,
2298 .def_clk_sel
= S3C2410_UCON_CLKSEL0
,
2300 .clksel_mask
= S5PV210_UCON_CLKMASK
,
2301 .clksel_shift
= S5PV210_UCON_CLKSHIFT
,
2303 .def_cfg
= &(struct s3c2410_uartcfg
) {
2304 .ucon
= S5PV210_UCON_DEFAULT
,
2305 .ufcon
= S5PV210_UFCON_DEFAULT
,
2307 .fifosize
= { 256, 64, 16, 16 },
2309 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2311 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2314 #if defined(CONFIG_ARCH_EXYNOS)
2315 #define EXYNOS_COMMON_SERIAL_DRV_DATA \
2316 .info = &(struct s3c24xx_uart_info) { \
2317 .name = "Samsung Exynos UART", \
2318 .type = PORT_S3C6400, \
2320 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2321 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2322 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2323 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2324 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2325 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2326 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2329 .clksel_shift = 0, \
2331 .def_cfg = &(struct s3c2410_uartcfg) { \
2332 .ucon = S5PV210_UCON_DEFAULT, \
2333 .ufcon = S5PV210_UFCON_DEFAULT, \
2337 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2338 EXYNOS_COMMON_SERIAL_DRV_DATA
,
2339 .fifosize
= { 256, 64, 16, 16 },
2342 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data
= {
2343 EXYNOS_COMMON_SERIAL_DRV_DATA
,
2344 .fifosize
= { 64, 256, 16, 256 },
2347 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2348 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2350 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2351 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2354 static const struct platform_device_id s3c24xx_serial_driver_ids
[] = {
2356 .name
= "s3c2410-uart",
2357 .driver_data
= S3C2410_SERIAL_DRV_DATA
,
2359 .name
= "s3c2412-uart",
2360 .driver_data
= S3C2412_SERIAL_DRV_DATA
,
2362 .name
= "s3c2440-uart",
2363 .driver_data
= S3C2440_SERIAL_DRV_DATA
,
2365 .name
= "s3c6400-uart",
2366 .driver_data
= S3C6400_SERIAL_DRV_DATA
,
2368 .name
= "s5pv210-uart",
2369 .driver_data
= S5PV210_SERIAL_DRV_DATA
,
2371 .name
= "exynos4210-uart",
2372 .driver_data
= EXYNOS4210_SERIAL_DRV_DATA
,
2374 .name
= "exynos5433-uart",
2375 .driver_data
= EXYNOS5433_SERIAL_DRV_DATA
,
2379 MODULE_DEVICE_TABLE(platform
, s3c24xx_serial_driver_ids
);
2382 static const struct of_device_id s3c24xx_uart_dt_match
[] = {
2383 { .compatible
= "samsung,s3c2410-uart",
2384 .data
= (void *)S3C2410_SERIAL_DRV_DATA
},
2385 { .compatible
= "samsung,s3c2412-uart",
2386 .data
= (void *)S3C2412_SERIAL_DRV_DATA
},
2387 { .compatible
= "samsung,s3c2440-uart",
2388 .data
= (void *)S3C2440_SERIAL_DRV_DATA
},
2389 { .compatible
= "samsung,s3c6400-uart",
2390 .data
= (void *)S3C6400_SERIAL_DRV_DATA
},
2391 { .compatible
= "samsung,s5pv210-uart",
2392 .data
= (void *)S5PV210_SERIAL_DRV_DATA
},
2393 { .compatible
= "samsung,exynos4210-uart",
2394 .data
= (void *)EXYNOS4210_SERIAL_DRV_DATA
},
2395 { .compatible
= "samsung,exynos5433-uart",
2396 .data
= (void *)EXYNOS5433_SERIAL_DRV_DATA
},
2399 MODULE_DEVICE_TABLE(of
, s3c24xx_uart_dt_match
);
2402 static struct platform_driver samsung_serial_driver
= {
2403 .probe
= s3c24xx_serial_probe
,
2404 .remove
= s3c24xx_serial_remove
,
2405 .id_table
= s3c24xx_serial_driver_ids
,
2407 .name
= "samsung-uart",
2408 .pm
= SERIAL_SAMSUNG_PM_OPS
,
2409 .of_match_table
= of_match_ptr(s3c24xx_uart_dt_match
),
2413 module_platform_driver(samsung_serial_driver
);
2415 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2420 struct samsung_early_console_data
{
2424 static void samsung_early_busyuart(struct uart_port
*port
)
2426 while (!(readl(port
->membase
+ S3C2410_UTRSTAT
) & S3C2410_UTRSTAT_TXFE
))
2430 static void samsung_early_busyuart_fifo(struct uart_port
*port
)
2432 struct samsung_early_console_data
*data
= port
->private_data
;
2434 while (readl(port
->membase
+ S3C2410_UFSTAT
) & data
->txfull_mask
)
2438 static void samsung_early_putc(struct uart_port
*port
, int c
)
2440 if (readl(port
->membase
+ S3C2410_UFCON
) & S3C2410_UFCON_FIFOMODE
)
2441 samsung_early_busyuart_fifo(port
);
2443 samsung_early_busyuart(port
);
2445 writeb(c
, port
->membase
+ S3C2410_UTXH
);
2448 static void samsung_early_write(struct console
*con
, const char *s
, unsigned n
)
2450 struct earlycon_device
*dev
= con
->data
;
2452 uart_console_write(&dev
->port
, s
, n
, samsung_early_putc
);
2455 static int __init
samsung_early_console_setup(struct earlycon_device
*device
,
2458 if (!device
->port
.membase
)
2461 device
->con
->write
= samsung_early_write
;
2466 static struct samsung_early_console_data s3c2410_early_console_data
= {
2467 .txfull_mask
= S3C2410_UFSTAT_TXFULL
,
2470 static int __init
s3c2410_early_console_setup(struct earlycon_device
*device
,
2473 device
->port
.private_data
= &s3c2410_early_console_data
;
2474 return samsung_early_console_setup(device
, opt
);
2476 OF_EARLYCON_DECLARE(s3c2410
, "samsung,s3c2410-uart",
2477 s3c2410_early_console_setup
);
2478 EARLYCON_DECLARE(s3c2410
, s3c2410_early_console_setup
);
2480 /* S3C2412, S3C2440, S3C64xx */
2481 static struct samsung_early_console_data s3c2440_early_console_data
= {
2482 .txfull_mask
= S3C2440_UFSTAT_TXFULL
,
2485 static int __init
s3c2440_early_console_setup(struct earlycon_device
*device
,
2488 device
->port
.private_data
= &s3c2440_early_console_data
;
2489 return samsung_early_console_setup(device
, opt
);
2491 OF_EARLYCON_DECLARE(s3c2412
, "samsung,s3c2412-uart",
2492 s3c2440_early_console_setup
);
2493 OF_EARLYCON_DECLARE(s3c2440
, "samsung,s3c2440-uart",
2494 s3c2440_early_console_setup
);
2495 OF_EARLYCON_DECLARE(s3c6400
, "samsung,s3c6400-uart",
2496 s3c2440_early_console_setup
);
2497 EARLYCON_DECLARE(s3c2412
, s3c2440_early_console_setup
);
2498 EARLYCON_DECLARE(s3c2440
, s3c2440_early_console_setup
);
2499 EARLYCON_DECLARE(s3c6400
, s3c2440_early_console_setup
);
2501 /* S5PV210, EXYNOS */
2502 static struct samsung_early_console_data s5pv210_early_console_data
= {
2503 .txfull_mask
= S5PV210_UFSTAT_TXFULL
,
2506 static int __init
s5pv210_early_console_setup(struct earlycon_device
*device
,
2509 device
->port
.private_data
= &s5pv210_early_console_data
;
2510 return samsung_early_console_setup(device
, opt
);
2512 OF_EARLYCON_DECLARE(s5pv210
, "samsung,s5pv210-uart",
2513 s5pv210_early_console_setup
);
2514 OF_EARLYCON_DECLARE(exynos4210
, "samsung,exynos4210-uart",
2515 s5pv210_early_console_setup
);
2516 EARLYCON_DECLARE(s5pv210
, s5pv210_early_console_setup
);
2517 EARLYCON_DECLARE(exynos4210
, s5pv210_early_console_setup
);
2520 MODULE_ALIAS("platform:samsung-uart");
2521 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2522 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2523 MODULE_LICENSE("GPL v2");