2 * Driver core for Samsung SoC onboard UARTs.
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 /* Hote on 2410 error handling
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #include <linux/module.h>
32 #include <linux/ioport.h>
34 #include <linux/platform_device.h>
35 #include <linux/init.h>
36 #include <linux/sysrq.h>
37 #include <linux/console.h>
38 #include <linux/tty.h>
39 #include <linux/tty_flip.h>
40 #include <linux/serial_core.h>
41 #include <linux/serial.h>
42 #include <linux/serial_s3c.h>
43 #include <linux/delay.h>
44 #include <linux/clk.h>
45 #include <linux/cpufreq.h>
50 #ifdef CONFIG_SAMSUNG_CLOCK
51 #include <plat/clock.h>
56 /* UART name and device definitions */
58 #define S3C24XX_SERIAL_NAME "ttySAC"
59 #define S3C24XX_SERIAL_MAJOR 204
60 #define S3C24XX_SERIAL_MINOR 64
62 /* macros to change one thing to another */
64 #define tx_enabled(port) ((port)->unused[0])
65 #define rx_enabled(port) ((port)->unused[1])
67 /* flag to ignore all characters coming in */
68 #define RXSTAT_DUMMY_READ (0x10000000)
70 static inline struct s3c24xx_uart_port
*to_ourport(struct uart_port
*port
)
72 return container_of(port
, struct s3c24xx_uart_port
, port
);
75 /* translate a port to the device name */
77 static inline const char *s3c24xx_serial_portname(struct uart_port
*port
)
79 return to_platform_device(port
->dev
)->name
;
82 static int s3c24xx_serial_txempty_nofifo(struct uart_port
*port
)
84 return rd_regl(port
, S3C2410_UTRSTAT
) & S3C2410_UTRSTAT_TXE
;
88 * s3c64xx and later SoC's include the interrupt mask and status registers in
89 * the controller itself, unlike the s3c24xx SoC's which have these registers
90 * in the interrupt controller. Check if the port type is s3c64xx or higher.
92 static int s3c24xx_serial_has_interrupt_mask(struct uart_port
*port
)
94 return to_ourport(port
)->info
->type
== PORT_S3C6400
;
97 static void s3c24xx_serial_rx_enable(struct uart_port
*port
)
100 unsigned int ucon
, ufcon
;
103 spin_lock_irqsave(&port
->lock
, flags
);
105 while (--count
&& !s3c24xx_serial_txempty_nofifo(port
))
108 ufcon
= rd_regl(port
, S3C2410_UFCON
);
109 ufcon
|= S3C2410_UFCON_RESETRX
;
110 wr_regl(port
, S3C2410_UFCON
, ufcon
);
112 ucon
= rd_regl(port
, S3C2410_UCON
);
113 ucon
|= S3C2410_UCON_RXIRQMODE
;
114 wr_regl(port
, S3C2410_UCON
, ucon
);
116 rx_enabled(port
) = 1;
117 spin_unlock_irqrestore(&port
->lock
, flags
);
120 static void s3c24xx_serial_rx_disable(struct uart_port
*port
)
125 spin_lock_irqsave(&port
->lock
, flags
);
127 ucon
= rd_regl(port
, S3C2410_UCON
);
128 ucon
&= ~S3C2410_UCON_RXIRQMODE
;
129 wr_regl(port
, S3C2410_UCON
, ucon
);
131 rx_enabled(port
) = 0;
132 spin_unlock_irqrestore(&port
->lock
, flags
);
135 static void s3c24xx_serial_stop_tx(struct uart_port
*port
)
137 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
139 if (tx_enabled(port
)) {
140 if (s3c24xx_serial_has_interrupt_mask(port
))
141 __set_bit(S3C64XX_UINTM_TXD
,
142 portaddrl(port
, S3C64XX_UINTM
));
144 disable_irq_nosync(ourport
->tx_irq
);
145 tx_enabled(port
) = 0;
146 if (port
->flags
& UPF_CONS_FLOW
)
147 s3c24xx_serial_rx_enable(port
);
151 static void s3c24xx_serial_start_tx(struct uart_port
*port
)
153 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
155 if (!tx_enabled(port
)) {
156 if (port
->flags
& UPF_CONS_FLOW
)
157 s3c24xx_serial_rx_disable(port
);
159 if (s3c24xx_serial_has_interrupt_mask(port
))
160 __clear_bit(S3C64XX_UINTM_TXD
,
161 portaddrl(port
, S3C64XX_UINTM
));
163 enable_irq(ourport
->tx_irq
);
164 tx_enabled(port
) = 1;
168 static void s3c24xx_serial_stop_rx(struct uart_port
*port
)
170 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
172 if (rx_enabled(port
)) {
173 dbg("s3c24xx_serial_stop_rx: port=%p\n", port
);
174 if (s3c24xx_serial_has_interrupt_mask(port
))
175 __set_bit(S3C64XX_UINTM_RXD
,
176 portaddrl(port
, S3C64XX_UINTM
));
178 disable_irq_nosync(ourport
->rx_irq
);
179 rx_enabled(port
) = 0;
183 static void s3c24xx_serial_enable_ms(struct uart_port
*port
)
187 static inline struct s3c24xx_uart_info
*s3c24xx_port_to_info(struct uart_port
*port
)
189 return to_ourport(port
)->info
;
192 static inline struct s3c2410_uartcfg
*s3c24xx_port_to_cfg(struct uart_port
*port
)
194 struct s3c24xx_uart_port
*ourport
;
196 if (port
->dev
== NULL
)
199 ourport
= container_of(port
, struct s3c24xx_uart_port
, port
);
203 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port
*ourport
,
204 unsigned long ufstat
)
206 struct s3c24xx_uart_info
*info
= ourport
->info
;
208 if (ufstat
& info
->rx_fifofull
)
209 return ourport
->port
.fifosize
;
211 return (ufstat
& info
->rx_fifomask
) >> info
->rx_fifoshift
;
215 /* ? - where has parity gone?? */
216 #define S3C2410_UERSTAT_PARITY (0x1000)
219 s3c24xx_serial_rx_chars(int irq
, void *dev_id
)
221 struct s3c24xx_uart_port
*ourport
= dev_id
;
222 struct uart_port
*port
= &ourport
->port
;
223 unsigned int ufcon
, ch
, flag
, ufstat
, uerstat
;
227 spin_lock_irqsave(&port
->lock
, flags
);
229 while (max_count
-- > 0) {
230 ufcon
= rd_regl(port
, S3C2410_UFCON
);
231 ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
233 if (s3c24xx_serial_rx_fifocnt(ourport
, ufstat
) == 0)
236 uerstat
= rd_regl(port
, S3C2410_UERSTAT
);
237 ch
= rd_regb(port
, S3C2410_URXH
);
239 if (port
->flags
& UPF_CONS_FLOW
) {
240 int txe
= s3c24xx_serial_txempty_nofifo(port
);
242 if (rx_enabled(port
)) {
244 rx_enabled(port
) = 0;
249 ufcon
|= S3C2410_UFCON_RESETRX
;
250 wr_regl(port
, S3C2410_UFCON
, ufcon
);
251 rx_enabled(port
) = 1;
258 /* insert the character into the buffer */
263 if (unlikely(uerstat
& S3C2410_UERSTAT_ANY
)) {
264 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
267 /* check for break */
268 if (uerstat
& S3C2410_UERSTAT_BREAK
) {
271 if (uart_handle_break(port
))
275 if (uerstat
& S3C2410_UERSTAT_FRAME
)
276 port
->icount
.frame
++;
277 if (uerstat
& S3C2410_UERSTAT_OVERRUN
)
278 port
->icount
.overrun
++;
280 uerstat
&= port
->read_status_mask
;
282 if (uerstat
& S3C2410_UERSTAT_BREAK
)
284 else if (uerstat
& S3C2410_UERSTAT_PARITY
)
286 else if (uerstat
& (S3C2410_UERSTAT_FRAME
|
287 S3C2410_UERSTAT_OVERRUN
))
291 if (uart_handle_sysrq_char(port
, ch
))
294 uart_insert_char(port
, uerstat
, S3C2410_UERSTAT_OVERRUN
,
300 tty_flip_buffer_push(&port
->state
->port
);
303 spin_unlock_irqrestore(&port
->lock
, flags
);
307 static irqreturn_t
s3c24xx_serial_tx_chars(int irq
, void *id
)
309 struct s3c24xx_uart_port
*ourport
= id
;
310 struct uart_port
*port
= &ourport
->port
;
311 struct circ_buf
*xmit
= &port
->state
->xmit
;
315 spin_lock_irqsave(&port
->lock
, flags
);
318 wr_regb(port
, S3C2410_UTXH
, port
->x_char
);
324 /* if there isn't anything more to transmit, or the uart is now
325 * stopped, disable the uart and exit
328 if (uart_circ_empty(xmit
) || uart_tx_stopped(port
)) {
329 s3c24xx_serial_stop_tx(port
);
333 /* try and drain the buffer... */
335 while (!uart_circ_empty(xmit
) && count
-- > 0) {
336 if (rd_regl(port
, S3C2410_UFSTAT
) & ourport
->info
->tx_fifofull
)
339 wr_regb(port
, S3C2410_UTXH
, xmit
->buf
[xmit
->tail
]);
340 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
344 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
) {
345 spin_unlock(&port
->lock
);
346 uart_write_wakeup(port
);
347 spin_lock(&port
->lock
);
350 if (uart_circ_empty(xmit
))
351 s3c24xx_serial_stop_tx(port
);
354 spin_unlock_irqrestore(&port
->lock
, flags
);
358 /* interrupt handler for s3c64xx and later SoC's.*/
359 static irqreturn_t
s3c64xx_serial_handle_irq(int irq
, void *id
)
361 struct s3c24xx_uart_port
*ourport
= id
;
362 struct uart_port
*port
= &ourport
->port
;
363 unsigned int pend
= rd_regl(port
, S3C64XX_UINTP
);
364 irqreturn_t ret
= IRQ_HANDLED
;
366 if (pend
& S3C64XX_UINTM_RXD_MSK
) {
367 ret
= s3c24xx_serial_rx_chars(irq
, id
);
368 wr_regl(port
, S3C64XX_UINTP
, S3C64XX_UINTM_RXD_MSK
);
370 if (pend
& S3C64XX_UINTM_TXD_MSK
) {
371 ret
= s3c24xx_serial_tx_chars(irq
, id
);
372 wr_regl(port
, S3C64XX_UINTP
, S3C64XX_UINTM_TXD_MSK
);
377 static unsigned int s3c24xx_serial_tx_empty(struct uart_port
*port
)
379 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
380 unsigned long ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
381 unsigned long ufcon
= rd_regl(port
, S3C2410_UFCON
);
383 if (ufcon
& S3C2410_UFCON_FIFOMODE
) {
384 if ((ufstat
& info
->tx_fifomask
) != 0 ||
385 (ufstat
& info
->tx_fifofull
))
391 return s3c24xx_serial_txempty_nofifo(port
);
394 /* no modem control lines */
395 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port
*port
)
397 unsigned int umstat
= rd_regb(port
, S3C2410_UMSTAT
);
399 if (umstat
& S3C2410_UMSTAT_CTS
)
400 return TIOCM_CAR
| TIOCM_DSR
| TIOCM_CTS
;
402 return TIOCM_CAR
| TIOCM_DSR
;
405 static void s3c24xx_serial_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
407 /* todo - possibly remove AFC and do manual CTS */
410 static void s3c24xx_serial_break_ctl(struct uart_port
*port
, int break_state
)
415 spin_lock_irqsave(&port
->lock
, flags
);
417 ucon
= rd_regl(port
, S3C2410_UCON
);
420 ucon
|= S3C2410_UCON_SBREAK
;
422 ucon
&= ~S3C2410_UCON_SBREAK
;
424 wr_regl(port
, S3C2410_UCON
, ucon
);
426 spin_unlock_irqrestore(&port
->lock
, flags
);
429 static void s3c24xx_serial_shutdown(struct uart_port
*port
)
431 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
433 if (ourport
->tx_claimed
) {
434 if (!s3c24xx_serial_has_interrupt_mask(port
))
435 free_irq(ourport
->tx_irq
, ourport
);
436 tx_enabled(port
) = 0;
437 ourport
->tx_claimed
= 0;
440 if (ourport
->rx_claimed
) {
441 if (!s3c24xx_serial_has_interrupt_mask(port
))
442 free_irq(ourport
->rx_irq
, ourport
);
443 ourport
->rx_claimed
= 0;
444 rx_enabled(port
) = 0;
447 /* Clear pending interrupts and mask all interrupts */
448 if (s3c24xx_serial_has_interrupt_mask(port
)) {
449 free_irq(port
->irq
, ourport
);
451 wr_regl(port
, S3C64XX_UINTP
, 0xf);
452 wr_regl(port
, S3C64XX_UINTM
, 0xf);
456 static int s3c24xx_serial_startup(struct uart_port
*port
)
458 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
461 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
462 port
->mapbase
, port
->membase
);
464 rx_enabled(port
) = 1;
466 ret
= request_irq(ourport
->rx_irq
, s3c24xx_serial_rx_chars
, 0,
467 s3c24xx_serial_portname(port
), ourport
);
470 dev_err(port
->dev
, "cannot get irq %d\n", ourport
->rx_irq
);
474 ourport
->rx_claimed
= 1;
476 dbg("requesting tx irq...\n");
478 tx_enabled(port
) = 1;
480 ret
= request_irq(ourport
->tx_irq
, s3c24xx_serial_tx_chars
, 0,
481 s3c24xx_serial_portname(port
), ourport
);
484 dev_err(port
->dev
, "cannot get irq %d\n", ourport
->tx_irq
);
488 ourport
->tx_claimed
= 1;
490 dbg("s3c24xx_serial_startup ok\n");
492 /* the port reset code should have done the correct
493 * register setup for the port controls */
498 s3c24xx_serial_shutdown(port
);
502 static int s3c64xx_serial_startup(struct uart_port
*port
)
504 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
507 dbg("s3c64xx_serial_startup: port=%p (%08lx,%p)\n",
508 port
->mapbase
, port
->membase
);
510 wr_regl(port
, S3C64XX_UINTM
, 0xf);
512 ret
= request_irq(port
->irq
, s3c64xx_serial_handle_irq
, IRQF_SHARED
,
513 s3c24xx_serial_portname(port
), ourport
);
515 dev_err(port
->dev
, "cannot get irq %d\n", port
->irq
);
519 /* For compatibility with s3c24xx Soc's */
520 rx_enabled(port
) = 1;
521 ourport
->rx_claimed
= 1;
522 tx_enabled(port
) = 0;
523 ourport
->tx_claimed
= 1;
525 /* Enable Rx Interrupt */
526 __clear_bit(S3C64XX_UINTM_RXD
, portaddrl(port
, S3C64XX_UINTM
));
527 dbg("s3c64xx_serial_startup ok\n");
531 /* power power management control */
533 static void s3c24xx_serial_pm(struct uart_port
*port
, unsigned int level
,
536 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
538 ourport
->pm_level
= level
;
542 if (!IS_ERR(ourport
->baudclk
))
543 clk_disable_unprepare(ourport
->baudclk
);
545 clk_disable_unprepare(ourport
->clk
);
549 clk_prepare_enable(ourport
->clk
);
551 if (!IS_ERR(ourport
->baudclk
))
552 clk_prepare_enable(ourport
->baudclk
);
556 dev_err(port
->dev
, "s3c24xx_serial: unknown pm %d\n", level
);
560 /* baud rate calculation
562 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
563 * of different sources, including the peripheral clock ("pclk") and an
564 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
565 * with a programmable extra divisor.
567 * The following code goes through the clock sources, and calculates the
568 * baud clocks (and the resultant actual baud rates) and then tries to
569 * pick the closest one and select that.
573 #define MAX_CLK_NAME_LENGTH 15
575 static inline int s3c24xx_serial_getsource(struct uart_port
*port
)
577 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
580 if (info
->num_clks
== 1)
583 ucon
= rd_regl(port
, S3C2410_UCON
);
584 ucon
&= info
->clksel_mask
;
585 return ucon
>> info
->clksel_shift
;
588 static void s3c24xx_serial_setsource(struct uart_port
*port
,
589 unsigned int clk_sel
)
591 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
594 if (info
->num_clks
== 1)
597 ucon
= rd_regl(port
, S3C2410_UCON
);
598 if ((ucon
& info
->clksel_mask
) >> info
->clksel_shift
== clk_sel
)
601 ucon
&= ~info
->clksel_mask
;
602 ucon
|= clk_sel
<< info
->clksel_shift
;
603 wr_regl(port
, S3C2410_UCON
, ucon
);
606 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port
*ourport
,
607 unsigned int req_baud
, struct clk
**best_clk
,
608 unsigned int *clk_num
)
610 struct s3c24xx_uart_info
*info
= ourport
->info
;
613 unsigned int cnt
, baud
, quot
, clk_sel
, best_quot
= 0;
614 char clkname
[MAX_CLK_NAME_LENGTH
];
615 int calc_deviation
, deviation
= (1 << 30) - 1;
617 clk_sel
= (ourport
->cfg
->clk_sel
) ? ourport
->cfg
->clk_sel
:
618 ourport
->info
->def_clk_sel
;
619 for (cnt
= 0; cnt
< info
->num_clks
; cnt
++) {
620 if (!(clk_sel
& (1 << cnt
)))
623 sprintf(clkname
, "clk_uart_baud%d", cnt
);
624 clk
= clk_get(ourport
->port
.dev
, clkname
);
628 rate
= clk_get_rate(clk
);
632 if (ourport
->info
->has_divslot
) {
633 unsigned long div
= rate
/ req_baud
;
635 /* The UDIVSLOT register on the newer UARTs allows us to
636 * get a divisor adjustment of 1/16th on the baud clock.
638 * We don't keep the UDIVSLOT value (the 16ths we
639 * calculated by not multiplying the baud by 16) as it
640 * is easy enough to recalculate.
646 quot
= (rate
+ (8 * req_baud
)) / (16 * req_baud
);
647 baud
= rate
/ (quot
* 16);
651 calc_deviation
= req_baud
- baud
;
652 if (calc_deviation
< 0)
653 calc_deviation
= -calc_deviation
;
655 if (calc_deviation
< deviation
) {
659 deviation
= calc_deviation
;
668 * This table takes the fractional value of the baud divisor and gives
669 * the recommended setting for the UDIVSLOT register.
671 static u16 udivslot_table
[16] = {
690 static void s3c24xx_serial_set_termios(struct uart_port
*port
,
691 struct ktermios
*termios
,
692 struct ktermios
*old
)
694 struct s3c2410_uartcfg
*cfg
= s3c24xx_port_to_cfg(port
);
695 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
696 struct clk
*clk
= ERR_PTR(-EINVAL
);
698 unsigned int baud
, quot
, clk_sel
= 0;
701 unsigned int udivslot
= 0;
704 * We don't support modem control lines.
706 termios
->c_cflag
&= ~(HUPCL
| CMSPAR
);
707 termios
->c_cflag
|= CLOCAL
;
710 * Ask the core to calculate the divisor for us.
713 baud
= uart_get_baud_rate(port
, termios
, old
, 0, 115200*8);
714 quot
= s3c24xx_serial_getclk(ourport
, baud
, &clk
, &clk_sel
);
715 if (baud
== 38400 && (port
->flags
& UPF_SPD_MASK
) == UPF_SPD_CUST
)
716 quot
= port
->custom_divisor
;
720 /* check to see if we need to change clock source */
722 if (ourport
->baudclk
!= clk
) {
723 s3c24xx_serial_setsource(port
, clk_sel
);
725 if (!IS_ERR(ourport
->baudclk
)) {
726 clk_disable_unprepare(ourport
->baudclk
);
727 ourport
->baudclk
= ERR_PTR(-EINVAL
);
730 clk_prepare_enable(clk
);
732 ourport
->baudclk
= clk
;
733 ourport
->baudclk_rate
= clk
? clk_get_rate(clk
) : 0;
736 if (ourport
->info
->has_divslot
) {
737 unsigned int div
= ourport
->baudclk_rate
/ baud
;
739 if (cfg
->has_fracval
) {
740 udivslot
= (div
& 15);
741 dbg("fracval = %04x\n", udivslot
);
743 udivslot
= udivslot_table
[div
& 15];
744 dbg("udivslot = %04x (div %d)\n", udivslot
, div
& 15);
748 switch (termios
->c_cflag
& CSIZE
) {
750 dbg("config: 5bits/char\n");
751 ulcon
= S3C2410_LCON_CS5
;
754 dbg("config: 6bits/char\n");
755 ulcon
= S3C2410_LCON_CS6
;
758 dbg("config: 7bits/char\n");
759 ulcon
= S3C2410_LCON_CS7
;
763 dbg("config: 8bits/char\n");
764 ulcon
= S3C2410_LCON_CS8
;
768 /* preserve original lcon IR settings */
769 ulcon
|= (cfg
->ulcon
& S3C2410_LCON_IRM
);
771 if (termios
->c_cflag
& CSTOPB
)
772 ulcon
|= S3C2410_LCON_STOPB
;
774 umcon
= (termios
->c_cflag
& CRTSCTS
) ? S3C2410_UMCOM_AFC
: 0;
776 if (termios
->c_cflag
& PARENB
) {
777 if (termios
->c_cflag
& PARODD
)
778 ulcon
|= S3C2410_LCON_PODD
;
780 ulcon
|= S3C2410_LCON_PEVEN
;
782 ulcon
|= S3C2410_LCON_PNONE
;
785 spin_lock_irqsave(&port
->lock
, flags
);
787 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
788 ulcon
, quot
, udivslot
);
790 wr_regl(port
, S3C2410_ULCON
, ulcon
);
791 wr_regl(port
, S3C2410_UBRDIV
, quot
);
792 wr_regl(port
, S3C2410_UMCON
, umcon
);
794 if (ourport
->info
->has_divslot
)
795 wr_regl(port
, S3C2443_DIVSLOT
, udivslot
);
797 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
798 rd_regl(port
, S3C2410_ULCON
),
799 rd_regl(port
, S3C2410_UCON
),
800 rd_regl(port
, S3C2410_UFCON
));
803 * Update the per-port timeout.
805 uart_update_timeout(port
, termios
->c_cflag
, baud
);
808 * Which character status flags are we interested in?
810 port
->read_status_mask
= S3C2410_UERSTAT_OVERRUN
;
811 if (termios
->c_iflag
& INPCK
)
812 port
->read_status_mask
|= S3C2410_UERSTAT_FRAME
| S3C2410_UERSTAT_PARITY
;
815 * Which character status flags should we ignore?
817 port
->ignore_status_mask
= 0;
818 if (termios
->c_iflag
& IGNPAR
)
819 port
->ignore_status_mask
|= S3C2410_UERSTAT_OVERRUN
;
820 if (termios
->c_iflag
& IGNBRK
&& termios
->c_iflag
& IGNPAR
)
821 port
->ignore_status_mask
|= S3C2410_UERSTAT_FRAME
;
824 * Ignore all characters if CREAD is not set.
826 if ((termios
->c_cflag
& CREAD
) == 0)
827 port
->ignore_status_mask
|= RXSTAT_DUMMY_READ
;
829 spin_unlock_irqrestore(&port
->lock
, flags
);
832 static const char *s3c24xx_serial_type(struct uart_port
*port
)
834 switch (port
->type
) {
848 #define MAP_SIZE (0x100)
850 static void s3c24xx_serial_release_port(struct uart_port
*port
)
852 release_mem_region(port
->mapbase
, MAP_SIZE
);
855 static int s3c24xx_serial_request_port(struct uart_port
*port
)
857 const char *name
= s3c24xx_serial_portname(port
);
858 return request_mem_region(port
->mapbase
, MAP_SIZE
, name
) ? 0 : -EBUSY
;
861 static void s3c24xx_serial_config_port(struct uart_port
*port
, int flags
)
863 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
865 if (flags
& UART_CONFIG_TYPE
&&
866 s3c24xx_serial_request_port(port
) == 0)
867 port
->type
= info
->type
;
871 * verify the new serial_struct (for TIOCSSERIAL).
874 s3c24xx_serial_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
876 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
878 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= info
->type
)
885 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
887 static struct console s3c24xx_serial_console
;
889 static int __init
s3c24xx_serial_console_init(void)
891 register_console(&s3c24xx_serial_console
);
894 console_initcall(s3c24xx_serial_console_init
);
896 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
898 #define S3C24XX_SERIAL_CONSOLE NULL
901 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
902 static int s3c24xx_serial_get_poll_char(struct uart_port
*port
);
903 static void s3c24xx_serial_put_poll_char(struct uart_port
*port
,
907 static struct uart_ops s3c24xx_serial_ops
= {
908 .pm
= s3c24xx_serial_pm
,
909 .tx_empty
= s3c24xx_serial_tx_empty
,
910 .get_mctrl
= s3c24xx_serial_get_mctrl
,
911 .set_mctrl
= s3c24xx_serial_set_mctrl
,
912 .stop_tx
= s3c24xx_serial_stop_tx
,
913 .start_tx
= s3c24xx_serial_start_tx
,
914 .stop_rx
= s3c24xx_serial_stop_rx
,
915 .enable_ms
= s3c24xx_serial_enable_ms
,
916 .break_ctl
= s3c24xx_serial_break_ctl
,
917 .startup
= s3c24xx_serial_startup
,
918 .shutdown
= s3c24xx_serial_shutdown
,
919 .set_termios
= s3c24xx_serial_set_termios
,
920 .type
= s3c24xx_serial_type
,
921 .release_port
= s3c24xx_serial_release_port
,
922 .request_port
= s3c24xx_serial_request_port
,
923 .config_port
= s3c24xx_serial_config_port
,
924 .verify_port
= s3c24xx_serial_verify_port
,
925 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
926 .poll_get_char
= s3c24xx_serial_get_poll_char
,
927 .poll_put_char
= s3c24xx_serial_put_poll_char
,
931 static struct uart_driver s3c24xx_uart_drv
= {
932 .owner
= THIS_MODULE
,
933 .driver_name
= "s3c2410_serial",
934 .nr
= CONFIG_SERIAL_SAMSUNG_UARTS
,
935 .cons
= S3C24XX_SERIAL_CONSOLE
,
936 .dev_name
= S3C24XX_SERIAL_NAME
,
937 .major
= S3C24XX_SERIAL_MAJOR
,
938 .minor
= S3C24XX_SERIAL_MINOR
,
941 static struct s3c24xx_uart_port s3c24xx_serial_ports
[CONFIG_SERIAL_SAMSUNG_UARTS
] = {
944 .lock
= __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports
[0].port
.lock
),
948 .ops
= &s3c24xx_serial_ops
,
949 .flags
= UPF_BOOT_AUTOCONF
,
955 .lock
= __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports
[1].port
.lock
),
959 .ops
= &s3c24xx_serial_ops
,
960 .flags
= UPF_BOOT_AUTOCONF
,
964 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
968 .lock
= __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports
[2].port
.lock
),
972 .ops
= &s3c24xx_serial_ops
,
973 .flags
= UPF_BOOT_AUTOCONF
,
978 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
981 .lock
= __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports
[3].port
.lock
),
985 .ops
= &s3c24xx_serial_ops
,
986 .flags
= UPF_BOOT_AUTOCONF
,
993 /* s3c24xx_serial_resetport
995 * reset the fifos and other the settings.
998 static void s3c24xx_serial_resetport(struct uart_port
*port
,
999 struct s3c2410_uartcfg
*cfg
)
1001 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
1002 unsigned long ucon
= rd_regl(port
, S3C2410_UCON
);
1003 unsigned int ucon_mask
;
1005 ucon_mask
= info
->clksel_mask
;
1006 if (info
->type
== PORT_S3C2440
)
1007 ucon_mask
|= S3C2440_UCON0_DIVMASK
;
1010 wr_regl(port
, S3C2410_UCON
, ucon
| cfg
->ucon
);
1012 /* reset both fifos */
1013 wr_regl(port
, S3C2410_UFCON
, cfg
->ufcon
| S3C2410_UFCON_RESETBOTH
);
1014 wr_regl(port
, S3C2410_UFCON
, cfg
->ufcon
);
1016 /* some delay is required after fifo reset */
1021 #ifdef CONFIG_CPU_FREQ
1023 static int s3c24xx_serial_cpufreq_transition(struct notifier_block
*nb
,
1024 unsigned long val
, void *data
)
1026 struct s3c24xx_uart_port
*port
;
1027 struct uart_port
*uport
;
1029 port
= container_of(nb
, struct s3c24xx_uart_port
, freq_transition
);
1030 uport
= &port
->port
;
1032 /* check to see if port is enabled */
1034 if (port
->pm_level
!= 0)
1037 /* try and work out if the baudrate is changing, we can detect
1038 * a change in rate, but we do not have support for detecting
1039 * a disturbance in the clock-rate over the change.
1042 if (IS_ERR(port
->baudclk
))
1045 if (port
->baudclk_rate
== clk_get_rate(port
->baudclk
))
1048 if (val
== CPUFREQ_PRECHANGE
) {
1049 /* we should really shut the port down whilst the
1050 * frequency change is in progress. */
1052 } else if (val
== CPUFREQ_POSTCHANGE
) {
1053 struct ktermios
*termios
;
1054 struct tty_struct
*tty
;
1056 if (uport
->state
== NULL
)
1059 tty
= uport
->state
->port
.tty
;
1064 termios
= &tty
->termios
;
1066 if (termios
== NULL
) {
1067 dev_warn(uport
->dev
, "%s: no termios?\n", __func__
);
1071 s3c24xx_serial_set_termios(uport
, termios
, NULL
);
1078 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port
*port
)
1080 port
->freq_transition
.notifier_call
= s3c24xx_serial_cpufreq_transition
;
1082 return cpufreq_register_notifier(&port
->freq_transition
,
1083 CPUFREQ_TRANSITION_NOTIFIER
);
1086 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port
*port
)
1088 cpufreq_unregister_notifier(&port
->freq_transition
,
1089 CPUFREQ_TRANSITION_NOTIFIER
);
1093 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port
*port
)
1098 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port
*port
)
1103 /* s3c24xx_serial_init_port
1105 * initialise a single serial port from the platform device given
1108 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port
*ourport
,
1109 struct platform_device
*platdev
)
1111 struct uart_port
*port
= &ourport
->port
;
1112 struct s3c2410_uartcfg
*cfg
= ourport
->cfg
;
1113 struct resource
*res
;
1116 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port
, platdev
);
1118 if (platdev
== NULL
)
1121 if (port
->mapbase
!= 0)
1124 /* setup info for port */
1125 port
->dev
= &platdev
->dev
;
1127 /* Startup sequence is different for s3c64xx and higher SoC's */
1128 if (s3c24xx_serial_has_interrupt_mask(port
))
1129 s3c24xx_serial_ops
.startup
= s3c64xx_serial_startup
;
1133 if (cfg
->uart_flags
& UPF_CONS_FLOW
) {
1134 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1135 port
->flags
|= UPF_CONS_FLOW
;
1138 /* sort our the physical and virtual addresses for each UART */
1140 res
= platform_get_resource(platdev
, IORESOURCE_MEM
, 0);
1142 dev_err(port
->dev
, "failed to find memory resource for uart\n");
1146 dbg("resource %p (%lx..%lx)\n", res
, res
->start
, res
->end
);
1148 port
->membase
= devm_ioremap(port
->dev
, res
->start
, resource_size(res
));
1149 if (!port
->membase
) {
1150 dev_err(port
->dev
, "failed to remap controller address\n");
1154 port
->mapbase
= res
->start
;
1155 ret
= platform_get_irq(platdev
, 0);
1160 ourport
->rx_irq
= ret
;
1161 ourport
->tx_irq
= ret
+ 1;
1164 ret
= platform_get_irq(platdev
, 1);
1166 ourport
->tx_irq
= ret
;
1168 ourport
->clk
= clk_get(&platdev
->dev
, "uart");
1170 /* Keep all interrupts masked and cleared */
1171 if (s3c24xx_serial_has_interrupt_mask(port
)) {
1172 wr_regl(port
, S3C64XX_UINTM
, 0xf);
1173 wr_regl(port
, S3C64XX_UINTP
, 0xf);
1174 wr_regl(port
, S3C64XX_UINTSP
, 0xf);
1177 dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
1178 port
->mapbase
, port
->membase
, port
->irq
,
1179 ourport
->rx_irq
, ourport
->tx_irq
, port
->uartclk
);
1181 /* reset the fifos (and setup the uart) */
1182 s3c24xx_serial_resetport(port
, cfg
);
1186 #ifdef CONFIG_SAMSUNG_CLOCK
1187 static ssize_t
s3c24xx_serial_show_clksrc(struct device
*dev
,
1188 struct device_attribute
*attr
,
1191 struct uart_port
*port
= s3c24xx_dev_to_port(dev
);
1192 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
1194 if (IS_ERR(ourport
->baudclk
))
1197 return snprintf(buf
, PAGE_SIZE
, "* %s\n",
1198 ourport
->baudclk
->name
?: "(null)");
1201 static DEVICE_ATTR(clock_source
, S_IRUGO
, s3c24xx_serial_show_clksrc
, NULL
);
1204 /* Device driver serial port probe */
1206 static const struct of_device_id s3c24xx_uart_dt_match
[];
1207 static int probe_index
;
1209 static inline struct s3c24xx_serial_drv_data
*s3c24xx_get_driver_data(
1210 struct platform_device
*pdev
)
1213 if (pdev
->dev
.of_node
) {
1214 const struct of_device_id
*match
;
1215 match
= of_match_node(s3c24xx_uart_dt_match
, pdev
->dev
.of_node
);
1216 return (struct s3c24xx_serial_drv_data
*)match
->data
;
1219 return (struct s3c24xx_serial_drv_data
*)
1220 platform_get_device_id(pdev
)->driver_data
;
1223 static int s3c24xx_serial_probe(struct platform_device
*pdev
)
1225 struct s3c24xx_uart_port
*ourport
;
1228 dbg("s3c24xx_serial_probe(%p) %d\n", pdev
, probe_index
);
1230 ourport
= &s3c24xx_serial_ports
[probe_index
];
1232 ourport
->drv_data
= s3c24xx_get_driver_data(pdev
);
1233 if (!ourport
->drv_data
) {
1234 dev_err(&pdev
->dev
, "could not find driver data\n");
1238 ourport
->baudclk
= ERR_PTR(-EINVAL
);
1239 ourport
->info
= ourport
->drv_data
->info
;
1240 ourport
->cfg
= (pdev
->dev
.platform_data
) ?
1241 (struct s3c2410_uartcfg
*)pdev
->dev
.platform_data
:
1242 ourport
->drv_data
->def_cfg
;
1244 ourport
->port
.fifosize
= (ourport
->info
->fifosize
) ?
1245 ourport
->info
->fifosize
:
1246 ourport
->drv_data
->fifosize
[probe_index
];
1250 dbg("%s: initialising port %p...\n", __func__
, ourport
);
1252 ret
= s3c24xx_serial_init_port(ourport
, pdev
);
1256 dbg("%s: adding port\n", __func__
);
1257 uart_add_one_port(&s3c24xx_uart_drv
, &ourport
->port
);
1258 platform_set_drvdata(pdev
, &ourport
->port
);
1260 #ifdef CONFIG_SAMSUNG_CLOCK
1261 ret
= device_create_file(&pdev
->dev
, &dev_attr_clock_source
);
1263 dev_err(&pdev
->dev
, "failed to add clock source attr.\n");
1266 ret
= s3c24xx_serial_cpufreq_register(ourport
);
1268 dev_err(&pdev
->dev
, "failed to add cpufreq notifier\n");
1276 static int s3c24xx_serial_remove(struct platform_device
*dev
)
1278 struct uart_port
*port
= s3c24xx_dev_to_port(&dev
->dev
);
1281 s3c24xx_serial_cpufreq_deregister(to_ourport(port
));
1282 #ifdef CONFIG_SAMSUNG_CLOCK
1283 device_remove_file(&dev
->dev
, &dev_attr_clock_source
);
1285 uart_remove_one_port(&s3c24xx_uart_drv
, port
);
1291 /* UART power management code */
1292 #ifdef CONFIG_PM_SLEEP
1293 static int s3c24xx_serial_suspend(struct device
*dev
)
1295 struct uart_port
*port
= s3c24xx_dev_to_port(dev
);
1298 uart_suspend_port(&s3c24xx_uart_drv
, port
);
1303 static int s3c24xx_serial_resume(struct device
*dev
)
1305 struct uart_port
*port
= s3c24xx_dev_to_port(dev
);
1306 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
1309 clk_prepare_enable(ourport
->clk
);
1310 s3c24xx_serial_resetport(port
, s3c24xx_port_to_cfg(port
));
1311 clk_disable_unprepare(ourport
->clk
);
1313 uart_resume_port(&s3c24xx_uart_drv
, port
);
1319 static int s3c24xx_serial_resume_noirq(struct device
*dev
)
1321 struct uart_port
*port
= s3c24xx_dev_to_port(dev
);
1324 /* restore IRQ mask */
1325 if (s3c24xx_serial_has_interrupt_mask(port
)) {
1326 unsigned int uintm
= 0xf;
1327 if (tx_enabled(port
))
1328 uintm
&= ~S3C64XX_UINTM_TXD_MSK
;
1329 if (rx_enabled(port
))
1330 uintm
&= ~S3C64XX_UINTM_RXD_MSK
;
1331 wr_regl(port
, S3C64XX_UINTM
, uintm
);
1338 static const struct dev_pm_ops s3c24xx_serial_pm_ops
= {
1339 .suspend
= s3c24xx_serial_suspend
,
1340 .resume
= s3c24xx_serial_resume
,
1341 .resume_noirq
= s3c24xx_serial_resume_noirq
,
1343 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1345 #else /* !CONFIG_PM_SLEEP */
1347 #define SERIAL_SAMSUNG_PM_OPS NULL
1348 #endif /* CONFIG_PM_SLEEP */
1352 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1354 static struct uart_port
*cons_uart
;
1357 s3c24xx_serial_console_txrdy(struct uart_port
*port
, unsigned int ufcon
)
1359 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
1360 unsigned long ufstat
, utrstat
;
1362 if (ufcon
& S3C2410_UFCON_FIFOMODE
) {
1363 /* fifo mode - check amount of data in fifo registers... */
1365 ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
1366 return (ufstat
& info
->tx_fifofull
) ? 0 : 1;
1369 /* in non-fifo mode, we go and use the tx buffer empty */
1371 utrstat
= rd_regl(port
, S3C2410_UTRSTAT
);
1372 return (utrstat
& S3C2410_UTRSTAT_TXE
) ? 1 : 0;
1376 s3c24xx_port_configured(unsigned int ucon
)
1378 /* consider the serial port configured if the tx/rx mode set */
1379 return (ucon
& 0xf) != 0;
1382 #ifdef CONFIG_CONSOLE_POLL
1384 * Console polling routines for writing and reading from the uart while
1385 * in an interrupt or debug context.
1388 static int s3c24xx_serial_get_poll_char(struct uart_port
*port
)
1390 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
1391 unsigned int ufstat
;
1393 ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
1394 if (s3c24xx_serial_rx_fifocnt(ourport
, ufstat
) == 0)
1395 return NO_POLL_CHAR
;
1397 return rd_regb(port
, S3C2410_URXH
);
1400 static void s3c24xx_serial_put_poll_char(struct uart_port
*port
,
1403 unsigned int ufcon
= rd_regl(cons_uart
, S3C2410_UFCON
);
1404 unsigned int ucon
= rd_regl(cons_uart
, S3C2410_UCON
);
1406 /* not possible to xmit on unconfigured port */
1407 if (!s3c24xx_port_configured(ucon
))
1410 while (!s3c24xx_serial_console_txrdy(port
, ufcon
))
1412 wr_regb(cons_uart
, S3C2410_UTXH
, c
);
1415 #endif /* CONFIG_CONSOLE_POLL */
1418 s3c24xx_serial_console_putchar(struct uart_port
*port
, int ch
)
1420 unsigned int ufcon
= rd_regl(cons_uart
, S3C2410_UFCON
);
1421 unsigned int ucon
= rd_regl(cons_uart
, S3C2410_UCON
);
1423 /* not possible to xmit on unconfigured port */
1424 if (!s3c24xx_port_configured(ucon
))
1427 while (!s3c24xx_serial_console_txrdy(port
, ufcon
))
1429 wr_regb(cons_uart
, S3C2410_UTXH
, ch
);
1433 s3c24xx_serial_console_write(struct console
*co
, const char *s
,
1436 uart_console_write(cons_uart
, s
, count
, s3c24xx_serial_console_putchar
);
1440 s3c24xx_serial_get_options(struct uart_port
*port
, int *baud
,
1441 int *parity
, int *bits
)
1446 unsigned int ubrdiv
;
1448 unsigned int clk_sel
;
1449 char clk_name
[MAX_CLK_NAME_LENGTH
];
1451 ulcon
= rd_regl(port
, S3C2410_ULCON
);
1452 ucon
= rd_regl(port
, S3C2410_UCON
);
1453 ubrdiv
= rd_regl(port
, S3C2410_UBRDIV
);
1455 dbg("s3c24xx_serial_get_options: port=%p\n"
1456 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1457 port
, ulcon
, ucon
, ubrdiv
);
1459 if (s3c24xx_port_configured(ucon
)) {
1460 switch (ulcon
& S3C2410_LCON_CSMASK
) {
1461 case S3C2410_LCON_CS5
:
1464 case S3C2410_LCON_CS6
:
1467 case S3C2410_LCON_CS7
:
1471 case S3C2410_LCON_CS8
:
1476 switch (ulcon
& S3C2410_LCON_PMASK
) {
1477 case S3C2410_LCON_PEVEN
:
1481 case S3C2410_LCON_PODD
:
1485 case S3C2410_LCON_PNONE
:
1490 /* now calculate the baud rate */
1492 clk_sel
= s3c24xx_serial_getsource(port
);
1493 sprintf(clk_name
, "clk_uart_baud%d", clk_sel
);
1495 clk
= clk_get(port
->dev
, clk_name
);
1497 rate
= clk_get_rate(clk
);
1501 *baud
= rate
/ (16 * (ubrdiv
+ 1));
1502 dbg("calculated baud %d\n", *baud
);
1508 s3c24xx_serial_console_setup(struct console
*co
, char *options
)
1510 struct uart_port
*port
;
1516 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1517 co
, co
->index
, options
);
1519 /* is this a valid port */
1521 if (co
->index
== -1 || co
->index
>= CONFIG_SERIAL_SAMSUNG_UARTS
)
1524 port
= &s3c24xx_serial_ports
[co
->index
].port
;
1526 /* is the port configured? */
1528 if (port
->mapbase
== 0x0)
1533 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port
, co
->index
);
1536 * Check whether an invalid uart number has been specified, and
1537 * if so, search for the first available port that does have
1541 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1543 s3c24xx_serial_get_options(port
, &baud
, &parity
, &bits
);
1545 dbg("s3c24xx_serial_console_setup: baud %d\n", baud
);
1547 return uart_set_options(port
, co
, baud
, parity
, bits
, flow
);
1550 static struct console s3c24xx_serial_console
= {
1551 .name
= S3C24XX_SERIAL_NAME
,
1552 .device
= uart_console_device
,
1553 .flags
= CON_PRINTBUFFER
,
1555 .write
= s3c24xx_serial_console_write
,
1556 .setup
= s3c24xx_serial_console_setup
,
1557 .data
= &s3c24xx_uart_drv
,
1559 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1561 #ifdef CONFIG_CPU_S3C2410
1562 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data
= {
1563 .info
= &(struct s3c24xx_uart_info
) {
1564 .name
= "Samsung S3C2410 UART",
1565 .type
= PORT_S3C2410
,
1567 .rx_fifomask
= S3C2410_UFSTAT_RXMASK
,
1568 .rx_fifoshift
= S3C2410_UFSTAT_RXSHIFT
,
1569 .rx_fifofull
= S3C2410_UFSTAT_RXFULL
,
1570 .tx_fifofull
= S3C2410_UFSTAT_TXFULL
,
1571 .tx_fifomask
= S3C2410_UFSTAT_TXMASK
,
1572 .tx_fifoshift
= S3C2410_UFSTAT_TXSHIFT
,
1573 .def_clk_sel
= S3C2410_UCON_CLKSEL0
,
1575 .clksel_mask
= S3C2410_UCON_CLKMASK
,
1576 .clksel_shift
= S3C2410_UCON_CLKSHIFT
,
1578 .def_cfg
= &(struct s3c2410_uartcfg
) {
1579 .ucon
= S3C2410_UCON_DEFAULT
,
1580 .ufcon
= S3C2410_UFCON_DEFAULT
,
1583 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
1585 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1588 #ifdef CONFIG_CPU_S3C2412
1589 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data
= {
1590 .info
= &(struct s3c24xx_uart_info
) {
1591 .name
= "Samsung S3C2412 UART",
1592 .type
= PORT_S3C2412
,
1595 .rx_fifomask
= S3C2440_UFSTAT_RXMASK
,
1596 .rx_fifoshift
= S3C2440_UFSTAT_RXSHIFT
,
1597 .rx_fifofull
= S3C2440_UFSTAT_RXFULL
,
1598 .tx_fifofull
= S3C2440_UFSTAT_TXFULL
,
1599 .tx_fifomask
= S3C2440_UFSTAT_TXMASK
,
1600 .tx_fifoshift
= S3C2440_UFSTAT_TXSHIFT
,
1601 .def_clk_sel
= S3C2410_UCON_CLKSEL2
,
1603 .clksel_mask
= S3C2412_UCON_CLKMASK
,
1604 .clksel_shift
= S3C2412_UCON_CLKSHIFT
,
1606 .def_cfg
= &(struct s3c2410_uartcfg
) {
1607 .ucon
= S3C2410_UCON_DEFAULT
,
1608 .ufcon
= S3C2410_UFCON_DEFAULT
,
1611 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
1613 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1616 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
1617 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
1618 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data
= {
1619 .info
= &(struct s3c24xx_uart_info
) {
1620 .name
= "Samsung S3C2440 UART",
1621 .type
= PORT_S3C2440
,
1624 .rx_fifomask
= S3C2440_UFSTAT_RXMASK
,
1625 .rx_fifoshift
= S3C2440_UFSTAT_RXSHIFT
,
1626 .rx_fifofull
= S3C2440_UFSTAT_RXFULL
,
1627 .tx_fifofull
= S3C2440_UFSTAT_TXFULL
,
1628 .tx_fifomask
= S3C2440_UFSTAT_TXMASK
,
1629 .tx_fifoshift
= S3C2440_UFSTAT_TXSHIFT
,
1630 .def_clk_sel
= S3C2410_UCON_CLKSEL2
,
1632 .clksel_mask
= S3C2412_UCON_CLKMASK
,
1633 .clksel_shift
= S3C2412_UCON_CLKSHIFT
,
1635 .def_cfg
= &(struct s3c2410_uartcfg
) {
1636 .ucon
= S3C2410_UCON_DEFAULT
,
1637 .ufcon
= S3C2410_UFCON_DEFAULT
,
1640 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
1642 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1645 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || \
1646 defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450) || \
1647 defined(CONFIG_CPU_S5PC100)
1648 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data
= {
1649 .info
= &(struct s3c24xx_uart_info
) {
1650 .name
= "Samsung S3C6400 UART",
1651 .type
= PORT_S3C6400
,
1654 .rx_fifomask
= S3C2440_UFSTAT_RXMASK
,
1655 .rx_fifoshift
= S3C2440_UFSTAT_RXSHIFT
,
1656 .rx_fifofull
= S3C2440_UFSTAT_RXFULL
,
1657 .tx_fifofull
= S3C2440_UFSTAT_TXFULL
,
1658 .tx_fifomask
= S3C2440_UFSTAT_TXMASK
,
1659 .tx_fifoshift
= S3C2440_UFSTAT_TXSHIFT
,
1660 .def_clk_sel
= S3C2410_UCON_CLKSEL2
,
1662 .clksel_mask
= S3C6400_UCON_CLKMASK
,
1663 .clksel_shift
= S3C6400_UCON_CLKSHIFT
,
1665 .def_cfg
= &(struct s3c2410_uartcfg
) {
1666 .ucon
= S3C2410_UCON_DEFAULT
,
1667 .ufcon
= S3C2410_UFCON_DEFAULT
,
1670 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
1672 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1675 #ifdef CONFIG_CPU_S5PV210
1676 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data
= {
1677 .info
= &(struct s3c24xx_uart_info
) {
1678 .name
= "Samsung S5PV210 UART",
1679 .type
= PORT_S3C6400
,
1681 .rx_fifomask
= S5PV210_UFSTAT_RXMASK
,
1682 .rx_fifoshift
= S5PV210_UFSTAT_RXSHIFT
,
1683 .rx_fifofull
= S5PV210_UFSTAT_RXFULL
,
1684 .tx_fifofull
= S5PV210_UFSTAT_TXFULL
,
1685 .tx_fifomask
= S5PV210_UFSTAT_TXMASK
,
1686 .tx_fifoshift
= S5PV210_UFSTAT_TXSHIFT
,
1687 .def_clk_sel
= S3C2410_UCON_CLKSEL0
,
1689 .clksel_mask
= S5PV210_UCON_CLKMASK
,
1690 .clksel_shift
= S5PV210_UCON_CLKSHIFT
,
1692 .def_cfg
= &(struct s3c2410_uartcfg
) {
1693 .ucon
= S5PV210_UCON_DEFAULT
,
1694 .ufcon
= S5PV210_UFCON_DEFAULT
,
1696 .fifosize
= { 256, 64, 16, 16 },
1698 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
1700 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1703 #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) || \
1704 defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) || \
1705 defined(CONFIG_SOC_EXYNOS5440)
1706 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data
= {
1707 .info
= &(struct s3c24xx_uart_info
) {
1708 .name
= "Samsung Exynos4 UART",
1709 .type
= PORT_S3C6400
,
1711 .rx_fifomask
= S5PV210_UFSTAT_RXMASK
,
1712 .rx_fifoshift
= S5PV210_UFSTAT_RXSHIFT
,
1713 .rx_fifofull
= S5PV210_UFSTAT_RXFULL
,
1714 .tx_fifofull
= S5PV210_UFSTAT_TXFULL
,
1715 .tx_fifomask
= S5PV210_UFSTAT_TXMASK
,
1716 .tx_fifoshift
= S5PV210_UFSTAT_TXSHIFT
,
1717 .def_clk_sel
= S3C2410_UCON_CLKSEL0
,
1722 .def_cfg
= &(struct s3c2410_uartcfg
) {
1723 .ucon
= S5PV210_UCON_DEFAULT
,
1724 .ufcon
= S5PV210_UFCON_DEFAULT
,
1727 .fifosize
= { 256, 64, 16, 16 },
1729 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
1731 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1734 static struct platform_device_id s3c24xx_serial_driver_ids
[] = {
1736 .name
= "s3c2410-uart",
1737 .driver_data
= S3C2410_SERIAL_DRV_DATA
,
1739 .name
= "s3c2412-uart",
1740 .driver_data
= S3C2412_SERIAL_DRV_DATA
,
1742 .name
= "s3c2440-uart",
1743 .driver_data
= S3C2440_SERIAL_DRV_DATA
,
1745 .name
= "s3c6400-uart",
1746 .driver_data
= S3C6400_SERIAL_DRV_DATA
,
1748 .name
= "s5pv210-uart",
1749 .driver_data
= S5PV210_SERIAL_DRV_DATA
,
1751 .name
= "exynos4210-uart",
1752 .driver_data
= EXYNOS4210_SERIAL_DRV_DATA
,
1756 MODULE_DEVICE_TABLE(platform
, s3c24xx_serial_driver_ids
);
1759 static const struct of_device_id s3c24xx_uart_dt_match
[] = {
1760 { .compatible
= "samsung,s3c2410-uart",
1761 .data
= (void *)S3C2410_SERIAL_DRV_DATA
},
1762 { .compatible
= "samsung,s3c2412-uart",
1763 .data
= (void *)S3C2412_SERIAL_DRV_DATA
},
1764 { .compatible
= "samsung,s3c2440-uart",
1765 .data
= (void *)S3C2440_SERIAL_DRV_DATA
},
1766 { .compatible
= "samsung,s3c6400-uart",
1767 .data
= (void *)S3C6400_SERIAL_DRV_DATA
},
1768 { .compatible
= "samsung,s5pv210-uart",
1769 .data
= (void *)S5PV210_SERIAL_DRV_DATA
},
1770 { .compatible
= "samsung,exynos4210-uart",
1771 .data
= (void *)EXYNOS4210_SERIAL_DRV_DATA
},
1774 MODULE_DEVICE_TABLE(of
, s3c24xx_uart_dt_match
);
1777 static struct platform_driver samsung_serial_driver
= {
1778 .probe
= s3c24xx_serial_probe
,
1779 .remove
= s3c24xx_serial_remove
,
1780 .id_table
= s3c24xx_serial_driver_ids
,
1782 .name
= "samsung-uart",
1783 .owner
= THIS_MODULE
,
1784 .pm
= SERIAL_SAMSUNG_PM_OPS
,
1785 .of_match_table
= of_match_ptr(s3c24xx_uart_dt_match
),
1789 /* module initialisation code */
1791 static int __init
s3c24xx_serial_modinit(void)
1795 ret
= uart_register_driver(&s3c24xx_uart_drv
);
1797 pr_err("Failed to register Samsung UART driver\n");
1801 return platform_driver_register(&samsung_serial_driver
);
1804 static void __exit
s3c24xx_serial_modexit(void)
1806 platform_driver_unregister(&samsung_serial_driver
);
1807 uart_unregister_driver(&s3c24xx_uart_drv
);
1810 module_init(s3c24xx_serial_modinit
);
1811 module_exit(s3c24xx_serial_modexit
);
1813 MODULE_ALIAS("platform:samsung-uart");
1814 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1815 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1816 MODULE_LICENSE("GPL v2");