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serial: sh-sci: Fix crash in rx_timer_fn() on PIO fallback
[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / sh-sci.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 */
18 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19 #define SUPPORT_SYSRQ
20 #endif
21
22 #undef DEBUG
23
24 #include <linux/clk.h>
25 #include <linux/console.h>
26 #include <linux/ctype.h>
27 #include <linux/cpufreq.h>
28 #include <linux/delay.h>
29 #include <linux/dmaengine.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/err.h>
32 #include <linux/errno.h>
33 #include <linux/init.h>
34 #include <linux/interrupt.h>
35 #include <linux/ioport.h>
36 #include <linux/major.h>
37 #include <linux/module.h>
38 #include <linux/mm.h>
39 #include <linux/of.h>
40 #include <linux/of_device.h>
41 #include <linux/platform_device.h>
42 #include <linux/pm_runtime.h>
43 #include <linux/scatterlist.h>
44 #include <linux/serial.h>
45 #include <linux/serial_sci.h>
46 #include <linux/sh_dma.h>
47 #include <linux/slab.h>
48 #include <linux/string.h>
49 #include <linux/sysrq.h>
50 #include <linux/timer.h>
51 #include <linux/tty.h>
52 #include <linux/tty_flip.h>
53
54 #ifdef CONFIG_SUPERH
55 #include <asm/sh_bios.h>
56 #endif
57
58 #include "serial_mctrl_gpio.h"
59 #include "sh-sci.h"
60
61 /* Offsets into the sci_port->irqs array */
62 enum {
63 SCIx_ERI_IRQ,
64 SCIx_RXI_IRQ,
65 SCIx_TXI_IRQ,
66 SCIx_BRI_IRQ,
67 SCIx_NR_IRQS,
68
69 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
70 };
71
72 #define SCIx_IRQ_IS_MUXED(port) \
73 ((port)->irqs[SCIx_ERI_IRQ] == \
74 (port)->irqs[SCIx_RXI_IRQ]) || \
75 ((port)->irqs[SCIx_ERI_IRQ] && \
76 ((port)->irqs[SCIx_RXI_IRQ] < 0))
77
78 enum SCI_CLKS {
79 SCI_FCK, /* Functional Clock */
80 SCI_SCK, /* Optional External Clock */
81 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
82 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
83 SCI_NUM_CLKS
84 };
85
86 /* Bit x set means sampling rate x + 1 is supported */
87 #define SCI_SR(x) BIT((x) - 1)
88 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
89
90 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
91 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
92 SCI_SR(19) | SCI_SR(27)
93
94 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
95 #define max_sr(_port) fls((_port)->sampling_rate_mask)
96
97 /* Iterate over all supported sampling rates, from high to low */
98 #define for_each_sr(_sr, _port) \
99 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
100 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
101
102 struct plat_sci_reg {
103 u8 offset, size;
104 };
105
106 struct sci_port_params {
107 const struct plat_sci_reg regs[SCIx_NR_REGS];
108 unsigned int fifosize;
109 unsigned int overrun_reg;
110 unsigned int overrun_mask;
111 unsigned int sampling_rate_mask;
112 unsigned int error_mask;
113 unsigned int error_clear;
114 };
115
116 struct sci_port {
117 struct uart_port port;
118
119 /* Platform configuration */
120 const struct sci_port_params *params;
121 const struct plat_sci_port *cfg;
122 unsigned int sampling_rate_mask;
123 resource_size_t reg_size;
124 struct mctrl_gpios *gpios;
125
126 /* Clocks */
127 struct clk *clks[SCI_NUM_CLKS];
128 unsigned long clk_rates[SCI_NUM_CLKS];
129
130 int irqs[SCIx_NR_IRQS];
131 char *irqstr[SCIx_NR_IRQS];
132
133 struct dma_chan *chan_tx;
134 struct dma_chan *chan_rx;
135
136 #ifdef CONFIG_SERIAL_SH_SCI_DMA
137 dma_cookie_t cookie_tx;
138 dma_cookie_t cookie_rx[2];
139 dma_cookie_t active_rx;
140 dma_addr_t tx_dma_addr;
141 unsigned int tx_dma_len;
142 struct scatterlist sg_rx[2];
143 void *rx_buf[2];
144 size_t buf_len_rx;
145 struct work_struct work_tx;
146 struct timer_list rx_timer;
147 unsigned int rx_timeout;
148 #endif
149 unsigned int rx_frame;
150 int rx_trigger;
151 struct timer_list rx_fifo_timer;
152 int rx_fifo_timeout;
153 u16 hscif_tot;
154
155 bool has_rtscts;
156 bool autorts;
157 };
158
159 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
160
161 static struct sci_port sci_ports[SCI_NPORTS];
162 static struct uart_driver sci_uart_driver;
163
164 static inline struct sci_port *
165 to_sci_port(struct uart_port *uart)
166 {
167 return container_of(uart, struct sci_port, port);
168 }
169
170 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
171 /*
172 * Common SCI definitions, dependent on the port's regshift
173 * value.
174 */
175 [SCIx_SCI_REGTYPE] = {
176 .regs = {
177 [SCSMR] = { 0x00, 8 },
178 [SCBRR] = { 0x01, 8 },
179 [SCSCR] = { 0x02, 8 },
180 [SCxTDR] = { 0x03, 8 },
181 [SCxSR] = { 0x04, 8 },
182 [SCxRDR] = { 0x05, 8 },
183 },
184 .fifosize = 1,
185 .overrun_reg = SCxSR,
186 .overrun_mask = SCI_ORER,
187 .sampling_rate_mask = SCI_SR(32),
188 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
189 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
190 },
191
192 /*
193 * Common definitions for legacy IrDA ports.
194 */
195 [SCIx_IRDA_REGTYPE] = {
196 .regs = {
197 [SCSMR] = { 0x00, 8 },
198 [SCBRR] = { 0x02, 8 },
199 [SCSCR] = { 0x04, 8 },
200 [SCxTDR] = { 0x06, 8 },
201 [SCxSR] = { 0x08, 16 },
202 [SCxRDR] = { 0x0a, 8 },
203 [SCFCR] = { 0x0c, 8 },
204 [SCFDR] = { 0x0e, 16 },
205 },
206 .fifosize = 1,
207 .overrun_reg = SCxSR,
208 .overrun_mask = SCI_ORER,
209 .sampling_rate_mask = SCI_SR(32),
210 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
211 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
212 },
213
214 /*
215 * Common SCIFA definitions.
216 */
217 [SCIx_SCIFA_REGTYPE] = {
218 .regs = {
219 [SCSMR] = { 0x00, 16 },
220 [SCBRR] = { 0x04, 8 },
221 [SCSCR] = { 0x08, 16 },
222 [SCxTDR] = { 0x20, 8 },
223 [SCxSR] = { 0x14, 16 },
224 [SCxRDR] = { 0x24, 8 },
225 [SCFCR] = { 0x18, 16 },
226 [SCFDR] = { 0x1c, 16 },
227 [SCPCR] = { 0x30, 16 },
228 [SCPDR] = { 0x34, 16 },
229 },
230 .fifosize = 64,
231 .overrun_reg = SCxSR,
232 .overrun_mask = SCIFA_ORER,
233 .sampling_rate_mask = SCI_SR_SCIFAB,
234 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
235 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
236 },
237
238 /*
239 * Common SCIFB definitions.
240 */
241 [SCIx_SCIFB_REGTYPE] = {
242 .regs = {
243 [SCSMR] = { 0x00, 16 },
244 [SCBRR] = { 0x04, 8 },
245 [SCSCR] = { 0x08, 16 },
246 [SCxTDR] = { 0x40, 8 },
247 [SCxSR] = { 0x14, 16 },
248 [SCxRDR] = { 0x60, 8 },
249 [SCFCR] = { 0x18, 16 },
250 [SCTFDR] = { 0x38, 16 },
251 [SCRFDR] = { 0x3c, 16 },
252 [SCPCR] = { 0x30, 16 },
253 [SCPDR] = { 0x34, 16 },
254 },
255 .fifosize = 256,
256 .overrun_reg = SCxSR,
257 .overrun_mask = SCIFA_ORER,
258 .sampling_rate_mask = SCI_SR_SCIFAB,
259 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
260 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
261 },
262
263 /*
264 * Common SH-2(A) SCIF definitions for ports with FIFO data
265 * count registers.
266 */
267 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
268 .regs = {
269 [SCSMR] = { 0x00, 16 },
270 [SCBRR] = { 0x04, 8 },
271 [SCSCR] = { 0x08, 16 },
272 [SCxTDR] = { 0x0c, 8 },
273 [SCxSR] = { 0x10, 16 },
274 [SCxRDR] = { 0x14, 8 },
275 [SCFCR] = { 0x18, 16 },
276 [SCFDR] = { 0x1c, 16 },
277 [SCSPTR] = { 0x20, 16 },
278 [SCLSR] = { 0x24, 16 },
279 },
280 .fifosize = 16,
281 .overrun_reg = SCLSR,
282 .overrun_mask = SCLSR_ORER,
283 .sampling_rate_mask = SCI_SR(32),
284 .error_mask = SCIF_DEFAULT_ERROR_MASK,
285 .error_clear = SCIF_ERROR_CLEAR,
286 },
287
288 /*
289 * Common SH-3 SCIF definitions.
290 */
291 [SCIx_SH3_SCIF_REGTYPE] = {
292 .regs = {
293 [SCSMR] = { 0x00, 8 },
294 [SCBRR] = { 0x02, 8 },
295 [SCSCR] = { 0x04, 8 },
296 [SCxTDR] = { 0x06, 8 },
297 [SCxSR] = { 0x08, 16 },
298 [SCxRDR] = { 0x0a, 8 },
299 [SCFCR] = { 0x0c, 8 },
300 [SCFDR] = { 0x0e, 16 },
301 },
302 .fifosize = 16,
303 .overrun_reg = SCLSR,
304 .overrun_mask = SCLSR_ORER,
305 .sampling_rate_mask = SCI_SR(32),
306 .error_mask = SCIF_DEFAULT_ERROR_MASK,
307 .error_clear = SCIF_ERROR_CLEAR,
308 },
309
310 /*
311 * Common SH-4(A) SCIF(B) definitions.
312 */
313 [SCIx_SH4_SCIF_REGTYPE] = {
314 .regs = {
315 [SCSMR] = { 0x00, 16 },
316 [SCBRR] = { 0x04, 8 },
317 [SCSCR] = { 0x08, 16 },
318 [SCxTDR] = { 0x0c, 8 },
319 [SCxSR] = { 0x10, 16 },
320 [SCxRDR] = { 0x14, 8 },
321 [SCFCR] = { 0x18, 16 },
322 [SCFDR] = { 0x1c, 16 },
323 [SCSPTR] = { 0x20, 16 },
324 [SCLSR] = { 0x24, 16 },
325 },
326 .fifosize = 16,
327 .overrun_reg = SCLSR,
328 .overrun_mask = SCLSR_ORER,
329 .sampling_rate_mask = SCI_SR(32),
330 .error_mask = SCIF_DEFAULT_ERROR_MASK,
331 .error_clear = SCIF_ERROR_CLEAR,
332 },
333
334 /*
335 * Common SCIF definitions for ports with a Baud Rate Generator for
336 * External Clock (BRG).
337 */
338 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
339 .regs = {
340 [SCSMR] = { 0x00, 16 },
341 [SCBRR] = { 0x04, 8 },
342 [SCSCR] = { 0x08, 16 },
343 [SCxTDR] = { 0x0c, 8 },
344 [SCxSR] = { 0x10, 16 },
345 [SCxRDR] = { 0x14, 8 },
346 [SCFCR] = { 0x18, 16 },
347 [SCFDR] = { 0x1c, 16 },
348 [SCSPTR] = { 0x20, 16 },
349 [SCLSR] = { 0x24, 16 },
350 [SCDL] = { 0x30, 16 },
351 [SCCKS] = { 0x34, 16 },
352 },
353 .fifosize = 16,
354 .overrun_reg = SCLSR,
355 .overrun_mask = SCLSR_ORER,
356 .sampling_rate_mask = SCI_SR(32),
357 .error_mask = SCIF_DEFAULT_ERROR_MASK,
358 .error_clear = SCIF_ERROR_CLEAR,
359 },
360
361 /*
362 * Common HSCIF definitions.
363 */
364 [SCIx_HSCIF_REGTYPE] = {
365 .regs = {
366 [SCSMR] = { 0x00, 16 },
367 [SCBRR] = { 0x04, 8 },
368 [SCSCR] = { 0x08, 16 },
369 [SCxTDR] = { 0x0c, 8 },
370 [SCxSR] = { 0x10, 16 },
371 [SCxRDR] = { 0x14, 8 },
372 [SCFCR] = { 0x18, 16 },
373 [SCFDR] = { 0x1c, 16 },
374 [SCSPTR] = { 0x20, 16 },
375 [SCLSR] = { 0x24, 16 },
376 [HSSRR] = { 0x40, 16 },
377 [SCDL] = { 0x30, 16 },
378 [SCCKS] = { 0x34, 16 },
379 [HSRTRGR] = { 0x54, 16 },
380 [HSTTRGR] = { 0x58, 16 },
381 },
382 .fifosize = 128,
383 .overrun_reg = SCLSR,
384 .overrun_mask = SCLSR_ORER,
385 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
386 .error_mask = SCIF_DEFAULT_ERROR_MASK,
387 .error_clear = SCIF_ERROR_CLEAR,
388 },
389
390 /*
391 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
392 * register.
393 */
394 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
395 .regs = {
396 [SCSMR] = { 0x00, 16 },
397 [SCBRR] = { 0x04, 8 },
398 [SCSCR] = { 0x08, 16 },
399 [SCxTDR] = { 0x0c, 8 },
400 [SCxSR] = { 0x10, 16 },
401 [SCxRDR] = { 0x14, 8 },
402 [SCFCR] = { 0x18, 16 },
403 [SCFDR] = { 0x1c, 16 },
404 [SCLSR] = { 0x24, 16 },
405 },
406 .fifosize = 16,
407 .overrun_reg = SCLSR,
408 .overrun_mask = SCLSR_ORER,
409 .sampling_rate_mask = SCI_SR(32),
410 .error_mask = SCIF_DEFAULT_ERROR_MASK,
411 .error_clear = SCIF_ERROR_CLEAR,
412 },
413
414 /*
415 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
416 * count registers.
417 */
418 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
419 .regs = {
420 [SCSMR] = { 0x00, 16 },
421 [SCBRR] = { 0x04, 8 },
422 [SCSCR] = { 0x08, 16 },
423 [SCxTDR] = { 0x0c, 8 },
424 [SCxSR] = { 0x10, 16 },
425 [SCxRDR] = { 0x14, 8 },
426 [SCFCR] = { 0x18, 16 },
427 [SCFDR] = { 0x1c, 16 },
428 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
429 [SCRFDR] = { 0x20, 16 },
430 [SCSPTR] = { 0x24, 16 },
431 [SCLSR] = { 0x28, 16 },
432 },
433 .fifosize = 16,
434 .overrun_reg = SCLSR,
435 .overrun_mask = SCLSR_ORER,
436 .sampling_rate_mask = SCI_SR(32),
437 .error_mask = SCIF_DEFAULT_ERROR_MASK,
438 .error_clear = SCIF_ERROR_CLEAR,
439 },
440
441 /*
442 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
443 * registers.
444 */
445 [SCIx_SH7705_SCIF_REGTYPE] = {
446 .regs = {
447 [SCSMR] = { 0x00, 16 },
448 [SCBRR] = { 0x04, 8 },
449 [SCSCR] = { 0x08, 16 },
450 [SCxTDR] = { 0x20, 8 },
451 [SCxSR] = { 0x14, 16 },
452 [SCxRDR] = { 0x24, 8 },
453 [SCFCR] = { 0x18, 16 },
454 [SCFDR] = { 0x1c, 16 },
455 },
456 .fifosize = 64,
457 .overrun_reg = SCxSR,
458 .overrun_mask = SCIFA_ORER,
459 .sampling_rate_mask = SCI_SR(16),
460 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
461 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
462 },
463 };
464
465 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
466
467 /*
468 * The "offset" here is rather misleading, in that it refers to an enum
469 * value relative to the port mapping rather than the fixed offset
470 * itself, which needs to be manually retrieved from the platform's
471 * register map for the given port.
472 */
473 static unsigned int sci_serial_in(struct uart_port *p, int offset)
474 {
475 const struct plat_sci_reg *reg = sci_getreg(p, offset);
476
477 if (reg->size == 8)
478 return ioread8(p->membase + (reg->offset << p->regshift));
479 else if (reg->size == 16)
480 return ioread16(p->membase + (reg->offset << p->regshift));
481 else
482 WARN(1, "Invalid register access\n");
483
484 return 0;
485 }
486
487 static void sci_serial_out(struct uart_port *p, int offset, int value)
488 {
489 const struct plat_sci_reg *reg = sci_getreg(p, offset);
490
491 if (reg->size == 8)
492 iowrite8(value, p->membase + (reg->offset << p->regshift));
493 else if (reg->size == 16)
494 iowrite16(value, p->membase + (reg->offset << p->regshift));
495 else
496 WARN(1, "Invalid register access\n");
497 }
498
499 static void sci_port_enable(struct sci_port *sci_port)
500 {
501 unsigned int i;
502
503 if (!sci_port->port.dev)
504 return;
505
506 pm_runtime_get_sync(sci_port->port.dev);
507
508 for (i = 0; i < SCI_NUM_CLKS; i++) {
509 clk_prepare_enable(sci_port->clks[i]);
510 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
511 }
512 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
513 }
514
515 static void sci_port_disable(struct sci_port *sci_port)
516 {
517 unsigned int i;
518
519 if (!sci_port->port.dev)
520 return;
521
522 for (i = SCI_NUM_CLKS; i-- > 0; )
523 clk_disable_unprepare(sci_port->clks[i]);
524
525 pm_runtime_put_sync(sci_port->port.dev);
526 }
527
528 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
529 {
530 /*
531 * Not all ports (such as SCIFA) will support REIE. Rather than
532 * special-casing the port type, we check the port initialization
533 * IRQ enable mask to see whether the IRQ is desired at all. If
534 * it's unset, it's logically inferred that there's no point in
535 * testing for it.
536 */
537 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
538 }
539
540 static void sci_start_tx(struct uart_port *port)
541 {
542 struct sci_port *s = to_sci_port(port);
543 unsigned short ctrl;
544
545 #ifdef CONFIG_SERIAL_SH_SCI_DMA
546 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
547 u16 new, scr = serial_port_in(port, SCSCR);
548 if (s->chan_tx)
549 new = scr | SCSCR_TDRQE;
550 else
551 new = scr & ~SCSCR_TDRQE;
552 if (new != scr)
553 serial_port_out(port, SCSCR, new);
554 }
555
556 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
557 dma_submit_error(s->cookie_tx)) {
558 s->cookie_tx = 0;
559 schedule_work(&s->work_tx);
560 }
561 #endif
562
563 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
564 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
565 ctrl = serial_port_in(port, SCSCR);
566 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
567 }
568 }
569
570 static void sci_stop_tx(struct uart_port *port)
571 {
572 unsigned short ctrl;
573
574 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
575 ctrl = serial_port_in(port, SCSCR);
576
577 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
578 ctrl &= ~SCSCR_TDRQE;
579
580 ctrl &= ~SCSCR_TIE;
581
582 serial_port_out(port, SCSCR, ctrl);
583 }
584
585 static void sci_start_rx(struct uart_port *port)
586 {
587 unsigned short ctrl;
588
589 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
590
591 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
592 ctrl &= ~SCSCR_RDRQE;
593
594 serial_port_out(port, SCSCR, ctrl);
595 }
596
597 static void sci_stop_rx(struct uart_port *port)
598 {
599 unsigned short ctrl;
600
601 ctrl = serial_port_in(port, SCSCR);
602
603 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
604 ctrl &= ~SCSCR_RDRQE;
605
606 ctrl &= ~port_rx_irq_mask(port);
607
608 serial_port_out(port, SCSCR, ctrl);
609 }
610
611 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
612 {
613 if (port->type == PORT_SCI) {
614 /* Just store the mask */
615 serial_port_out(port, SCxSR, mask);
616 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
617 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
618 /* Only clear the status bits we want to clear */
619 serial_port_out(port, SCxSR,
620 serial_port_in(port, SCxSR) & mask);
621 } else {
622 /* Store the mask, clear parity/framing errors */
623 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
624 }
625 }
626
627 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
628 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
629
630 #ifdef CONFIG_CONSOLE_POLL
631 static int sci_poll_get_char(struct uart_port *port)
632 {
633 unsigned short status;
634 int c;
635
636 do {
637 status = serial_port_in(port, SCxSR);
638 if (status & SCxSR_ERRORS(port)) {
639 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
640 continue;
641 }
642 break;
643 } while (1);
644
645 if (!(status & SCxSR_RDxF(port)))
646 return NO_POLL_CHAR;
647
648 c = serial_port_in(port, SCxRDR);
649
650 /* Dummy read */
651 serial_port_in(port, SCxSR);
652 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
653
654 return c;
655 }
656 #endif
657
658 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
659 {
660 unsigned short status;
661
662 do {
663 status = serial_port_in(port, SCxSR);
664 } while (!(status & SCxSR_TDxE(port)));
665
666 serial_port_out(port, SCxTDR, c);
667 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
668 }
669 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
670 CONFIG_SERIAL_SH_SCI_EARLYCON */
671
672 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
673 {
674 struct sci_port *s = to_sci_port(port);
675
676 /*
677 * Use port-specific handler if provided.
678 */
679 if (s->cfg->ops && s->cfg->ops->init_pins) {
680 s->cfg->ops->init_pins(port, cflag);
681 return;
682 }
683
684 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
685 u16 data = serial_port_in(port, SCPDR);
686 u16 ctrl = serial_port_in(port, SCPCR);
687
688 /* Enable RXD and TXD pin functions */
689 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
690 if (to_sci_port(port)->has_rtscts) {
691 /* RTS# is output, active low, unless autorts */
692 if (!(port->mctrl & TIOCM_RTS)) {
693 ctrl |= SCPCR_RTSC;
694 data |= SCPDR_RTSD;
695 } else if (!s->autorts) {
696 ctrl |= SCPCR_RTSC;
697 data &= ~SCPDR_RTSD;
698 } else {
699 /* Enable RTS# pin function */
700 ctrl &= ~SCPCR_RTSC;
701 }
702 /* Enable CTS# pin function */
703 ctrl &= ~SCPCR_CTSC;
704 }
705 serial_port_out(port, SCPDR, data);
706 serial_port_out(port, SCPCR, ctrl);
707 } else if (sci_getreg(port, SCSPTR)->size) {
708 u16 status = serial_port_in(port, SCSPTR);
709
710 /* RTS# is always output; and active low, unless autorts */
711 status |= SCSPTR_RTSIO;
712 if (!(port->mctrl & TIOCM_RTS))
713 status |= SCSPTR_RTSDT;
714 else if (!s->autorts)
715 status &= ~SCSPTR_RTSDT;
716 /* CTS# and SCK are inputs */
717 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
718 serial_port_out(port, SCSPTR, status);
719 }
720 }
721
722 static int sci_txfill(struct uart_port *port)
723 {
724 struct sci_port *s = to_sci_port(port);
725 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
726 const struct plat_sci_reg *reg;
727
728 reg = sci_getreg(port, SCTFDR);
729 if (reg->size)
730 return serial_port_in(port, SCTFDR) & fifo_mask;
731
732 reg = sci_getreg(port, SCFDR);
733 if (reg->size)
734 return serial_port_in(port, SCFDR) >> 8;
735
736 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
737 }
738
739 static int sci_txroom(struct uart_port *port)
740 {
741 return port->fifosize - sci_txfill(port);
742 }
743
744 static int sci_rxfill(struct uart_port *port)
745 {
746 struct sci_port *s = to_sci_port(port);
747 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
748 const struct plat_sci_reg *reg;
749
750 reg = sci_getreg(port, SCRFDR);
751 if (reg->size)
752 return serial_port_in(port, SCRFDR) & fifo_mask;
753
754 reg = sci_getreg(port, SCFDR);
755 if (reg->size)
756 return serial_port_in(port, SCFDR) & fifo_mask;
757
758 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
759 }
760
761 /* ********************************************************************** *
762 * the interrupt related routines *
763 * ********************************************************************** */
764
765 static void sci_transmit_chars(struct uart_port *port)
766 {
767 struct circ_buf *xmit = &port->state->xmit;
768 unsigned int stopped = uart_tx_stopped(port);
769 unsigned short status;
770 unsigned short ctrl;
771 int count;
772
773 status = serial_port_in(port, SCxSR);
774 if (!(status & SCxSR_TDxE(port))) {
775 ctrl = serial_port_in(port, SCSCR);
776 if (uart_circ_empty(xmit))
777 ctrl &= ~SCSCR_TIE;
778 else
779 ctrl |= SCSCR_TIE;
780 serial_port_out(port, SCSCR, ctrl);
781 return;
782 }
783
784 count = sci_txroom(port);
785
786 do {
787 unsigned char c;
788
789 if (port->x_char) {
790 c = port->x_char;
791 port->x_char = 0;
792 } else if (!uart_circ_empty(xmit) && !stopped) {
793 c = xmit->buf[xmit->tail];
794 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
795 } else {
796 break;
797 }
798
799 serial_port_out(port, SCxTDR, c);
800
801 port->icount.tx++;
802 } while (--count > 0);
803
804 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
805
806 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
807 uart_write_wakeup(port);
808 if (uart_circ_empty(xmit))
809 sci_stop_tx(port);
810
811 }
812
813 /* On SH3, SCIF may read end-of-break as a space->mark char */
814 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
815
816 static void sci_receive_chars(struct uart_port *port)
817 {
818 struct tty_port *tport = &port->state->port;
819 int i, count, copied = 0;
820 unsigned short status;
821 unsigned char flag;
822
823 status = serial_port_in(port, SCxSR);
824 if (!(status & SCxSR_RDxF(port)))
825 return;
826
827 while (1) {
828 /* Don't copy more bytes than there is room for in the buffer */
829 count = tty_buffer_request_room(tport, sci_rxfill(port));
830
831 /* If for any reason we can't copy more data, we're done! */
832 if (count == 0)
833 break;
834
835 if (port->type == PORT_SCI) {
836 char c = serial_port_in(port, SCxRDR);
837 if (uart_handle_sysrq_char(port, c))
838 count = 0;
839 else
840 tty_insert_flip_char(tport, c, TTY_NORMAL);
841 } else {
842 for (i = 0; i < count; i++) {
843 char c = serial_port_in(port, SCxRDR);
844
845 status = serial_port_in(port, SCxSR);
846 if (uart_handle_sysrq_char(port, c)) {
847 count--; i--;
848 continue;
849 }
850
851 /* Store data and status */
852 if (status & SCxSR_FER(port)) {
853 flag = TTY_FRAME;
854 port->icount.frame++;
855 dev_notice(port->dev, "frame error\n");
856 } else if (status & SCxSR_PER(port)) {
857 flag = TTY_PARITY;
858 port->icount.parity++;
859 dev_notice(port->dev, "parity error\n");
860 } else
861 flag = TTY_NORMAL;
862
863 tty_insert_flip_char(tport, c, flag);
864 }
865 }
866
867 serial_port_in(port, SCxSR); /* dummy read */
868 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
869
870 copied += count;
871 port->icount.rx += count;
872 }
873
874 if (copied) {
875 /* Tell the rest of the system the news. New characters! */
876 tty_flip_buffer_push(tport);
877 } else {
878 /* TTY buffers full; read from RX reg to prevent lockup */
879 serial_port_in(port, SCxRDR);
880 serial_port_in(port, SCxSR); /* dummy read */
881 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
882 }
883 }
884
885 static int sci_handle_errors(struct uart_port *port)
886 {
887 int copied = 0;
888 unsigned short status = serial_port_in(port, SCxSR);
889 struct tty_port *tport = &port->state->port;
890 struct sci_port *s = to_sci_port(port);
891
892 /* Handle overruns */
893 if (status & s->params->overrun_mask) {
894 port->icount.overrun++;
895
896 /* overrun error */
897 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
898 copied++;
899
900 dev_notice(port->dev, "overrun error\n");
901 }
902
903 if (status & SCxSR_FER(port)) {
904 /* frame error */
905 port->icount.frame++;
906
907 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
908 copied++;
909
910 dev_notice(port->dev, "frame error\n");
911 }
912
913 if (status & SCxSR_PER(port)) {
914 /* parity error */
915 port->icount.parity++;
916
917 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
918 copied++;
919
920 dev_notice(port->dev, "parity error\n");
921 }
922
923 if (copied)
924 tty_flip_buffer_push(tport);
925
926 return copied;
927 }
928
929 static int sci_handle_fifo_overrun(struct uart_port *port)
930 {
931 struct tty_port *tport = &port->state->port;
932 struct sci_port *s = to_sci_port(port);
933 const struct plat_sci_reg *reg;
934 int copied = 0;
935 u16 status;
936
937 reg = sci_getreg(port, s->params->overrun_reg);
938 if (!reg->size)
939 return 0;
940
941 status = serial_port_in(port, s->params->overrun_reg);
942 if (status & s->params->overrun_mask) {
943 status &= ~s->params->overrun_mask;
944 serial_port_out(port, s->params->overrun_reg, status);
945
946 port->icount.overrun++;
947
948 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
949 tty_flip_buffer_push(tport);
950
951 dev_dbg(port->dev, "overrun error\n");
952 copied++;
953 }
954
955 return copied;
956 }
957
958 static int sci_handle_breaks(struct uart_port *port)
959 {
960 int copied = 0;
961 unsigned short status = serial_port_in(port, SCxSR);
962 struct tty_port *tport = &port->state->port;
963
964 if (uart_handle_break(port))
965 return 0;
966
967 if (status & SCxSR_BRK(port)) {
968 port->icount.brk++;
969
970 /* Notify of BREAK */
971 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
972 copied++;
973
974 dev_dbg(port->dev, "BREAK detected\n");
975 }
976
977 if (copied)
978 tty_flip_buffer_push(tport);
979
980 copied += sci_handle_fifo_overrun(port);
981
982 return copied;
983 }
984
985 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
986 {
987 unsigned int bits;
988
989 if (rx_trig < 1)
990 rx_trig = 1;
991 if (rx_trig >= port->fifosize)
992 rx_trig = port->fifosize;
993
994 /* HSCIF can be set to an arbitrary level. */
995 if (sci_getreg(port, HSRTRGR)->size) {
996 serial_port_out(port, HSRTRGR, rx_trig);
997 return rx_trig;
998 }
999
1000 switch (port->type) {
1001 case PORT_SCIF:
1002 if (rx_trig < 4) {
1003 bits = 0;
1004 rx_trig = 1;
1005 } else if (rx_trig < 8) {
1006 bits = SCFCR_RTRG0;
1007 rx_trig = 4;
1008 } else if (rx_trig < 14) {
1009 bits = SCFCR_RTRG1;
1010 rx_trig = 8;
1011 } else {
1012 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1013 rx_trig = 14;
1014 }
1015 break;
1016 case PORT_SCIFA:
1017 case PORT_SCIFB:
1018 if (rx_trig < 16) {
1019 bits = 0;
1020 rx_trig = 1;
1021 } else if (rx_trig < 32) {
1022 bits = SCFCR_RTRG0;
1023 rx_trig = 16;
1024 } else if (rx_trig < 48) {
1025 bits = SCFCR_RTRG1;
1026 rx_trig = 32;
1027 } else {
1028 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1029 rx_trig = 48;
1030 }
1031 break;
1032 default:
1033 WARN(1, "unknown FIFO configuration");
1034 return 1;
1035 }
1036
1037 serial_port_out(port, SCFCR,
1038 (serial_port_in(port, SCFCR) &
1039 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1040
1041 return rx_trig;
1042 }
1043
1044 static int scif_rtrg_enabled(struct uart_port *port)
1045 {
1046 if (sci_getreg(port, HSRTRGR)->size)
1047 return serial_port_in(port, HSRTRGR) != 0;
1048 else
1049 return (serial_port_in(port, SCFCR) &
1050 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1051 }
1052
1053 static void rx_fifo_timer_fn(struct timer_list *t)
1054 {
1055 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1056 struct uart_port *port = &s->port;
1057
1058 dev_dbg(port->dev, "Rx timed out\n");
1059 scif_set_rtrg(port, 1);
1060 }
1061
1062 static ssize_t rx_trigger_show(struct device *dev,
1063 struct device_attribute *attr,
1064 char *buf)
1065 {
1066 struct uart_port *port = dev_get_drvdata(dev);
1067 struct sci_port *sci = to_sci_port(port);
1068
1069 return sprintf(buf, "%d\n", sci->rx_trigger);
1070 }
1071
1072 static ssize_t rx_trigger_store(struct device *dev,
1073 struct device_attribute *attr,
1074 const char *buf,
1075 size_t count)
1076 {
1077 struct uart_port *port = dev_get_drvdata(dev);
1078 struct sci_port *sci = to_sci_port(port);
1079 int ret;
1080 long r;
1081
1082 ret = kstrtol(buf, 0, &r);
1083 if (ret)
1084 return ret;
1085
1086 sci->rx_trigger = scif_set_rtrg(port, r);
1087 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1088 scif_set_rtrg(port, 1);
1089
1090 return count;
1091 }
1092
1093 static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store);
1094
1095 static ssize_t rx_fifo_timeout_show(struct device *dev,
1096 struct device_attribute *attr,
1097 char *buf)
1098 {
1099 struct uart_port *port = dev_get_drvdata(dev);
1100 struct sci_port *sci = to_sci_port(port);
1101 int v;
1102
1103 if (port->type == PORT_HSCIF)
1104 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1105 else
1106 v = sci->rx_fifo_timeout;
1107
1108 return sprintf(buf, "%d\n", v);
1109 }
1110
1111 static ssize_t rx_fifo_timeout_store(struct device *dev,
1112 struct device_attribute *attr,
1113 const char *buf,
1114 size_t count)
1115 {
1116 struct uart_port *port = dev_get_drvdata(dev);
1117 struct sci_port *sci = to_sci_port(port);
1118 int ret;
1119 long r;
1120
1121 ret = kstrtol(buf, 0, &r);
1122 if (ret)
1123 return ret;
1124
1125 if (port->type == PORT_HSCIF) {
1126 if (r < 0 || r > 3)
1127 return -EINVAL;
1128 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1129 } else {
1130 sci->rx_fifo_timeout = r;
1131 scif_set_rtrg(port, 1);
1132 if (r > 0)
1133 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1134 }
1135
1136 return count;
1137 }
1138
1139 static DEVICE_ATTR_RW(rx_fifo_timeout);
1140
1141
1142 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1143 static void sci_dma_tx_complete(void *arg)
1144 {
1145 struct sci_port *s = arg;
1146 struct uart_port *port = &s->port;
1147 struct circ_buf *xmit = &port->state->xmit;
1148 unsigned long flags;
1149
1150 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1151
1152 spin_lock_irqsave(&port->lock, flags);
1153
1154 xmit->tail += s->tx_dma_len;
1155 xmit->tail &= UART_XMIT_SIZE - 1;
1156
1157 port->icount.tx += s->tx_dma_len;
1158
1159 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1160 uart_write_wakeup(port);
1161
1162 if (!uart_circ_empty(xmit)) {
1163 s->cookie_tx = 0;
1164 schedule_work(&s->work_tx);
1165 } else {
1166 s->cookie_tx = -EINVAL;
1167 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1168 u16 ctrl = serial_port_in(port, SCSCR);
1169 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1170 }
1171 }
1172
1173 spin_unlock_irqrestore(&port->lock, flags);
1174 }
1175
1176 /* Locking: called with port lock held */
1177 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1178 {
1179 struct uart_port *port = &s->port;
1180 struct tty_port *tport = &port->state->port;
1181 int copied;
1182
1183 copied = tty_insert_flip_string(tport, buf, count);
1184 if (copied < count)
1185 port->icount.buf_overrun++;
1186
1187 port->icount.rx += copied;
1188
1189 return copied;
1190 }
1191
1192 static int sci_dma_rx_find_active(struct sci_port *s)
1193 {
1194 unsigned int i;
1195
1196 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1197 if (s->active_rx == s->cookie_rx[i])
1198 return i;
1199
1200 return -1;
1201 }
1202
1203 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1204 {
1205 struct dma_chan *chan = s->chan_rx;
1206 struct uart_port *port = &s->port;
1207 unsigned long flags;
1208
1209 spin_lock_irqsave(&port->lock, flags);
1210 s->chan_rx = NULL;
1211 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1212 spin_unlock_irqrestore(&port->lock, flags);
1213 dmaengine_terminate_all(chan);
1214 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1215 sg_dma_address(&s->sg_rx[0]));
1216 dma_release_channel(chan);
1217 if (enable_pio) {
1218 spin_lock_irqsave(&port->lock, flags);
1219 sci_start_rx(port);
1220 spin_unlock_irqrestore(&port->lock, flags);
1221 }
1222 }
1223
1224 static void sci_dma_rx_complete(void *arg)
1225 {
1226 struct sci_port *s = arg;
1227 struct dma_chan *chan = s->chan_rx;
1228 struct uart_port *port = &s->port;
1229 struct dma_async_tx_descriptor *desc;
1230 unsigned long flags;
1231 int active, count = 0;
1232
1233 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1234 s->active_rx);
1235
1236 spin_lock_irqsave(&port->lock, flags);
1237
1238 active = sci_dma_rx_find_active(s);
1239 if (active >= 0)
1240 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1241
1242 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1243
1244 if (count)
1245 tty_flip_buffer_push(&port->state->port);
1246
1247 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1248 DMA_DEV_TO_MEM,
1249 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1250 if (!desc)
1251 goto fail;
1252
1253 desc->callback = sci_dma_rx_complete;
1254 desc->callback_param = s;
1255 s->cookie_rx[active] = dmaengine_submit(desc);
1256 if (dma_submit_error(s->cookie_rx[active]))
1257 goto fail;
1258
1259 s->active_rx = s->cookie_rx[!active];
1260
1261 dma_async_issue_pending(chan);
1262
1263 spin_unlock_irqrestore(&port->lock, flags);
1264 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1265 __func__, s->cookie_rx[active], active, s->active_rx);
1266 return;
1267
1268 fail:
1269 spin_unlock_irqrestore(&port->lock, flags);
1270 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1271 sci_rx_dma_release(s, true);
1272 }
1273
1274 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1275 {
1276 struct dma_chan *chan = s->chan_tx;
1277 struct uart_port *port = &s->port;
1278 unsigned long flags;
1279
1280 spin_lock_irqsave(&port->lock, flags);
1281 s->chan_tx = NULL;
1282 s->cookie_tx = -EINVAL;
1283 spin_unlock_irqrestore(&port->lock, flags);
1284 dmaengine_terminate_all(chan);
1285 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1286 DMA_TO_DEVICE);
1287 dma_release_channel(chan);
1288 if (enable_pio) {
1289 spin_lock_irqsave(&port->lock, flags);
1290 sci_start_tx(port);
1291 spin_unlock_irqrestore(&port->lock, flags);
1292 }
1293 }
1294
1295 static void sci_submit_rx(struct sci_port *s)
1296 {
1297 struct dma_chan *chan = s->chan_rx;
1298 int i;
1299
1300 for (i = 0; i < 2; i++) {
1301 struct scatterlist *sg = &s->sg_rx[i];
1302 struct dma_async_tx_descriptor *desc;
1303
1304 desc = dmaengine_prep_slave_sg(chan,
1305 sg, 1, DMA_DEV_TO_MEM,
1306 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1307 if (!desc)
1308 goto fail;
1309
1310 desc->callback = sci_dma_rx_complete;
1311 desc->callback_param = s;
1312 s->cookie_rx[i] = dmaengine_submit(desc);
1313 if (dma_submit_error(s->cookie_rx[i]))
1314 goto fail;
1315
1316 }
1317
1318 s->active_rx = s->cookie_rx[0];
1319
1320 dma_async_issue_pending(chan);
1321 return;
1322
1323 fail:
1324 if (i)
1325 dmaengine_terminate_all(chan);
1326 for (i = 0; i < 2; i++)
1327 s->cookie_rx[i] = -EINVAL;
1328 s->active_rx = 0;
1329 sci_rx_dma_release(s, true);
1330 }
1331
1332 static void work_fn_tx(struct work_struct *work)
1333 {
1334 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1335 struct dma_async_tx_descriptor *desc;
1336 struct dma_chan *chan = s->chan_tx;
1337 struct uart_port *port = &s->port;
1338 struct circ_buf *xmit = &port->state->xmit;
1339 dma_addr_t buf;
1340 int head, tail;
1341
1342 /*
1343 * DMA is idle now.
1344 * Port xmit buffer is already mapped, and it is one page... Just adjust
1345 * offsets and lengths. Since it is a circular buffer, we have to
1346 * transmit till the end, and then the rest. Take the port lock to get a
1347 * consistent xmit buffer state.
1348 */
1349 spin_lock_irq(&port->lock);
1350 head = xmit->head;
1351 tail = xmit->tail;
1352 buf = s->tx_dma_addr + (tail & (UART_XMIT_SIZE - 1));
1353 s->tx_dma_len = min_t(unsigned int,
1354 CIRC_CNT(head, tail, UART_XMIT_SIZE),
1355 CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE));
1356 if (!s->tx_dma_len) {
1357 /* Transmit buffer has been flushed */
1358 spin_unlock_irq(&port->lock);
1359 return;
1360 }
1361
1362 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1363 DMA_MEM_TO_DEV,
1364 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1365 if (!desc) {
1366 spin_unlock_irq(&port->lock);
1367 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1368 /* switch to PIO */
1369 sci_tx_dma_release(s, true);
1370 return;
1371 }
1372
1373 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1374 DMA_TO_DEVICE);
1375
1376 desc->callback = sci_dma_tx_complete;
1377 desc->callback_param = s;
1378 s->cookie_tx = dmaengine_submit(desc);
1379 if (dma_submit_error(s->cookie_tx)) {
1380 spin_unlock_irq(&port->lock);
1381 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1382 /* switch to PIO */
1383 sci_tx_dma_release(s, true);
1384 return;
1385 }
1386
1387 spin_unlock_irq(&port->lock);
1388 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1389 __func__, xmit->buf, tail, head, s->cookie_tx);
1390
1391 dma_async_issue_pending(chan);
1392 }
1393
1394 static void rx_timer_fn(struct timer_list *t)
1395 {
1396 struct sci_port *s = from_timer(s, t, rx_timer);
1397 struct dma_chan *chan = s->chan_rx;
1398 struct uart_port *port = &s->port;
1399 struct dma_tx_state state;
1400 enum dma_status status;
1401 unsigned long flags;
1402 unsigned int read;
1403 int active, count;
1404 u16 scr;
1405
1406 dev_dbg(port->dev, "DMA Rx timed out\n");
1407
1408 spin_lock_irqsave(&port->lock, flags);
1409
1410 active = sci_dma_rx_find_active(s);
1411 if (active < 0) {
1412 spin_unlock_irqrestore(&port->lock, flags);
1413 return;
1414 }
1415
1416 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1417 if (status == DMA_COMPLETE) {
1418 spin_unlock_irqrestore(&port->lock, flags);
1419 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1420 s->active_rx, active);
1421
1422 /* Let packet complete handler take care of the packet */
1423 return;
1424 }
1425
1426 dmaengine_pause(chan);
1427
1428 /*
1429 * sometimes DMA transfer doesn't stop even if it is stopped and
1430 * data keeps on coming until transaction is complete so check
1431 * for DMA_COMPLETE again
1432 * Let packet complete handler take care of the packet
1433 */
1434 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1435 if (status == DMA_COMPLETE) {
1436 spin_unlock_irqrestore(&port->lock, flags);
1437 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1438 return;
1439 }
1440
1441 /* Handle incomplete DMA receive */
1442 dmaengine_terminate_all(s->chan_rx);
1443 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1444
1445 if (read) {
1446 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1447 if (count)
1448 tty_flip_buffer_push(&port->state->port);
1449 }
1450
1451 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1452 sci_submit_rx(s);
1453
1454 /* Direct new serial port interrupts back to CPU */
1455 scr = serial_port_in(port, SCSCR);
1456 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1457 scr &= ~SCSCR_RDRQE;
1458 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1459 }
1460 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1461
1462 spin_unlock_irqrestore(&port->lock, flags);
1463 }
1464
1465 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1466 enum dma_transfer_direction dir)
1467 {
1468 struct dma_chan *chan;
1469 struct dma_slave_config cfg;
1470 int ret;
1471
1472 chan = dma_request_slave_channel(port->dev,
1473 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1474 if (!chan) {
1475 dev_warn(port->dev, "dma_request_slave_channel failed\n");
1476 return NULL;
1477 }
1478
1479 memset(&cfg, 0, sizeof(cfg));
1480 cfg.direction = dir;
1481 if (dir == DMA_MEM_TO_DEV) {
1482 cfg.dst_addr = port->mapbase +
1483 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1484 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1485 } else {
1486 cfg.src_addr = port->mapbase +
1487 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1488 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1489 }
1490
1491 ret = dmaengine_slave_config(chan, &cfg);
1492 if (ret) {
1493 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1494 dma_release_channel(chan);
1495 return NULL;
1496 }
1497
1498 return chan;
1499 }
1500
1501 static void sci_request_dma(struct uart_port *port)
1502 {
1503 struct sci_port *s = to_sci_port(port);
1504 struct dma_chan *chan;
1505
1506 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1507
1508 /*
1509 * DMA on console may interfere with Kernel log messages which use
1510 * plain putchar(). So, simply don't use it with a console.
1511 */
1512 if (uart_console(port))
1513 return;
1514
1515 if (!port->dev->of_node)
1516 return;
1517
1518 s->cookie_tx = -EINVAL;
1519
1520 /*
1521 * Don't request a dma channel if no channel was specified
1522 * in the device tree.
1523 */
1524 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1525 return;
1526
1527 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1528 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1529 if (chan) {
1530 s->chan_tx = chan;
1531 /* UART circular tx buffer is an aligned page. */
1532 s->tx_dma_addr = dma_map_single(chan->device->dev,
1533 port->state->xmit.buf,
1534 UART_XMIT_SIZE,
1535 DMA_TO_DEVICE);
1536 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1537 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1538 dma_release_channel(chan);
1539 s->chan_tx = NULL;
1540 } else {
1541 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1542 __func__, UART_XMIT_SIZE,
1543 port->state->xmit.buf, &s->tx_dma_addr);
1544 }
1545
1546 INIT_WORK(&s->work_tx, work_fn_tx);
1547 }
1548
1549 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1550 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1551 if (chan) {
1552 unsigned int i;
1553 dma_addr_t dma;
1554 void *buf;
1555
1556 s->chan_rx = chan;
1557
1558 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1559 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1560 &dma, GFP_KERNEL);
1561 if (!buf) {
1562 dev_warn(port->dev,
1563 "Failed to allocate Rx dma buffer, using PIO\n");
1564 dma_release_channel(chan);
1565 s->chan_rx = NULL;
1566 return;
1567 }
1568
1569 for (i = 0; i < 2; i++) {
1570 struct scatterlist *sg = &s->sg_rx[i];
1571
1572 sg_init_table(sg, 1);
1573 s->rx_buf[i] = buf;
1574 sg_dma_address(sg) = dma;
1575 sg_dma_len(sg) = s->buf_len_rx;
1576
1577 buf += s->buf_len_rx;
1578 dma += s->buf_len_rx;
1579 }
1580
1581 timer_setup(&s->rx_timer, rx_timer_fn, 0);
1582
1583 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1584 sci_submit_rx(s);
1585 }
1586 }
1587
1588 static void sci_free_dma(struct uart_port *port)
1589 {
1590 struct sci_port *s = to_sci_port(port);
1591
1592 if (s->chan_tx)
1593 sci_tx_dma_release(s, false);
1594 if (s->chan_rx)
1595 sci_rx_dma_release(s, false);
1596 }
1597
1598 static void sci_flush_buffer(struct uart_port *port)
1599 {
1600 struct sci_port *s = to_sci_port(port);
1601
1602 /*
1603 * In uart_flush_buffer(), the xmit circular buffer has just been
1604 * cleared, so we have to reset tx_dma_len accordingly, and stop any
1605 * pending transfers
1606 */
1607 s->tx_dma_len = 0;
1608 if (s->chan_tx) {
1609 dmaengine_terminate_async(s->chan_tx);
1610 s->cookie_tx = -EINVAL;
1611 }
1612 }
1613 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
1614 static inline void sci_request_dma(struct uart_port *port)
1615 {
1616 }
1617
1618 static inline void sci_free_dma(struct uart_port *port)
1619 {
1620 }
1621
1622 #define sci_flush_buffer NULL
1623 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1624
1625 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1626 {
1627 struct uart_port *port = ptr;
1628 struct sci_port *s = to_sci_port(port);
1629
1630 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1631 if (s->chan_rx) {
1632 u16 scr = serial_port_in(port, SCSCR);
1633 u16 ssr = serial_port_in(port, SCxSR);
1634
1635 /* Disable future Rx interrupts */
1636 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1637 disable_irq_nosync(irq);
1638 scr |= SCSCR_RDRQE;
1639 } else {
1640 scr &= ~SCSCR_RIE;
1641 sci_submit_rx(s);
1642 }
1643 serial_port_out(port, SCSCR, scr);
1644 /* Clear current interrupt */
1645 serial_port_out(port, SCxSR,
1646 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1647 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1648 jiffies, s->rx_timeout);
1649 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1650
1651 return IRQ_HANDLED;
1652 }
1653 #endif
1654
1655 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1656 if (!scif_rtrg_enabled(port))
1657 scif_set_rtrg(port, s->rx_trigger);
1658
1659 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1660 s->rx_frame * s->rx_fifo_timeout, 1000));
1661 }
1662
1663 /* I think sci_receive_chars has to be called irrespective
1664 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1665 * to be disabled?
1666 */
1667 sci_receive_chars(ptr);
1668
1669 return IRQ_HANDLED;
1670 }
1671
1672 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1673 {
1674 struct uart_port *port = ptr;
1675 unsigned long flags;
1676
1677 spin_lock_irqsave(&port->lock, flags);
1678 sci_transmit_chars(port);
1679 spin_unlock_irqrestore(&port->lock, flags);
1680
1681 return IRQ_HANDLED;
1682 }
1683
1684 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1685 {
1686 struct uart_port *port = ptr;
1687 struct sci_port *s = to_sci_port(port);
1688
1689 /* Handle errors */
1690 if (port->type == PORT_SCI) {
1691 if (sci_handle_errors(port)) {
1692 /* discard character in rx buffer */
1693 serial_port_in(port, SCxSR);
1694 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1695 }
1696 } else {
1697 sci_handle_fifo_overrun(port);
1698 if (!s->chan_rx)
1699 sci_receive_chars(ptr);
1700 }
1701
1702 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1703
1704 /* Kick the transmission */
1705 if (!s->chan_tx)
1706 sci_tx_interrupt(irq, ptr);
1707
1708 return IRQ_HANDLED;
1709 }
1710
1711 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1712 {
1713 struct uart_port *port = ptr;
1714
1715 /* Handle BREAKs */
1716 sci_handle_breaks(port);
1717 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1718
1719 return IRQ_HANDLED;
1720 }
1721
1722 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1723 {
1724 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1725 struct uart_port *port = ptr;
1726 struct sci_port *s = to_sci_port(port);
1727 irqreturn_t ret = IRQ_NONE;
1728
1729 ssr_status = serial_port_in(port, SCxSR);
1730 scr_status = serial_port_in(port, SCSCR);
1731 if (s->params->overrun_reg == SCxSR)
1732 orer_status = ssr_status;
1733 else if (sci_getreg(port, s->params->overrun_reg)->size)
1734 orer_status = serial_port_in(port, s->params->overrun_reg);
1735
1736 err_enabled = scr_status & port_rx_irq_mask(port);
1737
1738 /* Tx Interrupt */
1739 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1740 !s->chan_tx)
1741 ret = sci_tx_interrupt(irq, ptr);
1742
1743 /*
1744 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1745 * DR flags
1746 */
1747 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1748 (scr_status & SCSCR_RIE))
1749 ret = sci_rx_interrupt(irq, ptr);
1750
1751 /* Error Interrupt */
1752 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1753 ret = sci_er_interrupt(irq, ptr);
1754
1755 /* Break Interrupt */
1756 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1757 ret = sci_br_interrupt(irq, ptr);
1758
1759 /* Overrun Interrupt */
1760 if (orer_status & s->params->overrun_mask) {
1761 sci_handle_fifo_overrun(port);
1762 ret = IRQ_HANDLED;
1763 }
1764
1765 return ret;
1766 }
1767
1768 static const struct sci_irq_desc {
1769 const char *desc;
1770 irq_handler_t handler;
1771 } sci_irq_desc[] = {
1772 /*
1773 * Split out handlers, the default case.
1774 */
1775 [SCIx_ERI_IRQ] = {
1776 .desc = "rx err",
1777 .handler = sci_er_interrupt,
1778 },
1779
1780 [SCIx_RXI_IRQ] = {
1781 .desc = "rx full",
1782 .handler = sci_rx_interrupt,
1783 },
1784
1785 [SCIx_TXI_IRQ] = {
1786 .desc = "tx empty",
1787 .handler = sci_tx_interrupt,
1788 },
1789
1790 [SCIx_BRI_IRQ] = {
1791 .desc = "break",
1792 .handler = sci_br_interrupt,
1793 },
1794
1795 /*
1796 * Special muxed handler.
1797 */
1798 [SCIx_MUX_IRQ] = {
1799 .desc = "mux",
1800 .handler = sci_mpxed_interrupt,
1801 },
1802 };
1803
1804 static int sci_request_irq(struct sci_port *port)
1805 {
1806 struct uart_port *up = &port->port;
1807 int i, j, ret = 0;
1808
1809 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1810 const struct sci_irq_desc *desc;
1811 int irq;
1812
1813 if (SCIx_IRQ_IS_MUXED(port)) {
1814 i = SCIx_MUX_IRQ;
1815 irq = up->irq;
1816 } else {
1817 irq = port->irqs[i];
1818
1819 /*
1820 * Certain port types won't support all of the
1821 * available interrupt sources.
1822 */
1823 if (unlikely(irq < 0))
1824 continue;
1825 }
1826
1827 desc = sci_irq_desc + i;
1828 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1829 dev_name(up->dev), desc->desc);
1830 if (!port->irqstr[j]) {
1831 ret = -ENOMEM;
1832 goto out_nomem;
1833 }
1834
1835 ret = request_irq(irq, desc->handler, up->irqflags,
1836 port->irqstr[j], port);
1837 if (unlikely(ret)) {
1838 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1839 goto out_noirq;
1840 }
1841 }
1842
1843 return 0;
1844
1845 out_noirq:
1846 while (--i >= 0)
1847 free_irq(port->irqs[i], port);
1848
1849 out_nomem:
1850 while (--j >= 0)
1851 kfree(port->irqstr[j]);
1852
1853 return ret;
1854 }
1855
1856 static void sci_free_irq(struct sci_port *port)
1857 {
1858 int i, j;
1859
1860 /*
1861 * Intentionally in reverse order so we iterate over the muxed
1862 * IRQ first.
1863 */
1864 for (i = 0; i < SCIx_NR_IRQS; i++) {
1865 int irq = port->irqs[i];
1866
1867 /*
1868 * Certain port types won't support all of the available
1869 * interrupt sources.
1870 */
1871 if (unlikely(irq < 0))
1872 continue;
1873
1874 /* Check if already freed (irq was muxed) */
1875 for (j = 0; j < i; j++)
1876 if (port->irqs[j] == irq)
1877 j = i + 1;
1878 if (j > i)
1879 continue;
1880
1881 free_irq(port->irqs[i], port);
1882 kfree(port->irqstr[i]);
1883
1884 if (SCIx_IRQ_IS_MUXED(port)) {
1885 /* If there's only one IRQ, we're done. */
1886 return;
1887 }
1888 }
1889 }
1890
1891 static unsigned int sci_tx_empty(struct uart_port *port)
1892 {
1893 unsigned short status = serial_port_in(port, SCxSR);
1894 unsigned short in_tx_fifo = sci_txfill(port);
1895
1896 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1897 }
1898
1899 static void sci_set_rts(struct uart_port *port, bool state)
1900 {
1901 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1902 u16 data = serial_port_in(port, SCPDR);
1903
1904 /* Active low */
1905 if (state)
1906 data &= ~SCPDR_RTSD;
1907 else
1908 data |= SCPDR_RTSD;
1909 serial_port_out(port, SCPDR, data);
1910
1911 /* RTS# is output */
1912 serial_port_out(port, SCPCR,
1913 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1914 } else if (sci_getreg(port, SCSPTR)->size) {
1915 u16 ctrl = serial_port_in(port, SCSPTR);
1916
1917 /* Active low */
1918 if (state)
1919 ctrl &= ~SCSPTR_RTSDT;
1920 else
1921 ctrl |= SCSPTR_RTSDT;
1922 serial_port_out(port, SCSPTR, ctrl);
1923 }
1924 }
1925
1926 static bool sci_get_cts(struct uart_port *port)
1927 {
1928 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1929 /* Active low */
1930 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
1931 } else if (sci_getreg(port, SCSPTR)->size) {
1932 /* Active low */
1933 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
1934 }
1935
1936 return true;
1937 }
1938
1939 /*
1940 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1941 * CTS/RTS is supported in hardware by at least one port and controlled
1942 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1943 * handled via the ->init_pins() op, which is a bit of a one-way street,
1944 * lacking any ability to defer pin control -- this will later be
1945 * converted over to the GPIO framework).
1946 *
1947 * Other modes (such as loopback) are supported generically on certain
1948 * port types, but not others. For these it's sufficient to test for the
1949 * existence of the support register and simply ignore the port type.
1950 */
1951 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1952 {
1953 struct sci_port *s = to_sci_port(port);
1954
1955 if (mctrl & TIOCM_LOOP) {
1956 const struct plat_sci_reg *reg;
1957
1958 /*
1959 * Standard loopback mode for SCFCR ports.
1960 */
1961 reg = sci_getreg(port, SCFCR);
1962 if (reg->size)
1963 serial_port_out(port, SCFCR,
1964 serial_port_in(port, SCFCR) |
1965 SCFCR_LOOP);
1966 }
1967
1968 mctrl_gpio_set(s->gpios, mctrl);
1969
1970 if (!s->has_rtscts)
1971 return;
1972
1973 if (!(mctrl & TIOCM_RTS)) {
1974 /* Disable Auto RTS */
1975 serial_port_out(port, SCFCR,
1976 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
1977
1978 /* Clear RTS */
1979 sci_set_rts(port, 0);
1980 } else if (s->autorts) {
1981 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1982 /* Enable RTS# pin function */
1983 serial_port_out(port, SCPCR,
1984 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
1985 }
1986
1987 /* Enable Auto RTS */
1988 serial_port_out(port, SCFCR,
1989 serial_port_in(port, SCFCR) | SCFCR_MCE);
1990 } else {
1991 /* Set RTS */
1992 sci_set_rts(port, 1);
1993 }
1994 }
1995
1996 static unsigned int sci_get_mctrl(struct uart_port *port)
1997 {
1998 struct sci_port *s = to_sci_port(port);
1999 struct mctrl_gpios *gpios = s->gpios;
2000 unsigned int mctrl = 0;
2001
2002 mctrl_gpio_get(gpios, &mctrl);
2003
2004 /*
2005 * CTS/RTS is handled in hardware when supported, while nothing
2006 * else is wired up.
2007 */
2008 if (s->autorts) {
2009 if (sci_get_cts(port))
2010 mctrl |= TIOCM_CTS;
2011 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
2012 mctrl |= TIOCM_CTS;
2013 }
2014 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
2015 mctrl |= TIOCM_DSR;
2016 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
2017 mctrl |= TIOCM_CAR;
2018
2019 return mctrl;
2020 }
2021
2022 static void sci_enable_ms(struct uart_port *port)
2023 {
2024 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2025 }
2026
2027 static void sci_break_ctl(struct uart_port *port, int break_state)
2028 {
2029 unsigned short scscr, scsptr;
2030 unsigned long flags;
2031
2032 /* check wheter the port has SCSPTR */
2033 if (!sci_getreg(port, SCSPTR)->size) {
2034 /*
2035 * Not supported by hardware. Most parts couple break and rx
2036 * interrupts together, with break detection always enabled.
2037 */
2038 return;
2039 }
2040
2041 spin_lock_irqsave(&port->lock, flags);
2042 scsptr = serial_port_in(port, SCSPTR);
2043 scscr = serial_port_in(port, SCSCR);
2044
2045 if (break_state == -1) {
2046 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2047 scscr &= ~SCSCR_TE;
2048 } else {
2049 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2050 scscr |= SCSCR_TE;
2051 }
2052
2053 serial_port_out(port, SCSPTR, scsptr);
2054 serial_port_out(port, SCSCR, scscr);
2055 spin_unlock_irqrestore(&port->lock, flags);
2056 }
2057
2058 static int sci_startup(struct uart_port *port)
2059 {
2060 struct sci_port *s = to_sci_port(port);
2061 int ret;
2062
2063 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2064
2065 sci_request_dma(port);
2066
2067 ret = sci_request_irq(s);
2068 if (unlikely(ret < 0)) {
2069 sci_free_dma(port);
2070 return ret;
2071 }
2072
2073 return 0;
2074 }
2075
2076 static void sci_shutdown(struct uart_port *port)
2077 {
2078 struct sci_port *s = to_sci_port(port);
2079 unsigned long flags;
2080 u16 scr;
2081
2082 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2083
2084 s->autorts = false;
2085 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2086
2087 spin_lock_irqsave(&port->lock, flags);
2088 sci_stop_rx(port);
2089 sci_stop_tx(port);
2090 /*
2091 * Stop RX and TX, disable related interrupts, keep clock source
2092 * and HSCIF TOT bits
2093 */
2094 scr = serial_port_in(port, SCSCR);
2095 serial_port_out(port, SCSCR, scr &
2096 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2097 spin_unlock_irqrestore(&port->lock, flags);
2098
2099 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2100 if (s->chan_rx) {
2101 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2102 port->line);
2103 del_timer_sync(&s->rx_timer);
2104 }
2105 #endif
2106
2107 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2108 del_timer_sync(&s->rx_fifo_timer);
2109 sci_free_irq(s);
2110 sci_free_dma(port);
2111 }
2112
2113 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2114 unsigned int *srr)
2115 {
2116 unsigned long freq = s->clk_rates[SCI_SCK];
2117 int err, min_err = INT_MAX;
2118 unsigned int sr;
2119
2120 if (s->port.type != PORT_HSCIF)
2121 freq *= 2;
2122
2123 for_each_sr(sr, s) {
2124 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2125 if (abs(err) >= abs(min_err))
2126 continue;
2127
2128 min_err = err;
2129 *srr = sr - 1;
2130
2131 if (!err)
2132 break;
2133 }
2134
2135 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2136 *srr + 1);
2137 return min_err;
2138 }
2139
2140 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2141 unsigned long freq, unsigned int *dlr,
2142 unsigned int *srr)
2143 {
2144 int err, min_err = INT_MAX;
2145 unsigned int sr, dl;
2146
2147 if (s->port.type != PORT_HSCIF)
2148 freq *= 2;
2149
2150 for_each_sr(sr, s) {
2151 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2152 dl = clamp(dl, 1U, 65535U);
2153
2154 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2155 if (abs(err) >= abs(min_err))
2156 continue;
2157
2158 min_err = err;
2159 *dlr = dl;
2160 *srr = sr - 1;
2161
2162 if (!err)
2163 break;
2164 }
2165
2166 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2167 min_err, *dlr, *srr + 1);
2168 return min_err;
2169 }
2170
2171 /* calculate sample rate, BRR, and clock select */
2172 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2173 unsigned int *brr, unsigned int *srr,
2174 unsigned int *cks)
2175 {
2176 unsigned long freq = s->clk_rates[SCI_FCK];
2177 unsigned int sr, br, prediv, scrate, c;
2178 int err, min_err = INT_MAX;
2179
2180 if (s->port.type != PORT_HSCIF)
2181 freq *= 2;
2182
2183 /*
2184 * Find the combination of sample rate and clock select with the
2185 * smallest deviation from the desired baud rate.
2186 * Prefer high sample rates to maximise the receive margin.
2187 *
2188 * M: Receive margin (%)
2189 * N: Ratio of bit rate to clock (N = sampling rate)
2190 * D: Clock duty (D = 0 to 1.0)
2191 * L: Frame length (L = 9 to 12)
2192 * F: Absolute value of clock frequency deviation
2193 *
2194 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2195 * (|D - 0.5| / N * (1 + F))|
2196 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2197 */
2198 for_each_sr(sr, s) {
2199 for (c = 0; c <= 3; c++) {
2200 /* integerized formulas from HSCIF documentation */
2201 prediv = sr * (1 << (2 * c + 1));
2202
2203 /*
2204 * We need to calculate:
2205 *
2206 * br = freq / (prediv * bps) clamped to [1..256]
2207 * err = freq / (br * prediv) - bps
2208 *
2209 * Watch out for overflow when calculating the desired
2210 * sampling clock rate!
2211 */
2212 if (bps > UINT_MAX / prediv)
2213 break;
2214
2215 scrate = prediv * bps;
2216 br = DIV_ROUND_CLOSEST(freq, scrate);
2217 br = clamp(br, 1U, 256U);
2218
2219 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2220 if (abs(err) >= abs(min_err))
2221 continue;
2222
2223 min_err = err;
2224 *brr = br - 1;
2225 *srr = sr - 1;
2226 *cks = c;
2227
2228 if (!err)
2229 goto found;
2230 }
2231 }
2232
2233 found:
2234 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2235 min_err, *brr, *srr + 1, *cks);
2236 return min_err;
2237 }
2238
2239 static void sci_reset(struct uart_port *port)
2240 {
2241 const struct plat_sci_reg *reg;
2242 unsigned int status;
2243 struct sci_port *s = to_sci_port(port);
2244
2245 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2246
2247 reg = sci_getreg(port, SCFCR);
2248 if (reg->size)
2249 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2250
2251 sci_clear_SCxSR(port,
2252 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2253 SCxSR_BREAK_CLEAR(port));
2254 if (sci_getreg(port, SCLSR)->size) {
2255 status = serial_port_in(port, SCLSR);
2256 status &= ~(SCLSR_TO | SCLSR_ORER);
2257 serial_port_out(port, SCLSR, status);
2258 }
2259
2260 if (s->rx_trigger > 1) {
2261 if (s->rx_fifo_timeout) {
2262 scif_set_rtrg(port, 1);
2263 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2264 } else {
2265 if (port->type == PORT_SCIFA ||
2266 port->type == PORT_SCIFB)
2267 scif_set_rtrg(port, 1);
2268 else
2269 scif_set_rtrg(port, s->rx_trigger);
2270 }
2271 }
2272 }
2273
2274 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2275 struct ktermios *old)
2276 {
2277 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2278 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2279 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2280 struct sci_port *s = to_sci_port(port);
2281 const struct plat_sci_reg *reg;
2282 int min_err = INT_MAX, err;
2283 unsigned long max_freq = 0;
2284 int best_clk = -1;
2285 unsigned long flags;
2286
2287 if ((termios->c_cflag & CSIZE) == CS7)
2288 smr_val |= SCSMR_CHR;
2289 if (termios->c_cflag & PARENB)
2290 smr_val |= SCSMR_PE;
2291 if (termios->c_cflag & PARODD)
2292 smr_val |= SCSMR_PE | SCSMR_ODD;
2293 if (termios->c_cflag & CSTOPB)
2294 smr_val |= SCSMR_STOP;
2295
2296 /*
2297 * earlyprintk comes here early on with port->uartclk set to zero.
2298 * the clock framework is not up and running at this point so here
2299 * we assume that 115200 is the maximum baud rate. please note that
2300 * the baud rate is not programmed during earlyprintk - it is assumed
2301 * that the previous boot loader has enabled required clocks and
2302 * setup the baud rate generator hardware for us already.
2303 */
2304 if (!port->uartclk) {
2305 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2306 goto done;
2307 }
2308
2309 for (i = 0; i < SCI_NUM_CLKS; i++)
2310 max_freq = max(max_freq, s->clk_rates[i]);
2311
2312 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2313 if (!baud)
2314 goto done;
2315
2316 /*
2317 * There can be multiple sources for the sampling clock. Find the one
2318 * that gives us the smallest deviation from the desired baud rate.
2319 */
2320
2321 /* Optional Undivided External Clock */
2322 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2323 port->type != PORT_SCIFB) {
2324 err = sci_sck_calc(s, baud, &srr1);
2325 if (abs(err) < abs(min_err)) {
2326 best_clk = SCI_SCK;
2327 scr_val = SCSCR_CKE1;
2328 sccks = SCCKS_CKS;
2329 min_err = err;
2330 srr = srr1;
2331 if (!err)
2332 goto done;
2333 }
2334 }
2335
2336 /* Optional BRG Frequency Divided External Clock */
2337 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2338 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2339 &srr1);
2340 if (abs(err) < abs(min_err)) {
2341 best_clk = SCI_SCIF_CLK;
2342 scr_val = SCSCR_CKE1;
2343 sccks = 0;
2344 min_err = err;
2345 dl = dl1;
2346 srr = srr1;
2347 if (!err)
2348 goto done;
2349 }
2350 }
2351
2352 /* Optional BRG Frequency Divided Internal Clock */
2353 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2354 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2355 &srr1);
2356 if (abs(err) < abs(min_err)) {
2357 best_clk = SCI_BRG_INT;
2358 scr_val = SCSCR_CKE1;
2359 sccks = SCCKS_XIN;
2360 min_err = err;
2361 dl = dl1;
2362 srr = srr1;
2363 if (!min_err)
2364 goto done;
2365 }
2366 }
2367
2368 /* Divided Functional Clock using standard Bit Rate Register */
2369 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2370 if (abs(err) < abs(min_err)) {
2371 best_clk = SCI_FCK;
2372 scr_val = 0;
2373 min_err = err;
2374 brr = brr1;
2375 srr = srr1;
2376 cks = cks1;
2377 }
2378
2379 done:
2380 if (best_clk >= 0)
2381 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2382 s->clks[best_clk], baud, min_err);
2383
2384 sci_port_enable(s);
2385
2386 /*
2387 * Program the optional External Baud Rate Generator (BRG) first.
2388 * It controls the mux to select (H)SCK or frequency divided clock.
2389 */
2390 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2391 serial_port_out(port, SCDL, dl);
2392 serial_port_out(port, SCCKS, sccks);
2393 }
2394
2395 spin_lock_irqsave(&port->lock, flags);
2396
2397 sci_reset(port);
2398
2399 uart_update_timeout(port, termios->c_cflag, baud);
2400
2401 if (best_clk >= 0) {
2402 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2403 switch (srr + 1) {
2404 case 5: smr_val |= SCSMR_SRC_5; break;
2405 case 7: smr_val |= SCSMR_SRC_7; break;
2406 case 11: smr_val |= SCSMR_SRC_11; break;
2407 case 13: smr_val |= SCSMR_SRC_13; break;
2408 case 16: smr_val |= SCSMR_SRC_16; break;
2409 case 17: smr_val |= SCSMR_SRC_17; break;
2410 case 19: smr_val |= SCSMR_SRC_19; break;
2411 case 27: smr_val |= SCSMR_SRC_27; break;
2412 }
2413 smr_val |= cks;
2414 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2415 serial_port_out(port, SCSMR, smr_val);
2416 serial_port_out(port, SCBRR, brr);
2417 if (sci_getreg(port, HSSRR)->size)
2418 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
2419
2420 /* Wait one bit interval */
2421 udelay((1000000 + (baud - 1)) / baud);
2422 } else {
2423 /* Don't touch the bit rate configuration */
2424 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2425 smr_val |= serial_port_in(port, SCSMR) &
2426 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2427 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2428 serial_port_out(port, SCSMR, smr_val);
2429 }
2430
2431 sci_init_pins(port, termios->c_cflag);
2432
2433 port->status &= ~UPSTAT_AUTOCTS;
2434 s->autorts = false;
2435 reg = sci_getreg(port, SCFCR);
2436 if (reg->size) {
2437 unsigned short ctrl = serial_port_in(port, SCFCR);
2438
2439 if ((port->flags & UPF_HARD_FLOW) &&
2440 (termios->c_cflag & CRTSCTS)) {
2441 /* There is no CTS interrupt to restart the hardware */
2442 port->status |= UPSTAT_AUTOCTS;
2443 /* MCE is enabled when RTS is raised */
2444 s->autorts = true;
2445 }
2446
2447 /*
2448 * As we've done a sci_reset() above, ensure we don't
2449 * interfere with the FIFOs while toggling MCE. As the
2450 * reset values could still be set, simply mask them out.
2451 */
2452 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2453
2454 serial_port_out(port, SCFCR, ctrl);
2455 }
2456 if (port->flags & UPF_HARD_FLOW) {
2457 /* Refresh (Auto) RTS */
2458 sci_set_mctrl(port, port->mctrl);
2459 }
2460
2461 scr_val |= SCSCR_RE | SCSCR_TE |
2462 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2463 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2464 if ((srr + 1 == 5) &&
2465 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2466 /*
2467 * In asynchronous mode, when the sampling rate is 1/5, first
2468 * received data may become invalid on some SCIFA and SCIFB.
2469 * To avoid this problem wait more than 1 serial data time (1
2470 * bit time x serial data number) after setting SCSCR.RE = 1.
2471 */
2472 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2473 }
2474
2475 /*
2476 * Calculate delay for 2 DMA buffers (4 FIFO).
2477 * See serial_core.c::uart_update_timeout().
2478 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2479 * function calculates 1 jiffie for the data plus 5 jiffies for the
2480 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2481 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2482 * value obtained by this formula is too small. Therefore, if the value
2483 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2484 */
2485 /* byte size and parity */
2486 switch (termios->c_cflag & CSIZE) {
2487 case CS5:
2488 bits = 7;
2489 break;
2490 case CS6:
2491 bits = 8;
2492 break;
2493 case CS7:
2494 bits = 9;
2495 break;
2496 default:
2497 bits = 10;
2498 break;
2499 }
2500
2501 if (termios->c_cflag & CSTOPB)
2502 bits++;
2503 if (termios->c_cflag & PARENB)
2504 bits++;
2505
2506 s->rx_frame = (100 * bits * HZ) / (baud / 10);
2507 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2508 s->rx_timeout = DIV_ROUND_UP(s->buf_len_rx * 2 * s->rx_frame, 1000);
2509 if (s->rx_timeout < msecs_to_jiffies(20))
2510 s->rx_timeout = msecs_to_jiffies(20);
2511 #endif
2512
2513 if ((termios->c_cflag & CREAD) != 0)
2514 sci_start_rx(port);
2515
2516 spin_unlock_irqrestore(&port->lock, flags);
2517
2518 sci_port_disable(s);
2519
2520 if (UART_ENABLE_MS(port, termios->c_cflag))
2521 sci_enable_ms(port);
2522 }
2523
2524 static void sci_pm(struct uart_port *port, unsigned int state,
2525 unsigned int oldstate)
2526 {
2527 struct sci_port *sci_port = to_sci_port(port);
2528
2529 switch (state) {
2530 case UART_PM_STATE_OFF:
2531 sci_port_disable(sci_port);
2532 break;
2533 default:
2534 sci_port_enable(sci_port);
2535 break;
2536 }
2537 }
2538
2539 static const char *sci_type(struct uart_port *port)
2540 {
2541 switch (port->type) {
2542 case PORT_IRDA:
2543 return "irda";
2544 case PORT_SCI:
2545 return "sci";
2546 case PORT_SCIF:
2547 return "scif";
2548 case PORT_SCIFA:
2549 return "scifa";
2550 case PORT_SCIFB:
2551 return "scifb";
2552 case PORT_HSCIF:
2553 return "hscif";
2554 }
2555
2556 return NULL;
2557 }
2558
2559 static int sci_remap_port(struct uart_port *port)
2560 {
2561 struct sci_port *sport = to_sci_port(port);
2562
2563 /*
2564 * Nothing to do if there's already an established membase.
2565 */
2566 if (port->membase)
2567 return 0;
2568
2569 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2570 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2571 if (unlikely(!port->membase)) {
2572 dev_err(port->dev, "can't remap port#%d\n", port->line);
2573 return -ENXIO;
2574 }
2575 } else {
2576 /*
2577 * For the simple (and majority of) cases where we don't
2578 * need to do any remapping, just cast the cookie
2579 * directly.
2580 */
2581 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2582 }
2583
2584 return 0;
2585 }
2586
2587 static void sci_release_port(struct uart_port *port)
2588 {
2589 struct sci_port *sport = to_sci_port(port);
2590
2591 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2592 iounmap(port->membase);
2593 port->membase = NULL;
2594 }
2595
2596 release_mem_region(port->mapbase, sport->reg_size);
2597 }
2598
2599 static int sci_request_port(struct uart_port *port)
2600 {
2601 struct resource *res;
2602 struct sci_port *sport = to_sci_port(port);
2603 int ret;
2604
2605 res = request_mem_region(port->mapbase, sport->reg_size,
2606 dev_name(port->dev));
2607 if (unlikely(res == NULL)) {
2608 dev_err(port->dev, "request_mem_region failed.");
2609 return -EBUSY;
2610 }
2611
2612 ret = sci_remap_port(port);
2613 if (unlikely(ret != 0)) {
2614 release_resource(res);
2615 return ret;
2616 }
2617
2618 return 0;
2619 }
2620
2621 static void sci_config_port(struct uart_port *port, int flags)
2622 {
2623 if (flags & UART_CONFIG_TYPE) {
2624 struct sci_port *sport = to_sci_port(port);
2625
2626 port->type = sport->cfg->type;
2627 sci_request_port(port);
2628 }
2629 }
2630
2631 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2632 {
2633 if (ser->baud_base < 2400)
2634 /* No paper tape reader for Mitch.. */
2635 return -EINVAL;
2636
2637 return 0;
2638 }
2639
2640 static const struct uart_ops sci_uart_ops = {
2641 .tx_empty = sci_tx_empty,
2642 .set_mctrl = sci_set_mctrl,
2643 .get_mctrl = sci_get_mctrl,
2644 .start_tx = sci_start_tx,
2645 .stop_tx = sci_stop_tx,
2646 .stop_rx = sci_stop_rx,
2647 .enable_ms = sci_enable_ms,
2648 .break_ctl = sci_break_ctl,
2649 .startup = sci_startup,
2650 .shutdown = sci_shutdown,
2651 .flush_buffer = sci_flush_buffer,
2652 .set_termios = sci_set_termios,
2653 .pm = sci_pm,
2654 .type = sci_type,
2655 .release_port = sci_release_port,
2656 .request_port = sci_request_port,
2657 .config_port = sci_config_port,
2658 .verify_port = sci_verify_port,
2659 #ifdef CONFIG_CONSOLE_POLL
2660 .poll_get_char = sci_poll_get_char,
2661 .poll_put_char = sci_poll_put_char,
2662 #endif
2663 };
2664
2665 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2666 {
2667 const char *clk_names[] = {
2668 [SCI_FCK] = "fck",
2669 [SCI_SCK] = "sck",
2670 [SCI_BRG_INT] = "brg_int",
2671 [SCI_SCIF_CLK] = "scif_clk",
2672 };
2673 struct clk *clk;
2674 unsigned int i;
2675
2676 if (sci_port->cfg->type == PORT_HSCIF)
2677 clk_names[SCI_SCK] = "hsck";
2678
2679 for (i = 0; i < SCI_NUM_CLKS; i++) {
2680 clk = devm_clk_get(dev, clk_names[i]);
2681 if (PTR_ERR(clk) == -EPROBE_DEFER)
2682 return -EPROBE_DEFER;
2683
2684 if (IS_ERR(clk) && i == SCI_FCK) {
2685 /*
2686 * "fck" used to be called "sci_ick", and we need to
2687 * maintain DT backward compatibility.
2688 */
2689 clk = devm_clk_get(dev, "sci_ick");
2690 if (PTR_ERR(clk) == -EPROBE_DEFER)
2691 return -EPROBE_DEFER;
2692
2693 if (!IS_ERR(clk))
2694 goto found;
2695
2696 /*
2697 * Not all SH platforms declare a clock lookup entry
2698 * for SCI devices, in which case we need to get the
2699 * global "peripheral_clk" clock.
2700 */
2701 clk = devm_clk_get(dev, "peripheral_clk");
2702 if (!IS_ERR(clk))
2703 goto found;
2704
2705 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2706 PTR_ERR(clk));
2707 return PTR_ERR(clk);
2708 }
2709
2710 found:
2711 if (IS_ERR(clk))
2712 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2713 PTR_ERR(clk));
2714 else
2715 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2716 clk, clk_get_rate(clk));
2717 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2718 }
2719 return 0;
2720 }
2721
2722 static const struct sci_port_params *
2723 sci_probe_regmap(const struct plat_sci_port *cfg)
2724 {
2725 unsigned int regtype;
2726
2727 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2728 return &sci_port_params[cfg->regtype];
2729
2730 switch (cfg->type) {
2731 case PORT_SCI:
2732 regtype = SCIx_SCI_REGTYPE;
2733 break;
2734 case PORT_IRDA:
2735 regtype = SCIx_IRDA_REGTYPE;
2736 break;
2737 case PORT_SCIFA:
2738 regtype = SCIx_SCIFA_REGTYPE;
2739 break;
2740 case PORT_SCIFB:
2741 regtype = SCIx_SCIFB_REGTYPE;
2742 break;
2743 case PORT_SCIF:
2744 /*
2745 * The SH-4 is a bit of a misnomer here, although that's
2746 * where this particular port layout originated. This
2747 * configuration (or some slight variation thereof)
2748 * remains the dominant model for all SCIFs.
2749 */
2750 regtype = SCIx_SH4_SCIF_REGTYPE;
2751 break;
2752 case PORT_HSCIF:
2753 regtype = SCIx_HSCIF_REGTYPE;
2754 break;
2755 default:
2756 pr_err("Can't probe register map for given port\n");
2757 return NULL;
2758 }
2759
2760 return &sci_port_params[regtype];
2761 }
2762
2763 static int sci_init_single(struct platform_device *dev,
2764 struct sci_port *sci_port, unsigned int index,
2765 const struct plat_sci_port *p, bool early)
2766 {
2767 struct uart_port *port = &sci_port->port;
2768 const struct resource *res;
2769 unsigned int i;
2770 int ret;
2771
2772 sci_port->cfg = p;
2773
2774 port->ops = &sci_uart_ops;
2775 port->iotype = UPIO_MEM;
2776 port->line = index;
2777
2778 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2779 if (res == NULL)
2780 return -ENOMEM;
2781
2782 port->mapbase = res->start;
2783 sci_port->reg_size = resource_size(res);
2784
2785 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2786 sci_port->irqs[i] = platform_get_irq(dev, i);
2787
2788 /* The SCI generates several interrupts. They can be muxed together or
2789 * connected to different interrupt lines. In the muxed case only one
2790 * interrupt resource is specified. In the non-muxed case three or four
2791 * interrupt resources are specified, as the BRI interrupt is optional.
2792 */
2793 if (sci_port->irqs[0] < 0)
2794 return -ENXIO;
2795
2796 if (sci_port->irqs[1] < 0) {
2797 sci_port->irqs[1] = sci_port->irqs[0];
2798 sci_port->irqs[2] = sci_port->irqs[0];
2799 sci_port->irqs[3] = sci_port->irqs[0];
2800 }
2801
2802 sci_port->params = sci_probe_regmap(p);
2803 if (unlikely(sci_port->params == NULL))
2804 return -EINVAL;
2805
2806 switch (p->type) {
2807 case PORT_SCIFB:
2808 sci_port->rx_trigger = 48;
2809 break;
2810 case PORT_HSCIF:
2811 sci_port->rx_trigger = 64;
2812 break;
2813 case PORT_SCIFA:
2814 sci_port->rx_trigger = 32;
2815 break;
2816 case PORT_SCIF:
2817 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2818 /* RX triggering not implemented for this IP */
2819 sci_port->rx_trigger = 1;
2820 else
2821 sci_port->rx_trigger = 8;
2822 break;
2823 default:
2824 sci_port->rx_trigger = 1;
2825 break;
2826 }
2827
2828 sci_port->rx_fifo_timeout = 0;
2829 sci_port->hscif_tot = 0;
2830
2831 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2832 * match the SoC datasheet, this should be investigated. Let platform
2833 * data override the sampling rate for now.
2834 */
2835 sci_port->sampling_rate_mask = p->sampling_rate
2836 ? SCI_SR(p->sampling_rate)
2837 : sci_port->params->sampling_rate_mask;
2838
2839 if (!early) {
2840 ret = sci_init_clocks(sci_port, &dev->dev);
2841 if (ret < 0)
2842 return ret;
2843
2844 port->dev = &dev->dev;
2845
2846 pm_runtime_enable(&dev->dev);
2847 }
2848
2849 port->type = p->type;
2850 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2851 port->fifosize = sci_port->params->fifosize;
2852
2853 if (port->type == PORT_SCI) {
2854 if (sci_port->reg_size >= 0x20)
2855 port->regshift = 2;
2856 else
2857 port->regshift = 1;
2858 }
2859
2860 /*
2861 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2862 * for the multi-IRQ ports, which is where we are primarily
2863 * concerned with the shutdown path synchronization.
2864 *
2865 * For the muxed case there's nothing more to do.
2866 */
2867 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2868 port->irqflags = 0;
2869
2870 port->serial_in = sci_serial_in;
2871 port->serial_out = sci_serial_out;
2872
2873 return 0;
2874 }
2875
2876 static void sci_cleanup_single(struct sci_port *port)
2877 {
2878 pm_runtime_disable(port->port.dev);
2879 }
2880
2881 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2882 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2883 static void serial_console_putchar(struct uart_port *port, int ch)
2884 {
2885 sci_poll_put_char(port, ch);
2886 }
2887
2888 /*
2889 * Print a string to the serial port trying not to disturb
2890 * any possible real use of the port...
2891 */
2892 static void serial_console_write(struct console *co, const char *s,
2893 unsigned count)
2894 {
2895 struct sci_port *sci_port = &sci_ports[co->index];
2896 struct uart_port *port = &sci_port->port;
2897 unsigned short bits, ctrl, ctrl_temp;
2898 unsigned long flags;
2899 int locked = 1;
2900
2901 #if defined(SUPPORT_SYSRQ)
2902 if (port->sysrq)
2903 locked = 0;
2904 else
2905 #endif
2906 if (oops_in_progress)
2907 locked = spin_trylock_irqsave(&port->lock, flags);
2908 else
2909 spin_lock_irqsave(&port->lock, flags);
2910
2911 /* first save SCSCR then disable interrupts, keep clock source */
2912 ctrl = serial_port_in(port, SCSCR);
2913 ctrl_temp = SCSCR_RE | SCSCR_TE |
2914 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2915 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2916 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
2917
2918 uart_console_write(port, s, count, serial_console_putchar);
2919
2920 /* wait until fifo is empty and last bit has been transmitted */
2921 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2922 while ((serial_port_in(port, SCxSR) & bits) != bits)
2923 cpu_relax();
2924
2925 /* restore the SCSCR */
2926 serial_port_out(port, SCSCR, ctrl);
2927
2928 if (locked)
2929 spin_unlock_irqrestore(&port->lock, flags);
2930 }
2931
2932 static int serial_console_setup(struct console *co, char *options)
2933 {
2934 struct sci_port *sci_port;
2935 struct uart_port *port;
2936 int baud = 115200;
2937 int bits = 8;
2938 int parity = 'n';
2939 int flow = 'n';
2940 int ret;
2941
2942 /*
2943 * Refuse to handle any bogus ports.
2944 */
2945 if (co->index < 0 || co->index >= SCI_NPORTS)
2946 return -ENODEV;
2947
2948 sci_port = &sci_ports[co->index];
2949 port = &sci_port->port;
2950
2951 /*
2952 * Refuse to handle uninitialized ports.
2953 */
2954 if (!port->ops)
2955 return -ENODEV;
2956
2957 ret = sci_remap_port(port);
2958 if (unlikely(ret != 0))
2959 return ret;
2960
2961 if (options)
2962 uart_parse_options(options, &baud, &parity, &bits, &flow);
2963
2964 return uart_set_options(port, co, baud, parity, bits, flow);
2965 }
2966
2967 static struct console serial_console = {
2968 .name = "ttySC",
2969 .device = uart_console_device,
2970 .write = serial_console_write,
2971 .setup = serial_console_setup,
2972 .flags = CON_PRINTBUFFER,
2973 .index = -1,
2974 .data = &sci_uart_driver,
2975 };
2976
2977 static struct console early_serial_console = {
2978 .name = "early_ttySC",
2979 .write = serial_console_write,
2980 .flags = CON_PRINTBUFFER,
2981 .index = -1,
2982 };
2983
2984 static char early_serial_buf[32];
2985
2986 static int sci_probe_earlyprintk(struct platform_device *pdev)
2987 {
2988 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2989
2990 if (early_serial_console.data)
2991 return -EEXIST;
2992
2993 early_serial_console.index = pdev->id;
2994
2995 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2996
2997 serial_console_setup(&early_serial_console, early_serial_buf);
2998
2999 if (!strstr(early_serial_buf, "keep"))
3000 early_serial_console.flags |= CON_BOOT;
3001
3002 register_console(&early_serial_console);
3003 return 0;
3004 }
3005
3006 #define SCI_CONSOLE (&serial_console)
3007
3008 #else
3009 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3010 {
3011 return -EINVAL;
3012 }
3013
3014 #define SCI_CONSOLE NULL
3015
3016 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3017
3018 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3019
3020 static DEFINE_MUTEX(sci_uart_registration_lock);
3021 static struct uart_driver sci_uart_driver = {
3022 .owner = THIS_MODULE,
3023 .driver_name = "sci",
3024 .dev_name = "ttySC",
3025 .major = SCI_MAJOR,
3026 .minor = SCI_MINOR_START,
3027 .nr = SCI_NPORTS,
3028 .cons = SCI_CONSOLE,
3029 };
3030
3031 static int sci_remove(struct platform_device *dev)
3032 {
3033 struct sci_port *port = platform_get_drvdata(dev);
3034 unsigned int type = port->port.type; /* uart_remove_... clears it */
3035
3036 uart_remove_one_port(&sci_uart_driver, &port->port);
3037
3038 sci_cleanup_single(port);
3039
3040 if (port->port.fifosize > 1) {
3041 sysfs_remove_file(&dev->dev.kobj,
3042 &dev_attr_rx_fifo_trigger.attr);
3043 }
3044 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) {
3045 sysfs_remove_file(&dev->dev.kobj,
3046 &dev_attr_rx_fifo_timeout.attr);
3047 }
3048
3049 return 0;
3050 }
3051
3052
3053 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3054 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3055 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3056
3057 static const struct of_device_id of_sci_match[] = {
3058 /* SoC-specific types */
3059 {
3060 .compatible = "renesas,scif-r7s72100",
3061 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3062 },
3063 /* Family-specific types */
3064 {
3065 .compatible = "renesas,rcar-gen1-scif",
3066 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3067 }, {
3068 .compatible = "renesas,rcar-gen2-scif",
3069 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3070 }, {
3071 .compatible = "renesas,rcar-gen3-scif",
3072 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3073 },
3074 /* Generic types */
3075 {
3076 .compatible = "renesas,scif",
3077 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3078 }, {
3079 .compatible = "renesas,scifa",
3080 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3081 }, {
3082 .compatible = "renesas,scifb",
3083 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3084 }, {
3085 .compatible = "renesas,hscif",
3086 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3087 }, {
3088 .compatible = "renesas,sci",
3089 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3090 }, {
3091 /* Terminator */
3092 },
3093 };
3094 MODULE_DEVICE_TABLE(of, of_sci_match);
3095
3096 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3097 unsigned int *dev_id)
3098 {
3099 struct device_node *np = pdev->dev.of_node;
3100 struct plat_sci_port *p;
3101 struct sci_port *sp;
3102 const void *data;
3103 int id;
3104
3105 if (!IS_ENABLED(CONFIG_OF) || !np)
3106 return NULL;
3107
3108 data = of_device_get_match_data(&pdev->dev);
3109
3110 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3111 if (!p)
3112 return NULL;
3113
3114 /* Get the line number from the aliases node. */
3115 id = of_alias_get_id(np, "serial");
3116 if (id < 0) {
3117 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3118 return NULL;
3119 }
3120 if (id >= ARRAY_SIZE(sci_ports)) {
3121 dev_err(&pdev->dev, "serial%d out of range\n", id);
3122 return NULL;
3123 }
3124
3125 sp = &sci_ports[id];
3126 *dev_id = id;
3127
3128 p->type = SCI_OF_TYPE(data);
3129 p->regtype = SCI_OF_REGTYPE(data);
3130
3131 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3132
3133 return p;
3134 }
3135
3136 static int sci_probe_single(struct platform_device *dev,
3137 unsigned int index,
3138 struct plat_sci_port *p,
3139 struct sci_port *sciport)
3140 {
3141 int ret;
3142
3143 /* Sanity check */
3144 if (unlikely(index >= SCI_NPORTS)) {
3145 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3146 index+1, SCI_NPORTS);
3147 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3148 return -EINVAL;
3149 }
3150
3151 mutex_lock(&sci_uart_registration_lock);
3152 if (!sci_uart_driver.state) {
3153 ret = uart_register_driver(&sci_uart_driver);
3154 if (ret) {
3155 mutex_unlock(&sci_uart_registration_lock);
3156 return ret;
3157 }
3158 }
3159 mutex_unlock(&sci_uart_registration_lock);
3160
3161 ret = sci_init_single(dev, sciport, index, p, false);
3162 if (ret)
3163 return ret;
3164
3165 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3166 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3167 return PTR_ERR(sciport->gpios);
3168
3169 if (sciport->has_rtscts) {
3170 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3171 UART_GPIO_CTS)) ||
3172 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3173 UART_GPIO_RTS))) {
3174 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3175 return -EINVAL;
3176 }
3177 sciport->port.flags |= UPF_HARD_FLOW;
3178 }
3179
3180 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3181 if (ret) {
3182 sci_cleanup_single(sciport);
3183 return ret;
3184 }
3185
3186 return 0;
3187 }
3188
3189 static int sci_probe(struct platform_device *dev)
3190 {
3191 struct plat_sci_port *p;
3192 struct sci_port *sp;
3193 unsigned int dev_id;
3194 int ret;
3195
3196 /*
3197 * If we've come here via earlyprintk initialization, head off to
3198 * the special early probe. We don't have sufficient device state
3199 * to make it beyond this yet.
3200 */
3201 if (is_early_platform_device(dev))
3202 return sci_probe_earlyprintk(dev);
3203
3204 if (dev->dev.of_node) {
3205 p = sci_parse_dt(dev, &dev_id);
3206 if (p == NULL)
3207 return -EINVAL;
3208 } else {
3209 p = dev->dev.platform_data;
3210 if (p == NULL) {
3211 dev_err(&dev->dev, "no platform data supplied\n");
3212 return -EINVAL;
3213 }
3214
3215 dev_id = dev->id;
3216 }
3217
3218 sp = &sci_ports[dev_id];
3219 platform_set_drvdata(dev, sp);
3220
3221 ret = sci_probe_single(dev, dev_id, p, sp);
3222 if (ret)
3223 return ret;
3224
3225 if (sp->port.fifosize > 1) {
3226 ret = sysfs_create_file(&dev->dev.kobj,
3227 &dev_attr_rx_fifo_trigger.attr);
3228 if (ret)
3229 return ret;
3230 }
3231 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3232 sp->port.type == PORT_HSCIF) {
3233 ret = sysfs_create_file(&dev->dev.kobj,
3234 &dev_attr_rx_fifo_timeout.attr);
3235 if (ret) {
3236 if (sp->port.fifosize > 1) {
3237 sysfs_remove_file(&dev->dev.kobj,
3238 &dev_attr_rx_fifo_trigger.attr);
3239 }
3240 return ret;
3241 }
3242 }
3243
3244 #ifdef CONFIG_SH_STANDARD_BIOS
3245 sh_bios_gdb_detach();
3246 #endif
3247
3248 return 0;
3249 }
3250
3251 static __maybe_unused int sci_suspend(struct device *dev)
3252 {
3253 struct sci_port *sport = dev_get_drvdata(dev);
3254
3255 if (sport)
3256 uart_suspend_port(&sci_uart_driver, &sport->port);
3257
3258 return 0;
3259 }
3260
3261 static __maybe_unused int sci_resume(struct device *dev)
3262 {
3263 struct sci_port *sport = dev_get_drvdata(dev);
3264
3265 if (sport)
3266 uart_resume_port(&sci_uart_driver, &sport->port);
3267
3268 return 0;
3269 }
3270
3271 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3272
3273 static struct platform_driver sci_driver = {
3274 .probe = sci_probe,
3275 .remove = sci_remove,
3276 .driver = {
3277 .name = "sh-sci",
3278 .pm = &sci_dev_pm_ops,
3279 .of_match_table = of_match_ptr(of_sci_match),
3280 },
3281 };
3282
3283 static int __init sci_init(void)
3284 {
3285 pr_info("%s\n", banner);
3286
3287 return platform_driver_register(&sci_driver);
3288 }
3289
3290 static void __exit sci_exit(void)
3291 {
3292 platform_driver_unregister(&sci_driver);
3293
3294 if (sci_uart_driver.state)
3295 uart_unregister_driver(&sci_uart_driver);
3296 }
3297
3298 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3299 early_platform_init_buffer("earlyprintk", &sci_driver,
3300 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3301 #endif
3302 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3303 static struct plat_sci_port port_cfg __initdata;
3304
3305 static int __init early_console_setup(struct earlycon_device *device,
3306 int type)
3307 {
3308 if (!device->port.membase)
3309 return -ENODEV;
3310
3311 device->port.serial_in = sci_serial_in;
3312 device->port.serial_out = sci_serial_out;
3313 device->port.type = type;
3314 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3315 port_cfg.type = type;
3316 sci_ports[0].cfg = &port_cfg;
3317 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3318 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3319 sci_serial_out(&sci_ports[0].port, SCSCR,
3320 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3321
3322 device->con->write = serial_console_write;
3323 return 0;
3324 }
3325 static int __init sci_early_console_setup(struct earlycon_device *device,
3326 const char *opt)
3327 {
3328 return early_console_setup(device, PORT_SCI);
3329 }
3330 static int __init scif_early_console_setup(struct earlycon_device *device,
3331 const char *opt)
3332 {
3333 return early_console_setup(device, PORT_SCIF);
3334 }
3335 static int __init scifa_early_console_setup(struct earlycon_device *device,
3336 const char *opt)
3337 {
3338 return early_console_setup(device, PORT_SCIFA);
3339 }
3340 static int __init scifb_early_console_setup(struct earlycon_device *device,
3341 const char *opt)
3342 {
3343 return early_console_setup(device, PORT_SCIFB);
3344 }
3345 static int __init hscif_early_console_setup(struct earlycon_device *device,
3346 const char *opt)
3347 {
3348 return early_console_setup(device, PORT_HSCIF);
3349 }
3350
3351 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3352 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3353 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3354 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3355 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3356 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3357
3358 module_init(sci_init);
3359 module_exit(sci_exit);
3360
3361 MODULE_LICENSE("GPL");
3362 MODULE_ALIAS("platform:sh-sci");
3363 MODULE_AUTHOR("Paul Mundt");
3364 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
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