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[mirror_ubuntu-artful-kernel.git] / drivers / tty / serial / sh-sci.c
1 /*
2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Copyright (C) 2015 Glider bvba
6 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 *
8 * based off of the old drivers/char/sh-sci.c by:
9 *
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15 * Removed SH7300 support (Jul 2007).
16 *
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details.
20 */
21 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #define SUPPORT_SYSRQ
23 #endif
24
25 #undef DEBUG
26
27 #include <linux/clk.h>
28 #include <linux/console.h>
29 #include <linux/ctype.h>
30 #include <linux/cpufreq.h>
31 #include <linux/delay.h>
32 #include <linux/dmaengine.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/err.h>
35 #include <linux/errno.h>
36 #include <linux/init.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/major.h>
40 #include <linux/module.h>
41 #include <linux/mm.h>
42 #include <linux/of.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
55
56 #ifdef CONFIG_SUPERH
57 #include <asm/sh_bios.h>
58 #endif
59
60 #include "serial_mctrl_gpio.h"
61 #include "sh-sci.h"
62
63 /* Offsets into the sci_port->irqs array */
64 enum {
65 SCIx_ERI_IRQ,
66 SCIx_RXI_IRQ,
67 SCIx_TXI_IRQ,
68 SCIx_BRI_IRQ,
69 SCIx_NR_IRQS,
70
71 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
72 };
73
74 #define SCIx_IRQ_IS_MUXED(port) \
75 ((port)->irqs[SCIx_ERI_IRQ] == \
76 (port)->irqs[SCIx_RXI_IRQ]) || \
77 ((port)->irqs[SCIx_ERI_IRQ] && \
78 ((port)->irqs[SCIx_RXI_IRQ] < 0))
79
80 enum SCI_CLKS {
81 SCI_FCK, /* Functional Clock */
82 SCI_SCK, /* Optional External Clock */
83 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
84 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
85 SCI_NUM_CLKS
86 };
87
88 /* Bit x set means sampling rate x + 1 is supported */
89 #define SCI_SR(x) BIT((x) - 1)
90 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
91
92 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
93 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
94 SCI_SR(19) | SCI_SR(27)
95
96 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
97 #define max_sr(_port) fls((_port)->sampling_rate_mask)
98
99 /* Iterate over all supported sampling rates, from high to low */
100 #define for_each_sr(_sr, _port) \
101 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
102 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
103
104 struct plat_sci_reg {
105 u8 offset, size;
106 };
107
108 struct sci_port_params {
109 const struct plat_sci_reg regs[SCIx_NR_REGS];
110 unsigned int fifosize;
111 unsigned int overrun_reg;
112 unsigned int overrun_mask;
113 unsigned int sampling_rate_mask;
114 unsigned int error_mask;
115 unsigned int error_clear;
116 };
117
118 struct sci_port {
119 struct uart_port port;
120
121 /* Platform configuration */
122 const struct sci_port_params *params;
123 const struct plat_sci_port *cfg;
124 unsigned int sampling_rate_mask;
125 resource_size_t reg_size;
126 struct mctrl_gpios *gpios;
127
128 /* Clocks */
129 struct clk *clks[SCI_NUM_CLKS];
130 unsigned long clk_rates[SCI_NUM_CLKS];
131
132 int irqs[SCIx_NR_IRQS];
133 char *irqstr[SCIx_NR_IRQS];
134
135 struct dma_chan *chan_tx;
136 struct dma_chan *chan_rx;
137
138 #ifdef CONFIG_SERIAL_SH_SCI_DMA
139 dma_cookie_t cookie_tx;
140 dma_cookie_t cookie_rx[2];
141 dma_cookie_t active_rx;
142 dma_addr_t tx_dma_addr;
143 unsigned int tx_dma_len;
144 struct scatterlist sg_rx[2];
145 void *rx_buf[2];
146 size_t buf_len_rx;
147 struct work_struct work_tx;
148 struct timer_list rx_timer;
149 unsigned int rx_timeout;
150 #endif
151 unsigned int rx_frame;
152 int rx_trigger;
153 struct timer_list rx_fifo_timer;
154 int rx_fifo_timeout;
155
156 bool has_rtscts;
157 bool autorts;
158 };
159
160 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
161
162 static struct sci_port sci_ports[SCI_NPORTS];
163 static struct uart_driver sci_uart_driver;
164
165 static inline struct sci_port *
166 to_sci_port(struct uart_port *uart)
167 {
168 return container_of(uart, struct sci_port, port);
169 }
170
171 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
172 /*
173 * Common SCI definitions, dependent on the port's regshift
174 * value.
175 */
176 [SCIx_SCI_REGTYPE] = {
177 .regs = {
178 [SCSMR] = { 0x00, 8 },
179 [SCBRR] = { 0x01, 8 },
180 [SCSCR] = { 0x02, 8 },
181 [SCxTDR] = { 0x03, 8 },
182 [SCxSR] = { 0x04, 8 },
183 [SCxRDR] = { 0x05, 8 },
184 },
185 .fifosize = 1,
186 .overrun_reg = SCxSR,
187 .overrun_mask = SCI_ORER,
188 .sampling_rate_mask = SCI_SR(32),
189 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
190 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
191 },
192
193 /*
194 * Common definitions for legacy IrDA ports.
195 */
196 [SCIx_IRDA_REGTYPE] = {
197 .regs = {
198 [SCSMR] = { 0x00, 8 },
199 [SCBRR] = { 0x02, 8 },
200 [SCSCR] = { 0x04, 8 },
201 [SCxTDR] = { 0x06, 8 },
202 [SCxSR] = { 0x08, 16 },
203 [SCxRDR] = { 0x0a, 8 },
204 [SCFCR] = { 0x0c, 8 },
205 [SCFDR] = { 0x0e, 16 },
206 },
207 .fifosize = 1,
208 .overrun_reg = SCxSR,
209 .overrun_mask = SCI_ORER,
210 .sampling_rate_mask = SCI_SR(32),
211 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
212 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
213 },
214
215 /*
216 * Common SCIFA definitions.
217 */
218 [SCIx_SCIFA_REGTYPE] = {
219 .regs = {
220 [SCSMR] = { 0x00, 16 },
221 [SCBRR] = { 0x04, 8 },
222 [SCSCR] = { 0x08, 16 },
223 [SCxTDR] = { 0x20, 8 },
224 [SCxSR] = { 0x14, 16 },
225 [SCxRDR] = { 0x24, 8 },
226 [SCFCR] = { 0x18, 16 },
227 [SCFDR] = { 0x1c, 16 },
228 [SCPCR] = { 0x30, 16 },
229 [SCPDR] = { 0x34, 16 },
230 },
231 .fifosize = 64,
232 .overrun_reg = SCxSR,
233 .overrun_mask = SCIFA_ORER,
234 .sampling_rate_mask = SCI_SR_SCIFAB,
235 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
236 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
237 },
238
239 /*
240 * Common SCIFB definitions.
241 */
242 [SCIx_SCIFB_REGTYPE] = {
243 .regs = {
244 [SCSMR] = { 0x00, 16 },
245 [SCBRR] = { 0x04, 8 },
246 [SCSCR] = { 0x08, 16 },
247 [SCxTDR] = { 0x40, 8 },
248 [SCxSR] = { 0x14, 16 },
249 [SCxRDR] = { 0x60, 8 },
250 [SCFCR] = { 0x18, 16 },
251 [SCTFDR] = { 0x38, 16 },
252 [SCRFDR] = { 0x3c, 16 },
253 [SCPCR] = { 0x30, 16 },
254 [SCPDR] = { 0x34, 16 },
255 },
256 .fifosize = 256,
257 .overrun_reg = SCxSR,
258 .overrun_mask = SCIFA_ORER,
259 .sampling_rate_mask = SCI_SR_SCIFAB,
260 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
261 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
262 },
263
264 /*
265 * Common SH-2(A) SCIF definitions for ports with FIFO data
266 * count registers.
267 */
268 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
269 .regs = {
270 [SCSMR] = { 0x00, 16 },
271 [SCBRR] = { 0x04, 8 },
272 [SCSCR] = { 0x08, 16 },
273 [SCxTDR] = { 0x0c, 8 },
274 [SCxSR] = { 0x10, 16 },
275 [SCxRDR] = { 0x14, 8 },
276 [SCFCR] = { 0x18, 16 },
277 [SCFDR] = { 0x1c, 16 },
278 [SCSPTR] = { 0x20, 16 },
279 [SCLSR] = { 0x24, 16 },
280 },
281 .fifosize = 16,
282 .overrun_reg = SCLSR,
283 .overrun_mask = SCLSR_ORER,
284 .sampling_rate_mask = SCI_SR(32),
285 .error_mask = SCIF_DEFAULT_ERROR_MASK,
286 .error_clear = SCIF_ERROR_CLEAR,
287 },
288
289 /*
290 * Common SH-3 SCIF definitions.
291 */
292 [SCIx_SH3_SCIF_REGTYPE] = {
293 .regs = {
294 [SCSMR] = { 0x00, 8 },
295 [SCBRR] = { 0x02, 8 },
296 [SCSCR] = { 0x04, 8 },
297 [SCxTDR] = { 0x06, 8 },
298 [SCxSR] = { 0x08, 16 },
299 [SCxRDR] = { 0x0a, 8 },
300 [SCFCR] = { 0x0c, 8 },
301 [SCFDR] = { 0x0e, 16 },
302 },
303 .fifosize = 16,
304 .overrun_reg = SCLSR,
305 .overrun_mask = SCLSR_ORER,
306 .sampling_rate_mask = SCI_SR(32),
307 .error_mask = SCIF_DEFAULT_ERROR_MASK,
308 .error_clear = SCIF_ERROR_CLEAR,
309 },
310
311 /*
312 * Common SH-4(A) SCIF(B) definitions.
313 */
314 [SCIx_SH4_SCIF_REGTYPE] = {
315 .regs = {
316 [SCSMR] = { 0x00, 16 },
317 [SCBRR] = { 0x04, 8 },
318 [SCSCR] = { 0x08, 16 },
319 [SCxTDR] = { 0x0c, 8 },
320 [SCxSR] = { 0x10, 16 },
321 [SCxRDR] = { 0x14, 8 },
322 [SCFCR] = { 0x18, 16 },
323 [SCFDR] = { 0x1c, 16 },
324 [SCSPTR] = { 0x20, 16 },
325 [SCLSR] = { 0x24, 16 },
326 },
327 .fifosize = 16,
328 .overrun_reg = SCLSR,
329 .overrun_mask = SCLSR_ORER,
330 .sampling_rate_mask = SCI_SR(32),
331 .error_mask = SCIF_DEFAULT_ERROR_MASK,
332 .error_clear = SCIF_ERROR_CLEAR,
333 },
334
335 /*
336 * Common SCIF definitions for ports with a Baud Rate Generator for
337 * External Clock (BRG).
338 */
339 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
340 .regs = {
341 [SCSMR] = { 0x00, 16 },
342 [SCBRR] = { 0x04, 8 },
343 [SCSCR] = { 0x08, 16 },
344 [SCxTDR] = { 0x0c, 8 },
345 [SCxSR] = { 0x10, 16 },
346 [SCxRDR] = { 0x14, 8 },
347 [SCFCR] = { 0x18, 16 },
348 [SCFDR] = { 0x1c, 16 },
349 [SCSPTR] = { 0x20, 16 },
350 [SCLSR] = { 0x24, 16 },
351 [SCDL] = { 0x30, 16 },
352 [SCCKS] = { 0x34, 16 },
353 },
354 .fifosize = 16,
355 .overrun_reg = SCLSR,
356 .overrun_mask = SCLSR_ORER,
357 .sampling_rate_mask = SCI_SR(32),
358 .error_mask = SCIF_DEFAULT_ERROR_MASK,
359 .error_clear = SCIF_ERROR_CLEAR,
360 },
361
362 /*
363 * Common HSCIF definitions.
364 */
365 [SCIx_HSCIF_REGTYPE] = {
366 .regs = {
367 [SCSMR] = { 0x00, 16 },
368 [SCBRR] = { 0x04, 8 },
369 [SCSCR] = { 0x08, 16 },
370 [SCxTDR] = { 0x0c, 8 },
371 [SCxSR] = { 0x10, 16 },
372 [SCxRDR] = { 0x14, 8 },
373 [SCFCR] = { 0x18, 16 },
374 [SCFDR] = { 0x1c, 16 },
375 [SCSPTR] = { 0x20, 16 },
376 [SCLSR] = { 0x24, 16 },
377 [HSSRR] = { 0x40, 16 },
378 [SCDL] = { 0x30, 16 },
379 [SCCKS] = { 0x34, 16 },
380 [HSRTRGR] = { 0x54, 16 },
381 [HSTTRGR] = { 0x58, 16 },
382 },
383 .fifosize = 128,
384 .overrun_reg = SCLSR,
385 .overrun_mask = SCLSR_ORER,
386 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
387 .error_mask = SCIF_DEFAULT_ERROR_MASK,
388 .error_clear = SCIF_ERROR_CLEAR,
389 },
390
391 /*
392 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
393 * register.
394 */
395 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
396 .regs = {
397 [SCSMR] = { 0x00, 16 },
398 [SCBRR] = { 0x04, 8 },
399 [SCSCR] = { 0x08, 16 },
400 [SCxTDR] = { 0x0c, 8 },
401 [SCxSR] = { 0x10, 16 },
402 [SCxRDR] = { 0x14, 8 },
403 [SCFCR] = { 0x18, 16 },
404 [SCFDR] = { 0x1c, 16 },
405 [SCLSR] = { 0x24, 16 },
406 },
407 .fifosize = 16,
408 .overrun_reg = SCLSR,
409 .overrun_mask = SCLSR_ORER,
410 .sampling_rate_mask = SCI_SR(32),
411 .error_mask = SCIF_DEFAULT_ERROR_MASK,
412 .error_clear = SCIF_ERROR_CLEAR,
413 },
414
415 /*
416 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
417 * count registers.
418 */
419 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
420 .regs = {
421 [SCSMR] = { 0x00, 16 },
422 [SCBRR] = { 0x04, 8 },
423 [SCSCR] = { 0x08, 16 },
424 [SCxTDR] = { 0x0c, 8 },
425 [SCxSR] = { 0x10, 16 },
426 [SCxRDR] = { 0x14, 8 },
427 [SCFCR] = { 0x18, 16 },
428 [SCFDR] = { 0x1c, 16 },
429 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
430 [SCRFDR] = { 0x20, 16 },
431 [SCSPTR] = { 0x24, 16 },
432 [SCLSR] = { 0x28, 16 },
433 },
434 .fifosize = 16,
435 .overrun_reg = SCLSR,
436 .overrun_mask = SCLSR_ORER,
437 .sampling_rate_mask = SCI_SR(32),
438 .error_mask = SCIF_DEFAULT_ERROR_MASK,
439 .error_clear = SCIF_ERROR_CLEAR,
440 },
441
442 /*
443 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
444 * registers.
445 */
446 [SCIx_SH7705_SCIF_REGTYPE] = {
447 .regs = {
448 [SCSMR] = { 0x00, 16 },
449 [SCBRR] = { 0x04, 8 },
450 [SCSCR] = { 0x08, 16 },
451 [SCxTDR] = { 0x20, 8 },
452 [SCxSR] = { 0x14, 16 },
453 [SCxRDR] = { 0x24, 8 },
454 [SCFCR] = { 0x18, 16 },
455 [SCFDR] = { 0x1c, 16 },
456 },
457 .fifosize = 64,
458 .overrun_reg = SCxSR,
459 .overrun_mask = SCIFA_ORER,
460 .sampling_rate_mask = SCI_SR(16),
461 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
462 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
463 },
464 };
465
466 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
467
468 /*
469 * The "offset" here is rather misleading, in that it refers to an enum
470 * value relative to the port mapping rather than the fixed offset
471 * itself, which needs to be manually retrieved from the platform's
472 * register map for the given port.
473 */
474 static unsigned int sci_serial_in(struct uart_port *p, int offset)
475 {
476 const struct plat_sci_reg *reg = sci_getreg(p, offset);
477
478 if (reg->size == 8)
479 return ioread8(p->membase + (reg->offset << p->regshift));
480 else if (reg->size == 16)
481 return ioread16(p->membase + (reg->offset << p->regshift));
482 else
483 WARN(1, "Invalid register access\n");
484
485 return 0;
486 }
487
488 static void sci_serial_out(struct uart_port *p, int offset, int value)
489 {
490 const struct plat_sci_reg *reg = sci_getreg(p, offset);
491
492 if (reg->size == 8)
493 iowrite8(value, p->membase + (reg->offset << p->regshift));
494 else if (reg->size == 16)
495 iowrite16(value, p->membase + (reg->offset << p->regshift));
496 else
497 WARN(1, "Invalid register access\n");
498 }
499
500 static void sci_port_enable(struct sci_port *sci_port)
501 {
502 unsigned int i;
503
504 if (!sci_port->port.dev)
505 return;
506
507 pm_runtime_get_sync(sci_port->port.dev);
508
509 for (i = 0; i < SCI_NUM_CLKS; i++) {
510 clk_prepare_enable(sci_port->clks[i]);
511 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
512 }
513 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
514 }
515
516 static void sci_port_disable(struct sci_port *sci_port)
517 {
518 unsigned int i;
519
520 if (!sci_port->port.dev)
521 return;
522
523 for (i = SCI_NUM_CLKS; i-- > 0; )
524 clk_disable_unprepare(sci_port->clks[i]);
525
526 pm_runtime_put_sync(sci_port->port.dev);
527 }
528
529 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
530 {
531 /*
532 * Not all ports (such as SCIFA) will support REIE. Rather than
533 * special-casing the port type, we check the port initialization
534 * IRQ enable mask to see whether the IRQ is desired at all. If
535 * it's unset, it's logically inferred that there's no point in
536 * testing for it.
537 */
538 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
539 }
540
541 static void sci_start_tx(struct uart_port *port)
542 {
543 struct sci_port *s = to_sci_port(port);
544 unsigned short ctrl;
545
546 #ifdef CONFIG_SERIAL_SH_SCI_DMA
547 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
548 u16 new, scr = serial_port_in(port, SCSCR);
549 if (s->chan_tx)
550 new = scr | SCSCR_TDRQE;
551 else
552 new = scr & ~SCSCR_TDRQE;
553 if (new != scr)
554 serial_port_out(port, SCSCR, new);
555 }
556
557 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
558 dma_submit_error(s->cookie_tx)) {
559 s->cookie_tx = 0;
560 schedule_work(&s->work_tx);
561 }
562 #endif
563
564 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
565 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
566 ctrl = serial_port_in(port, SCSCR);
567 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
568 }
569 }
570
571 static void sci_stop_tx(struct uart_port *port)
572 {
573 unsigned short ctrl;
574
575 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
576 ctrl = serial_port_in(port, SCSCR);
577
578 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
579 ctrl &= ~SCSCR_TDRQE;
580
581 ctrl &= ~SCSCR_TIE;
582
583 serial_port_out(port, SCSCR, ctrl);
584 }
585
586 static void sci_start_rx(struct uart_port *port)
587 {
588 unsigned short ctrl;
589
590 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
591
592 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
593 ctrl &= ~SCSCR_RDRQE;
594
595 serial_port_out(port, SCSCR, ctrl);
596 }
597
598 static void sci_stop_rx(struct uart_port *port)
599 {
600 unsigned short ctrl;
601
602 ctrl = serial_port_in(port, SCSCR);
603
604 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
605 ctrl &= ~SCSCR_RDRQE;
606
607 ctrl &= ~port_rx_irq_mask(port);
608
609 serial_port_out(port, SCSCR, ctrl);
610 }
611
612 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
613 {
614 if (port->type == PORT_SCI) {
615 /* Just store the mask */
616 serial_port_out(port, SCxSR, mask);
617 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
618 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
619 /* Only clear the status bits we want to clear */
620 serial_port_out(port, SCxSR,
621 serial_port_in(port, SCxSR) & mask);
622 } else {
623 /* Store the mask, clear parity/framing errors */
624 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
625 }
626 }
627
628 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
629 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
630
631 #ifdef CONFIG_CONSOLE_POLL
632 static int sci_poll_get_char(struct uart_port *port)
633 {
634 unsigned short status;
635 int c;
636
637 do {
638 status = serial_port_in(port, SCxSR);
639 if (status & SCxSR_ERRORS(port)) {
640 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
641 continue;
642 }
643 break;
644 } while (1);
645
646 if (!(status & SCxSR_RDxF(port)))
647 return NO_POLL_CHAR;
648
649 c = serial_port_in(port, SCxRDR);
650
651 /* Dummy read */
652 serial_port_in(port, SCxSR);
653 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
654
655 return c;
656 }
657 #endif
658
659 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
660 {
661 unsigned short status;
662
663 do {
664 status = serial_port_in(port, SCxSR);
665 } while (!(status & SCxSR_TDxE(port)));
666
667 serial_port_out(port, SCxTDR, c);
668 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
669 }
670 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
671 CONFIG_SERIAL_SH_SCI_EARLYCON */
672
673 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
674 {
675 struct sci_port *s = to_sci_port(port);
676
677 /*
678 * Use port-specific handler if provided.
679 */
680 if (s->cfg->ops && s->cfg->ops->init_pins) {
681 s->cfg->ops->init_pins(port, cflag);
682 return;
683 }
684
685 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
686 u16 data = serial_port_in(port, SCPDR);
687 u16 ctrl = serial_port_in(port, SCPCR);
688
689 /* Enable RXD and TXD pin functions */
690 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
691 if (to_sci_port(port)->has_rtscts) {
692 /* RTS# is output, active low, unless autorts */
693 if (!(port->mctrl & TIOCM_RTS)) {
694 ctrl |= SCPCR_RTSC;
695 data |= SCPDR_RTSD;
696 } else if (!s->autorts) {
697 ctrl |= SCPCR_RTSC;
698 data &= ~SCPDR_RTSD;
699 } else {
700 /* Enable RTS# pin function */
701 ctrl &= ~SCPCR_RTSC;
702 }
703 /* Enable CTS# pin function */
704 ctrl &= ~SCPCR_CTSC;
705 }
706 serial_port_out(port, SCPDR, data);
707 serial_port_out(port, SCPCR, ctrl);
708 } else if (sci_getreg(port, SCSPTR)->size) {
709 u16 status = serial_port_in(port, SCSPTR);
710
711 /* RTS# is always output; and active low, unless autorts */
712 status |= SCSPTR_RTSIO;
713 if (!(port->mctrl & TIOCM_RTS))
714 status |= SCSPTR_RTSDT;
715 else if (!s->autorts)
716 status &= ~SCSPTR_RTSDT;
717 /* CTS# and SCK are inputs */
718 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
719 serial_port_out(port, SCSPTR, status);
720 }
721 }
722
723 static int sci_txfill(struct uart_port *port)
724 {
725 struct sci_port *s = to_sci_port(port);
726 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
727 const struct plat_sci_reg *reg;
728
729 reg = sci_getreg(port, SCTFDR);
730 if (reg->size)
731 return serial_port_in(port, SCTFDR) & fifo_mask;
732
733 reg = sci_getreg(port, SCFDR);
734 if (reg->size)
735 return serial_port_in(port, SCFDR) >> 8;
736
737 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
738 }
739
740 static int sci_txroom(struct uart_port *port)
741 {
742 return port->fifosize - sci_txfill(port);
743 }
744
745 static int sci_rxfill(struct uart_port *port)
746 {
747 struct sci_port *s = to_sci_port(port);
748 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
749 const struct plat_sci_reg *reg;
750
751 reg = sci_getreg(port, SCRFDR);
752 if (reg->size)
753 return serial_port_in(port, SCRFDR) & fifo_mask;
754
755 reg = sci_getreg(port, SCFDR);
756 if (reg->size)
757 return serial_port_in(port, SCFDR) & fifo_mask;
758
759 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
760 }
761
762 /* ********************************************************************** *
763 * the interrupt related routines *
764 * ********************************************************************** */
765
766 static void sci_transmit_chars(struct uart_port *port)
767 {
768 struct circ_buf *xmit = &port->state->xmit;
769 unsigned int stopped = uart_tx_stopped(port);
770 unsigned short status;
771 unsigned short ctrl;
772 int count;
773
774 status = serial_port_in(port, SCxSR);
775 if (!(status & SCxSR_TDxE(port))) {
776 ctrl = serial_port_in(port, SCSCR);
777 if (uart_circ_empty(xmit))
778 ctrl &= ~SCSCR_TIE;
779 else
780 ctrl |= SCSCR_TIE;
781 serial_port_out(port, SCSCR, ctrl);
782 return;
783 }
784
785 count = sci_txroom(port);
786
787 do {
788 unsigned char c;
789
790 if (port->x_char) {
791 c = port->x_char;
792 port->x_char = 0;
793 } else if (!uart_circ_empty(xmit) && !stopped) {
794 c = xmit->buf[xmit->tail];
795 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
796 } else {
797 break;
798 }
799
800 serial_port_out(port, SCxTDR, c);
801
802 port->icount.tx++;
803 } while (--count > 0);
804
805 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
806
807 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
808 uart_write_wakeup(port);
809 if (uart_circ_empty(xmit)) {
810 sci_stop_tx(port);
811 } else {
812 ctrl = serial_port_in(port, SCSCR);
813
814 if (port->type != PORT_SCI) {
815 serial_port_in(port, SCxSR); /* Dummy read */
816 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
817 }
818
819 ctrl |= SCSCR_TIE;
820 serial_port_out(port, SCSCR, ctrl);
821 }
822 }
823
824 /* On SH3, SCIF may read end-of-break as a space->mark char */
825 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
826
827 static void sci_receive_chars(struct uart_port *port)
828 {
829 struct tty_port *tport = &port->state->port;
830 int i, count, copied = 0;
831 unsigned short status;
832 unsigned char flag;
833
834 status = serial_port_in(port, SCxSR);
835 if (!(status & SCxSR_RDxF(port)))
836 return;
837
838 while (1) {
839 /* Don't copy more bytes than there is room for in the buffer */
840 count = tty_buffer_request_room(tport, sci_rxfill(port));
841
842 /* If for any reason we can't copy more data, we're done! */
843 if (count == 0)
844 break;
845
846 if (port->type == PORT_SCI) {
847 char c = serial_port_in(port, SCxRDR);
848 if (uart_handle_sysrq_char(port, c))
849 count = 0;
850 else
851 tty_insert_flip_char(tport, c, TTY_NORMAL);
852 } else {
853 for (i = 0; i < count; i++) {
854 char c = serial_port_in(port, SCxRDR);
855
856 status = serial_port_in(port, SCxSR);
857 if (uart_handle_sysrq_char(port, c)) {
858 count--; i--;
859 continue;
860 }
861
862 /* Store data and status */
863 if (status & SCxSR_FER(port)) {
864 flag = TTY_FRAME;
865 port->icount.frame++;
866 dev_notice(port->dev, "frame error\n");
867 } else if (status & SCxSR_PER(port)) {
868 flag = TTY_PARITY;
869 port->icount.parity++;
870 dev_notice(port->dev, "parity error\n");
871 } else
872 flag = TTY_NORMAL;
873
874 tty_insert_flip_char(tport, c, flag);
875 }
876 }
877
878 serial_port_in(port, SCxSR); /* dummy read */
879 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
880
881 copied += count;
882 port->icount.rx += count;
883 }
884
885 if (copied) {
886 /* Tell the rest of the system the news. New characters! */
887 tty_flip_buffer_push(tport);
888 } else {
889 serial_port_in(port, SCxSR); /* dummy read */
890 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
891 }
892 }
893
894 static int sci_handle_errors(struct uart_port *port)
895 {
896 int copied = 0;
897 unsigned short status = serial_port_in(port, SCxSR);
898 struct tty_port *tport = &port->state->port;
899 struct sci_port *s = to_sci_port(port);
900
901 /* Handle overruns */
902 if (status & s->params->overrun_mask) {
903 port->icount.overrun++;
904
905 /* overrun error */
906 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
907 copied++;
908
909 dev_notice(port->dev, "overrun error\n");
910 }
911
912 if (status & SCxSR_FER(port)) {
913 /* frame error */
914 port->icount.frame++;
915
916 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
917 copied++;
918
919 dev_notice(port->dev, "frame error\n");
920 }
921
922 if (status & SCxSR_PER(port)) {
923 /* parity error */
924 port->icount.parity++;
925
926 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
927 copied++;
928
929 dev_notice(port->dev, "parity error\n");
930 }
931
932 if (copied)
933 tty_flip_buffer_push(tport);
934
935 return copied;
936 }
937
938 static int sci_handle_fifo_overrun(struct uart_port *port)
939 {
940 struct tty_port *tport = &port->state->port;
941 struct sci_port *s = to_sci_port(port);
942 const struct plat_sci_reg *reg;
943 int copied = 0;
944 u16 status;
945
946 reg = sci_getreg(port, s->params->overrun_reg);
947 if (!reg->size)
948 return 0;
949
950 status = serial_port_in(port, s->params->overrun_reg);
951 if (status & s->params->overrun_mask) {
952 status &= ~s->params->overrun_mask;
953 serial_port_out(port, s->params->overrun_reg, status);
954
955 port->icount.overrun++;
956
957 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
958 tty_flip_buffer_push(tport);
959
960 dev_dbg(port->dev, "overrun error\n");
961 copied++;
962 }
963
964 return copied;
965 }
966
967 static int sci_handle_breaks(struct uart_port *port)
968 {
969 int copied = 0;
970 unsigned short status = serial_port_in(port, SCxSR);
971 struct tty_port *tport = &port->state->port;
972
973 if (uart_handle_break(port))
974 return 0;
975
976 if (status & SCxSR_BRK(port)) {
977 port->icount.brk++;
978
979 /* Notify of BREAK */
980 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
981 copied++;
982
983 dev_dbg(port->dev, "BREAK detected\n");
984 }
985
986 if (copied)
987 tty_flip_buffer_push(tport);
988
989 copied += sci_handle_fifo_overrun(port);
990
991 return copied;
992 }
993
994 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
995 {
996 unsigned int bits;
997
998 if (rx_trig < 1)
999 rx_trig = 1;
1000 if (rx_trig >= port->fifosize)
1001 rx_trig = port->fifosize;
1002
1003 /* HSCIF can be set to an arbitrary level. */
1004 if (sci_getreg(port, HSRTRGR)->size) {
1005 serial_port_out(port, HSRTRGR, rx_trig);
1006 return rx_trig;
1007 }
1008
1009 switch (port->type) {
1010 case PORT_SCIF:
1011 if (rx_trig < 4) {
1012 bits = 0;
1013 rx_trig = 1;
1014 } else if (rx_trig < 8) {
1015 bits = SCFCR_RTRG0;
1016 rx_trig = 4;
1017 } else if (rx_trig < 14) {
1018 bits = SCFCR_RTRG1;
1019 rx_trig = 8;
1020 } else {
1021 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1022 rx_trig = 14;
1023 }
1024 break;
1025 case PORT_SCIFA:
1026 case PORT_SCIFB:
1027 if (rx_trig < 16) {
1028 bits = 0;
1029 rx_trig = 1;
1030 } else if (rx_trig < 32) {
1031 bits = SCFCR_RTRG0;
1032 rx_trig = 16;
1033 } else if (rx_trig < 48) {
1034 bits = SCFCR_RTRG1;
1035 rx_trig = 32;
1036 } else {
1037 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1038 rx_trig = 48;
1039 }
1040 break;
1041 default:
1042 WARN(1, "unknown FIFO configuration");
1043 return 1;
1044 }
1045
1046 serial_port_out(port, SCFCR,
1047 (serial_port_in(port, SCFCR) &
1048 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1049
1050 return rx_trig;
1051 }
1052
1053 static int scif_rtrg_enabled(struct uart_port *port)
1054 {
1055 if (sci_getreg(port, HSRTRGR)->size)
1056 return serial_port_in(port, HSRTRGR) != 0;
1057 else
1058 return (serial_port_in(port, SCFCR) &
1059 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1060 }
1061
1062 static void rx_fifo_timer_fn(unsigned long arg)
1063 {
1064 struct sci_port *s = (struct sci_port *)arg;
1065 struct uart_port *port = &s->port;
1066
1067 dev_dbg(port->dev, "Rx timed out\n");
1068 scif_set_rtrg(port, 1);
1069 }
1070
1071 static ssize_t rx_trigger_show(struct device *dev,
1072 struct device_attribute *attr,
1073 char *buf)
1074 {
1075 struct uart_port *port = dev_get_drvdata(dev);
1076 struct sci_port *sci = to_sci_port(port);
1077
1078 return sprintf(buf, "%d\n", sci->rx_trigger);
1079 }
1080
1081 static ssize_t rx_trigger_store(struct device *dev,
1082 struct device_attribute *attr,
1083 const char *buf,
1084 size_t count)
1085 {
1086 struct uart_port *port = dev_get_drvdata(dev);
1087 struct sci_port *sci = to_sci_port(port);
1088 long r;
1089
1090 if (kstrtol(buf, 0, &r) == -EINVAL)
1091 return -EINVAL;
1092
1093 sci->rx_trigger = scif_set_rtrg(port, r);
1094 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1095 scif_set_rtrg(port, 1);
1096
1097 return count;
1098 }
1099
1100 static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store);
1101
1102 static ssize_t rx_fifo_timeout_show(struct device *dev,
1103 struct device_attribute *attr,
1104 char *buf)
1105 {
1106 struct uart_port *port = dev_get_drvdata(dev);
1107 struct sci_port *sci = to_sci_port(port);
1108
1109 return sprintf(buf, "%d\n", sci->rx_fifo_timeout);
1110 }
1111
1112 static ssize_t rx_fifo_timeout_store(struct device *dev,
1113 struct device_attribute *attr,
1114 const char *buf,
1115 size_t count)
1116 {
1117 struct uart_port *port = dev_get_drvdata(dev);
1118 struct sci_port *sci = to_sci_port(port);
1119 long r;
1120
1121 if (kstrtol(buf, 0, &r) == -EINVAL)
1122 return -EINVAL;
1123 sci->rx_fifo_timeout = r;
1124 scif_set_rtrg(port, 1);
1125 if (r > 0)
1126 setup_timer(&sci->rx_fifo_timer, rx_fifo_timer_fn,
1127 (unsigned long)sci);
1128 return count;
1129 }
1130
1131 static DEVICE_ATTR(rx_fifo_timeout, 0644, rx_fifo_timeout_show, rx_fifo_timeout_store);
1132
1133
1134 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1135 static void sci_dma_tx_complete(void *arg)
1136 {
1137 struct sci_port *s = arg;
1138 struct uart_port *port = &s->port;
1139 struct circ_buf *xmit = &port->state->xmit;
1140 unsigned long flags;
1141
1142 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1143
1144 spin_lock_irqsave(&port->lock, flags);
1145
1146 xmit->tail += s->tx_dma_len;
1147 xmit->tail &= UART_XMIT_SIZE - 1;
1148
1149 port->icount.tx += s->tx_dma_len;
1150
1151 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1152 uart_write_wakeup(port);
1153
1154 if (!uart_circ_empty(xmit)) {
1155 s->cookie_tx = 0;
1156 schedule_work(&s->work_tx);
1157 } else {
1158 s->cookie_tx = -EINVAL;
1159 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1160 u16 ctrl = serial_port_in(port, SCSCR);
1161 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1162 }
1163 }
1164
1165 spin_unlock_irqrestore(&port->lock, flags);
1166 }
1167
1168 /* Locking: called with port lock held */
1169 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1170 {
1171 struct uart_port *port = &s->port;
1172 struct tty_port *tport = &port->state->port;
1173 int copied;
1174
1175 copied = tty_insert_flip_string(tport, buf, count);
1176 if (copied < count)
1177 port->icount.buf_overrun++;
1178
1179 port->icount.rx += copied;
1180
1181 return copied;
1182 }
1183
1184 static int sci_dma_rx_find_active(struct sci_port *s)
1185 {
1186 unsigned int i;
1187
1188 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1189 if (s->active_rx == s->cookie_rx[i])
1190 return i;
1191
1192 return -1;
1193 }
1194
1195 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1196 {
1197 struct dma_chan *chan = s->chan_rx;
1198 struct uart_port *port = &s->port;
1199 unsigned long flags;
1200
1201 spin_lock_irqsave(&port->lock, flags);
1202 s->chan_rx = NULL;
1203 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1204 spin_unlock_irqrestore(&port->lock, flags);
1205 dmaengine_terminate_all(chan);
1206 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1207 sg_dma_address(&s->sg_rx[0]));
1208 dma_release_channel(chan);
1209 if (enable_pio)
1210 sci_start_rx(port);
1211 }
1212
1213 static void sci_dma_rx_complete(void *arg)
1214 {
1215 struct sci_port *s = arg;
1216 struct dma_chan *chan = s->chan_rx;
1217 struct uart_port *port = &s->port;
1218 struct dma_async_tx_descriptor *desc;
1219 unsigned long flags;
1220 int active, count = 0;
1221
1222 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1223 s->active_rx);
1224
1225 spin_lock_irqsave(&port->lock, flags);
1226
1227 active = sci_dma_rx_find_active(s);
1228 if (active >= 0)
1229 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1230
1231 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1232
1233 if (count)
1234 tty_flip_buffer_push(&port->state->port);
1235
1236 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1237 DMA_DEV_TO_MEM,
1238 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1239 if (!desc)
1240 goto fail;
1241
1242 desc->callback = sci_dma_rx_complete;
1243 desc->callback_param = s;
1244 s->cookie_rx[active] = dmaengine_submit(desc);
1245 if (dma_submit_error(s->cookie_rx[active]))
1246 goto fail;
1247
1248 s->active_rx = s->cookie_rx[!active];
1249
1250 dma_async_issue_pending(chan);
1251
1252 spin_unlock_irqrestore(&port->lock, flags);
1253 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1254 __func__, s->cookie_rx[active], active, s->active_rx);
1255 return;
1256
1257 fail:
1258 spin_unlock_irqrestore(&port->lock, flags);
1259 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1260 sci_rx_dma_release(s, true);
1261 }
1262
1263 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1264 {
1265 struct dma_chan *chan = s->chan_tx;
1266 struct uart_port *port = &s->port;
1267 unsigned long flags;
1268
1269 spin_lock_irqsave(&port->lock, flags);
1270 s->chan_tx = NULL;
1271 s->cookie_tx = -EINVAL;
1272 spin_unlock_irqrestore(&port->lock, flags);
1273 dmaengine_terminate_all(chan);
1274 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1275 DMA_TO_DEVICE);
1276 dma_release_channel(chan);
1277 if (enable_pio)
1278 sci_start_tx(port);
1279 }
1280
1281 static void sci_submit_rx(struct sci_port *s)
1282 {
1283 struct dma_chan *chan = s->chan_rx;
1284 int i;
1285
1286 for (i = 0; i < 2; i++) {
1287 struct scatterlist *sg = &s->sg_rx[i];
1288 struct dma_async_tx_descriptor *desc;
1289
1290 desc = dmaengine_prep_slave_sg(chan,
1291 sg, 1, DMA_DEV_TO_MEM,
1292 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1293 if (!desc)
1294 goto fail;
1295
1296 desc->callback = sci_dma_rx_complete;
1297 desc->callback_param = s;
1298 s->cookie_rx[i] = dmaengine_submit(desc);
1299 if (dma_submit_error(s->cookie_rx[i]))
1300 goto fail;
1301
1302 }
1303
1304 s->active_rx = s->cookie_rx[0];
1305
1306 dma_async_issue_pending(chan);
1307 return;
1308
1309 fail:
1310 if (i)
1311 dmaengine_terminate_all(chan);
1312 for (i = 0; i < 2; i++)
1313 s->cookie_rx[i] = -EINVAL;
1314 s->active_rx = -EINVAL;
1315 sci_rx_dma_release(s, true);
1316 }
1317
1318 static void work_fn_tx(struct work_struct *work)
1319 {
1320 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1321 struct dma_async_tx_descriptor *desc;
1322 struct dma_chan *chan = s->chan_tx;
1323 struct uart_port *port = &s->port;
1324 struct circ_buf *xmit = &port->state->xmit;
1325 dma_addr_t buf;
1326
1327 /*
1328 * DMA is idle now.
1329 * Port xmit buffer is already mapped, and it is one page... Just adjust
1330 * offsets and lengths. Since it is a circular buffer, we have to
1331 * transmit till the end, and then the rest. Take the port lock to get a
1332 * consistent xmit buffer state.
1333 */
1334 spin_lock_irq(&port->lock);
1335 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1336 s->tx_dma_len = min_t(unsigned int,
1337 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1338 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1339 spin_unlock_irq(&port->lock);
1340
1341 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1342 DMA_MEM_TO_DEV,
1343 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1344 if (!desc) {
1345 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1346 /* switch to PIO */
1347 sci_tx_dma_release(s, true);
1348 return;
1349 }
1350
1351 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1352 DMA_TO_DEVICE);
1353
1354 spin_lock_irq(&port->lock);
1355 desc->callback = sci_dma_tx_complete;
1356 desc->callback_param = s;
1357 spin_unlock_irq(&port->lock);
1358 s->cookie_tx = dmaengine_submit(desc);
1359 if (dma_submit_error(s->cookie_tx)) {
1360 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1361 /* switch to PIO */
1362 sci_tx_dma_release(s, true);
1363 return;
1364 }
1365
1366 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1367 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1368
1369 dma_async_issue_pending(chan);
1370 }
1371
1372 static void rx_timer_fn(unsigned long arg)
1373 {
1374 struct sci_port *s = (struct sci_port *)arg;
1375 struct dma_chan *chan = s->chan_rx;
1376 struct uart_port *port = &s->port;
1377 struct dma_tx_state state;
1378 enum dma_status status;
1379 unsigned long flags;
1380 unsigned int read;
1381 int active, count;
1382 u16 scr;
1383
1384 dev_dbg(port->dev, "DMA Rx timed out\n");
1385
1386 spin_lock_irqsave(&port->lock, flags);
1387
1388 active = sci_dma_rx_find_active(s);
1389 if (active < 0) {
1390 spin_unlock_irqrestore(&port->lock, flags);
1391 return;
1392 }
1393
1394 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1395 if (status == DMA_COMPLETE) {
1396 spin_unlock_irqrestore(&port->lock, flags);
1397 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1398 s->active_rx, active);
1399
1400 /* Let packet complete handler take care of the packet */
1401 return;
1402 }
1403
1404 dmaengine_pause(chan);
1405
1406 /*
1407 * sometimes DMA transfer doesn't stop even if it is stopped and
1408 * data keeps on coming until transaction is complete so check
1409 * for DMA_COMPLETE again
1410 * Let packet complete handler take care of the packet
1411 */
1412 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1413 if (status == DMA_COMPLETE) {
1414 spin_unlock_irqrestore(&port->lock, flags);
1415 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1416 return;
1417 }
1418
1419 /* Handle incomplete DMA receive */
1420 dmaengine_terminate_all(s->chan_rx);
1421 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1422
1423 if (read) {
1424 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1425 if (count)
1426 tty_flip_buffer_push(&port->state->port);
1427 }
1428
1429 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1430 sci_submit_rx(s);
1431
1432 /* Direct new serial port interrupts back to CPU */
1433 scr = serial_port_in(port, SCSCR);
1434 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1435 scr &= ~SCSCR_RDRQE;
1436 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1437 }
1438 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1439
1440 spin_unlock_irqrestore(&port->lock, flags);
1441 }
1442
1443 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1444 enum dma_transfer_direction dir)
1445 {
1446 struct dma_chan *chan;
1447 struct dma_slave_config cfg;
1448 int ret;
1449
1450 chan = dma_request_slave_channel(port->dev,
1451 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1452 if (!chan) {
1453 dev_warn(port->dev, "dma_request_slave_channel failed\n");
1454 return NULL;
1455 }
1456
1457 memset(&cfg, 0, sizeof(cfg));
1458 cfg.direction = dir;
1459 if (dir == DMA_MEM_TO_DEV) {
1460 cfg.dst_addr = port->mapbase +
1461 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1462 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1463 } else {
1464 cfg.src_addr = port->mapbase +
1465 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1466 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1467 }
1468
1469 ret = dmaengine_slave_config(chan, &cfg);
1470 if (ret) {
1471 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1472 dma_release_channel(chan);
1473 return NULL;
1474 }
1475
1476 return chan;
1477 }
1478
1479 static void sci_request_dma(struct uart_port *port)
1480 {
1481 struct sci_port *s = to_sci_port(port);
1482 struct dma_chan *chan;
1483
1484 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1485
1486 if (!port->dev->of_node)
1487 return;
1488
1489 s->cookie_tx = -EINVAL;
1490 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1491 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1492 if (chan) {
1493 s->chan_tx = chan;
1494 /* UART circular tx buffer is an aligned page. */
1495 s->tx_dma_addr = dma_map_single(chan->device->dev,
1496 port->state->xmit.buf,
1497 UART_XMIT_SIZE,
1498 DMA_TO_DEVICE);
1499 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1500 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1501 dma_release_channel(chan);
1502 s->chan_tx = NULL;
1503 } else {
1504 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1505 __func__, UART_XMIT_SIZE,
1506 port->state->xmit.buf, &s->tx_dma_addr);
1507 }
1508
1509 INIT_WORK(&s->work_tx, work_fn_tx);
1510 }
1511
1512 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1513 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1514 if (chan) {
1515 unsigned int i;
1516 dma_addr_t dma;
1517 void *buf;
1518
1519 s->chan_rx = chan;
1520
1521 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1522 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1523 &dma, GFP_KERNEL);
1524 if (!buf) {
1525 dev_warn(port->dev,
1526 "Failed to allocate Rx dma buffer, using PIO\n");
1527 dma_release_channel(chan);
1528 s->chan_rx = NULL;
1529 return;
1530 }
1531
1532 for (i = 0; i < 2; i++) {
1533 struct scatterlist *sg = &s->sg_rx[i];
1534
1535 sg_init_table(sg, 1);
1536 s->rx_buf[i] = buf;
1537 sg_dma_address(sg) = dma;
1538 sg_dma_len(sg) = s->buf_len_rx;
1539
1540 buf += s->buf_len_rx;
1541 dma += s->buf_len_rx;
1542 }
1543
1544 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1545
1546 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1547 sci_submit_rx(s);
1548 }
1549 }
1550
1551 static void sci_free_dma(struct uart_port *port)
1552 {
1553 struct sci_port *s = to_sci_port(port);
1554
1555 if (s->chan_tx)
1556 sci_tx_dma_release(s, false);
1557 if (s->chan_rx)
1558 sci_rx_dma_release(s, false);
1559 }
1560
1561 static void sci_flush_buffer(struct uart_port *port)
1562 {
1563 /*
1564 * In uart_flush_buffer(), the xmit circular buffer has just been
1565 * cleared, so we have to reset tx_dma_len accordingly.
1566 */
1567 to_sci_port(port)->tx_dma_len = 0;
1568 }
1569 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
1570 static inline void sci_request_dma(struct uart_port *port)
1571 {
1572 }
1573
1574 static inline void sci_free_dma(struct uart_port *port)
1575 {
1576 }
1577
1578 #define sci_flush_buffer NULL
1579 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1580
1581 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1582 {
1583 struct uart_port *port = ptr;
1584 struct sci_port *s = to_sci_port(port);
1585
1586 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1587 if (s->chan_rx) {
1588 u16 scr = serial_port_in(port, SCSCR);
1589 u16 ssr = serial_port_in(port, SCxSR);
1590
1591 /* Disable future Rx interrupts */
1592 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1593 disable_irq_nosync(irq);
1594 scr |= SCSCR_RDRQE;
1595 } else {
1596 scr &= ~SCSCR_RIE;
1597 sci_submit_rx(s);
1598 }
1599 serial_port_out(port, SCSCR, scr);
1600 /* Clear current interrupt */
1601 serial_port_out(port, SCxSR,
1602 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1603 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1604 jiffies, s->rx_timeout);
1605 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1606
1607 return IRQ_HANDLED;
1608 }
1609 #endif
1610
1611 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1612 if (!scif_rtrg_enabled(port))
1613 scif_set_rtrg(port, s->rx_trigger);
1614
1615 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1616 s->rx_frame * s->rx_fifo_timeout, 1000));
1617 }
1618
1619 /* I think sci_receive_chars has to be called irrespective
1620 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1621 * to be disabled?
1622 */
1623 sci_receive_chars(ptr);
1624
1625 return IRQ_HANDLED;
1626 }
1627
1628 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1629 {
1630 struct uart_port *port = ptr;
1631 unsigned long flags;
1632
1633 spin_lock_irqsave(&port->lock, flags);
1634 sci_transmit_chars(port);
1635 spin_unlock_irqrestore(&port->lock, flags);
1636
1637 return IRQ_HANDLED;
1638 }
1639
1640 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1641 {
1642 struct uart_port *port = ptr;
1643 struct sci_port *s = to_sci_port(port);
1644
1645 /* Handle errors */
1646 if (port->type == PORT_SCI) {
1647 if (sci_handle_errors(port)) {
1648 /* discard character in rx buffer */
1649 serial_port_in(port, SCxSR);
1650 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1651 }
1652 } else {
1653 sci_handle_fifo_overrun(port);
1654 if (!s->chan_rx)
1655 sci_receive_chars(ptr);
1656 }
1657
1658 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1659
1660 /* Kick the transmission */
1661 if (!s->chan_tx)
1662 sci_tx_interrupt(irq, ptr);
1663
1664 return IRQ_HANDLED;
1665 }
1666
1667 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1668 {
1669 struct uart_port *port = ptr;
1670
1671 /* Handle BREAKs */
1672 sci_handle_breaks(port);
1673 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1674
1675 return IRQ_HANDLED;
1676 }
1677
1678 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1679 {
1680 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1681 struct uart_port *port = ptr;
1682 struct sci_port *s = to_sci_port(port);
1683 irqreturn_t ret = IRQ_NONE;
1684
1685 ssr_status = serial_port_in(port, SCxSR);
1686 scr_status = serial_port_in(port, SCSCR);
1687 if (s->params->overrun_reg == SCxSR)
1688 orer_status = ssr_status;
1689 else if (sci_getreg(port, s->params->overrun_reg)->size)
1690 orer_status = serial_port_in(port, s->params->overrun_reg);
1691
1692 err_enabled = scr_status & port_rx_irq_mask(port);
1693
1694 /* Tx Interrupt */
1695 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1696 !s->chan_tx)
1697 ret = sci_tx_interrupt(irq, ptr);
1698
1699 /*
1700 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1701 * DR flags
1702 */
1703 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1704 (scr_status & SCSCR_RIE))
1705 ret = sci_rx_interrupt(irq, ptr);
1706
1707 /* Error Interrupt */
1708 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1709 ret = sci_er_interrupt(irq, ptr);
1710
1711 /* Break Interrupt */
1712 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1713 ret = sci_br_interrupt(irq, ptr);
1714
1715 /* Overrun Interrupt */
1716 if (orer_status & s->params->overrun_mask) {
1717 sci_handle_fifo_overrun(port);
1718 ret = IRQ_HANDLED;
1719 }
1720
1721 return ret;
1722 }
1723
1724 static const struct sci_irq_desc {
1725 const char *desc;
1726 irq_handler_t handler;
1727 } sci_irq_desc[] = {
1728 /*
1729 * Split out handlers, the default case.
1730 */
1731 [SCIx_ERI_IRQ] = {
1732 .desc = "rx err",
1733 .handler = sci_er_interrupt,
1734 },
1735
1736 [SCIx_RXI_IRQ] = {
1737 .desc = "rx full",
1738 .handler = sci_rx_interrupt,
1739 },
1740
1741 [SCIx_TXI_IRQ] = {
1742 .desc = "tx empty",
1743 .handler = sci_tx_interrupt,
1744 },
1745
1746 [SCIx_BRI_IRQ] = {
1747 .desc = "break",
1748 .handler = sci_br_interrupt,
1749 },
1750
1751 /*
1752 * Special muxed handler.
1753 */
1754 [SCIx_MUX_IRQ] = {
1755 .desc = "mux",
1756 .handler = sci_mpxed_interrupt,
1757 },
1758 };
1759
1760 static int sci_request_irq(struct sci_port *port)
1761 {
1762 struct uart_port *up = &port->port;
1763 int i, j, ret = 0;
1764
1765 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1766 const struct sci_irq_desc *desc;
1767 int irq;
1768
1769 if (SCIx_IRQ_IS_MUXED(port)) {
1770 i = SCIx_MUX_IRQ;
1771 irq = up->irq;
1772 } else {
1773 irq = port->irqs[i];
1774
1775 /*
1776 * Certain port types won't support all of the
1777 * available interrupt sources.
1778 */
1779 if (unlikely(irq < 0))
1780 continue;
1781 }
1782
1783 desc = sci_irq_desc + i;
1784 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1785 dev_name(up->dev), desc->desc);
1786 if (!port->irqstr[j]) {
1787 ret = -ENOMEM;
1788 goto out_nomem;
1789 }
1790
1791 ret = request_irq(irq, desc->handler, up->irqflags,
1792 port->irqstr[j], port);
1793 if (unlikely(ret)) {
1794 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1795 goto out_noirq;
1796 }
1797 }
1798
1799 return 0;
1800
1801 out_noirq:
1802 while (--i >= 0)
1803 free_irq(port->irqs[i], port);
1804
1805 out_nomem:
1806 while (--j >= 0)
1807 kfree(port->irqstr[j]);
1808
1809 return ret;
1810 }
1811
1812 static void sci_free_irq(struct sci_port *port)
1813 {
1814 int i;
1815
1816 /*
1817 * Intentionally in reverse order so we iterate over the muxed
1818 * IRQ first.
1819 */
1820 for (i = 0; i < SCIx_NR_IRQS; i++) {
1821 int irq = port->irqs[i];
1822
1823 /*
1824 * Certain port types won't support all of the available
1825 * interrupt sources.
1826 */
1827 if (unlikely(irq < 0))
1828 continue;
1829
1830 free_irq(port->irqs[i], port);
1831 kfree(port->irqstr[i]);
1832
1833 if (SCIx_IRQ_IS_MUXED(port)) {
1834 /* If there's only one IRQ, we're done. */
1835 return;
1836 }
1837 }
1838 }
1839
1840 static unsigned int sci_tx_empty(struct uart_port *port)
1841 {
1842 unsigned short status = serial_port_in(port, SCxSR);
1843 unsigned short in_tx_fifo = sci_txfill(port);
1844
1845 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1846 }
1847
1848 static void sci_set_rts(struct uart_port *port, bool state)
1849 {
1850 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1851 u16 data = serial_port_in(port, SCPDR);
1852
1853 /* Active low */
1854 if (state)
1855 data &= ~SCPDR_RTSD;
1856 else
1857 data |= SCPDR_RTSD;
1858 serial_port_out(port, SCPDR, data);
1859
1860 /* RTS# is output */
1861 serial_port_out(port, SCPCR,
1862 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1863 } else if (sci_getreg(port, SCSPTR)->size) {
1864 u16 ctrl = serial_port_in(port, SCSPTR);
1865
1866 /* Active low */
1867 if (state)
1868 ctrl &= ~SCSPTR_RTSDT;
1869 else
1870 ctrl |= SCSPTR_RTSDT;
1871 serial_port_out(port, SCSPTR, ctrl);
1872 }
1873 }
1874
1875 static bool sci_get_cts(struct uart_port *port)
1876 {
1877 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1878 /* Active low */
1879 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
1880 } else if (sci_getreg(port, SCSPTR)->size) {
1881 /* Active low */
1882 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
1883 }
1884
1885 return true;
1886 }
1887
1888 /*
1889 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1890 * CTS/RTS is supported in hardware by at least one port and controlled
1891 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1892 * handled via the ->init_pins() op, which is a bit of a one-way street,
1893 * lacking any ability to defer pin control -- this will later be
1894 * converted over to the GPIO framework).
1895 *
1896 * Other modes (such as loopback) are supported generically on certain
1897 * port types, but not others. For these it's sufficient to test for the
1898 * existence of the support register and simply ignore the port type.
1899 */
1900 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1901 {
1902 struct sci_port *s = to_sci_port(port);
1903
1904 if (mctrl & TIOCM_LOOP) {
1905 const struct plat_sci_reg *reg;
1906
1907 /*
1908 * Standard loopback mode for SCFCR ports.
1909 */
1910 reg = sci_getreg(port, SCFCR);
1911 if (reg->size)
1912 serial_port_out(port, SCFCR,
1913 serial_port_in(port, SCFCR) |
1914 SCFCR_LOOP);
1915 }
1916
1917 mctrl_gpio_set(s->gpios, mctrl);
1918
1919 if (!s->has_rtscts)
1920 return;
1921
1922 if (!(mctrl & TIOCM_RTS)) {
1923 /* Disable Auto RTS */
1924 serial_port_out(port, SCFCR,
1925 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
1926
1927 /* Clear RTS */
1928 sci_set_rts(port, 0);
1929 } else if (s->autorts) {
1930 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1931 /* Enable RTS# pin function */
1932 serial_port_out(port, SCPCR,
1933 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
1934 }
1935
1936 /* Enable Auto RTS */
1937 serial_port_out(port, SCFCR,
1938 serial_port_in(port, SCFCR) | SCFCR_MCE);
1939 } else {
1940 /* Set RTS */
1941 sci_set_rts(port, 1);
1942 }
1943 }
1944
1945 static unsigned int sci_get_mctrl(struct uart_port *port)
1946 {
1947 struct sci_port *s = to_sci_port(port);
1948 struct mctrl_gpios *gpios = s->gpios;
1949 unsigned int mctrl = 0;
1950
1951 mctrl_gpio_get(gpios, &mctrl);
1952
1953 /*
1954 * CTS/RTS is handled in hardware when supported, while nothing
1955 * else is wired up.
1956 */
1957 if (s->autorts) {
1958 if (sci_get_cts(port))
1959 mctrl |= TIOCM_CTS;
1960 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
1961 mctrl |= TIOCM_CTS;
1962 }
1963 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
1964 mctrl |= TIOCM_DSR;
1965 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
1966 mctrl |= TIOCM_CAR;
1967
1968 return mctrl;
1969 }
1970
1971 static void sci_enable_ms(struct uart_port *port)
1972 {
1973 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
1974 }
1975
1976 static void sci_break_ctl(struct uart_port *port, int break_state)
1977 {
1978 unsigned short scscr, scsptr;
1979
1980 /* check wheter the port has SCSPTR */
1981 if (!sci_getreg(port, SCSPTR)->size) {
1982 /*
1983 * Not supported by hardware. Most parts couple break and rx
1984 * interrupts together, with break detection always enabled.
1985 */
1986 return;
1987 }
1988
1989 scsptr = serial_port_in(port, SCSPTR);
1990 scscr = serial_port_in(port, SCSCR);
1991
1992 if (break_state == -1) {
1993 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1994 scscr &= ~SCSCR_TE;
1995 } else {
1996 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1997 scscr |= SCSCR_TE;
1998 }
1999
2000 serial_port_out(port, SCSPTR, scsptr);
2001 serial_port_out(port, SCSCR, scscr);
2002 }
2003
2004 static int sci_startup(struct uart_port *port)
2005 {
2006 struct sci_port *s = to_sci_port(port);
2007 int ret;
2008
2009 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2010
2011 sci_request_dma(port);
2012
2013 ret = sci_request_irq(s);
2014 if (unlikely(ret < 0)) {
2015 sci_free_dma(port);
2016 return ret;
2017 }
2018
2019 return 0;
2020 }
2021
2022 static void sci_shutdown(struct uart_port *port)
2023 {
2024 struct sci_port *s = to_sci_port(port);
2025 unsigned long flags;
2026 u16 scr;
2027
2028 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2029
2030 s->autorts = false;
2031 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2032
2033 spin_lock_irqsave(&port->lock, flags);
2034 sci_stop_rx(port);
2035 sci_stop_tx(port);
2036 /* Stop RX and TX, disable related interrupts, keep clock source */
2037 scr = serial_port_in(port, SCSCR);
2038 serial_port_out(port, SCSCR, scr & (SCSCR_CKE1 | SCSCR_CKE0));
2039 spin_unlock_irqrestore(&port->lock, flags);
2040
2041 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2042 if (s->chan_rx) {
2043 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2044 port->line);
2045 del_timer_sync(&s->rx_timer);
2046 }
2047 #endif
2048
2049 sci_free_irq(s);
2050 sci_free_dma(port);
2051 }
2052
2053 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2054 unsigned int *srr)
2055 {
2056 unsigned long freq = s->clk_rates[SCI_SCK];
2057 int err, min_err = INT_MAX;
2058 unsigned int sr;
2059
2060 if (s->port.type != PORT_HSCIF)
2061 freq *= 2;
2062
2063 for_each_sr(sr, s) {
2064 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2065 if (abs(err) >= abs(min_err))
2066 continue;
2067
2068 min_err = err;
2069 *srr = sr - 1;
2070
2071 if (!err)
2072 break;
2073 }
2074
2075 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2076 *srr + 1);
2077 return min_err;
2078 }
2079
2080 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2081 unsigned long freq, unsigned int *dlr,
2082 unsigned int *srr)
2083 {
2084 int err, min_err = INT_MAX;
2085 unsigned int sr, dl;
2086
2087 if (s->port.type != PORT_HSCIF)
2088 freq *= 2;
2089
2090 for_each_sr(sr, s) {
2091 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2092 dl = clamp(dl, 1U, 65535U);
2093
2094 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2095 if (abs(err) >= abs(min_err))
2096 continue;
2097
2098 min_err = err;
2099 *dlr = dl;
2100 *srr = sr - 1;
2101
2102 if (!err)
2103 break;
2104 }
2105
2106 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2107 min_err, *dlr, *srr + 1);
2108 return min_err;
2109 }
2110
2111 /* calculate sample rate, BRR, and clock select */
2112 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2113 unsigned int *brr, unsigned int *srr,
2114 unsigned int *cks)
2115 {
2116 unsigned long freq = s->clk_rates[SCI_FCK];
2117 unsigned int sr, br, prediv, scrate, c;
2118 int err, min_err = INT_MAX;
2119
2120 if (s->port.type != PORT_HSCIF)
2121 freq *= 2;
2122
2123 /*
2124 * Find the combination of sample rate and clock select with the
2125 * smallest deviation from the desired baud rate.
2126 * Prefer high sample rates to maximise the receive margin.
2127 *
2128 * M: Receive margin (%)
2129 * N: Ratio of bit rate to clock (N = sampling rate)
2130 * D: Clock duty (D = 0 to 1.0)
2131 * L: Frame length (L = 9 to 12)
2132 * F: Absolute value of clock frequency deviation
2133 *
2134 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2135 * (|D - 0.5| / N * (1 + F))|
2136 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2137 */
2138 for_each_sr(sr, s) {
2139 for (c = 0; c <= 3; c++) {
2140 /* integerized formulas from HSCIF documentation */
2141 prediv = sr * (1 << (2 * c + 1));
2142
2143 /*
2144 * We need to calculate:
2145 *
2146 * br = freq / (prediv * bps) clamped to [1..256]
2147 * err = freq / (br * prediv) - bps
2148 *
2149 * Watch out for overflow when calculating the desired
2150 * sampling clock rate!
2151 */
2152 if (bps > UINT_MAX / prediv)
2153 break;
2154
2155 scrate = prediv * bps;
2156 br = DIV_ROUND_CLOSEST(freq, scrate);
2157 br = clamp(br, 1U, 256U);
2158
2159 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2160 if (abs(err) >= abs(min_err))
2161 continue;
2162
2163 min_err = err;
2164 *brr = br - 1;
2165 *srr = sr - 1;
2166 *cks = c;
2167
2168 if (!err)
2169 goto found;
2170 }
2171 }
2172
2173 found:
2174 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2175 min_err, *brr, *srr + 1, *cks);
2176 return min_err;
2177 }
2178
2179 static void sci_reset(struct uart_port *port)
2180 {
2181 const struct plat_sci_reg *reg;
2182 unsigned int status;
2183 struct sci_port *s = to_sci_port(port);
2184
2185 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
2186
2187 reg = sci_getreg(port, SCFCR);
2188 if (reg->size)
2189 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2190
2191 sci_clear_SCxSR(port,
2192 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2193 SCxSR_BREAK_CLEAR(port));
2194 if (sci_getreg(port, SCLSR)->size) {
2195 status = serial_port_in(port, SCLSR);
2196 status &= ~(SCLSR_TO | SCLSR_ORER);
2197 serial_port_out(port, SCLSR, status);
2198 }
2199
2200 if (s->rx_trigger > 1) {
2201 if (s->rx_fifo_timeout) {
2202 scif_set_rtrg(port, 1);
2203 setup_timer(&s->rx_fifo_timer, rx_fifo_timer_fn,
2204 (unsigned long)s);
2205 } else {
2206 if (port->type == PORT_SCIFA ||
2207 port->type == PORT_SCIFB)
2208 scif_set_rtrg(port, 1);
2209 else
2210 scif_set_rtrg(port, s->rx_trigger);
2211 }
2212 }
2213 }
2214
2215 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2216 struct ktermios *old)
2217 {
2218 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2219 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2220 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2221 struct sci_port *s = to_sci_port(port);
2222 const struct plat_sci_reg *reg;
2223 int min_err = INT_MAX, err;
2224 unsigned long max_freq = 0;
2225 int best_clk = -1;
2226
2227 if ((termios->c_cflag & CSIZE) == CS7)
2228 smr_val |= SCSMR_CHR;
2229 if (termios->c_cflag & PARENB)
2230 smr_val |= SCSMR_PE;
2231 if (termios->c_cflag & PARODD)
2232 smr_val |= SCSMR_PE | SCSMR_ODD;
2233 if (termios->c_cflag & CSTOPB)
2234 smr_val |= SCSMR_STOP;
2235
2236 /*
2237 * earlyprintk comes here early on with port->uartclk set to zero.
2238 * the clock framework is not up and running at this point so here
2239 * we assume that 115200 is the maximum baud rate. please note that
2240 * the baud rate is not programmed during earlyprintk - it is assumed
2241 * that the previous boot loader has enabled required clocks and
2242 * setup the baud rate generator hardware for us already.
2243 */
2244 if (!port->uartclk) {
2245 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2246 goto done;
2247 }
2248
2249 for (i = 0; i < SCI_NUM_CLKS; i++)
2250 max_freq = max(max_freq, s->clk_rates[i]);
2251
2252 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2253 if (!baud)
2254 goto done;
2255
2256 /*
2257 * There can be multiple sources for the sampling clock. Find the one
2258 * that gives us the smallest deviation from the desired baud rate.
2259 */
2260
2261 /* Optional Undivided External Clock */
2262 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2263 port->type != PORT_SCIFB) {
2264 err = sci_sck_calc(s, baud, &srr1);
2265 if (abs(err) < abs(min_err)) {
2266 best_clk = SCI_SCK;
2267 scr_val = SCSCR_CKE1;
2268 sccks = SCCKS_CKS;
2269 min_err = err;
2270 srr = srr1;
2271 if (!err)
2272 goto done;
2273 }
2274 }
2275
2276 /* Optional BRG Frequency Divided External Clock */
2277 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2278 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2279 &srr1);
2280 if (abs(err) < abs(min_err)) {
2281 best_clk = SCI_SCIF_CLK;
2282 scr_val = SCSCR_CKE1;
2283 sccks = 0;
2284 min_err = err;
2285 dl = dl1;
2286 srr = srr1;
2287 if (!err)
2288 goto done;
2289 }
2290 }
2291
2292 /* Optional BRG Frequency Divided Internal Clock */
2293 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2294 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2295 &srr1);
2296 if (abs(err) < abs(min_err)) {
2297 best_clk = SCI_BRG_INT;
2298 scr_val = SCSCR_CKE1;
2299 sccks = SCCKS_XIN;
2300 min_err = err;
2301 dl = dl1;
2302 srr = srr1;
2303 if (!min_err)
2304 goto done;
2305 }
2306 }
2307
2308 /* Divided Functional Clock using standard Bit Rate Register */
2309 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2310 if (abs(err) < abs(min_err)) {
2311 best_clk = SCI_FCK;
2312 scr_val = 0;
2313 min_err = err;
2314 brr = brr1;
2315 srr = srr1;
2316 cks = cks1;
2317 }
2318
2319 done:
2320 if (best_clk >= 0)
2321 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2322 s->clks[best_clk], baud, min_err);
2323
2324 sci_port_enable(s);
2325
2326 /*
2327 * Program the optional External Baud Rate Generator (BRG) first.
2328 * It controls the mux to select (H)SCK or frequency divided clock.
2329 */
2330 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2331 serial_port_out(port, SCDL, dl);
2332 serial_port_out(port, SCCKS, sccks);
2333 }
2334
2335 sci_reset(port);
2336
2337 uart_update_timeout(port, termios->c_cflag, baud);
2338
2339 if (best_clk >= 0) {
2340 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2341 switch (srr + 1) {
2342 case 5: smr_val |= SCSMR_SRC_5; break;
2343 case 7: smr_val |= SCSMR_SRC_7; break;
2344 case 11: smr_val |= SCSMR_SRC_11; break;
2345 case 13: smr_val |= SCSMR_SRC_13; break;
2346 case 16: smr_val |= SCSMR_SRC_16; break;
2347 case 17: smr_val |= SCSMR_SRC_17; break;
2348 case 19: smr_val |= SCSMR_SRC_19; break;
2349 case 27: smr_val |= SCSMR_SRC_27; break;
2350 }
2351 smr_val |= cks;
2352 dev_dbg(port->dev,
2353 "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n",
2354 scr_val, smr_val, brr, sccks, dl, srr);
2355 serial_port_out(port, SCSCR, scr_val);
2356 serial_port_out(port, SCSMR, smr_val);
2357 serial_port_out(port, SCBRR, brr);
2358 if (sci_getreg(port, HSSRR)->size)
2359 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
2360
2361 /* Wait one bit interval */
2362 udelay((1000000 + (baud - 1)) / baud);
2363 } else {
2364 /* Don't touch the bit rate configuration */
2365 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2366 smr_val |= serial_port_in(port, SCSMR) &
2367 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2368 dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
2369 serial_port_out(port, SCSCR, scr_val);
2370 serial_port_out(port, SCSMR, smr_val);
2371 }
2372
2373 sci_init_pins(port, termios->c_cflag);
2374
2375 port->status &= ~UPSTAT_AUTOCTS;
2376 s->autorts = false;
2377 reg = sci_getreg(port, SCFCR);
2378 if (reg->size) {
2379 unsigned short ctrl = serial_port_in(port, SCFCR);
2380
2381 if ((port->flags & UPF_HARD_FLOW) &&
2382 (termios->c_cflag & CRTSCTS)) {
2383 /* There is no CTS interrupt to restart the hardware */
2384 port->status |= UPSTAT_AUTOCTS;
2385 /* MCE is enabled when RTS is raised */
2386 s->autorts = true;
2387 }
2388
2389 /*
2390 * As we've done a sci_reset() above, ensure we don't
2391 * interfere with the FIFOs while toggling MCE. As the
2392 * reset values could still be set, simply mask them out.
2393 */
2394 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2395
2396 serial_port_out(port, SCFCR, ctrl);
2397 }
2398 if (port->flags & UPF_HARD_FLOW) {
2399 /* Refresh (Auto) RTS */
2400 sci_set_mctrl(port, port->mctrl);
2401 }
2402
2403 scr_val |= SCSCR_RE | SCSCR_TE |
2404 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2405 dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
2406 serial_port_out(port, SCSCR, scr_val);
2407 if ((srr + 1 == 5) &&
2408 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2409 /*
2410 * In asynchronous mode, when the sampling rate is 1/5, first
2411 * received data may become invalid on some SCIFA and SCIFB.
2412 * To avoid this problem wait more than 1 serial data time (1
2413 * bit time x serial data number) after setting SCSCR.RE = 1.
2414 */
2415 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2416 }
2417
2418 /*
2419 * Calculate delay for 2 DMA buffers (4 FIFO).
2420 * See serial_core.c::uart_update_timeout().
2421 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2422 * function calculates 1 jiffie for the data plus 5 jiffies for the
2423 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2424 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2425 * value obtained by this formula is too small. Therefore, if the value
2426 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2427 */
2428 /* byte size and parity */
2429 switch (termios->c_cflag & CSIZE) {
2430 case CS5:
2431 bits = 7;
2432 break;
2433 case CS6:
2434 bits = 8;
2435 break;
2436 case CS7:
2437 bits = 9;
2438 break;
2439 default:
2440 bits = 10;
2441 break;
2442 }
2443
2444 if (termios->c_cflag & CSTOPB)
2445 bits++;
2446 if (termios->c_cflag & PARENB)
2447 bits++;
2448
2449 s->rx_frame = (100 * bits * HZ) / (baud / 10);
2450 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2451 s->rx_timeout = DIV_ROUND_UP(s->buf_len_rx * 2 * s->rx_frame, 1000);
2452 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2453 s->rx_timeout * 1000 / HZ, port->timeout);
2454 if (s->rx_timeout < msecs_to_jiffies(20))
2455 s->rx_timeout = msecs_to_jiffies(20);
2456 #endif
2457
2458 if ((termios->c_cflag & CREAD) != 0)
2459 sci_start_rx(port);
2460
2461 sci_port_disable(s);
2462
2463 if (UART_ENABLE_MS(port, termios->c_cflag))
2464 sci_enable_ms(port);
2465 }
2466
2467 static void sci_pm(struct uart_port *port, unsigned int state,
2468 unsigned int oldstate)
2469 {
2470 struct sci_port *sci_port = to_sci_port(port);
2471
2472 switch (state) {
2473 case UART_PM_STATE_OFF:
2474 sci_port_disable(sci_port);
2475 break;
2476 default:
2477 sci_port_enable(sci_port);
2478 break;
2479 }
2480 }
2481
2482 static const char *sci_type(struct uart_port *port)
2483 {
2484 switch (port->type) {
2485 case PORT_IRDA:
2486 return "irda";
2487 case PORT_SCI:
2488 return "sci";
2489 case PORT_SCIF:
2490 return "scif";
2491 case PORT_SCIFA:
2492 return "scifa";
2493 case PORT_SCIFB:
2494 return "scifb";
2495 case PORT_HSCIF:
2496 return "hscif";
2497 }
2498
2499 return NULL;
2500 }
2501
2502 static int sci_remap_port(struct uart_port *port)
2503 {
2504 struct sci_port *sport = to_sci_port(port);
2505
2506 /*
2507 * Nothing to do if there's already an established membase.
2508 */
2509 if (port->membase)
2510 return 0;
2511
2512 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2513 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2514 if (unlikely(!port->membase)) {
2515 dev_err(port->dev, "can't remap port#%d\n", port->line);
2516 return -ENXIO;
2517 }
2518 } else {
2519 /*
2520 * For the simple (and majority of) cases where we don't
2521 * need to do any remapping, just cast the cookie
2522 * directly.
2523 */
2524 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2525 }
2526
2527 return 0;
2528 }
2529
2530 static void sci_release_port(struct uart_port *port)
2531 {
2532 struct sci_port *sport = to_sci_port(port);
2533
2534 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2535 iounmap(port->membase);
2536 port->membase = NULL;
2537 }
2538
2539 release_mem_region(port->mapbase, sport->reg_size);
2540 }
2541
2542 static int sci_request_port(struct uart_port *port)
2543 {
2544 struct resource *res;
2545 struct sci_port *sport = to_sci_port(port);
2546 int ret;
2547
2548 res = request_mem_region(port->mapbase, sport->reg_size,
2549 dev_name(port->dev));
2550 if (unlikely(res == NULL)) {
2551 dev_err(port->dev, "request_mem_region failed.");
2552 return -EBUSY;
2553 }
2554
2555 ret = sci_remap_port(port);
2556 if (unlikely(ret != 0)) {
2557 release_resource(res);
2558 return ret;
2559 }
2560
2561 return 0;
2562 }
2563
2564 static void sci_config_port(struct uart_port *port, int flags)
2565 {
2566 if (flags & UART_CONFIG_TYPE) {
2567 struct sci_port *sport = to_sci_port(port);
2568
2569 port->type = sport->cfg->type;
2570 sci_request_port(port);
2571 }
2572 }
2573
2574 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2575 {
2576 if (ser->baud_base < 2400)
2577 /* No paper tape reader for Mitch.. */
2578 return -EINVAL;
2579
2580 return 0;
2581 }
2582
2583 static const struct uart_ops sci_uart_ops = {
2584 .tx_empty = sci_tx_empty,
2585 .set_mctrl = sci_set_mctrl,
2586 .get_mctrl = sci_get_mctrl,
2587 .start_tx = sci_start_tx,
2588 .stop_tx = sci_stop_tx,
2589 .stop_rx = sci_stop_rx,
2590 .enable_ms = sci_enable_ms,
2591 .break_ctl = sci_break_ctl,
2592 .startup = sci_startup,
2593 .shutdown = sci_shutdown,
2594 .flush_buffer = sci_flush_buffer,
2595 .set_termios = sci_set_termios,
2596 .pm = sci_pm,
2597 .type = sci_type,
2598 .release_port = sci_release_port,
2599 .request_port = sci_request_port,
2600 .config_port = sci_config_port,
2601 .verify_port = sci_verify_port,
2602 #ifdef CONFIG_CONSOLE_POLL
2603 .poll_get_char = sci_poll_get_char,
2604 .poll_put_char = sci_poll_put_char,
2605 #endif
2606 };
2607
2608 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2609 {
2610 const char *clk_names[] = {
2611 [SCI_FCK] = "fck",
2612 [SCI_SCK] = "sck",
2613 [SCI_BRG_INT] = "brg_int",
2614 [SCI_SCIF_CLK] = "scif_clk",
2615 };
2616 struct clk *clk;
2617 unsigned int i;
2618
2619 if (sci_port->cfg->type == PORT_HSCIF)
2620 clk_names[SCI_SCK] = "hsck";
2621
2622 for (i = 0; i < SCI_NUM_CLKS; i++) {
2623 clk = devm_clk_get(dev, clk_names[i]);
2624 if (PTR_ERR(clk) == -EPROBE_DEFER)
2625 return -EPROBE_DEFER;
2626
2627 if (IS_ERR(clk) && i == SCI_FCK) {
2628 /*
2629 * "fck" used to be called "sci_ick", and we need to
2630 * maintain DT backward compatibility.
2631 */
2632 clk = devm_clk_get(dev, "sci_ick");
2633 if (PTR_ERR(clk) == -EPROBE_DEFER)
2634 return -EPROBE_DEFER;
2635
2636 if (!IS_ERR(clk))
2637 goto found;
2638
2639 /*
2640 * Not all SH platforms declare a clock lookup entry
2641 * for SCI devices, in which case we need to get the
2642 * global "peripheral_clk" clock.
2643 */
2644 clk = devm_clk_get(dev, "peripheral_clk");
2645 if (!IS_ERR(clk))
2646 goto found;
2647
2648 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2649 PTR_ERR(clk));
2650 return PTR_ERR(clk);
2651 }
2652
2653 found:
2654 if (IS_ERR(clk))
2655 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2656 PTR_ERR(clk));
2657 else
2658 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2659 clk, clk);
2660 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2661 }
2662 return 0;
2663 }
2664
2665 static const struct sci_port_params *
2666 sci_probe_regmap(const struct plat_sci_port *cfg)
2667 {
2668 unsigned int regtype;
2669
2670 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2671 return &sci_port_params[cfg->regtype];
2672
2673 switch (cfg->type) {
2674 case PORT_SCI:
2675 regtype = SCIx_SCI_REGTYPE;
2676 break;
2677 case PORT_IRDA:
2678 regtype = SCIx_IRDA_REGTYPE;
2679 break;
2680 case PORT_SCIFA:
2681 regtype = SCIx_SCIFA_REGTYPE;
2682 break;
2683 case PORT_SCIFB:
2684 regtype = SCIx_SCIFB_REGTYPE;
2685 break;
2686 case PORT_SCIF:
2687 /*
2688 * The SH-4 is a bit of a misnomer here, although that's
2689 * where this particular port layout originated. This
2690 * configuration (or some slight variation thereof)
2691 * remains the dominant model for all SCIFs.
2692 */
2693 regtype = SCIx_SH4_SCIF_REGTYPE;
2694 break;
2695 case PORT_HSCIF:
2696 regtype = SCIx_HSCIF_REGTYPE;
2697 break;
2698 default:
2699 pr_err("Can't probe register map for given port\n");
2700 return NULL;
2701 }
2702
2703 return &sci_port_params[regtype];
2704 }
2705
2706 static int sci_init_single(struct platform_device *dev,
2707 struct sci_port *sci_port, unsigned int index,
2708 const struct plat_sci_port *p, bool early)
2709 {
2710 struct uart_port *port = &sci_port->port;
2711 const struct resource *res;
2712 unsigned int i;
2713 int ret;
2714
2715 sci_port->cfg = p;
2716
2717 port->ops = &sci_uart_ops;
2718 port->iotype = UPIO_MEM;
2719 port->line = index;
2720
2721 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2722 if (res == NULL)
2723 return -ENOMEM;
2724
2725 port->mapbase = res->start;
2726 sci_port->reg_size = resource_size(res);
2727
2728 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2729 sci_port->irqs[i] = platform_get_irq(dev, i);
2730
2731 /* The SCI generates several interrupts. They can be muxed together or
2732 * connected to different interrupt lines. In the muxed case only one
2733 * interrupt resource is specified. In the non-muxed case three or four
2734 * interrupt resources are specified, as the BRI interrupt is optional.
2735 */
2736 if (sci_port->irqs[0] < 0)
2737 return -ENXIO;
2738
2739 if (sci_port->irqs[1] < 0) {
2740 sci_port->irqs[1] = sci_port->irqs[0];
2741 sci_port->irqs[2] = sci_port->irqs[0];
2742 sci_port->irqs[3] = sci_port->irqs[0];
2743 }
2744
2745 sci_port->params = sci_probe_regmap(p);
2746 if (unlikely(sci_port->params == NULL))
2747 return -EINVAL;
2748
2749 switch (p->type) {
2750 case PORT_SCIFB:
2751 sci_port->rx_trigger = 48;
2752 break;
2753 case PORT_HSCIF:
2754 sci_port->rx_trigger = 64;
2755 break;
2756 case PORT_SCIFA:
2757 sci_port->rx_trigger = 32;
2758 break;
2759 case PORT_SCIF:
2760 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2761 /* RX triggering not implemented for this IP */
2762 sci_port->rx_trigger = 1;
2763 else
2764 sci_port->rx_trigger = 8;
2765 break;
2766 default:
2767 sci_port->rx_trigger = 1;
2768 break;
2769 }
2770
2771 sci_port->rx_fifo_timeout = 0;
2772
2773 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2774 * match the SoC datasheet, this should be investigated. Let platform
2775 * data override the sampling rate for now.
2776 */
2777 sci_port->sampling_rate_mask = p->sampling_rate
2778 ? SCI_SR(p->sampling_rate)
2779 : sci_port->params->sampling_rate_mask;
2780
2781 if (!early) {
2782 ret = sci_init_clocks(sci_port, &dev->dev);
2783 if (ret < 0)
2784 return ret;
2785
2786 port->dev = &dev->dev;
2787
2788 pm_runtime_enable(&dev->dev);
2789 }
2790
2791 port->type = p->type;
2792 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2793 port->fifosize = sci_port->params->fifosize;
2794
2795 if (port->type == PORT_SCI) {
2796 if (sci_port->reg_size >= 0x20)
2797 port->regshift = 2;
2798 else
2799 port->regshift = 1;
2800 }
2801
2802 /*
2803 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2804 * for the multi-IRQ ports, which is where we are primarily
2805 * concerned with the shutdown path synchronization.
2806 *
2807 * For the muxed case there's nothing more to do.
2808 */
2809 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2810 port->irqflags = 0;
2811
2812 port->serial_in = sci_serial_in;
2813 port->serial_out = sci_serial_out;
2814
2815 return 0;
2816 }
2817
2818 static void sci_cleanup_single(struct sci_port *port)
2819 {
2820 pm_runtime_disable(port->port.dev);
2821 }
2822
2823 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2824 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2825 static void serial_console_putchar(struct uart_port *port, int ch)
2826 {
2827 sci_poll_put_char(port, ch);
2828 }
2829
2830 /*
2831 * Print a string to the serial port trying not to disturb
2832 * any possible real use of the port...
2833 */
2834 static void serial_console_write(struct console *co, const char *s,
2835 unsigned count)
2836 {
2837 struct sci_port *sci_port = &sci_ports[co->index];
2838 struct uart_port *port = &sci_port->port;
2839 unsigned short bits, ctrl, ctrl_temp;
2840 unsigned long flags;
2841 int locked = 1;
2842
2843 local_irq_save(flags);
2844 #if defined(SUPPORT_SYSRQ)
2845 if (port->sysrq)
2846 locked = 0;
2847 else
2848 #endif
2849 if (oops_in_progress)
2850 locked = spin_trylock(&port->lock);
2851 else
2852 spin_lock(&port->lock);
2853
2854 /* first save SCSCR then disable interrupts, keep clock source */
2855 ctrl = serial_port_in(port, SCSCR);
2856 ctrl_temp = SCSCR_RE | SCSCR_TE |
2857 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2858 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2859 serial_port_out(port, SCSCR, ctrl_temp);
2860
2861 uart_console_write(port, s, count, serial_console_putchar);
2862
2863 /* wait until fifo is empty and last bit has been transmitted */
2864 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2865 while ((serial_port_in(port, SCxSR) & bits) != bits)
2866 cpu_relax();
2867
2868 /* restore the SCSCR */
2869 serial_port_out(port, SCSCR, ctrl);
2870
2871 if (locked)
2872 spin_unlock(&port->lock);
2873 local_irq_restore(flags);
2874 }
2875
2876 static int serial_console_setup(struct console *co, char *options)
2877 {
2878 struct sci_port *sci_port;
2879 struct uart_port *port;
2880 int baud = 115200;
2881 int bits = 8;
2882 int parity = 'n';
2883 int flow = 'n';
2884 int ret;
2885
2886 /*
2887 * Refuse to handle any bogus ports.
2888 */
2889 if (co->index < 0 || co->index >= SCI_NPORTS)
2890 return -ENODEV;
2891
2892 sci_port = &sci_ports[co->index];
2893 port = &sci_port->port;
2894
2895 /*
2896 * Refuse to handle uninitialized ports.
2897 */
2898 if (!port->ops)
2899 return -ENODEV;
2900
2901 ret = sci_remap_port(port);
2902 if (unlikely(ret != 0))
2903 return ret;
2904
2905 if (options)
2906 uart_parse_options(options, &baud, &parity, &bits, &flow);
2907
2908 return uart_set_options(port, co, baud, parity, bits, flow);
2909 }
2910
2911 static struct console serial_console = {
2912 .name = "ttySC",
2913 .device = uart_console_device,
2914 .write = serial_console_write,
2915 .setup = serial_console_setup,
2916 .flags = CON_PRINTBUFFER,
2917 .index = -1,
2918 .data = &sci_uart_driver,
2919 };
2920
2921 static struct console early_serial_console = {
2922 .name = "early_ttySC",
2923 .write = serial_console_write,
2924 .flags = CON_PRINTBUFFER,
2925 .index = -1,
2926 };
2927
2928 static char early_serial_buf[32];
2929
2930 static int sci_probe_earlyprintk(struct platform_device *pdev)
2931 {
2932 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2933
2934 if (early_serial_console.data)
2935 return -EEXIST;
2936
2937 early_serial_console.index = pdev->id;
2938
2939 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2940
2941 serial_console_setup(&early_serial_console, early_serial_buf);
2942
2943 if (!strstr(early_serial_buf, "keep"))
2944 early_serial_console.flags |= CON_BOOT;
2945
2946 register_console(&early_serial_console);
2947 return 0;
2948 }
2949
2950 #define SCI_CONSOLE (&serial_console)
2951
2952 #else
2953 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2954 {
2955 return -EINVAL;
2956 }
2957
2958 #define SCI_CONSOLE NULL
2959
2960 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
2961
2962 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2963
2964 static DEFINE_MUTEX(sci_uart_registration_lock);
2965 static struct uart_driver sci_uart_driver = {
2966 .owner = THIS_MODULE,
2967 .driver_name = "sci",
2968 .dev_name = "ttySC",
2969 .major = SCI_MAJOR,
2970 .minor = SCI_MINOR_START,
2971 .nr = SCI_NPORTS,
2972 .cons = SCI_CONSOLE,
2973 };
2974
2975 static int sci_remove(struct platform_device *dev)
2976 {
2977 struct sci_port *port = platform_get_drvdata(dev);
2978
2979 uart_remove_one_port(&sci_uart_driver, &port->port);
2980
2981 sci_cleanup_single(port);
2982
2983 if (port->port.fifosize > 1) {
2984 sysfs_remove_file(&dev->dev.kobj,
2985 &dev_attr_rx_fifo_trigger.attr);
2986 }
2987 if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB) {
2988 sysfs_remove_file(&dev->dev.kobj,
2989 &dev_attr_rx_fifo_timeout.attr);
2990 }
2991
2992 return 0;
2993 }
2994
2995
2996 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
2997 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
2998 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
2999
3000 static const struct of_device_id of_sci_match[] = {
3001 /* SoC-specific types */
3002 {
3003 .compatible = "renesas,scif-r7s72100",
3004 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3005 },
3006 /* Family-specific types */
3007 {
3008 .compatible = "renesas,rcar-gen1-scif",
3009 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3010 }, {
3011 .compatible = "renesas,rcar-gen2-scif",
3012 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3013 }, {
3014 .compatible = "renesas,rcar-gen3-scif",
3015 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3016 },
3017 /* Generic types */
3018 {
3019 .compatible = "renesas,scif",
3020 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3021 }, {
3022 .compatible = "renesas,scifa",
3023 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3024 }, {
3025 .compatible = "renesas,scifb",
3026 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3027 }, {
3028 .compatible = "renesas,hscif",
3029 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3030 }, {
3031 .compatible = "renesas,sci",
3032 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3033 }, {
3034 /* Terminator */
3035 },
3036 };
3037 MODULE_DEVICE_TABLE(of, of_sci_match);
3038
3039 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3040 unsigned int *dev_id)
3041 {
3042 struct device_node *np = pdev->dev.of_node;
3043 const struct of_device_id *match;
3044 struct plat_sci_port *p;
3045 struct sci_port *sp;
3046 int id;
3047
3048 if (!IS_ENABLED(CONFIG_OF) || !np)
3049 return NULL;
3050
3051 match = of_match_node(of_sci_match, np);
3052 if (!match)
3053 return NULL;
3054
3055 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3056 if (!p)
3057 return NULL;
3058
3059 /* Get the line number from the aliases node. */
3060 id = of_alias_get_id(np, "serial");
3061 if (id < 0) {
3062 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3063 return NULL;
3064 }
3065
3066 sp = &sci_ports[id];
3067 *dev_id = id;
3068
3069 p->type = SCI_OF_TYPE(match->data);
3070 p->regtype = SCI_OF_REGTYPE(match->data);
3071
3072 if (of_find_property(np, "uart-has-rtscts", NULL))
3073 sp->has_rtscts = true;
3074
3075 return p;
3076 }
3077
3078 static int sci_probe_single(struct platform_device *dev,
3079 unsigned int index,
3080 struct plat_sci_port *p,
3081 struct sci_port *sciport)
3082 {
3083 int ret;
3084
3085 /* Sanity check */
3086 if (unlikely(index >= SCI_NPORTS)) {
3087 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3088 index+1, SCI_NPORTS);
3089 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3090 return -EINVAL;
3091 }
3092
3093 mutex_lock(&sci_uart_registration_lock);
3094 if (!sci_uart_driver.state) {
3095 ret = uart_register_driver(&sci_uart_driver);
3096 if (ret) {
3097 mutex_unlock(&sci_uart_registration_lock);
3098 return ret;
3099 }
3100 }
3101 mutex_unlock(&sci_uart_registration_lock);
3102
3103 ret = sci_init_single(dev, sciport, index, p, false);
3104 if (ret)
3105 return ret;
3106
3107 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3108 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3109 return PTR_ERR(sciport->gpios);
3110
3111 if (sciport->has_rtscts) {
3112 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3113 UART_GPIO_CTS)) ||
3114 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3115 UART_GPIO_RTS))) {
3116 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3117 return -EINVAL;
3118 }
3119 sciport->port.flags |= UPF_HARD_FLOW;
3120 }
3121
3122 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3123 if (ret) {
3124 sci_cleanup_single(sciport);
3125 return ret;
3126 }
3127
3128 return 0;
3129 }
3130
3131 static int sci_probe(struct platform_device *dev)
3132 {
3133 struct plat_sci_port *p;
3134 struct sci_port *sp;
3135 unsigned int dev_id;
3136 int ret;
3137
3138 /*
3139 * If we've come here via earlyprintk initialization, head off to
3140 * the special early probe. We don't have sufficient device state
3141 * to make it beyond this yet.
3142 */
3143 if (is_early_platform_device(dev))
3144 return sci_probe_earlyprintk(dev);
3145
3146 if (dev->dev.of_node) {
3147 p = sci_parse_dt(dev, &dev_id);
3148 if (p == NULL)
3149 return -EINVAL;
3150 } else {
3151 p = dev->dev.platform_data;
3152 if (p == NULL) {
3153 dev_err(&dev->dev, "no platform data supplied\n");
3154 return -EINVAL;
3155 }
3156
3157 dev_id = dev->id;
3158 }
3159
3160 sp = &sci_ports[dev_id];
3161 platform_set_drvdata(dev, sp);
3162
3163 ret = sci_probe_single(dev, dev_id, p, sp);
3164 if (ret)
3165 return ret;
3166
3167 if (sp->port.fifosize > 1) {
3168 ret = sysfs_create_file(&dev->dev.kobj,
3169 &dev_attr_rx_fifo_trigger.attr);
3170 if (ret)
3171 return ret;
3172 }
3173 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB) {
3174 ret = sysfs_create_file(&dev->dev.kobj,
3175 &dev_attr_rx_fifo_timeout.attr);
3176 if (ret) {
3177 if (sp->port.fifosize > 1) {
3178 sysfs_remove_file(&dev->dev.kobj,
3179 &dev_attr_rx_fifo_trigger.attr);
3180 }
3181 return ret;
3182 }
3183 }
3184
3185 #ifdef CONFIG_SH_STANDARD_BIOS
3186 sh_bios_gdb_detach();
3187 #endif
3188
3189 return 0;
3190 }
3191
3192 static __maybe_unused int sci_suspend(struct device *dev)
3193 {
3194 struct sci_port *sport = dev_get_drvdata(dev);
3195
3196 if (sport)
3197 uart_suspend_port(&sci_uart_driver, &sport->port);
3198
3199 return 0;
3200 }
3201
3202 static __maybe_unused int sci_resume(struct device *dev)
3203 {
3204 struct sci_port *sport = dev_get_drvdata(dev);
3205
3206 if (sport)
3207 uart_resume_port(&sci_uart_driver, &sport->port);
3208
3209 return 0;
3210 }
3211
3212 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3213
3214 static struct platform_driver sci_driver = {
3215 .probe = sci_probe,
3216 .remove = sci_remove,
3217 .driver = {
3218 .name = "sh-sci",
3219 .pm = &sci_dev_pm_ops,
3220 .of_match_table = of_match_ptr(of_sci_match),
3221 },
3222 };
3223
3224 static int __init sci_init(void)
3225 {
3226 pr_info("%s\n", banner);
3227
3228 return platform_driver_register(&sci_driver);
3229 }
3230
3231 static void __exit sci_exit(void)
3232 {
3233 platform_driver_unregister(&sci_driver);
3234
3235 if (sci_uart_driver.state)
3236 uart_unregister_driver(&sci_uart_driver);
3237 }
3238
3239 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3240 early_platform_init_buffer("earlyprintk", &sci_driver,
3241 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3242 #endif
3243 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3244 static struct __init plat_sci_port port_cfg;
3245
3246 static int __init early_console_setup(struct earlycon_device *device,
3247 int type)
3248 {
3249 if (!device->port.membase)
3250 return -ENODEV;
3251
3252 device->port.serial_in = sci_serial_in;
3253 device->port.serial_out = sci_serial_out;
3254 device->port.type = type;
3255 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3256 port_cfg.type = type;
3257 sci_ports[0].cfg = &port_cfg;
3258 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3259 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3260 sci_serial_out(&sci_ports[0].port, SCSCR,
3261 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3262
3263 device->con->write = serial_console_write;
3264 return 0;
3265 }
3266 static int __init sci_early_console_setup(struct earlycon_device *device,
3267 const char *opt)
3268 {
3269 return early_console_setup(device, PORT_SCI);
3270 }
3271 static int __init scif_early_console_setup(struct earlycon_device *device,
3272 const char *opt)
3273 {
3274 return early_console_setup(device, PORT_SCIF);
3275 }
3276 static int __init scifa_early_console_setup(struct earlycon_device *device,
3277 const char *opt)
3278 {
3279 return early_console_setup(device, PORT_SCIFA);
3280 }
3281 static int __init scifb_early_console_setup(struct earlycon_device *device,
3282 const char *opt)
3283 {
3284 return early_console_setup(device, PORT_SCIFB);
3285 }
3286 static int __init hscif_early_console_setup(struct earlycon_device *device,
3287 const char *opt)
3288 {
3289 return early_console_setup(device, PORT_HSCIF);
3290 }
3291
3292 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3293 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3294 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3295 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3296 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3297 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3298
3299 module_init(sci_init);
3300 module_exit(sci_exit);
3301
3302 MODULE_LICENSE("GPL");
3303 MODULE_ALIAS("platform:sh-sci");
3304 MODULE_AUTHOR("Paul Mundt");
3305 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
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