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Merge branch 'fixes' of git://git.armlinux.org.uk/~rmk/linux-arm
[mirror_ubuntu-hirsute-kernel.git] / drivers / tty / synclinkmp.c
1 // SPDX-License-Identifier: GPL-1.0+
2 /*
3 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
4 *
5 * Device driver for Microgate SyncLink Multiport
6 * high speed multiprotocol serial adapter.
7 *
8 * written by Paul Fulghum for Microgate Corporation
9 * paulkf@microgate.com
10 *
11 * Microgate and SyncLink are trademarks of Microgate Corporation
12 *
13 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29 #if defined(__i386__)
30 # define BREAKPOINT() asm(" int $3");
31 #else
32 # define BREAKPOINT() { }
33 #endif
34
35 #define MAX_DEVICES 12
36
37 #include <linux/module.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/sched.h>
41 #include <linux/timer.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
50 #include <linux/ptrace.h>
51 #include <linux/ioport.h>
52 #include <linux/mm.h>
53 #include <linux/seq_file.h>
54 #include <linux/slab.h>
55 #include <linux/netdevice.h>
56 #include <linux/vmalloc.h>
57 #include <linux/init.h>
58 #include <linux/delay.h>
59 #include <linux/ioctl.h>
60
61 #include <asm/io.h>
62 #include <asm/irq.h>
63 #include <asm/dma.h>
64 #include <linux/bitops.h>
65 #include <asm/types.h>
66 #include <linux/termios.h>
67 #include <linux/workqueue.h>
68 #include <linux/hdlc.h>
69 #include <linux/synclink.h>
70
71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72 #define SYNCLINK_GENERIC_HDLC 1
73 #else
74 #define SYNCLINK_GENERIC_HDLC 0
75 #endif
76
77 #define GET_USER(error,value,addr) error = get_user(value,addr)
78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
81
82 #include <linux/uaccess.h>
83
84 static MGSL_PARAMS default_params = {
85 MGSL_MODE_HDLC, /* unsigned long mode */
86 0, /* unsigned char loopback; */
87 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
88 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
89 0, /* unsigned long clock_speed; */
90 0xff, /* unsigned char addr_filter; */
91 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
92 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
93 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
94 9600, /* unsigned long data_rate; */
95 8, /* unsigned char data_bits; */
96 1, /* unsigned char stop_bits; */
97 ASYNC_PARITY_NONE /* unsigned char parity; */
98 };
99
100 /* size in bytes of DMA data buffers */
101 #define SCABUFSIZE 1024
102 #define SCA_MEM_SIZE 0x40000
103 #define SCA_BASE_SIZE 512
104 #define SCA_REG_SIZE 16
105 #define SCA_MAX_PORTS 4
106 #define SCAMAXDESC 128
107
108 #define BUFFERLISTSIZE 4096
109
110 /* SCA-I style DMA buffer descriptor */
111 typedef struct _SCADESC
112 {
113 u16 next; /* lower l6 bits of next descriptor addr */
114 u16 buf_ptr; /* lower 16 bits of buffer addr */
115 u8 buf_base; /* upper 8 bits of buffer addr */
116 u8 pad1;
117 u16 length; /* length of buffer */
118 u8 status; /* status of buffer */
119 u8 pad2;
120 } SCADESC, *PSCADESC;
121
122 typedef struct _SCADESC_EX
123 {
124 /* device driver bookkeeping section */
125 char *virt_addr; /* virtual address of data buffer */
126 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
127 } SCADESC_EX, *PSCADESC_EX;
128
129 /* The queue of BH actions to be performed */
130
131 #define BH_RECEIVE 1
132 #define BH_TRANSMIT 2
133 #define BH_STATUS 4
134
135 #define IO_PIN_SHUTDOWN_LIMIT 100
136
137 struct _input_signal_events {
138 int ri_up;
139 int ri_down;
140 int dsr_up;
141 int dsr_down;
142 int dcd_up;
143 int dcd_down;
144 int cts_up;
145 int cts_down;
146 };
147
148 /*
149 * Device instance data structure
150 */
151 typedef struct _synclinkmp_info {
152 void *if_ptr; /* General purpose pointer (used by SPPP) */
153 int magic;
154 struct tty_port port;
155 int line;
156 unsigned short close_delay;
157 unsigned short closing_wait; /* time to wait before closing */
158
159 struct mgsl_icount icount;
160
161 int timeout;
162 int x_char; /* xon/xoff character */
163 u16 read_status_mask1; /* break detection (SR1 indications) */
164 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
165 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
166 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
167 unsigned char *tx_buf;
168 int tx_put;
169 int tx_get;
170 int tx_count;
171
172 wait_queue_head_t status_event_wait_q;
173 wait_queue_head_t event_wait_q;
174 struct timer_list tx_timer; /* HDLC transmit timeout timer */
175 struct _synclinkmp_info *next_device; /* device list link */
176 struct timer_list status_timer; /* input signal status check timer */
177
178 spinlock_t lock; /* spinlock for synchronizing with ISR */
179 struct work_struct task; /* task structure for scheduling bh */
180
181 u32 max_frame_size; /* as set by device config */
182
183 u32 pending_bh;
184
185 bool bh_running; /* Protection from multiple */
186 int isr_overflow;
187 bool bh_requested;
188
189 int dcd_chkcount; /* check counts to prevent */
190 int cts_chkcount; /* too many IRQs if a signal */
191 int dsr_chkcount; /* is floating */
192 int ri_chkcount;
193
194 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
195 unsigned long buffer_list_phys;
196
197 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
198 SCADESC *rx_buf_list; /* list of receive buffer entries */
199 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
200 unsigned int current_rx_buf;
201
202 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
203 SCADESC *tx_buf_list; /* list of transmit buffer entries */
204 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
205 unsigned int last_tx_buf;
206
207 unsigned char *tmp_rx_buf;
208 unsigned int tmp_rx_buf_count;
209
210 bool rx_enabled;
211 bool rx_overflow;
212
213 bool tx_enabled;
214 bool tx_active;
215 u32 idle_mode;
216
217 unsigned char ie0_value;
218 unsigned char ie1_value;
219 unsigned char ie2_value;
220 unsigned char ctrlreg_value;
221 unsigned char old_signals;
222
223 char device_name[25]; /* device instance name */
224
225 int port_count;
226 int adapter_num;
227 int port_num;
228
229 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
230
231 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
232
233 unsigned int irq_level; /* interrupt level */
234 unsigned long irq_flags;
235 bool irq_requested; /* true if IRQ requested */
236
237 MGSL_PARAMS params; /* communications parameters */
238
239 unsigned char serial_signals; /* current serial signal states */
240
241 bool irq_occurred; /* for diagnostics use */
242 unsigned int init_error; /* Initialization startup error */
243
244 u32 last_mem_alloc;
245 unsigned char* memory_base; /* shared memory address (PCI only) */
246 u32 phys_memory_base;
247 int shared_mem_requested;
248
249 unsigned char* sca_base; /* HD64570 SCA Memory address */
250 u32 phys_sca_base;
251 u32 sca_offset;
252 bool sca_base_requested;
253
254 unsigned char* lcr_base; /* local config registers (PCI only) */
255 u32 phys_lcr_base;
256 u32 lcr_offset;
257 int lcr_mem_requested;
258
259 unsigned char* statctrl_base; /* status/control register memory */
260 u32 phys_statctrl_base;
261 u32 statctrl_offset;
262 bool sca_statctrl_requested;
263
264 u32 misc_ctrl_value;
265 char *flag_buf;
266 bool drop_rts_on_tx_done;
267
268 struct _input_signal_events input_signal_events;
269
270 /* SPPP/Cisco HDLC device parts */
271 int netcount;
272 spinlock_t netlock;
273
274 #if SYNCLINK_GENERIC_HDLC
275 struct net_device *netdev;
276 #endif
277
278 } SLMP_INFO;
279
280 #define MGSL_MAGIC 0x5401
281
282 /*
283 * define serial signal status change macros
284 */
285 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
286 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
287 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
288 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
289
290 /* Common Register macros */
291 #define LPR 0x00
292 #define PABR0 0x02
293 #define PABR1 0x03
294 #define WCRL 0x04
295 #define WCRM 0x05
296 #define WCRH 0x06
297 #define DPCR 0x08
298 #define DMER 0x09
299 #define ISR0 0x10
300 #define ISR1 0x11
301 #define ISR2 0x12
302 #define IER0 0x14
303 #define IER1 0x15
304 #define IER2 0x16
305 #define ITCR 0x18
306 #define INTVR 0x1a
307 #define IMVR 0x1c
308
309 /* MSCI Register macros */
310 #define TRB 0x20
311 #define TRBL 0x20
312 #define TRBH 0x21
313 #define SR0 0x22
314 #define SR1 0x23
315 #define SR2 0x24
316 #define SR3 0x25
317 #define FST 0x26
318 #define IE0 0x28
319 #define IE1 0x29
320 #define IE2 0x2a
321 #define FIE 0x2b
322 #define CMD 0x2c
323 #define MD0 0x2e
324 #define MD1 0x2f
325 #define MD2 0x30
326 #define CTL 0x31
327 #define SA0 0x32
328 #define SA1 0x33
329 #define IDL 0x34
330 #define TMC 0x35
331 #define RXS 0x36
332 #define TXS 0x37
333 #define TRC0 0x38
334 #define TRC1 0x39
335 #define RRC 0x3a
336 #define CST0 0x3c
337 #define CST1 0x3d
338
339 /* Timer Register Macros */
340 #define TCNT 0x60
341 #define TCNTL 0x60
342 #define TCNTH 0x61
343 #define TCONR 0x62
344 #define TCONRL 0x62
345 #define TCONRH 0x63
346 #define TMCS 0x64
347 #define TEPR 0x65
348
349 /* DMA Controller Register macros */
350 #define DARL 0x80
351 #define DARH 0x81
352 #define DARB 0x82
353 #define BAR 0x80
354 #define BARL 0x80
355 #define BARH 0x81
356 #define BARB 0x82
357 #define SAR 0x84
358 #define SARL 0x84
359 #define SARH 0x85
360 #define SARB 0x86
361 #define CPB 0x86
362 #define CDA 0x88
363 #define CDAL 0x88
364 #define CDAH 0x89
365 #define EDA 0x8a
366 #define EDAL 0x8a
367 #define EDAH 0x8b
368 #define BFL 0x8c
369 #define BFLL 0x8c
370 #define BFLH 0x8d
371 #define BCR 0x8e
372 #define BCRL 0x8e
373 #define BCRH 0x8f
374 #define DSR 0x90
375 #define DMR 0x91
376 #define FCT 0x93
377 #define DIR 0x94
378 #define DCMD 0x95
379
380 /* combine with timer or DMA register address */
381 #define TIMER0 0x00
382 #define TIMER1 0x08
383 #define TIMER2 0x10
384 #define TIMER3 0x18
385 #define RXDMA 0x00
386 #define TXDMA 0x20
387
388 /* SCA Command Codes */
389 #define NOOP 0x00
390 #define TXRESET 0x01
391 #define TXENABLE 0x02
392 #define TXDISABLE 0x03
393 #define TXCRCINIT 0x04
394 #define TXCRCEXCL 0x05
395 #define TXEOM 0x06
396 #define TXABORT 0x07
397 #define MPON 0x08
398 #define TXBUFCLR 0x09
399 #define RXRESET 0x11
400 #define RXENABLE 0x12
401 #define RXDISABLE 0x13
402 #define RXCRCINIT 0x14
403 #define RXREJECT 0x15
404 #define SEARCHMP 0x16
405 #define RXCRCEXCL 0x17
406 #define RXCRCCALC 0x18
407 #define CHRESET 0x21
408 #define HUNT 0x31
409
410 /* DMA command codes */
411 #define SWABORT 0x01
412 #define FEICLEAR 0x02
413
414 /* IE0 */
415 #define TXINTE BIT7
416 #define RXINTE BIT6
417 #define TXRDYE BIT1
418 #define RXRDYE BIT0
419
420 /* IE1 & SR1 */
421 #define UDRN BIT7
422 #define IDLE BIT6
423 #define SYNCD BIT4
424 #define FLGD BIT4
425 #define CCTS BIT3
426 #define CDCD BIT2
427 #define BRKD BIT1
428 #define ABTD BIT1
429 #define GAPD BIT1
430 #define BRKE BIT0
431 #define IDLD BIT0
432
433 /* IE2 & SR2 */
434 #define EOM BIT7
435 #define PMP BIT6
436 #define SHRT BIT6
437 #define PE BIT5
438 #define ABT BIT5
439 #define FRME BIT4
440 #define RBIT BIT4
441 #define OVRN BIT3
442 #define CRCE BIT2
443
444
445 /*
446 * Global linked list of SyncLink devices
447 */
448 static SLMP_INFO *synclinkmp_device_list = NULL;
449 static int synclinkmp_adapter_count = -1;
450 static int synclinkmp_device_count = 0;
451
452 /*
453 * Set this param to non-zero to load eax with the
454 * .text section address and breakpoint on module load.
455 * This is useful for use with gdb and add-symbol-file command.
456 */
457 static bool break_on_load = 0;
458
459 /*
460 * Driver major number, defaults to zero to get auto
461 * assigned major number. May be forced as module parameter.
462 */
463 static int ttymajor = 0;
464
465 /*
466 * Array of user specified options for ISA adapters.
467 */
468 static int debug_level = 0;
469 static int maxframe[MAX_DEVICES] = {0,};
470
471 module_param(break_on_load, bool, 0);
472 module_param(ttymajor, int, 0);
473 module_param(debug_level, int, 0);
474 module_param_array(maxframe, int, NULL, 0);
475
476 static char *driver_name = "SyncLink MultiPort driver";
477 static char *driver_version = "$Revision: 4.38 $";
478
479 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
480 static void synclinkmp_remove_one(struct pci_dev *dev);
481
482 static const struct pci_device_id synclinkmp_pci_tbl[] = {
483 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
484 { 0, }, /* terminate list */
485 };
486 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
487
488 MODULE_LICENSE("GPL");
489
490 static struct pci_driver synclinkmp_pci_driver = {
491 .name = "synclinkmp",
492 .id_table = synclinkmp_pci_tbl,
493 .probe = synclinkmp_init_one,
494 .remove = synclinkmp_remove_one,
495 };
496
497
498 static struct tty_driver *serial_driver;
499
500 /* number of characters left in xmit buffer before we ask for more */
501 #define WAKEUP_CHARS 256
502
503
504 /* tty callbacks */
505
506 static int open(struct tty_struct *tty, struct file * filp);
507 static void close(struct tty_struct *tty, struct file * filp);
508 static void hangup(struct tty_struct *tty);
509 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
510
511 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
512 static int put_char(struct tty_struct *tty, unsigned char ch);
513 static void send_xchar(struct tty_struct *tty, char ch);
514 static void wait_until_sent(struct tty_struct *tty, int timeout);
515 static int write_room(struct tty_struct *tty);
516 static void flush_chars(struct tty_struct *tty);
517 static void flush_buffer(struct tty_struct *tty);
518 static void tx_hold(struct tty_struct *tty);
519 static void tx_release(struct tty_struct *tty);
520
521 static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
522 static int chars_in_buffer(struct tty_struct *tty);
523 static void throttle(struct tty_struct * tty);
524 static void unthrottle(struct tty_struct * tty);
525 static int set_break(struct tty_struct *tty, int break_state);
526
527 #if SYNCLINK_GENERIC_HDLC
528 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
529 static void hdlcdev_tx_done(SLMP_INFO *info);
530 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
531 static int hdlcdev_init(SLMP_INFO *info);
532 static void hdlcdev_exit(SLMP_INFO *info);
533 #endif
534
535 /* ioctl handlers */
536
537 static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
538 static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
539 static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
540 static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
541 static int set_txidle(SLMP_INFO *info, int idle_mode);
542 static int tx_enable(SLMP_INFO *info, int enable);
543 static int tx_abort(SLMP_INFO *info);
544 static int rx_enable(SLMP_INFO *info, int enable);
545 static int modem_input_wait(SLMP_INFO *info,int arg);
546 static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
547 static int tiocmget(struct tty_struct *tty);
548 static int tiocmset(struct tty_struct *tty,
549 unsigned int set, unsigned int clear);
550 static int set_break(struct tty_struct *tty, int break_state);
551
552 static int add_device(SLMP_INFO *info);
553 static int device_init(int adapter_num, struct pci_dev *pdev);
554 static int claim_resources(SLMP_INFO *info);
555 static void release_resources(SLMP_INFO *info);
556
557 static int startup(SLMP_INFO *info);
558 static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
559 static int carrier_raised(struct tty_port *port);
560 static void shutdown(SLMP_INFO *info);
561 static void program_hw(SLMP_INFO *info);
562 static void change_params(SLMP_INFO *info);
563
564 static bool init_adapter(SLMP_INFO *info);
565 static bool register_test(SLMP_INFO *info);
566 static bool irq_test(SLMP_INFO *info);
567 static bool loopback_test(SLMP_INFO *info);
568 static int adapter_test(SLMP_INFO *info);
569 static bool memory_test(SLMP_INFO *info);
570
571 static void reset_adapter(SLMP_INFO *info);
572 static void reset_port(SLMP_INFO *info);
573 static void async_mode(SLMP_INFO *info);
574 static void hdlc_mode(SLMP_INFO *info);
575
576 static void rx_stop(SLMP_INFO *info);
577 static void rx_start(SLMP_INFO *info);
578 static void rx_reset_buffers(SLMP_INFO *info);
579 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
580 static bool rx_get_frame(SLMP_INFO *info);
581
582 static void tx_start(SLMP_INFO *info);
583 static void tx_stop(SLMP_INFO *info);
584 static void tx_load_fifo(SLMP_INFO *info);
585 static void tx_set_idle(SLMP_INFO *info);
586 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
587
588 static void get_signals(SLMP_INFO *info);
589 static void set_signals(SLMP_INFO *info);
590 static void enable_loopback(SLMP_INFO *info, int enable);
591 static void set_rate(SLMP_INFO *info, u32 data_rate);
592
593 static int bh_action(SLMP_INFO *info);
594 static void bh_handler(struct work_struct *work);
595 static void bh_receive(SLMP_INFO *info);
596 static void bh_transmit(SLMP_INFO *info);
597 static void bh_status(SLMP_INFO *info);
598 static void isr_timer(SLMP_INFO *info);
599 static void isr_rxint(SLMP_INFO *info);
600 static void isr_rxrdy(SLMP_INFO *info);
601 static void isr_txint(SLMP_INFO *info);
602 static void isr_txrdy(SLMP_INFO *info);
603 static void isr_rxdmaok(SLMP_INFO *info);
604 static void isr_rxdmaerror(SLMP_INFO *info);
605 static void isr_txdmaok(SLMP_INFO *info);
606 static void isr_txdmaerror(SLMP_INFO *info);
607 static void isr_io_pin(SLMP_INFO *info, u16 status);
608
609 static int alloc_dma_bufs(SLMP_INFO *info);
610 static void free_dma_bufs(SLMP_INFO *info);
611 static int alloc_buf_list(SLMP_INFO *info);
612 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
613 static int alloc_tmp_rx_buf(SLMP_INFO *info);
614 static void free_tmp_rx_buf(SLMP_INFO *info);
615
616 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
617 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
618 static void tx_timeout(struct timer_list *t);
619 static void status_timeout(struct timer_list *t);
620
621 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
622 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
623 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
624 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
625 static unsigned char read_status_reg(SLMP_INFO * info);
626 static void write_control_reg(SLMP_INFO * info);
627
628
629 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
630 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
631 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
632
633 static u32 misc_ctrl_value = 0x007e4040;
634 static u32 lcr1_brdr_value = 0x00800028;
635
636 static u32 read_ahead_count = 8;
637
638 /* DPCR, DMA Priority Control
639 *
640 * 07..05 Not used, must be 0
641 * 04 BRC, bus release condition: 0=all transfers complete
642 * 1=release after 1 xfer on all channels
643 * 03 CCC, channel change condition: 0=every cycle
644 * 1=after each channel completes all xfers
645 * 02..00 PR<2..0>, priority 100=round robin
646 *
647 * 00000100 = 0x00
648 */
649 static unsigned char dma_priority = 0x04;
650
651 // Number of bytes that can be written to shared RAM
652 // in a single write operation
653 static u32 sca_pci_load_interval = 64;
654
655 /*
656 * 1st function defined in .text section. Calling this function in
657 * init_module() followed by a breakpoint allows a remote debugger
658 * (gdb) to get the .text address for the add-symbol-file command.
659 * This allows remote debugging of dynamically loadable modules.
660 */
661 static void* synclinkmp_get_text_ptr(void);
662 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
663
664 static inline int sanity_check(SLMP_INFO *info,
665 char *name, const char *routine)
666 {
667 #ifdef SANITY_CHECK
668 static const char *badmagic =
669 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
670 static const char *badinfo =
671 "Warning: null synclinkmp_struct for (%s) in %s\n";
672
673 if (!info) {
674 printk(badinfo, name, routine);
675 return 1;
676 }
677 if (info->magic != MGSL_MAGIC) {
678 printk(badmagic, name, routine);
679 return 1;
680 }
681 #else
682 if (!info)
683 return 1;
684 #endif
685 return 0;
686 }
687
688 /**
689 * line discipline callback wrappers
690 *
691 * The wrappers maintain line discipline references
692 * while calling into the line discipline.
693 *
694 * ldisc_receive_buf - pass receive data to line discipline
695 */
696
697 static void ldisc_receive_buf(struct tty_struct *tty,
698 const __u8 *data, char *flags, int count)
699 {
700 struct tty_ldisc *ld;
701 if (!tty)
702 return;
703 ld = tty_ldisc_ref(tty);
704 if (ld) {
705 if (ld->ops->receive_buf)
706 ld->ops->receive_buf(tty, data, flags, count);
707 tty_ldisc_deref(ld);
708 }
709 }
710
711 /* tty callbacks */
712
713 static int install(struct tty_driver *driver, struct tty_struct *tty)
714 {
715 SLMP_INFO *info;
716 int line = tty->index;
717
718 if (line >= synclinkmp_device_count) {
719 printk("%s(%d): open with invalid line #%d.\n",
720 __FILE__,__LINE__,line);
721 return -ENODEV;
722 }
723
724 info = synclinkmp_device_list;
725 while (info && info->line != line)
726 info = info->next_device;
727 if (sanity_check(info, tty->name, "open"))
728 return -ENODEV;
729 if (info->init_error) {
730 printk("%s(%d):%s device is not allocated, init error=%d\n",
731 __FILE__, __LINE__, info->device_name,
732 info->init_error);
733 return -ENODEV;
734 }
735
736 tty->driver_data = info;
737
738 return tty_port_install(&info->port, driver, tty);
739 }
740
741 /* Called when a port is opened. Init and enable port.
742 */
743 static int open(struct tty_struct *tty, struct file *filp)
744 {
745 SLMP_INFO *info = tty->driver_data;
746 unsigned long flags;
747 int retval;
748
749 info->port.tty = tty;
750
751 if (debug_level >= DEBUG_LEVEL_INFO)
752 printk("%s(%d):%s open(), old ref count = %d\n",
753 __FILE__,__LINE__,tty->driver->name, info->port.count);
754
755 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
756
757 spin_lock_irqsave(&info->netlock, flags);
758 if (info->netcount) {
759 retval = -EBUSY;
760 spin_unlock_irqrestore(&info->netlock, flags);
761 goto cleanup;
762 }
763 info->port.count++;
764 spin_unlock_irqrestore(&info->netlock, flags);
765
766 if (info->port.count == 1) {
767 /* 1st open on this device, init hardware */
768 retval = startup(info);
769 if (retval < 0)
770 goto cleanup;
771 }
772
773 retval = block_til_ready(tty, filp, info);
774 if (retval) {
775 if (debug_level >= DEBUG_LEVEL_INFO)
776 printk("%s(%d):%s block_til_ready() returned %d\n",
777 __FILE__,__LINE__, info->device_name, retval);
778 goto cleanup;
779 }
780
781 if (debug_level >= DEBUG_LEVEL_INFO)
782 printk("%s(%d):%s open() success\n",
783 __FILE__,__LINE__, info->device_name);
784 retval = 0;
785
786 cleanup:
787 if (retval) {
788 if (tty->count == 1)
789 info->port.tty = NULL; /* tty layer will release tty struct */
790 if(info->port.count)
791 info->port.count--;
792 }
793
794 return retval;
795 }
796
797 /* Called when port is closed. Wait for remaining data to be
798 * sent. Disable port and free resources.
799 */
800 static void close(struct tty_struct *tty, struct file *filp)
801 {
802 SLMP_INFO * info = tty->driver_data;
803
804 if (sanity_check(info, tty->name, "close"))
805 return;
806
807 if (debug_level >= DEBUG_LEVEL_INFO)
808 printk("%s(%d):%s close() entry, count=%d\n",
809 __FILE__,__LINE__, info->device_name, info->port.count);
810
811 if (tty_port_close_start(&info->port, tty, filp) == 0)
812 goto cleanup;
813
814 mutex_lock(&info->port.mutex);
815 if (tty_port_initialized(&info->port))
816 wait_until_sent(tty, info->timeout);
817
818 flush_buffer(tty);
819 tty_ldisc_flush(tty);
820 shutdown(info);
821 mutex_unlock(&info->port.mutex);
822
823 tty_port_close_end(&info->port, tty);
824 info->port.tty = NULL;
825 cleanup:
826 if (debug_level >= DEBUG_LEVEL_INFO)
827 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
828 tty->driver->name, info->port.count);
829 }
830
831 /* Called by tty_hangup() when a hangup is signaled.
832 * This is the same as closing all open descriptors for the port.
833 */
834 static void hangup(struct tty_struct *tty)
835 {
836 SLMP_INFO *info = tty->driver_data;
837 unsigned long flags;
838
839 if (debug_level >= DEBUG_LEVEL_INFO)
840 printk("%s(%d):%s hangup()\n",
841 __FILE__,__LINE__, info->device_name );
842
843 if (sanity_check(info, tty->name, "hangup"))
844 return;
845
846 mutex_lock(&info->port.mutex);
847 flush_buffer(tty);
848 shutdown(info);
849
850 spin_lock_irqsave(&info->port.lock, flags);
851 info->port.count = 0;
852 info->port.tty = NULL;
853 spin_unlock_irqrestore(&info->port.lock, flags);
854 tty_port_set_active(&info->port, 1);
855 mutex_unlock(&info->port.mutex);
856
857 wake_up_interruptible(&info->port.open_wait);
858 }
859
860 /* Set new termios settings
861 */
862 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
863 {
864 SLMP_INFO *info = tty->driver_data;
865 unsigned long flags;
866
867 if (debug_level >= DEBUG_LEVEL_INFO)
868 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
869 tty->driver->name );
870
871 change_params(info);
872
873 /* Handle transition to B0 status */
874 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
875 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
876 spin_lock_irqsave(&info->lock,flags);
877 set_signals(info);
878 spin_unlock_irqrestore(&info->lock,flags);
879 }
880
881 /* Handle transition away from B0 status */
882 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
883 info->serial_signals |= SerialSignal_DTR;
884 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
885 info->serial_signals |= SerialSignal_RTS;
886 spin_lock_irqsave(&info->lock,flags);
887 set_signals(info);
888 spin_unlock_irqrestore(&info->lock,flags);
889 }
890
891 /* Handle turning off CRTSCTS */
892 if (old_termios->c_cflag & CRTSCTS && !C_CRTSCTS(tty)) {
893 tty->hw_stopped = 0;
894 tx_release(tty);
895 }
896 }
897
898 /* Send a block of data
899 *
900 * Arguments:
901 *
902 * tty pointer to tty information structure
903 * buf pointer to buffer containing send data
904 * count size of send data in bytes
905 *
906 * Return Value: number of characters written
907 */
908 static int write(struct tty_struct *tty,
909 const unsigned char *buf, int count)
910 {
911 int c, ret = 0;
912 SLMP_INFO *info = tty->driver_data;
913 unsigned long flags;
914
915 if (debug_level >= DEBUG_LEVEL_INFO)
916 printk("%s(%d):%s write() count=%d\n",
917 __FILE__,__LINE__,info->device_name,count);
918
919 if (sanity_check(info, tty->name, "write"))
920 goto cleanup;
921
922 if (!info->tx_buf)
923 goto cleanup;
924
925 if (info->params.mode == MGSL_MODE_HDLC) {
926 if (count > info->max_frame_size) {
927 ret = -EIO;
928 goto cleanup;
929 }
930 if (info->tx_active)
931 goto cleanup;
932 if (info->tx_count) {
933 /* send accumulated data from send_char() calls */
934 /* as frame and wait before accepting more data. */
935 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
936 goto start;
937 }
938 ret = info->tx_count = count;
939 tx_load_dma_buffer(info, buf, count);
940 goto start;
941 }
942
943 for (;;) {
944 c = min_t(int, count,
945 min(info->max_frame_size - info->tx_count - 1,
946 info->max_frame_size - info->tx_put));
947 if (c <= 0)
948 break;
949
950 memcpy(info->tx_buf + info->tx_put, buf, c);
951
952 spin_lock_irqsave(&info->lock,flags);
953 info->tx_put += c;
954 if (info->tx_put >= info->max_frame_size)
955 info->tx_put -= info->max_frame_size;
956 info->tx_count += c;
957 spin_unlock_irqrestore(&info->lock,flags);
958
959 buf += c;
960 count -= c;
961 ret += c;
962 }
963
964 if (info->params.mode == MGSL_MODE_HDLC) {
965 if (count) {
966 ret = info->tx_count = 0;
967 goto cleanup;
968 }
969 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
970 }
971 start:
972 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
973 spin_lock_irqsave(&info->lock,flags);
974 if (!info->tx_active)
975 tx_start(info);
976 spin_unlock_irqrestore(&info->lock,flags);
977 }
978
979 cleanup:
980 if (debug_level >= DEBUG_LEVEL_INFO)
981 printk( "%s(%d):%s write() returning=%d\n",
982 __FILE__,__LINE__,info->device_name,ret);
983 return ret;
984 }
985
986 /* Add a character to the transmit buffer.
987 */
988 static int put_char(struct tty_struct *tty, unsigned char ch)
989 {
990 SLMP_INFO *info = tty->driver_data;
991 unsigned long flags;
992 int ret = 0;
993
994 if ( debug_level >= DEBUG_LEVEL_INFO ) {
995 printk( "%s(%d):%s put_char(%d)\n",
996 __FILE__,__LINE__,info->device_name,ch);
997 }
998
999 if (sanity_check(info, tty->name, "put_char"))
1000 return 0;
1001
1002 if (!info->tx_buf)
1003 return 0;
1004
1005 spin_lock_irqsave(&info->lock,flags);
1006
1007 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1008 !info->tx_active ) {
1009
1010 if (info->tx_count < info->max_frame_size - 1) {
1011 info->tx_buf[info->tx_put++] = ch;
1012 if (info->tx_put >= info->max_frame_size)
1013 info->tx_put -= info->max_frame_size;
1014 info->tx_count++;
1015 ret = 1;
1016 }
1017 }
1018
1019 spin_unlock_irqrestore(&info->lock,flags);
1020 return ret;
1021 }
1022
1023 /* Send a high-priority XON/XOFF character
1024 */
1025 static void send_xchar(struct tty_struct *tty, char ch)
1026 {
1027 SLMP_INFO *info = tty->driver_data;
1028 unsigned long flags;
1029
1030 if (debug_level >= DEBUG_LEVEL_INFO)
1031 printk("%s(%d):%s send_xchar(%d)\n",
1032 __FILE__,__LINE__, info->device_name, ch );
1033
1034 if (sanity_check(info, tty->name, "send_xchar"))
1035 return;
1036
1037 info->x_char = ch;
1038 if (ch) {
1039 /* Make sure transmit interrupts are on */
1040 spin_lock_irqsave(&info->lock,flags);
1041 if (!info->tx_enabled)
1042 tx_start(info);
1043 spin_unlock_irqrestore(&info->lock,flags);
1044 }
1045 }
1046
1047 /* Wait until the transmitter is empty.
1048 */
1049 static void wait_until_sent(struct tty_struct *tty, int timeout)
1050 {
1051 SLMP_INFO * info = tty->driver_data;
1052 unsigned long orig_jiffies, char_time;
1053
1054 if (!info )
1055 return;
1056
1057 if (debug_level >= DEBUG_LEVEL_INFO)
1058 printk("%s(%d):%s wait_until_sent() entry\n",
1059 __FILE__,__LINE__, info->device_name );
1060
1061 if (sanity_check(info, tty->name, "wait_until_sent"))
1062 return;
1063
1064 if (!tty_port_initialized(&info->port))
1065 goto exit;
1066
1067 orig_jiffies = jiffies;
1068
1069 /* Set check interval to 1/5 of estimated time to
1070 * send a character, and make it at least 1. The check
1071 * interval should also be less than the timeout.
1072 * Note: use tight timings here to satisfy the NIST-PCTS.
1073 */
1074
1075 if ( info->params.data_rate ) {
1076 char_time = info->timeout/(32 * 5);
1077 if (!char_time)
1078 char_time++;
1079 } else
1080 char_time = 1;
1081
1082 if (timeout)
1083 char_time = min_t(unsigned long, char_time, timeout);
1084
1085 if ( info->params.mode == MGSL_MODE_HDLC ) {
1086 while (info->tx_active) {
1087 msleep_interruptible(jiffies_to_msecs(char_time));
1088 if (signal_pending(current))
1089 break;
1090 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1091 break;
1092 }
1093 } else {
1094 /*
1095 * TODO: determine if there is something similar to USC16C32
1096 * TXSTATUS_ALL_SENT status
1097 */
1098 while ( info->tx_active && info->tx_enabled) {
1099 msleep_interruptible(jiffies_to_msecs(char_time));
1100 if (signal_pending(current))
1101 break;
1102 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1103 break;
1104 }
1105 }
1106
1107 exit:
1108 if (debug_level >= DEBUG_LEVEL_INFO)
1109 printk("%s(%d):%s wait_until_sent() exit\n",
1110 __FILE__,__LINE__, info->device_name );
1111 }
1112
1113 /* Return the count of free bytes in transmit buffer
1114 */
1115 static int write_room(struct tty_struct *tty)
1116 {
1117 SLMP_INFO *info = tty->driver_data;
1118 int ret;
1119
1120 if (sanity_check(info, tty->name, "write_room"))
1121 return 0;
1122
1123 if (info->params.mode == MGSL_MODE_HDLC) {
1124 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1125 } else {
1126 ret = info->max_frame_size - info->tx_count - 1;
1127 if (ret < 0)
1128 ret = 0;
1129 }
1130
1131 if (debug_level >= DEBUG_LEVEL_INFO)
1132 printk("%s(%d):%s write_room()=%d\n",
1133 __FILE__, __LINE__, info->device_name, ret);
1134
1135 return ret;
1136 }
1137
1138 /* enable transmitter and send remaining buffered characters
1139 */
1140 static void flush_chars(struct tty_struct *tty)
1141 {
1142 SLMP_INFO *info = tty->driver_data;
1143 unsigned long flags;
1144
1145 if ( debug_level >= DEBUG_LEVEL_INFO )
1146 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1147 __FILE__,__LINE__,info->device_name,info->tx_count);
1148
1149 if (sanity_check(info, tty->name, "flush_chars"))
1150 return;
1151
1152 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1153 !info->tx_buf)
1154 return;
1155
1156 if ( debug_level >= DEBUG_LEVEL_INFO )
1157 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1158 __FILE__,__LINE__,info->device_name );
1159
1160 spin_lock_irqsave(&info->lock,flags);
1161
1162 if (!info->tx_active) {
1163 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1164 info->tx_count ) {
1165 /* operating in synchronous (frame oriented) mode */
1166 /* copy data from circular tx_buf to */
1167 /* transmit DMA buffer. */
1168 tx_load_dma_buffer(info,
1169 info->tx_buf,info->tx_count);
1170 }
1171 tx_start(info);
1172 }
1173
1174 spin_unlock_irqrestore(&info->lock,flags);
1175 }
1176
1177 /* Discard all data in the send buffer
1178 */
1179 static void flush_buffer(struct tty_struct *tty)
1180 {
1181 SLMP_INFO *info = tty->driver_data;
1182 unsigned long flags;
1183
1184 if (debug_level >= DEBUG_LEVEL_INFO)
1185 printk("%s(%d):%s flush_buffer() entry\n",
1186 __FILE__,__LINE__, info->device_name );
1187
1188 if (sanity_check(info, tty->name, "flush_buffer"))
1189 return;
1190
1191 spin_lock_irqsave(&info->lock,flags);
1192 info->tx_count = info->tx_put = info->tx_get = 0;
1193 del_timer(&info->tx_timer);
1194 spin_unlock_irqrestore(&info->lock,flags);
1195
1196 tty_wakeup(tty);
1197 }
1198
1199 /* throttle (stop) transmitter
1200 */
1201 static void tx_hold(struct tty_struct *tty)
1202 {
1203 SLMP_INFO *info = tty->driver_data;
1204 unsigned long flags;
1205
1206 if (sanity_check(info, tty->name, "tx_hold"))
1207 return;
1208
1209 if ( debug_level >= DEBUG_LEVEL_INFO )
1210 printk("%s(%d):%s tx_hold()\n",
1211 __FILE__,__LINE__,info->device_name);
1212
1213 spin_lock_irqsave(&info->lock,flags);
1214 if (info->tx_enabled)
1215 tx_stop(info);
1216 spin_unlock_irqrestore(&info->lock,flags);
1217 }
1218
1219 /* release (start) transmitter
1220 */
1221 static void tx_release(struct tty_struct *tty)
1222 {
1223 SLMP_INFO *info = tty->driver_data;
1224 unsigned long flags;
1225
1226 if (sanity_check(info, tty->name, "tx_release"))
1227 return;
1228
1229 if ( debug_level >= DEBUG_LEVEL_INFO )
1230 printk("%s(%d):%s tx_release()\n",
1231 __FILE__,__LINE__,info->device_name);
1232
1233 spin_lock_irqsave(&info->lock,flags);
1234 if (!info->tx_enabled)
1235 tx_start(info);
1236 spin_unlock_irqrestore(&info->lock,flags);
1237 }
1238
1239 /* Service an IOCTL request
1240 *
1241 * Arguments:
1242 *
1243 * tty pointer to tty instance data
1244 * cmd IOCTL command code
1245 * arg command argument/context
1246 *
1247 * Return Value: 0 if success, otherwise error code
1248 */
1249 static int ioctl(struct tty_struct *tty,
1250 unsigned int cmd, unsigned long arg)
1251 {
1252 SLMP_INFO *info = tty->driver_data;
1253 void __user *argp = (void __user *)arg;
1254
1255 if (debug_level >= DEBUG_LEVEL_INFO)
1256 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1257 info->device_name, cmd );
1258
1259 if (sanity_check(info, tty->name, "ioctl"))
1260 return -ENODEV;
1261
1262 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1263 (cmd != TIOCMIWAIT)) {
1264 if (tty_io_error(tty))
1265 return -EIO;
1266 }
1267
1268 switch (cmd) {
1269 case MGSL_IOCGPARAMS:
1270 return get_params(info, argp);
1271 case MGSL_IOCSPARAMS:
1272 return set_params(info, argp);
1273 case MGSL_IOCGTXIDLE:
1274 return get_txidle(info, argp);
1275 case MGSL_IOCSTXIDLE:
1276 return set_txidle(info, (int)arg);
1277 case MGSL_IOCTXENABLE:
1278 return tx_enable(info, (int)arg);
1279 case MGSL_IOCRXENABLE:
1280 return rx_enable(info, (int)arg);
1281 case MGSL_IOCTXABORT:
1282 return tx_abort(info);
1283 case MGSL_IOCGSTATS:
1284 return get_stats(info, argp);
1285 case MGSL_IOCWAITEVENT:
1286 return wait_mgsl_event(info, argp);
1287 case MGSL_IOCLOOPTXDONE:
1288 return 0; // TODO: Not supported, need to document
1289 /* Wait for modem input (DCD,RI,DSR,CTS) change
1290 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1291 */
1292 case TIOCMIWAIT:
1293 return modem_input_wait(info,(int)arg);
1294
1295 /*
1296 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1297 * Return: write counters to the user passed counter struct
1298 * NB: both 1->0 and 0->1 transitions are counted except for
1299 * RI where only 0->1 is counted.
1300 */
1301 default:
1302 return -ENOIOCTLCMD;
1303 }
1304 return 0;
1305 }
1306
1307 static int get_icount(struct tty_struct *tty,
1308 struct serial_icounter_struct *icount)
1309 {
1310 SLMP_INFO *info = tty->driver_data;
1311 struct mgsl_icount cnow; /* kernel counter temps */
1312 unsigned long flags;
1313
1314 spin_lock_irqsave(&info->lock,flags);
1315 cnow = info->icount;
1316 spin_unlock_irqrestore(&info->lock,flags);
1317
1318 icount->cts = cnow.cts;
1319 icount->dsr = cnow.dsr;
1320 icount->rng = cnow.rng;
1321 icount->dcd = cnow.dcd;
1322 icount->rx = cnow.rx;
1323 icount->tx = cnow.tx;
1324 icount->frame = cnow.frame;
1325 icount->overrun = cnow.overrun;
1326 icount->parity = cnow.parity;
1327 icount->brk = cnow.brk;
1328 icount->buf_overrun = cnow.buf_overrun;
1329
1330 return 0;
1331 }
1332
1333 /*
1334 * /proc fs routines....
1335 */
1336
1337 static inline void line_info(struct seq_file *m, SLMP_INFO *info)
1338 {
1339 char stat_buf[30];
1340 unsigned long flags;
1341
1342 seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1343 "\tIRQ=%d MaxFrameSize=%u\n",
1344 info->device_name,
1345 info->phys_sca_base,
1346 info->phys_memory_base,
1347 info->phys_statctrl_base,
1348 info->phys_lcr_base,
1349 info->irq_level,
1350 info->max_frame_size );
1351
1352 /* output current serial signal states */
1353 spin_lock_irqsave(&info->lock,flags);
1354 get_signals(info);
1355 spin_unlock_irqrestore(&info->lock,flags);
1356
1357 stat_buf[0] = 0;
1358 stat_buf[1] = 0;
1359 if (info->serial_signals & SerialSignal_RTS)
1360 strcat(stat_buf, "|RTS");
1361 if (info->serial_signals & SerialSignal_CTS)
1362 strcat(stat_buf, "|CTS");
1363 if (info->serial_signals & SerialSignal_DTR)
1364 strcat(stat_buf, "|DTR");
1365 if (info->serial_signals & SerialSignal_DSR)
1366 strcat(stat_buf, "|DSR");
1367 if (info->serial_signals & SerialSignal_DCD)
1368 strcat(stat_buf, "|CD");
1369 if (info->serial_signals & SerialSignal_RI)
1370 strcat(stat_buf, "|RI");
1371
1372 if (info->params.mode == MGSL_MODE_HDLC) {
1373 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1374 info->icount.txok, info->icount.rxok);
1375 if (info->icount.txunder)
1376 seq_printf(m, " txunder:%d", info->icount.txunder);
1377 if (info->icount.txabort)
1378 seq_printf(m, " txabort:%d", info->icount.txabort);
1379 if (info->icount.rxshort)
1380 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1381 if (info->icount.rxlong)
1382 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1383 if (info->icount.rxover)
1384 seq_printf(m, " rxover:%d", info->icount.rxover);
1385 if (info->icount.rxcrc)
1386 seq_printf(m, " rxlong:%d", info->icount.rxcrc);
1387 } else {
1388 seq_printf(m, "\tASYNC tx:%d rx:%d",
1389 info->icount.tx, info->icount.rx);
1390 if (info->icount.frame)
1391 seq_printf(m, " fe:%d", info->icount.frame);
1392 if (info->icount.parity)
1393 seq_printf(m, " pe:%d", info->icount.parity);
1394 if (info->icount.brk)
1395 seq_printf(m, " brk:%d", info->icount.brk);
1396 if (info->icount.overrun)
1397 seq_printf(m, " oe:%d", info->icount.overrun);
1398 }
1399
1400 /* Append serial signal status to end */
1401 seq_printf(m, " %s\n", stat_buf+1);
1402
1403 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1404 info->tx_active,info->bh_requested,info->bh_running,
1405 info->pending_bh);
1406 }
1407
1408 /* Called to print information about devices
1409 */
1410 static int synclinkmp_proc_show(struct seq_file *m, void *v)
1411 {
1412 SLMP_INFO *info;
1413
1414 seq_printf(m, "synclinkmp driver:%s\n", driver_version);
1415
1416 info = synclinkmp_device_list;
1417 while( info ) {
1418 line_info(m, info);
1419 info = info->next_device;
1420 }
1421 return 0;
1422 }
1423
1424 /* Return the count of bytes in transmit buffer
1425 */
1426 static int chars_in_buffer(struct tty_struct *tty)
1427 {
1428 SLMP_INFO *info = tty->driver_data;
1429
1430 if (sanity_check(info, tty->name, "chars_in_buffer"))
1431 return 0;
1432
1433 if (debug_level >= DEBUG_LEVEL_INFO)
1434 printk("%s(%d):%s chars_in_buffer()=%d\n",
1435 __FILE__, __LINE__, info->device_name, info->tx_count);
1436
1437 return info->tx_count;
1438 }
1439
1440 /* Signal remote device to throttle send data (our receive data)
1441 */
1442 static void throttle(struct tty_struct * tty)
1443 {
1444 SLMP_INFO *info = tty->driver_data;
1445 unsigned long flags;
1446
1447 if (debug_level >= DEBUG_LEVEL_INFO)
1448 printk("%s(%d):%s throttle() entry\n",
1449 __FILE__,__LINE__, info->device_name );
1450
1451 if (sanity_check(info, tty->name, "throttle"))
1452 return;
1453
1454 if (I_IXOFF(tty))
1455 send_xchar(tty, STOP_CHAR(tty));
1456
1457 if (C_CRTSCTS(tty)) {
1458 spin_lock_irqsave(&info->lock,flags);
1459 info->serial_signals &= ~SerialSignal_RTS;
1460 set_signals(info);
1461 spin_unlock_irqrestore(&info->lock,flags);
1462 }
1463 }
1464
1465 /* Signal remote device to stop throttling send data (our receive data)
1466 */
1467 static void unthrottle(struct tty_struct * tty)
1468 {
1469 SLMP_INFO *info = tty->driver_data;
1470 unsigned long flags;
1471
1472 if (debug_level >= DEBUG_LEVEL_INFO)
1473 printk("%s(%d):%s unthrottle() entry\n",
1474 __FILE__,__LINE__, info->device_name );
1475
1476 if (sanity_check(info, tty->name, "unthrottle"))
1477 return;
1478
1479 if (I_IXOFF(tty)) {
1480 if (info->x_char)
1481 info->x_char = 0;
1482 else
1483 send_xchar(tty, START_CHAR(tty));
1484 }
1485
1486 if (C_CRTSCTS(tty)) {
1487 spin_lock_irqsave(&info->lock,flags);
1488 info->serial_signals |= SerialSignal_RTS;
1489 set_signals(info);
1490 spin_unlock_irqrestore(&info->lock,flags);
1491 }
1492 }
1493
1494 /* set or clear transmit break condition
1495 * break_state -1=set break condition, 0=clear
1496 */
1497 static int set_break(struct tty_struct *tty, int break_state)
1498 {
1499 unsigned char RegValue;
1500 SLMP_INFO * info = tty->driver_data;
1501 unsigned long flags;
1502
1503 if (debug_level >= DEBUG_LEVEL_INFO)
1504 printk("%s(%d):%s set_break(%d)\n",
1505 __FILE__,__LINE__, info->device_name, break_state);
1506
1507 if (sanity_check(info, tty->name, "set_break"))
1508 return -EINVAL;
1509
1510 spin_lock_irqsave(&info->lock,flags);
1511 RegValue = read_reg(info, CTL);
1512 if (break_state == -1)
1513 RegValue |= BIT3;
1514 else
1515 RegValue &= ~BIT3;
1516 write_reg(info, CTL, RegValue);
1517 spin_unlock_irqrestore(&info->lock,flags);
1518 return 0;
1519 }
1520
1521 #if SYNCLINK_GENERIC_HDLC
1522
1523 /**
1524 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1525 * set encoding and frame check sequence (FCS) options
1526 *
1527 * dev pointer to network device structure
1528 * encoding serial encoding setting
1529 * parity FCS setting
1530 *
1531 * returns 0 if success, otherwise error code
1532 */
1533 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1534 unsigned short parity)
1535 {
1536 SLMP_INFO *info = dev_to_port(dev);
1537 unsigned char new_encoding;
1538 unsigned short new_crctype;
1539
1540 /* return error if TTY interface open */
1541 if (info->port.count)
1542 return -EBUSY;
1543
1544 switch (encoding)
1545 {
1546 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1547 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1548 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1549 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1550 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1551 default: return -EINVAL;
1552 }
1553
1554 switch (parity)
1555 {
1556 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1557 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1558 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1559 default: return -EINVAL;
1560 }
1561
1562 info->params.encoding = new_encoding;
1563 info->params.crc_type = new_crctype;
1564
1565 /* if network interface up, reprogram hardware */
1566 if (info->netcount)
1567 program_hw(info);
1568
1569 return 0;
1570 }
1571
1572 /**
1573 * called by generic HDLC layer to send frame
1574 *
1575 * skb socket buffer containing HDLC frame
1576 * dev pointer to network device structure
1577 */
1578 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1579 struct net_device *dev)
1580 {
1581 SLMP_INFO *info = dev_to_port(dev);
1582 unsigned long flags;
1583
1584 if (debug_level >= DEBUG_LEVEL_INFO)
1585 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1586
1587 /* stop sending until this frame completes */
1588 netif_stop_queue(dev);
1589
1590 /* copy data to device buffers */
1591 info->tx_count = skb->len;
1592 tx_load_dma_buffer(info, skb->data, skb->len);
1593
1594 /* update network statistics */
1595 dev->stats.tx_packets++;
1596 dev->stats.tx_bytes += skb->len;
1597
1598 /* done with socket buffer, so free it */
1599 dev_kfree_skb(skb);
1600
1601 /* save start time for transmit timeout detection */
1602 netif_trans_update(dev);
1603
1604 /* start hardware transmitter if necessary */
1605 spin_lock_irqsave(&info->lock,flags);
1606 if (!info->tx_active)
1607 tx_start(info);
1608 spin_unlock_irqrestore(&info->lock,flags);
1609
1610 return NETDEV_TX_OK;
1611 }
1612
1613 /**
1614 * called by network layer when interface enabled
1615 * claim resources and initialize hardware
1616 *
1617 * dev pointer to network device structure
1618 *
1619 * returns 0 if success, otherwise error code
1620 */
1621 static int hdlcdev_open(struct net_device *dev)
1622 {
1623 SLMP_INFO *info = dev_to_port(dev);
1624 int rc;
1625 unsigned long flags;
1626
1627 if (debug_level >= DEBUG_LEVEL_INFO)
1628 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1629
1630 /* generic HDLC layer open processing */
1631 rc = hdlc_open(dev);
1632 if (rc)
1633 return rc;
1634
1635 /* arbitrate between network and tty opens */
1636 spin_lock_irqsave(&info->netlock, flags);
1637 if (info->port.count != 0 || info->netcount != 0) {
1638 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1639 spin_unlock_irqrestore(&info->netlock, flags);
1640 return -EBUSY;
1641 }
1642 info->netcount=1;
1643 spin_unlock_irqrestore(&info->netlock, flags);
1644
1645 /* claim resources and init adapter */
1646 if ((rc = startup(info)) != 0) {
1647 spin_lock_irqsave(&info->netlock, flags);
1648 info->netcount=0;
1649 spin_unlock_irqrestore(&info->netlock, flags);
1650 return rc;
1651 }
1652
1653 /* assert RTS and DTR, apply hardware settings */
1654 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1655 program_hw(info);
1656
1657 /* enable network layer transmit */
1658 netif_trans_update(dev);
1659 netif_start_queue(dev);
1660
1661 /* inform generic HDLC layer of current DCD status */
1662 spin_lock_irqsave(&info->lock, flags);
1663 get_signals(info);
1664 spin_unlock_irqrestore(&info->lock, flags);
1665 if (info->serial_signals & SerialSignal_DCD)
1666 netif_carrier_on(dev);
1667 else
1668 netif_carrier_off(dev);
1669 return 0;
1670 }
1671
1672 /**
1673 * called by network layer when interface is disabled
1674 * shutdown hardware and release resources
1675 *
1676 * dev pointer to network device structure
1677 *
1678 * returns 0 if success, otherwise error code
1679 */
1680 static int hdlcdev_close(struct net_device *dev)
1681 {
1682 SLMP_INFO *info = dev_to_port(dev);
1683 unsigned long flags;
1684
1685 if (debug_level >= DEBUG_LEVEL_INFO)
1686 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1687
1688 netif_stop_queue(dev);
1689
1690 /* shutdown adapter and release resources */
1691 shutdown(info);
1692
1693 hdlc_close(dev);
1694
1695 spin_lock_irqsave(&info->netlock, flags);
1696 info->netcount=0;
1697 spin_unlock_irqrestore(&info->netlock, flags);
1698
1699 return 0;
1700 }
1701
1702 /**
1703 * called by network layer to process IOCTL call to network device
1704 *
1705 * dev pointer to network device structure
1706 * ifr pointer to network interface request structure
1707 * cmd IOCTL command code
1708 *
1709 * returns 0 if success, otherwise error code
1710 */
1711 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1712 {
1713 const size_t size = sizeof(sync_serial_settings);
1714 sync_serial_settings new_line;
1715 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1716 SLMP_INFO *info = dev_to_port(dev);
1717 unsigned int flags;
1718
1719 if (debug_level >= DEBUG_LEVEL_INFO)
1720 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1721
1722 /* return error if TTY interface open */
1723 if (info->port.count)
1724 return -EBUSY;
1725
1726 if (cmd != SIOCWANDEV)
1727 return hdlc_ioctl(dev, ifr, cmd);
1728
1729 switch(ifr->ifr_settings.type) {
1730 case IF_GET_IFACE: /* return current sync_serial_settings */
1731
1732 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1733 if (ifr->ifr_settings.size < size) {
1734 ifr->ifr_settings.size = size; /* data size wanted */
1735 return -ENOBUFS;
1736 }
1737
1738 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1739 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1740 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1741 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1742
1743 memset(&new_line, 0, sizeof(new_line));
1744 switch (flags){
1745 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1746 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1747 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1748 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1749 default: new_line.clock_type = CLOCK_DEFAULT;
1750 }
1751
1752 new_line.clock_rate = info->params.clock_speed;
1753 new_line.loopback = info->params.loopback ? 1:0;
1754
1755 if (copy_to_user(line, &new_line, size))
1756 return -EFAULT;
1757 return 0;
1758
1759 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1760
1761 if(!capable(CAP_NET_ADMIN))
1762 return -EPERM;
1763 if (copy_from_user(&new_line, line, size))
1764 return -EFAULT;
1765
1766 switch (new_line.clock_type)
1767 {
1768 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1769 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1770 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1771 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1772 case CLOCK_DEFAULT: flags = info->params.flags &
1773 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1774 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1775 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1776 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1777 default: return -EINVAL;
1778 }
1779
1780 if (new_line.loopback != 0 && new_line.loopback != 1)
1781 return -EINVAL;
1782
1783 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1784 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1785 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1786 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1787 info->params.flags |= flags;
1788
1789 info->params.loopback = new_line.loopback;
1790
1791 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1792 info->params.clock_speed = new_line.clock_rate;
1793 else
1794 info->params.clock_speed = 0;
1795
1796 /* if network interface up, reprogram hardware */
1797 if (info->netcount)
1798 program_hw(info);
1799 return 0;
1800
1801 default:
1802 return hdlc_ioctl(dev, ifr, cmd);
1803 }
1804 }
1805
1806 /**
1807 * called by network layer when transmit timeout is detected
1808 *
1809 * dev pointer to network device structure
1810 */
1811 static void hdlcdev_tx_timeout(struct net_device *dev)
1812 {
1813 SLMP_INFO *info = dev_to_port(dev);
1814 unsigned long flags;
1815
1816 if (debug_level >= DEBUG_LEVEL_INFO)
1817 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1818
1819 dev->stats.tx_errors++;
1820 dev->stats.tx_aborted_errors++;
1821
1822 spin_lock_irqsave(&info->lock,flags);
1823 tx_stop(info);
1824 spin_unlock_irqrestore(&info->lock,flags);
1825
1826 netif_wake_queue(dev);
1827 }
1828
1829 /**
1830 * called by device driver when transmit completes
1831 * reenable network layer transmit if stopped
1832 *
1833 * info pointer to device instance information
1834 */
1835 static void hdlcdev_tx_done(SLMP_INFO *info)
1836 {
1837 if (netif_queue_stopped(info->netdev))
1838 netif_wake_queue(info->netdev);
1839 }
1840
1841 /**
1842 * called by device driver when frame received
1843 * pass frame to network layer
1844 *
1845 * info pointer to device instance information
1846 * buf pointer to buffer contianing frame data
1847 * size count of data bytes in buf
1848 */
1849 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1850 {
1851 struct sk_buff *skb = dev_alloc_skb(size);
1852 struct net_device *dev = info->netdev;
1853
1854 if (debug_level >= DEBUG_LEVEL_INFO)
1855 printk("hdlcdev_rx(%s)\n",dev->name);
1856
1857 if (skb == NULL) {
1858 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1859 dev->name);
1860 dev->stats.rx_dropped++;
1861 return;
1862 }
1863
1864 skb_put_data(skb, buf, size);
1865
1866 skb->protocol = hdlc_type_trans(skb, dev);
1867
1868 dev->stats.rx_packets++;
1869 dev->stats.rx_bytes += size;
1870
1871 netif_rx(skb);
1872 }
1873
1874 static const struct net_device_ops hdlcdev_ops = {
1875 .ndo_open = hdlcdev_open,
1876 .ndo_stop = hdlcdev_close,
1877 .ndo_start_xmit = hdlc_start_xmit,
1878 .ndo_do_ioctl = hdlcdev_ioctl,
1879 .ndo_tx_timeout = hdlcdev_tx_timeout,
1880 };
1881
1882 /**
1883 * called by device driver when adding device instance
1884 * do generic HDLC initialization
1885 *
1886 * info pointer to device instance information
1887 *
1888 * returns 0 if success, otherwise error code
1889 */
1890 static int hdlcdev_init(SLMP_INFO *info)
1891 {
1892 int rc;
1893 struct net_device *dev;
1894 hdlc_device *hdlc;
1895
1896 /* allocate and initialize network and HDLC layer objects */
1897
1898 dev = alloc_hdlcdev(info);
1899 if (!dev) {
1900 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1901 return -ENOMEM;
1902 }
1903
1904 /* for network layer reporting purposes only */
1905 dev->mem_start = info->phys_sca_base;
1906 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1907 dev->irq = info->irq_level;
1908
1909 /* network layer callbacks and settings */
1910 dev->netdev_ops = &hdlcdev_ops;
1911 dev->watchdog_timeo = 10 * HZ;
1912 dev->tx_queue_len = 50;
1913
1914 /* generic HDLC layer callbacks and settings */
1915 hdlc = dev_to_hdlc(dev);
1916 hdlc->attach = hdlcdev_attach;
1917 hdlc->xmit = hdlcdev_xmit;
1918
1919 /* register objects with HDLC layer */
1920 rc = register_hdlc_device(dev);
1921 if (rc) {
1922 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1923 free_netdev(dev);
1924 return rc;
1925 }
1926
1927 info->netdev = dev;
1928 return 0;
1929 }
1930
1931 /**
1932 * called by device driver when removing device instance
1933 * do generic HDLC cleanup
1934 *
1935 * info pointer to device instance information
1936 */
1937 static void hdlcdev_exit(SLMP_INFO *info)
1938 {
1939 unregister_hdlc_device(info->netdev);
1940 free_netdev(info->netdev);
1941 info->netdev = NULL;
1942 }
1943
1944 #endif /* CONFIG_HDLC */
1945
1946
1947 /* Return next bottom half action to perform.
1948 * Return Value: BH action code or 0 if nothing to do.
1949 */
1950 static int bh_action(SLMP_INFO *info)
1951 {
1952 unsigned long flags;
1953 int rc = 0;
1954
1955 spin_lock_irqsave(&info->lock,flags);
1956
1957 if (info->pending_bh & BH_RECEIVE) {
1958 info->pending_bh &= ~BH_RECEIVE;
1959 rc = BH_RECEIVE;
1960 } else if (info->pending_bh & BH_TRANSMIT) {
1961 info->pending_bh &= ~BH_TRANSMIT;
1962 rc = BH_TRANSMIT;
1963 } else if (info->pending_bh & BH_STATUS) {
1964 info->pending_bh &= ~BH_STATUS;
1965 rc = BH_STATUS;
1966 }
1967
1968 if (!rc) {
1969 /* Mark BH routine as complete */
1970 info->bh_running = false;
1971 info->bh_requested = false;
1972 }
1973
1974 spin_unlock_irqrestore(&info->lock,flags);
1975
1976 return rc;
1977 }
1978
1979 /* Perform bottom half processing of work items queued by ISR.
1980 */
1981 static void bh_handler(struct work_struct *work)
1982 {
1983 SLMP_INFO *info = container_of(work, SLMP_INFO, task);
1984 int action;
1985
1986 if ( debug_level >= DEBUG_LEVEL_BH )
1987 printk( "%s(%d):%s bh_handler() entry\n",
1988 __FILE__,__LINE__,info->device_name);
1989
1990 info->bh_running = true;
1991
1992 while((action = bh_action(info)) != 0) {
1993
1994 /* Process work item */
1995 if ( debug_level >= DEBUG_LEVEL_BH )
1996 printk( "%s(%d):%s bh_handler() work item action=%d\n",
1997 __FILE__,__LINE__,info->device_name, action);
1998
1999 switch (action) {
2000
2001 case BH_RECEIVE:
2002 bh_receive(info);
2003 break;
2004 case BH_TRANSMIT:
2005 bh_transmit(info);
2006 break;
2007 case BH_STATUS:
2008 bh_status(info);
2009 break;
2010 default:
2011 /* unknown work item ID */
2012 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2013 __FILE__,__LINE__,info->device_name,action);
2014 break;
2015 }
2016 }
2017
2018 if ( debug_level >= DEBUG_LEVEL_BH )
2019 printk( "%s(%d):%s bh_handler() exit\n",
2020 __FILE__,__LINE__,info->device_name);
2021 }
2022
2023 static void bh_receive(SLMP_INFO *info)
2024 {
2025 if ( debug_level >= DEBUG_LEVEL_BH )
2026 printk( "%s(%d):%s bh_receive()\n",
2027 __FILE__,__LINE__,info->device_name);
2028
2029 while( rx_get_frame(info) );
2030 }
2031
2032 static void bh_transmit(SLMP_INFO *info)
2033 {
2034 struct tty_struct *tty = info->port.tty;
2035
2036 if ( debug_level >= DEBUG_LEVEL_BH )
2037 printk( "%s(%d):%s bh_transmit() entry\n",
2038 __FILE__,__LINE__,info->device_name);
2039
2040 if (tty)
2041 tty_wakeup(tty);
2042 }
2043
2044 static void bh_status(SLMP_INFO *info)
2045 {
2046 if ( debug_level >= DEBUG_LEVEL_BH )
2047 printk( "%s(%d):%s bh_status() entry\n",
2048 __FILE__,__LINE__,info->device_name);
2049
2050 info->ri_chkcount = 0;
2051 info->dsr_chkcount = 0;
2052 info->dcd_chkcount = 0;
2053 info->cts_chkcount = 0;
2054 }
2055
2056 static void isr_timer(SLMP_INFO * info)
2057 {
2058 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2059
2060 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2061 write_reg(info, IER2, 0);
2062
2063 /* TMCS, Timer Control/Status Register
2064 *
2065 * 07 CMF, Compare match flag (read only) 1=match
2066 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2067 * 05 Reserved, must be 0
2068 * 04 TME, Timer Enable
2069 * 03..00 Reserved, must be 0
2070 *
2071 * 0000 0000
2072 */
2073 write_reg(info, (unsigned char)(timer + TMCS), 0);
2074
2075 info->irq_occurred = true;
2076
2077 if ( debug_level >= DEBUG_LEVEL_ISR )
2078 printk("%s(%d):%s isr_timer()\n",
2079 __FILE__,__LINE__,info->device_name);
2080 }
2081
2082 static void isr_rxint(SLMP_INFO * info)
2083 {
2084 struct tty_struct *tty = info->port.tty;
2085 struct mgsl_icount *icount = &info->icount;
2086 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2087 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2088
2089 /* clear status bits */
2090 if (status)
2091 write_reg(info, SR1, status);
2092
2093 if (status2)
2094 write_reg(info, SR2, status2);
2095
2096 if ( debug_level >= DEBUG_LEVEL_ISR )
2097 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2098 __FILE__,__LINE__,info->device_name,status,status2);
2099
2100 if (info->params.mode == MGSL_MODE_ASYNC) {
2101 if (status & BRKD) {
2102 icount->brk++;
2103
2104 /* process break detection if tty control
2105 * is not set to ignore it
2106 */
2107 if (!(status & info->ignore_status_mask1)) {
2108 if (info->read_status_mask1 & BRKD) {
2109 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2110 if (tty && (info->port.flags & ASYNC_SAK))
2111 do_SAK(tty);
2112 }
2113 }
2114 }
2115 }
2116 else {
2117 if (status & (FLGD|IDLD)) {
2118 if (status & FLGD)
2119 info->icount.exithunt++;
2120 else if (status & IDLD)
2121 info->icount.rxidle++;
2122 wake_up_interruptible(&info->event_wait_q);
2123 }
2124 }
2125
2126 if (status & CDCD) {
2127 /* simulate a common modem status change interrupt
2128 * for our handler
2129 */
2130 get_signals( info );
2131 isr_io_pin(info,
2132 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2133 }
2134 }
2135
2136 /*
2137 * handle async rx data interrupts
2138 */
2139 static void isr_rxrdy(SLMP_INFO * info)
2140 {
2141 u16 status;
2142 unsigned char DataByte;
2143 struct mgsl_icount *icount = &info->icount;
2144
2145 if ( debug_level >= DEBUG_LEVEL_ISR )
2146 printk("%s(%d):%s isr_rxrdy\n",
2147 __FILE__,__LINE__,info->device_name);
2148
2149 while((status = read_reg(info,CST0)) & BIT0)
2150 {
2151 int flag = 0;
2152 bool over = false;
2153 DataByte = read_reg(info,TRB);
2154
2155 icount->rx++;
2156
2157 if ( status & (PE + FRME + OVRN) ) {
2158 printk("%s(%d):%s rxerr=%04X\n",
2159 __FILE__,__LINE__,info->device_name,status);
2160
2161 /* update error statistics */
2162 if (status & PE)
2163 icount->parity++;
2164 else if (status & FRME)
2165 icount->frame++;
2166 else if (status & OVRN)
2167 icount->overrun++;
2168
2169 /* discard char if tty control flags say so */
2170 if (status & info->ignore_status_mask2)
2171 continue;
2172
2173 status &= info->read_status_mask2;
2174
2175 if (status & PE)
2176 flag = TTY_PARITY;
2177 else if (status & FRME)
2178 flag = TTY_FRAME;
2179 if (status & OVRN) {
2180 /* Overrun is special, since it's
2181 * reported immediately, and doesn't
2182 * affect the current character
2183 */
2184 over = true;
2185 }
2186 } /* end of if (error) */
2187
2188 tty_insert_flip_char(&info->port, DataByte, flag);
2189 if (over)
2190 tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
2191 }
2192
2193 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2194 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2195 __FILE__,__LINE__,info->device_name,
2196 icount->rx,icount->brk,icount->parity,
2197 icount->frame,icount->overrun);
2198 }
2199
2200 tty_flip_buffer_push(&info->port);
2201 }
2202
2203 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2204 {
2205 if ( debug_level >= DEBUG_LEVEL_ISR )
2206 printk("%s(%d):%s isr_txeom status=%02x\n",
2207 __FILE__,__LINE__,info->device_name,status);
2208
2209 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2210 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2211 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2212
2213 if (status & UDRN) {
2214 write_reg(info, CMD, TXRESET);
2215 write_reg(info, CMD, TXENABLE);
2216 } else
2217 write_reg(info, CMD, TXBUFCLR);
2218
2219 /* disable and clear tx interrupts */
2220 info->ie0_value &= ~TXRDYE;
2221 info->ie1_value &= ~(IDLE + UDRN);
2222 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2223 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2224
2225 if ( info->tx_active ) {
2226 if (info->params.mode != MGSL_MODE_ASYNC) {
2227 if (status & UDRN)
2228 info->icount.txunder++;
2229 else if (status & IDLE)
2230 info->icount.txok++;
2231 }
2232
2233 info->tx_active = false;
2234 info->tx_count = info->tx_put = info->tx_get = 0;
2235
2236 del_timer(&info->tx_timer);
2237
2238 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2239 info->serial_signals &= ~SerialSignal_RTS;
2240 info->drop_rts_on_tx_done = false;
2241 set_signals(info);
2242 }
2243
2244 #if SYNCLINK_GENERIC_HDLC
2245 if (info->netcount)
2246 hdlcdev_tx_done(info);
2247 else
2248 #endif
2249 {
2250 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2251 tx_stop(info);
2252 return;
2253 }
2254 info->pending_bh |= BH_TRANSMIT;
2255 }
2256 }
2257 }
2258
2259
2260 /*
2261 * handle tx status interrupts
2262 */
2263 static void isr_txint(SLMP_INFO * info)
2264 {
2265 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2266
2267 /* clear status bits */
2268 write_reg(info, SR1, status);
2269
2270 if ( debug_level >= DEBUG_LEVEL_ISR )
2271 printk("%s(%d):%s isr_txint status=%02x\n",
2272 __FILE__,__LINE__,info->device_name,status);
2273
2274 if (status & (UDRN + IDLE))
2275 isr_txeom(info, status);
2276
2277 if (status & CCTS) {
2278 /* simulate a common modem status change interrupt
2279 * for our handler
2280 */
2281 get_signals( info );
2282 isr_io_pin(info,
2283 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2284
2285 }
2286 }
2287
2288 /*
2289 * handle async tx data interrupts
2290 */
2291 static void isr_txrdy(SLMP_INFO * info)
2292 {
2293 if ( debug_level >= DEBUG_LEVEL_ISR )
2294 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2295 __FILE__,__LINE__,info->device_name,info->tx_count);
2296
2297 if (info->params.mode != MGSL_MODE_ASYNC) {
2298 /* disable TXRDY IRQ, enable IDLE IRQ */
2299 info->ie0_value &= ~TXRDYE;
2300 info->ie1_value |= IDLE;
2301 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2302 return;
2303 }
2304
2305 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2306 tx_stop(info);
2307 return;
2308 }
2309
2310 if ( info->tx_count )
2311 tx_load_fifo( info );
2312 else {
2313 info->tx_active = false;
2314 info->ie0_value &= ~TXRDYE;
2315 write_reg(info, IE0, info->ie0_value);
2316 }
2317
2318 if (info->tx_count < WAKEUP_CHARS)
2319 info->pending_bh |= BH_TRANSMIT;
2320 }
2321
2322 static void isr_rxdmaok(SLMP_INFO * info)
2323 {
2324 /* BIT7 = EOT (end of transfer)
2325 * BIT6 = EOM (end of message/frame)
2326 */
2327 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2328
2329 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2330 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2331
2332 if ( debug_level >= DEBUG_LEVEL_ISR )
2333 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2334 __FILE__,__LINE__,info->device_name,status);
2335
2336 info->pending_bh |= BH_RECEIVE;
2337 }
2338
2339 static void isr_rxdmaerror(SLMP_INFO * info)
2340 {
2341 /* BIT5 = BOF (buffer overflow)
2342 * BIT4 = COF (counter overflow)
2343 */
2344 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2345
2346 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2347 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2348
2349 if ( debug_level >= DEBUG_LEVEL_ISR )
2350 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2351 __FILE__,__LINE__,info->device_name,status);
2352
2353 info->rx_overflow = true;
2354 info->pending_bh |= BH_RECEIVE;
2355 }
2356
2357 static void isr_txdmaok(SLMP_INFO * info)
2358 {
2359 unsigned char status_reg1 = read_reg(info, SR1);
2360
2361 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2362 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2363 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2364
2365 if ( debug_level >= DEBUG_LEVEL_ISR )
2366 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2367 __FILE__,__LINE__,info->device_name,status_reg1);
2368
2369 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2370 write_reg16(info, TRC0, 0);
2371 info->ie0_value |= TXRDYE;
2372 write_reg(info, IE0, info->ie0_value);
2373 }
2374
2375 static void isr_txdmaerror(SLMP_INFO * info)
2376 {
2377 /* BIT5 = BOF (buffer overflow)
2378 * BIT4 = COF (counter overflow)
2379 */
2380 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2381
2382 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2383 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2384
2385 if ( debug_level >= DEBUG_LEVEL_ISR )
2386 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2387 __FILE__,__LINE__,info->device_name,status);
2388 }
2389
2390 /* handle input serial signal changes
2391 */
2392 static void isr_io_pin( SLMP_INFO *info, u16 status )
2393 {
2394 struct mgsl_icount *icount;
2395
2396 if ( debug_level >= DEBUG_LEVEL_ISR )
2397 printk("%s(%d):isr_io_pin status=%04X\n",
2398 __FILE__,__LINE__,status);
2399
2400 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2401 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2402 icount = &info->icount;
2403 /* update input line counters */
2404 if (status & MISCSTATUS_RI_LATCHED) {
2405 icount->rng++;
2406 if ( status & SerialSignal_RI )
2407 info->input_signal_events.ri_up++;
2408 else
2409 info->input_signal_events.ri_down++;
2410 }
2411 if (status & MISCSTATUS_DSR_LATCHED) {
2412 icount->dsr++;
2413 if ( status & SerialSignal_DSR )
2414 info->input_signal_events.dsr_up++;
2415 else
2416 info->input_signal_events.dsr_down++;
2417 }
2418 if (status & MISCSTATUS_DCD_LATCHED) {
2419 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2420 info->ie1_value &= ~CDCD;
2421 write_reg(info, IE1, info->ie1_value);
2422 }
2423 icount->dcd++;
2424 if (status & SerialSignal_DCD) {
2425 info->input_signal_events.dcd_up++;
2426 } else
2427 info->input_signal_events.dcd_down++;
2428 #if SYNCLINK_GENERIC_HDLC
2429 if (info->netcount) {
2430 if (status & SerialSignal_DCD)
2431 netif_carrier_on(info->netdev);
2432 else
2433 netif_carrier_off(info->netdev);
2434 }
2435 #endif
2436 }
2437 if (status & MISCSTATUS_CTS_LATCHED)
2438 {
2439 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2440 info->ie1_value &= ~CCTS;
2441 write_reg(info, IE1, info->ie1_value);
2442 }
2443 icount->cts++;
2444 if ( status & SerialSignal_CTS )
2445 info->input_signal_events.cts_up++;
2446 else
2447 info->input_signal_events.cts_down++;
2448 }
2449 wake_up_interruptible(&info->status_event_wait_q);
2450 wake_up_interruptible(&info->event_wait_q);
2451
2452 if (tty_port_check_carrier(&info->port) &&
2453 (status & MISCSTATUS_DCD_LATCHED) ) {
2454 if ( debug_level >= DEBUG_LEVEL_ISR )
2455 printk("%s CD now %s...", info->device_name,
2456 (status & SerialSignal_DCD) ? "on" : "off");
2457 if (status & SerialSignal_DCD)
2458 wake_up_interruptible(&info->port.open_wait);
2459 else {
2460 if ( debug_level >= DEBUG_LEVEL_ISR )
2461 printk("doing serial hangup...");
2462 if (info->port.tty)
2463 tty_hangup(info->port.tty);
2464 }
2465 }
2466
2467 if (tty_port_cts_enabled(&info->port) &&
2468 (status & MISCSTATUS_CTS_LATCHED) ) {
2469 if ( info->port.tty ) {
2470 if (info->port.tty->hw_stopped) {
2471 if (status & SerialSignal_CTS) {
2472 if ( debug_level >= DEBUG_LEVEL_ISR )
2473 printk("CTS tx start...");
2474 info->port.tty->hw_stopped = 0;
2475 tx_start(info);
2476 info->pending_bh |= BH_TRANSMIT;
2477 return;
2478 }
2479 } else {
2480 if (!(status & SerialSignal_CTS)) {
2481 if ( debug_level >= DEBUG_LEVEL_ISR )
2482 printk("CTS tx stop...");
2483 info->port.tty->hw_stopped = 1;
2484 tx_stop(info);
2485 }
2486 }
2487 }
2488 }
2489 }
2490
2491 info->pending_bh |= BH_STATUS;
2492 }
2493
2494 /* Interrupt service routine entry point.
2495 *
2496 * Arguments:
2497 * irq interrupt number that caused interrupt
2498 * dev_id device ID supplied during interrupt registration
2499 * regs interrupted processor context
2500 */
2501 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2502 {
2503 SLMP_INFO *info = dev_id;
2504 unsigned char status, status0, status1=0;
2505 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2506 unsigned char timerstatus0, timerstatus1=0;
2507 unsigned char shift;
2508 unsigned int i;
2509 unsigned short tmp;
2510
2511 if ( debug_level >= DEBUG_LEVEL_ISR )
2512 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2513 __FILE__, __LINE__, info->irq_level);
2514
2515 spin_lock(&info->lock);
2516
2517 for(;;) {
2518
2519 /* get status for SCA0 (ports 0-1) */
2520 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2521 status0 = (unsigned char)tmp;
2522 dmastatus0 = (unsigned char)(tmp>>8);
2523 timerstatus0 = read_reg(info, ISR2);
2524
2525 if ( debug_level >= DEBUG_LEVEL_ISR )
2526 printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2527 __FILE__, __LINE__, info->device_name,
2528 status0, dmastatus0, timerstatus0);
2529
2530 if (info->port_count == 4) {
2531 /* get status for SCA1 (ports 2-3) */
2532 tmp = read_reg16(info->port_array[2], ISR0);
2533 status1 = (unsigned char)tmp;
2534 dmastatus1 = (unsigned char)(tmp>>8);
2535 timerstatus1 = read_reg(info->port_array[2], ISR2);
2536
2537 if ( debug_level >= DEBUG_LEVEL_ISR )
2538 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2539 __FILE__,__LINE__,info->device_name,
2540 status1,dmastatus1,timerstatus1);
2541 }
2542
2543 if (!status0 && !dmastatus0 && !timerstatus0 &&
2544 !status1 && !dmastatus1 && !timerstatus1)
2545 break;
2546
2547 for(i=0; i < info->port_count ; i++) {
2548 if (info->port_array[i] == NULL)
2549 continue;
2550 if (i < 2) {
2551 status = status0;
2552 dmastatus = dmastatus0;
2553 } else {
2554 status = status1;
2555 dmastatus = dmastatus1;
2556 }
2557
2558 shift = i & 1 ? 4 :0;
2559
2560 if (status & BIT0 << shift)
2561 isr_rxrdy(info->port_array[i]);
2562 if (status & BIT1 << shift)
2563 isr_txrdy(info->port_array[i]);
2564 if (status & BIT2 << shift)
2565 isr_rxint(info->port_array[i]);
2566 if (status & BIT3 << shift)
2567 isr_txint(info->port_array[i]);
2568
2569 if (dmastatus & BIT0 << shift)
2570 isr_rxdmaerror(info->port_array[i]);
2571 if (dmastatus & BIT1 << shift)
2572 isr_rxdmaok(info->port_array[i]);
2573 if (dmastatus & BIT2 << shift)
2574 isr_txdmaerror(info->port_array[i]);
2575 if (dmastatus & BIT3 << shift)
2576 isr_txdmaok(info->port_array[i]);
2577 }
2578
2579 if (timerstatus0 & (BIT5 | BIT4))
2580 isr_timer(info->port_array[0]);
2581 if (timerstatus0 & (BIT7 | BIT6))
2582 isr_timer(info->port_array[1]);
2583 if (timerstatus1 & (BIT5 | BIT4))
2584 isr_timer(info->port_array[2]);
2585 if (timerstatus1 & (BIT7 | BIT6))
2586 isr_timer(info->port_array[3]);
2587 }
2588
2589 for(i=0; i < info->port_count ; i++) {
2590 SLMP_INFO * port = info->port_array[i];
2591
2592 /* Request bottom half processing if there's something
2593 * for it to do and the bh is not already running.
2594 *
2595 * Note: startup adapter diags require interrupts.
2596 * do not request bottom half processing if the
2597 * device is not open in a normal mode.
2598 */
2599 if ( port && (port->port.count || port->netcount) &&
2600 port->pending_bh && !port->bh_running &&
2601 !port->bh_requested ) {
2602 if ( debug_level >= DEBUG_LEVEL_ISR )
2603 printk("%s(%d):%s queueing bh task.\n",
2604 __FILE__,__LINE__,port->device_name);
2605 schedule_work(&port->task);
2606 port->bh_requested = true;
2607 }
2608 }
2609
2610 spin_unlock(&info->lock);
2611
2612 if ( debug_level >= DEBUG_LEVEL_ISR )
2613 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2614 __FILE__, __LINE__, info->irq_level);
2615 return IRQ_HANDLED;
2616 }
2617
2618 /* Initialize and start device.
2619 */
2620 static int startup(SLMP_INFO * info)
2621 {
2622 if ( debug_level >= DEBUG_LEVEL_INFO )
2623 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2624
2625 if (tty_port_initialized(&info->port))
2626 return 0;
2627
2628 if (!info->tx_buf) {
2629 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2630 if (!info->tx_buf) {
2631 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2632 __FILE__,__LINE__,info->device_name);
2633 return -ENOMEM;
2634 }
2635 }
2636
2637 info->pending_bh = 0;
2638
2639 memset(&info->icount, 0, sizeof(info->icount));
2640
2641 /* program hardware for current parameters */
2642 reset_port(info);
2643
2644 change_params(info);
2645
2646 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2647
2648 if (info->port.tty)
2649 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2650
2651 tty_port_set_initialized(&info->port, 1);
2652
2653 return 0;
2654 }
2655
2656 /* Called by close() and hangup() to shutdown hardware
2657 */
2658 static void shutdown(SLMP_INFO * info)
2659 {
2660 unsigned long flags;
2661
2662 if (!tty_port_initialized(&info->port))
2663 return;
2664
2665 if (debug_level >= DEBUG_LEVEL_INFO)
2666 printk("%s(%d):%s synclinkmp_shutdown()\n",
2667 __FILE__,__LINE__, info->device_name );
2668
2669 /* clear status wait queue because status changes */
2670 /* can't happen after shutting down the hardware */
2671 wake_up_interruptible(&info->status_event_wait_q);
2672 wake_up_interruptible(&info->event_wait_q);
2673
2674 del_timer(&info->tx_timer);
2675 del_timer(&info->status_timer);
2676
2677 kfree(info->tx_buf);
2678 info->tx_buf = NULL;
2679
2680 spin_lock_irqsave(&info->lock,flags);
2681
2682 reset_port(info);
2683
2684 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2685 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2686 set_signals(info);
2687 }
2688
2689 spin_unlock_irqrestore(&info->lock,flags);
2690
2691 if (info->port.tty)
2692 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2693
2694 tty_port_set_initialized(&info->port, 0);
2695 }
2696
2697 static void program_hw(SLMP_INFO *info)
2698 {
2699 unsigned long flags;
2700
2701 spin_lock_irqsave(&info->lock,flags);
2702
2703 rx_stop(info);
2704 tx_stop(info);
2705
2706 info->tx_count = info->tx_put = info->tx_get = 0;
2707
2708 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2709 hdlc_mode(info);
2710 else
2711 async_mode(info);
2712
2713 set_signals(info);
2714
2715 info->dcd_chkcount = 0;
2716 info->cts_chkcount = 0;
2717 info->ri_chkcount = 0;
2718 info->dsr_chkcount = 0;
2719
2720 info->ie1_value |= (CDCD|CCTS);
2721 write_reg(info, IE1, info->ie1_value);
2722
2723 get_signals(info);
2724
2725 if (info->netcount || (info->port.tty && info->port.tty->termios.c_cflag & CREAD) )
2726 rx_start(info);
2727
2728 spin_unlock_irqrestore(&info->lock,flags);
2729 }
2730
2731 /* Reconfigure adapter based on new parameters
2732 */
2733 static void change_params(SLMP_INFO *info)
2734 {
2735 unsigned cflag;
2736 int bits_per_char;
2737
2738 if (!info->port.tty)
2739 return;
2740
2741 if (debug_level >= DEBUG_LEVEL_INFO)
2742 printk("%s(%d):%s change_params()\n",
2743 __FILE__,__LINE__, info->device_name );
2744
2745 cflag = info->port.tty->termios.c_cflag;
2746
2747 /* if B0 rate (hangup) specified then negate RTS and DTR */
2748 /* otherwise assert RTS and DTR */
2749 if (cflag & CBAUD)
2750 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
2751 else
2752 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2753
2754 /* byte size and parity */
2755
2756 switch (cflag & CSIZE) {
2757 case CS5: info->params.data_bits = 5; break;
2758 case CS6: info->params.data_bits = 6; break;
2759 case CS7: info->params.data_bits = 7; break;
2760 case CS8: info->params.data_bits = 8; break;
2761 /* Never happens, but GCC is too dumb to figure it out */
2762 default: info->params.data_bits = 7; break;
2763 }
2764
2765 if (cflag & CSTOPB)
2766 info->params.stop_bits = 2;
2767 else
2768 info->params.stop_bits = 1;
2769
2770 info->params.parity = ASYNC_PARITY_NONE;
2771 if (cflag & PARENB) {
2772 if (cflag & PARODD)
2773 info->params.parity = ASYNC_PARITY_ODD;
2774 else
2775 info->params.parity = ASYNC_PARITY_EVEN;
2776 #ifdef CMSPAR
2777 if (cflag & CMSPAR)
2778 info->params.parity = ASYNC_PARITY_SPACE;
2779 #endif
2780 }
2781
2782 /* calculate number of jiffies to transmit a full
2783 * FIFO (32 bytes) at specified data rate
2784 */
2785 bits_per_char = info->params.data_bits +
2786 info->params.stop_bits + 1;
2787
2788 /* if port data rate is set to 460800 or less then
2789 * allow tty settings to override, otherwise keep the
2790 * current data rate.
2791 */
2792 if (info->params.data_rate <= 460800) {
2793 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2794 }
2795
2796 if ( info->params.data_rate ) {
2797 info->timeout = (32*HZ*bits_per_char) /
2798 info->params.data_rate;
2799 }
2800 info->timeout += HZ/50; /* Add .02 seconds of slop */
2801
2802 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2803 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2804
2805 /* process tty input control flags */
2806
2807 info->read_status_mask2 = OVRN;
2808 if (I_INPCK(info->port.tty))
2809 info->read_status_mask2 |= PE | FRME;
2810 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2811 info->read_status_mask1 |= BRKD;
2812 if (I_IGNPAR(info->port.tty))
2813 info->ignore_status_mask2 |= PE | FRME;
2814 if (I_IGNBRK(info->port.tty)) {
2815 info->ignore_status_mask1 |= BRKD;
2816 /* If ignoring parity and break indicators, ignore
2817 * overruns too. (For real raw support).
2818 */
2819 if (I_IGNPAR(info->port.tty))
2820 info->ignore_status_mask2 |= OVRN;
2821 }
2822
2823 program_hw(info);
2824 }
2825
2826 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2827 {
2828 int err;
2829
2830 if (debug_level >= DEBUG_LEVEL_INFO)
2831 printk("%s(%d):%s get_params()\n",
2832 __FILE__,__LINE__, info->device_name);
2833
2834 if (!user_icount) {
2835 memset(&info->icount, 0, sizeof(info->icount));
2836 } else {
2837 mutex_lock(&info->port.mutex);
2838 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2839 mutex_unlock(&info->port.mutex);
2840 if (err)
2841 return -EFAULT;
2842 }
2843
2844 return 0;
2845 }
2846
2847 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2848 {
2849 int err;
2850 if (debug_level >= DEBUG_LEVEL_INFO)
2851 printk("%s(%d):%s get_params()\n",
2852 __FILE__,__LINE__, info->device_name);
2853
2854 mutex_lock(&info->port.mutex);
2855 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2856 mutex_unlock(&info->port.mutex);
2857 if (err) {
2858 if ( debug_level >= DEBUG_LEVEL_INFO )
2859 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2860 __FILE__,__LINE__,info->device_name);
2861 return -EFAULT;
2862 }
2863
2864 return 0;
2865 }
2866
2867 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2868 {
2869 unsigned long flags;
2870 MGSL_PARAMS tmp_params;
2871 int err;
2872
2873 if (debug_level >= DEBUG_LEVEL_INFO)
2874 printk("%s(%d):%s set_params\n",
2875 __FILE__,__LINE__,info->device_name );
2876 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2877 if (err) {
2878 if ( debug_level >= DEBUG_LEVEL_INFO )
2879 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2880 __FILE__,__LINE__,info->device_name);
2881 return -EFAULT;
2882 }
2883
2884 mutex_lock(&info->port.mutex);
2885 spin_lock_irqsave(&info->lock,flags);
2886 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2887 spin_unlock_irqrestore(&info->lock,flags);
2888
2889 change_params(info);
2890 mutex_unlock(&info->port.mutex);
2891
2892 return 0;
2893 }
2894
2895 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2896 {
2897 int err;
2898
2899 if (debug_level >= DEBUG_LEVEL_INFO)
2900 printk("%s(%d):%s get_txidle()=%d\n",
2901 __FILE__,__LINE__, info->device_name, info->idle_mode);
2902
2903 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2904 if (err) {
2905 if ( debug_level >= DEBUG_LEVEL_INFO )
2906 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2907 __FILE__,__LINE__,info->device_name);
2908 return -EFAULT;
2909 }
2910
2911 return 0;
2912 }
2913
2914 static int set_txidle(SLMP_INFO * info, int idle_mode)
2915 {
2916 unsigned long flags;
2917
2918 if (debug_level >= DEBUG_LEVEL_INFO)
2919 printk("%s(%d):%s set_txidle(%d)\n",
2920 __FILE__,__LINE__,info->device_name, idle_mode );
2921
2922 spin_lock_irqsave(&info->lock,flags);
2923 info->idle_mode = idle_mode;
2924 tx_set_idle( info );
2925 spin_unlock_irqrestore(&info->lock,flags);
2926 return 0;
2927 }
2928
2929 static int tx_enable(SLMP_INFO * info, int enable)
2930 {
2931 unsigned long flags;
2932
2933 if (debug_level >= DEBUG_LEVEL_INFO)
2934 printk("%s(%d):%s tx_enable(%d)\n",
2935 __FILE__,__LINE__,info->device_name, enable);
2936
2937 spin_lock_irqsave(&info->lock,flags);
2938 if ( enable ) {
2939 if ( !info->tx_enabled ) {
2940 tx_start(info);
2941 }
2942 } else {
2943 if ( info->tx_enabled )
2944 tx_stop(info);
2945 }
2946 spin_unlock_irqrestore(&info->lock,flags);
2947 return 0;
2948 }
2949
2950 /* abort send HDLC frame
2951 */
2952 static int tx_abort(SLMP_INFO * info)
2953 {
2954 unsigned long flags;
2955
2956 if (debug_level >= DEBUG_LEVEL_INFO)
2957 printk("%s(%d):%s tx_abort()\n",
2958 __FILE__,__LINE__,info->device_name);
2959
2960 spin_lock_irqsave(&info->lock,flags);
2961 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
2962 info->ie1_value &= ~UDRN;
2963 info->ie1_value |= IDLE;
2964 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
2965 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
2966
2967 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
2968 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2969
2970 write_reg(info, CMD, TXABORT);
2971 }
2972 spin_unlock_irqrestore(&info->lock,flags);
2973 return 0;
2974 }
2975
2976 static int rx_enable(SLMP_INFO * info, int enable)
2977 {
2978 unsigned long flags;
2979
2980 if (debug_level >= DEBUG_LEVEL_INFO)
2981 printk("%s(%d):%s rx_enable(%d)\n",
2982 __FILE__,__LINE__,info->device_name,enable);
2983
2984 spin_lock_irqsave(&info->lock,flags);
2985 if ( enable ) {
2986 if ( !info->rx_enabled )
2987 rx_start(info);
2988 } else {
2989 if ( info->rx_enabled )
2990 rx_stop(info);
2991 }
2992 spin_unlock_irqrestore(&info->lock,flags);
2993 return 0;
2994 }
2995
2996 /* wait for specified event to occur
2997 */
2998 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
2999 {
3000 unsigned long flags;
3001 int s;
3002 int rc=0;
3003 struct mgsl_icount cprev, cnow;
3004 int events;
3005 int mask;
3006 struct _input_signal_events oldsigs, newsigs;
3007 DECLARE_WAITQUEUE(wait, current);
3008
3009 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3010 if (rc) {
3011 return -EFAULT;
3012 }
3013
3014 if (debug_level >= DEBUG_LEVEL_INFO)
3015 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3016 __FILE__,__LINE__,info->device_name,mask);
3017
3018 spin_lock_irqsave(&info->lock,flags);
3019
3020 /* return immediately if state matches requested events */
3021 get_signals(info);
3022 s = info->serial_signals;
3023
3024 events = mask &
3025 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3026 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3027 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3028 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3029 if (events) {
3030 spin_unlock_irqrestore(&info->lock,flags);
3031 goto exit;
3032 }
3033
3034 /* save current irq counts */
3035 cprev = info->icount;
3036 oldsigs = info->input_signal_events;
3037
3038 /* enable hunt and idle irqs if needed */
3039 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3040 unsigned char oldval = info->ie1_value;
3041 unsigned char newval = oldval +
3042 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3043 (mask & MgslEvent_IdleReceived ? IDLD:0);
3044 if ( oldval != newval ) {
3045 info->ie1_value = newval;
3046 write_reg(info, IE1, info->ie1_value);
3047 }
3048 }
3049
3050 set_current_state(TASK_INTERRUPTIBLE);
3051 add_wait_queue(&info->event_wait_q, &wait);
3052
3053 spin_unlock_irqrestore(&info->lock,flags);
3054
3055 for(;;) {
3056 schedule();
3057 if (signal_pending(current)) {
3058 rc = -ERESTARTSYS;
3059 break;
3060 }
3061
3062 /* get current irq counts */
3063 spin_lock_irqsave(&info->lock,flags);
3064 cnow = info->icount;
3065 newsigs = info->input_signal_events;
3066 set_current_state(TASK_INTERRUPTIBLE);
3067 spin_unlock_irqrestore(&info->lock,flags);
3068
3069 /* if no change, wait aborted for some reason */
3070 if (newsigs.dsr_up == oldsigs.dsr_up &&
3071 newsigs.dsr_down == oldsigs.dsr_down &&
3072 newsigs.dcd_up == oldsigs.dcd_up &&
3073 newsigs.dcd_down == oldsigs.dcd_down &&
3074 newsigs.cts_up == oldsigs.cts_up &&
3075 newsigs.cts_down == oldsigs.cts_down &&
3076 newsigs.ri_up == oldsigs.ri_up &&
3077 newsigs.ri_down == oldsigs.ri_down &&
3078 cnow.exithunt == cprev.exithunt &&
3079 cnow.rxidle == cprev.rxidle) {
3080 rc = -EIO;
3081 break;
3082 }
3083
3084 events = mask &
3085 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3086 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3087 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3088 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3089 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3090 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3091 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3092 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3093 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3094 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3095 if (events)
3096 break;
3097
3098 cprev = cnow;
3099 oldsigs = newsigs;
3100 }
3101
3102 remove_wait_queue(&info->event_wait_q, &wait);
3103 set_current_state(TASK_RUNNING);
3104
3105
3106 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3107 spin_lock_irqsave(&info->lock,flags);
3108 if (!waitqueue_active(&info->event_wait_q)) {
3109 /* disable enable exit hunt mode/idle rcvd IRQs */
3110 info->ie1_value &= ~(FLGD|IDLD);
3111 write_reg(info, IE1, info->ie1_value);
3112 }
3113 spin_unlock_irqrestore(&info->lock,flags);
3114 }
3115 exit:
3116 if ( rc == 0 )
3117 PUT_USER(rc, events, mask_ptr);
3118
3119 return rc;
3120 }
3121
3122 static int modem_input_wait(SLMP_INFO *info,int arg)
3123 {
3124 unsigned long flags;
3125 int rc;
3126 struct mgsl_icount cprev, cnow;
3127 DECLARE_WAITQUEUE(wait, current);
3128
3129 /* save current irq counts */
3130 spin_lock_irqsave(&info->lock,flags);
3131 cprev = info->icount;
3132 add_wait_queue(&info->status_event_wait_q, &wait);
3133 set_current_state(TASK_INTERRUPTIBLE);
3134 spin_unlock_irqrestore(&info->lock,flags);
3135
3136 for(;;) {
3137 schedule();
3138 if (signal_pending(current)) {
3139 rc = -ERESTARTSYS;
3140 break;
3141 }
3142
3143 /* get new irq counts */
3144 spin_lock_irqsave(&info->lock,flags);
3145 cnow = info->icount;
3146 set_current_state(TASK_INTERRUPTIBLE);
3147 spin_unlock_irqrestore(&info->lock,flags);
3148
3149 /* if no change, wait aborted for some reason */
3150 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3151 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3152 rc = -EIO;
3153 break;
3154 }
3155
3156 /* check for change in caller specified modem input */
3157 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3158 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3159 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3160 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3161 rc = 0;
3162 break;
3163 }
3164
3165 cprev = cnow;
3166 }
3167 remove_wait_queue(&info->status_event_wait_q, &wait);
3168 set_current_state(TASK_RUNNING);
3169 return rc;
3170 }
3171
3172 /* return the state of the serial control and status signals
3173 */
3174 static int tiocmget(struct tty_struct *tty)
3175 {
3176 SLMP_INFO *info = tty->driver_data;
3177 unsigned int result;
3178 unsigned long flags;
3179
3180 spin_lock_irqsave(&info->lock,flags);
3181 get_signals(info);
3182 spin_unlock_irqrestore(&info->lock,flags);
3183
3184 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS : 0) |
3185 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR : 0) |
3186 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR : 0) |
3187 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG : 0) |
3188 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR : 0) |
3189 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS : 0);
3190
3191 if (debug_level >= DEBUG_LEVEL_INFO)
3192 printk("%s(%d):%s tiocmget() value=%08X\n",
3193 __FILE__,__LINE__, info->device_name, result );
3194 return result;
3195 }
3196
3197 /* set modem control signals (DTR/RTS)
3198 */
3199 static int tiocmset(struct tty_struct *tty,
3200 unsigned int set, unsigned int clear)
3201 {
3202 SLMP_INFO *info = tty->driver_data;
3203 unsigned long flags;
3204
3205 if (debug_level >= DEBUG_LEVEL_INFO)
3206 printk("%s(%d):%s tiocmset(%x,%x)\n",
3207 __FILE__,__LINE__,info->device_name, set, clear);
3208
3209 if (set & TIOCM_RTS)
3210 info->serial_signals |= SerialSignal_RTS;
3211 if (set & TIOCM_DTR)
3212 info->serial_signals |= SerialSignal_DTR;
3213 if (clear & TIOCM_RTS)
3214 info->serial_signals &= ~SerialSignal_RTS;
3215 if (clear & TIOCM_DTR)
3216 info->serial_signals &= ~SerialSignal_DTR;
3217
3218 spin_lock_irqsave(&info->lock,flags);
3219 set_signals(info);
3220 spin_unlock_irqrestore(&info->lock,flags);
3221
3222 return 0;
3223 }
3224
3225 static int carrier_raised(struct tty_port *port)
3226 {
3227 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3228 unsigned long flags;
3229
3230 spin_lock_irqsave(&info->lock,flags);
3231 get_signals(info);
3232 spin_unlock_irqrestore(&info->lock,flags);
3233
3234 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3235 }
3236
3237 static void dtr_rts(struct tty_port *port, int on)
3238 {
3239 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3240 unsigned long flags;
3241
3242 spin_lock_irqsave(&info->lock,flags);
3243 if (on)
3244 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
3245 else
3246 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3247 set_signals(info);
3248 spin_unlock_irqrestore(&info->lock,flags);
3249 }
3250
3251 /* Block the current process until the specified port is ready to open.
3252 */
3253 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3254 SLMP_INFO *info)
3255 {
3256 DECLARE_WAITQUEUE(wait, current);
3257 int retval;
3258 bool do_clocal = false;
3259 unsigned long flags;
3260 int cd;
3261 struct tty_port *port = &info->port;
3262
3263 if (debug_level >= DEBUG_LEVEL_INFO)
3264 printk("%s(%d):%s block_til_ready()\n",
3265 __FILE__,__LINE__, tty->driver->name );
3266
3267 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3268 /* nonblock mode is set or port is not enabled */
3269 /* just verify that callout device is not active */
3270 tty_port_set_active(port, 1);
3271 return 0;
3272 }
3273
3274 if (C_CLOCAL(tty))
3275 do_clocal = true;
3276
3277 /* Wait for carrier detect and the line to become
3278 * free (i.e., not in use by the callout). While we are in
3279 * this loop, port->count is dropped by one, so that
3280 * close() knows when to free things. We restore it upon
3281 * exit, either normal or abnormal.
3282 */
3283
3284 retval = 0;
3285 add_wait_queue(&port->open_wait, &wait);
3286
3287 if (debug_level >= DEBUG_LEVEL_INFO)
3288 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3289 __FILE__,__LINE__, tty->driver->name, port->count );
3290
3291 spin_lock_irqsave(&info->lock, flags);
3292 port->count--;
3293 spin_unlock_irqrestore(&info->lock, flags);
3294 port->blocked_open++;
3295
3296 while (1) {
3297 if (C_BAUD(tty) && tty_port_initialized(port))
3298 tty_port_raise_dtr_rts(port);
3299
3300 set_current_state(TASK_INTERRUPTIBLE);
3301
3302 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3303 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3304 -EAGAIN : -ERESTARTSYS;
3305 break;
3306 }
3307
3308 cd = tty_port_carrier_raised(port);
3309 if (do_clocal || cd)
3310 break;
3311
3312 if (signal_pending(current)) {
3313 retval = -ERESTARTSYS;
3314 break;
3315 }
3316
3317 if (debug_level >= DEBUG_LEVEL_INFO)
3318 printk("%s(%d):%s block_til_ready() count=%d\n",
3319 __FILE__,__LINE__, tty->driver->name, port->count );
3320
3321 tty_unlock(tty);
3322 schedule();
3323 tty_lock(tty);
3324 }
3325
3326 set_current_state(TASK_RUNNING);
3327 remove_wait_queue(&port->open_wait, &wait);
3328 if (!tty_hung_up_p(filp))
3329 port->count++;
3330 port->blocked_open--;
3331
3332 if (debug_level >= DEBUG_LEVEL_INFO)
3333 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3334 __FILE__,__LINE__, tty->driver->name, port->count );
3335
3336 if (!retval)
3337 tty_port_set_active(port, 1);
3338
3339 return retval;
3340 }
3341
3342 static int alloc_dma_bufs(SLMP_INFO *info)
3343 {
3344 unsigned short BuffersPerFrame;
3345 unsigned short BufferCount;
3346
3347 // Force allocation to start at 64K boundary for each port.
3348 // This is necessary because *all* buffer descriptors for a port
3349 // *must* be in the same 64K block. All descriptors on a port
3350 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3351 // into the CBP register.
3352 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3353
3354 /* Calculate the number of DMA buffers necessary to hold the */
3355 /* largest allowable frame size. Note: If the max frame size is */
3356 /* not an even multiple of the DMA buffer size then we need to */
3357 /* round the buffer count per frame up one. */
3358
3359 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3360 if ( info->max_frame_size % SCABUFSIZE )
3361 BuffersPerFrame++;
3362
3363 /* calculate total number of data buffers (SCABUFSIZE) possible
3364 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3365 * for the descriptor list (BUFFERLISTSIZE).
3366 */
3367 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3368
3369 /* limit number of buffers to maximum amount of descriptors */
3370 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3371 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3372
3373 /* use enough buffers to transmit one max size frame */
3374 info->tx_buf_count = BuffersPerFrame + 1;
3375
3376 /* never use more than half the available buffers for transmit */
3377 if (info->tx_buf_count > (BufferCount/2))
3378 info->tx_buf_count = BufferCount/2;
3379
3380 if (info->tx_buf_count > SCAMAXDESC)
3381 info->tx_buf_count = SCAMAXDESC;
3382
3383 /* use remaining buffers for receive */
3384 info->rx_buf_count = BufferCount - info->tx_buf_count;
3385
3386 if (info->rx_buf_count > SCAMAXDESC)
3387 info->rx_buf_count = SCAMAXDESC;
3388
3389 if ( debug_level >= DEBUG_LEVEL_INFO )
3390 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3391 __FILE__,__LINE__, info->device_name,
3392 info->tx_buf_count,info->rx_buf_count);
3393
3394 if ( alloc_buf_list( info ) < 0 ||
3395 alloc_frame_bufs(info,
3396 info->rx_buf_list,
3397 info->rx_buf_list_ex,
3398 info->rx_buf_count) < 0 ||
3399 alloc_frame_bufs(info,
3400 info->tx_buf_list,
3401 info->tx_buf_list_ex,
3402 info->tx_buf_count) < 0 ||
3403 alloc_tmp_rx_buf(info) < 0 ) {
3404 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3405 __FILE__,__LINE__, info->device_name);
3406 return -ENOMEM;
3407 }
3408
3409 rx_reset_buffers( info );
3410
3411 return 0;
3412 }
3413
3414 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3415 */
3416 static int alloc_buf_list(SLMP_INFO *info)
3417 {
3418 unsigned int i;
3419
3420 /* build list in adapter shared memory */
3421 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3422 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3423 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3424
3425 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3426
3427 /* Save virtual address pointers to the receive and */
3428 /* transmit buffer lists. (Receive 1st). These pointers will */
3429 /* be used by the processor to access the lists. */
3430 info->rx_buf_list = (SCADESC *)info->buffer_list;
3431
3432 info->tx_buf_list = (SCADESC *)info->buffer_list;
3433 info->tx_buf_list += info->rx_buf_count;
3434
3435 /* Build links for circular buffer entry lists (tx and rx)
3436 *
3437 * Note: links are physical addresses read by the SCA device
3438 * to determine the next buffer entry to use.
3439 */
3440
3441 for ( i = 0; i < info->rx_buf_count; i++ ) {
3442 /* calculate and store physical address of this buffer entry */
3443 info->rx_buf_list_ex[i].phys_entry =
3444 info->buffer_list_phys + (i * SCABUFSIZE);
3445
3446 /* calculate and store physical address of */
3447 /* next entry in cirular list of entries */
3448 info->rx_buf_list[i].next = info->buffer_list_phys;
3449 if ( i < info->rx_buf_count - 1 )
3450 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3451
3452 info->rx_buf_list[i].length = SCABUFSIZE;
3453 }
3454
3455 for ( i = 0; i < info->tx_buf_count; i++ ) {
3456 /* calculate and store physical address of this buffer entry */
3457 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3458 ((info->rx_buf_count + i) * sizeof(SCADESC));
3459
3460 /* calculate and store physical address of */
3461 /* next entry in cirular list of entries */
3462
3463 info->tx_buf_list[i].next = info->buffer_list_phys +
3464 info->rx_buf_count * sizeof(SCADESC);
3465
3466 if ( i < info->tx_buf_count - 1 )
3467 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3468 }
3469
3470 return 0;
3471 }
3472
3473 /* Allocate the frame DMA buffers used by the specified buffer list.
3474 */
3475 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3476 {
3477 int i;
3478 unsigned long phys_addr;
3479
3480 for ( i = 0; i < count; i++ ) {
3481 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3482 phys_addr = info->port_array[0]->last_mem_alloc;
3483 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3484
3485 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3486 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3487 }
3488
3489 return 0;
3490 }
3491
3492 static void free_dma_bufs(SLMP_INFO *info)
3493 {
3494 info->buffer_list = NULL;
3495 info->rx_buf_list = NULL;
3496 info->tx_buf_list = NULL;
3497 }
3498
3499 /* allocate buffer large enough to hold max_frame_size.
3500 * This buffer is used to pass an assembled frame to the line discipline.
3501 */
3502 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3503 {
3504 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3505 if (info->tmp_rx_buf == NULL)
3506 return -ENOMEM;
3507 /* unused flag buffer to satisfy receive_buf calling interface */
3508 info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
3509 if (!info->flag_buf) {
3510 kfree(info->tmp_rx_buf);
3511 info->tmp_rx_buf = NULL;
3512 return -ENOMEM;
3513 }
3514 return 0;
3515 }
3516
3517 static void free_tmp_rx_buf(SLMP_INFO *info)
3518 {
3519 kfree(info->tmp_rx_buf);
3520 info->tmp_rx_buf = NULL;
3521 kfree(info->flag_buf);
3522 info->flag_buf = NULL;
3523 }
3524
3525 static int claim_resources(SLMP_INFO *info)
3526 {
3527 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3528 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3529 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3530 info->init_error = DiagStatus_AddressConflict;
3531 goto errout;
3532 }
3533 else
3534 info->shared_mem_requested = true;
3535
3536 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3537 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3538 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3539 info->init_error = DiagStatus_AddressConflict;
3540 goto errout;
3541 }
3542 else
3543 info->lcr_mem_requested = true;
3544
3545 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3546 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3547 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3548 info->init_error = DiagStatus_AddressConflict;
3549 goto errout;
3550 }
3551 else
3552 info->sca_base_requested = true;
3553
3554 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3555 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3556 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3557 info->init_error = DiagStatus_AddressConflict;
3558 goto errout;
3559 }
3560 else
3561 info->sca_statctrl_requested = true;
3562
3563 info->memory_base = ioremap_nocache(info->phys_memory_base,
3564 SCA_MEM_SIZE);
3565 if (!info->memory_base) {
3566 printk( "%s(%d):%s Can't map shared memory, MemAddr=%08X\n",
3567 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3568 info->init_error = DiagStatus_CantAssignPciResources;
3569 goto errout;
3570 }
3571
3572 info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3573 if (!info->lcr_base) {
3574 printk( "%s(%d):%s Can't map LCR memory, MemAddr=%08X\n",
3575 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3576 info->init_error = DiagStatus_CantAssignPciResources;
3577 goto errout;
3578 }
3579 info->lcr_base += info->lcr_offset;
3580
3581 info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3582 if (!info->sca_base) {
3583 printk( "%s(%d):%s Can't map SCA memory, MemAddr=%08X\n",
3584 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3585 info->init_error = DiagStatus_CantAssignPciResources;
3586 goto errout;
3587 }
3588 info->sca_base += info->sca_offset;
3589
3590 info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3591 PAGE_SIZE);
3592 if (!info->statctrl_base) {
3593 printk( "%s(%d):%s Can't map SCA Status/Control memory, MemAddr=%08X\n",
3594 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3595 info->init_error = DiagStatus_CantAssignPciResources;
3596 goto errout;
3597 }
3598 info->statctrl_base += info->statctrl_offset;
3599
3600 if ( !memory_test(info) ) {
3601 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3602 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3603 info->init_error = DiagStatus_MemoryError;
3604 goto errout;
3605 }
3606
3607 return 0;
3608
3609 errout:
3610 release_resources( info );
3611 return -ENODEV;
3612 }
3613
3614 static void release_resources(SLMP_INFO *info)
3615 {
3616 if ( debug_level >= DEBUG_LEVEL_INFO )
3617 printk( "%s(%d):%s release_resources() entry\n",
3618 __FILE__,__LINE__,info->device_name );
3619
3620 if ( info->irq_requested ) {
3621 free_irq(info->irq_level, info);
3622 info->irq_requested = false;
3623 }
3624
3625 if ( info->shared_mem_requested ) {
3626 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3627 info->shared_mem_requested = false;
3628 }
3629 if ( info->lcr_mem_requested ) {
3630 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3631 info->lcr_mem_requested = false;
3632 }
3633 if ( info->sca_base_requested ) {
3634 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3635 info->sca_base_requested = false;
3636 }
3637 if ( info->sca_statctrl_requested ) {
3638 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3639 info->sca_statctrl_requested = false;
3640 }
3641
3642 if (info->memory_base){
3643 iounmap(info->memory_base);
3644 info->memory_base = NULL;
3645 }
3646
3647 if (info->sca_base) {
3648 iounmap(info->sca_base - info->sca_offset);
3649 info->sca_base=NULL;
3650 }
3651
3652 if (info->statctrl_base) {
3653 iounmap(info->statctrl_base - info->statctrl_offset);
3654 info->statctrl_base=NULL;
3655 }
3656
3657 if (info->lcr_base){
3658 iounmap(info->lcr_base - info->lcr_offset);
3659 info->lcr_base = NULL;
3660 }
3661
3662 if ( debug_level >= DEBUG_LEVEL_INFO )
3663 printk( "%s(%d):%s release_resources() exit\n",
3664 __FILE__,__LINE__,info->device_name );
3665 }
3666
3667 /* Add the specified device instance data structure to the
3668 * global linked list of devices and increment the device count.
3669 */
3670 static int add_device(SLMP_INFO *info)
3671 {
3672 info->next_device = NULL;
3673 info->line = synclinkmp_device_count;
3674 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3675
3676 if (info->line < MAX_DEVICES) {
3677 if (maxframe[info->line])
3678 info->max_frame_size = maxframe[info->line];
3679 }
3680
3681 synclinkmp_device_count++;
3682
3683 if ( !synclinkmp_device_list )
3684 synclinkmp_device_list = info;
3685 else {
3686 SLMP_INFO *current_dev = synclinkmp_device_list;
3687 while( current_dev->next_device )
3688 current_dev = current_dev->next_device;
3689 current_dev->next_device = info;
3690 }
3691
3692 if ( info->max_frame_size < 4096 )
3693 info->max_frame_size = 4096;
3694 else if ( info->max_frame_size > 65535 )
3695 info->max_frame_size = 65535;
3696
3697 printk( "SyncLink MultiPort %s: "
3698 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3699 info->device_name,
3700 info->phys_sca_base,
3701 info->phys_memory_base,
3702 info->phys_statctrl_base,
3703 info->phys_lcr_base,
3704 info->irq_level,
3705 info->max_frame_size );
3706
3707 #if SYNCLINK_GENERIC_HDLC
3708 return hdlcdev_init(info);
3709 #else
3710 return 0;
3711 #endif
3712 }
3713
3714 static const struct tty_port_operations port_ops = {
3715 .carrier_raised = carrier_raised,
3716 .dtr_rts = dtr_rts,
3717 };
3718
3719 /* Allocate and initialize a device instance structure
3720 *
3721 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3722 */
3723 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3724 {
3725 SLMP_INFO *info;
3726
3727 info = kzalloc(sizeof(SLMP_INFO),
3728 GFP_KERNEL);
3729
3730 if (!info) {
3731 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3732 __FILE__,__LINE__, adapter_num, port_num);
3733 } else {
3734 tty_port_init(&info->port);
3735 info->port.ops = &port_ops;
3736 info->magic = MGSL_MAGIC;
3737 INIT_WORK(&info->task, bh_handler);
3738 info->max_frame_size = 4096;
3739 info->port.close_delay = 5*HZ/10;
3740 info->port.closing_wait = 30*HZ;
3741 init_waitqueue_head(&info->status_event_wait_q);
3742 init_waitqueue_head(&info->event_wait_q);
3743 spin_lock_init(&info->netlock);
3744 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3745 info->idle_mode = HDLC_TXIDLE_FLAGS;
3746 info->adapter_num = adapter_num;
3747 info->port_num = port_num;
3748
3749 /* Copy configuration info to device instance data */
3750 info->irq_level = pdev->irq;
3751 info->phys_lcr_base = pci_resource_start(pdev,0);
3752 info->phys_sca_base = pci_resource_start(pdev,2);
3753 info->phys_memory_base = pci_resource_start(pdev,3);
3754 info->phys_statctrl_base = pci_resource_start(pdev,4);
3755
3756 /* Because veremap only works on page boundaries we must map
3757 * a larger area than is actually implemented for the LCR
3758 * memory range. We map a full page starting at the page boundary.
3759 */
3760 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3761 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3762
3763 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3764 info->phys_sca_base &= ~(PAGE_SIZE-1);
3765
3766 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3767 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3768
3769 info->bus_type = MGSL_BUS_TYPE_PCI;
3770 info->irq_flags = IRQF_SHARED;
3771
3772 timer_setup(&info->tx_timer, tx_timeout, 0);
3773 timer_setup(&info->status_timer, status_timeout, 0);
3774
3775 /* Store the PCI9050 misc control register value because a flaw
3776 * in the PCI9050 prevents LCR registers from being read if
3777 * BIOS assigns an LCR base address with bit 7 set.
3778 *
3779 * Only the misc control register is accessed for which only
3780 * write access is needed, so set an initial value and change
3781 * bits to the device instance data as we write the value
3782 * to the actual misc control register.
3783 */
3784 info->misc_ctrl_value = 0x087e4546;
3785
3786 /* initial port state is unknown - if startup errors
3787 * occur, init_error will be set to indicate the
3788 * problem. Once the port is fully initialized,
3789 * this value will be set to 0 to indicate the
3790 * port is available.
3791 */
3792 info->init_error = -1;
3793 }
3794
3795 return info;
3796 }
3797
3798 static int device_init(int adapter_num, struct pci_dev *pdev)
3799 {
3800 SLMP_INFO *port_array[SCA_MAX_PORTS];
3801 int port, rc;
3802
3803 /* allocate device instances for up to SCA_MAX_PORTS devices */
3804 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3805 port_array[port] = alloc_dev(adapter_num,port,pdev);
3806 if( port_array[port] == NULL ) {
3807 for (--port; port >= 0; --port) {
3808 tty_port_destroy(&port_array[port]->port);
3809 kfree(port_array[port]);
3810 }
3811 return -ENOMEM;
3812 }
3813 }
3814
3815 /* give copy of port_array to all ports and add to device list */
3816 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3817 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3818 rc = add_device( port_array[port] );
3819 if (rc)
3820 goto err_add;
3821 spin_lock_init(&port_array[port]->lock);
3822 }
3823
3824 /* Allocate and claim adapter resources */
3825 if ( !claim_resources(port_array[0]) ) {
3826
3827 alloc_dma_bufs(port_array[0]);
3828
3829 /* copy resource information from first port to others */
3830 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3831 port_array[port]->lock = port_array[0]->lock;
3832 port_array[port]->irq_level = port_array[0]->irq_level;
3833 port_array[port]->memory_base = port_array[0]->memory_base;
3834 port_array[port]->sca_base = port_array[0]->sca_base;
3835 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3836 port_array[port]->lcr_base = port_array[0]->lcr_base;
3837 alloc_dma_bufs(port_array[port]);
3838 }
3839
3840 rc = request_irq(port_array[0]->irq_level,
3841 synclinkmp_interrupt,
3842 port_array[0]->irq_flags,
3843 port_array[0]->device_name,
3844 port_array[0]);
3845 if ( rc ) {
3846 printk( "%s(%d):%s Can't request interrupt, IRQ=%d\n",
3847 __FILE__,__LINE__,
3848 port_array[0]->device_name,
3849 port_array[0]->irq_level );
3850 goto err_irq;
3851 }
3852 port_array[0]->irq_requested = true;
3853 adapter_test(port_array[0]);
3854 }
3855 return 0;
3856 err_irq:
3857 release_resources( port_array[0] );
3858 err_add:
3859 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3860 tty_port_destroy(&port_array[port]->port);
3861 kfree(port_array[port]);
3862 }
3863 return rc;
3864 }
3865
3866 static const struct tty_operations ops = {
3867 .install = install,
3868 .open = open,
3869 .close = close,
3870 .write = write,
3871 .put_char = put_char,
3872 .flush_chars = flush_chars,
3873 .write_room = write_room,
3874 .chars_in_buffer = chars_in_buffer,
3875 .flush_buffer = flush_buffer,
3876 .ioctl = ioctl,
3877 .throttle = throttle,
3878 .unthrottle = unthrottle,
3879 .send_xchar = send_xchar,
3880 .break_ctl = set_break,
3881 .wait_until_sent = wait_until_sent,
3882 .set_termios = set_termios,
3883 .stop = tx_hold,
3884 .start = tx_release,
3885 .hangup = hangup,
3886 .tiocmget = tiocmget,
3887 .tiocmset = tiocmset,
3888 .get_icount = get_icount,
3889 .proc_show = synclinkmp_proc_show,
3890 };
3891
3892
3893 static void synclinkmp_cleanup(void)
3894 {
3895 int rc;
3896 SLMP_INFO *info;
3897 SLMP_INFO *tmp;
3898
3899 printk("Unloading %s %s\n", driver_name, driver_version);
3900
3901 if (serial_driver) {
3902 rc = tty_unregister_driver(serial_driver);
3903 if (rc)
3904 printk("%s(%d) failed to unregister tty driver err=%d\n",
3905 __FILE__,__LINE__,rc);
3906 put_tty_driver(serial_driver);
3907 }
3908
3909 /* reset devices */
3910 info = synclinkmp_device_list;
3911 while(info) {
3912 reset_port(info);
3913 info = info->next_device;
3914 }
3915
3916 /* release devices */
3917 info = synclinkmp_device_list;
3918 while(info) {
3919 #if SYNCLINK_GENERIC_HDLC
3920 hdlcdev_exit(info);
3921 #endif
3922 free_dma_bufs(info);
3923 free_tmp_rx_buf(info);
3924 if ( info->port_num == 0 ) {
3925 if (info->sca_base)
3926 write_reg(info, LPR, 1); /* set low power mode */
3927 release_resources(info);
3928 }
3929 tmp = info;
3930 info = info->next_device;
3931 tty_port_destroy(&tmp->port);
3932 kfree(tmp);
3933 }
3934
3935 pci_unregister_driver(&synclinkmp_pci_driver);
3936 }
3937
3938 /* Driver initialization entry point.
3939 */
3940
3941 static int __init synclinkmp_init(void)
3942 {
3943 int rc;
3944
3945 if (break_on_load) {
3946 synclinkmp_get_text_ptr();
3947 BREAKPOINT();
3948 }
3949
3950 printk("%s %s\n", driver_name, driver_version);
3951
3952 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3953 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3954 return rc;
3955 }
3956
3957 serial_driver = alloc_tty_driver(128);
3958 if (!serial_driver) {
3959 rc = -ENOMEM;
3960 goto error;
3961 }
3962
3963 /* Initialize the tty_driver structure */
3964
3965 serial_driver->driver_name = "synclinkmp";
3966 serial_driver->name = "ttySLM";
3967 serial_driver->major = ttymajor;
3968 serial_driver->minor_start = 64;
3969 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3970 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3971 serial_driver->init_termios = tty_std_termios;
3972 serial_driver->init_termios.c_cflag =
3973 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3974 serial_driver->init_termios.c_ispeed = 9600;
3975 serial_driver->init_termios.c_ospeed = 9600;
3976 serial_driver->flags = TTY_DRIVER_REAL_RAW;
3977 tty_set_operations(serial_driver, &ops);
3978 if ((rc = tty_register_driver(serial_driver)) < 0) {
3979 printk("%s(%d):Couldn't register serial driver\n",
3980 __FILE__,__LINE__);
3981 put_tty_driver(serial_driver);
3982 serial_driver = NULL;
3983 goto error;
3984 }
3985
3986 printk("%s %s, tty major#%d\n",
3987 driver_name, driver_version,
3988 serial_driver->major);
3989
3990 return 0;
3991
3992 error:
3993 synclinkmp_cleanup();
3994 return rc;
3995 }
3996
3997 static void __exit synclinkmp_exit(void)
3998 {
3999 synclinkmp_cleanup();
4000 }
4001
4002 module_init(synclinkmp_init);
4003 module_exit(synclinkmp_exit);
4004
4005 /* Set the port for internal loopback mode.
4006 * The TxCLK and RxCLK signals are generated from the BRG and
4007 * the TxD is looped back to the RxD internally.
4008 */
4009 static void enable_loopback(SLMP_INFO *info, int enable)
4010 {
4011 if (enable) {
4012 /* MD2 (Mode Register 2)
4013 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4014 */
4015 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4016
4017 /* degate external TxC clock source */
4018 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4019 write_control_reg(info);
4020
4021 /* RXS/TXS (Rx/Tx clock source)
4022 * 07 Reserved, must be 0
4023 * 06..04 Clock Source, 100=BRG
4024 * 03..00 Clock Divisor, 0000=1
4025 */
4026 write_reg(info, RXS, 0x40);
4027 write_reg(info, TXS, 0x40);
4028
4029 } else {
4030 /* MD2 (Mode Register 2)
4031 * 01..00 CNCT<1..0> Channel connection, 0=normal
4032 */
4033 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4034
4035 /* RXS/TXS (Rx/Tx clock source)
4036 * 07 Reserved, must be 0
4037 * 06..04 Clock Source, 000=RxC/TxC Pin
4038 * 03..00 Clock Divisor, 0000=1
4039 */
4040 write_reg(info, RXS, 0x00);
4041 write_reg(info, TXS, 0x00);
4042 }
4043
4044 /* set LinkSpeed if available, otherwise default to 2Mbps */
4045 if (info->params.clock_speed)
4046 set_rate(info, info->params.clock_speed);
4047 else
4048 set_rate(info, 3686400);
4049 }
4050
4051 /* Set the baud rate register to the desired speed
4052 *
4053 * data_rate data rate of clock in bits per second
4054 * A data rate of 0 disables the AUX clock.
4055 */
4056 static void set_rate( SLMP_INFO *info, u32 data_rate )
4057 {
4058 u32 TMCValue;
4059 unsigned char BRValue;
4060 u32 Divisor=0;
4061
4062 /* fBRG = fCLK/(TMC * 2^BR)
4063 */
4064 if (data_rate != 0) {
4065 Divisor = 14745600/data_rate;
4066 if (!Divisor)
4067 Divisor = 1;
4068
4069 TMCValue = Divisor;
4070
4071 BRValue = 0;
4072 if (TMCValue != 1 && TMCValue != 2) {
4073 /* BRValue of 0 provides 50/50 duty cycle *only* when
4074 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4075 * 50/50 duty cycle.
4076 */
4077 BRValue = 1;
4078 TMCValue >>= 1;
4079 }
4080
4081 /* while TMCValue is too big for TMC register, divide
4082 * by 2 and increment BR exponent.
4083 */
4084 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4085 TMCValue >>= 1;
4086
4087 write_reg(info, TXS,
4088 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4089 write_reg(info, RXS,
4090 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4091 write_reg(info, TMC, (unsigned char)TMCValue);
4092 }
4093 else {
4094 write_reg(info, TXS,0);
4095 write_reg(info, RXS,0);
4096 write_reg(info, TMC, 0);
4097 }
4098 }
4099
4100 /* Disable receiver
4101 */
4102 static void rx_stop(SLMP_INFO *info)
4103 {
4104 if (debug_level >= DEBUG_LEVEL_ISR)
4105 printk("%s(%d):%s rx_stop()\n",
4106 __FILE__,__LINE__, info->device_name );
4107
4108 write_reg(info, CMD, RXRESET);
4109
4110 info->ie0_value &= ~RXRDYE;
4111 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
4112
4113 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4114 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4115 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4116
4117 info->rx_enabled = false;
4118 info->rx_overflow = false;
4119 }
4120
4121 /* enable the receiver
4122 */
4123 static void rx_start(SLMP_INFO *info)
4124 {
4125 int i;
4126
4127 if (debug_level >= DEBUG_LEVEL_ISR)
4128 printk("%s(%d):%s rx_start()\n",
4129 __FILE__,__LINE__, info->device_name );
4130
4131 write_reg(info, CMD, RXRESET);
4132
4133 if ( info->params.mode == MGSL_MODE_HDLC ) {
4134 /* HDLC, disabe IRQ on rxdata */
4135 info->ie0_value &= ~RXRDYE;
4136 write_reg(info, IE0, info->ie0_value);
4137
4138 /* Reset all Rx DMA buffers and program rx dma */
4139 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4140 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4141
4142 for (i = 0; i < info->rx_buf_count; i++) {
4143 info->rx_buf_list[i].status = 0xff;
4144
4145 // throttle to 4 shared memory writes at a time to prevent
4146 // hogging local bus (keep latency time for DMA requests low).
4147 if (!(i % 4))
4148 read_status_reg(info);
4149 }
4150 info->current_rx_buf = 0;
4151
4152 /* set current/1st descriptor address */
4153 write_reg16(info, RXDMA + CDA,
4154 info->rx_buf_list_ex[0].phys_entry);
4155
4156 /* set new last rx descriptor address */
4157 write_reg16(info, RXDMA + EDA,
4158 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4159
4160 /* set buffer length (shared by all rx dma data buffers) */
4161 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4162
4163 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4164 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4165 } else {
4166 /* async, enable IRQ on rxdata */
4167 info->ie0_value |= RXRDYE;
4168 write_reg(info, IE0, info->ie0_value);
4169 }
4170
4171 write_reg(info, CMD, RXENABLE);
4172
4173 info->rx_overflow = false;
4174 info->rx_enabled = true;
4175 }
4176
4177 /* Enable the transmitter and send a transmit frame if
4178 * one is loaded in the DMA buffers.
4179 */
4180 static void tx_start(SLMP_INFO *info)
4181 {
4182 if (debug_level >= DEBUG_LEVEL_ISR)
4183 printk("%s(%d):%s tx_start() tx_count=%d\n",
4184 __FILE__,__LINE__, info->device_name,info->tx_count );
4185
4186 if (!info->tx_enabled ) {
4187 write_reg(info, CMD, TXRESET);
4188 write_reg(info, CMD, TXENABLE);
4189 info->tx_enabled = true;
4190 }
4191
4192 if ( info->tx_count ) {
4193
4194 /* If auto RTS enabled and RTS is inactive, then assert */
4195 /* RTS and set a flag indicating that the driver should */
4196 /* negate RTS when the transmission completes. */
4197
4198 info->drop_rts_on_tx_done = false;
4199
4200 if (info->params.mode != MGSL_MODE_ASYNC) {
4201
4202 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4203 get_signals( info );
4204 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4205 info->serial_signals |= SerialSignal_RTS;
4206 set_signals( info );
4207 info->drop_rts_on_tx_done = true;
4208 }
4209 }
4210
4211 write_reg16(info, TRC0,
4212 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4213
4214 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4215 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4216
4217 /* set TX CDA (current descriptor address) */
4218 write_reg16(info, TXDMA + CDA,
4219 info->tx_buf_list_ex[0].phys_entry);
4220
4221 /* set TX EDA (last descriptor address) */
4222 write_reg16(info, TXDMA + EDA,
4223 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4224
4225 /* enable underrun IRQ */
4226 info->ie1_value &= ~IDLE;
4227 info->ie1_value |= UDRN;
4228 write_reg(info, IE1, info->ie1_value);
4229 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4230
4231 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4232 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4233
4234 mod_timer(&info->tx_timer, jiffies +
4235 msecs_to_jiffies(5000));
4236 }
4237 else {
4238 tx_load_fifo(info);
4239 /* async, enable IRQ on txdata */
4240 info->ie0_value |= TXRDYE;
4241 write_reg(info, IE0, info->ie0_value);
4242 }
4243
4244 info->tx_active = true;
4245 }
4246 }
4247
4248 /* stop the transmitter and DMA
4249 */
4250 static void tx_stop( SLMP_INFO *info )
4251 {
4252 if (debug_level >= DEBUG_LEVEL_ISR)
4253 printk("%s(%d):%s tx_stop()\n",
4254 __FILE__,__LINE__, info->device_name );
4255
4256 del_timer(&info->tx_timer);
4257
4258 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4259 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4260
4261 write_reg(info, CMD, TXRESET);
4262
4263 info->ie1_value &= ~(UDRN + IDLE);
4264 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4265 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4266
4267 info->ie0_value &= ~TXRDYE;
4268 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4269
4270 info->tx_enabled = false;
4271 info->tx_active = false;
4272 }
4273
4274 /* Fill the transmit FIFO until the FIFO is full or
4275 * there is no more data to load.
4276 */
4277 static void tx_load_fifo(SLMP_INFO *info)
4278 {
4279 u8 TwoBytes[2];
4280
4281 /* do nothing is now tx data available and no XON/XOFF pending */
4282
4283 if ( !info->tx_count && !info->x_char )
4284 return;
4285
4286 /* load the Transmit FIFO until FIFOs full or all data sent */
4287
4288 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4289
4290 /* there is more space in the transmit FIFO and */
4291 /* there is more data in transmit buffer */
4292
4293 if ( (info->tx_count > 1) && !info->x_char ) {
4294 /* write 16-bits */
4295 TwoBytes[0] = info->tx_buf[info->tx_get++];
4296 if (info->tx_get >= info->max_frame_size)
4297 info->tx_get -= info->max_frame_size;
4298 TwoBytes[1] = info->tx_buf[info->tx_get++];
4299 if (info->tx_get >= info->max_frame_size)
4300 info->tx_get -= info->max_frame_size;
4301
4302 write_reg16(info, TRB, *((u16 *)TwoBytes));
4303
4304 info->tx_count -= 2;
4305 info->icount.tx += 2;
4306 } else {
4307 /* only 1 byte left to transmit or 1 FIFO slot left */
4308
4309 if (info->x_char) {
4310 /* transmit pending high priority char */
4311 write_reg(info, TRB, info->x_char);
4312 info->x_char = 0;
4313 } else {
4314 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4315 if (info->tx_get >= info->max_frame_size)
4316 info->tx_get -= info->max_frame_size;
4317 info->tx_count--;
4318 }
4319 info->icount.tx++;
4320 }
4321 }
4322 }
4323
4324 /* Reset a port to a known state
4325 */
4326 static void reset_port(SLMP_INFO *info)
4327 {
4328 if (info->sca_base) {
4329
4330 tx_stop(info);
4331 rx_stop(info);
4332
4333 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4334 set_signals(info);
4335
4336 /* disable all port interrupts */
4337 info->ie0_value = 0;
4338 info->ie1_value = 0;
4339 info->ie2_value = 0;
4340 write_reg(info, IE0, info->ie0_value);
4341 write_reg(info, IE1, info->ie1_value);
4342 write_reg(info, IE2, info->ie2_value);
4343
4344 write_reg(info, CMD, CHRESET);
4345 }
4346 }
4347
4348 /* Reset all the ports to a known state.
4349 */
4350 static void reset_adapter(SLMP_INFO *info)
4351 {
4352 int i;
4353
4354 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4355 if (info->port_array[i])
4356 reset_port(info->port_array[i]);
4357 }
4358 }
4359
4360 /* Program port for asynchronous communications.
4361 */
4362 static void async_mode(SLMP_INFO *info)
4363 {
4364
4365 unsigned char RegValue;
4366
4367 tx_stop(info);
4368 rx_stop(info);
4369
4370 /* MD0, Mode Register 0
4371 *
4372 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4373 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4374 * 03 Reserved, must be 0
4375 * 02 CRCCC, CRC Calculation, 0=disabled
4376 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4377 *
4378 * 0000 0000
4379 */
4380 RegValue = 0x00;
4381 if (info->params.stop_bits != 1)
4382 RegValue |= BIT1;
4383 write_reg(info, MD0, RegValue);
4384
4385 /* MD1, Mode Register 1
4386 *
4387 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4388 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4389 * 03..02 RXCHR<1..0>, rx char size
4390 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4391 *
4392 * 0100 0000
4393 */
4394 RegValue = 0x40;
4395 switch (info->params.data_bits) {
4396 case 7: RegValue |= BIT4 + BIT2; break;
4397 case 6: RegValue |= BIT5 + BIT3; break;
4398 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4399 }
4400 if (info->params.parity != ASYNC_PARITY_NONE) {
4401 RegValue |= BIT1;
4402 if (info->params.parity == ASYNC_PARITY_ODD)
4403 RegValue |= BIT0;
4404 }
4405 write_reg(info, MD1, RegValue);
4406
4407 /* MD2, Mode Register 2
4408 *
4409 * 07..02 Reserved, must be 0
4410 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4411 *
4412 * 0000 0000
4413 */
4414 RegValue = 0x00;
4415 if (info->params.loopback)
4416 RegValue |= (BIT1 + BIT0);
4417 write_reg(info, MD2, RegValue);
4418
4419 /* RXS, Receive clock source
4420 *
4421 * 07 Reserved, must be 0
4422 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4423 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4424 */
4425 RegValue=BIT6;
4426 write_reg(info, RXS, RegValue);
4427
4428 /* TXS, Transmit clock source
4429 *
4430 * 07 Reserved, must be 0
4431 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4432 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4433 */
4434 RegValue=BIT6;
4435 write_reg(info, TXS, RegValue);
4436
4437 /* Control Register
4438 *
4439 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4440 */
4441 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4442 write_control_reg(info);
4443
4444 tx_set_idle(info);
4445
4446 /* RRC Receive Ready Control 0
4447 *
4448 * 07..05 Reserved, must be 0
4449 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4450 */
4451 write_reg(info, RRC, 0x00);
4452
4453 /* TRC0 Transmit Ready Control 0
4454 *
4455 * 07..05 Reserved, must be 0
4456 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4457 */
4458 write_reg(info, TRC0, 0x10);
4459
4460 /* TRC1 Transmit Ready Control 1
4461 *
4462 * 07..05 Reserved, must be 0
4463 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4464 */
4465 write_reg(info, TRC1, 0x1e);
4466
4467 /* CTL, MSCI control register
4468 *
4469 * 07..06 Reserved, set to 0
4470 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4471 * 04 IDLC, idle control, 0=mark 1=idle register
4472 * 03 BRK, break, 0=off 1 =on (async)
4473 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4474 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4475 * 00 RTS, RTS output control, 0=active 1=inactive
4476 *
4477 * 0001 0001
4478 */
4479 RegValue = 0x10;
4480 if (!(info->serial_signals & SerialSignal_RTS))
4481 RegValue |= 0x01;
4482 write_reg(info, CTL, RegValue);
4483
4484 /* enable status interrupts */
4485 info->ie0_value |= TXINTE + RXINTE;
4486 write_reg(info, IE0, info->ie0_value);
4487
4488 /* enable break detect interrupt */
4489 info->ie1_value = BRKD;
4490 write_reg(info, IE1, info->ie1_value);
4491
4492 /* enable rx overrun interrupt */
4493 info->ie2_value = OVRN;
4494 write_reg(info, IE2, info->ie2_value);
4495
4496 set_rate( info, info->params.data_rate * 16 );
4497 }
4498
4499 /* Program the SCA for HDLC communications.
4500 */
4501 static void hdlc_mode(SLMP_INFO *info)
4502 {
4503 unsigned char RegValue;
4504 u32 DpllDivisor;
4505
4506 // Can't use DPLL because SCA outputs recovered clock on RxC when
4507 // DPLL mode selected. This causes output contention with RxC receiver.
4508 // Use of DPLL would require external hardware to disable RxC receiver
4509 // when DPLL mode selected.
4510 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4511
4512 /* disable DMA interrupts */
4513 write_reg(info, TXDMA + DIR, 0);
4514 write_reg(info, RXDMA + DIR, 0);
4515
4516 /* MD0, Mode Register 0
4517 *
4518 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4519 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4520 * 03 Reserved, must be 0
4521 * 02 CRCCC, CRC Calculation, 1=enabled
4522 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4523 * 00 CRC0, CRC initial value, 1 = all 1s
4524 *
4525 * 1000 0001
4526 */
4527 RegValue = 0x81;
4528 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4529 RegValue |= BIT4;
4530 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4531 RegValue |= BIT4;
4532 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4533 RegValue |= BIT2 + BIT1;
4534 write_reg(info, MD0, RegValue);
4535
4536 /* MD1, Mode Register 1
4537 *
4538 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4539 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4540 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4541 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4542 *
4543 * 0000 0000
4544 */
4545 RegValue = 0x00;
4546 write_reg(info, MD1, RegValue);
4547
4548 /* MD2, Mode Register 2
4549 *
4550 * 07 NRZFM, 0=NRZ, 1=FM
4551 * 06..05 CODE<1..0> Encoding, 00=NRZ
4552 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4553 * 02 Reserved, must be 0
4554 * 01..00 CNCT<1..0> Channel connection, 0=normal
4555 *
4556 * 0000 0000
4557 */
4558 RegValue = 0x00;
4559 switch(info->params.encoding) {
4560 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4561 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4562 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4563 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4564 #if 0
4565 case HDLC_ENCODING_NRZB: /* not supported */
4566 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4567 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4568 #endif
4569 }
4570 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4571 DpllDivisor = 16;
4572 RegValue |= BIT3;
4573 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4574 DpllDivisor = 8;
4575 } else {
4576 DpllDivisor = 32;
4577 RegValue |= BIT4;
4578 }
4579 write_reg(info, MD2, RegValue);
4580
4581
4582 /* RXS, Receive clock source
4583 *
4584 * 07 Reserved, must be 0
4585 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4586 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4587 */
4588 RegValue=0;
4589 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4590 RegValue |= BIT6;
4591 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4592 RegValue |= BIT6 + BIT5;
4593 write_reg(info, RXS, RegValue);
4594
4595 /* TXS, Transmit clock source
4596 *
4597 * 07 Reserved, must be 0
4598 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4599 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4600 */
4601 RegValue=0;
4602 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4603 RegValue |= BIT6;
4604 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4605 RegValue |= BIT6 + BIT5;
4606 write_reg(info, TXS, RegValue);
4607
4608 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4609 set_rate(info, info->params.clock_speed * DpllDivisor);
4610 else
4611 set_rate(info, info->params.clock_speed);
4612
4613 /* GPDATA (General Purpose I/O Data Register)
4614 *
4615 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4616 */
4617 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4618 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4619 else
4620 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4621 write_control_reg(info);
4622
4623 /* RRC Receive Ready Control 0
4624 *
4625 * 07..05 Reserved, must be 0
4626 * 04..00 RRC<4..0> Rx FIFO trigger active
4627 */
4628 write_reg(info, RRC, rx_active_fifo_level);
4629
4630 /* TRC0 Transmit Ready Control 0
4631 *
4632 * 07..05 Reserved, must be 0
4633 * 04..00 TRC<4..0> Tx FIFO trigger active
4634 */
4635 write_reg(info, TRC0, tx_active_fifo_level);
4636
4637 /* TRC1 Transmit Ready Control 1
4638 *
4639 * 07..05 Reserved, must be 0
4640 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4641 */
4642 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4643
4644 /* DMR, DMA Mode Register
4645 *
4646 * 07..05 Reserved, must be 0
4647 * 04 TMOD, Transfer Mode: 1=chained-block
4648 * 03 Reserved, must be 0
4649 * 02 NF, Number of Frames: 1=multi-frame
4650 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4651 * 00 Reserved, must be 0
4652 *
4653 * 0001 0100
4654 */
4655 write_reg(info, TXDMA + DMR, 0x14);
4656 write_reg(info, RXDMA + DMR, 0x14);
4657
4658 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4659 write_reg(info, RXDMA + CPB,
4660 (unsigned char)(info->buffer_list_phys >> 16));
4661
4662 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4663 write_reg(info, TXDMA + CPB,
4664 (unsigned char)(info->buffer_list_phys >> 16));
4665
4666 /* enable status interrupts. other code enables/disables
4667 * the individual sources for these two interrupt classes.
4668 */
4669 info->ie0_value |= TXINTE + RXINTE;
4670 write_reg(info, IE0, info->ie0_value);
4671
4672 /* CTL, MSCI control register
4673 *
4674 * 07..06 Reserved, set to 0
4675 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4676 * 04 IDLC, idle control, 0=mark 1=idle register
4677 * 03 BRK, break, 0=off 1 =on (async)
4678 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4679 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4680 * 00 RTS, RTS output control, 0=active 1=inactive
4681 *
4682 * 0001 0001
4683 */
4684 RegValue = 0x10;
4685 if (!(info->serial_signals & SerialSignal_RTS))
4686 RegValue |= 0x01;
4687 write_reg(info, CTL, RegValue);
4688
4689 /* preamble not supported ! */
4690
4691 tx_set_idle(info);
4692 tx_stop(info);
4693 rx_stop(info);
4694
4695 set_rate(info, info->params.clock_speed);
4696
4697 if (info->params.loopback)
4698 enable_loopback(info,1);
4699 }
4700
4701 /* Set the transmit HDLC idle mode
4702 */
4703 static void tx_set_idle(SLMP_INFO *info)
4704 {
4705 unsigned char RegValue = 0xff;
4706
4707 /* Map API idle mode to SCA register bits */
4708 switch(info->idle_mode) {
4709 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4710 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4711 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4712 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4713 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4714 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4715 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4716 }
4717
4718 write_reg(info, IDL, RegValue);
4719 }
4720
4721 /* Query the adapter for the state of the V24 status (input) signals.
4722 */
4723 static void get_signals(SLMP_INFO *info)
4724 {
4725 u16 status = read_reg(info, SR3);
4726 u16 gpstatus = read_status_reg(info);
4727 u16 testbit;
4728
4729 /* clear all serial signals except RTS and DTR */
4730 info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
4731
4732 /* set serial signal bits to reflect MISR */
4733
4734 if (!(status & BIT3))
4735 info->serial_signals |= SerialSignal_CTS;
4736
4737 if ( !(status & BIT2))
4738 info->serial_signals |= SerialSignal_DCD;
4739
4740 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4741 if (!(gpstatus & testbit))
4742 info->serial_signals |= SerialSignal_RI;
4743
4744 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4745 if (!(gpstatus & testbit))
4746 info->serial_signals |= SerialSignal_DSR;
4747 }
4748
4749 /* Set the state of RTS and DTR based on contents of
4750 * serial_signals member of device context.
4751 */
4752 static void set_signals(SLMP_INFO *info)
4753 {
4754 unsigned char RegValue;
4755 u16 EnableBit;
4756
4757 RegValue = read_reg(info, CTL);
4758 if (info->serial_signals & SerialSignal_RTS)
4759 RegValue &= ~BIT0;
4760 else
4761 RegValue |= BIT0;
4762 write_reg(info, CTL, RegValue);
4763
4764 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4765 EnableBit = BIT1 << (info->port_num*2);
4766 if (info->serial_signals & SerialSignal_DTR)
4767 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4768 else
4769 info->port_array[0]->ctrlreg_value |= EnableBit;
4770 write_control_reg(info);
4771 }
4772
4773 /*******************/
4774 /* DMA Buffer Code */
4775 /*******************/
4776
4777 /* Set the count for all receive buffers to SCABUFSIZE
4778 * and set the current buffer to the first buffer. This effectively
4779 * makes all buffers free and discards any data in buffers.
4780 */
4781 static void rx_reset_buffers(SLMP_INFO *info)
4782 {
4783 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4784 }
4785
4786 /* Free the buffers used by a received frame
4787 *
4788 * info pointer to device instance data
4789 * first index of 1st receive buffer of frame
4790 * last index of last receive buffer of frame
4791 */
4792 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4793 {
4794 bool done = false;
4795
4796 while(!done) {
4797 /* reset current buffer for reuse */
4798 info->rx_buf_list[first].status = 0xff;
4799
4800 if (first == last) {
4801 done = true;
4802 /* set new last rx descriptor address */
4803 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4804 }
4805
4806 first++;
4807 if (first == info->rx_buf_count)
4808 first = 0;
4809 }
4810
4811 /* set current buffer to next buffer after last buffer of frame */
4812 info->current_rx_buf = first;
4813 }
4814
4815 /* Return a received frame from the receive DMA buffers.
4816 * Only frames received without errors are returned.
4817 *
4818 * Return Value: true if frame returned, otherwise false
4819 */
4820 static bool rx_get_frame(SLMP_INFO *info)
4821 {
4822 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4823 unsigned short status;
4824 unsigned int framesize = 0;
4825 bool ReturnCode = false;
4826 unsigned long flags;
4827 struct tty_struct *tty = info->port.tty;
4828 unsigned char addr_field = 0xff;
4829 SCADESC *desc;
4830 SCADESC_EX *desc_ex;
4831
4832 CheckAgain:
4833 /* assume no frame returned, set zero length */
4834 framesize = 0;
4835 addr_field = 0xff;
4836
4837 /*
4838 * current_rx_buf points to the 1st buffer of the next available
4839 * receive frame. To find the last buffer of the frame look for
4840 * a non-zero status field in the buffer entries. (The status
4841 * field is set by the 16C32 after completing a receive frame.
4842 */
4843 StartIndex = EndIndex = info->current_rx_buf;
4844
4845 for ( ;; ) {
4846 desc = &info->rx_buf_list[EndIndex];
4847 desc_ex = &info->rx_buf_list_ex[EndIndex];
4848
4849 if (desc->status == 0xff)
4850 goto Cleanup; /* current desc still in use, no frames available */
4851
4852 if (framesize == 0 && info->params.addr_filter != 0xff)
4853 addr_field = desc_ex->virt_addr[0];
4854
4855 framesize += desc->length;
4856
4857 /* Status != 0 means last buffer of frame */
4858 if (desc->status)
4859 break;
4860
4861 EndIndex++;
4862 if (EndIndex == info->rx_buf_count)
4863 EndIndex = 0;
4864
4865 if (EndIndex == info->current_rx_buf) {
4866 /* all buffers have been 'used' but none mark */
4867 /* the end of a frame. Reset buffers and receiver. */
4868 if ( info->rx_enabled ){
4869 spin_lock_irqsave(&info->lock,flags);
4870 rx_start(info);
4871 spin_unlock_irqrestore(&info->lock,flags);
4872 }
4873 goto Cleanup;
4874 }
4875
4876 }
4877
4878 /* check status of receive frame */
4879
4880 /* frame status is byte stored after frame data
4881 *
4882 * 7 EOM (end of msg), 1 = last buffer of frame
4883 * 6 Short Frame, 1 = short frame
4884 * 5 Abort, 1 = frame aborted
4885 * 4 Residue, 1 = last byte is partial
4886 * 3 Overrun, 1 = overrun occurred during frame reception
4887 * 2 CRC, 1 = CRC error detected
4888 *
4889 */
4890 status = desc->status;
4891
4892 /* ignore CRC bit if not using CRC (bit is undefined) */
4893 /* Note:CRC is not save to data buffer */
4894 if (info->params.crc_type == HDLC_CRC_NONE)
4895 status &= ~BIT2;
4896
4897 if (framesize == 0 ||
4898 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4899 /* discard 0 byte frames, this seems to occur sometime
4900 * when remote is idling flags.
4901 */
4902 rx_free_frame_buffers(info, StartIndex, EndIndex);
4903 goto CheckAgain;
4904 }
4905
4906 if (framesize < 2)
4907 status |= BIT6;
4908
4909 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4910 /* received frame has errors,
4911 * update counts and mark frame size as 0
4912 */
4913 if (status & BIT6)
4914 info->icount.rxshort++;
4915 else if (status & BIT5)
4916 info->icount.rxabort++;
4917 else if (status & BIT3)
4918 info->icount.rxover++;
4919 else
4920 info->icount.rxcrc++;
4921
4922 framesize = 0;
4923 #if SYNCLINK_GENERIC_HDLC
4924 {
4925 info->netdev->stats.rx_errors++;
4926 info->netdev->stats.rx_frame_errors++;
4927 }
4928 #endif
4929 }
4930
4931 if ( debug_level >= DEBUG_LEVEL_BH )
4932 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4933 __FILE__,__LINE__,info->device_name,status,framesize);
4934
4935 if ( debug_level >= DEBUG_LEVEL_DATA )
4936 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4937 min_t(unsigned int, framesize, SCABUFSIZE), 0);
4938
4939 if (framesize) {
4940 if (framesize > info->max_frame_size)
4941 info->icount.rxlong++;
4942 else {
4943 /* copy dma buffer(s) to contiguous intermediate buffer */
4944 int copy_count = framesize;
4945 int index = StartIndex;
4946 unsigned char *ptmp = info->tmp_rx_buf;
4947 info->tmp_rx_buf_count = framesize;
4948
4949 info->icount.rxok++;
4950
4951 while(copy_count) {
4952 int partial_count = min(copy_count,SCABUFSIZE);
4953 memcpy( ptmp,
4954 info->rx_buf_list_ex[index].virt_addr,
4955 partial_count );
4956 ptmp += partial_count;
4957 copy_count -= partial_count;
4958
4959 if ( ++index == info->rx_buf_count )
4960 index = 0;
4961 }
4962
4963 #if SYNCLINK_GENERIC_HDLC
4964 if (info->netcount)
4965 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4966 else
4967 #endif
4968 ldisc_receive_buf(tty,info->tmp_rx_buf,
4969 info->flag_buf, framesize);
4970 }
4971 }
4972 /* Free the buffers used by this frame. */
4973 rx_free_frame_buffers( info, StartIndex, EndIndex );
4974
4975 ReturnCode = true;
4976
4977 Cleanup:
4978 if ( info->rx_enabled && info->rx_overflow ) {
4979 /* Receiver is enabled, but needs to restarted due to
4980 * rx buffer overflow. If buffers are empty, restart receiver.
4981 */
4982 if (info->rx_buf_list[EndIndex].status == 0xff) {
4983 spin_lock_irqsave(&info->lock,flags);
4984 rx_start(info);
4985 spin_unlock_irqrestore(&info->lock,flags);
4986 }
4987 }
4988
4989 return ReturnCode;
4990 }
4991
4992 /* load the transmit DMA buffer with data
4993 */
4994 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
4995 {
4996 unsigned short copy_count;
4997 unsigned int i = 0;
4998 SCADESC *desc;
4999 SCADESC_EX *desc_ex;
5000
5001 if ( debug_level >= DEBUG_LEVEL_DATA )
5002 trace_block(info, buf, min_t(unsigned int, count, SCABUFSIZE), 1);
5003
5004 /* Copy source buffer to one or more DMA buffers, starting with
5005 * the first transmit dma buffer.
5006 */
5007 for(i=0;;)
5008 {
5009 copy_count = min_t(unsigned int, count, SCABUFSIZE);
5010
5011 desc = &info->tx_buf_list[i];
5012 desc_ex = &info->tx_buf_list_ex[i];
5013
5014 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5015
5016 desc->length = copy_count;
5017 desc->status = 0;
5018
5019 buf += copy_count;
5020 count -= copy_count;
5021
5022 if (!count)
5023 break;
5024
5025 i++;
5026 if (i >= info->tx_buf_count)
5027 i = 0;
5028 }
5029
5030 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
5031 info->last_tx_buf = ++i;
5032 }
5033
5034 static bool register_test(SLMP_INFO *info)
5035 {
5036 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5037 static unsigned int count = ARRAY_SIZE(testval);
5038 unsigned int i;
5039 bool rc = true;
5040 unsigned long flags;
5041
5042 spin_lock_irqsave(&info->lock,flags);
5043 reset_port(info);
5044
5045 /* assume failure */
5046 info->init_error = DiagStatus_AddressFailure;
5047
5048 /* Write bit patterns to various registers but do it out of */
5049 /* sync, then read back and verify values. */
5050
5051 for (i = 0 ; i < count ; i++) {
5052 write_reg(info, TMC, testval[i]);
5053 write_reg(info, IDL, testval[(i+1)%count]);
5054 write_reg(info, SA0, testval[(i+2)%count]);
5055 write_reg(info, SA1, testval[(i+3)%count]);
5056
5057 if ( (read_reg(info, TMC) != testval[i]) ||
5058 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5059 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5060 (read_reg(info, SA1) != testval[(i+3)%count]) )
5061 {
5062 rc = false;
5063 break;
5064 }
5065 }
5066
5067 reset_port(info);
5068 spin_unlock_irqrestore(&info->lock,flags);
5069
5070 return rc;
5071 }
5072
5073 static bool irq_test(SLMP_INFO *info)
5074 {
5075 unsigned long timeout;
5076 unsigned long flags;
5077
5078 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5079
5080 spin_lock_irqsave(&info->lock,flags);
5081 reset_port(info);
5082
5083 /* assume failure */
5084 info->init_error = DiagStatus_IrqFailure;
5085 info->irq_occurred = false;
5086
5087 /* setup timer0 on SCA0 to interrupt */
5088
5089 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5090 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5091
5092 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
5093 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
5094
5095
5096 /* TMCS, Timer Control/Status Register
5097 *
5098 * 07 CMF, Compare match flag (read only) 1=match
5099 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5100 * 05 Reserved, must be 0
5101 * 04 TME, Timer Enable
5102 * 03..00 Reserved, must be 0
5103 *
5104 * 0101 0000
5105 */
5106 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5107
5108 spin_unlock_irqrestore(&info->lock,flags);
5109
5110 timeout=100;
5111 while( timeout-- && !info->irq_occurred ) {
5112 msleep_interruptible(10);
5113 }
5114
5115 spin_lock_irqsave(&info->lock,flags);
5116 reset_port(info);
5117 spin_unlock_irqrestore(&info->lock,flags);
5118
5119 return info->irq_occurred;
5120 }
5121
5122 /* initialize individual SCA device (2 ports)
5123 */
5124 static bool sca_init(SLMP_INFO *info)
5125 {
5126 /* set wait controller to single mem partition (low), no wait states */
5127 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5128 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5129 write_reg(info, WCRL, 0); /* wait controller low range */
5130 write_reg(info, WCRM, 0); /* wait controller mid range */
5131 write_reg(info, WCRH, 0); /* wait controller high range */
5132
5133 /* DPCR, DMA Priority Control
5134 *
5135 * 07..05 Not used, must be 0
5136 * 04 BRC, bus release condition: 0=all transfers complete
5137 * 03 CCC, channel change condition: 0=every cycle
5138 * 02..00 PR<2..0>, priority 100=round robin
5139 *
5140 * 00000100 = 0x04
5141 */
5142 write_reg(info, DPCR, dma_priority);
5143
5144 /* DMA Master Enable, BIT7: 1=enable all channels */
5145 write_reg(info, DMER, 0x80);
5146
5147 /* enable all interrupt classes */
5148 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5149 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5150 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5151
5152 /* ITCR, interrupt control register
5153 * 07 IPC, interrupt priority, 0=MSCI->DMA
5154 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5155 * 04 VOS, Vector Output, 0=unmodified vector
5156 * 03..00 Reserved, must be 0
5157 */
5158 write_reg(info, ITCR, 0);
5159
5160 return true;
5161 }
5162
5163 /* initialize adapter hardware
5164 */
5165 static bool init_adapter(SLMP_INFO *info)
5166 {
5167 int i;
5168
5169 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5170 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5171 u32 readval;
5172
5173 info->misc_ctrl_value |= BIT30;
5174 *MiscCtrl = info->misc_ctrl_value;
5175
5176 /*
5177 * Force at least 170ns delay before clearing
5178 * reset bit. Each read from LCR takes at least
5179 * 30ns so 10 times for 300ns to be safe.
5180 */
5181 for(i=0;i<10;i++)
5182 readval = *MiscCtrl;
5183
5184 info->misc_ctrl_value &= ~BIT30;
5185 *MiscCtrl = info->misc_ctrl_value;
5186
5187 /* init control reg (all DTRs off, all clksel=input) */
5188 info->ctrlreg_value = 0xaa;
5189 write_control_reg(info);
5190
5191 {
5192 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5193 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5194
5195 switch(read_ahead_count)
5196 {
5197 case 16:
5198 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5199 break;
5200 case 8:
5201 lcr1_brdr_value |= BIT5 + BIT4;
5202 break;
5203 case 4:
5204 lcr1_brdr_value |= BIT5 + BIT3;
5205 break;
5206 case 0:
5207 lcr1_brdr_value |= BIT5;
5208 break;
5209 }
5210
5211 *LCR1BRDR = lcr1_brdr_value;
5212 *MiscCtrl = misc_ctrl_value;
5213 }
5214
5215 sca_init(info->port_array[0]);
5216 sca_init(info->port_array[2]);
5217
5218 return true;
5219 }
5220
5221 /* Loopback an HDLC frame to test the hardware
5222 * interrupt and DMA functions.
5223 */
5224 static bool loopback_test(SLMP_INFO *info)
5225 {
5226 #define TESTFRAMESIZE 20
5227
5228 unsigned long timeout;
5229 u16 count = TESTFRAMESIZE;
5230 unsigned char buf[TESTFRAMESIZE];
5231 bool rc = false;
5232 unsigned long flags;
5233
5234 struct tty_struct *oldtty = info->port.tty;
5235 u32 speed = info->params.clock_speed;
5236
5237 info->params.clock_speed = 3686400;
5238 info->port.tty = NULL;
5239
5240 /* assume failure */
5241 info->init_error = DiagStatus_DmaFailure;
5242
5243 /* build and send transmit frame */
5244 for (count = 0; count < TESTFRAMESIZE;++count)
5245 buf[count] = (unsigned char)count;
5246
5247 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5248
5249 /* program hardware for HDLC and enabled receiver */
5250 spin_lock_irqsave(&info->lock,flags);
5251 hdlc_mode(info);
5252 enable_loopback(info,1);
5253 rx_start(info);
5254 info->tx_count = count;
5255 tx_load_dma_buffer(info,buf,count);
5256 tx_start(info);
5257 spin_unlock_irqrestore(&info->lock,flags);
5258
5259 /* wait for receive complete */
5260 /* Set a timeout for waiting for interrupt. */
5261 for ( timeout = 100; timeout; --timeout ) {
5262 msleep_interruptible(10);
5263
5264 if (rx_get_frame(info)) {
5265 rc = true;
5266 break;
5267 }
5268 }
5269
5270 /* verify received frame length and contents */
5271 if (rc &&
5272 ( info->tmp_rx_buf_count != count ||
5273 memcmp(buf, info->tmp_rx_buf,count))) {
5274 rc = false;
5275 }
5276
5277 spin_lock_irqsave(&info->lock,flags);
5278 reset_adapter(info);
5279 spin_unlock_irqrestore(&info->lock,flags);
5280
5281 info->params.clock_speed = speed;
5282 info->port.tty = oldtty;
5283
5284 return rc;
5285 }
5286
5287 /* Perform diagnostics on hardware
5288 */
5289 static int adapter_test( SLMP_INFO *info )
5290 {
5291 unsigned long flags;
5292 if ( debug_level >= DEBUG_LEVEL_INFO )
5293 printk( "%s(%d):Testing device %s\n",
5294 __FILE__,__LINE__,info->device_name );
5295
5296 spin_lock_irqsave(&info->lock,flags);
5297 init_adapter(info);
5298 spin_unlock_irqrestore(&info->lock,flags);
5299
5300 info->port_array[0]->port_count = 0;
5301
5302 if ( register_test(info->port_array[0]) &&
5303 register_test(info->port_array[1])) {
5304
5305 info->port_array[0]->port_count = 2;
5306
5307 if ( register_test(info->port_array[2]) &&
5308 register_test(info->port_array[3]) )
5309 info->port_array[0]->port_count += 2;
5310 }
5311 else {
5312 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5313 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5314 return -ENODEV;
5315 }
5316
5317 if ( !irq_test(info->port_array[0]) ||
5318 !irq_test(info->port_array[1]) ||
5319 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5320 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5321 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5322 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5323 return -ENODEV;
5324 }
5325
5326 if (!loopback_test(info->port_array[0]) ||
5327 !loopback_test(info->port_array[1]) ||
5328 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5329 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5330 printk( "%s(%d):DMA test failure for device %s\n",
5331 __FILE__,__LINE__,info->device_name);
5332 return -ENODEV;
5333 }
5334
5335 if ( debug_level >= DEBUG_LEVEL_INFO )
5336 printk( "%s(%d):device %s passed diagnostics\n",
5337 __FILE__,__LINE__,info->device_name );
5338
5339 info->port_array[0]->init_error = 0;
5340 info->port_array[1]->init_error = 0;
5341 if ( info->port_count > 2 ) {
5342 info->port_array[2]->init_error = 0;
5343 info->port_array[3]->init_error = 0;
5344 }
5345
5346 return 0;
5347 }
5348
5349 /* Test the shared memory on a PCI adapter.
5350 */
5351 static bool memory_test(SLMP_INFO *info)
5352 {
5353 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5354 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5355 unsigned long count = ARRAY_SIZE(testval);
5356 unsigned long i;
5357 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5358 unsigned long * addr = (unsigned long *)info->memory_base;
5359
5360 /* Test data lines with test pattern at one location. */
5361
5362 for ( i = 0 ; i < count ; i++ ) {
5363 *addr = testval[i];
5364 if ( *addr != testval[i] )
5365 return false;
5366 }
5367
5368 /* Test address lines with incrementing pattern over */
5369 /* entire address range. */
5370
5371 for ( i = 0 ; i < limit ; i++ ) {
5372 *addr = i * 4;
5373 addr++;
5374 }
5375
5376 addr = (unsigned long *)info->memory_base;
5377
5378 for ( i = 0 ; i < limit ; i++ ) {
5379 if ( *addr != i * 4 )
5380 return false;
5381 addr++;
5382 }
5383
5384 memset( info->memory_base, 0, SCA_MEM_SIZE );
5385 return true;
5386 }
5387
5388 /* Load data into PCI adapter shared memory.
5389 *
5390 * The PCI9050 releases control of the local bus
5391 * after completing the current read or write operation.
5392 *
5393 * While the PCI9050 write FIFO not empty, the
5394 * PCI9050 treats all of the writes as a single transaction
5395 * and does not release the bus. This causes DMA latency problems
5396 * at high speeds when copying large data blocks to the shared memory.
5397 *
5398 * This function breaks a write into multiple transations by
5399 * interleaving a read which flushes the write FIFO and 'completes'
5400 * the write transation. This allows any pending DMA request to gain control
5401 * of the local bus in a timely fasion.
5402 */
5403 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5404 {
5405 /* A load interval of 16 allows for 4 32-bit writes at */
5406 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5407
5408 unsigned short interval = count / sca_pci_load_interval;
5409 unsigned short i;
5410
5411 for ( i = 0 ; i < interval ; i++ )
5412 {
5413 memcpy(dest, src, sca_pci_load_interval);
5414 read_status_reg(info);
5415 dest += sca_pci_load_interval;
5416 src += sca_pci_load_interval;
5417 }
5418
5419 memcpy(dest, src, count % sca_pci_load_interval);
5420 }
5421
5422 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5423 {
5424 int i;
5425 int linecount;
5426 if (xmit)
5427 printk("%s tx data:\n",info->device_name);
5428 else
5429 printk("%s rx data:\n",info->device_name);
5430
5431 while(count) {
5432 if (count > 16)
5433 linecount = 16;
5434 else
5435 linecount = count;
5436
5437 for(i=0;i<linecount;i++)
5438 printk("%02X ",(unsigned char)data[i]);
5439 for(;i<17;i++)
5440 printk(" ");
5441 for(i=0;i<linecount;i++) {
5442 if (data[i]>=040 && data[i]<=0176)
5443 printk("%c",data[i]);
5444 else
5445 printk(".");
5446 }
5447 printk("\n");
5448
5449 data += linecount;
5450 count -= linecount;
5451 }
5452 } /* end of trace_block() */
5453
5454 /* called when HDLC frame times out
5455 * update stats and do tx completion processing
5456 */
5457 static void tx_timeout(struct timer_list *t)
5458 {
5459 SLMP_INFO *info = from_timer(info, t, tx_timer);
5460 unsigned long flags;
5461
5462 if ( debug_level >= DEBUG_LEVEL_INFO )
5463 printk( "%s(%d):%s tx_timeout()\n",
5464 __FILE__,__LINE__,info->device_name);
5465 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5466 info->icount.txtimeout++;
5467 }
5468 spin_lock_irqsave(&info->lock,flags);
5469 info->tx_active = false;
5470 info->tx_count = info->tx_put = info->tx_get = 0;
5471
5472 spin_unlock_irqrestore(&info->lock,flags);
5473
5474 #if SYNCLINK_GENERIC_HDLC
5475 if (info->netcount)
5476 hdlcdev_tx_done(info);
5477 else
5478 #endif
5479 bh_transmit(info);
5480 }
5481
5482 /* called to periodically check the DSR/RI modem signal input status
5483 */
5484 static void status_timeout(struct timer_list *t)
5485 {
5486 u16 status = 0;
5487 SLMP_INFO *info = from_timer(info, t, status_timer);
5488 unsigned long flags;
5489 unsigned char delta;
5490
5491
5492 spin_lock_irqsave(&info->lock,flags);
5493 get_signals(info);
5494 spin_unlock_irqrestore(&info->lock,flags);
5495
5496 /* check for DSR/RI state change */
5497
5498 delta = info->old_signals ^ info->serial_signals;
5499 info->old_signals = info->serial_signals;
5500
5501 if (delta & SerialSignal_DSR)
5502 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5503
5504 if (delta & SerialSignal_RI)
5505 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5506
5507 if (delta & SerialSignal_DCD)
5508 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5509
5510 if (delta & SerialSignal_CTS)
5511 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5512
5513 if (status)
5514 isr_io_pin(info,status);
5515
5516 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5517 }
5518
5519
5520 /* Register Access Routines -
5521 * All registers are memory mapped
5522 */
5523 #define CALC_REGADDR() \
5524 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5525 if (info->port_num > 1) \
5526 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5527 if ( info->port_num & 1) { \
5528 if (Addr > 0x7f) \
5529 RegAddr += 0x40; /* DMA access */ \
5530 else if (Addr > 0x1f && Addr < 0x60) \
5531 RegAddr += 0x20; /* MSCI access */ \
5532 }
5533
5534
5535 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5536 {
5537 CALC_REGADDR();
5538 return *RegAddr;
5539 }
5540 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5541 {
5542 CALC_REGADDR();
5543 *RegAddr = Value;
5544 }
5545
5546 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5547 {
5548 CALC_REGADDR();
5549 return *((u16 *)RegAddr);
5550 }
5551
5552 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5553 {
5554 CALC_REGADDR();
5555 *((u16 *)RegAddr) = Value;
5556 }
5557
5558 static unsigned char read_status_reg(SLMP_INFO * info)
5559 {
5560 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5561 return *RegAddr;
5562 }
5563
5564 static void write_control_reg(SLMP_INFO * info)
5565 {
5566 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5567 *RegAddr = info->port_array[0]->ctrlreg_value;
5568 }
5569
5570
5571 static int synclinkmp_init_one (struct pci_dev *dev,
5572 const struct pci_device_id *ent)
5573 {
5574 if (pci_enable_device(dev)) {
5575 printk("error enabling pci device %p\n", dev);
5576 return -EIO;
5577 }
5578 return device_init( ++synclinkmp_adapter_count, dev );
5579 }
5580
5581 static void synclinkmp_remove_one (struct pci_dev *dev)
5582 {
5583 }
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