drivers/usb/chipidea/ci.h

   1 /*
   2  * ci.h - common structures, functions, and macros of the ChipIdea driver
   3  *
   4  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
   5  *
   6  * Author: David Lopo
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __DRIVERS_USB_CHIPIDEA_CI_H
  14 #define __DRIVERS_USB_CHIPIDEA_CI_H
  15
  16 #include <linux/list.h>
  17 #include <linux/irqreturn.h>
  18 #include <linux/usb.h>
  19 #include <linux/usb/gadget.h>
  20 #include <linux/usb/otg-fsm.h>
  21 #include <linux/usb/otg.h>
  22 #include <linux/ulpi/interface.h>
  23
  24 /******************************************************************************
  25  * DEFINE
  26  *****************************************************************************/
  27 #define TD_PAGE_COUNT      5
  28 #define CI_HDRC_PAGE_SIZE  4096ul /* page size for TD's */
  29 #define ENDPT_MAX          32
  30
  31 /******************************************************************************
  32  * REGISTERS
  33  *****************************************************************************/
  34 /* Identification Registers */
  35 #define ID_ID                           0x0
  36 #define ID_HWGENERAL                    0x4
  37 #define ID_HWHOST                       0x8
  38 #define ID_HWDEVICE                     0xc
  39 #define ID_HWTXBUF                      0x10
  40 #define ID_HWRXBUF                      0x14
  41 #define ID_SBUSCFG                      0x90
  42
  43 /* register indices */
  44 enum ci_hw_regs {
  45         CAP_CAPLENGTH,
  46         CAP_HCCPARAMS,
  47         CAP_DCCPARAMS,
  48         CAP_TESTMODE,
  49         CAP_LAST = CAP_TESTMODE,
  50         OP_USBCMD,
  51         OP_USBSTS,
  52         OP_USBINTR,
  53         OP_DEVICEADDR,
  54         OP_ENDPTLISTADDR,
  55         OP_TTCTRL,
  56         OP_BURSTSIZE,
  57         OP_ULPI_VIEWPORT,
  58         OP_PORTSC,
  59         OP_DEVLC,
  60         OP_OTGSC,
  61         OP_USBMODE,
  62         OP_ENDPTSETUPSTAT,
  63         OP_ENDPTPRIME,
  64         OP_ENDPTFLUSH,
  65         OP_ENDPTSTAT,
  66         OP_ENDPTCOMPLETE,
  67         OP_ENDPTCTRL,
  68         /* endptctrl1..15 follow */
  69         OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
  70 };
  71
  72 /******************************************************************************
  73  * STRUCTURES
  74  *****************************************************************************/
  75 /**
  76  * struct ci_hw_ep - endpoint representation
  77  * @ep: endpoint structure for gadget drivers
  78  * @dir: endpoint direction (TX/RX)
  79  * @num: endpoint number
  80  * @type: endpoint type
  81  * @name: string description of the endpoint
  82  * @qh: queue head for this endpoint
  83  * @wedge: is the endpoint wedged
  84  * @ci: pointer to the controller
  85  * @lock: pointer to controller's spinlock
  86  * @td_pool: pointer to controller's TD pool
  87  */
  88 struct ci_hw_ep {
  89         struct usb_ep                           ep;
  90         u8                                      dir;
  91         u8                                      num;
  92         u8                                      type;
  93         char                                    name[16];
  94         struct {
  95                 struct list_head        queue;
  96                 struct ci_hw_qh         *ptr;
  97                 dma_addr_t              dma;
  98         }                                       qh;
  99         int                                     wedge;
 100
 101         /* global resources */
 102         struct ci_hdrc                          *ci;
 103         spinlock_t                              *lock;
 104         struct dma_pool                         *td_pool;
 105         struct td_node                          *pending_td;
 106 };
 107
 108 enum ci_role {
 109         CI_ROLE_HOST = 0,
 110         CI_ROLE_GADGET,
 111         CI_ROLE_END,
 112 };
 113
 114 enum ci_revision {
 115         CI_REVISION_1X = 10,    /* Revision 1.x */
 116         CI_REVISION_20 = 20, /* Revision 2.0 */
 117         CI_REVISION_21, /* Revision 2.1 */
 118         CI_REVISION_22, /* Revision 2.2 */
 119         CI_REVISION_23, /* Revision 2.3 */
 120         CI_REVISION_24, /* Revision 2.4 */
 121         CI_REVISION_25, /* Revision 2.5 */
 122         CI_REVISION_25_PLUS, /* Revision above than 2.5 */
 123         CI_REVISION_UNKNOWN = 99, /* Unknown Revision */
 124 };
 125
 126 /**
 127  * struct ci_role_driver - host/gadget role driver
 128  * @start: start this role
 129  * @stop: stop this role
 130  * @irq: irq handler for this role
 131  * @name: role name string (host/gadget)
 132  */
 133 struct ci_role_driver {
 134         int             (*start)(struct ci_hdrc *);
 135         void            (*stop)(struct ci_hdrc *);
 136         irqreturn_t     (*irq)(struct ci_hdrc *);
 137         const char      *name;
 138 };
 139
 140 /**
 141  * struct hw_bank - hardware register mapping representation
 142  * @lpm: set if the device is LPM capable
 143  * @phys: physical address of the controller's registers
 144  * @abs: absolute address of the beginning of register window
 145  * @cap: capability registers
 146  * @op: operational registers
 147  * @size: size of the register window
 148  * @regmap: register lookup table
 149  */
 150 struct hw_bank {
 151         unsigned        lpm;
 152         resource_size_t phys;
 153         void __iomem    *abs;
 154         void __iomem    *cap;
 155         void __iomem    *op;
 156         size_t          size;
 157         void __iomem    *regmap[OP_LAST + 1];
 158 };
 159
 160 /**
 161  * struct ci_hdrc - chipidea device representation
 162  * @dev: pointer to parent device
 163  * @lock: access synchronization
 164  * @hw_bank: hardware register mapping
 165  * @irq: IRQ number
 166  * @roles: array of supported roles for this controller
 167  * @role: current role
 168  * @is_otg: if the device is otg-capable
 169  * @fsm: otg finite state machine
 170  * @otg_fsm_hrtimer: hrtimer for otg fsm timers
 171  * @hr_timeouts: time out list for active otg fsm timers
 172  * @enabled_otg_timer_bits: bits of enabled otg timers
 173  * @next_otg_timer: next nearest enabled timer to be expired
 174  * @work: work for role changing
 175  * @wq: workqueue thread
 176  * @qh_pool: allocation pool for queue heads
 177  * @td_pool: allocation pool for transfer descriptors
 178  * @gadget: device side representation for peripheral controller
 179  * @driver: gadget driver
 180  * @hw_ep_max: total number of endpoints supported by hardware
 181  * @ci_hw_ep: array of endpoints
 182  * @ep0_dir: ep0 direction
 183  * @ep0out: pointer to ep0 OUT endpoint
 184  * @ep0in: pointer to ep0 IN endpoint
 185  * @status: ep0 status request
 186  * @setaddr: if we should set the address on status completion
 187  * @address: usb address received from the host
 188  * @remote_wakeup: host-enabled remote wakeup
 189  * @suspended: suspended by host
 190  * @test_mode: the selected test mode
 191  * @platdata: platform specific information supplied by parent device
 192  * @vbus_active: is VBUS active
 193  * @ulpi: pointer to ULPI device, if any
 194  * @ulpi_ops: ULPI read/write ops for this device
 195  * @phy: pointer to PHY, if any
 196  * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework
 197  * @hcd: pointer to usb_hcd for ehci host driver
 198  * @debugfs: root dentry for this controller in debugfs
 199  * @id_event: indicates there is an id event, and handled at ci_otg_work
 200  * @b_sess_valid_event: indicates there is a vbus event, and handled
 201  * at ci_otg_work
 202  * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
 203  * @supports_runtime_pm: if runtime pm is supported
 204  * @in_lpm: if the core in low power mode
 205  * @wakeup_int: if wakeup interrupt occur
 206  * @rev: The revision number for controller
 207  */
 208 struct ci_hdrc {
 209         struct device                   *dev;
 210         spinlock_t                      lock;
 211         struct hw_bank                  hw_bank;
 212         int                             irq;
 213         struct ci_role_driver           *roles[CI_ROLE_END];
 214         enum ci_role                    role;
 215         bool                            is_otg;
 216         struct usb_otg                  otg;
 217         struct otg_fsm                  fsm;
 218         struct hrtimer                  otg_fsm_hrtimer;
 219         ktime_t                         hr_timeouts[NUM_OTG_FSM_TIMERS];
 220         unsigned                        enabled_otg_timer_bits;
 221         enum otg_fsm_timer              next_otg_timer;
 222         struct work_struct              work;
 223         struct workqueue_struct         *wq;
 224
 225         struct dma_pool                 *qh_pool;
 226         struct dma_pool                 *td_pool;
 227
 228         struct usb_gadget               gadget;
 229         struct usb_gadget_driver        *driver;
 230         unsigned                        hw_ep_max;
 231         struct ci_hw_ep                 ci_hw_ep[ENDPT_MAX];
 232         u32                             ep0_dir;
 233         struct ci_hw_ep                 *ep0out, *ep0in;
 234
 235         struct usb_request              *status;
 236         bool                            setaddr;
 237         u8                              address;
 238         u8                              remote_wakeup;
 239         u8                              suspended;
 240         u8                              test_mode;
 241
 242         struct ci_hdrc_platform_data    *platdata;
 243         int                             vbus_active;
 244 #ifdef CONFIG_USB_CHIPIDEA_ULPI
 245         struct ulpi                     *ulpi;
 246         struct ulpi_ops                 ulpi_ops;
 247 #endif
 248         struct phy                      *phy;
 249         /* old usb_phy interface */
 250         struct usb_phy                  *usb_phy;
 251         struct usb_hcd                  *hcd;
 252         struct dentry                   *debugfs;
 253         bool                            id_event;
 254         bool                            b_sess_valid_event;
 255         bool                            imx28_write_fix;
 256         bool                            supports_runtime_pm;
 257         bool                            in_lpm;
 258         bool                            wakeup_int;
 259         enum ci_revision                rev;
 260 };
 261
 262 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
 263 {
 264         BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
 265         return ci->roles[ci->role];
 266 }
 267
 268 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
 269 {
 270         int ret;
 271
 272         if (role >= CI_ROLE_END)
 273                 return -EINVAL;
 274
 275         if (!ci->roles[role])
 276                 return -ENXIO;
 277
 278         ret = ci->roles[role]->start(ci);
 279         if (!ret)
 280                 ci->role = role;
 281         return ret;
 282 }
 283
 284 static inline void ci_role_stop(struct ci_hdrc *ci)
 285 {
 286         enum ci_role role = ci->role;
 287
 288         if (role == CI_ROLE_END)
 289                 return;
 290
 291         ci->role = CI_ROLE_END;
 292
 293         ci->roles[role]->stop(ci);
 294 }
 295
 296 /**
 297  * hw_read_id_reg: reads from a identification register
 298  * @ci: the controller
 299  * @offset: offset from the beginning of identification registers region
 300  * @mask: bitfield mask
 301  *
 302  * This function returns register contents
 303  */
 304 static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
 305 {
 306         return ioread32(ci->hw_bank.abs + offset) & mask;
 307 }
 308
 309 /**
 310  * hw_write_id_reg: writes to a identification register
 311  * @ci: the controller
 312  * @offset: offset from the beginning of identification registers region
 313  * @mask: bitfield mask
 314  * @data: new value
 315  */
 316 static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
 317                             u32 mask, u32 data)
 318 {
 319         if (~mask)
 320                 data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
 321                         | (data & mask);
 322
 323         iowrite32(data, ci->hw_bank.abs + offset);
 324 }
 325
 326 /**
 327  * hw_read: reads from a hw register
 328  * @ci: the controller
 329  * @reg:  register index
 330  * @mask: bitfield mask
 331  *
 332  * This function returns register contents
 333  */
 334 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
 335 {
 336         return ioread32(ci->hw_bank.regmap[reg]) & mask;
 337 }
 338
 339 #ifdef CONFIG_SOC_IMX28
 340 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
 341 {
 342         __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
 343 }
 344 #else
 345 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
 346 {
 347 }
 348 #endif
 349
 350 static inline void __hw_write(struct ci_hdrc *ci, u32 val,
 351                 void __iomem *addr)
 352 {
 353         if (ci->imx28_write_fix)
 354                 imx28_ci_writel(val, addr);
 355         else
 356                 iowrite32(val, addr);
 357 }
 358
 359 /**
 360  * hw_write: writes to a hw register
 361  * @ci: the controller
 362  * @reg:  register index
 363  * @mask: bitfield mask
 364  * @data: new value
 365  */
 366 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
 367                             u32 mask, u32 data)
 368 {
 369         if (~mask)
 370                 data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
 371                         | (data & mask);
 372
 373         __hw_write(ci, data, ci->hw_bank.regmap[reg]);
 374 }
 375
 376 /**
 377  * hw_test_and_clear: tests & clears a hw register
 378  * @ci: the controller
 379  * @reg:  register index
 380  * @mask: bitfield mask
 381  *
 382  * This function returns register contents
 383  */
 384 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
 385                                     u32 mask)
 386 {
 387         u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
 388
 389         __hw_write(ci, val, ci->hw_bank.regmap[reg]);
 390         return val;
 391 }
 392
 393 /**
 394  * hw_test_and_write: tests & writes a hw register
 395  * @ci: the controller
 396  * @reg:  register index
 397  * @mask: bitfield mask
 398  * @data: new value
 399  *
 400  * This function returns register contents
 401  */
 402 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
 403                                     u32 mask, u32 data)
 404 {
 405         u32 val = hw_read(ci, reg, ~0);
 406
 407         hw_write(ci, reg, mask, data);
 408         return (val & mask) >> __ffs(mask);
 409 }
 410
 411 /**
 412  * ci_otg_is_fsm_mode: runtime check if otg controller
 413  * is in otg fsm mode.
 414  *
 415  * @ci: chipidea device
 416  */
 417 static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
 418 {
 419 #ifdef CONFIG_USB_OTG_FSM
 420         struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps;
 421
 422         return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
 423                 ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support ||
 424                 otg_caps->hnp_support || otg_caps->adp_support);
 425 #else
 426         return false;
 427 #endif
 428 }
 429
 430 #if IS_ENABLED(CONFIG_USB_CHIPIDEA_ULPI)
 431 int ci_ulpi_init(struct ci_hdrc *ci);
 432 void ci_ulpi_exit(struct ci_hdrc *ci);
 433 int ci_ulpi_resume(struct ci_hdrc *ci);
 434 #else
 435 static inline int ci_ulpi_init(struct ci_hdrc *ci) { return 0; }
 436 static inline void ci_ulpi_exit(struct ci_hdrc *ci) { }
 437 static inline int ci_ulpi_resume(struct ci_hdrc *ci) { return 0; }
 438 #endif
 439
 440 u32 hw_read_intr_enable(struct ci_hdrc *ci);
 441
 442 u32 hw_read_intr_status(struct ci_hdrc *ci);
 443
 444 int hw_device_reset(struct ci_hdrc *ci);
 445
 446 int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
 447
 448 u8 hw_port_test_get(struct ci_hdrc *ci);
 449
 450 void hw_phymode_configure(struct ci_hdrc *ci);
 451
 452 void ci_platform_configure(struct ci_hdrc *ci);
 453
 454 int dbg_create_files(struct ci_hdrc *ci);
 455
 456 void dbg_remove_files(struct ci_hdrc *ci);
 457 #endif  /* __DRIVERS_USB_CHIPIDEA_CI_H */