1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * core.h - DesignWare HS OTG Controller common declarations
5 * Copyright (C) 2004-2013 Synopsys, Inc.
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38 #ifndef __DWC2_CORE_H__
39 #define __DWC2_CORE_H__
41 #include <linux/phy/phy.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/usb/gadget.h>
44 #include <linux/usb/otg.h>
45 #include <linux/usb/phy.h>
49 * Suggested defines for tracers:
50 * - no_printk: Disable tracing
51 * - pr_info: Print this info to the console
52 * - trace_printk: Print this info to trace buffer (good for verbose logging)
55 #define DWC2_TRACE_SCHEDULER no_printk
56 #define DWC2_TRACE_SCHEDULER_VB no_printk
58 /* Detailed scheduler tracing, but won't overwhelm console */
59 #define dwc2_sch_dbg(hsotg, fmt, ...) \
60 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \
61 dev_name(hsotg->dev), ##__VA_ARGS__)
63 /* Verbose scheduler tracing */
64 #define dwc2_sch_vdbg(hsotg, fmt, ...) \
65 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \
66 dev_name(hsotg->dev), ##__VA_ARGS__)
70 * There are some MIPS machines that can run in either big-endian
71 * or little-endian mode and that use the dwc2 register without
72 * a byteswap in both ways.
73 * Unlike other architectures, MIPS apparently does not require a
74 * barrier before the __raw_writel() to synchronize with DMA but does
75 * require the barrier after the __raw_writel() to serialize a set of
76 * writes. This set of operations was added specifically for MIPS and
77 * should only be used there.
79 static inline u32
dwc2_readl(const void __iomem
*addr
)
81 u32 value
= __raw_readl(addr
);
83 /* In order to preserve endianness __raw_* operation is used. Therefore
84 * a barrier is needed to ensure IO access is not re-ordered across
91 static inline void dwc2_writel(u32 value
, void __iomem
*addr
)
93 __raw_writel(value
, addr
);
96 * In order to preserve endianness __raw_* operation is used. Therefore
97 * a barrier is needed to ensure IO access is not re-ordered across
101 #ifdef DWC2_LOG_WRITES
102 pr_info("INFO:: wrote %08x to %p\n", value
, addr
);
106 /* Normal architectures just use readl/write */
107 static inline u32
dwc2_readl(const void __iomem
*addr
)
112 static inline void dwc2_writel(u32 value
, void __iomem
*addr
)
116 #ifdef DWC2_LOG_WRITES
117 pr_info("info:: wrote %08x to %p\n", value
, addr
);
122 /* Maximum number of Endpoints/HostChannels */
123 #define MAX_EPS_CHANNELS 16
125 /* dwc2-hsotg declarations */
126 static const char * const dwc2_hsotg_supply_names
[] = {
127 "vusb_d", /* digital USB supply, 1.2V */
128 "vusb_a", /* analog USB supply, 1.1V */
131 #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names)
136 * Unfortunately there seems to be a limit of the amount of data that can
137 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
138 * packets (which practically means 1 packet and 63 bytes of data) when the
141 * This means if we are wanting to move >127 bytes of data, we need to
142 * split the transactions up, but just doing one packet at a time does
143 * not work (this may be an implicit DATA0 PID on first packet of the
144 * transaction) and doing 2 packets is outside the controller's limits.
146 * If we try to lower the MPS size for EP0, then no transfers work properly
147 * for EP0, and the system will fail basic enumeration. As no cause for this
148 * has currently been found, we cannot support any large IN transfers for
151 #define EP0_MPS_LIMIT 64
154 struct dwc2_hsotg_req
;
157 * struct dwc2_hsotg_ep - driver endpoint definition.
158 * @ep: The gadget layer representation of the endpoint.
159 * @name: The driver generated name for the endpoint.
160 * @queue: Queue of requests for this endpoint.
161 * @parent: Reference back to the parent device structure.
162 * @req: The current request that the endpoint is processing. This is
163 * used to indicate an request has been loaded onto the endpoint
164 * and has yet to be completed (maybe due to data move, or simply
165 * awaiting an ack from the core all the data has been completed).
166 * @debugfs: File entry for debugfs file for this endpoint.
167 * @lock: State lock to protect contents of endpoint.
168 * @dir_in: Set to true if this endpoint is of the IN direction, which
169 * means that it is sending data to the Host.
170 * @index: The index for the endpoint registers.
171 * @mc: Multi Count - number of transactions per microframe
172 * @interval - Interval for periodic endpoints, in frames or microframes.
173 * @name: The name array passed to the USB core.
174 * @halted: Set if the endpoint has been halted.
175 * @periodic: Set if this is a periodic ep, such as Interrupt
176 * @isochronous: Set if this is a isochronous ep
177 * @send_zlp: Set if we need to send a zero-length packet.
178 * @desc_list_dma: The DMA address of descriptor chain currently in use.
179 * @desc_list: Pointer to descriptor DMA chain head currently in use.
180 * @desc_count: Count of entries within the DMA descriptor chain of EP.
181 * @isoc_chain_num: Number of ISOC chain currently in use - either 0 or 1.
182 * @next_desc: index of next free descriptor in the ISOC chain under SW control.
183 * @total_data: The total number of data bytes done.
184 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
185 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
186 * @last_load: The offset of data for the last start of request.
187 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
188 * @target_frame: Targeted frame num to setup next ISOC transfer
189 * @frame_overrun: Indicates SOF number overrun in DSTS
191 * This is the driver's state for each registered enpoint, allowing it
192 * to keep track of transactions that need doing. Each endpoint has a
193 * lock to protect the state, to try and avoid using an overall lock
194 * for the host controller as much as possible.
196 * For periodic IN endpoints, we have fifo_size and fifo_load to try
197 * and keep track of the amount of data in the periodic FIFO for each
198 * of these as we don't have a status register that tells us how much
199 * is in each of them. (note, this may actually be useless information
200 * as in shared-fifo mode periodic in acts like a single-frame packet
201 * buffer than a fifo)
203 struct dwc2_hsotg_ep
{
205 struct list_head queue
;
206 struct dwc2_hsotg
*parent
;
207 struct dwc2_hsotg_req
*req
;
208 struct dentry
*debugfs
;
210 unsigned long total_data
;
211 unsigned int size_loaded
;
212 unsigned int last_load
;
213 unsigned int fifo_load
;
214 unsigned short fifo_size
;
215 unsigned short fifo_index
;
217 unsigned char dir_in
;
220 unsigned char interval
;
222 unsigned int halted
:1;
223 unsigned int periodic
:1;
224 unsigned int isochronous
:1;
225 unsigned int send_zlp
:1;
226 unsigned int target_frame
;
227 #define TARGET_FRAME_INITIAL 0xFFFFFFFF
230 dma_addr_t desc_list_dma
;
231 struct dwc2_dma_desc
*desc_list
;
234 unsigned char isoc_chain_num
;
235 unsigned int next_desc
;
241 * struct dwc2_hsotg_req - data transfer request
242 * @req: The USB gadget request
243 * @queue: The list of requests for the endpoint this is queued for.
244 * @saved_req_buf: variable to save req.buf when bounce buffers are used.
246 struct dwc2_hsotg_req
{
247 struct usb_request req
;
248 struct list_head queue
;
252 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
253 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
254 #define call_gadget(_hs, _entry) \
256 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
257 (_hs)->driver && (_hs)->driver->_entry) { \
258 spin_unlock(&_hs->lock); \
259 (_hs)->driver->_entry(&(_hs)->gadget); \
260 spin_lock(&_hs->lock); \
264 #define call_gadget(_hs, _entry) do {} while (0)
268 struct dwc2_host_chan
;
272 DWC2_L0
, /* On state */
273 DWC2_L1
, /* LPM sleep state */
274 DWC2_L2
, /* USB suspend state */
275 DWC2_L3
, /* Off state */
278 /* Gadget ep0 states */
279 enum dwc2_ep0_state
{
288 * struct dwc2_core_params - Parameters for configuring the core
290 * @otg_cap: Specifies the OTG capabilities.
291 * 0 - HNP and SRP capable
292 * 1 - SRP Only capable
293 * 2 - No HNP/SRP capable (always available)
294 * Defaults to best available option (0, 1, then 2)
295 * @host_dma: Specifies whether to use slave or DMA mode for accessing
296 * the data FIFOs. The driver will automatically detect the
297 * value for this parameter if none is specified.
298 * 0 - Slave (always available)
299 * 1 - DMA (default, if available)
300 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
301 * address DMA mode or descriptor DMA mode for accessing
302 * the data FIFOs. The driver will automatically detect the
303 * value for this if none is specified.
305 * 1 - Descriptor DMA (default, if available)
306 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
307 * address DMA mode or descriptor DMA mode for accessing
308 * the data FIFOs in Full Speed mode only. The driver
309 * will automatically detect the value for this if none is
312 * 1 - Descriptor DMA in FS (default, if available)
313 * @speed: Specifies the maximum speed of operation in host and
314 * device mode. The actual speed depends on the speed of
315 * the attached device and the value of phy_type.
317 * (default when phy_type is UTMI+ or ULPI)
319 * (default when phy_type is Full Speed)
320 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
321 * 1 - Allow dynamic FIFO sizing (default, if available)
322 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
323 * are enabled for non-periodic IN endpoints in device
325 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
326 * dynamic FIFO sizing is enabled
328 * Actual maximum value is autodetected and also
330 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
331 * in host mode when dynamic FIFO sizing is enabled
333 * Actual maximum value is autodetected and also
335 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
336 * host mode when dynamic FIFO sizing is enabled
338 * Actual maximum value is autodetected and also
340 * @max_transfer_size: The maximum transfer size supported, in bytes
342 * Actual maximum value is autodetected and also
344 * @max_packet_count: The maximum number of packets in a transfer
346 * Actual maximum value is autodetected and also
348 * @host_channels: The number of host channel registers to use
350 * Actual maximum value is autodetected and also
352 * @phy_type: Specifies the type of PHY interface to use. By default,
353 * the driver will automatically detect the phy_type.
357 * Defaults to best available option (2, 1, then 0)
358 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
359 * is applicable for a phy_type of UTMI+ or ULPI. (For a
360 * ULPI phy_type, this parameter indicates the data width
361 * between the MAC and the ULPI Wrapper.) Also, this
362 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
363 * parameter was set to "8 and 16 bits", meaning that the
364 * core has been configured to work at either data path
366 * 8 or 16 (default 16 if available)
367 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
368 * data rate. This parameter is only applicable if phy_type
370 * 0 - single data rate ULPI interface with 8 bit wide
372 * 1 - double data rate ULPI interface with 4 bit wide
374 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
375 * external supply to drive the VBus
376 * 0 - Internal supply (default)
377 * 1 - External supply
378 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
379 * speed PHY. This parameter is only applicable if phy_type
383 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
386 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
387 * when attached to a Full Speed or Low Speed device in
389 * 0 - Don't support low power mode (default)
390 * 1 - Support low power mode
391 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
392 * when connected to a Low Speed device in host
393 * mode. This parameter is applicable only if
394 * host_support_fs_ls_low_power is enabled.
396 * (default when phy_type is UTMI+ or ULPI)
398 * (default when phy_type is Full Speed)
399 * @oc_disable: Flag to disable overcurrent condition.
400 * 0 - Allow overcurrent condition to get detected
401 * 1 - Disable overcurrent condtion to get detected
402 * @ts_dline: Enable Term Select Dline pulsing
405 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
406 * 0 - No (default for core < 2.92a)
407 * 1 - Yes (default for core >= 2.92a)
408 * @ahbcfg: This field allows the default value of the GAHBCFG
409 * register to be overridden
410 * -1 - GAHBCFG value will be set to 0x06
412 * all others - GAHBCFG value will be overridden with
414 * Not all bits can be controlled like this, the
415 * bits defined by GAHBCFG_CTRL_MASK are controlled
416 * by the driver and are ignored in this
417 * configuration value.
418 * @uframe_sched: True to enable the microframe scheduler
419 * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
420 * Disable CONIDSTSCHNG controller interrupt in such
424 * @hibernation: Specifies whether the controller support hibernation.
425 * If hibernation is enabled, the controller will enter
426 * hibernation in both peripheral and host mode when
430 * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO
432 * 0 - Deactivate the transceiver (default)
433 * 1 - Activate the transceiver
434 * @g_dma: Enables gadget dma usage (default: autodetect).
435 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect).
436 * @g_rx_fifo_size: The periodic rx fifo size for the device, in
437 * DWORDS from 16-32768 (default: 2048 if
438 * possible, otherwise autodetect).
439 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in
440 * DWORDS from 16-32768 (default: 1024 if
441 * possible, otherwise autodetect).
442 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo
443 * mode. Each value corresponds to one EP
444 * starting from EP1 (max 15 values). Sizes are
445 * in DWORDS with possible values from from
446 * 16-32768 (default: 256, 256, 256, 256, 768,
447 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0).
448 * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL
449 * while full&low speed device connect. And change speed
450 * back to DWC2_SPEED_PARAM_HIGH while device is gone.
454 * The following parameters may be specified when starting the module. These
455 * parameters define how the DWC_otg controller should be configured. A
456 * value of -1 (or any other out of range value) for any parameter means
457 * to read the value from hardware (if possible) or use the builtin
458 * default described above.
460 struct dwc2_core_params
{
462 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
463 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
464 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
467 #define DWC2_PHY_TYPE_PARAM_FS 0
468 #define DWC2_PHY_TYPE_PARAM_UTMI 1
469 #define DWC2_PHY_TYPE_PARAM_ULPI 2
472 #define DWC2_SPEED_PARAM_HIGH 0
473 #define DWC2_SPEED_PARAM_FULL 1
474 #define DWC2_SPEED_PARAM_LOW 2
478 bool phy_ulpi_ext_vbus
;
479 bool enable_dynamic_fifo
;
480 bool en_multiple_tx_fifo
;
486 bool external_id_pin_ctl
;
488 bool activate_stm_fs_transceiver
;
489 u16 max_packet_count
;
490 u32 max_transfer_size
;
493 /* Host parameters */
495 bool dma_desc_enable
;
496 bool dma_desc_fs_enable
;
497 bool host_support_fs_ls_low_power
;
498 bool host_ls_low_power_phy_clk
;
502 u16 host_rx_fifo_size
;
503 u16 host_nperio_tx_fifo_size
;
504 u16 host_perio_tx_fifo_size
;
506 /* Gadget parameters */
510 u32 g_np_tx_fifo_size
;
511 u32 g_tx_fifo_size
[MAX_EPS_CHANNELS
];
513 bool change_speed_quirk
;
517 * struct dwc2_hw_params - Autodetected parameters.
519 * These parameters are the various parameters read from hardware
520 * registers during initialization. They typically contain the best
521 * supported or maximum value that can be configured in the
522 * corresponding dwc2_core_params value.
524 * The values that are not in dwc2_core_params are documented below.
526 * @op_mode Mode of Operation
527 * 0 - HNP- and SRP-Capable OTG (Host & Device)
528 * 1 - SRP-Capable OTG (Host & Device)
529 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
530 * 3 - SRP-Capable Device
532 * 5 - SRP-Capable Host
538 * @power_optimized Are power optimizations enabled?
539 * @num_dev_ep Number of device endpoints available
540 * @num_dev_perio_in_ep Number of device periodic IN endpoints
542 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue
545 * @host_perio_tx_q_depth
546 * Host Mode Periodic Request Queue Depth
549 * Non-Periodic Request Queue Depth
551 * @hs_phy_type High-speed PHY interface type
552 * 0 - High-speed interface not supported
556 * @fs_phy_type Full-speed PHY interface type
557 * 0 - Full speed interface not supported
558 * 1 - Dedicated full speed interface
559 * 2 - FS pins shared with UTMI+ pins
560 * 3 - FS pins shared with ULPI pins
561 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
562 * @utmi_phy_data_width UTMI+ PHY data width
566 * @snpsid: Value from SNPSID register
567 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
569 struct dwc2_hw_params
{
572 unsigned dma_desc_enable
:1;
573 unsigned enable_dynamic_fifo
:1;
574 unsigned en_multiple_tx_fifo
:1;
575 unsigned rx_fifo_size
:16;
576 unsigned host_nperio_tx_fifo_size
:16;
577 unsigned dev_nperio_tx_fifo_size
:16;
578 unsigned host_perio_tx_fifo_size
:16;
579 unsigned nperio_tx_q_depth
:3;
580 unsigned host_perio_tx_q_depth
:3;
581 unsigned dev_token_q_depth
:5;
582 unsigned max_transfer_size
:26;
583 unsigned max_packet_count
:11;
584 unsigned host_channels
:5;
585 unsigned hs_phy_type
:2;
586 unsigned fs_phy_type
:2;
587 unsigned i2c_enable
:1;
588 unsigned num_dev_ep
:4;
589 unsigned num_dev_perio_in_ep
:4;
590 unsigned total_fifo_size
:16;
591 unsigned power_optimized
:1;
592 unsigned utmi_phy_data_width
:2;
597 /* Size of control and EP0 buffers */
598 #define DWC2_CTRL_BUFF_SIZE 8
601 * struct dwc2_gregs_backup - Holds global registers state before
602 * entering partial power down
603 * @gotgctl: Backup of GOTGCTL register
604 * @gintmsk: Backup of GINTMSK register
605 * @gahbcfg: Backup of GAHBCFG register
606 * @gusbcfg: Backup of GUSBCFG register
607 * @grxfsiz: Backup of GRXFSIZ register
608 * @gnptxfsiz: Backup of GNPTXFSIZ register
609 * @gi2cctl: Backup of GI2CCTL register
610 * @hptxfsiz: Backup of HPTXFSIZ register
611 * @gdfifocfg: Backup of GDFIFOCFG register
612 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
613 * @gpwrdn: Backup of GPWRDN register
615 struct dwc2_gregs_backup
{
626 u32 dtxfsiz
[MAX_EPS_CHANNELS
];
632 * struct dwc2_dregs_backup - Holds device registers state before
633 * entering partial power down
634 * @dcfg: Backup of DCFG register
635 * @dctl: Backup of DCTL register
636 * @daintmsk: Backup of DAINTMSK register
637 * @diepmsk: Backup of DIEPMSK register
638 * @doepmsk: Backup of DOEPMSK register
639 * @diepctl: Backup of DIEPCTL register
640 * @dieptsiz: Backup of DIEPTSIZ register
641 * @diepdma: Backup of DIEPDMA register
642 * @doepctl: Backup of DOEPCTL register
643 * @doeptsiz: Backup of DOEPTSIZ register
644 * @doepdma: Backup of DOEPDMA register
646 struct dwc2_dregs_backup
{
652 u32 diepctl
[MAX_EPS_CHANNELS
];
653 u32 dieptsiz
[MAX_EPS_CHANNELS
];
654 u32 diepdma
[MAX_EPS_CHANNELS
];
655 u32 doepctl
[MAX_EPS_CHANNELS
];
656 u32 doeptsiz
[MAX_EPS_CHANNELS
];
657 u32 doepdma
[MAX_EPS_CHANNELS
];
662 * struct dwc2_hregs_backup - Holds host registers state before
663 * entering partial power down
664 * @hcfg: Backup of HCFG register
665 * @haintmsk: Backup of HAINTMSK register
666 * @hcintmsk: Backup of HCINTMSK register
667 * @hptr0: Backup of HPTR0 register
668 * @hfir: Backup of HFIR register
670 struct dwc2_hregs_backup
{
673 u32 hcintmsk
[MAX_EPS_CHANNELS
];
680 * Constants related to high speed periodic scheduling
682 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a
683 * reservation point of view it's assumed that the schedule goes right back to
684 * the beginning after the end of the schedule.
686 * What does that mean for scheduling things with a long interval? It means
687 * we'll reserve time for them in every possible microframe that they could
688 * ever be scheduled in. ...but we'll still only actually schedule them as
689 * often as they were requested.
691 * We keep our schedule in a "bitmap" structure. This simplifies having
692 * to keep track of and merge intervals: we just let the bitmap code do most
693 * of the heavy lifting. In a way scheduling is much like memory allocation.
695 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're
696 * supposed to schedule for periodic transfers). That's according to spec.
698 * Note that though we only schedule 80% of each microframe, the bitmap that we
699 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of
700 * space for each uFrame).
703 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
704 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
705 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might
706 * be bugs). The 8 comes from the USB spec: number of microframes per frame.
708 #define DWC2_US_PER_UFRAME 125
709 #define DWC2_HS_PERIODIC_US_PER_UFRAME 100
711 #define DWC2_HS_SCHEDULE_UFRAMES 8
712 #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \
713 DWC2_HS_PERIODIC_US_PER_UFRAME)
716 * Constants related to low speed scheduling
718 * For high speed we schedule every 1us. For low speed that's a bit overkill,
719 * so we make up a unit called a "slice" that's worth 25us. There are 40
720 * slices in a full frame and we can schedule 36 of those (90%) for periodic
723 * Our low speed schedule can be as short as 1 frame or could be longer. When
724 * we only schedule 1 frame it means that we'll need to reserve a time every
725 * frame even for things that only transfer very rarely, so something that runs
726 * every 2048 frames will get time reserved in every frame. Our low speed
727 * schedule can be longer and we'll be able to handle more overlap, but that
728 * will come at increased memory cost and increased time to schedule.
730 * Note: one other advantage of a short low speed schedule is that if we mess
731 * up and miss scheduling we can jump in and use any of the slots that we
732 * happened to reserve.
734 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for
735 * the schedule. There will be one schedule per TT.
738 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
740 #define DWC2_US_PER_SLICE 25
741 #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE)
743 #define DWC2_ROUND_US_TO_SLICE(us) \
744 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \
747 #define DWC2_LS_PERIODIC_US_PER_FRAME \
749 #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \
750 (DWC2_LS_PERIODIC_US_PER_FRAME / \
753 #define DWC2_LS_SCHEDULE_FRAMES 1
754 #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \
755 DWC2_LS_PERIODIC_SLICES_PER_FRAME)
758 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
759 * and periodic schedules
761 * These are common for both host and peripheral modes:
763 * @dev: The struct device pointer
764 * @regs: Pointer to controller regs
765 * @hw_params: Parameters that were autodetected from the
767 * @core_params: Parameters that define how the core should be configured
768 * @op_state: The operational State, during transitions (a_host=>
769 * a_peripheral and b_device=>b_host) this may not match
770 * the core, but allows the software to determine
772 * @dr_mode: Requested mode of operation, one of following:
773 * - USB_DR_MODE_PERIPHERAL
776 * @hcd_enabled Host mode sub-driver initialization indicator.
777 * @gadget_enabled Peripheral mode sub-driver initialization indicator.
778 * @ll_hw_enabled Status of low-level hardware resources.
779 * @phy: The otg phy transceiver structure for phy control.
780 * @uphy: The otg phy transceiver structure for old USB phy
782 * @plat: The platform specific configuration data. This can be
783 * removed once all SoCs support usb transceiver.
784 * @supplies: Definition of USB power supplies
785 * @phyif: PHY interface width
786 * @lock: Spinlock that protects all the driver data structures
787 * @priv: Stores a pointer to the struct usb_hcd
788 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
789 * transfer are in process of being queued
790 * @srp_success: Stores status of SRP request in the case of a FS PHY
791 * with an I2C interface
792 * @wq_otg: Workqueue object used for handling of some interrupts
793 * @wf_otg: Work object for handling Connector ID Status Change
795 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
796 * @lx_state: Lx state of connected device
797 * @gregs_backup: Backup of global registers during suspend
798 * @dregs_backup: Backup of device registers during suspend
799 * @hregs_backup: Backup of host registers during suspend
801 * These are for host mode:
803 * @flags: Flags for handling root port state changes
804 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
805 * Transfers associated with these QHs are not currently
806 * assigned to a host channel.
807 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
808 * Transfers associated with these QHs are currently
809 * assigned to a host channel.
810 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
811 * non-periodic schedule
812 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
813 * list of QHs for periodic transfers that are _not_
814 * scheduled for the next frame. Each QH in the list has an
815 * interval counter that determines when it needs to be
816 * scheduled for execution. This scheduling mechanism
817 * allows only a simple calculation for periodic bandwidth
818 * used (i.e. must assume that all periodic transfers may
819 * need to execute in the same frame). However, it greatly
820 * simplifies scheduling and should be sufficient for the
821 * vast majority of OTG hosts, which need to connect to a
822 * small number of peripherals at one time. Items move from
823 * this list to periodic_sched_ready when the QH interval
824 * counter is 0 at SOF.
825 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
826 * the next frame, but have not yet been assigned to host
827 * channels. Items move from this list to
828 * periodic_sched_assigned as host channels become
829 * available during the current frame.
830 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
831 * frame that are assigned to host channels. Items move
832 * from this list to periodic_sched_queued as the
833 * transactions for the QH are queued to the DWC_otg
835 * @periodic_sched_queued: List of periodic QHs that have been queued for
836 * execution. Items move from this list to either
837 * periodic_sched_inactive or periodic_sched_ready when the
838 * channel associated with the transfer is released. If the
839 * interval for the QH is 1, the item moves to
840 * periodic_sched_ready because it must be rescheduled for
841 * the next frame. Otherwise, the item moves to
842 * periodic_sched_inactive.
843 * @split_order: List keeping track of channels doing splits, in order.
844 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
845 * This value is in microseconds per (micro)frame. The
846 * assumption is that all periodic transfers may occur in
847 * the same (micro)frame.
848 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
849 * host is in high speed mode; low speed schedules are
850 * stored elsewhere since we need one per TT.
851 * @frame_number: Frame number read from the core at SOF. The value ranges
852 * from 0 to HFNUM_MAX_FRNUM.
853 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
854 * SOF enable/disable.
855 * @free_hc_list: Free host channels in the controller. This is a list of
856 * struct dwc2_host_chan items.
857 * @periodic_channels: Number of host channels assigned to periodic transfers.
858 * Currently assuming that there is a dedicated host
859 * channel for each periodic transaction and at least one
860 * host channel is available for non-periodic transactions.
861 * @non_periodic_channels: Number of host channels assigned to non-periodic
863 * @available_host_channels Number of host channels available for the microframe
865 * @hc_ptr_array: Array of pointers to the host channel descriptors.
866 * Allows accessing a host channel descriptor given the
867 * host channel number. This is useful in interrupt
869 * @status_buf: Buffer used for data received during the status phase of
870 * a control transfer.
871 * @status_buf_dma: DMA address for status_buf
872 * @start_work: Delayed work for handling host A-cable connection
873 * @reset_work: Delayed work for handling a port reset
874 * @otg_port: OTG port number
875 * @frame_list: Frame list
876 * @frame_list_dma: Frame list DMA address
877 * @frame_list_sz: Frame list size
878 * @desc_gen_cache: Kmem cache for generic descriptors
879 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors
881 * These are for peripheral mode:
883 * @driver: USB gadget driver
884 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
885 * @num_of_eps: Number of available EPs (excluding EP0)
886 * @debug_root: Root directrory for debugfs.
887 * @debug_file: Main status file for debugfs.
888 * @debug_testmode: Testmode status file for debugfs.
889 * @debug_fifo: FIFO status file for debugfs.
890 * @ep0_reply: Request used for ep0 reply.
891 * @ep0_buff: Buffer for EP0 reply data, if needed.
892 * @ctrl_buff: Buffer for EP0 control requests.
893 * @ctrl_req: Request for EP0 control packets.
894 * @ep0_state: EP0 control transfers state
895 * @test_mode: USB test mode requested by the host
896 * @setup_desc_dma: EP0 setup stage desc chain DMA address
897 * @setup_desc: EP0 setup stage desc chain pointer
898 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address
899 * @ctrl_in_desc: EP0 IN data phase desc chain pointer
900 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address
901 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer
902 * @eps: The endpoints being supplied to the gadget framework
907 /** Params detected from hardware */
908 struct dwc2_hw_params hw_params
;
909 /** Params to actually use */
910 struct dwc2_core_params params
;
911 enum usb_otg_state op_state
;
912 enum usb_dr_mode dr_mode
;
913 unsigned int hcd_enabled
:1;
914 unsigned int gadget_enabled
:1;
915 unsigned int ll_hw_enabled
:1;
918 struct usb_phy
*uphy
;
919 struct dwc2_hsotg_plat
*plat
;
920 struct regulator_bulk_data supplies
[DWC2_NUM_SUPPLIES
];
927 struct reset_control
*reset
;
929 unsigned int queuing_high_bandwidth
:1;
930 unsigned int srp_success
:1;
932 struct workqueue_struct
*wq_otg
;
933 struct work_struct wf_otg
;
934 struct timer_list wkp_timer
;
935 enum dwc2_lx_state lx_state
;
936 struct dwc2_gregs_backup gr_backup
;
937 struct dwc2_dregs_backup dr_backup
;
938 struct dwc2_hregs_backup hr_backup
;
940 struct dentry
*debug_root
;
941 struct debugfs_regset32
*regset
;
943 /* DWC OTG HW Release versions */
944 #define DWC2_CORE_REV_2_71a 0x4f54271a
945 #define DWC2_CORE_REV_2_90a 0x4f54290a
946 #define DWC2_CORE_REV_2_91a 0x4f54291a
947 #define DWC2_CORE_REV_2_92a 0x4f54292a
948 #define DWC2_CORE_REV_2_94a 0x4f54294a
949 #define DWC2_CORE_REV_3_00a 0x4f54300a
950 #define DWC2_CORE_REV_3_10a 0x4f54310a
951 #define DWC2_FS_IOT_REV_1_00a 0x5531100a
952 #define DWC2_HS_IOT_REV_1_00a 0x5532100a
954 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
955 union dwc2_hcd_internal_flags
{
958 unsigned port_connect_status_change
:1;
959 unsigned port_connect_status
:1;
960 unsigned port_reset_change
:1;
961 unsigned port_enable_change
:1;
962 unsigned port_suspend_change
:1;
963 unsigned port_over_current_change
:1;
964 unsigned port_l1_change
:1;
965 unsigned reserved
:25;
969 struct list_head non_periodic_sched_inactive
;
970 struct list_head non_periodic_sched_active
;
971 struct list_head
*non_periodic_qh_ptr
;
972 struct list_head periodic_sched_inactive
;
973 struct list_head periodic_sched_ready
;
974 struct list_head periodic_sched_assigned
;
975 struct list_head periodic_sched_queued
;
976 struct list_head split_order
;
978 unsigned long hs_periodic_bitmap
[
979 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US
, BITS_PER_LONG
)];
981 u16 periodic_qh_count
;
987 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
988 #define FRAME_NUM_ARRAY_SIZE 1000
989 u16
*frame_num_array
;
990 u16
*last_frame_num_array
;
992 int dumped_frame_num_array
;
995 struct list_head free_hc_list
;
996 int periodic_channels
;
997 int non_periodic_channels
;
998 int available_host_channels
;
999 struct dwc2_host_chan
*hc_ptr_array
[MAX_EPS_CHANNELS
];
1001 dma_addr_t status_buf_dma
;
1002 #define DWC2_HCD_STATUS_BUF_SIZE 64
1004 struct delayed_work start_work
;
1005 struct delayed_work reset_work
;
1008 dma_addr_t frame_list_dma
;
1010 struct kmem_cache
*desc_gen_cache
;
1011 struct kmem_cache
*desc_hsisoc_cache
;
1017 u32 hfnum_7_samples_a
;
1018 u64 hfnum_7_frrem_accum_a
;
1019 u32 hfnum_0_samples_a
;
1020 u64 hfnum_0_frrem_accum_a
;
1021 u32 hfnum_other_samples_a
;
1022 u64 hfnum_other_frrem_accum_a
;
1024 u32 hfnum_7_samples_b
;
1025 u64 hfnum_7_frrem_accum_b
;
1026 u32 hfnum_0_samples_b
;
1027 u64 hfnum_0_frrem_accum_b
;
1028 u32 hfnum_other_samples_b
;
1029 u64 hfnum_other_frrem_accum_b
;
1031 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
1033 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1034 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1035 /* Gadget structures */
1036 struct usb_gadget_driver
*driver
;
1038 unsigned int dedicated_fifos
:1;
1039 unsigned char num_of_eps
;
1042 struct usb_request
*ep0_reply
;
1043 struct usb_request
*ctrl_req
;
1046 enum dwc2_ep0_state ep0_state
;
1049 dma_addr_t setup_desc_dma
[2];
1050 struct dwc2_dma_desc
*setup_desc
[2];
1051 dma_addr_t ctrl_in_desc_dma
;
1052 struct dwc2_dma_desc
*ctrl_in_desc
;
1053 dma_addr_t ctrl_out_desc_dma
;
1054 struct dwc2_dma_desc
*ctrl_out_desc
;
1056 struct usb_gadget gadget
;
1057 unsigned int enabled
:1;
1058 unsigned int connected
:1;
1059 struct dwc2_hsotg_ep
*eps_in
[MAX_EPS_CHANNELS
];
1060 struct dwc2_hsotg_ep
*eps_out
[MAX_EPS_CHANNELS
];
1061 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
1064 /* Reasons for halting a host channel */
1065 enum dwc2_halt_status
{
1066 DWC2_HC_XFER_NO_HALT_STATUS
,
1067 DWC2_HC_XFER_COMPLETE
,
1068 DWC2_HC_XFER_URB_COMPLETE
,
1073 DWC2_HC_XFER_XACT_ERR
,
1074 DWC2_HC_XFER_FRAME_OVERRUN
,
1075 DWC2_HC_XFER_BABBLE_ERR
,
1076 DWC2_HC_XFER_DATA_TOGGLE_ERR
,
1077 DWC2_HC_XFER_AHB_ERR
,
1078 DWC2_HC_XFER_PERIODIC_INCOMPLETE
,
1079 DWC2_HC_XFER_URB_DEQUEUE
,
1082 /* Core version information */
1083 static inline bool dwc2_is_iot(struct dwc2_hsotg
*hsotg
)
1085 return (hsotg
->hw_params
.snpsid
& 0xfff00000) == 0x55300000;
1088 static inline bool dwc2_is_fs_iot(struct dwc2_hsotg
*hsotg
)
1090 return (hsotg
->hw_params
.snpsid
& 0xffff0000) == 0x55310000;
1093 static inline bool dwc2_is_hs_iot(struct dwc2_hsotg
*hsotg
)
1095 return (hsotg
->hw_params
.snpsid
& 0xffff0000) == 0x55320000;
1099 * The following functions support initialization of the core driver component
1100 * and the DWC_otg controller
1102 int dwc2_core_reset(struct dwc2_hsotg
*hsotg
, bool skip_wait
);
1103 int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg
*hsotg
);
1104 int dwc2_enter_hibernation(struct dwc2_hsotg
*hsotg
);
1105 int dwc2_exit_hibernation(struct dwc2_hsotg
*hsotg
, bool restore
);
1107 bool dwc2_force_mode_if_needed(struct dwc2_hsotg
*hsotg
, bool host
);
1108 void dwc2_clear_force_mode(struct dwc2_hsotg
*hsotg
);
1109 void dwc2_force_dr_mode(struct dwc2_hsotg
*hsotg
);
1111 bool dwc2_is_controller_alive(struct dwc2_hsotg
*hsotg
);
1114 * Common core Functions.
1115 * The following functions support managing the DWC_otg controller in either
1116 * device or host mode.
1118 void dwc2_read_packet(struct dwc2_hsotg
*hsotg
, u8
*dest
, u16 bytes
);
1119 void dwc2_flush_tx_fifo(struct dwc2_hsotg
*hsotg
, const int num
);
1120 void dwc2_flush_rx_fifo(struct dwc2_hsotg
*hsotg
);
1122 void dwc2_enable_global_interrupts(struct dwc2_hsotg
*hcd
);
1123 void dwc2_disable_global_interrupts(struct dwc2_hsotg
*hcd
);
1125 /* This function should be called on every hardware interrupt. */
1126 irqreturn_t
dwc2_handle_common_intr(int irq
, void *dev
);
1128 /* The device ID match table */
1129 extern const struct of_device_id dwc2_of_match_table
[];
1131 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg
*hsotg
);
1132 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg
*hsotg
);
1135 int dwc2_get_hwparams(struct dwc2_hsotg
*hsotg
);
1136 int dwc2_init_params(struct dwc2_hsotg
*hsotg
);
1139 * The following functions check the controller's OTG operation mode
1140 * capability (GHWCFG2.OTG_MODE).
1142 * These functions can be used before the internal hsotg->hw_params
1143 * are read in and cached so they always read directly from the
1146 unsigned int dwc2_op_mode(struct dwc2_hsotg
*hsotg
);
1147 bool dwc2_hw_is_otg(struct dwc2_hsotg
*hsotg
);
1148 bool dwc2_hw_is_host(struct dwc2_hsotg
*hsotg
);
1149 bool dwc2_hw_is_device(struct dwc2_hsotg
*hsotg
);
1152 * Returns the mode of operation, host or device
1154 static inline int dwc2_is_host_mode(struct dwc2_hsotg
*hsotg
)
1156 return (dwc2_readl(hsotg
->regs
+ GINTSTS
) & GINTSTS_CURMODE_HOST
) != 0;
1159 static inline int dwc2_is_device_mode(struct dwc2_hsotg
*hsotg
)
1161 return (dwc2_readl(hsotg
->regs
+ GINTSTS
) & GINTSTS_CURMODE_HOST
) == 0;
1165 * Dump core registers and SPRAM
1167 void dwc2_dump_dev_registers(struct dwc2_hsotg
*hsotg
);
1168 void dwc2_dump_host_registers(struct dwc2_hsotg
*hsotg
);
1169 void dwc2_dump_global_registers(struct dwc2_hsotg
*hsotg
);
1171 /* Gadget defines */
1172 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1173 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1174 int dwc2_hsotg_remove(struct dwc2_hsotg
*hsotg
);
1175 int dwc2_hsotg_suspend(struct dwc2_hsotg
*dwc2
);
1176 int dwc2_hsotg_resume(struct dwc2_hsotg
*dwc2
);
1177 int dwc2_gadget_init(struct dwc2_hsotg
*hsotg
, int irq
);
1178 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg
*dwc2
,
1180 void dwc2_hsotg_core_connect(struct dwc2_hsotg
*hsotg
);
1181 void dwc2_hsotg_disconnect(struct dwc2_hsotg
*dwc2
);
1182 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg
*hsotg
, int testmode
);
1183 #define dwc2_is_device_connected(hsotg) (hsotg->connected)
1184 int dwc2_backup_device_registers(struct dwc2_hsotg
*hsotg
);
1185 int dwc2_restore_device_registers(struct dwc2_hsotg
*hsotg
);
1186 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg
*hsotg
);
1187 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg
*hsotg
);
1188 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg
*hsotg
);
1190 static inline int dwc2_hsotg_remove(struct dwc2_hsotg
*dwc2
)
1192 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg
*dwc2
)
1194 static inline int dwc2_hsotg_resume(struct dwc2_hsotg
*dwc2
)
1196 static inline int dwc2_gadget_init(struct dwc2_hsotg
*hsotg
, int irq
)
1198 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg
*dwc2
,
1200 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg
*hsotg
) {}
1201 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg
*dwc2
) {}
1202 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg
*hsotg
,
1205 #define dwc2_is_device_connected(hsotg) (0)
1206 static inline int dwc2_backup_device_registers(struct dwc2_hsotg
*hsotg
)
1208 static inline int dwc2_restore_device_registers(struct dwc2_hsotg
*hsotg
)
1210 static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg
*hsotg
)
1212 static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg
*hsotg
)
1214 static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg
*hsotg
)
1218 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1219 int dwc2_hcd_get_frame_number(struct dwc2_hsotg
*hsotg
);
1220 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg
*hsotg
, int us
);
1221 void dwc2_hcd_connect(struct dwc2_hsotg
*hsotg
);
1222 void dwc2_hcd_disconnect(struct dwc2_hsotg
*hsotg
, bool force
);
1223 void dwc2_hcd_start(struct dwc2_hsotg
*hsotg
);
1224 int dwc2_backup_host_registers(struct dwc2_hsotg
*hsotg
);
1225 int dwc2_restore_host_registers(struct dwc2_hsotg
*hsotg
);
1227 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg
*hsotg
)
1229 static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg
*hsotg
,
1232 static inline void dwc2_hcd_connect(struct dwc2_hsotg
*hsotg
) {}
1233 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg
*hsotg
, bool force
) {}
1234 static inline void dwc2_hcd_start(struct dwc2_hsotg
*hsotg
) {}
1235 static inline void dwc2_hcd_remove(struct dwc2_hsotg
*hsotg
) {}
1236 static inline int dwc2_hcd_init(struct dwc2_hsotg
*hsotg
)
1238 static inline int dwc2_backup_host_registers(struct dwc2_hsotg
*hsotg
)
1240 static inline int dwc2_restore_host_registers(struct dwc2_hsotg
*hsotg
)
1245 #endif /* __DWC2_CORE_H__ */