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1 /**
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
9 *
10 * S3C USB2.0 High-speed / OtG driver
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/mutex.h>
24 #include <linux/seq_file.h>
25 #include <linux/delay.h>
26 #include <linux/io.h>
27 #include <linux/slab.h>
28 #include <linux/of_platform.h>
29
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/phy.h>
33
34 #include "core.h"
35 #include "hw.h"
36
37 /* conversion functions */
38 static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
39 {
40 return container_of(req, struct dwc2_hsotg_req, req);
41 }
42
43 static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
44 {
45 return container_of(ep, struct dwc2_hsotg_ep, ep);
46 }
47
48 static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
49 {
50 return container_of(gadget, struct dwc2_hsotg, gadget);
51 }
52
53 static inline void __orr32(void __iomem *ptr, u32 val)
54 {
55 dwc2_writel(dwc2_readl(ptr) | val, ptr);
56 }
57
58 static inline void __bic32(void __iomem *ptr, u32 val)
59 {
60 dwc2_writel(dwc2_readl(ptr) & ~val, ptr);
61 }
62
63 static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
64 u32 ep_index, u32 dir_in)
65 {
66 if (dir_in)
67 return hsotg->eps_in[ep_index];
68 else
69 return hsotg->eps_out[ep_index];
70 }
71
72 /* forward declaration of functions */
73 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
74
75 /**
76 * using_dma - return the DMA status of the driver.
77 * @hsotg: The driver state.
78 *
79 * Return true if we're using DMA.
80 *
81 * Currently, we have the DMA support code worked into everywhere
82 * that needs it, but the AMBA DMA implementation in the hardware can
83 * only DMA from 32bit aligned addresses. This means that gadgets such
84 * as the CDC Ethernet cannot work as they often pass packets which are
85 * not 32bit aligned.
86 *
87 * Unfortunately the choice to use DMA or not is global to the controller
88 * and seems to be only settable when the controller is being put through
89 * a core reset. This means we either need to fix the gadgets to take
90 * account of DMA alignment, or add bounce buffers (yuerk).
91 *
92 * g_using_dma is set depending on dts flag.
93 */
94 static inline bool using_dma(struct dwc2_hsotg *hsotg)
95 {
96 return hsotg->g_using_dma;
97 }
98
99 /**
100 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
101 * @hs_ep: The endpoint
102 * @increment: The value to increment by
103 *
104 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
105 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
106 */
107 static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
108 {
109 hs_ep->target_frame += hs_ep->interval;
110 if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) {
111 hs_ep->frame_overrun = 1;
112 hs_ep->target_frame &= DSTS_SOFFN_LIMIT;
113 } else {
114 hs_ep->frame_overrun = 0;
115 }
116 }
117
118 /**
119 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
120 * @hsotg: The device state
121 * @ints: A bitmask of the interrupts to enable
122 */
123 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
124 {
125 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
126 u32 new_gsintmsk;
127
128 new_gsintmsk = gsintmsk | ints;
129
130 if (new_gsintmsk != gsintmsk) {
131 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
132 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
133 }
134 }
135
136 /**
137 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
138 * @hsotg: The device state
139 * @ints: A bitmask of the interrupts to enable
140 */
141 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
142 {
143 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
144 u32 new_gsintmsk;
145
146 new_gsintmsk = gsintmsk & ~ints;
147
148 if (new_gsintmsk != gsintmsk)
149 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
150 }
151
152 /**
153 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
154 * @hsotg: The device state
155 * @ep: The endpoint index
156 * @dir_in: True if direction is in.
157 * @en: The enable value, true to enable
158 *
159 * Set or clear the mask for an individual endpoint's interrupt
160 * request.
161 */
162 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
163 unsigned int ep, unsigned int dir_in,
164 unsigned int en)
165 {
166 unsigned long flags;
167 u32 bit = 1 << ep;
168 u32 daint;
169
170 if (!dir_in)
171 bit <<= 16;
172
173 local_irq_save(flags);
174 daint = dwc2_readl(hsotg->regs + DAINTMSK);
175 if (en)
176 daint |= bit;
177 else
178 daint &= ~bit;
179 dwc2_writel(daint, hsotg->regs + DAINTMSK);
180 local_irq_restore(flags);
181 }
182
183 /**
184 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
185 * @hsotg: The device instance.
186 */
187 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
188 {
189 unsigned int fifo;
190 unsigned int addr;
191 int timeout;
192 u32 dptxfsizn;
193 u32 val;
194
195 /* Reset fifo map if not correctly cleared during previous session */
196 WARN_ON(hsotg->fifo_map);
197 hsotg->fifo_map = 0;
198
199 /* set RX/NPTX FIFO sizes */
200 dwc2_writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ);
201 dwc2_writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) |
202 (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT),
203 hsotg->regs + GNPTXFSIZ);
204
205 /*
206 * arange all the rest of the TX FIFOs, as some versions of this
207 * block have overlapping default addresses. This also ensures
208 * that if the settings have been changed, then they are set to
209 * known values.
210 */
211
212 /* start at the end of the GNPTXFSIZ, rounded up */
213 addr = hsotg->g_rx_fifo_sz + hsotg->g_np_g_tx_fifo_sz;
214
215 /*
216 * Configure fifos sizes from provided configuration and assign
217 * them to endpoints dynamically according to maxpacket size value of
218 * given endpoint.
219 */
220 for (fifo = 1; fifo < MAX_EPS_CHANNELS; fifo++) {
221 dptxfsizn = dwc2_readl(hsotg->regs + DPTXFSIZN(fifo));
222
223 val = (dptxfsizn & FIFOSIZE_DEPTH_MASK) | addr;
224 addr += dptxfsizn >> FIFOSIZE_DEPTH_SHIFT;
225
226 if (addr > hsotg->fifo_mem)
227 break;
228
229 dwc2_writel(val, hsotg->regs + DPTXFSIZN(fifo));
230 }
231
232 /*
233 * according to p428 of the design guide, we need to ensure that
234 * all fifos are flushed before continuing
235 */
236
237 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
238 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
239
240 /* wait until the fifos are both flushed */
241 timeout = 100;
242 while (1) {
243 val = dwc2_readl(hsotg->regs + GRSTCTL);
244
245 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
246 break;
247
248 if (--timeout == 0) {
249 dev_err(hsotg->dev,
250 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
251 __func__, val);
252 break;
253 }
254
255 udelay(1);
256 }
257
258 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
259 }
260
261 /**
262 * @ep: USB endpoint to allocate request for.
263 * @flags: Allocation flags
264 *
265 * Allocate a new USB request structure appropriate for the specified endpoint
266 */
267 static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
268 gfp_t flags)
269 {
270 struct dwc2_hsotg_req *req;
271
272 req = kzalloc(sizeof(struct dwc2_hsotg_req), flags);
273 if (!req)
274 return NULL;
275
276 INIT_LIST_HEAD(&req->queue);
277
278 return &req->req;
279 }
280
281 /**
282 * is_ep_periodic - return true if the endpoint is in periodic mode.
283 * @hs_ep: The endpoint to query.
284 *
285 * Returns true if the endpoint is in periodic mode, meaning it is being
286 * used for an Interrupt or ISO transfer.
287 */
288 static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
289 {
290 return hs_ep->periodic;
291 }
292
293 /**
294 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
295 * @hsotg: The device state.
296 * @hs_ep: The endpoint for the request
297 * @hs_req: The request being processed.
298 *
299 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
300 * of a request to ensure the buffer is ready for access by the caller.
301 */
302 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
303 struct dwc2_hsotg_ep *hs_ep,
304 struct dwc2_hsotg_req *hs_req)
305 {
306 struct usb_request *req = &hs_req->req;
307
308 /* ignore this if we're not moving any data */
309 if (hs_req->req.length == 0)
310 return;
311
312 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
313 }
314
315 /**
316 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
317 * @hsotg: The controller state.
318 * @hs_ep: The endpoint we're going to write for.
319 * @hs_req: The request to write data for.
320 *
321 * This is called when the TxFIFO has some space in it to hold a new
322 * transmission and we have something to give it. The actual setup of
323 * the data size is done elsewhere, so all we have to do is to actually
324 * write the data.
325 *
326 * The return value is zero if there is more space (or nothing was done)
327 * otherwise -ENOSPC is returned if the FIFO space was used up.
328 *
329 * This routine is only needed for PIO
330 */
331 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
332 struct dwc2_hsotg_ep *hs_ep,
333 struct dwc2_hsotg_req *hs_req)
334 {
335 bool periodic = is_ep_periodic(hs_ep);
336 u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
337 int buf_pos = hs_req->req.actual;
338 int to_write = hs_ep->size_loaded;
339 void *data;
340 int can_write;
341 int pkt_round;
342 int max_transfer;
343
344 to_write -= (buf_pos - hs_ep->last_load);
345
346 /* if there's nothing to write, get out early */
347 if (to_write == 0)
348 return 0;
349
350 if (periodic && !hsotg->dedicated_fifos) {
351 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
352 int size_left;
353 int size_done;
354
355 /*
356 * work out how much data was loaded so we can calculate
357 * how much data is left in the fifo.
358 */
359
360 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
361
362 /*
363 * if shared fifo, we cannot write anything until the
364 * previous data has been completely sent.
365 */
366 if (hs_ep->fifo_load != 0) {
367 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
368 return -ENOSPC;
369 }
370
371 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
372 __func__, size_left,
373 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
374
375 /* how much of the data has moved */
376 size_done = hs_ep->size_loaded - size_left;
377
378 /* how much data is left in the fifo */
379 can_write = hs_ep->fifo_load - size_done;
380 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
381 __func__, can_write);
382
383 can_write = hs_ep->fifo_size - can_write;
384 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
385 __func__, can_write);
386
387 if (can_write <= 0) {
388 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
389 return -ENOSPC;
390 }
391 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
392 can_write = dwc2_readl(hsotg->regs +
393 DTXFSTS(hs_ep->fifo_index));
394
395 can_write &= 0xffff;
396 can_write *= 4;
397 } else {
398 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
399 dev_dbg(hsotg->dev,
400 "%s: no queue slots available (0x%08x)\n",
401 __func__, gnptxsts);
402
403 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
404 return -ENOSPC;
405 }
406
407 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
408 can_write *= 4; /* fifo size is in 32bit quantities. */
409 }
410
411 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
412
413 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
414 __func__, gnptxsts, can_write, to_write, max_transfer);
415
416 /*
417 * limit to 512 bytes of data, it seems at least on the non-periodic
418 * FIFO, requests of >512 cause the endpoint to get stuck with a
419 * fragment of the end of the transfer in it.
420 */
421 if (can_write > 512 && !periodic)
422 can_write = 512;
423
424 /*
425 * limit the write to one max-packet size worth of data, but allow
426 * the transfer to return that it did not run out of fifo space
427 * doing it.
428 */
429 if (to_write > max_transfer) {
430 to_write = max_transfer;
431
432 /* it's needed only when we do not use dedicated fifos */
433 if (!hsotg->dedicated_fifos)
434 dwc2_hsotg_en_gsint(hsotg,
435 periodic ? GINTSTS_PTXFEMP :
436 GINTSTS_NPTXFEMP);
437 }
438
439 /* see if we can write data */
440
441 if (to_write > can_write) {
442 to_write = can_write;
443 pkt_round = to_write % max_transfer;
444
445 /*
446 * Round the write down to an
447 * exact number of packets.
448 *
449 * Note, we do not currently check to see if we can ever
450 * write a full packet or not to the FIFO.
451 */
452
453 if (pkt_round)
454 to_write -= pkt_round;
455
456 /*
457 * enable correct FIFO interrupt to alert us when there
458 * is more room left.
459 */
460
461 /* it's needed only when we do not use dedicated fifos */
462 if (!hsotg->dedicated_fifos)
463 dwc2_hsotg_en_gsint(hsotg,
464 periodic ? GINTSTS_PTXFEMP :
465 GINTSTS_NPTXFEMP);
466 }
467
468 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
469 to_write, hs_req->req.length, can_write, buf_pos);
470
471 if (to_write <= 0)
472 return -ENOSPC;
473
474 hs_req->req.actual = buf_pos + to_write;
475 hs_ep->total_data += to_write;
476
477 if (periodic)
478 hs_ep->fifo_load += to_write;
479
480 to_write = DIV_ROUND_UP(to_write, 4);
481 data = hs_req->req.buf + buf_pos;
482
483 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
484
485 return (to_write >= can_write) ? -ENOSPC : 0;
486 }
487
488 /**
489 * get_ep_limit - get the maximum data legnth for this endpoint
490 * @hs_ep: The endpoint
491 *
492 * Return the maximum data that can be queued in one go on a given endpoint
493 * so that transfers that are too long can be split.
494 */
495 static unsigned get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
496 {
497 int index = hs_ep->index;
498 unsigned maxsize;
499 unsigned maxpkt;
500
501 if (index != 0) {
502 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
503 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
504 } else {
505 maxsize = 64+64;
506 if (hs_ep->dir_in)
507 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
508 else
509 maxpkt = 2;
510 }
511
512 /* we made the constant loading easier above by using +1 */
513 maxpkt--;
514 maxsize--;
515
516 /*
517 * constrain by packet count if maxpkts*pktsize is greater
518 * than the length register size.
519 */
520
521 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
522 maxsize = maxpkt * hs_ep->ep.maxpacket;
523
524 return maxsize;
525 }
526
527 /**
528 * dwc2_hsotg_read_frameno - read current frame number
529 * @hsotg: The device instance
530 *
531 * Return the current frame number
532 */
533 static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
534 {
535 u32 dsts;
536
537 dsts = dwc2_readl(hsotg->regs + DSTS);
538 dsts &= DSTS_SOFFN_MASK;
539 dsts >>= DSTS_SOFFN_SHIFT;
540
541 return dsts;
542 }
543
544 /**
545 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
546 * @hsotg: The controller state.
547 * @hs_ep: The endpoint to process a request for
548 * @hs_req: The request to start.
549 * @continuing: True if we are doing more for the current request.
550 *
551 * Start the given request running by setting the endpoint registers
552 * appropriately, and writing any data to the FIFOs.
553 */
554 static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
555 struct dwc2_hsotg_ep *hs_ep,
556 struct dwc2_hsotg_req *hs_req,
557 bool continuing)
558 {
559 struct usb_request *ureq = &hs_req->req;
560 int index = hs_ep->index;
561 int dir_in = hs_ep->dir_in;
562 u32 epctrl_reg;
563 u32 epsize_reg;
564 u32 epsize;
565 u32 ctrl;
566 unsigned length;
567 unsigned packets;
568 unsigned maxreq;
569
570 if (index != 0) {
571 if (hs_ep->req && !continuing) {
572 dev_err(hsotg->dev, "%s: active request\n", __func__);
573 WARN_ON(1);
574 return;
575 } else if (hs_ep->req != hs_req && continuing) {
576 dev_err(hsotg->dev,
577 "%s: continue different req\n", __func__);
578 WARN_ON(1);
579 return;
580 }
581 }
582
583 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
584 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
585
586 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
587 __func__, dwc2_readl(hsotg->regs + epctrl_reg), index,
588 hs_ep->dir_in ? "in" : "out");
589
590 /* If endpoint is stalled, we will restart request later */
591 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
592
593 if (index && ctrl & DXEPCTL_STALL) {
594 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
595 return;
596 }
597
598 length = ureq->length - ureq->actual;
599 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
600 ureq->length, ureq->actual);
601
602 maxreq = get_ep_limit(hs_ep);
603 if (length > maxreq) {
604 int round = maxreq % hs_ep->ep.maxpacket;
605
606 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
607 __func__, length, maxreq, round);
608
609 /* round down to multiple of packets */
610 if (round)
611 maxreq -= round;
612
613 length = maxreq;
614 }
615
616 if (length)
617 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
618 else
619 packets = 1; /* send one packet if length is zero. */
620
621 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
622 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
623 return;
624 }
625
626 if (dir_in && index != 0)
627 if (hs_ep->isochronous)
628 epsize = DXEPTSIZ_MC(packets);
629 else
630 epsize = DXEPTSIZ_MC(1);
631 else
632 epsize = 0;
633
634 /*
635 * zero length packet should be programmed on its own and should not
636 * be counted in DIEPTSIZ.PktCnt with other packets.
637 */
638 if (dir_in && ureq->zero && !continuing) {
639 /* Test if zlp is actually required. */
640 if ((ureq->length >= hs_ep->ep.maxpacket) &&
641 !(ureq->length % hs_ep->ep.maxpacket))
642 hs_ep->send_zlp = 1;
643 }
644
645 epsize |= DXEPTSIZ_PKTCNT(packets);
646 epsize |= DXEPTSIZ_XFERSIZE(length);
647
648 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
649 __func__, packets, length, ureq->length, epsize, epsize_reg);
650
651 /* store the request as the current one we're doing */
652 hs_ep->req = hs_req;
653
654 /* write size / packets */
655 dwc2_writel(epsize, hsotg->regs + epsize_reg);
656
657 if (using_dma(hsotg) && !continuing) {
658 unsigned int dma_reg;
659
660 /*
661 * write DMA address to control register, buffer already
662 * synced by dwc2_hsotg_ep_queue().
663 */
664
665 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
666 dwc2_writel(ureq->dma, hsotg->regs + dma_reg);
667
668 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
669 __func__, &ureq->dma, dma_reg);
670 }
671
672 if (hs_ep->isochronous && hs_ep->interval == 1) {
673 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
674 dwc2_gadget_incr_frame_num(hs_ep);
675
676 if (hs_ep->target_frame & 0x1)
677 ctrl |= DXEPCTL_SETODDFR;
678 else
679 ctrl |= DXEPCTL_SETEVENFR;
680 }
681
682 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
683
684 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
685
686 /* For Setup request do not clear NAK */
687 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
688 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
689
690 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
691 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
692
693 /*
694 * set these, it seems that DMA support increments past the end
695 * of the packet buffer so we need to calculate the length from
696 * this information.
697 */
698 hs_ep->size_loaded = length;
699 hs_ep->last_load = ureq->actual;
700
701 if (dir_in && !using_dma(hsotg)) {
702 /* set these anyway, we may need them for non-periodic in */
703 hs_ep->fifo_load = 0;
704
705 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
706 }
707
708 /*
709 * Note, trying to clear the NAK here causes problems with transmit
710 * on the S3C6400 ending up with the TXFIFO becoming full.
711 */
712
713 /* check ep is enabled */
714 if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
715 dev_dbg(hsotg->dev,
716 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
717 index, dwc2_readl(hsotg->regs + epctrl_reg));
718
719 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
720 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
721
722 /* enable ep interrupts */
723 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
724 }
725
726 /**
727 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
728 * @hsotg: The device state.
729 * @hs_ep: The endpoint the request is on.
730 * @req: The request being processed.
731 *
732 * We've been asked to queue a request, so ensure that the memory buffer
733 * is correctly setup for DMA. If we've been passed an extant DMA address
734 * then ensure the buffer has been synced to memory. If our buffer has no
735 * DMA memory, then we map the memory and mark our request to allow us to
736 * cleanup on completion.
737 */
738 static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
739 struct dwc2_hsotg_ep *hs_ep,
740 struct usb_request *req)
741 {
742 struct dwc2_hsotg_req *hs_req = our_req(req);
743 int ret;
744
745 /* if the length is zero, ignore the DMA data */
746 if (hs_req->req.length == 0)
747 return 0;
748
749 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
750 if (ret)
751 goto dma_error;
752
753 return 0;
754
755 dma_error:
756 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
757 __func__, req->buf, req->length);
758
759 return -EIO;
760 }
761
762 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
763 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
764 {
765 void *req_buf = hs_req->req.buf;
766
767 /* If dma is not being used or buffer is aligned */
768 if (!using_dma(hsotg) || !((long)req_buf & 3))
769 return 0;
770
771 WARN_ON(hs_req->saved_req_buf);
772
773 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
774 hs_ep->ep.name, req_buf, hs_req->req.length);
775
776 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
777 if (!hs_req->req.buf) {
778 hs_req->req.buf = req_buf;
779 dev_err(hsotg->dev,
780 "%s: unable to allocate memory for bounce buffer\n",
781 __func__);
782 return -ENOMEM;
783 }
784
785 /* Save actual buffer */
786 hs_req->saved_req_buf = req_buf;
787
788 if (hs_ep->dir_in)
789 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
790 return 0;
791 }
792
793 static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
794 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
795 {
796 /* If dma is not being used or buffer was aligned */
797 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
798 return;
799
800 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
801 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
802
803 /* Copy data from bounce buffer on successful out transfer */
804 if (!hs_ep->dir_in && !hs_req->req.status)
805 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
806 hs_req->req.actual);
807
808 /* Free bounce buffer */
809 kfree(hs_req->req.buf);
810
811 hs_req->req.buf = hs_req->saved_req_buf;
812 hs_req->saved_req_buf = NULL;
813 }
814
815 /**
816 * dwc2_gadget_target_frame_elapsed - Checks target frame
817 * @hs_ep: The driver endpoint to check
818 *
819 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
820 * corresponding transfer.
821 */
822 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
823 {
824 struct dwc2_hsotg *hsotg = hs_ep->parent;
825 u32 target_frame = hs_ep->target_frame;
826 u32 current_frame = dwc2_hsotg_read_frameno(hsotg);
827 bool frame_overrun = hs_ep->frame_overrun;
828
829 if (!frame_overrun && current_frame >= target_frame)
830 return true;
831
832 if (frame_overrun && current_frame >= target_frame &&
833 ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2))
834 return true;
835
836 return false;
837 }
838
839 static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
840 gfp_t gfp_flags)
841 {
842 struct dwc2_hsotg_req *hs_req = our_req(req);
843 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
844 struct dwc2_hsotg *hs = hs_ep->parent;
845 bool first;
846 int ret;
847
848 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
849 ep->name, req, req->length, req->buf, req->no_interrupt,
850 req->zero, req->short_not_ok);
851
852 /* Prevent new request submission when controller is suspended */
853 if (hs->lx_state == DWC2_L2) {
854 dev_dbg(hs->dev, "%s: don't submit request while suspended\n",
855 __func__);
856 return -EAGAIN;
857 }
858
859 /* initialise status of the request */
860 INIT_LIST_HEAD(&hs_req->queue);
861 req->actual = 0;
862 req->status = -EINPROGRESS;
863
864 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
865 if (ret)
866 return ret;
867
868 /* if we're using DMA, sync the buffers as necessary */
869 if (using_dma(hs)) {
870 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
871 if (ret)
872 return ret;
873 }
874
875 first = list_empty(&hs_ep->queue);
876 list_add_tail(&hs_req->queue, &hs_ep->queue);
877
878 if (first) {
879 if (!hs_ep->isochronous) {
880 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
881 return 0;
882 }
883
884 while (dwc2_gadget_target_frame_elapsed(hs_ep))
885 dwc2_gadget_incr_frame_num(hs_ep);
886
887 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
888 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
889 }
890 return 0;
891 }
892
893 static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
894 gfp_t gfp_flags)
895 {
896 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
897 struct dwc2_hsotg *hs = hs_ep->parent;
898 unsigned long flags = 0;
899 int ret = 0;
900
901 spin_lock_irqsave(&hs->lock, flags);
902 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
903 spin_unlock_irqrestore(&hs->lock, flags);
904
905 return ret;
906 }
907
908 static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
909 struct usb_request *req)
910 {
911 struct dwc2_hsotg_req *hs_req = our_req(req);
912
913 kfree(hs_req);
914 }
915
916 /**
917 * dwc2_hsotg_complete_oursetup - setup completion callback
918 * @ep: The endpoint the request was on.
919 * @req: The request completed.
920 *
921 * Called on completion of any requests the driver itself
922 * submitted that need cleaning up.
923 */
924 static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
925 struct usb_request *req)
926 {
927 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
928 struct dwc2_hsotg *hsotg = hs_ep->parent;
929
930 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
931
932 dwc2_hsotg_ep_free_request(ep, req);
933 }
934
935 /**
936 * ep_from_windex - convert control wIndex value to endpoint
937 * @hsotg: The driver state.
938 * @windex: The control request wIndex field (in host order).
939 *
940 * Convert the given wIndex into a pointer to an driver endpoint
941 * structure, or return NULL if it is not a valid endpoint.
942 */
943 static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
944 u32 windex)
945 {
946 struct dwc2_hsotg_ep *ep;
947 int dir = (windex & USB_DIR_IN) ? 1 : 0;
948 int idx = windex & 0x7F;
949
950 if (windex >= 0x100)
951 return NULL;
952
953 if (idx > hsotg->num_of_eps)
954 return NULL;
955
956 ep = index_to_ep(hsotg, idx, dir);
957
958 if (idx && ep->dir_in != dir)
959 return NULL;
960
961 return ep;
962 }
963
964 /**
965 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
966 * @hsotg: The driver state.
967 * @testmode: requested usb test mode
968 * Enable usb Test Mode requested by the Host.
969 */
970 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
971 {
972 int dctl = dwc2_readl(hsotg->regs + DCTL);
973
974 dctl &= ~DCTL_TSTCTL_MASK;
975 switch (testmode) {
976 case TEST_J:
977 case TEST_K:
978 case TEST_SE0_NAK:
979 case TEST_PACKET:
980 case TEST_FORCE_EN:
981 dctl |= testmode << DCTL_TSTCTL_SHIFT;
982 break;
983 default:
984 return -EINVAL;
985 }
986 dwc2_writel(dctl, hsotg->regs + DCTL);
987 return 0;
988 }
989
990 /**
991 * dwc2_hsotg_send_reply - send reply to control request
992 * @hsotg: The device state
993 * @ep: Endpoint 0
994 * @buff: Buffer for request
995 * @length: Length of reply.
996 *
997 * Create a request and queue it on the given endpoint. This is useful as
998 * an internal method of sending replies to certain control requests, etc.
999 */
1000 static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1001 struct dwc2_hsotg_ep *ep,
1002 void *buff,
1003 int length)
1004 {
1005 struct usb_request *req;
1006 int ret;
1007
1008 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1009
1010 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1011 hsotg->ep0_reply = req;
1012 if (!req) {
1013 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1014 return -ENOMEM;
1015 }
1016
1017 req->buf = hsotg->ep0_buff;
1018 req->length = length;
1019 /*
1020 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1021 * STATUS stage.
1022 */
1023 req->zero = 0;
1024 req->complete = dwc2_hsotg_complete_oursetup;
1025
1026 if (length)
1027 memcpy(req->buf, buff, length);
1028
1029 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1030 if (ret) {
1031 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1032 return ret;
1033 }
1034
1035 return 0;
1036 }
1037
1038 /**
1039 * dwc2_hsotg_process_req_status - process request GET_STATUS
1040 * @hsotg: The device state
1041 * @ctrl: USB control request
1042 */
1043 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1044 struct usb_ctrlrequest *ctrl)
1045 {
1046 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1047 struct dwc2_hsotg_ep *ep;
1048 __le16 reply;
1049 int ret;
1050
1051 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1052
1053 if (!ep0->dir_in) {
1054 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1055 return -EINVAL;
1056 }
1057
1058 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1059 case USB_RECIP_DEVICE:
1060 reply = cpu_to_le16(0); /* bit 0 => self powered,
1061 * bit 1 => remote wakeup */
1062 break;
1063
1064 case USB_RECIP_INTERFACE:
1065 /* currently, the data result should be zero */
1066 reply = cpu_to_le16(0);
1067 break;
1068
1069 case USB_RECIP_ENDPOINT:
1070 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1071 if (!ep)
1072 return -ENOENT;
1073
1074 reply = cpu_to_le16(ep->halted ? 1 : 0);
1075 break;
1076
1077 default:
1078 return 0;
1079 }
1080
1081 if (le16_to_cpu(ctrl->wLength) != 2)
1082 return -EINVAL;
1083
1084 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1085 if (ret) {
1086 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1087 return ret;
1088 }
1089
1090 return 1;
1091 }
1092
1093 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1094
1095 /**
1096 * get_ep_head - return the first request on the endpoint
1097 * @hs_ep: The controller endpoint to get
1098 *
1099 * Get the first request on the endpoint.
1100 */
1101 static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1102 {
1103 if (list_empty(&hs_ep->queue))
1104 return NULL;
1105
1106 return list_first_entry(&hs_ep->queue, struct dwc2_hsotg_req, queue);
1107 }
1108
1109 /**
1110 * dwc2_gadget_start_next_request - Starts next request from ep queue
1111 * @hs_ep: Endpoint structure
1112 *
1113 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1114 * in its handler. Hence we need to unmask it here to be able to do
1115 * resynchronization.
1116 */
1117 static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1118 {
1119 u32 mask;
1120 struct dwc2_hsotg *hsotg = hs_ep->parent;
1121 int dir_in = hs_ep->dir_in;
1122 struct dwc2_hsotg_req *hs_req;
1123 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
1124
1125 if (!list_empty(&hs_ep->queue)) {
1126 hs_req = get_ep_head(hs_ep);
1127 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1128 return;
1129 }
1130 if (!hs_ep->isochronous)
1131 return;
1132
1133 if (dir_in) {
1134 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1135 __func__);
1136 } else {
1137 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1138 __func__);
1139 mask = dwc2_readl(hsotg->regs + epmsk_reg);
1140 mask |= DOEPMSK_OUTTKNEPDISMSK;
1141 dwc2_writel(mask, hsotg->regs + epmsk_reg);
1142 }
1143 }
1144
1145 /**
1146 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1147 * @hsotg: The device state
1148 * @ctrl: USB control request
1149 */
1150 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1151 struct usb_ctrlrequest *ctrl)
1152 {
1153 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1154 struct dwc2_hsotg_req *hs_req;
1155 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1156 struct dwc2_hsotg_ep *ep;
1157 int ret;
1158 bool halted;
1159 u32 recip;
1160 u32 wValue;
1161 u32 wIndex;
1162
1163 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1164 __func__, set ? "SET" : "CLEAR");
1165
1166 wValue = le16_to_cpu(ctrl->wValue);
1167 wIndex = le16_to_cpu(ctrl->wIndex);
1168 recip = ctrl->bRequestType & USB_RECIP_MASK;
1169
1170 switch (recip) {
1171 case USB_RECIP_DEVICE:
1172 switch (wValue) {
1173 case USB_DEVICE_TEST_MODE:
1174 if ((wIndex & 0xff) != 0)
1175 return -EINVAL;
1176 if (!set)
1177 return -EINVAL;
1178
1179 hsotg->test_mode = wIndex >> 8;
1180 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1181 if (ret) {
1182 dev_err(hsotg->dev,
1183 "%s: failed to send reply\n", __func__);
1184 return ret;
1185 }
1186 break;
1187 default:
1188 return -ENOENT;
1189 }
1190 break;
1191
1192 case USB_RECIP_ENDPOINT:
1193 ep = ep_from_windex(hsotg, wIndex);
1194 if (!ep) {
1195 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1196 __func__, wIndex);
1197 return -ENOENT;
1198 }
1199
1200 switch (wValue) {
1201 case USB_ENDPOINT_HALT:
1202 halted = ep->halted;
1203
1204 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1205
1206 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1207 if (ret) {
1208 dev_err(hsotg->dev,
1209 "%s: failed to send reply\n", __func__);
1210 return ret;
1211 }
1212
1213 /*
1214 * we have to complete all requests for ep if it was
1215 * halted, and the halt was cleared by CLEAR_FEATURE
1216 */
1217
1218 if (!set && halted) {
1219 /*
1220 * If we have request in progress,
1221 * then complete it
1222 */
1223 if (ep->req) {
1224 hs_req = ep->req;
1225 ep->req = NULL;
1226 list_del_init(&hs_req->queue);
1227 if (hs_req->req.complete) {
1228 spin_unlock(&hsotg->lock);
1229 usb_gadget_giveback_request(
1230 &ep->ep, &hs_req->req);
1231 spin_lock(&hsotg->lock);
1232 }
1233 }
1234
1235 /* If we have pending request, then start it */
1236 if (!ep->req) {
1237 dwc2_gadget_start_next_request(ep);
1238 }
1239 }
1240
1241 break;
1242
1243 default:
1244 return -ENOENT;
1245 }
1246 break;
1247 default:
1248 return -ENOENT;
1249 }
1250 return 1;
1251 }
1252
1253 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1254
1255 /**
1256 * dwc2_hsotg_stall_ep0 - stall ep0
1257 * @hsotg: The device state
1258 *
1259 * Set stall for ep0 as response for setup request.
1260 */
1261 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1262 {
1263 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1264 u32 reg;
1265 u32 ctrl;
1266
1267 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1268 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1269
1270 /*
1271 * DxEPCTL_Stall will be cleared by EP once it has
1272 * taken effect, so no need to clear later.
1273 */
1274
1275 ctrl = dwc2_readl(hsotg->regs + reg);
1276 ctrl |= DXEPCTL_STALL;
1277 ctrl |= DXEPCTL_CNAK;
1278 dwc2_writel(ctrl, hsotg->regs + reg);
1279
1280 dev_dbg(hsotg->dev,
1281 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1282 ctrl, reg, dwc2_readl(hsotg->regs + reg));
1283
1284 /*
1285 * complete won't be called, so we enqueue
1286 * setup request here
1287 */
1288 dwc2_hsotg_enqueue_setup(hsotg);
1289 }
1290
1291 /**
1292 * dwc2_hsotg_process_control - process a control request
1293 * @hsotg: The device state
1294 * @ctrl: The control request received
1295 *
1296 * The controller has received the SETUP phase of a control request, and
1297 * needs to work out what to do next (and whether to pass it on to the
1298 * gadget driver).
1299 */
1300 static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1301 struct usb_ctrlrequest *ctrl)
1302 {
1303 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1304 int ret = 0;
1305 u32 dcfg;
1306
1307 dev_dbg(hsotg->dev,
1308 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1309 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1310 ctrl->wIndex, ctrl->wLength);
1311
1312 if (ctrl->wLength == 0) {
1313 ep0->dir_in = 1;
1314 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1315 } else if (ctrl->bRequestType & USB_DIR_IN) {
1316 ep0->dir_in = 1;
1317 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1318 } else {
1319 ep0->dir_in = 0;
1320 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1321 }
1322
1323 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1324 switch (ctrl->bRequest) {
1325 case USB_REQ_SET_ADDRESS:
1326 hsotg->connected = 1;
1327 dcfg = dwc2_readl(hsotg->regs + DCFG);
1328 dcfg &= ~DCFG_DEVADDR_MASK;
1329 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1330 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1331 dwc2_writel(dcfg, hsotg->regs + DCFG);
1332
1333 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1334
1335 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1336 return;
1337
1338 case USB_REQ_GET_STATUS:
1339 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1340 break;
1341
1342 case USB_REQ_CLEAR_FEATURE:
1343 case USB_REQ_SET_FEATURE:
1344 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1345 break;
1346 }
1347 }
1348
1349 /* as a fallback, try delivering it to the driver to deal with */
1350
1351 if (ret == 0 && hsotg->driver) {
1352 spin_unlock(&hsotg->lock);
1353 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1354 spin_lock(&hsotg->lock);
1355 if (ret < 0)
1356 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1357 }
1358
1359 /*
1360 * the request is either unhandlable, or is not formatted correctly
1361 * so respond with a STALL for the status stage to indicate failure.
1362 */
1363
1364 if (ret < 0)
1365 dwc2_hsotg_stall_ep0(hsotg);
1366 }
1367
1368 /**
1369 * dwc2_hsotg_complete_setup - completion of a setup transfer
1370 * @ep: The endpoint the request was on.
1371 * @req: The request completed.
1372 *
1373 * Called on completion of any requests the driver itself submitted for
1374 * EP0 setup packets
1375 */
1376 static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1377 struct usb_request *req)
1378 {
1379 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1380 struct dwc2_hsotg *hsotg = hs_ep->parent;
1381
1382 if (req->status < 0) {
1383 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1384 return;
1385 }
1386
1387 spin_lock(&hsotg->lock);
1388 if (req->actual == 0)
1389 dwc2_hsotg_enqueue_setup(hsotg);
1390 else
1391 dwc2_hsotg_process_control(hsotg, req->buf);
1392 spin_unlock(&hsotg->lock);
1393 }
1394
1395 /**
1396 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1397 * @hsotg: The device state.
1398 *
1399 * Enqueue a request on EP0 if necessary to received any SETUP packets
1400 * received from the host.
1401 */
1402 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
1403 {
1404 struct usb_request *req = hsotg->ctrl_req;
1405 struct dwc2_hsotg_req *hs_req = our_req(req);
1406 int ret;
1407
1408 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1409
1410 req->zero = 0;
1411 req->length = 8;
1412 req->buf = hsotg->ctrl_buff;
1413 req->complete = dwc2_hsotg_complete_setup;
1414
1415 if (!list_empty(&hs_req->queue)) {
1416 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1417 return;
1418 }
1419
1420 hsotg->eps_out[0]->dir_in = 0;
1421 hsotg->eps_out[0]->send_zlp = 0;
1422 hsotg->ep0_state = DWC2_EP0_SETUP;
1423
1424 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
1425 if (ret < 0) {
1426 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1427 /*
1428 * Don't think there's much we can do other than watch the
1429 * driver fail.
1430 */
1431 }
1432 }
1433
1434 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1435 struct dwc2_hsotg_ep *hs_ep)
1436 {
1437 u32 ctrl;
1438 u8 index = hs_ep->index;
1439 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1440 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1441
1442 if (hs_ep->dir_in)
1443 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
1444 index);
1445 else
1446 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
1447 index);
1448
1449 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1450 DXEPTSIZ_XFERSIZE(0), hsotg->regs +
1451 epsiz_reg);
1452
1453 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1454 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1455 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1456 ctrl |= DXEPCTL_USBACTEP;
1457 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1458 }
1459
1460 /**
1461 * dwc2_hsotg_complete_request - complete a request given to us
1462 * @hsotg: The device state.
1463 * @hs_ep: The endpoint the request was on.
1464 * @hs_req: The request to complete.
1465 * @result: The result code (0 => Ok, otherwise errno)
1466 *
1467 * The given request has finished, so call the necessary completion
1468 * if it has one and then look to see if we can start a new request
1469 * on the endpoint.
1470 *
1471 * Note, expects the ep to already be locked as appropriate.
1472 */
1473 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1474 struct dwc2_hsotg_ep *hs_ep,
1475 struct dwc2_hsotg_req *hs_req,
1476 int result)
1477 {
1478
1479 if (!hs_req) {
1480 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1481 return;
1482 }
1483
1484 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1485 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1486
1487 /*
1488 * only replace the status if we've not already set an error
1489 * from a previous transaction
1490 */
1491
1492 if (hs_req->req.status == -EINPROGRESS)
1493 hs_req->req.status = result;
1494
1495 if (using_dma(hsotg))
1496 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1497
1498 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
1499
1500 hs_ep->req = NULL;
1501 list_del_init(&hs_req->queue);
1502
1503 /*
1504 * call the complete request with the locks off, just in case the
1505 * request tries to queue more work for this endpoint.
1506 */
1507
1508 if (hs_req->req.complete) {
1509 spin_unlock(&hsotg->lock);
1510 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
1511 spin_lock(&hsotg->lock);
1512 }
1513
1514 /*
1515 * Look to see if there is anything else to do. Note, the completion
1516 * of the previous request may have caused a new request to be started
1517 * so be careful when doing this.
1518 */
1519
1520 if (!hs_ep->req && result >= 0) {
1521 dwc2_gadget_start_next_request(hs_ep);
1522 }
1523 }
1524
1525 /**
1526 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
1527 * @hsotg: The device state.
1528 * @ep_idx: The endpoint index for the data
1529 * @size: The size of data in the fifo, in bytes
1530 *
1531 * The FIFO status shows there is data to read from the FIFO for a given
1532 * endpoint, so sort out whether we need to read the data into a request
1533 * that has been made for that endpoint.
1534 */
1535 static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
1536 {
1537 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
1538 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1539 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
1540 int to_read;
1541 int max_req;
1542 int read_ptr;
1543
1544
1545 if (!hs_req) {
1546 u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx));
1547 int ptr;
1548
1549 dev_dbg(hsotg->dev,
1550 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
1551 __func__, size, ep_idx, epctl);
1552
1553 /* dump the data from the FIFO, we've nothing we can do */
1554 for (ptr = 0; ptr < size; ptr += 4)
1555 (void)dwc2_readl(fifo);
1556
1557 return;
1558 }
1559
1560 to_read = size;
1561 read_ptr = hs_req->req.actual;
1562 max_req = hs_req->req.length - read_ptr;
1563
1564 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1565 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1566
1567 if (to_read > max_req) {
1568 /*
1569 * more data appeared than we where willing
1570 * to deal with in this request.
1571 */
1572
1573 /* currently we don't deal this */
1574 WARN_ON_ONCE(1);
1575 }
1576
1577 hs_ep->total_data += to_read;
1578 hs_req->req.actual += to_read;
1579 to_read = DIV_ROUND_UP(to_read, 4);
1580
1581 /*
1582 * note, we might over-write the buffer end by 3 bytes depending on
1583 * alignment of the data.
1584 */
1585 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
1586 }
1587
1588 /**
1589 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
1590 * @hsotg: The device instance
1591 * @dir_in: If IN zlp
1592 *
1593 * Generate a zero-length IN packet request for terminating a SETUP
1594 * transaction.
1595 *
1596 * Note, since we don't write any data to the TxFIFO, then it is
1597 * currently believed that we do not need to wait for any space in
1598 * the TxFIFO.
1599 */
1600 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
1601 {
1602 /* eps_out[0] is used in both directions */
1603 hsotg->eps_out[0]->dir_in = dir_in;
1604 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
1605
1606 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
1607 }
1608
1609 static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
1610 u32 epctl_reg)
1611 {
1612 u32 ctrl;
1613
1614 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1615 if (ctrl & DXEPCTL_EOFRNUM)
1616 ctrl |= DXEPCTL_SETEVENFR;
1617 else
1618 ctrl |= DXEPCTL_SETODDFR;
1619 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1620 }
1621
1622 /**
1623 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1624 * @hsotg: The device instance
1625 * @epnum: The endpoint received from
1626 *
1627 * The RXFIFO has delivered an OutDone event, which means that the data
1628 * transfer for an OUT endpoint has been completed, either by a short
1629 * packet or by the finish of a transfer.
1630 */
1631 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
1632 {
1633 u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum));
1634 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
1635 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1636 struct usb_request *req = &hs_req->req;
1637 unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1638 int result = 0;
1639
1640 if (!hs_req) {
1641 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1642 return;
1643 }
1644
1645 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
1646 dev_dbg(hsotg->dev, "zlp packet received\n");
1647 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1648 dwc2_hsotg_enqueue_setup(hsotg);
1649 return;
1650 }
1651
1652 if (using_dma(hsotg)) {
1653 unsigned size_done;
1654
1655 /*
1656 * Calculate the size of the transfer by checking how much
1657 * is left in the endpoint size register and then working it
1658 * out from the amount we loaded for the transfer.
1659 *
1660 * We need to do this as DMA pointers are always 32bit aligned
1661 * so may overshoot/undershoot the transfer.
1662 */
1663
1664 size_done = hs_ep->size_loaded - size_left;
1665 size_done += hs_ep->last_load;
1666
1667 req->actual = size_done;
1668 }
1669
1670 /* if there is more request to do, schedule new transfer */
1671 if (req->actual < req->length && size_left == 0) {
1672 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1673 return;
1674 }
1675
1676 if (req->actual < req->length && req->short_not_ok) {
1677 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1678 __func__, req->actual, req->length);
1679
1680 /*
1681 * todo - what should we return here? there's no one else
1682 * even bothering to check the status.
1683 */
1684 }
1685
1686 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
1687 /* Move to STATUS IN */
1688 dwc2_hsotg_ep0_zlp(hsotg, true);
1689 return;
1690 }
1691
1692 /*
1693 * Slave mode OUT transfers do not go through XferComplete so
1694 * adjust the ISOC parity here.
1695 */
1696 if (!using_dma(hsotg)) {
1697 if (hs_ep->isochronous && hs_ep->interval == 1)
1698 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
1699 else if (hs_ep->isochronous && hs_ep->interval > 1)
1700 dwc2_gadget_incr_frame_num(hs_ep);
1701 }
1702
1703 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1704 }
1705
1706 /**
1707 * dwc2_hsotg_handle_rx - RX FIFO has data
1708 * @hsotg: The device instance
1709 *
1710 * The IRQ handler has detected that the RX FIFO has some data in it
1711 * that requires processing, so find out what is in there and do the
1712 * appropriate read.
1713 *
1714 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1715 * chunks, so if you have x packets received on an endpoint you'll get x
1716 * FIFO events delivered, each with a packet's worth of data in it.
1717 *
1718 * When using DMA, we should not be processing events from the RXFIFO
1719 * as the actual data should be sent to the memory directly and we turn
1720 * on the completion interrupts to get notifications of transfer completion.
1721 */
1722 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
1723 {
1724 u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP);
1725 u32 epnum, status, size;
1726
1727 WARN_ON(using_dma(hsotg));
1728
1729 epnum = grxstsr & GRXSTS_EPNUM_MASK;
1730 status = grxstsr & GRXSTS_PKTSTS_MASK;
1731
1732 size = grxstsr & GRXSTS_BYTECNT_MASK;
1733 size >>= GRXSTS_BYTECNT_SHIFT;
1734
1735 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1736 __func__, grxstsr, size, epnum);
1737
1738 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
1739 case GRXSTS_PKTSTS_GLOBALOUTNAK:
1740 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
1741 break;
1742
1743 case GRXSTS_PKTSTS_OUTDONE:
1744 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1745 dwc2_hsotg_read_frameno(hsotg));
1746
1747 if (!using_dma(hsotg))
1748 dwc2_hsotg_handle_outdone(hsotg, epnum);
1749 break;
1750
1751 case GRXSTS_PKTSTS_SETUPDONE:
1752 dev_dbg(hsotg->dev,
1753 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1754 dwc2_hsotg_read_frameno(hsotg),
1755 dwc2_readl(hsotg->regs + DOEPCTL(0)));
1756 /*
1757 * Call dwc2_hsotg_handle_outdone here if it was not called from
1758 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
1759 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
1760 */
1761 if (hsotg->ep0_state == DWC2_EP0_SETUP)
1762 dwc2_hsotg_handle_outdone(hsotg, epnum);
1763 break;
1764
1765 case GRXSTS_PKTSTS_OUTRX:
1766 dwc2_hsotg_rx_data(hsotg, epnum, size);
1767 break;
1768
1769 case GRXSTS_PKTSTS_SETUPRX:
1770 dev_dbg(hsotg->dev,
1771 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1772 dwc2_hsotg_read_frameno(hsotg),
1773 dwc2_readl(hsotg->regs + DOEPCTL(0)));
1774
1775 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
1776
1777 dwc2_hsotg_rx_data(hsotg, epnum, size);
1778 break;
1779
1780 default:
1781 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1782 __func__, grxstsr);
1783
1784 dwc2_hsotg_dump(hsotg);
1785 break;
1786 }
1787 }
1788
1789 /**
1790 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
1791 * @mps: The maximum packet size in bytes.
1792 */
1793 static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
1794 {
1795 switch (mps) {
1796 case 64:
1797 return D0EPCTL_MPS_64;
1798 case 32:
1799 return D0EPCTL_MPS_32;
1800 case 16:
1801 return D0EPCTL_MPS_16;
1802 case 8:
1803 return D0EPCTL_MPS_8;
1804 }
1805
1806 /* bad max packet size, warn and return invalid result */
1807 WARN_ON(1);
1808 return (u32)-1;
1809 }
1810
1811 /**
1812 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1813 * @hsotg: The driver state.
1814 * @ep: The index number of the endpoint
1815 * @mps: The maximum packet size in bytes
1816 *
1817 * Configure the maximum packet size for the given endpoint, updating
1818 * the hardware control registers to reflect this.
1819 */
1820 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
1821 unsigned int ep, unsigned int mps, unsigned int dir_in)
1822 {
1823 struct dwc2_hsotg_ep *hs_ep;
1824 void __iomem *regs = hsotg->regs;
1825 u32 mpsval;
1826 u32 mcval;
1827 u32 reg;
1828
1829 hs_ep = index_to_ep(hsotg, ep, dir_in);
1830 if (!hs_ep)
1831 return;
1832
1833 if (ep == 0) {
1834 /* EP0 is a special case */
1835 mpsval = dwc2_hsotg_ep0_mps(mps);
1836 if (mpsval > 3)
1837 goto bad_mps;
1838 hs_ep->ep.maxpacket = mps;
1839 hs_ep->mc = 1;
1840 } else {
1841 mpsval = mps & DXEPCTL_MPS_MASK;
1842 if (mpsval > 1024)
1843 goto bad_mps;
1844 mcval = ((mps >> 11) & 0x3) + 1;
1845 hs_ep->mc = mcval;
1846 if (mcval > 3)
1847 goto bad_mps;
1848 hs_ep->ep.maxpacket = mpsval;
1849 }
1850
1851 if (dir_in) {
1852 reg = dwc2_readl(regs + DIEPCTL(ep));
1853 reg &= ~DXEPCTL_MPS_MASK;
1854 reg |= mpsval;
1855 dwc2_writel(reg, regs + DIEPCTL(ep));
1856 } else {
1857 reg = dwc2_readl(regs + DOEPCTL(ep));
1858 reg &= ~DXEPCTL_MPS_MASK;
1859 reg |= mpsval;
1860 dwc2_writel(reg, regs + DOEPCTL(ep));
1861 }
1862
1863 return;
1864
1865 bad_mps:
1866 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1867 }
1868
1869 /**
1870 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
1871 * @hsotg: The driver state
1872 * @idx: The index for the endpoint (0..15)
1873 */
1874 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
1875 {
1876 int timeout;
1877 int val;
1878
1879 dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
1880 hsotg->regs + GRSTCTL);
1881
1882 /* wait until the fifo is flushed */
1883 timeout = 100;
1884
1885 while (1) {
1886 val = dwc2_readl(hsotg->regs + GRSTCTL);
1887
1888 if ((val & (GRSTCTL_TXFFLSH)) == 0)
1889 break;
1890
1891 if (--timeout == 0) {
1892 dev_err(hsotg->dev,
1893 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1894 __func__, val);
1895 break;
1896 }
1897
1898 udelay(1);
1899 }
1900 }
1901
1902 /**
1903 * dwc2_hsotg_trytx - check to see if anything needs transmitting
1904 * @hsotg: The driver state
1905 * @hs_ep: The driver endpoint to check.
1906 *
1907 * Check to see if there is a request that has data to send, and if so
1908 * make an attempt to write data into the FIFO.
1909 */
1910 static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
1911 struct dwc2_hsotg_ep *hs_ep)
1912 {
1913 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1914
1915 if (!hs_ep->dir_in || !hs_req) {
1916 /**
1917 * if request is not enqueued, we disable interrupts
1918 * for endpoints, excepting ep0
1919 */
1920 if (hs_ep->index != 0)
1921 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
1922 hs_ep->dir_in, 0);
1923 return 0;
1924 }
1925
1926 if (hs_req->req.actual < hs_req->req.length) {
1927 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1928 hs_ep->index);
1929 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1930 }
1931
1932 return 0;
1933 }
1934
1935 /**
1936 * dwc2_hsotg_complete_in - complete IN transfer
1937 * @hsotg: The device state.
1938 * @hs_ep: The endpoint that has just completed.
1939 *
1940 * An IN transfer has been completed, update the transfer's state and then
1941 * call the relevant completion routines.
1942 */
1943 static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
1944 struct dwc2_hsotg_ep *hs_ep)
1945 {
1946 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1947 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1948 int size_left, size_done;
1949
1950 if (!hs_req) {
1951 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1952 return;
1953 }
1954
1955 /* Finish ZLP handling for IN EP0 transactions */
1956 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
1957 dev_dbg(hsotg->dev, "zlp packet sent\n");
1958 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1959 if (hsotg->test_mode) {
1960 int ret;
1961
1962 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
1963 if (ret < 0) {
1964 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
1965 hsotg->test_mode);
1966 dwc2_hsotg_stall_ep0(hsotg);
1967 return;
1968 }
1969 }
1970 dwc2_hsotg_enqueue_setup(hsotg);
1971 return;
1972 }
1973
1974 /*
1975 * Calculate the size of the transfer by checking how much is left
1976 * in the endpoint size register and then working it out from
1977 * the amount we loaded for the transfer.
1978 *
1979 * We do this even for DMA, as the transfer may have incremented
1980 * past the end of the buffer (DMA transfers are always 32bit
1981 * aligned).
1982 */
1983
1984 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1985
1986 size_done = hs_ep->size_loaded - size_left;
1987 size_done += hs_ep->last_load;
1988
1989 if (hs_req->req.actual != size_done)
1990 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1991 __func__, hs_req->req.actual, size_done);
1992
1993 hs_req->req.actual = size_done;
1994 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
1995 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
1996
1997 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1998 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1999 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2000 return;
2001 }
2002
2003 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
2004 if (hs_ep->send_zlp) {
2005 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2006 hs_ep->send_zlp = 0;
2007 /* transfer will be completed on next complete interrupt */
2008 return;
2009 }
2010
2011 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2012 /* Move to STATUS OUT */
2013 dwc2_hsotg_ep0_zlp(hsotg, false);
2014 return;
2015 }
2016
2017 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2018 }
2019
2020 /**
2021 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2022 * @hsotg: The device state.
2023 * @idx: Index of ep.
2024 * @dir_in: Endpoint direction 1-in 0-out.
2025 *
2026 * Reads for endpoint with given index and direction, by masking
2027 * epint_reg with coresponding mask.
2028 */
2029 static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2030 unsigned int idx, int dir_in)
2031 {
2032 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2033 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2034 u32 ints;
2035 u32 mask;
2036 u32 diepempmsk;
2037
2038 mask = dwc2_readl(hsotg->regs + epmsk_reg);
2039 diepempmsk = dwc2_readl(hsotg->regs + DIEPEMPMSK);
2040 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2041 mask |= DXEPINT_SETUP_RCVD;
2042
2043 ints = dwc2_readl(hsotg->regs + epint_reg);
2044 ints &= mask;
2045 return ints;
2046 }
2047
2048 /**
2049 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2050 * @hs_ep: The endpoint on which interrupt is asserted.
2051 *
2052 * This interrupt indicates that the endpoint has been disabled per the
2053 * application's request.
2054 *
2055 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2056 * in case of ISOC completes current request.
2057 *
2058 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2059 * request starts it.
2060 */
2061 static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2062 {
2063 struct dwc2_hsotg *hsotg = hs_ep->parent;
2064 struct dwc2_hsotg_req *hs_req;
2065 unsigned char idx = hs_ep->index;
2066 int dir_in = hs_ep->dir_in;
2067 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2068 int dctl = dwc2_readl(hsotg->regs + DCTL);
2069
2070 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2071
2072 if (dir_in) {
2073 int epctl = dwc2_readl(hsotg->regs + epctl_reg);
2074
2075 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2076
2077 if (hs_ep->isochronous) {
2078 dwc2_hsotg_complete_in(hsotg, hs_ep);
2079 return;
2080 }
2081
2082 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2083 int dctl = dwc2_readl(hsotg->regs + DCTL);
2084
2085 dctl |= DCTL_CGNPINNAK;
2086 dwc2_writel(dctl, hsotg->regs + DCTL);
2087 }
2088 return;
2089 }
2090
2091 if (dctl & DCTL_GOUTNAKSTS) {
2092 dctl |= DCTL_CGOUTNAK;
2093 dwc2_writel(dctl, hsotg->regs + DCTL);
2094 }
2095
2096 if (!hs_ep->isochronous)
2097 return;
2098
2099 if (list_empty(&hs_ep->queue)) {
2100 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2101 __func__, hs_ep);
2102 return;
2103 }
2104
2105 do {
2106 hs_req = get_ep_head(hs_ep);
2107 if (hs_req)
2108 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2109 -ENODATA);
2110 dwc2_gadget_incr_frame_num(hs_ep);
2111 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2112
2113 dwc2_gadget_start_next_request(hs_ep);
2114 }
2115
2116 /**
2117 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2118 * @hs_ep: The endpoint on which interrupt is asserted.
2119 *
2120 * This is starting point for ISOC-OUT transfer, synchronization done with
2121 * first out token received from host while corresponding EP is disabled.
2122 *
2123 * Device does not know initial frame in which out token will come. For this
2124 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2125 * getting this interrupt SW starts calculation for next transfer frame.
2126 */
2127 static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2128 {
2129 struct dwc2_hsotg *hsotg = ep->parent;
2130 int dir_in = ep->dir_in;
2131 u32 doepmsk;
2132
2133 if (dir_in || !ep->isochronous)
2134 return;
2135
2136 dwc2_hsotg_complete_request(hsotg, ep, get_ep_head(ep), -ENODATA);
2137
2138 if (ep->interval > 1 &&
2139 ep->target_frame == TARGET_FRAME_INITIAL) {
2140 u32 dsts;
2141 u32 ctrl;
2142
2143 dsts = dwc2_readl(hsotg->regs + DSTS);
2144 ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
2145 dwc2_gadget_incr_frame_num(ep);
2146
2147 ctrl = dwc2_readl(hsotg->regs + DOEPCTL(ep->index));
2148 if (ep->target_frame & 0x1)
2149 ctrl |= DXEPCTL_SETODDFR;
2150 else
2151 ctrl |= DXEPCTL_SETEVENFR;
2152
2153 dwc2_writel(ctrl, hsotg->regs + DOEPCTL(ep->index));
2154 }
2155
2156 dwc2_gadget_start_next_request(ep);
2157 doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
2158 doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK;
2159 dwc2_writel(doepmsk, hsotg->regs + DOEPMSK);
2160 }
2161
2162 /**
2163 * dwc2_gadget_handle_nak - handle NAK interrupt
2164 * @hs_ep: The endpoint on which interrupt is asserted.
2165 *
2166 * This is starting point for ISOC-IN transfer, synchronization done with
2167 * first IN token received from host while corresponding EP is disabled.
2168 *
2169 * Device does not know when first one token will arrive from host. On first
2170 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2171 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2172 * sent in response to that as there was no data in FIFO. SW is basing on this
2173 * interrupt to obtain frame in which token has come and then based on the
2174 * interval calculates next frame for transfer.
2175 */
2176 static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2177 {
2178 struct dwc2_hsotg *hsotg = hs_ep->parent;
2179 int dir_in = hs_ep->dir_in;
2180
2181 if (!dir_in || !hs_ep->isochronous)
2182 return;
2183
2184 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2185 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
2186 if (hs_ep->interval > 1) {
2187 u32 ctrl = dwc2_readl(hsotg->regs +
2188 DIEPCTL(hs_ep->index));
2189 if (hs_ep->target_frame & 0x1)
2190 ctrl |= DXEPCTL_SETODDFR;
2191 else
2192 ctrl |= DXEPCTL_SETEVENFR;
2193
2194 dwc2_writel(ctrl, hsotg->regs + DIEPCTL(hs_ep->index));
2195 }
2196
2197 dwc2_hsotg_complete_request(hsotg, hs_ep,
2198 get_ep_head(hs_ep), 0);
2199 }
2200
2201 dwc2_gadget_incr_frame_num(hs_ep);
2202 }
2203
2204 /**
2205 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
2206 * @hsotg: The driver state
2207 * @idx: The index for the endpoint (0..15)
2208 * @dir_in: Set if this is an IN endpoint
2209 *
2210 * Process and clear any interrupt pending for an individual endpoint
2211 */
2212 static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
2213 int dir_in)
2214 {
2215 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
2216 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2217 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2218 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
2219 u32 ints;
2220 u32 ctrl;
2221
2222 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
2223 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
2224
2225 /* Clear endpoint interrupts */
2226 dwc2_writel(ints, hsotg->regs + epint_reg);
2227
2228 if (!hs_ep) {
2229 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
2230 __func__, idx, dir_in ? "in" : "out");
2231 return;
2232 }
2233
2234 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
2235 __func__, idx, dir_in ? "in" : "out", ints);
2236
2237 /* Don't process XferCompl interrupt if it is a setup packet */
2238 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
2239 ints &= ~DXEPINT_XFERCOMPL;
2240
2241 if (ints & DXEPINT_STSPHSERCVD)
2242 dev_dbg(hsotg->dev, "%s: StsPhseRcvd asserted\n", __func__);
2243
2244 if (ints & DXEPINT_XFERCOMPL) {
2245 dev_dbg(hsotg->dev,
2246 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
2247 __func__, dwc2_readl(hsotg->regs + epctl_reg),
2248 dwc2_readl(hsotg->regs + epsiz_reg));
2249
2250 /*
2251 * we get OutDone from the FIFO, so we only need to look
2252 * at completing IN requests here
2253 */
2254 if (dir_in) {
2255 if (hs_ep->isochronous && hs_ep->interval > 1)
2256 dwc2_gadget_incr_frame_num(hs_ep);
2257
2258 dwc2_hsotg_complete_in(hsotg, hs_ep);
2259 if (ints & DXEPINT_NAKINTRPT)
2260 ints &= ~DXEPINT_NAKINTRPT;
2261
2262 if (idx == 0 && !hs_ep->req)
2263 dwc2_hsotg_enqueue_setup(hsotg);
2264 } else if (using_dma(hsotg)) {
2265 /*
2266 * We're using DMA, we need to fire an OutDone here
2267 * as we ignore the RXFIFO.
2268 */
2269 if (hs_ep->isochronous && hs_ep->interval > 1)
2270 dwc2_gadget_incr_frame_num(hs_ep);
2271
2272 dwc2_hsotg_handle_outdone(hsotg, idx);
2273 }
2274 }
2275
2276 if (ints & DXEPINT_EPDISBLD)
2277 dwc2_gadget_handle_ep_disabled(hs_ep);
2278
2279 if (ints & DXEPINT_OUTTKNEPDIS)
2280 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
2281
2282 if (ints & DXEPINT_NAKINTRPT)
2283 dwc2_gadget_handle_nak(hs_ep);
2284
2285 if (ints & DXEPINT_AHBERR)
2286 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
2287
2288 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
2289 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
2290
2291 if (using_dma(hsotg) && idx == 0) {
2292 /*
2293 * this is the notification we've received a
2294 * setup packet. In non-DMA mode we'd get this
2295 * from the RXFIFO, instead we need to process
2296 * the setup here.
2297 */
2298
2299 if (dir_in)
2300 WARN_ON_ONCE(1);
2301 else
2302 dwc2_hsotg_handle_outdone(hsotg, 0);
2303 }
2304 }
2305
2306 if (ints & DXEPINT_BACK2BACKSETUP)
2307 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
2308
2309 if (dir_in && !hs_ep->isochronous) {
2310 /* not sure if this is important, but we'll clear it anyway */
2311 if (ints & DXEPINT_INTKNTXFEMP) {
2312 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
2313 __func__, idx);
2314 }
2315
2316 /* this probably means something bad is happening */
2317 if (ints & DXEPINT_INTKNEPMIS) {
2318 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
2319 __func__, idx);
2320 }
2321
2322 /* FIFO has space or is empty (see GAHBCFG) */
2323 if (hsotg->dedicated_fifos &&
2324 ints & DXEPINT_TXFEMP) {
2325 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
2326 __func__, idx);
2327 if (!using_dma(hsotg))
2328 dwc2_hsotg_trytx(hsotg, hs_ep);
2329 }
2330 }
2331 }
2332
2333 /**
2334 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2335 * @hsotg: The device state.
2336 *
2337 * Handle updating the device settings after the enumeration phase has
2338 * been completed.
2339 */
2340 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
2341 {
2342 u32 dsts = dwc2_readl(hsotg->regs + DSTS);
2343 int ep0_mps = 0, ep_mps = 8;
2344
2345 /*
2346 * This should signal the finish of the enumeration phase
2347 * of the USB handshaking, so we should now know what rate
2348 * we connected at.
2349 */
2350
2351 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
2352
2353 /*
2354 * note, since we're limited by the size of transfer on EP0, and
2355 * it seems IN transfers must be a even number of packets we do
2356 * not advertise a 64byte MPS on EP0.
2357 */
2358
2359 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2360 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
2361 case DSTS_ENUMSPD_FS:
2362 case DSTS_ENUMSPD_FS48:
2363 hsotg->gadget.speed = USB_SPEED_FULL;
2364 ep0_mps = EP0_MPS_LIMIT;
2365 ep_mps = 1023;
2366 break;
2367
2368 case DSTS_ENUMSPD_HS:
2369 hsotg->gadget.speed = USB_SPEED_HIGH;
2370 ep0_mps = EP0_MPS_LIMIT;
2371 ep_mps = 1024;
2372 break;
2373
2374 case DSTS_ENUMSPD_LS:
2375 hsotg->gadget.speed = USB_SPEED_LOW;
2376 /*
2377 * note, we don't actually support LS in this driver at the
2378 * moment, and the documentation seems to imply that it isn't
2379 * supported by the PHYs on some of the devices.
2380 */
2381 break;
2382 }
2383 dev_info(hsotg->dev, "new device is %s\n",
2384 usb_speed_string(hsotg->gadget.speed));
2385
2386 /*
2387 * we should now know the maximum packet size for an
2388 * endpoint, so set the endpoints to a default value.
2389 */
2390
2391 if (ep0_mps) {
2392 int i;
2393 /* Initialize ep0 for both in and out directions */
2394 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 1);
2395 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0);
2396 for (i = 1; i < hsotg->num_of_eps; i++) {
2397 if (hsotg->eps_in[i])
2398 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 1);
2399 if (hsotg->eps_out[i])
2400 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 0);
2401 }
2402 }
2403
2404 /* ensure after enumeration our EP0 is active */
2405
2406 dwc2_hsotg_enqueue_setup(hsotg);
2407
2408 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2409 dwc2_readl(hsotg->regs + DIEPCTL0),
2410 dwc2_readl(hsotg->regs + DOEPCTL0));
2411 }
2412
2413 /**
2414 * kill_all_requests - remove all requests from the endpoint's queue
2415 * @hsotg: The device state.
2416 * @ep: The endpoint the requests may be on.
2417 * @result: The result code to use.
2418 *
2419 * Go through the requests on the given endpoint and mark them
2420 * completed with the given result code.
2421 */
2422 static void kill_all_requests(struct dwc2_hsotg *hsotg,
2423 struct dwc2_hsotg_ep *ep,
2424 int result)
2425 {
2426 struct dwc2_hsotg_req *req, *treq;
2427 unsigned size;
2428
2429 ep->req = NULL;
2430
2431 list_for_each_entry_safe(req, treq, &ep->queue, queue)
2432 dwc2_hsotg_complete_request(hsotg, ep, req,
2433 result);
2434
2435 if (!hsotg->dedicated_fifos)
2436 return;
2437 size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
2438 if (size < ep->fifo_size)
2439 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
2440 }
2441
2442 /**
2443 * dwc2_hsotg_disconnect - disconnect service
2444 * @hsotg: The device state.
2445 *
2446 * The device has been disconnected. Remove all current
2447 * transactions and signal the gadget driver that this
2448 * has happened.
2449 */
2450 void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
2451 {
2452 unsigned ep;
2453
2454 if (!hsotg->connected)
2455 return;
2456
2457 hsotg->connected = 0;
2458 hsotg->test_mode = 0;
2459
2460 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
2461 if (hsotg->eps_in[ep])
2462 kill_all_requests(hsotg, hsotg->eps_in[ep],
2463 -ESHUTDOWN);
2464 if (hsotg->eps_out[ep])
2465 kill_all_requests(hsotg, hsotg->eps_out[ep],
2466 -ESHUTDOWN);
2467 }
2468
2469 call_gadget(hsotg, disconnect);
2470 hsotg->lx_state = DWC2_L3;
2471 }
2472
2473 /**
2474 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2475 * @hsotg: The device state:
2476 * @periodic: True if this is a periodic FIFO interrupt
2477 */
2478 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
2479 {
2480 struct dwc2_hsotg_ep *ep;
2481 int epno, ret;
2482
2483 /* look through for any more data to transmit */
2484 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
2485 ep = index_to_ep(hsotg, epno, 1);
2486
2487 if (!ep)
2488 continue;
2489
2490 if (!ep->dir_in)
2491 continue;
2492
2493 if ((periodic && !ep->periodic) ||
2494 (!periodic && ep->periodic))
2495 continue;
2496
2497 ret = dwc2_hsotg_trytx(hsotg, ep);
2498 if (ret < 0)
2499 break;
2500 }
2501 }
2502
2503 /* IRQ flags which will trigger a retry around the IRQ loop */
2504 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
2505 GINTSTS_PTXFEMP | \
2506 GINTSTS_RXFLVL)
2507
2508 /**
2509 * dwc2_hsotg_core_init - issue softreset to the core
2510 * @hsotg: The device state
2511 *
2512 * Issue a soft reset to the core, and await the core finishing it.
2513 */
2514 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
2515 bool is_usb_reset)
2516 {
2517 u32 intmsk;
2518 u32 val;
2519 u32 usbcfg;
2520
2521 /* Kill any ep0 requests as controller will be reinitialized */
2522 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
2523
2524 if (!is_usb_reset)
2525 if (dwc2_core_reset(hsotg))
2526 return;
2527
2528 /*
2529 * we must now enable ep0 ready for host detection and then
2530 * set configuration.
2531 */
2532
2533 /* keep other bits untouched (so e.g. forced modes are not lost) */
2534 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2535 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
2536 GUSBCFG_HNPCAP);
2537
2538 /* set the PLL on, remove the HNP/SRP and set the PHY */
2539 val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
2540 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
2541 (val << GUSBCFG_USBTRDTIM_SHIFT);
2542 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2543
2544 dwc2_hsotg_init_fifo(hsotg);
2545
2546 if (!is_usb_reset)
2547 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2548
2549 dwc2_writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS, hsotg->regs + DCFG);
2550
2551 /* Clear any pending OTG interrupts */
2552 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
2553
2554 /* Clear any pending interrupts */
2555 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
2556 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
2557 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
2558 GINTSTS_USBRST | GINTSTS_RESETDET |
2559 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
2560 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
2561 GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
2562
2563 if (hsotg->core_params->external_id_pin_ctl <= 0)
2564 intmsk |= GINTSTS_CONIDSTSCHNG;
2565
2566 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
2567
2568 if (using_dma(hsotg))
2569 dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
2570 (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT),
2571 hsotg->regs + GAHBCFG);
2572 else
2573 dwc2_writel(((hsotg->dedicated_fifos) ?
2574 (GAHBCFG_NP_TXF_EMP_LVL |
2575 GAHBCFG_P_TXF_EMP_LVL) : 0) |
2576 GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG);
2577
2578 /*
2579 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2580 * when we have no data to transfer. Otherwise we get being flooded by
2581 * interrupts.
2582 */
2583
2584 dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
2585 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
2586 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
2587 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
2588 hsotg->regs + DIEPMSK);
2589
2590 /*
2591 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2592 * DMA mode we may need this.
2593 */
2594 dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK) : 0) |
2595 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
2596 DOEPMSK_SETUPMSK | DOEPMSK_STSPHSERCVDMSK,
2597 hsotg->regs + DOEPMSK);
2598
2599 dwc2_writel(0, hsotg->regs + DAINTMSK);
2600
2601 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2602 dwc2_readl(hsotg->regs + DIEPCTL0),
2603 dwc2_readl(hsotg->regs + DOEPCTL0));
2604
2605 /* enable in and out endpoint interrupts */
2606 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
2607
2608 /*
2609 * Enable the RXFIFO when in slave mode, as this is how we collect
2610 * the data. In DMA mode, we get events from the FIFO but also
2611 * things we cannot process, so do not use it.
2612 */
2613 if (!using_dma(hsotg))
2614 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
2615
2616 /* Enable interrupts for EP0 in and out */
2617 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2618 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2619
2620 if (!is_usb_reset) {
2621 __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2622 udelay(10); /* see openiboot */
2623 __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2624 }
2625
2626 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL));
2627
2628 /*
2629 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2630 * writing to the EPCTL register..
2631 */
2632
2633 /* set to read 1 8byte packet */
2634 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2635 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
2636
2637 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
2638 DXEPCTL_CNAK | DXEPCTL_EPENA |
2639 DXEPCTL_USBACTEP,
2640 hsotg->regs + DOEPCTL0);
2641
2642 /* enable, but don't activate EP0in */
2643 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
2644 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
2645
2646 dwc2_hsotg_enqueue_setup(hsotg);
2647
2648 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2649 dwc2_readl(hsotg->regs + DIEPCTL0),
2650 dwc2_readl(hsotg->regs + DOEPCTL0));
2651
2652 /* clear global NAKs */
2653 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
2654 if (!is_usb_reset)
2655 val |= DCTL_SFTDISCON;
2656 __orr32(hsotg->regs + DCTL, val);
2657
2658 /* must be at-least 3ms to allow bus to see disconnect */
2659 mdelay(3);
2660
2661 hsotg->lx_state = DWC2_L0;
2662 }
2663
2664 static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
2665 {
2666 /* set the soft-disconnect bit */
2667 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2668 }
2669
2670 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
2671 {
2672 /* remove the soft-disconnect and let's go */
2673 __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2674 }
2675
2676 /**
2677 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
2678 * @hsotg: The device state:
2679 *
2680 * This interrupt indicates one of the following conditions occurred while
2681 * transmitting an ISOC transaction.
2682 * - Corrupted IN Token for ISOC EP.
2683 * - Packet not complete in FIFO.
2684 *
2685 * The following actions will be taken:
2686 * - Determine the EP
2687 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
2688 */
2689 static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
2690 {
2691 struct dwc2_hsotg_ep *hs_ep;
2692 u32 epctrl;
2693 u32 idx;
2694
2695 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
2696
2697 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
2698 hs_ep = hsotg->eps_in[idx];
2699 epctrl = dwc2_readl(hsotg->regs + DIEPCTL(idx));
2700 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous &&
2701 dwc2_gadget_target_frame_elapsed(hs_ep)) {
2702 epctrl |= DXEPCTL_SNAK;
2703 epctrl |= DXEPCTL_EPDIS;
2704 dwc2_writel(epctrl, hsotg->regs + DIEPCTL(idx));
2705 }
2706 }
2707
2708 /* Clear interrupt */
2709 dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS);
2710 }
2711
2712 /**
2713 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
2714 * @hsotg: The device state:
2715 *
2716 * This interrupt indicates one of the following conditions occurred while
2717 * transmitting an ISOC transaction.
2718 * - Corrupted OUT Token for ISOC EP.
2719 * - Packet not complete in FIFO.
2720 *
2721 * The following actions will be taken:
2722 * - Determine the EP
2723 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
2724 */
2725 static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
2726 {
2727 u32 gintsts;
2728 u32 gintmsk;
2729 u32 epctrl;
2730 struct dwc2_hsotg_ep *hs_ep;
2731 int idx;
2732
2733 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
2734
2735 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
2736 hs_ep = hsotg->eps_out[idx];
2737 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx));
2738 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous &&
2739 dwc2_gadget_target_frame_elapsed(hs_ep)) {
2740 /* Unmask GOUTNAKEFF interrupt */
2741 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
2742 gintmsk |= GINTSTS_GOUTNAKEFF;
2743 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
2744
2745 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
2746 if (!(gintsts & GINTSTS_GOUTNAKEFF))
2747 __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
2748 }
2749 }
2750
2751 /* Clear interrupt */
2752 dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS);
2753 }
2754
2755 /**
2756 * dwc2_hsotg_irq - handle device interrupt
2757 * @irq: The IRQ number triggered
2758 * @pw: The pw value when registered the handler.
2759 */
2760 static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
2761 {
2762 struct dwc2_hsotg *hsotg = pw;
2763 int retry_count = 8;
2764 u32 gintsts;
2765 u32 gintmsk;
2766
2767 if (!dwc2_is_device_mode(hsotg))
2768 return IRQ_NONE;
2769
2770 spin_lock(&hsotg->lock);
2771 irq_retry:
2772 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
2773 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
2774
2775 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2776 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2777
2778 gintsts &= gintmsk;
2779
2780 if (gintsts & GINTSTS_RESETDET) {
2781 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
2782
2783 dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS);
2784
2785 /* This event must be used only if controller is suspended */
2786 if (hsotg->lx_state == DWC2_L2) {
2787 dwc2_exit_hibernation(hsotg, true);
2788 hsotg->lx_state = DWC2_L0;
2789 }
2790 }
2791
2792 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
2793
2794 u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL);
2795 u32 connected = hsotg->connected;
2796
2797 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
2798 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2799 dwc2_readl(hsotg->regs + GNPTXSTS));
2800
2801 dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
2802
2803 /* Report disconnection if it is not already done. */
2804 dwc2_hsotg_disconnect(hsotg);
2805
2806 if (usb_status & GOTGCTL_BSESVLD && connected)
2807 dwc2_hsotg_core_init_disconnected(hsotg, true);
2808 }
2809
2810 if (gintsts & GINTSTS_ENUMDONE) {
2811 dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
2812
2813 dwc2_hsotg_irq_enumdone(hsotg);
2814 }
2815
2816 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
2817 u32 daint = dwc2_readl(hsotg->regs + DAINT);
2818 u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
2819 u32 daint_out, daint_in;
2820 int ep;
2821
2822 daint &= daintmsk;
2823 daint_out = daint >> DAINT_OUTEP_SHIFT;
2824 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
2825
2826 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2827
2828 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
2829 ep++, daint_out >>= 1) {
2830 if (daint_out & 1)
2831 dwc2_hsotg_epint(hsotg, ep, 0);
2832 }
2833
2834 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
2835 ep++, daint_in >>= 1) {
2836 if (daint_in & 1)
2837 dwc2_hsotg_epint(hsotg, ep, 1);
2838 }
2839 }
2840
2841 /* check both FIFOs */
2842
2843 if (gintsts & GINTSTS_NPTXFEMP) {
2844 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2845
2846 /*
2847 * Disable the interrupt to stop it happening again
2848 * unless one of these endpoint routines decides that
2849 * it needs re-enabling
2850 */
2851
2852 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
2853 dwc2_hsotg_irq_fifoempty(hsotg, false);
2854 }
2855
2856 if (gintsts & GINTSTS_PTXFEMP) {
2857 dev_dbg(hsotg->dev, "PTxFEmp\n");
2858
2859 /* See note in GINTSTS_NPTxFEmp */
2860
2861 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
2862 dwc2_hsotg_irq_fifoempty(hsotg, true);
2863 }
2864
2865 if (gintsts & GINTSTS_RXFLVL) {
2866 /*
2867 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2868 * we need to retry dwc2_hsotg_handle_rx if this is still
2869 * set.
2870 */
2871
2872 dwc2_hsotg_handle_rx(hsotg);
2873 }
2874
2875 if (gintsts & GINTSTS_ERLYSUSP) {
2876 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
2877 dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
2878 }
2879
2880 /*
2881 * these next two seem to crop-up occasionally causing the core
2882 * to shutdown the USB transfer, so try clearing them and logging
2883 * the occurrence.
2884 */
2885
2886 if (gintsts & GINTSTS_GOUTNAKEFF) {
2887 u8 idx;
2888 u32 epctrl;
2889 u32 gintmsk;
2890 struct dwc2_hsotg_ep *hs_ep;
2891
2892 /* Mask this interrupt */
2893 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
2894 gintmsk &= ~GINTSTS_GOUTNAKEFF;
2895 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
2896
2897 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
2898 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
2899 hs_ep = hsotg->eps_out[idx];
2900 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx));
2901
2902 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
2903 epctrl |= DXEPCTL_SNAK;
2904 epctrl |= DXEPCTL_EPDIS;
2905 dwc2_writel(epctrl, hsotg->regs + DOEPCTL(idx));
2906 }
2907 }
2908
2909 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
2910 }
2911
2912 if (gintsts & GINTSTS_GINNAKEFF) {
2913 dev_info(hsotg->dev, "GINNakEff triggered\n");
2914
2915 __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK);
2916
2917 dwc2_hsotg_dump(hsotg);
2918 }
2919
2920 if (gintsts & GINTSTS_INCOMPL_SOIN)
2921 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
2922
2923 if (gintsts & GINTSTS_INCOMPL_SOOUT)
2924 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
2925
2926 /*
2927 * if we've had fifo events, we should try and go around the
2928 * loop again to see if there's any point in returning yet.
2929 */
2930
2931 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2932 goto irq_retry;
2933
2934 spin_unlock(&hsotg->lock);
2935
2936 return IRQ_HANDLED;
2937 }
2938
2939 /**
2940 * dwc2_hsotg_ep_enable - enable the given endpoint
2941 * @ep: The USB endpint to configure
2942 * @desc: The USB endpoint descriptor to configure with.
2943 *
2944 * This is called from the USB gadget code's usb_ep_enable().
2945 */
2946 static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
2947 const struct usb_endpoint_descriptor *desc)
2948 {
2949 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2950 struct dwc2_hsotg *hsotg = hs_ep->parent;
2951 unsigned long flags;
2952 unsigned int index = hs_ep->index;
2953 u32 epctrl_reg;
2954 u32 epctrl;
2955 u32 mps;
2956 u32 mask;
2957 unsigned int dir_in;
2958 unsigned int i, val, size;
2959 int ret = 0;
2960
2961 dev_dbg(hsotg->dev,
2962 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2963 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2964 desc->wMaxPacketSize, desc->bInterval);
2965
2966 /* not to be called for EP0 */
2967 if (index == 0) {
2968 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
2969 return -EINVAL;
2970 }
2971
2972 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2973 if (dir_in != hs_ep->dir_in) {
2974 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2975 return -EINVAL;
2976 }
2977
2978 mps = usb_endpoint_maxp(desc);
2979
2980 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
2981
2982 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2983 epctrl = dwc2_readl(hsotg->regs + epctrl_reg);
2984
2985 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2986 __func__, epctrl, epctrl_reg);
2987
2988 spin_lock_irqsave(&hsotg->lock, flags);
2989
2990 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
2991 epctrl |= DXEPCTL_MPS(mps);
2992
2993 /*
2994 * mark the endpoint as active, otherwise the core may ignore
2995 * transactions entirely for this endpoint
2996 */
2997 epctrl |= DXEPCTL_USBACTEP;
2998
2999 /* update the endpoint state */
3000 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, dir_in);
3001
3002 /* default, set to non-periodic */
3003 hs_ep->isochronous = 0;
3004 hs_ep->periodic = 0;
3005 hs_ep->halted = 0;
3006 hs_ep->interval = desc->bInterval;
3007
3008 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
3009 case USB_ENDPOINT_XFER_ISOC:
3010 epctrl |= DXEPCTL_EPTYPE_ISO;
3011 epctrl |= DXEPCTL_SETEVENFR;
3012 hs_ep->isochronous = 1;
3013 hs_ep->interval = 1 << (desc->bInterval - 1);
3014 hs_ep->target_frame = TARGET_FRAME_INITIAL;
3015 if (dir_in) {
3016 hs_ep->periodic = 1;
3017 mask = dwc2_readl(hsotg->regs + DIEPMSK);
3018 mask |= DIEPMSK_NAKMSK;
3019 dwc2_writel(mask, hsotg->regs + DIEPMSK);
3020 } else {
3021 mask = dwc2_readl(hsotg->regs + DOEPMSK);
3022 mask |= DOEPMSK_OUTTKNEPDISMSK;
3023 dwc2_writel(mask, hsotg->regs + DOEPMSK);
3024 }
3025 break;
3026
3027 case USB_ENDPOINT_XFER_BULK:
3028 epctrl |= DXEPCTL_EPTYPE_BULK;
3029 break;
3030
3031 case USB_ENDPOINT_XFER_INT:
3032 if (dir_in)
3033 hs_ep->periodic = 1;
3034
3035 if (hsotg->gadget.speed == USB_SPEED_HIGH)
3036 hs_ep->interval = 1 << (desc->bInterval - 1);
3037
3038 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
3039 break;
3040
3041 case USB_ENDPOINT_XFER_CONTROL:
3042 epctrl |= DXEPCTL_EPTYPE_CONTROL;
3043 break;
3044 }
3045
3046 /*
3047 * if the hardware has dedicated fifos, we must give each IN EP
3048 * a unique tx-fifo even if it is non-periodic.
3049 */
3050 if (dir_in && hsotg->dedicated_fifos) {
3051 u32 fifo_index = 0;
3052 u32 fifo_size = UINT_MAX;
3053 size = hs_ep->ep.maxpacket*hs_ep->mc;
3054 for (i = 1; i < hsotg->num_of_eps; ++i) {
3055 if (hsotg->fifo_map & (1<<i))
3056 continue;
3057 val = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
3058 val = (val >> FIFOSIZE_DEPTH_SHIFT)*4;
3059 if (val < size)
3060 continue;
3061 /* Search for smallest acceptable fifo */
3062 if (val < fifo_size) {
3063 fifo_size = val;
3064 fifo_index = i;
3065 }
3066 }
3067 if (!fifo_index) {
3068 dev_err(hsotg->dev,
3069 "%s: No suitable fifo found\n", __func__);
3070 ret = -ENOMEM;
3071 goto error;
3072 }
3073 hsotg->fifo_map |= 1 << fifo_index;
3074 epctrl |= DXEPCTL_TXFNUM(fifo_index);
3075 hs_ep->fifo_index = fifo_index;
3076 hs_ep->fifo_size = fifo_size;
3077 }
3078
3079 /* for non control endpoints, set PID to D0 */
3080 if (index && !hs_ep->isochronous)
3081 epctrl |= DXEPCTL_SETD0PID;
3082
3083 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
3084 __func__, epctrl);
3085
3086 dwc2_writel(epctrl, hsotg->regs + epctrl_reg);
3087 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
3088 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
3089
3090 /* enable the endpoint interrupt */
3091 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
3092
3093 error:
3094 spin_unlock_irqrestore(&hsotg->lock, flags);
3095 return ret;
3096 }
3097
3098 /**
3099 * dwc2_hsotg_ep_disable - disable given endpoint
3100 * @ep: The endpoint to disable.
3101 */
3102 static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
3103 {
3104 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3105 struct dwc2_hsotg *hsotg = hs_ep->parent;
3106 int dir_in = hs_ep->dir_in;
3107 int index = hs_ep->index;
3108 unsigned long flags;
3109 u32 epctrl_reg;
3110 u32 ctrl;
3111
3112 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
3113
3114 if (ep == &hsotg->eps_out[0]->ep) {
3115 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
3116 return -EINVAL;
3117 }
3118
3119 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
3120
3121 spin_lock_irqsave(&hsotg->lock, flags);
3122
3123 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
3124 ctrl &= ~DXEPCTL_EPENA;
3125 ctrl &= ~DXEPCTL_USBACTEP;
3126 ctrl |= DXEPCTL_SNAK;
3127
3128 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
3129 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
3130
3131 /* disable endpoint interrupts */
3132 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
3133
3134 /* terminate all requests with shutdown */
3135 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
3136
3137 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
3138 hs_ep->fifo_index = 0;
3139 hs_ep->fifo_size = 0;
3140
3141 spin_unlock_irqrestore(&hsotg->lock, flags);
3142 return 0;
3143 }
3144
3145 /**
3146 * on_list - check request is on the given endpoint
3147 * @ep: The endpoint to check.
3148 * @test: The request to test if it is on the endpoint.
3149 */
3150 static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
3151 {
3152 struct dwc2_hsotg_req *req, *treq;
3153
3154 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
3155 if (req == test)
3156 return true;
3157 }
3158
3159 return false;
3160 }
3161
3162 static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg,
3163 u32 bit, u32 timeout)
3164 {
3165 u32 i;
3166
3167 for (i = 0; i < timeout; i++) {
3168 if (dwc2_readl(hs_otg->regs + reg) & bit)
3169 return 0;
3170 udelay(1);
3171 }
3172
3173 return -ETIMEDOUT;
3174 }
3175
3176 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3177 struct dwc2_hsotg_ep *hs_ep)
3178 {
3179 u32 epctrl_reg;
3180 u32 epint_reg;
3181
3182 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3183 DOEPCTL(hs_ep->index);
3184 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3185 DOEPINT(hs_ep->index);
3186
3187 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3188 hs_ep->name);
3189 if (hs_ep->dir_in) {
3190 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK);
3191 /* Wait for Nak effect */
3192 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3193 DXEPINT_INEPNAKEFF, 100))
3194 dev_warn(hsotg->dev,
3195 "%s: timeout DIEPINT.NAKEFF\n", __func__);
3196 } else {
3197 if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF))
3198 __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
3199
3200 /* Wait for global nak to take effect */
3201 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3202 GINTSTS_GOUTNAKEFF, 100))
3203 dev_warn(hsotg->dev,
3204 "%s: timeout GINTSTS.GOUTNAKEFF\n", __func__);
3205 }
3206
3207 /* Disable ep */
3208 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3209
3210 /* Wait for ep to be disabled */
3211 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3212 dev_warn(hsotg->dev,
3213 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3214
3215 if (hs_ep->dir_in) {
3216 if (hsotg->dedicated_fifos) {
3217 dwc2_writel(GRSTCTL_TXFNUM(hs_ep->fifo_index) |
3218 GRSTCTL_TXFFLSH, hsotg->regs + GRSTCTL);
3219 /* Wait for fifo flush */
3220 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL,
3221 GRSTCTL_TXFFLSH, 100))
3222 dev_warn(hsotg->dev,
3223 "%s: timeout flushing fifos\n",
3224 __func__);
3225 }
3226 /* TODO: Flush shared tx fifo */
3227 } else {
3228 /* Remove global NAKs */
3229 __bic32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
3230 }
3231 }
3232
3233 /**
3234 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
3235 * @ep: The endpoint to dequeue.
3236 * @req: The request to be removed from a queue.
3237 */
3238 static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
3239 {
3240 struct dwc2_hsotg_req *hs_req = our_req(req);
3241 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3242 struct dwc2_hsotg *hs = hs_ep->parent;
3243 unsigned long flags;
3244
3245 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
3246
3247 spin_lock_irqsave(&hs->lock, flags);
3248
3249 if (!on_list(hs_ep, hs_req)) {
3250 spin_unlock_irqrestore(&hs->lock, flags);
3251 return -EINVAL;
3252 }
3253
3254 /* Dequeue already started request */
3255 if (req == &hs_ep->req->req)
3256 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
3257
3258 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
3259 spin_unlock_irqrestore(&hs->lock, flags);
3260
3261 return 0;
3262 }
3263
3264 /**
3265 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
3266 * @ep: The endpoint to set halt.
3267 * @value: Set or unset the halt.
3268 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
3269 * the endpoint is busy processing requests.
3270 *
3271 * We need to stall the endpoint immediately if request comes from set_feature
3272 * protocol command handler.
3273 */
3274 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
3275 {
3276 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3277 struct dwc2_hsotg *hs = hs_ep->parent;
3278 int index = hs_ep->index;
3279 u32 epreg;
3280 u32 epctl;
3281 u32 xfertype;
3282
3283 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
3284
3285 if (index == 0) {
3286 if (value)
3287 dwc2_hsotg_stall_ep0(hs);
3288 else
3289 dev_warn(hs->dev,
3290 "%s: can't clear halt on ep0\n", __func__);
3291 return 0;
3292 }
3293
3294 if (hs_ep->isochronous) {
3295 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
3296 return -EINVAL;
3297 }
3298
3299 if (!now && value && !list_empty(&hs_ep->queue)) {
3300 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
3301 ep->name);
3302 return -EAGAIN;
3303 }
3304
3305 if (hs_ep->dir_in) {
3306 epreg = DIEPCTL(index);
3307 epctl = dwc2_readl(hs->regs + epreg);
3308
3309 if (value) {
3310 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
3311 if (epctl & DXEPCTL_EPENA)
3312 epctl |= DXEPCTL_EPDIS;
3313 } else {
3314 epctl &= ~DXEPCTL_STALL;
3315 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
3316 if (xfertype == DXEPCTL_EPTYPE_BULK ||
3317 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
3318 epctl |= DXEPCTL_SETD0PID;
3319 }
3320 dwc2_writel(epctl, hs->regs + epreg);
3321 } else {
3322
3323 epreg = DOEPCTL(index);
3324 epctl = dwc2_readl(hs->regs + epreg);
3325
3326 if (value)
3327 epctl |= DXEPCTL_STALL;
3328 else {
3329 epctl &= ~DXEPCTL_STALL;
3330 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
3331 if (xfertype == DXEPCTL_EPTYPE_BULK ||
3332 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
3333 epctl |= DXEPCTL_SETD0PID;
3334 }
3335 dwc2_writel(epctl, hs->regs + epreg);
3336 }
3337
3338 hs_ep->halted = value;
3339
3340 return 0;
3341 }
3342
3343 /**
3344 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
3345 * @ep: The endpoint to set halt.
3346 * @value: Set or unset the halt.
3347 */
3348 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
3349 {
3350 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3351 struct dwc2_hsotg *hs = hs_ep->parent;
3352 unsigned long flags = 0;
3353 int ret = 0;
3354
3355 spin_lock_irqsave(&hs->lock, flags);
3356 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
3357 spin_unlock_irqrestore(&hs->lock, flags);
3358
3359 return ret;
3360 }
3361
3362 static struct usb_ep_ops dwc2_hsotg_ep_ops = {
3363 .enable = dwc2_hsotg_ep_enable,
3364 .disable = dwc2_hsotg_ep_disable,
3365 .alloc_request = dwc2_hsotg_ep_alloc_request,
3366 .free_request = dwc2_hsotg_ep_free_request,
3367 .queue = dwc2_hsotg_ep_queue_lock,
3368 .dequeue = dwc2_hsotg_ep_dequeue,
3369 .set_halt = dwc2_hsotg_ep_sethalt_lock,
3370 /* note, don't believe we have any call for the fifo routines */
3371 };
3372
3373 /**
3374 * dwc2_hsotg_init - initalize the usb core
3375 * @hsotg: The driver state
3376 */
3377 static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
3378 {
3379 u32 trdtim;
3380 u32 usbcfg;
3381 /* unmask subset of endpoint interrupts */
3382
3383 dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
3384 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
3385 hsotg->regs + DIEPMSK);
3386
3387 dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
3388 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
3389 hsotg->regs + DOEPMSK);
3390
3391 dwc2_writel(0, hsotg->regs + DAINTMSK);
3392
3393 /* Be in disconnected state until gadget is registered */
3394 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
3395
3396 /* setup fifos */
3397
3398 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3399 dwc2_readl(hsotg->regs + GRXFSIZ),
3400 dwc2_readl(hsotg->regs + GNPTXFSIZ));
3401
3402 dwc2_hsotg_init_fifo(hsotg);
3403
3404 /* keep other bits untouched (so e.g. forced modes are not lost) */
3405 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
3406 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
3407 GUSBCFG_HNPCAP);
3408
3409 /* set the PLL on, remove the HNP/SRP and set the PHY */
3410 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
3411 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
3412 (trdtim << GUSBCFG_USBTRDTIM_SHIFT);
3413 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
3414
3415 if (using_dma(hsotg))
3416 __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN);
3417 }
3418
3419 /**
3420 * dwc2_hsotg_udc_start - prepare the udc for work
3421 * @gadget: The usb gadget state
3422 * @driver: The usb gadget driver
3423 *
3424 * Perform initialization to prepare udc device and driver
3425 * to work.
3426 */
3427 static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
3428 struct usb_gadget_driver *driver)
3429 {
3430 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3431 unsigned long flags;
3432 int ret;
3433
3434 if (!hsotg) {
3435 pr_err("%s: called with no device\n", __func__);
3436 return -ENODEV;
3437 }
3438
3439 if (!driver) {
3440 dev_err(hsotg->dev, "%s: no driver\n", __func__);
3441 return -EINVAL;
3442 }
3443
3444 if (driver->max_speed < USB_SPEED_FULL)
3445 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
3446
3447 if (!driver->setup) {
3448 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
3449 return -EINVAL;
3450 }
3451
3452 WARN_ON(hsotg->driver);
3453
3454 driver->driver.bus = NULL;
3455 hsotg->driver = driver;
3456 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
3457 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3458
3459 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
3460 ret = dwc2_lowlevel_hw_enable(hsotg);
3461 if (ret)
3462 goto err;
3463 }
3464
3465 if (!IS_ERR_OR_NULL(hsotg->uphy))
3466 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
3467
3468 spin_lock_irqsave(&hsotg->lock, flags);
3469 if (dwc2_hw_is_device(hsotg)) {
3470 dwc2_hsotg_init(hsotg);
3471 dwc2_hsotg_core_init_disconnected(hsotg, false);
3472 }
3473
3474 hsotg->enabled = 0;
3475 spin_unlock_irqrestore(&hsotg->lock, flags);
3476
3477 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
3478
3479 return 0;
3480
3481 err:
3482 hsotg->driver = NULL;
3483 return ret;
3484 }
3485
3486 /**
3487 * dwc2_hsotg_udc_stop - stop the udc
3488 * @gadget: The usb gadget state
3489 * @driver: The usb gadget driver
3490 *
3491 * Stop udc hw block and stay tunned for future transmissions
3492 */
3493 static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
3494 {
3495 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3496 unsigned long flags = 0;
3497 int ep;
3498
3499 if (!hsotg)
3500 return -ENODEV;
3501
3502 /* all endpoints should be shutdown */
3503 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3504 if (hsotg->eps_in[ep])
3505 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3506 if (hsotg->eps_out[ep])
3507 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3508 }
3509
3510 spin_lock_irqsave(&hsotg->lock, flags);
3511
3512 hsotg->driver = NULL;
3513 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3514 hsotg->enabled = 0;
3515
3516 spin_unlock_irqrestore(&hsotg->lock, flags);
3517
3518 if (!IS_ERR_OR_NULL(hsotg->uphy))
3519 otg_set_peripheral(hsotg->uphy->otg, NULL);
3520
3521 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
3522 dwc2_lowlevel_hw_disable(hsotg);
3523
3524 return 0;
3525 }
3526
3527 /**
3528 * dwc2_hsotg_gadget_getframe - read the frame number
3529 * @gadget: The usb gadget state
3530 *
3531 * Read the {micro} frame number
3532 */
3533 static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
3534 {
3535 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
3536 }
3537
3538 /**
3539 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
3540 * @gadget: The usb gadget state
3541 * @is_on: Current state of the USB PHY
3542 *
3543 * Connect/Disconnect the USB PHY pullup
3544 */
3545 static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
3546 {
3547 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3548 unsigned long flags = 0;
3549
3550 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
3551 hsotg->op_state);
3552
3553 /* Don't modify pullup state while in host mode */
3554 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
3555 hsotg->enabled = is_on;
3556 return 0;
3557 }
3558
3559 spin_lock_irqsave(&hsotg->lock, flags);
3560 if (is_on) {
3561 hsotg->enabled = 1;
3562 dwc2_hsotg_core_init_disconnected(hsotg, false);
3563 dwc2_hsotg_core_connect(hsotg);
3564 } else {
3565 dwc2_hsotg_core_disconnect(hsotg);
3566 dwc2_hsotg_disconnect(hsotg);
3567 hsotg->enabled = 0;
3568 }
3569
3570 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3571 spin_unlock_irqrestore(&hsotg->lock, flags);
3572
3573 return 0;
3574 }
3575
3576 static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
3577 {
3578 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3579 unsigned long flags;
3580
3581 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
3582 spin_lock_irqsave(&hsotg->lock, flags);
3583
3584 /*
3585 * If controller is hibernated, it must exit from hibernation
3586 * before being initialized / de-initialized
3587 */
3588 if (hsotg->lx_state == DWC2_L2)
3589 dwc2_exit_hibernation(hsotg, false);
3590
3591 if (is_active) {
3592 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3593
3594 dwc2_hsotg_core_init_disconnected(hsotg, false);
3595 if (hsotg->enabled)
3596 dwc2_hsotg_core_connect(hsotg);
3597 } else {
3598 dwc2_hsotg_core_disconnect(hsotg);
3599 dwc2_hsotg_disconnect(hsotg);
3600 }
3601
3602 spin_unlock_irqrestore(&hsotg->lock, flags);
3603 return 0;
3604 }
3605
3606 /**
3607 * dwc2_hsotg_vbus_draw - report bMaxPower field
3608 * @gadget: The usb gadget state
3609 * @mA: Amount of current
3610 *
3611 * Report how much power the device may consume to the phy.
3612 */
3613 static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned mA)
3614 {
3615 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3616
3617 if (IS_ERR_OR_NULL(hsotg->uphy))
3618 return -ENOTSUPP;
3619 return usb_phy_set_power(hsotg->uphy, mA);
3620 }
3621
3622 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
3623 .get_frame = dwc2_hsotg_gadget_getframe,
3624 .udc_start = dwc2_hsotg_udc_start,
3625 .udc_stop = dwc2_hsotg_udc_stop,
3626 .pullup = dwc2_hsotg_pullup,
3627 .vbus_session = dwc2_hsotg_vbus_session,
3628 .vbus_draw = dwc2_hsotg_vbus_draw,
3629 };
3630
3631 /**
3632 * dwc2_hsotg_initep - initialise a single endpoint
3633 * @hsotg: The device state.
3634 * @hs_ep: The endpoint to be initialised.
3635 * @epnum: The endpoint number
3636 *
3637 * Initialise the given endpoint (as part of the probe and device state
3638 * creation) to give to the gadget driver. Setup the endpoint name, any
3639 * direction information and other state that may be required.
3640 */
3641 static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
3642 struct dwc2_hsotg_ep *hs_ep,
3643 int epnum,
3644 bool dir_in)
3645 {
3646 char *dir;
3647
3648 if (epnum == 0)
3649 dir = "";
3650 else if (dir_in)
3651 dir = "in";
3652 else
3653 dir = "out";
3654
3655 hs_ep->dir_in = dir_in;
3656 hs_ep->index = epnum;
3657
3658 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
3659
3660 INIT_LIST_HEAD(&hs_ep->queue);
3661 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
3662
3663 /* add to the list of endpoints known by the gadget driver */
3664 if (epnum)
3665 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
3666
3667 hs_ep->parent = hsotg;
3668 hs_ep->ep.name = hs_ep->name;
3669 usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT);
3670 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
3671
3672 if (epnum == 0) {
3673 hs_ep->ep.caps.type_control = true;
3674 } else {
3675 hs_ep->ep.caps.type_iso = true;
3676 hs_ep->ep.caps.type_bulk = true;
3677 hs_ep->ep.caps.type_int = true;
3678 }
3679
3680 if (dir_in)
3681 hs_ep->ep.caps.dir_in = true;
3682 else
3683 hs_ep->ep.caps.dir_out = true;
3684
3685 /*
3686 * if we're using dma, we need to set the next-endpoint pointer
3687 * to be something valid.
3688 */
3689
3690 if (using_dma(hsotg)) {
3691 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
3692 if (dir_in)
3693 dwc2_writel(next, hsotg->regs + DIEPCTL(epnum));
3694 else
3695 dwc2_writel(next, hsotg->regs + DOEPCTL(epnum));
3696 }
3697 }
3698
3699 /**
3700 * dwc2_hsotg_hw_cfg - read HW configuration registers
3701 * @param: The device state
3702 *
3703 * Read the USB core HW configuration registers
3704 */
3705 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
3706 {
3707 u32 cfg;
3708 u32 ep_type;
3709 u32 i;
3710
3711 /* check hardware configuration */
3712
3713 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
3714
3715 /* Add ep0 */
3716 hsotg->num_of_eps++;
3717
3718 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct dwc2_hsotg_ep),
3719 GFP_KERNEL);
3720 if (!hsotg->eps_in[0])
3721 return -ENOMEM;
3722 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
3723 hsotg->eps_out[0] = hsotg->eps_in[0];
3724
3725 cfg = hsotg->hw_params.dev_ep_dirs;
3726 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
3727 ep_type = cfg & 3;
3728 /* Direction in or both */
3729 if (!(ep_type & 2)) {
3730 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
3731 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
3732 if (!hsotg->eps_in[i])
3733 return -ENOMEM;
3734 }
3735 /* Direction out or both */
3736 if (!(ep_type & 1)) {
3737 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
3738 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
3739 if (!hsotg->eps_out[i])
3740 return -ENOMEM;
3741 }
3742 }
3743
3744 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
3745 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
3746
3747 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
3748 hsotg->num_of_eps,
3749 hsotg->dedicated_fifos ? "dedicated" : "shared",
3750 hsotg->fifo_mem);
3751 return 0;
3752 }
3753
3754 /**
3755 * dwc2_hsotg_dump - dump state of the udc
3756 * @param: The device state
3757 */
3758 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
3759 {
3760 #ifdef DEBUG
3761 struct device *dev = hsotg->dev;
3762 void __iomem *regs = hsotg->regs;
3763 u32 val;
3764 int idx;
3765
3766 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3767 dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL),
3768 dwc2_readl(regs + DIEPMSK));
3769
3770 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
3771 dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1));
3772
3773 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3774 dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ));
3775
3776 /* show periodic fifo settings */
3777
3778 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3779 val = dwc2_readl(regs + DPTXFSIZN(idx));
3780 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
3781 val >> FIFOSIZE_DEPTH_SHIFT,
3782 val & FIFOSIZE_STARTADDR_MASK);
3783 }
3784
3785 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
3786 dev_info(dev,
3787 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
3788 dwc2_readl(regs + DIEPCTL(idx)),
3789 dwc2_readl(regs + DIEPTSIZ(idx)),
3790 dwc2_readl(regs + DIEPDMA(idx)));
3791
3792 val = dwc2_readl(regs + DOEPCTL(idx));
3793 dev_info(dev,
3794 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3795 idx, dwc2_readl(regs + DOEPCTL(idx)),
3796 dwc2_readl(regs + DOEPTSIZ(idx)),
3797 dwc2_readl(regs + DOEPDMA(idx)));
3798
3799 }
3800
3801 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3802 dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE));
3803 #endif
3804 }
3805
3806 #ifdef CONFIG_OF
3807 static void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg)
3808 {
3809 struct device_node *np = hsotg->dev->of_node;
3810
3811 /* Enable dma if requested in device tree */
3812 hsotg->g_using_dma = of_property_read_bool(np, "g-use-dma");
3813
3814 /* Register RX fifo size */
3815 of_property_read_u32(np, "g-rx-fifo-size", &hsotg->g_rx_fifo_sz);
3816
3817 /* Register NPTX fifo size */
3818 of_property_read_u32(np, "g-np-tx-fifo-size",
3819 &hsotg->g_np_g_tx_fifo_sz);
3820 }
3821 #else
3822 static inline void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg) { }
3823 #endif
3824
3825 /**
3826 * dwc2_gadget_init - init function for gadget
3827 * @dwc2: The data structure for the DWC2 driver.
3828 * @irq: The IRQ number for the controller.
3829 */
3830 int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
3831 {
3832 struct device *dev = hsotg->dev;
3833 int epnum;
3834 int ret;
3835
3836 /* Initialize to legacy fifo configuration values */
3837 hsotg->g_rx_fifo_sz = 2048;
3838 hsotg->g_np_g_tx_fifo_sz = 1024;
3839 /* Device tree specific probe */
3840 dwc2_hsotg_of_probe(hsotg);
3841
3842 /* Check against largest possible value. */
3843 if (hsotg->g_np_g_tx_fifo_sz >
3844 hsotg->hw_params.dev_nperio_tx_fifo_size) {
3845 dev_warn(dev, "Specified GNPTXFDEP=%d > %d\n",
3846 hsotg->g_np_g_tx_fifo_sz,
3847 hsotg->hw_params.dev_nperio_tx_fifo_size);
3848 hsotg->g_np_g_tx_fifo_sz =
3849 hsotg->hw_params.dev_nperio_tx_fifo_size;
3850 }
3851
3852 /* Dump fifo information */
3853 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
3854 hsotg->g_np_g_tx_fifo_sz);
3855 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->g_rx_fifo_sz);
3856
3857 hsotg->gadget.max_speed = USB_SPEED_HIGH;
3858 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
3859 hsotg->gadget.name = dev_name(dev);
3860 if (hsotg->dr_mode == USB_DR_MODE_OTG)
3861 hsotg->gadget.is_otg = 1;
3862 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
3863 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3864
3865 ret = dwc2_hsotg_hw_cfg(hsotg);
3866 if (ret) {
3867 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
3868 return ret;
3869 }
3870
3871 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
3872 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3873 if (!hsotg->ctrl_buff)
3874 return -ENOMEM;
3875
3876 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
3877 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3878 if (!hsotg->ep0_buff)
3879 return -ENOMEM;
3880
3881 ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED,
3882 dev_name(hsotg->dev), hsotg);
3883 if (ret < 0) {
3884 dev_err(dev, "cannot claim IRQ for gadget\n");
3885 return ret;
3886 }
3887
3888 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3889
3890 if (hsotg->num_of_eps == 0) {
3891 dev_err(dev, "wrong number of EPs (zero)\n");
3892 return -EINVAL;
3893 }
3894
3895 /* setup endpoint information */
3896
3897 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3898 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
3899
3900 /* allocate EP0 request */
3901
3902 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
3903 GFP_KERNEL);
3904 if (!hsotg->ctrl_req) {
3905 dev_err(dev, "failed to allocate ctrl req\n");
3906 return -ENOMEM;
3907 }
3908
3909 /* initialise the endpoints now the core has been initialised */
3910 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
3911 if (hsotg->eps_in[epnum])
3912 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
3913 epnum, 1);
3914 if (hsotg->eps_out[epnum])
3915 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
3916 epnum, 0);
3917 }
3918
3919 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
3920 if (ret)
3921 return ret;
3922
3923 dwc2_hsotg_dump(hsotg);
3924
3925 return 0;
3926 }
3927
3928 /**
3929 * dwc2_hsotg_remove - remove function for hsotg driver
3930 * @pdev: The platform information for the driver
3931 */
3932 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
3933 {
3934 usb_del_gadget_udc(&hsotg->gadget);
3935
3936 return 0;
3937 }
3938
3939 int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
3940 {
3941 unsigned long flags;
3942
3943 if (hsotg->lx_state != DWC2_L0)
3944 return 0;
3945
3946 if (hsotg->driver) {
3947 int ep;
3948
3949 dev_info(hsotg->dev, "suspending usb gadget %s\n",
3950 hsotg->driver->driver.name);
3951
3952 spin_lock_irqsave(&hsotg->lock, flags);
3953 if (hsotg->enabled)
3954 dwc2_hsotg_core_disconnect(hsotg);
3955 dwc2_hsotg_disconnect(hsotg);
3956 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3957 spin_unlock_irqrestore(&hsotg->lock, flags);
3958
3959 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3960 if (hsotg->eps_in[ep])
3961 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3962 if (hsotg->eps_out[ep])
3963 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3964 }
3965 }
3966
3967 return 0;
3968 }
3969
3970 int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
3971 {
3972 unsigned long flags;
3973
3974 if (hsotg->lx_state == DWC2_L2)
3975 return 0;
3976
3977 if (hsotg->driver) {
3978 dev_info(hsotg->dev, "resuming usb gadget %s\n",
3979 hsotg->driver->driver.name);
3980
3981 spin_lock_irqsave(&hsotg->lock, flags);
3982 dwc2_hsotg_core_init_disconnected(hsotg, false);
3983 if (hsotg->enabled)
3984 dwc2_hsotg_core_connect(hsotg);
3985 spin_unlock_irqrestore(&hsotg->lock, flags);
3986 }
3987
3988 return 0;
3989 }
3990
3991 /**
3992 * dwc2_backup_device_registers() - Backup controller device registers.
3993 * When suspending usb bus, registers needs to be backuped
3994 * if controller power is disabled once suspended.
3995 *
3996 * @hsotg: Programming view of the DWC_otg controller
3997 */
3998 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
3999 {
4000 struct dwc2_dregs_backup *dr;
4001 int i;
4002
4003 dev_dbg(hsotg->dev, "%s\n", __func__);
4004
4005 /* Backup dev regs */
4006 dr = &hsotg->dr_backup;
4007
4008 dr->dcfg = dwc2_readl(hsotg->regs + DCFG);
4009 dr->dctl = dwc2_readl(hsotg->regs + DCTL);
4010 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
4011 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK);
4012 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
4013
4014 for (i = 0; i < hsotg->num_of_eps; i++) {
4015 /* Backup IN EPs */
4016 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i));
4017
4018 /* Ensure DATA PID is correctly configured */
4019 if (dr->diepctl[i] & DXEPCTL_DPID)
4020 dr->diepctl[i] |= DXEPCTL_SETD1PID;
4021 else
4022 dr->diepctl[i] |= DXEPCTL_SETD0PID;
4023
4024 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i));
4025 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i));
4026
4027 /* Backup OUT EPs */
4028 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i));
4029
4030 /* Ensure DATA PID is correctly configured */
4031 if (dr->doepctl[i] & DXEPCTL_DPID)
4032 dr->doepctl[i] |= DXEPCTL_SETD1PID;
4033 else
4034 dr->doepctl[i] |= DXEPCTL_SETD0PID;
4035
4036 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i));
4037 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i));
4038 }
4039 dr->valid = true;
4040 return 0;
4041 }
4042
4043 /**
4044 * dwc2_restore_device_registers() - Restore controller device registers.
4045 * When resuming usb bus, device registers needs to be restored
4046 * if controller power were disabled.
4047 *
4048 * @hsotg: Programming view of the DWC_otg controller
4049 */
4050 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
4051 {
4052 struct dwc2_dregs_backup *dr;
4053 u32 dctl;
4054 int i;
4055
4056 dev_dbg(hsotg->dev, "%s\n", __func__);
4057
4058 /* Restore dev regs */
4059 dr = &hsotg->dr_backup;
4060 if (!dr->valid) {
4061 dev_err(hsotg->dev, "%s: no device registers to restore\n",
4062 __func__);
4063 return -EINVAL;
4064 }
4065 dr->valid = false;
4066
4067 dwc2_writel(dr->dcfg, hsotg->regs + DCFG);
4068 dwc2_writel(dr->dctl, hsotg->regs + DCTL);
4069 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK);
4070 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK);
4071 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK);
4072
4073 for (i = 0; i < hsotg->num_of_eps; i++) {
4074 /* Restore IN EPs */
4075 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i));
4076 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i));
4077 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i));
4078
4079 /* Restore OUT EPs */
4080 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i));
4081 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
4082 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i));
4083 }
4084
4085 /* Set the Power-On Programming done bit */
4086 dctl = dwc2_readl(hsotg->regs + DCTL);
4087 dctl |= DCTL_PWRONPRGDONE;
4088 dwc2_writel(dctl, hsotg->regs + DCTL);
4089
4090 return 0;
4091 }