1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
11 * S3C USB2.0 High-speed / OtG driver
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/interrupt.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/mutex.h>
21 #include <linux/seq_file.h>
22 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/of_platform.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
29 #include <linux/usb/phy.h>
34 /* conversion functions */
35 static inline struct dwc2_hsotg_req
*our_req(struct usb_request
*req
)
37 return container_of(req
, struct dwc2_hsotg_req
, req
);
40 static inline struct dwc2_hsotg_ep
*our_ep(struct usb_ep
*ep
)
42 return container_of(ep
, struct dwc2_hsotg_ep
, ep
);
45 static inline struct dwc2_hsotg
*to_hsotg(struct usb_gadget
*gadget
)
47 return container_of(gadget
, struct dwc2_hsotg
, gadget
);
50 static inline void __orr32(void __iomem
*ptr
, u32 val
)
52 dwc2_writel(dwc2_readl(ptr
) | val
, ptr
);
55 static inline void __bic32(void __iomem
*ptr
, u32 val
)
57 dwc2_writel(dwc2_readl(ptr
) & ~val
, ptr
);
60 static inline struct dwc2_hsotg_ep
*index_to_ep(struct dwc2_hsotg
*hsotg
,
61 u32 ep_index
, u32 dir_in
)
64 return hsotg
->eps_in
[ep_index
];
66 return hsotg
->eps_out
[ep_index
];
69 /* forward declaration of functions */
70 static void dwc2_hsotg_dump(struct dwc2_hsotg
*hsotg
);
73 * using_dma - return the DMA status of the driver.
74 * @hsotg: The driver state.
76 * Return true if we're using DMA.
78 * Currently, we have the DMA support code worked into everywhere
79 * that needs it, but the AMBA DMA implementation in the hardware can
80 * only DMA from 32bit aligned addresses. This means that gadgets such
81 * as the CDC Ethernet cannot work as they often pass packets which are
84 * Unfortunately the choice to use DMA or not is global to the controller
85 * and seems to be only settable when the controller is being put through
86 * a core reset. This means we either need to fix the gadgets to take
87 * account of DMA alignment, or add bounce buffers (yuerk).
89 * g_using_dma is set depending on dts flag.
91 static inline bool using_dma(struct dwc2_hsotg
*hsotg
)
93 return hsotg
->params
.g_dma
;
97 * using_desc_dma - return the descriptor DMA status of the driver.
98 * @hsotg: The driver state.
100 * Return true if we're using descriptor DMA.
102 static inline bool using_desc_dma(struct dwc2_hsotg
*hsotg
)
104 return hsotg
->params
.g_dma_desc
;
108 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
109 * @hs_ep: The endpoint
110 * @increment: The value to increment by
112 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
113 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
115 static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep
*hs_ep
)
117 hs_ep
->target_frame
+= hs_ep
->interval
;
118 if (hs_ep
->target_frame
> DSTS_SOFFN_LIMIT
) {
119 hs_ep
->frame_overrun
= 1;
120 hs_ep
->target_frame
&= DSTS_SOFFN_LIMIT
;
122 hs_ep
->frame_overrun
= 0;
127 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
128 * @hsotg: The device state
129 * @ints: A bitmask of the interrupts to enable
131 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg
*hsotg
, u32 ints
)
133 u32 gsintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
136 new_gsintmsk
= gsintmsk
| ints
;
138 if (new_gsintmsk
!= gsintmsk
) {
139 dev_dbg(hsotg
->dev
, "gsintmsk now 0x%08x\n", new_gsintmsk
);
140 dwc2_writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
145 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
146 * @hsotg: The device state
147 * @ints: A bitmask of the interrupts to enable
149 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg
*hsotg
, u32 ints
)
151 u32 gsintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
154 new_gsintmsk
= gsintmsk
& ~ints
;
156 if (new_gsintmsk
!= gsintmsk
)
157 dwc2_writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
161 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
162 * @hsotg: The device state
163 * @ep: The endpoint index
164 * @dir_in: True if direction is in.
165 * @en: The enable value, true to enable
167 * Set or clear the mask for an individual endpoint's interrupt
170 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg
*hsotg
,
171 unsigned int ep
, unsigned int dir_in
,
181 local_irq_save(flags
);
182 daint
= dwc2_readl(hsotg
->regs
+ DAINTMSK
);
187 dwc2_writel(daint
, hsotg
->regs
+ DAINTMSK
);
188 local_irq_restore(flags
);
192 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
194 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg
*hsotg
)
196 if (hsotg
->hw_params
.en_multiple_tx_fifo
)
197 /* In dedicated FIFO mode we need count of IN EPs */
198 return (dwc2_readl(hsotg
->regs
+ GHWCFG4
) &
199 GHWCFG4_NUM_IN_EPS_MASK
) >> GHWCFG4_NUM_IN_EPS_SHIFT
;
201 /* In shared FIFO mode we need count of Periodic IN EPs */
202 return hsotg
->hw_params
.num_dev_perio_in_ep
;
206 * dwc2_hsotg_ep_info_size - return Endpoint Info Control block size in DWORDs
208 static int dwc2_hsotg_ep_info_size(struct dwc2_hsotg
*hsotg
)
215 * Don't need additional space for ep info control registers in
218 if (!using_dma(hsotg
)) {
219 dev_dbg(hsotg
->dev
, "Buffer DMA ep info size 0\n");
224 * Buffer DMA mode - 1 location per endpoit
225 * Descriptor DMA mode - 4 locations per endpoint
227 ep_dirs
= hsotg
->hw_params
.dev_ep_dirs
;
229 for (i
= 0; i
<= hsotg
->hw_params
.num_dev_ep
; i
++) {
230 val
+= ep_dirs
& 3 ? 1 : 2;
234 if (using_desc_dma(hsotg
))
241 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
242 * device mode TX FIFOs
244 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg
*hsotg
)
251 np_tx_fifo_size
= min_t(u32
, hsotg
->hw_params
.dev_nperio_tx_fifo_size
,
252 hsotg
->params
.g_np_tx_fifo_size
);
254 /* Get Endpoint Info Control block size in DWORDs. */
255 ep_info_size
= dwc2_hsotg_ep_info_size(hsotg
);
256 tx_addr_max
= hsotg
->hw_params
.total_fifo_size
- ep_info_size
;
258 addr
= hsotg
->params
.g_rx_fifo_size
+ np_tx_fifo_size
;
259 if (tx_addr_max
<= addr
)
262 return tx_addr_max
- addr
;
266 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
269 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg
*hsotg
)
274 tx_fifo_depth
= dwc2_hsotg_tx_fifo_total_depth(hsotg
);
276 tx_fifo_count
= dwc2_hsotg_tx_fifo_count(hsotg
);
279 return tx_fifo_depth
;
281 return tx_fifo_depth
/ tx_fifo_count
;
285 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
286 * @hsotg: The device instance.
288 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg
*hsotg
)
294 u32
*txfsz
= hsotg
->params
.g_tx_fifo_size
;
296 /* Reset fifo map if not correctly cleared during previous session */
297 WARN_ON(hsotg
->fifo_map
);
300 /* set RX/NPTX FIFO sizes */
301 dwc2_writel(hsotg
->params
.g_rx_fifo_size
, hsotg
->regs
+ GRXFSIZ
);
302 dwc2_writel((hsotg
->params
.g_rx_fifo_size
<< FIFOSIZE_STARTADDR_SHIFT
) |
303 (hsotg
->params
.g_np_tx_fifo_size
<< FIFOSIZE_DEPTH_SHIFT
),
304 hsotg
->regs
+ GNPTXFSIZ
);
307 * arange all the rest of the TX FIFOs, as some versions of this
308 * block have overlapping default addresses. This also ensures
309 * that if the settings have been changed, then they are set to
313 /* start at the end of the GNPTXFSIZ, rounded up */
314 addr
= hsotg
->params
.g_rx_fifo_size
+ hsotg
->params
.g_np_tx_fifo_size
;
317 * Configure fifos sizes from provided configuration and assign
318 * them to endpoints dynamically according to maxpacket size value of
321 for (ep
= 1; ep
< MAX_EPS_CHANNELS
; ep
++) {
325 val
|= txfsz
[ep
] << FIFOSIZE_DEPTH_SHIFT
;
326 WARN_ONCE(addr
+ txfsz
[ep
] > hsotg
->fifo_mem
,
327 "insufficient fifo memory");
330 dwc2_writel(val
, hsotg
->regs
+ DPTXFSIZN(ep
));
331 val
= dwc2_readl(hsotg
->regs
+ DPTXFSIZN(ep
));
334 dwc2_writel(hsotg
->hw_params
.total_fifo_size
|
335 addr
<< GDFIFOCFG_EPINFOBASE_SHIFT
,
336 hsotg
->regs
+ GDFIFOCFG
);
338 * according to p428 of the design guide, we need to ensure that
339 * all fifos are flushed before continuing
342 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH
|
343 GRSTCTL_RXFFLSH
, hsotg
->regs
+ GRSTCTL
);
345 /* wait until the fifos are both flushed */
348 val
= dwc2_readl(hsotg
->regs
+ GRSTCTL
);
350 if ((val
& (GRSTCTL_TXFFLSH
| GRSTCTL_RXFFLSH
)) == 0)
353 if (--timeout
== 0) {
355 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
363 dev_dbg(hsotg
->dev
, "FIFOs reset, timeout at %d\n", timeout
);
367 * @ep: USB endpoint to allocate request for.
368 * @flags: Allocation flags
370 * Allocate a new USB request structure appropriate for the specified endpoint
372 static struct usb_request
*dwc2_hsotg_ep_alloc_request(struct usb_ep
*ep
,
375 struct dwc2_hsotg_req
*req
;
377 req
= kzalloc(sizeof(*req
), flags
);
381 INIT_LIST_HEAD(&req
->queue
);
387 * is_ep_periodic - return true if the endpoint is in periodic mode.
388 * @hs_ep: The endpoint to query.
390 * Returns true if the endpoint is in periodic mode, meaning it is being
391 * used for an Interrupt or ISO transfer.
393 static inline int is_ep_periodic(struct dwc2_hsotg_ep
*hs_ep
)
395 return hs_ep
->periodic
;
399 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
400 * @hsotg: The device state.
401 * @hs_ep: The endpoint for the request
402 * @hs_req: The request being processed.
404 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
405 * of a request to ensure the buffer is ready for access by the caller.
407 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg
*hsotg
,
408 struct dwc2_hsotg_ep
*hs_ep
,
409 struct dwc2_hsotg_req
*hs_req
)
411 struct usb_request
*req
= &hs_req
->req
;
413 usb_gadget_unmap_request(&hsotg
->gadget
, req
, hs_ep
->dir_in
);
417 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
418 * for Control endpoint
419 * @hsotg: The device state.
421 * This function will allocate 4 descriptor chains for EP 0: 2 for
422 * Setup stage, per one for IN and OUT data/status transactions.
424 static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg
*hsotg
)
426 hsotg
->setup_desc
[0] =
427 dmam_alloc_coherent(hsotg
->dev
,
428 sizeof(struct dwc2_dma_desc
),
429 &hsotg
->setup_desc_dma
[0],
431 if (!hsotg
->setup_desc
[0])
434 hsotg
->setup_desc
[1] =
435 dmam_alloc_coherent(hsotg
->dev
,
436 sizeof(struct dwc2_dma_desc
),
437 &hsotg
->setup_desc_dma
[1],
439 if (!hsotg
->setup_desc
[1])
442 hsotg
->ctrl_in_desc
=
443 dmam_alloc_coherent(hsotg
->dev
,
444 sizeof(struct dwc2_dma_desc
),
445 &hsotg
->ctrl_in_desc_dma
,
447 if (!hsotg
->ctrl_in_desc
)
450 hsotg
->ctrl_out_desc
=
451 dmam_alloc_coherent(hsotg
->dev
,
452 sizeof(struct dwc2_dma_desc
),
453 &hsotg
->ctrl_out_desc_dma
,
455 if (!hsotg
->ctrl_out_desc
)
465 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
466 * @hsotg: The controller state.
467 * @hs_ep: The endpoint we're going to write for.
468 * @hs_req: The request to write data for.
470 * This is called when the TxFIFO has some space in it to hold a new
471 * transmission and we have something to give it. The actual setup of
472 * the data size is done elsewhere, so all we have to do is to actually
475 * The return value is zero if there is more space (or nothing was done)
476 * otherwise -ENOSPC is returned if the FIFO space was used up.
478 * This routine is only needed for PIO
480 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg
*hsotg
,
481 struct dwc2_hsotg_ep
*hs_ep
,
482 struct dwc2_hsotg_req
*hs_req
)
484 bool periodic
= is_ep_periodic(hs_ep
);
485 u32 gnptxsts
= dwc2_readl(hsotg
->regs
+ GNPTXSTS
);
486 int buf_pos
= hs_req
->req
.actual
;
487 int to_write
= hs_ep
->size_loaded
;
493 to_write
-= (buf_pos
- hs_ep
->last_load
);
495 /* if there's nothing to write, get out early */
499 if (periodic
&& !hsotg
->dedicated_fifos
) {
500 u32 epsize
= dwc2_readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
505 * work out how much data was loaded so we can calculate
506 * how much data is left in the fifo.
509 size_left
= DXEPTSIZ_XFERSIZE_GET(epsize
);
512 * if shared fifo, we cannot write anything until the
513 * previous data has been completely sent.
515 if (hs_ep
->fifo_load
!= 0) {
516 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_PTXFEMP
);
520 dev_dbg(hsotg
->dev
, "%s: left=%d, load=%d, fifo=%d, size %d\n",
522 hs_ep
->size_loaded
, hs_ep
->fifo_load
, hs_ep
->fifo_size
);
524 /* how much of the data has moved */
525 size_done
= hs_ep
->size_loaded
- size_left
;
527 /* how much data is left in the fifo */
528 can_write
= hs_ep
->fifo_load
- size_done
;
529 dev_dbg(hsotg
->dev
, "%s: => can_write1=%d\n",
530 __func__
, can_write
);
532 can_write
= hs_ep
->fifo_size
- can_write
;
533 dev_dbg(hsotg
->dev
, "%s: => can_write2=%d\n",
534 __func__
, can_write
);
536 if (can_write
<= 0) {
537 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_PTXFEMP
);
540 } else if (hsotg
->dedicated_fifos
&& hs_ep
->index
!= 0) {
541 can_write
= dwc2_readl(hsotg
->regs
+
542 DTXFSTS(hs_ep
->fifo_index
));
547 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts
) == 0) {
549 "%s: no queue slots available (0x%08x)\n",
552 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_NPTXFEMP
);
556 can_write
= GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts
);
557 can_write
*= 4; /* fifo size is in 32bit quantities. */
560 max_transfer
= hs_ep
->ep
.maxpacket
* hs_ep
->mc
;
562 dev_dbg(hsotg
->dev
, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
563 __func__
, gnptxsts
, can_write
, to_write
, max_transfer
);
566 * limit to 512 bytes of data, it seems at least on the non-periodic
567 * FIFO, requests of >512 cause the endpoint to get stuck with a
568 * fragment of the end of the transfer in it.
570 if (can_write
> 512 && !periodic
)
574 * limit the write to one max-packet size worth of data, but allow
575 * the transfer to return that it did not run out of fifo space
578 if (to_write
> max_transfer
) {
579 to_write
= max_transfer
;
581 /* it's needed only when we do not use dedicated fifos */
582 if (!hsotg
->dedicated_fifos
)
583 dwc2_hsotg_en_gsint(hsotg
,
584 periodic
? GINTSTS_PTXFEMP
:
588 /* see if we can write data */
590 if (to_write
> can_write
) {
591 to_write
= can_write
;
592 pkt_round
= to_write
% max_transfer
;
595 * Round the write down to an
596 * exact number of packets.
598 * Note, we do not currently check to see if we can ever
599 * write a full packet or not to the FIFO.
603 to_write
-= pkt_round
;
606 * enable correct FIFO interrupt to alert us when there
610 /* it's needed only when we do not use dedicated fifos */
611 if (!hsotg
->dedicated_fifos
)
612 dwc2_hsotg_en_gsint(hsotg
,
613 periodic
? GINTSTS_PTXFEMP
:
617 dev_dbg(hsotg
->dev
, "write %d/%d, can_write %d, done %d\n",
618 to_write
, hs_req
->req
.length
, can_write
, buf_pos
);
623 hs_req
->req
.actual
= buf_pos
+ to_write
;
624 hs_ep
->total_data
+= to_write
;
627 hs_ep
->fifo_load
+= to_write
;
629 to_write
= DIV_ROUND_UP(to_write
, 4);
630 data
= hs_req
->req
.buf
+ buf_pos
;
632 iowrite32_rep(hsotg
->regs
+ EPFIFO(hs_ep
->index
), data
, to_write
);
634 return (to_write
>= can_write
) ? -ENOSPC
: 0;
638 * get_ep_limit - get the maximum data legnth for this endpoint
639 * @hs_ep: The endpoint
641 * Return the maximum data that can be queued in one go on a given endpoint
642 * so that transfers that are too long can be split.
644 static unsigned int get_ep_limit(struct dwc2_hsotg_ep
*hs_ep
)
646 int index
= hs_ep
->index
;
647 unsigned int maxsize
;
651 maxsize
= DXEPTSIZ_XFERSIZE_LIMIT
+ 1;
652 maxpkt
= DXEPTSIZ_PKTCNT_LIMIT
+ 1;
656 maxpkt
= DIEPTSIZ0_PKTCNT_LIMIT
+ 1;
661 /* we made the constant loading easier above by using +1 */
666 * constrain by packet count if maxpkts*pktsize is greater
667 * than the length register size.
670 if ((maxpkt
* hs_ep
->ep
.maxpacket
) < maxsize
)
671 maxsize
= maxpkt
* hs_ep
->ep
.maxpacket
;
677 * dwc2_hsotg_read_frameno - read current frame number
678 * @hsotg: The device instance
680 * Return the current frame number
682 static u32
dwc2_hsotg_read_frameno(struct dwc2_hsotg
*hsotg
)
686 dsts
= dwc2_readl(hsotg
->regs
+ DSTS
);
687 dsts
&= DSTS_SOFFN_MASK
;
688 dsts
>>= DSTS_SOFFN_SHIFT
;
694 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
695 * DMA descriptor chain prepared for specific endpoint
696 * @hs_ep: The endpoint
698 * Return the maximum data that can be queued in one go on a given endpoint
699 * depending on its descriptor chain capacity so that transfers that
700 * are too long can be split.
702 static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep
*hs_ep
)
704 int is_isoc
= hs_ep
->isochronous
;
705 unsigned int maxsize
;
708 maxsize
= hs_ep
->dir_in
? DEV_DMA_ISOC_TX_NBYTES_LIMIT
:
709 DEV_DMA_ISOC_RX_NBYTES_LIMIT
;
711 maxsize
= DEV_DMA_NBYTES_LIMIT
;
713 /* Above size of one descriptor was chosen, multiple it */
714 maxsize
*= MAX_DMA_DESC_NUM_GENERIC
;
720 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
721 * @hs_ep: The endpoint
722 * @mask: RX/TX bytes mask to be defined
724 * Returns maximum data payload for one descriptor after analyzing endpoint
726 * DMA descriptor transfer bytes limit depends on EP type:
728 * Isochronous - descriptor rx/tx bytes bitfield limit,
729 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
730 * have concatenations from various descriptors within one packet.
732 * Selects corresponding mask for RX/TX bytes as well.
734 static u32
dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep
*hs_ep
, u32
*mask
)
736 u32 mps
= hs_ep
->ep
.maxpacket
;
737 int dir_in
= hs_ep
->dir_in
;
740 if (!hs_ep
->index
&& !dir_in
) {
742 *mask
= DEV_DMA_NBYTES_MASK
;
743 } else if (hs_ep
->isochronous
) {
745 desc_size
= DEV_DMA_ISOC_TX_NBYTES_LIMIT
;
746 *mask
= DEV_DMA_ISOC_TX_NBYTES_MASK
;
748 desc_size
= DEV_DMA_ISOC_RX_NBYTES_LIMIT
;
749 *mask
= DEV_DMA_ISOC_RX_NBYTES_MASK
;
752 desc_size
= DEV_DMA_NBYTES_LIMIT
;
753 *mask
= DEV_DMA_NBYTES_MASK
;
755 /* Round down desc_size to be mps multiple */
756 desc_size
-= desc_size
% mps
;
763 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
764 * @hs_ep: The endpoint
765 * @dma_buff: DMA address to use
766 * @len: Length of the transfer
768 * This function will iterate over descriptor chain and fill its entries
769 * with corresponding information based on transfer data.
771 static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep
*hs_ep
,
775 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
776 int dir_in
= hs_ep
->dir_in
;
777 struct dwc2_dma_desc
*desc
= hs_ep
->desc_list
;
778 u32 mps
= hs_ep
->ep
.maxpacket
;
784 maxsize
= dwc2_gadget_get_desc_params(hs_ep
, &mask
);
786 hs_ep
->desc_count
= (len
/ maxsize
) +
787 ((len
% maxsize
) ? 1 : 0);
789 hs_ep
->desc_count
= 1;
791 for (i
= 0; i
< hs_ep
->desc_count
; ++i
) {
793 desc
->status
|= (DEV_DMA_BUFF_STS_HBUSY
794 << DEV_DMA_BUFF_STS_SHIFT
);
797 if (!hs_ep
->index
&& !dir_in
)
798 desc
->status
|= (DEV_DMA_L
| DEV_DMA_IOC
);
800 desc
->status
|= (maxsize
<<
801 DEV_DMA_NBYTES_SHIFT
& mask
);
802 desc
->buf
= dma_buff
+ offset
;
807 desc
->status
|= (DEV_DMA_L
| DEV_DMA_IOC
);
810 desc
->status
|= (len
% mps
) ? DEV_DMA_SHORT
:
811 ((hs_ep
->send_zlp
) ? DEV_DMA_SHORT
: 0);
813 dev_err(hsotg
->dev
, "wrong len %d\n", len
);
816 len
<< DEV_DMA_NBYTES_SHIFT
& mask
;
817 desc
->buf
= dma_buff
+ offset
;
820 desc
->status
&= ~DEV_DMA_BUFF_STS_MASK
;
821 desc
->status
|= (DEV_DMA_BUFF_STS_HREADY
822 << DEV_DMA_BUFF_STS_SHIFT
);
828 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
829 * @hs_ep: The isochronous endpoint.
830 * @dma_buff: usb requests dma buffer.
831 * @len: usb request transfer length.
833 * Finds out index of first free entry either in the bottom or up half of
834 * descriptor chain depend on which is under SW control and not processed
835 * by HW. Then fills that descriptor with the data of the arrived usb request,
836 * frame info, sets Last and IOC bits increments next_desc. If filled
837 * descriptor is not the first one, removes L bit from the previous descriptor
840 static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep
*hs_ep
,
841 dma_addr_t dma_buff
, unsigned int len
)
843 struct dwc2_dma_desc
*desc
;
844 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
849 maxsize
= dwc2_gadget_get_desc_params(hs_ep
, &mask
);
851 dev_err(hsotg
->dev
, "wrong len %d\n", len
);
856 * If SW has already filled half of chain, then return and wait for
857 * the other chain to be processed by HW.
859 if (hs_ep
->next_desc
== MAX_DMA_DESC_NUM_GENERIC
/ 2)
862 /* Increment frame number by interval for IN */
864 dwc2_gadget_incr_frame_num(hs_ep
);
866 index
= (MAX_DMA_DESC_NUM_GENERIC
/ 2) * hs_ep
->isoc_chain_num
+
869 /* Sanity check of calculated index */
870 if ((hs_ep
->isoc_chain_num
&& index
> MAX_DMA_DESC_NUM_GENERIC
) ||
871 (!hs_ep
->isoc_chain_num
&& index
> MAX_DMA_DESC_NUM_GENERIC
/ 2)) {
872 dev_err(hsotg
->dev
, "wrong index %d for iso chain\n", index
);
876 desc
= &hs_ep
->desc_list
[index
];
878 /* Clear L bit of previous desc if more than one entries in the chain */
879 if (hs_ep
->next_desc
)
880 hs_ep
->desc_list
[index
- 1].status
&= ~DEV_DMA_L
;
882 dev_dbg(hsotg
->dev
, "%s: Filling ep %d, dir %s isoc desc # %d\n",
883 __func__
, hs_ep
->index
, hs_ep
->dir_in
? "in" : "out", index
);
886 desc
->status
|= (DEV_DMA_BUFF_STS_HBUSY
<< DEV_DMA_BUFF_STS_SHIFT
);
888 desc
->buf
= dma_buff
;
889 desc
->status
|= (DEV_DMA_L
| DEV_DMA_IOC
|
890 ((len
<< DEV_DMA_NBYTES_SHIFT
) & mask
));
893 desc
->status
|= ((hs_ep
->mc
<< DEV_DMA_ISOC_PID_SHIFT
) &
894 DEV_DMA_ISOC_PID_MASK
) |
895 ((len
% hs_ep
->ep
.maxpacket
) ?
897 ((hs_ep
->target_frame
<<
898 DEV_DMA_ISOC_FRNUM_SHIFT
) &
899 DEV_DMA_ISOC_FRNUM_MASK
);
902 desc
->status
&= ~DEV_DMA_BUFF_STS_MASK
;
903 desc
->status
|= (DEV_DMA_BUFF_STS_HREADY
<< DEV_DMA_BUFF_STS_SHIFT
);
905 /* Update index of last configured entry in the chain */
912 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
913 * @hs_ep: The isochronous endpoint.
915 * Prepare first descriptor chain for isochronous endpoints. Afterwards
916 * write DMA address to HW and enable the endpoint.
918 * Switch between descriptor chains via isoc_chain_num to give SW opportunity
919 * to prepare second descriptor chain while first one is being processed by HW.
921 static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep
*hs_ep
)
923 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
924 struct dwc2_hsotg_req
*hs_req
, *treq
;
925 int index
= hs_ep
->index
;
931 if (list_empty(&hs_ep
->queue
)) {
932 dev_dbg(hsotg
->dev
, "%s: No requests in queue\n", __func__
);
936 list_for_each_entry_safe(hs_req
, treq
, &hs_ep
->queue
, queue
) {
937 ret
= dwc2_gadget_fill_isoc_desc(hs_ep
, hs_req
->req
.dma
,
940 dev_dbg(hsotg
->dev
, "%s: desc chain full\n", __func__
);
945 depctl
= hs_ep
->dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
946 dma_reg
= hs_ep
->dir_in
? DIEPDMA(index
) : DOEPDMA(index
);
948 /* write descriptor chain address to control register */
949 dwc2_writel(hs_ep
->desc_list_dma
, hsotg
->regs
+ dma_reg
);
951 ctrl
= dwc2_readl(hsotg
->regs
+ depctl
);
952 ctrl
|= DXEPCTL_EPENA
| DXEPCTL_CNAK
;
953 dwc2_writel(ctrl
, hsotg
->regs
+ depctl
);
955 /* Switch ISOC descriptor chain number being processed by SW*/
956 hs_ep
->isoc_chain_num
= (hs_ep
->isoc_chain_num
^ 1) & 0x1;
957 hs_ep
->next_desc
= 0;
961 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
962 * @hsotg: The controller state.
963 * @hs_ep: The endpoint to process a request for
964 * @hs_req: The request to start.
965 * @continuing: True if we are doing more for the current request.
967 * Start the given request running by setting the endpoint registers
968 * appropriately, and writing any data to the FIFOs.
970 static void dwc2_hsotg_start_req(struct dwc2_hsotg
*hsotg
,
971 struct dwc2_hsotg_ep
*hs_ep
,
972 struct dwc2_hsotg_req
*hs_req
,
975 struct usb_request
*ureq
= &hs_req
->req
;
976 int index
= hs_ep
->index
;
977 int dir_in
= hs_ep
->dir_in
;
983 unsigned int packets
;
985 unsigned int dma_reg
;
988 if (hs_ep
->req
&& !continuing
) {
989 dev_err(hsotg
->dev
, "%s: active request\n", __func__
);
992 } else if (hs_ep
->req
!= hs_req
&& continuing
) {
994 "%s: continue different req\n", __func__
);
1000 dma_reg
= dir_in
? DIEPDMA(index
) : DOEPDMA(index
);
1001 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
1002 epsize_reg
= dir_in
? DIEPTSIZ(index
) : DOEPTSIZ(index
);
1004 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
1005 __func__
, dwc2_readl(hsotg
->regs
+ epctrl_reg
), index
,
1006 hs_ep
->dir_in
? "in" : "out");
1008 /* If endpoint is stalled, we will restart request later */
1009 ctrl
= dwc2_readl(hsotg
->regs
+ epctrl_reg
);
1011 if (index
&& ctrl
& DXEPCTL_STALL
) {
1012 dev_warn(hsotg
->dev
, "%s: ep%d is stalled\n", __func__
, index
);
1016 length
= ureq
->length
- ureq
->actual
;
1017 dev_dbg(hsotg
->dev
, "ureq->length:%d ureq->actual:%d\n",
1018 ureq
->length
, ureq
->actual
);
1020 if (!using_desc_dma(hsotg
))
1021 maxreq
= get_ep_limit(hs_ep
);
1023 maxreq
= dwc2_gadget_get_chain_limit(hs_ep
);
1025 if (length
> maxreq
) {
1026 int round
= maxreq
% hs_ep
->ep
.maxpacket
;
1028 dev_dbg(hsotg
->dev
, "%s: length %d, max-req %d, r %d\n",
1029 __func__
, length
, maxreq
, round
);
1031 /* round down to multiple of packets */
1039 packets
= DIV_ROUND_UP(length
, hs_ep
->ep
.maxpacket
);
1041 packets
= 1; /* send one packet if length is zero. */
1043 if (hs_ep
->isochronous
&& length
> (hs_ep
->mc
* hs_ep
->ep
.maxpacket
)) {
1044 dev_err(hsotg
->dev
, "req length > maxpacket*mc\n");
1048 if (dir_in
&& index
!= 0)
1049 if (hs_ep
->isochronous
)
1050 epsize
= DXEPTSIZ_MC(packets
);
1052 epsize
= DXEPTSIZ_MC(1);
1057 * zero length packet should be programmed on its own and should not
1058 * be counted in DIEPTSIZ.PktCnt with other packets.
1060 if (dir_in
&& ureq
->zero
&& !continuing
) {
1061 /* Test if zlp is actually required. */
1062 if ((ureq
->length
>= hs_ep
->ep
.maxpacket
) &&
1063 !(ureq
->length
% hs_ep
->ep
.maxpacket
))
1064 hs_ep
->send_zlp
= 1;
1067 epsize
|= DXEPTSIZ_PKTCNT(packets
);
1068 epsize
|= DXEPTSIZ_XFERSIZE(length
);
1070 dev_dbg(hsotg
->dev
, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1071 __func__
, packets
, length
, ureq
->length
, epsize
, epsize_reg
);
1073 /* store the request as the current one we're doing */
1074 hs_ep
->req
= hs_req
;
1076 if (using_desc_dma(hsotg
)) {
1078 u32 mps
= hs_ep
->ep
.maxpacket
;
1080 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1084 else if (length
% mps
)
1085 length
+= (mps
- (length
% mps
));
1089 * If more data to send, adjust DMA for EP0 out data stage.
1090 * ureq->dma stays unchanged, hence increment it by already
1091 * passed passed data count before starting new transaction.
1093 if (!index
&& hsotg
->ep0_state
== DWC2_EP0_DATA_OUT
&&
1095 offset
= ureq
->actual
;
1097 /* Fill DDMA chain entries */
1098 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep
, ureq
->dma
+ offset
,
1101 /* write descriptor chain address to control register */
1102 dwc2_writel(hs_ep
->desc_list_dma
, hsotg
->regs
+ dma_reg
);
1104 dev_dbg(hsotg
->dev
, "%s: %08x pad => 0x%08x\n",
1105 __func__
, (u32
)hs_ep
->desc_list_dma
, dma_reg
);
1107 /* write size / packets */
1108 dwc2_writel(epsize
, hsotg
->regs
+ epsize_reg
);
1110 if (using_dma(hsotg
) && !continuing
&& (length
!= 0)) {
1112 * write DMA address to control register, buffer
1113 * already synced by dwc2_hsotg_ep_queue().
1116 dwc2_writel(ureq
->dma
, hsotg
->regs
+ dma_reg
);
1118 dev_dbg(hsotg
->dev
, "%s: %pad => 0x%08x\n",
1119 __func__
, &ureq
->dma
, dma_reg
);
1123 if (hs_ep
->isochronous
&& hs_ep
->interval
== 1) {
1124 hs_ep
->target_frame
= dwc2_hsotg_read_frameno(hsotg
);
1125 dwc2_gadget_incr_frame_num(hs_ep
);
1127 if (hs_ep
->target_frame
& 0x1)
1128 ctrl
|= DXEPCTL_SETODDFR
;
1130 ctrl
|= DXEPCTL_SETEVENFR
;
1133 ctrl
|= DXEPCTL_EPENA
; /* ensure ep enabled */
1135 dev_dbg(hsotg
->dev
, "ep0 state:%d\n", hsotg
->ep0_state
);
1137 /* For Setup request do not clear NAK */
1138 if (!(index
== 0 && hsotg
->ep0_state
== DWC2_EP0_SETUP
))
1139 ctrl
|= DXEPCTL_CNAK
; /* clear NAK set by core */
1141 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
1142 dwc2_writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
1145 * set these, it seems that DMA support increments past the end
1146 * of the packet buffer so we need to calculate the length from
1149 hs_ep
->size_loaded
= length
;
1150 hs_ep
->last_load
= ureq
->actual
;
1152 if (dir_in
&& !using_dma(hsotg
)) {
1153 /* set these anyway, we may need them for non-periodic in */
1154 hs_ep
->fifo_load
= 0;
1156 dwc2_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
1160 * Note, trying to clear the NAK here causes problems with transmit
1161 * on the S3C6400 ending up with the TXFIFO becoming full.
1164 /* check ep is enabled */
1165 if (!(dwc2_readl(hsotg
->regs
+ epctrl_reg
) & DXEPCTL_EPENA
))
1167 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1168 index
, dwc2_readl(hsotg
->regs
+ epctrl_reg
));
1170 dev_dbg(hsotg
->dev
, "%s: DXEPCTL=0x%08x\n",
1171 __func__
, dwc2_readl(hsotg
->regs
+ epctrl_reg
));
1173 /* enable ep interrupts */
1174 dwc2_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 1);
1178 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1179 * @hsotg: The device state.
1180 * @hs_ep: The endpoint the request is on.
1181 * @req: The request being processed.
1183 * We've been asked to queue a request, so ensure that the memory buffer
1184 * is correctly setup for DMA. If we've been passed an extant DMA address
1185 * then ensure the buffer has been synced to memory. If our buffer has no
1186 * DMA memory, then we map the memory and mark our request to allow us to
1187 * cleanup on completion.
1189 static int dwc2_hsotg_map_dma(struct dwc2_hsotg
*hsotg
,
1190 struct dwc2_hsotg_ep
*hs_ep
,
1191 struct usb_request
*req
)
1195 ret
= usb_gadget_map_request(&hsotg
->gadget
, req
, hs_ep
->dir_in
);
1202 dev_err(hsotg
->dev
, "%s: failed to map buffer %p, %d bytes\n",
1203 __func__
, req
->buf
, req
->length
);
1208 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg
*hsotg
,
1209 struct dwc2_hsotg_ep
*hs_ep
,
1210 struct dwc2_hsotg_req
*hs_req
)
1212 void *req_buf
= hs_req
->req
.buf
;
1214 /* If dma is not being used or buffer is aligned */
1215 if (!using_dma(hsotg
) || !((long)req_buf
& 3))
1218 WARN_ON(hs_req
->saved_req_buf
);
1220 dev_dbg(hsotg
->dev
, "%s: %s: buf=%p length=%d\n", __func__
,
1221 hs_ep
->ep
.name
, req_buf
, hs_req
->req
.length
);
1223 hs_req
->req
.buf
= kmalloc(hs_req
->req
.length
, GFP_ATOMIC
);
1224 if (!hs_req
->req
.buf
) {
1225 hs_req
->req
.buf
= req_buf
;
1227 "%s: unable to allocate memory for bounce buffer\n",
1232 /* Save actual buffer */
1233 hs_req
->saved_req_buf
= req_buf
;
1236 memcpy(hs_req
->req
.buf
, req_buf
, hs_req
->req
.length
);
1241 dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg
*hsotg
,
1242 struct dwc2_hsotg_ep
*hs_ep
,
1243 struct dwc2_hsotg_req
*hs_req
)
1245 /* If dma is not being used or buffer was aligned */
1246 if (!using_dma(hsotg
) || !hs_req
->saved_req_buf
)
1249 dev_dbg(hsotg
->dev
, "%s: %s: status=%d actual-length=%d\n", __func__
,
1250 hs_ep
->ep
.name
, hs_req
->req
.status
, hs_req
->req
.actual
);
1252 /* Copy data from bounce buffer on successful out transfer */
1253 if (!hs_ep
->dir_in
&& !hs_req
->req
.status
)
1254 memcpy(hs_req
->saved_req_buf
, hs_req
->req
.buf
,
1255 hs_req
->req
.actual
);
1257 /* Free bounce buffer */
1258 kfree(hs_req
->req
.buf
);
1260 hs_req
->req
.buf
= hs_req
->saved_req_buf
;
1261 hs_req
->saved_req_buf
= NULL
;
1265 * dwc2_gadget_target_frame_elapsed - Checks target frame
1266 * @hs_ep: The driver endpoint to check
1268 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1269 * corresponding transfer.
1271 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep
*hs_ep
)
1273 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
1274 u32 target_frame
= hs_ep
->target_frame
;
1275 u32 current_frame
= dwc2_hsotg_read_frameno(hsotg
);
1276 bool frame_overrun
= hs_ep
->frame_overrun
;
1278 if (!frame_overrun
&& current_frame
>= target_frame
)
1281 if (frame_overrun
&& current_frame
>= target_frame
&&
1282 ((current_frame
- target_frame
) < DSTS_SOFFN_LIMIT
/ 2))
1289 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1290 * @hsotg: The driver state
1291 * @hs_ep: the ep descriptor chain is for
1293 * Called to update EP0 structure's pointers depend on stage of
1296 static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg
*hsotg
,
1297 struct dwc2_hsotg_ep
*hs_ep
)
1299 switch (hsotg
->ep0_state
) {
1300 case DWC2_EP0_SETUP
:
1301 case DWC2_EP0_STATUS_OUT
:
1302 hs_ep
->desc_list
= hsotg
->setup_desc
[0];
1303 hs_ep
->desc_list_dma
= hsotg
->setup_desc_dma
[0];
1305 case DWC2_EP0_DATA_IN
:
1306 case DWC2_EP0_STATUS_IN
:
1307 hs_ep
->desc_list
= hsotg
->ctrl_in_desc
;
1308 hs_ep
->desc_list_dma
= hsotg
->ctrl_in_desc_dma
;
1310 case DWC2_EP0_DATA_OUT
:
1311 hs_ep
->desc_list
= hsotg
->ctrl_out_desc
;
1312 hs_ep
->desc_list_dma
= hsotg
->ctrl_out_desc_dma
;
1315 dev_err(hsotg
->dev
, "invalid EP 0 state in queue %d\n",
1323 static int dwc2_hsotg_ep_queue(struct usb_ep
*ep
, struct usb_request
*req
,
1326 struct dwc2_hsotg_req
*hs_req
= our_req(req
);
1327 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
1328 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
1332 dev_dbg(hs
->dev
, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1333 ep
->name
, req
, req
->length
, req
->buf
, req
->no_interrupt
,
1334 req
->zero
, req
->short_not_ok
);
1336 /* Prevent new request submission when controller is suspended */
1337 if (hs
->lx_state
== DWC2_L2
) {
1338 dev_dbg(hs
->dev
, "%s: don't submit request while suspended\n",
1343 /* initialise status of the request */
1344 INIT_LIST_HEAD(&hs_req
->queue
);
1346 req
->status
= -EINPROGRESS
;
1348 ret
= dwc2_hsotg_handle_unaligned_buf_start(hs
, hs_ep
, hs_req
);
1352 /* if we're using DMA, sync the buffers as necessary */
1353 if (using_dma(hs
)) {
1354 ret
= dwc2_hsotg_map_dma(hs
, hs_ep
, req
);
1358 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1359 if (using_desc_dma(hs
) && !hs_ep
->index
) {
1360 ret
= dwc2_gadget_set_ep0_desc_chain(hs
, hs_ep
);
1365 first
= list_empty(&hs_ep
->queue
);
1366 list_add_tail(&hs_req
->queue
, &hs_ep
->queue
);
1369 * Handle DDMA isochronous transfers separately - just add new entry
1370 * to the half of descriptor chain that is not processed by HW.
1371 * Transfer will be started once SW gets either one of NAK or
1372 * OutTknEpDis interrupts.
1374 if (using_desc_dma(hs
) && hs_ep
->isochronous
&&
1375 hs_ep
->target_frame
!= TARGET_FRAME_INITIAL
) {
1376 ret
= dwc2_gadget_fill_isoc_desc(hs_ep
, hs_req
->req
.dma
,
1377 hs_req
->req
.length
);
1379 dev_dbg(hs
->dev
, "%s: ISO desc chain full\n", __func__
);
1385 if (!hs_ep
->isochronous
) {
1386 dwc2_hsotg_start_req(hs
, hs_ep
, hs_req
, false);
1390 while (dwc2_gadget_target_frame_elapsed(hs_ep
))
1391 dwc2_gadget_incr_frame_num(hs_ep
);
1393 if (hs_ep
->target_frame
!= TARGET_FRAME_INITIAL
)
1394 dwc2_hsotg_start_req(hs
, hs_ep
, hs_req
, false);
1399 static int dwc2_hsotg_ep_queue_lock(struct usb_ep
*ep
, struct usb_request
*req
,
1402 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
1403 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
1404 unsigned long flags
= 0;
1407 spin_lock_irqsave(&hs
->lock
, flags
);
1408 ret
= dwc2_hsotg_ep_queue(ep
, req
, gfp_flags
);
1409 spin_unlock_irqrestore(&hs
->lock
, flags
);
1414 static void dwc2_hsotg_ep_free_request(struct usb_ep
*ep
,
1415 struct usb_request
*req
)
1417 struct dwc2_hsotg_req
*hs_req
= our_req(req
);
1423 * dwc2_hsotg_complete_oursetup - setup completion callback
1424 * @ep: The endpoint the request was on.
1425 * @req: The request completed.
1427 * Called on completion of any requests the driver itself
1428 * submitted that need cleaning up.
1430 static void dwc2_hsotg_complete_oursetup(struct usb_ep
*ep
,
1431 struct usb_request
*req
)
1433 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
1434 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
1436 dev_dbg(hsotg
->dev
, "%s: ep %p, req %p\n", __func__
, ep
, req
);
1438 dwc2_hsotg_ep_free_request(ep
, req
);
1442 * ep_from_windex - convert control wIndex value to endpoint
1443 * @hsotg: The driver state.
1444 * @windex: The control request wIndex field (in host order).
1446 * Convert the given wIndex into a pointer to an driver endpoint
1447 * structure, or return NULL if it is not a valid endpoint.
1449 static struct dwc2_hsotg_ep
*ep_from_windex(struct dwc2_hsotg
*hsotg
,
1452 struct dwc2_hsotg_ep
*ep
;
1453 int dir
= (windex
& USB_DIR_IN
) ? 1 : 0;
1454 int idx
= windex
& 0x7F;
1456 if (windex
>= 0x100)
1459 if (idx
> hsotg
->num_of_eps
)
1462 ep
= index_to_ep(hsotg
, idx
, dir
);
1464 if (idx
&& ep
->dir_in
!= dir
)
1471 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1472 * @hsotg: The driver state.
1473 * @testmode: requested usb test mode
1474 * Enable usb Test Mode requested by the Host.
1476 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg
*hsotg
, int testmode
)
1478 int dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
1480 dctl
&= ~DCTL_TSTCTL_MASK
;
1487 dctl
|= testmode
<< DCTL_TSTCTL_SHIFT
;
1492 dwc2_writel(dctl
, hsotg
->regs
+ DCTL
);
1497 * dwc2_hsotg_send_reply - send reply to control request
1498 * @hsotg: The device state
1500 * @buff: Buffer for request
1501 * @length: Length of reply.
1503 * Create a request and queue it on the given endpoint. This is useful as
1504 * an internal method of sending replies to certain control requests, etc.
1506 static int dwc2_hsotg_send_reply(struct dwc2_hsotg
*hsotg
,
1507 struct dwc2_hsotg_ep
*ep
,
1511 struct usb_request
*req
;
1514 dev_dbg(hsotg
->dev
, "%s: buff %p, len %d\n", __func__
, buff
, length
);
1516 req
= dwc2_hsotg_ep_alloc_request(&ep
->ep
, GFP_ATOMIC
);
1517 hsotg
->ep0_reply
= req
;
1519 dev_warn(hsotg
->dev
, "%s: cannot alloc req\n", __func__
);
1523 req
->buf
= hsotg
->ep0_buff
;
1524 req
->length
= length
;
1526 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1530 req
->complete
= dwc2_hsotg_complete_oursetup
;
1533 memcpy(req
->buf
, buff
, length
);
1535 ret
= dwc2_hsotg_ep_queue(&ep
->ep
, req
, GFP_ATOMIC
);
1537 dev_warn(hsotg
->dev
, "%s: cannot queue req\n", __func__
);
1545 * dwc2_hsotg_process_req_status - process request GET_STATUS
1546 * @hsotg: The device state
1547 * @ctrl: USB control request
1549 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg
*hsotg
,
1550 struct usb_ctrlrequest
*ctrl
)
1552 struct dwc2_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
1553 struct dwc2_hsotg_ep
*ep
;
1557 dev_dbg(hsotg
->dev
, "%s: USB_REQ_GET_STATUS\n", __func__
);
1560 dev_warn(hsotg
->dev
, "%s: direction out?\n", __func__
);
1564 switch (ctrl
->bRequestType
& USB_RECIP_MASK
) {
1565 case USB_RECIP_DEVICE
:
1567 * bit 0 => self powered
1568 * bit 1 => remote wakeup
1570 reply
= cpu_to_le16(0);
1573 case USB_RECIP_INTERFACE
:
1574 /* currently, the data result should be zero */
1575 reply
= cpu_to_le16(0);
1578 case USB_RECIP_ENDPOINT
:
1579 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
1583 reply
= cpu_to_le16(ep
->halted
? 1 : 0);
1590 if (le16_to_cpu(ctrl
->wLength
) != 2)
1593 ret
= dwc2_hsotg_send_reply(hsotg
, ep0
, &reply
, 2);
1595 dev_err(hsotg
->dev
, "%s: failed to send reply\n", __func__
);
1602 static int dwc2_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
, bool now
);
1605 * get_ep_head - return the first request on the endpoint
1606 * @hs_ep: The controller endpoint to get
1608 * Get the first request on the endpoint.
1610 static struct dwc2_hsotg_req
*get_ep_head(struct dwc2_hsotg_ep
*hs_ep
)
1612 return list_first_entry_or_null(&hs_ep
->queue
, struct dwc2_hsotg_req
,
1617 * dwc2_gadget_start_next_request - Starts next request from ep queue
1618 * @hs_ep: Endpoint structure
1620 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1621 * in its handler. Hence we need to unmask it here to be able to do
1622 * resynchronization.
1624 static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep
*hs_ep
)
1627 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
1628 int dir_in
= hs_ep
->dir_in
;
1629 struct dwc2_hsotg_req
*hs_req
;
1630 u32 epmsk_reg
= dir_in
? DIEPMSK
: DOEPMSK
;
1632 if (!list_empty(&hs_ep
->queue
)) {
1633 hs_req
= get_ep_head(hs_ep
);
1634 dwc2_hsotg_start_req(hsotg
, hs_ep
, hs_req
, false);
1637 if (!hs_ep
->isochronous
)
1641 dev_dbg(hsotg
->dev
, "%s: No more ISOC-IN requests\n",
1644 dev_dbg(hsotg
->dev
, "%s: No more ISOC-OUT requests\n",
1646 mask
= dwc2_readl(hsotg
->regs
+ epmsk_reg
);
1647 mask
|= DOEPMSK_OUTTKNEPDISMSK
;
1648 dwc2_writel(mask
, hsotg
->regs
+ epmsk_reg
);
1653 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1654 * @hsotg: The device state
1655 * @ctrl: USB control request
1657 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg
*hsotg
,
1658 struct usb_ctrlrequest
*ctrl
)
1660 struct dwc2_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
1661 struct dwc2_hsotg_req
*hs_req
;
1662 bool set
= (ctrl
->bRequest
== USB_REQ_SET_FEATURE
);
1663 struct dwc2_hsotg_ep
*ep
;
1670 dev_dbg(hsotg
->dev
, "%s: %s_FEATURE\n",
1671 __func__
, set
? "SET" : "CLEAR");
1673 wValue
= le16_to_cpu(ctrl
->wValue
);
1674 wIndex
= le16_to_cpu(ctrl
->wIndex
);
1675 recip
= ctrl
->bRequestType
& USB_RECIP_MASK
;
1678 case USB_RECIP_DEVICE
:
1680 case USB_DEVICE_TEST_MODE
:
1681 if ((wIndex
& 0xff) != 0)
1686 hsotg
->test_mode
= wIndex
>> 8;
1687 ret
= dwc2_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1690 "%s: failed to send reply\n", __func__
);
1699 case USB_RECIP_ENDPOINT
:
1700 ep
= ep_from_windex(hsotg
, wIndex
);
1702 dev_dbg(hsotg
->dev
, "%s: no endpoint for 0x%04x\n",
1708 case USB_ENDPOINT_HALT
:
1709 halted
= ep
->halted
;
1711 dwc2_hsotg_ep_sethalt(&ep
->ep
, set
, true);
1713 ret
= dwc2_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1716 "%s: failed to send reply\n", __func__
);
1721 * we have to complete all requests for ep if it was
1722 * halted, and the halt was cleared by CLEAR_FEATURE
1725 if (!set
&& halted
) {
1727 * If we have request in progress,
1733 list_del_init(&hs_req
->queue
);
1734 if (hs_req
->req
.complete
) {
1735 spin_unlock(&hsotg
->lock
);
1736 usb_gadget_giveback_request(
1737 &ep
->ep
, &hs_req
->req
);
1738 spin_lock(&hsotg
->lock
);
1742 /* If we have pending request, then start it */
1744 dwc2_gadget_start_next_request(ep
);
1759 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg
*hsotg
);
1762 * dwc2_hsotg_stall_ep0 - stall ep0
1763 * @hsotg: The device state
1765 * Set stall for ep0 as response for setup request.
1767 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg
*hsotg
)
1769 struct dwc2_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
1773 dev_dbg(hsotg
->dev
, "ep0 stall (dir=%d)\n", ep0
->dir_in
);
1774 reg
= (ep0
->dir_in
) ? DIEPCTL0
: DOEPCTL0
;
1777 * DxEPCTL_Stall will be cleared by EP once it has
1778 * taken effect, so no need to clear later.
1781 ctrl
= dwc2_readl(hsotg
->regs
+ reg
);
1782 ctrl
|= DXEPCTL_STALL
;
1783 ctrl
|= DXEPCTL_CNAK
;
1784 dwc2_writel(ctrl
, hsotg
->regs
+ reg
);
1787 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1788 ctrl
, reg
, dwc2_readl(hsotg
->regs
+ reg
));
1791 * complete won't be called, so we enqueue
1792 * setup request here
1794 dwc2_hsotg_enqueue_setup(hsotg
);
1798 * dwc2_hsotg_process_control - process a control request
1799 * @hsotg: The device state
1800 * @ctrl: The control request received
1802 * The controller has received the SETUP phase of a control request, and
1803 * needs to work out what to do next (and whether to pass it on to the
1806 static void dwc2_hsotg_process_control(struct dwc2_hsotg
*hsotg
,
1807 struct usb_ctrlrequest
*ctrl
)
1809 struct dwc2_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
1814 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1815 ctrl
->bRequestType
, ctrl
->bRequest
, ctrl
->wValue
,
1816 ctrl
->wIndex
, ctrl
->wLength
);
1818 if (ctrl
->wLength
== 0) {
1820 hsotg
->ep0_state
= DWC2_EP0_STATUS_IN
;
1821 } else if (ctrl
->bRequestType
& USB_DIR_IN
) {
1823 hsotg
->ep0_state
= DWC2_EP0_DATA_IN
;
1826 hsotg
->ep0_state
= DWC2_EP0_DATA_OUT
;
1829 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
) {
1830 switch (ctrl
->bRequest
) {
1831 case USB_REQ_SET_ADDRESS
:
1832 hsotg
->connected
= 1;
1833 dcfg
= dwc2_readl(hsotg
->regs
+ DCFG
);
1834 dcfg
&= ~DCFG_DEVADDR_MASK
;
1835 dcfg
|= (le16_to_cpu(ctrl
->wValue
) <<
1836 DCFG_DEVADDR_SHIFT
) & DCFG_DEVADDR_MASK
;
1837 dwc2_writel(dcfg
, hsotg
->regs
+ DCFG
);
1839 dev_info(hsotg
->dev
, "new address %d\n", ctrl
->wValue
);
1841 ret
= dwc2_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1844 case USB_REQ_GET_STATUS
:
1845 ret
= dwc2_hsotg_process_req_status(hsotg
, ctrl
);
1848 case USB_REQ_CLEAR_FEATURE
:
1849 case USB_REQ_SET_FEATURE
:
1850 ret
= dwc2_hsotg_process_req_feature(hsotg
, ctrl
);
1855 /* as a fallback, try delivering it to the driver to deal with */
1857 if (ret
== 0 && hsotg
->driver
) {
1858 spin_unlock(&hsotg
->lock
);
1859 ret
= hsotg
->driver
->setup(&hsotg
->gadget
, ctrl
);
1860 spin_lock(&hsotg
->lock
);
1862 dev_dbg(hsotg
->dev
, "driver->setup() ret %d\n", ret
);
1866 * the request is either unhandlable, or is not formatted correctly
1867 * so respond with a STALL for the status stage to indicate failure.
1871 dwc2_hsotg_stall_ep0(hsotg
);
1875 * dwc2_hsotg_complete_setup - completion of a setup transfer
1876 * @ep: The endpoint the request was on.
1877 * @req: The request completed.
1879 * Called on completion of any requests the driver itself submitted for
1882 static void dwc2_hsotg_complete_setup(struct usb_ep
*ep
,
1883 struct usb_request
*req
)
1885 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
1886 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
1888 if (req
->status
< 0) {
1889 dev_dbg(hsotg
->dev
, "%s: failed %d\n", __func__
, req
->status
);
1893 spin_lock(&hsotg
->lock
);
1894 if (req
->actual
== 0)
1895 dwc2_hsotg_enqueue_setup(hsotg
);
1897 dwc2_hsotg_process_control(hsotg
, req
->buf
);
1898 spin_unlock(&hsotg
->lock
);
1902 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1903 * @hsotg: The device state.
1905 * Enqueue a request on EP0 if necessary to received any SETUP packets
1906 * received from the host.
1908 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg
*hsotg
)
1910 struct usb_request
*req
= hsotg
->ctrl_req
;
1911 struct dwc2_hsotg_req
*hs_req
= our_req(req
);
1914 dev_dbg(hsotg
->dev
, "%s: queueing setup request\n", __func__
);
1918 req
->buf
= hsotg
->ctrl_buff
;
1919 req
->complete
= dwc2_hsotg_complete_setup
;
1921 if (!list_empty(&hs_req
->queue
)) {
1922 dev_dbg(hsotg
->dev
, "%s already queued???\n", __func__
);
1926 hsotg
->eps_out
[0]->dir_in
= 0;
1927 hsotg
->eps_out
[0]->send_zlp
= 0;
1928 hsotg
->ep0_state
= DWC2_EP0_SETUP
;
1930 ret
= dwc2_hsotg_ep_queue(&hsotg
->eps_out
[0]->ep
, req
, GFP_ATOMIC
);
1932 dev_err(hsotg
->dev
, "%s: failed queue (%d)\n", __func__
, ret
);
1934 * Don't think there's much we can do other than watch the
1940 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg
*hsotg
,
1941 struct dwc2_hsotg_ep
*hs_ep
)
1944 u8 index
= hs_ep
->index
;
1945 u32 epctl_reg
= hs_ep
->dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
1946 u32 epsiz_reg
= hs_ep
->dir_in
? DIEPTSIZ(index
) : DOEPTSIZ(index
);
1949 dev_dbg(hsotg
->dev
, "Sending zero-length packet on ep%d\n",
1952 dev_dbg(hsotg
->dev
, "Receiving zero-length packet on ep%d\n",
1954 if (using_desc_dma(hsotg
)) {
1955 /* Not specific buffer needed for ep0 ZLP */
1956 dma_addr_t dma
= hs_ep
->desc_list_dma
;
1958 dwc2_gadget_set_ep0_desc_chain(hsotg
, hs_ep
);
1959 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep
, dma
, 0);
1961 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1962 DXEPTSIZ_XFERSIZE(0), hsotg
->regs
+
1966 ctrl
= dwc2_readl(hsotg
->regs
+ epctl_reg
);
1967 ctrl
|= DXEPCTL_CNAK
; /* clear NAK set by core */
1968 ctrl
|= DXEPCTL_EPENA
; /* ensure ep enabled */
1969 ctrl
|= DXEPCTL_USBACTEP
;
1970 dwc2_writel(ctrl
, hsotg
->regs
+ epctl_reg
);
1974 * dwc2_hsotg_complete_request - complete a request given to us
1975 * @hsotg: The device state.
1976 * @hs_ep: The endpoint the request was on.
1977 * @hs_req: The request to complete.
1978 * @result: The result code (0 => Ok, otherwise errno)
1980 * The given request has finished, so call the necessary completion
1981 * if it has one and then look to see if we can start a new request
1984 * Note, expects the ep to already be locked as appropriate.
1986 static void dwc2_hsotg_complete_request(struct dwc2_hsotg
*hsotg
,
1987 struct dwc2_hsotg_ep
*hs_ep
,
1988 struct dwc2_hsotg_req
*hs_req
,
1992 dev_dbg(hsotg
->dev
, "%s: nothing to complete?\n", __func__
);
1996 dev_dbg(hsotg
->dev
, "complete: ep %p %s, req %p, %d => %p\n",
1997 hs_ep
, hs_ep
->ep
.name
, hs_req
, result
, hs_req
->req
.complete
);
2000 * only replace the status if we've not already set an error
2001 * from a previous transaction
2004 if (hs_req
->req
.status
== -EINPROGRESS
)
2005 hs_req
->req
.status
= result
;
2007 if (using_dma(hsotg
))
2008 dwc2_hsotg_unmap_dma(hsotg
, hs_ep
, hs_req
);
2010 dwc2_hsotg_handle_unaligned_buf_complete(hsotg
, hs_ep
, hs_req
);
2013 list_del_init(&hs_req
->queue
);
2016 * call the complete request with the locks off, just in case the
2017 * request tries to queue more work for this endpoint.
2020 if (hs_req
->req
.complete
) {
2021 spin_unlock(&hsotg
->lock
);
2022 usb_gadget_giveback_request(&hs_ep
->ep
, &hs_req
->req
);
2023 spin_lock(&hsotg
->lock
);
2026 /* In DDMA don't need to proceed to starting of next ISOC request */
2027 if (using_desc_dma(hsotg
) && hs_ep
->isochronous
)
2031 * Look to see if there is anything else to do. Note, the completion
2032 * of the previous request may have caused a new request to be started
2033 * so be careful when doing this.
2036 if (!hs_ep
->req
&& result
>= 0)
2037 dwc2_gadget_start_next_request(hs_ep
);
2041 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2042 * @hs_ep: The endpoint the request was on.
2044 * Get first request from the ep queue, determine descriptor on which complete
2045 * happened. SW based on isoc_chain_num discovers which half of the descriptor
2046 * chain is currently in use by HW, adjusts dma_address and calculates index
2047 * of completed descriptor based on the value of DEPDMA register. Update actual
2048 * length of request, giveback to gadget.
2050 static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep
*hs_ep
)
2052 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
2053 struct dwc2_hsotg_req
*hs_req
;
2054 struct usb_request
*ureq
;
2056 dma_addr_t dma_addr
;
2062 hs_req
= get_ep_head(hs_ep
);
2064 dev_warn(hsotg
->dev
, "%s: ISOC EP queue empty\n", __func__
);
2067 ureq
= &hs_req
->req
;
2069 dma_addr
= hs_ep
->desc_list_dma
;
2072 * If lower half of descriptor chain is currently use by SW,
2073 * that means higher half is being processed by HW, so shift
2074 * DMA address to higher half of descriptor chain.
2076 if (!hs_ep
->isoc_chain_num
)
2077 dma_addr
+= sizeof(struct dwc2_dma_desc
) *
2078 (MAX_DMA_DESC_NUM_GENERIC
/ 2);
2080 dma_reg
= hs_ep
->dir_in
? DIEPDMA(hs_ep
->index
) : DOEPDMA(hs_ep
->index
);
2081 depdma
= dwc2_readl(hsotg
->regs
+ dma_reg
);
2083 index
= (depdma
- dma_addr
) / sizeof(struct dwc2_dma_desc
) - 1;
2084 desc_sts
= hs_ep
->desc_list
[index
].status
;
2086 mask
= hs_ep
->dir_in
? DEV_DMA_ISOC_TX_NBYTES_MASK
:
2087 DEV_DMA_ISOC_RX_NBYTES_MASK
;
2088 ureq
->actual
= ureq
->length
-
2089 ((desc_sts
& mask
) >> DEV_DMA_ISOC_NBYTES_SHIFT
);
2091 /* Adjust actual length for ISOC Out if length is not align of 4 */
2092 if (!hs_ep
->dir_in
&& ureq
->length
& 0x3)
2093 ureq
->actual
+= 4 - (ureq
->length
& 0x3);
2095 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
2099 * dwc2_gadget_start_next_isoc_ddma - start next isoc request, if any.
2100 * @hs_ep: The isochronous endpoint to be re-enabled.
2102 * If ep has been disabled due to last descriptor servicing (IN endpoint) or
2103 * BNA (OUT endpoint) check the status of other half of descriptor chain that
2104 * was under SW control till HW was busy and restart the endpoint if needed.
2106 static void dwc2_gadget_start_next_isoc_ddma(struct dwc2_hsotg_ep
*hs_ep
)
2108 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
2112 u32 dma_addr
= hs_ep
->desc_list_dma
;
2113 unsigned char index
= hs_ep
->index
;
2115 dma_reg
= hs_ep
->dir_in
? DIEPDMA(index
) : DOEPDMA(index
);
2116 depctl
= hs_ep
->dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2118 ctrl
= dwc2_readl(hsotg
->regs
+ depctl
);
2121 * EP was disabled if HW has processed last descriptor or BNA was set.
2122 * So restart ep if SW has prepared new descriptor chain in ep_queue
2123 * routine while HW was busy.
2125 if (!(ctrl
& DXEPCTL_EPENA
)) {
2126 if (!hs_ep
->next_desc
) {
2127 dev_dbg(hsotg
->dev
, "%s: No more ISOC requests\n",
2132 dma_addr
+= sizeof(struct dwc2_dma_desc
) *
2133 (MAX_DMA_DESC_NUM_GENERIC
/ 2) *
2134 hs_ep
->isoc_chain_num
;
2135 dwc2_writel(dma_addr
, hsotg
->regs
+ dma_reg
);
2137 ctrl
|= DXEPCTL_EPENA
| DXEPCTL_CNAK
;
2138 dwc2_writel(ctrl
, hsotg
->regs
+ depctl
);
2140 /* Switch ISOC descriptor chain number being processed by SW*/
2141 hs_ep
->isoc_chain_num
= (hs_ep
->isoc_chain_num
^ 1) & 0x1;
2142 hs_ep
->next_desc
= 0;
2144 dev_dbg(hsotg
->dev
, "%s: Restarted isochronous endpoint\n",
2150 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2151 * @hsotg: The device state.
2152 * @ep_idx: The endpoint index for the data
2153 * @size: The size of data in the fifo, in bytes
2155 * The FIFO status shows there is data to read from the FIFO for a given
2156 * endpoint, so sort out whether we need to read the data into a request
2157 * that has been made for that endpoint.
2159 static void dwc2_hsotg_rx_data(struct dwc2_hsotg
*hsotg
, int ep_idx
, int size
)
2161 struct dwc2_hsotg_ep
*hs_ep
= hsotg
->eps_out
[ep_idx
];
2162 struct dwc2_hsotg_req
*hs_req
= hs_ep
->req
;
2163 void __iomem
*fifo
= hsotg
->regs
+ EPFIFO(ep_idx
);
2169 u32 epctl
= dwc2_readl(hsotg
->regs
+ DOEPCTL(ep_idx
));
2173 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2174 __func__
, size
, ep_idx
, epctl
);
2176 /* dump the data from the FIFO, we've nothing we can do */
2177 for (ptr
= 0; ptr
< size
; ptr
+= 4)
2178 (void)dwc2_readl(fifo
);
2184 read_ptr
= hs_req
->req
.actual
;
2185 max_req
= hs_req
->req
.length
- read_ptr
;
2187 dev_dbg(hsotg
->dev
, "%s: read %d/%d, done %d/%d\n",
2188 __func__
, to_read
, max_req
, read_ptr
, hs_req
->req
.length
);
2190 if (to_read
> max_req
) {
2192 * more data appeared than we where willing
2193 * to deal with in this request.
2196 /* currently we don't deal this */
2200 hs_ep
->total_data
+= to_read
;
2201 hs_req
->req
.actual
+= to_read
;
2202 to_read
= DIV_ROUND_UP(to_read
, 4);
2205 * note, we might over-write the buffer end by 3 bytes depending on
2206 * alignment of the data.
2208 ioread32_rep(fifo
, hs_req
->req
.buf
+ read_ptr
, to_read
);
2212 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2213 * @hsotg: The device instance
2214 * @dir_in: If IN zlp
2216 * Generate a zero-length IN packet request for terminating a SETUP
2219 * Note, since we don't write any data to the TxFIFO, then it is
2220 * currently believed that we do not need to wait for any space in
2223 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg
*hsotg
, bool dir_in
)
2225 /* eps_out[0] is used in both directions */
2226 hsotg
->eps_out
[0]->dir_in
= dir_in
;
2227 hsotg
->ep0_state
= dir_in
? DWC2_EP0_STATUS_IN
: DWC2_EP0_STATUS_OUT
;
2229 dwc2_hsotg_program_zlp(hsotg
, hsotg
->eps_out
[0]);
2232 static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg
*hsotg
,
2237 ctrl
= dwc2_readl(hsotg
->regs
+ epctl_reg
);
2238 if (ctrl
& DXEPCTL_EOFRNUM
)
2239 ctrl
|= DXEPCTL_SETEVENFR
;
2241 ctrl
|= DXEPCTL_SETODDFR
;
2242 dwc2_writel(ctrl
, hsotg
->regs
+ epctl_reg
);
2246 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2247 * @hs_ep - The endpoint on which transfer went
2249 * Iterate over endpoints descriptor chain and get info on bytes remained
2250 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2252 static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep
*hs_ep
)
2254 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
2255 unsigned int bytes_rem
= 0;
2256 struct dwc2_dma_desc
*desc
= hs_ep
->desc_list
;
2263 for (i
= 0; i
< hs_ep
->desc_count
; ++i
) {
2264 status
= desc
->status
;
2265 bytes_rem
+= status
& DEV_DMA_NBYTES_MASK
;
2267 if (status
& DEV_DMA_STS_MASK
)
2268 dev_err(hsotg
->dev
, "descriptor %d closed with %x\n",
2269 i
, status
& DEV_DMA_STS_MASK
);
2276 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2277 * @hsotg: The device instance
2278 * @epnum: The endpoint received from
2280 * The RXFIFO has delivered an OutDone event, which means that the data
2281 * transfer for an OUT endpoint has been completed, either by a short
2282 * packet or by the finish of a transfer.
2284 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg
*hsotg
, int epnum
)
2286 u32 epsize
= dwc2_readl(hsotg
->regs
+ DOEPTSIZ(epnum
));
2287 struct dwc2_hsotg_ep
*hs_ep
= hsotg
->eps_out
[epnum
];
2288 struct dwc2_hsotg_req
*hs_req
= hs_ep
->req
;
2289 struct usb_request
*req
= &hs_req
->req
;
2290 unsigned int size_left
= DXEPTSIZ_XFERSIZE_GET(epsize
);
2294 dev_dbg(hsotg
->dev
, "%s: no request active\n", __func__
);
2298 if (epnum
== 0 && hsotg
->ep0_state
== DWC2_EP0_STATUS_OUT
) {
2299 dev_dbg(hsotg
->dev
, "zlp packet received\n");
2300 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
2301 dwc2_hsotg_enqueue_setup(hsotg
);
2305 if (using_desc_dma(hsotg
))
2306 size_left
= dwc2_gadget_get_xfersize_ddma(hs_ep
);
2308 if (using_dma(hsotg
)) {
2309 unsigned int size_done
;
2312 * Calculate the size of the transfer by checking how much
2313 * is left in the endpoint size register and then working it
2314 * out from the amount we loaded for the transfer.
2316 * We need to do this as DMA pointers are always 32bit aligned
2317 * so may overshoot/undershoot the transfer.
2320 size_done
= hs_ep
->size_loaded
- size_left
;
2321 size_done
+= hs_ep
->last_load
;
2323 req
->actual
= size_done
;
2326 /* if there is more request to do, schedule new transfer */
2327 if (req
->actual
< req
->length
&& size_left
== 0) {
2328 dwc2_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
2332 if (req
->actual
< req
->length
&& req
->short_not_ok
) {
2333 dev_dbg(hsotg
->dev
, "%s: got %d/%d (short not ok) => error\n",
2334 __func__
, req
->actual
, req
->length
);
2337 * todo - what should we return here? there's no one else
2338 * even bothering to check the status.
2342 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2343 if (!using_desc_dma(hsotg
) && epnum
== 0 &&
2344 hsotg
->ep0_state
== DWC2_EP0_DATA_OUT
) {
2345 /* Move to STATUS IN */
2346 dwc2_hsotg_ep0_zlp(hsotg
, true);
2351 * Slave mode OUT transfers do not go through XferComplete so
2352 * adjust the ISOC parity here.
2354 if (!using_dma(hsotg
)) {
2355 if (hs_ep
->isochronous
&& hs_ep
->interval
== 1)
2356 dwc2_hsotg_change_ep_iso_parity(hsotg
, DOEPCTL(epnum
));
2357 else if (hs_ep
->isochronous
&& hs_ep
->interval
> 1)
2358 dwc2_gadget_incr_frame_num(hs_ep
);
2361 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, result
);
2365 * dwc2_hsotg_handle_rx - RX FIFO has data
2366 * @hsotg: The device instance
2368 * The IRQ handler has detected that the RX FIFO has some data in it
2369 * that requires processing, so find out what is in there and do the
2372 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2373 * chunks, so if you have x packets received on an endpoint you'll get x
2374 * FIFO events delivered, each with a packet's worth of data in it.
2376 * When using DMA, we should not be processing events from the RXFIFO
2377 * as the actual data should be sent to the memory directly and we turn
2378 * on the completion interrupts to get notifications of transfer completion.
2380 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg
*hsotg
)
2382 u32 grxstsr
= dwc2_readl(hsotg
->regs
+ GRXSTSP
);
2383 u32 epnum
, status
, size
;
2385 WARN_ON(using_dma(hsotg
));
2387 epnum
= grxstsr
& GRXSTS_EPNUM_MASK
;
2388 status
= grxstsr
& GRXSTS_PKTSTS_MASK
;
2390 size
= grxstsr
& GRXSTS_BYTECNT_MASK
;
2391 size
>>= GRXSTS_BYTECNT_SHIFT
;
2393 dev_dbg(hsotg
->dev
, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2394 __func__
, grxstsr
, size
, epnum
);
2396 switch ((status
& GRXSTS_PKTSTS_MASK
) >> GRXSTS_PKTSTS_SHIFT
) {
2397 case GRXSTS_PKTSTS_GLOBALOUTNAK
:
2398 dev_dbg(hsotg
->dev
, "GLOBALOUTNAK\n");
2401 case GRXSTS_PKTSTS_OUTDONE
:
2402 dev_dbg(hsotg
->dev
, "OutDone (Frame=0x%08x)\n",
2403 dwc2_hsotg_read_frameno(hsotg
));
2405 if (!using_dma(hsotg
))
2406 dwc2_hsotg_handle_outdone(hsotg
, epnum
);
2409 case GRXSTS_PKTSTS_SETUPDONE
:
2411 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2412 dwc2_hsotg_read_frameno(hsotg
),
2413 dwc2_readl(hsotg
->regs
+ DOEPCTL(0)));
2415 * Call dwc2_hsotg_handle_outdone here if it was not called from
2416 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2417 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2419 if (hsotg
->ep0_state
== DWC2_EP0_SETUP
)
2420 dwc2_hsotg_handle_outdone(hsotg
, epnum
);
2423 case GRXSTS_PKTSTS_OUTRX
:
2424 dwc2_hsotg_rx_data(hsotg
, epnum
, size
);
2427 case GRXSTS_PKTSTS_SETUPRX
:
2429 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2430 dwc2_hsotg_read_frameno(hsotg
),
2431 dwc2_readl(hsotg
->regs
+ DOEPCTL(0)));
2433 WARN_ON(hsotg
->ep0_state
!= DWC2_EP0_SETUP
);
2435 dwc2_hsotg_rx_data(hsotg
, epnum
, size
);
2439 dev_warn(hsotg
->dev
, "%s: unknown status %08x\n",
2442 dwc2_hsotg_dump(hsotg
);
2448 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2449 * @mps: The maximum packet size in bytes.
2451 static u32
dwc2_hsotg_ep0_mps(unsigned int mps
)
2455 return D0EPCTL_MPS_64
;
2457 return D0EPCTL_MPS_32
;
2459 return D0EPCTL_MPS_16
;
2461 return D0EPCTL_MPS_8
;
2464 /* bad max packet size, warn and return invalid result */
2470 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2471 * @hsotg: The driver state.
2472 * @ep: The index number of the endpoint
2473 * @mps: The maximum packet size in bytes
2474 * @mc: The multicount value
2476 * Configure the maximum packet size for the given endpoint, updating
2477 * the hardware control registers to reflect this.
2479 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg
*hsotg
,
2480 unsigned int ep
, unsigned int mps
,
2481 unsigned int mc
, unsigned int dir_in
)
2483 struct dwc2_hsotg_ep
*hs_ep
;
2484 void __iomem
*regs
= hsotg
->regs
;
2487 hs_ep
= index_to_ep(hsotg
, ep
, dir_in
);
2492 u32 mps_bytes
= mps
;
2494 /* EP0 is a special case */
2495 mps
= dwc2_hsotg_ep0_mps(mps_bytes
);
2498 hs_ep
->ep
.maxpacket
= mps_bytes
;
2506 hs_ep
->ep
.maxpacket
= mps
;
2510 reg
= dwc2_readl(regs
+ DIEPCTL(ep
));
2511 reg
&= ~DXEPCTL_MPS_MASK
;
2513 dwc2_writel(reg
, regs
+ DIEPCTL(ep
));
2515 reg
= dwc2_readl(regs
+ DOEPCTL(ep
));
2516 reg
&= ~DXEPCTL_MPS_MASK
;
2518 dwc2_writel(reg
, regs
+ DOEPCTL(ep
));
2524 dev_err(hsotg
->dev
, "ep%d: bad mps of %d\n", ep
, mps
);
2528 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2529 * @hsotg: The driver state
2530 * @idx: The index for the endpoint (0..15)
2532 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg
*hsotg
, unsigned int idx
)
2537 dwc2_writel(GRSTCTL_TXFNUM(idx
) | GRSTCTL_TXFFLSH
,
2538 hsotg
->regs
+ GRSTCTL
);
2540 /* wait until the fifo is flushed */
2544 val
= dwc2_readl(hsotg
->regs
+ GRSTCTL
);
2546 if ((val
& (GRSTCTL_TXFFLSH
)) == 0)
2549 if (--timeout
== 0) {
2551 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
2561 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2562 * @hsotg: The driver state
2563 * @hs_ep: The driver endpoint to check.
2565 * Check to see if there is a request that has data to send, and if so
2566 * make an attempt to write data into the FIFO.
2568 static int dwc2_hsotg_trytx(struct dwc2_hsotg
*hsotg
,
2569 struct dwc2_hsotg_ep
*hs_ep
)
2571 struct dwc2_hsotg_req
*hs_req
= hs_ep
->req
;
2573 if (!hs_ep
->dir_in
|| !hs_req
) {
2575 * if request is not enqueued, we disable interrupts
2576 * for endpoints, excepting ep0
2578 if (hs_ep
->index
!= 0)
2579 dwc2_hsotg_ctrl_epint(hsotg
, hs_ep
->index
,
2584 if (hs_req
->req
.actual
< hs_req
->req
.length
) {
2585 dev_dbg(hsotg
->dev
, "trying to write more for ep%d\n",
2587 return dwc2_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
2594 * dwc2_hsotg_complete_in - complete IN transfer
2595 * @hsotg: The device state.
2596 * @hs_ep: The endpoint that has just completed.
2598 * An IN transfer has been completed, update the transfer's state and then
2599 * call the relevant completion routines.
2601 static void dwc2_hsotg_complete_in(struct dwc2_hsotg
*hsotg
,
2602 struct dwc2_hsotg_ep
*hs_ep
)
2604 struct dwc2_hsotg_req
*hs_req
= hs_ep
->req
;
2605 u32 epsize
= dwc2_readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
2606 int size_left
, size_done
;
2609 dev_dbg(hsotg
->dev
, "XferCompl but no req\n");
2613 /* Finish ZLP handling for IN EP0 transactions */
2614 if (hs_ep
->index
== 0 && hsotg
->ep0_state
== DWC2_EP0_STATUS_IN
) {
2615 dev_dbg(hsotg
->dev
, "zlp packet sent\n");
2618 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2619 * changed to IN. Change back to complete OUT transfer request
2623 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
2624 if (hsotg
->test_mode
) {
2627 ret
= dwc2_hsotg_set_test_mode(hsotg
, hsotg
->test_mode
);
2629 dev_dbg(hsotg
->dev
, "Invalid Test #%d\n",
2631 dwc2_hsotg_stall_ep0(hsotg
);
2635 dwc2_hsotg_enqueue_setup(hsotg
);
2640 * Calculate the size of the transfer by checking how much is left
2641 * in the endpoint size register and then working it out from
2642 * the amount we loaded for the transfer.
2644 * We do this even for DMA, as the transfer may have incremented
2645 * past the end of the buffer (DMA transfers are always 32bit
2648 if (using_desc_dma(hsotg
)) {
2649 size_left
= dwc2_gadget_get_xfersize_ddma(hs_ep
);
2651 dev_err(hsotg
->dev
, "error parsing DDMA results %d\n",
2654 size_left
= DXEPTSIZ_XFERSIZE_GET(epsize
);
2657 size_done
= hs_ep
->size_loaded
- size_left
;
2658 size_done
+= hs_ep
->last_load
;
2660 if (hs_req
->req
.actual
!= size_done
)
2661 dev_dbg(hsotg
->dev
, "%s: adjusting size done %d => %d\n",
2662 __func__
, hs_req
->req
.actual
, size_done
);
2664 hs_req
->req
.actual
= size_done
;
2665 dev_dbg(hsotg
->dev
, "req->length:%d req->actual:%d req->zero:%d\n",
2666 hs_req
->req
.length
, hs_req
->req
.actual
, hs_req
->req
.zero
);
2668 if (!size_left
&& hs_req
->req
.actual
< hs_req
->req
.length
) {
2669 dev_dbg(hsotg
->dev
, "%s trying more for req...\n", __func__
);
2670 dwc2_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
2674 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
2675 if (hs_ep
->send_zlp
) {
2676 dwc2_hsotg_program_zlp(hsotg
, hs_ep
);
2677 hs_ep
->send_zlp
= 0;
2678 /* transfer will be completed on next complete interrupt */
2682 if (hs_ep
->index
== 0 && hsotg
->ep0_state
== DWC2_EP0_DATA_IN
) {
2683 /* Move to STATUS OUT */
2684 dwc2_hsotg_ep0_zlp(hsotg
, false);
2688 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
2692 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2693 * @hsotg: The device state.
2694 * @idx: Index of ep.
2695 * @dir_in: Endpoint direction 1-in 0-out.
2697 * Reads for endpoint with given index and direction, by masking
2698 * epint_reg with coresponding mask.
2700 static u32
dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg
*hsotg
,
2701 unsigned int idx
, int dir_in
)
2703 u32 epmsk_reg
= dir_in
? DIEPMSK
: DOEPMSK
;
2704 u32 epint_reg
= dir_in
? DIEPINT(idx
) : DOEPINT(idx
);
2709 mask
= dwc2_readl(hsotg
->regs
+ epmsk_reg
);
2710 diepempmsk
= dwc2_readl(hsotg
->regs
+ DIEPEMPMSK
);
2711 mask
|= ((diepempmsk
>> idx
) & 0x1) ? DIEPMSK_TXFIFOEMPTY
: 0;
2712 mask
|= DXEPINT_SETUP_RCVD
;
2714 ints
= dwc2_readl(hsotg
->regs
+ epint_reg
);
2720 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2721 * @hs_ep: The endpoint on which interrupt is asserted.
2723 * This interrupt indicates that the endpoint has been disabled per the
2724 * application's request.
2726 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2727 * in case of ISOC completes current request.
2729 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2730 * request starts it.
2732 static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep
*hs_ep
)
2734 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
2735 struct dwc2_hsotg_req
*hs_req
;
2736 unsigned char idx
= hs_ep
->index
;
2737 int dir_in
= hs_ep
->dir_in
;
2738 u32 epctl_reg
= dir_in
? DIEPCTL(idx
) : DOEPCTL(idx
);
2739 int dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
2741 dev_dbg(hsotg
->dev
, "%s: EPDisbld\n", __func__
);
2744 int epctl
= dwc2_readl(hsotg
->regs
+ epctl_reg
);
2746 dwc2_hsotg_txfifo_flush(hsotg
, hs_ep
->fifo_index
);
2748 if (hs_ep
->isochronous
) {
2749 dwc2_hsotg_complete_in(hsotg
, hs_ep
);
2753 if ((epctl
& DXEPCTL_STALL
) && (epctl
& DXEPCTL_EPTYPE_BULK
)) {
2754 int dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
2756 dctl
|= DCTL_CGNPINNAK
;
2757 dwc2_writel(dctl
, hsotg
->regs
+ DCTL
);
2762 if (dctl
& DCTL_GOUTNAKSTS
) {
2763 dctl
|= DCTL_CGOUTNAK
;
2764 dwc2_writel(dctl
, hsotg
->regs
+ DCTL
);
2767 if (!hs_ep
->isochronous
)
2770 if (list_empty(&hs_ep
->queue
)) {
2771 dev_dbg(hsotg
->dev
, "%s: complete_ep 0x%p, ep->queue empty!\n",
2777 hs_req
= get_ep_head(hs_ep
);
2779 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
,
2781 dwc2_gadget_incr_frame_num(hs_ep
);
2782 } while (dwc2_gadget_target_frame_elapsed(hs_ep
));
2784 dwc2_gadget_start_next_request(hs_ep
);
2788 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2789 * @hs_ep: The endpoint on which interrupt is asserted.
2791 * This is starting point for ISOC-OUT transfer, synchronization done with
2792 * first out token received from host while corresponding EP is disabled.
2794 * Device does not know initial frame in which out token will come. For this
2795 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2796 * getting this interrupt SW starts calculation for next transfer frame.
2798 static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep
*ep
)
2800 struct dwc2_hsotg
*hsotg
= ep
->parent
;
2801 int dir_in
= ep
->dir_in
;
2805 if (dir_in
|| !ep
->isochronous
)
2809 * Store frame in which irq was asserted here, as
2810 * it can change while completing request below.
2812 tmp
= dwc2_hsotg_read_frameno(hsotg
);
2814 dwc2_hsotg_complete_request(hsotg
, ep
, get_ep_head(ep
), -ENODATA
);
2816 if (using_desc_dma(hsotg
)) {
2817 if (ep
->target_frame
== TARGET_FRAME_INITIAL
) {
2818 /* Start first ISO Out */
2819 ep
->target_frame
= tmp
;
2820 dwc2_gadget_start_isoc_ddma(ep
);
2825 if (ep
->interval
> 1 &&
2826 ep
->target_frame
== TARGET_FRAME_INITIAL
) {
2830 dsts
= dwc2_readl(hsotg
->regs
+ DSTS
);
2831 ep
->target_frame
= dwc2_hsotg_read_frameno(hsotg
);
2832 dwc2_gadget_incr_frame_num(ep
);
2834 ctrl
= dwc2_readl(hsotg
->regs
+ DOEPCTL(ep
->index
));
2835 if (ep
->target_frame
& 0x1)
2836 ctrl
|= DXEPCTL_SETODDFR
;
2838 ctrl
|= DXEPCTL_SETEVENFR
;
2840 dwc2_writel(ctrl
, hsotg
->regs
+ DOEPCTL(ep
->index
));
2843 dwc2_gadget_start_next_request(ep
);
2844 doepmsk
= dwc2_readl(hsotg
->regs
+ DOEPMSK
);
2845 doepmsk
&= ~DOEPMSK_OUTTKNEPDISMSK
;
2846 dwc2_writel(doepmsk
, hsotg
->regs
+ DOEPMSK
);
2850 * dwc2_gadget_handle_nak - handle NAK interrupt
2851 * @hs_ep: The endpoint on which interrupt is asserted.
2853 * This is starting point for ISOC-IN transfer, synchronization done with
2854 * first IN token received from host while corresponding EP is disabled.
2856 * Device does not know when first one token will arrive from host. On first
2857 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2858 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2859 * sent in response to that as there was no data in FIFO. SW is basing on this
2860 * interrupt to obtain frame in which token has come and then based on the
2861 * interval calculates next frame for transfer.
2863 static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep
*hs_ep
)
2865 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
2866 int dir_in
= hs_ep
->dir_in
;
2868 if (!dir_in
|| !hs_ep
->isochronous
)
2871 if (hs_ep
->target_frame
== TARGET_FRAME_INITIAL
) {
2872 hs_ep
->target_frame
= dwc2_hsotg_read_frameno(hsotg
);
2874 if (using_desc_dma(hsotg
)) {
2875 dwc2_gadget_start_isoc_ddma(hs_ep
);
2879 if (hs_ep
->interval
> 1) {
2880 u32 ctrl
= dwc2_readl(hsotg
->regs
+
2881 DIEPCTL(hs_ep
->index
));
2882 if (hs_ep
->target_frame
& 0x1)
2883 ctrl
|= DXEPCTL_SETODDFR
;
2885 ctrl
|= DXEPCTL_SETEVENFR
;
2887 dwc2_writel(ctrl
, hsotg
->regs
+ DIEPCTL(hs_ep
->index
));
2890 dwc2_hsotg_complete_request(hsotg
, hs_ep
,
2891 get_ep_head(hs_ep
), 0);
2894 dwc2_gadget_incr_frame_num(hs_ep
);
2898 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
2899 * @hsotg: The driver state
2900 * @idx: The index for the endpoint (0..15)
2901 * @dir_in: Set if this is an IN endpoint
2903 * Process and clear any interrupt pending for an individual endpoint
2905 static void dwc2_hsotg_epint(struct dwc2_hsotg
*hsotg
, unsigned int idx
,
2908 struct dwc2_hsotg_ep
*hs_ep
= index_to_ep(hsotg
, idx
, dir_in
);
2909 u32 epint_reg
= dir_in
? DIEPINT(idx
) : DOEPINT(idx
);
2910 u32 epctl_reg
= dir_in
? DIEPCTL(idx
) : DOEPCTL(idx
);
2911 u32 epsiz_reg
= dir_in
? DIEPTSIZ(idx
) : DOEPTSIZ(idx
);
2915 ints
= dwc2_gadget_read_ep_interrupts(hsotg
, idx
, dir_in
);
2916 ctrl
= dwc2_readl(hsotg
->regs
+ epctl_reg
);
2918 /* Clear endpoint interrupts */
2919 dwc2_writel(ints
, hsotg
->regs
+ epint_reg
);
2922 dev_err(hsotg
->dev
, "%s:Interrupt for unconfigured ep%d(%s)\n",
2923 __func__
, idx
, dir_in
? "in" : "out");
2927 dev_dbg(hsotg
->dev
, "%s: ep%d(%s) DxEPINT=0x%08x\n",
2928 __func__
, idx
, dir_in
? "in" : "out", ints
);
2930 /* Don't process XferCompl interrupt if it is a setup packet */
2931 if (idx
== 0 && (ints
& (DXEPINT_SETUP
| DXEPINT_SETUP_RCVD
)))
2932 ints
&= ~DXEPINT_XFERCOMPL
;
2935 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
2936 * stage and xfercomplete was generated without SETUP phase done
2937 * interrupt. SW should parse received setup packet only after host's
2938 * exit from setup phase of control transfer.
2940 if (using_desc_dma(hsotg
) && idx
== 0 && !hs_ep
->dir_in
&&
2941 hsotg
->ep0_state
== DWC2_EP0_SETUP
&& !(ints
& DXEPINT_SETUP
))
2942 ints
&= ~DXEPINT_XFERCOMPL
;
2944 if (ints
& DXEPINT_XFERCOMPL
) {
2946 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
2947 __func__
, dwc2_readl(hsotg
->regs
+ epctl_reg
),
2948 dwc2_readl(hsotg
->regs
+ epsiz_reg
));
2950 /* In DDMA handle isochronous requests separately */
2951 if (using_desc_dma(hsotg
) && hs_ep
->isochronous
) {
2952 dwc2_gadget_complete_isoc_request_ddma(hs_ep
);
2953 /* Try to start next isoc request */
2954 dwc2_gadget_start_next_isoc_ddma(hs_ep
);
2955 } else if (dir_in
) {
2957 * We get OutDone from the FIFO, so we only
2958 * need to look at completing IN requests here
2959 * if operating slave mode
2961 if (hs_ep
->isochronous
&& hs_ep
->interval
> 1)
2962 dwc2_gadget_incr_frame_num(hs_ep
);
2964 dwc2_hsotg_complete_in(hsotg
, hs_ep
);
2965 if (ints
& DXEPINT_NAKINTRPT
)
2966 ints
&= ~DXEPINT_NAKINTRPT
;
2968 if (idx
== 0 && !hs_ep
->req
)
2969 dwc2_hsotg_enqueue_setup(hsotg
);
2970 } else if (using_dma(hsotg
)) {
2972 * We're using DMA, we need to fire an OutDone here
2973 * as we ignore the RXFIFO.
2975 if (hs_ep
->isochronous
&& hs_ep
->interval
> 1)
2976 dwc2_gadget_incr_frame_num(hs_ep
);
2978 dwc2_hsotg_handle_outdone(hsotg
, idx
);
2982 if (ints
& DXEPINT_EPDISBLD
)
2983 dwc2_gadget_handle_ep_disabled(hs_ep
);
2985 if (ints
& DXEPINT_OUTTKNEPDIS
)
2986 dwc2_gadget_handle_out_token_ep_disabled(hs_ep
);
2988 if (ints
& DXEPINT_NAKINTRPT
)
2989 dwc2_gadget_handle_nak(hs_ep
);
2991 if (ints
& DXEPINT_AHBERR
)
2992 dev_dbg(hsotg
->dev
, "%s: AHBErr\n", __func__
);
2994 if (ints
& DXEPINT_SETUP
) { /* Setup or Timeout */
2995 dev_dbg(hsotg
->dev
, "%s: Setup/Timeout\n", __func__
);
2997 if (using_dma(hsotg
) && idx
== 0) {
2999 * this is the notification we've received a
3000 * setup packet. In non-DMA mode we'd get this
3001 * from the RXFIFO, instead we need to process
3008 dwc2_hsotg_handle_outdone(hsotg
, 0);
3012 if (ints
& DXEPINT_STSPHSERCVD
) {
3013 dev_dbg(hsotg
->dev
, "%s: StsPhseRcvd\n", __func__
);
3015 /* Move to STATUS IN for DDMA */
3016 if (using_desc_dma(hsotg
))
3017 dwc2_hsotg_ep0_zlp(hsotg
, true);
3020 if (ints
& DXEPINT_BACK2BACKSETUP
)
3021 dev_dbg(hsotg
->dev
, "%s: B2BSetup/INEPNakEff\n", __func__
);
3023 if (ints
& DXEPINT_BNAINTR
) {
3024 dev_dbg(hsotg
->dev
, "%s: BNA interrupt\n", __func__
);
3027 * Try to start next isoc request, if any.
3028 * Sometimes the endpoint remains enabled after BNA interrupt
3029 * assertion, which is not expected, hence we can enter here
3032 if (hs_ep
->isochronous
)
3033 dwc2_gadget_start_next_isoc_ddma(hs_ep
);
3036 if (dir_in
&& !hs_ep
->isochronous
) {
3037 /* not sure if this is important, but we'll clear it anyway */
3038 if (ints
& DXEPINT_INTKNTXFEMP
) {
3039 dev_dbg(hsotg
->dev
, "%s: ep%d: INTknTXFEmpMsk\n",
3043 /* this probably means something bad is happening */
3044 if (ints
& DXEPINT_INTKNEPMIS
) {
3045 dev_warn(hsotg
->dev
, "%s: ep%d: INTknEP\n",
3049 /* FIFO has space or is empty (see GAHBCFG) */
3050 if (hsotg
->dedicated_fifos
&&
3051 ints
& DXEPINT_TXFEMP
) {
3052 dev_dbg(hsotg
->dev
, "%s: ep%d: TxFIFOEmpty\n",
3054 if (!using_dma(hsotg
))
3055 dwc2_hsotg_trytx(hsotg
, hs_ep
);
3061 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3062 * @hsotg: The device state.
3064 * Handle updating the device settings after the enumeration phase has
3067 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg
*hsotg
)
3069 u32 dsts
= dwc2_readl(hsotg
->regs
+ DSTS
);
3070 int ep0_mps
= 0, ep_mps
= 8;
3073 * This should signal the finish of the enumeration phase
3074 * of the USB handshaking, so we should now know what rate
3078 dev_dbg(hsotg
->dev
, "EnumDone (DSTS=0x%08x)\n", dsts
);
3081 * note, since we're limited by the size of transfer on EP0, and
3082 * it seems IN transfers must be a even number of packets we do
3083 * not advertise a 64byte MPS on EP0.
3086 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3087 switch ((dsts
& DSTS_ENUMSPD_MASK
) >> DSTS_ENUMSPD_SHIFT
) {
3088 case DSTS_ENUMSPD_FS
:
3089 case DSTS_ENUMSPD_FS48
:
3090 hsotg
->gadget
.speed
= USB_SPEED_FULL
;
3091 ep0_mps
= EP0_MPS_LIMIT
;
3095 case DSTS_ENUMSPD_HS
:
3096 hsotg
->gadget
.speed
= USB_SPEED_HIGH
;
3097 ep0_mps
= EP0_MPS_LIMIT
;
3101 case DSTS_ENUMSPD_LS
:
3102 hsotg
->gadget
.speed
= USB_SPEED_LOW
;
3106 * note, we don't actually support LS in this driver at the
3107 * moment, and the documentation seems to imply that it isn't
3108 * supported by the PHYs on some of the devices.
3112 dev_info(hsotg
->dev
, "new device is %s\n",
3113 usb_speed_string(hsotg
->gadget
.speed
));
3116 * we should now know the maximum packet size for an
3117 * endpoint, so set the endpoints to a default value.
3122 /* Initialize ep0 for both in and out directions */
3123 dwc2_hsotg_set_ep_maxpacket(hsotg
, 0, ep0_mps
, 0, 1);
3124 dwc2_hsotg_set_ep_maxpacket(hsotg
, 0, ep0_mps
, 0, 0);
3125 for (i
= 1; i
< hsotg
->num_of_eps
; i
++) {
3126 if (hsotg
->eps_in
[i
])
3127 dwc2_hsotg_set_ep_maxpacket(hsotg
, i
, ep_mps
,
3129 if (hsotg
->eps_out
[i
])
3130 dwc2_hsotg_set_ep_maxpacket(hsotg
, i
, ep_mps
,
3135 /* ensure after enumeration our EP0 is active */
3137 dwc2_hsotg_enqueue_setup(hsotg
);
3139 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3140 dwc2_readl(hsotg
->regs
+ DIEPCTL0
),
3141 dwc2_readl(hsotg
->regs
+ DOEPCTL0
));
3145 * kill_all_requests - remove all requests from the endpoint's queue
3146 * @hsotg: The device state.
3147 * @ep: The endpoint the requests may be on.
3148 * @result: The result code to use.
3150 * Go through the requests on the given endpoint and mark them
3151 * completed with the given result code.
3153 static void kill_all_requests(struct dwc2_hsotg
*hsotg
,
3154 struct dwc2_hsotg_ep
*ep
,
3157 struct dwc2_hsotg_req
*req
, *treq
;
3162 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
)
3163 dwc2_hsotg_complete_request(hsotg
, ep
, req
,
3166 if (!hsotg
->dedicated_fifos
)
3168 size
= (dwc2_readl(hsotg
->regs
+ DTXFSTS(ep
->fifo_index
)) & 0xffff) * 4;
3169 if (size
< ep
->fifo_size
)
3170 dwc2_hsotg_txfifo_flush(hsotg
, ep
->fifo_index
);
3174 * dwc2_hsotg_disconnect - disconnect service
3175 * @hsotg: The device state.
3177 * The device has been disconnected. Remove all current
3178 * transactions and signal the gadget driver that this
3181 void dwc2_hsotg_disconnect(struct dwc2_hsotg
*hsotg
)
3185 if (!hsotg
->connected
)
3188 hsotg
->connected
= 0;
3189 hsotg
->test_mode
= 0;
3191 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++) {
3192 if (hsotg
->eps_in
[ep
])
3193 kill_all_requests(hsotg
, hsotg
->eps_in
[ep
],
3195 if (hsotg
->eps_out
[ep
])
3196 kill_all_requests(hsotg
, hsotg
->eps_out
[ep
],
3200 call_gadget(hsotg
, disconnect
);
3201 hsotg
->lx_state
= DWC2_L3
;
3203 usb_gadget_set_state(&hsotg
->gadget
, USB_STATE_NOTATTACHED
);
3207 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3208 * @hsotg: The device state:
3209 * @periodic: True if this is a periodic FIFO interrupt
3211 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg
*hsotg
, bool periodic
)
3213 struct dwc2_hsotg_ep
*ep
;
3216 /* look through for any more data to transmit */
3217 for (epno
= 0; epno
< hsotg
->num_of_eps
; epno
++) {
3218 ep
= index_to_ep(hsotg
, epno
, 1);
3226 if ((periodic
&& !ep
->periodic
) ||
3227 (!periodic
&& ep
->periodic
))
3230 ret
= dwc2_hsotg_trytx(hsotg
, ep
);
3236 /* IRQ flags which will trigger a retry around the IRQ loop */
3237 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3242 * dwc2_hsotg_core_init - issue softreset to the core
3243 * @hsotg: The device state
3245 * Issue a soft reset to the core, and await the core finishing it.
3247 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg
*hsotg
,
3255 /* Kill any ep0 requests as controller will be reinitialized */
3256 kill_all_requests(hsotg
, hsotg
->eps_out
[0], -ECONNRESET
);
3259 if (dwc2_core_reset(hsotg
, true))
3263 * we must now enable ep0 ready for host detection and then
3264 * set configuration.
3267 /* keep other bits untouched (so e.g. forced modes are not lost) */
3268 usbcfg
= dwc2_readl(hsotg
->regs
+ GUSBCFG
);
3269 usbcfg
&= ~(GUSBCFG_TOUTCAL_MASK
| GUSBCFG_PHYIF16
| GUSBCFG_SRPCAP
|
3270 GUSBCFG_HNPCAP
| GUSBCFG_USBTRDTIM_MASK
);
3272 if (hsotg
->params
.phy_type
== DWC2_PHY_TYPE_PARAM_FS
&&
3273 (hsotg
->params
.speed
== DWC2_SPEED_PARAM_FULL
||
3274 hsotg
->params
.speed
== DWC2_SPEED_PARAM_LOW
)) {
3275 /* FS/LS Dedicated Transceiver Interface */
3276 usbcfg
|= GUSBCFG_PHYSEL
;
3278 /* set the PLL on, remove the HNP/SRP and set the PHY */
3279 val
= (hsotg
->phyif
== GUSBCFG_PHYIF8
) ? 9 : 5;
3280 usbcfg
|= hsotg
->phyif
| GUSBCFG_TOUTCAL(7) |
3281 (val
<< GUSBCFG_USBTRDTIM_SHIFT
);
3283 dwc2_writel(usbcfg
, hsotg
->regs
+ GUSBCFG
);
3285 dwc2_hsotg_init_fifo(hsotg
);
3288 __orr32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
3290 dcfg
|= DCFG_EPMISCNT(1);
3292 switch (hsotg
->params
.speed
) {
3293 case DWC2_SPEED_PARAM_LOW
:
3294 dcfg
|= DCFG_DEVSPD_LS
;
3296 case DWC2_SPEED_PARAM_FULL
:
3297 if (hsotg
->params
.phy_type
== DWC2_PHY_TYPE_PARAM_FS
)
3298 dcfg
|= DCFG_DEVSPD_FS48
;
3300 dcfg
|= DCFG_DEVSPD_FS
;
3303 dcfg
|= DCFG_DEVSPD_HS
;
3306 dwc2_writel(dcfg
, hsotg
->regs
+ DCFG
);
3308 /* Clear any pending OTG interrupts */
3309 dwc2_writel(0xffffffff, hsotg
->regs
+ GOTGINT
);
3311 /* Clear any pending interrupts */
3312 dwc2_writel(0xffffffff, hsotg
->regs
+ GINTSTS
);
3313 intmsk
= GINTSTS_ERLYSUSP
| GINTSTS_SESSREQINT
|
3314 GINTSTS_GOUTNAKEFF
| GINTSTS_GINNAKEFF
|
3315 GINTSTS_USBRST
| GINTSTS_RESETDET
|
3316 GINTSTS_ENUMDONE
| GINTSTS_OTGINT
|
3317 GINTSTS_USBSUSP
| GINTSTS_WKUPINT
;
3319 if (!using_desc_dma(hsotg
))
3320 intmsk
|= GINTSTS_INCOMPL_SOIN
| GINTSTS_INCOMPL_SOOUT
;
3322 if (!hsotg
->params
.external_id_pin_ctl
)
3323 intmsk
|= GINTSTS_CONIDSTSCHNG
;
3325 dwc2_writel(intmsk
, hsotg
->regs
+ GINTMSK
);
3327 if (using_dma(hsotg
)) {
3328 dwc2_writel(GAHBCFG_GLBL_INTR_EN
| GAHBCFG_DMA_EN
|
3329 (GAHBCFG_HBSTLEN_INCR4
<< GAHBCFG_HBSTLEN_SHIFT
),
3330 hsotg
->regs
+ GAHBCFG
);
3332 /* Set DDMA mode support in the core if needed */
3333 if (using_desc_dma(hsotg
))
3334 __orr32(hsotg
->regs
+ DCFG
, DCFG_DESCDMA_EN
);
3337 dwc2_writel(((hsotg
->dedicated_fifos
) ?
3338 (GAHBCFG_NP_TXF_EMP_LVL
|
3339 GAHBCFG_P_TXF_EMP_LVL
) : 0) |
3340 GAHBCFG_GLBL_INTR_EN
, hsotg
->regs
+ GAHBCFG
);
3344 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3345 * when we have no data to transfer. Otherwise we get being flooded by
3349 dwc2_writel(((hsotg
->dedicated_fifos
&& !using_dma(hsotg
)) ?
3350 DIEPMSK_TXFIFOEMPTY
| DIEPMSK_INTKNTXFEMPMSK
: 0) |
3351 DIEPMSK_EPDISBLDMSK
| DIEPMSK_XFERCOMPLMSK
|
3352 DIEPMSK_TIMEOUTMSK
| DIEPMSK_AHBERRMSK
,
3353 hsotg
->regs
+ DIEPMSK
);
3356 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3357 * DMA mode we may need this and StsPhseRcvd.
3359 dwc2_writel((using_dma(hsotg
) ? (DIEPMSK_XFERCOMPLMSK
|
3360 DOEPMSK_STSPHSERCVDMSK
) : 0) |
3361 DOEPMSK_EPDISBLDMSK
| DOEPMSK_AHBERRMSK
|
3363 hsotg
->regs
+ DOEPMSK
);
3365 /* Enable BNA interrupt for DDMA */
3366 if (using_desc_dma(hsotg
))
3367 __orr32(hsotg
->regs
+ DOEPMSK
, DOEPMSK_BNAMSK
);
3369 dwc2_writel(0, hsotg
->regs
+ DAINTMSK
);
3371 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3372 dwc2_readl(hsotg
->regs
+ DIEPCTL0
),
3373 dwc2_readl(hsotg
->regs
+ DOEPCTL0
));
3375 /* enable in and out endpoint interrupts */
3376 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_OEPINT
| GINTSTS_IEPINT
);
3379 * Enable the RXFIFO when in slave mode, as this is how we collect
3380 * the data. In DMA mode, we get events from the FIFO but also
3381 * things we cannot process, so do not use it.
3383 if (!using_dma(hsotg
))
3384 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_RXFLVL
);
3386 /* Enable interrupts for EP0 in and out */
3387 dwc2_hsotg_ctrl_epint(hsotg
, 0, 0, 1);
3388 dwc2_hsotg_ctrl_epint(hsotg
, 0, 1, 1);
3390 if (!is_usb_reset
) {
3391 __orr32(hsotg
->regs
+ DCTL
, DCTL_PWRONPRGDONE
);
3392 udelay(10); /* see openiboot */
3393 __bic32(hsotg
->regs
+ DCTL
, DCTL_PWRONPRGDONE
);
3396 dev_dbg(hsotg
->dev
, "DCTL=0x%08x\n", dwc2_readl(hsotg
->regs
+ DCTL
));
3399 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3400 * writing to the EPCTL register..
3403 /* set to read 1 8byte packet */
3404 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3405 DXEPTSIZ_XFERSIZE(8), hsotg
->regs
+ DOEPTSIZ0
);
3407 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg
->eps_out
[0]->ep
.maxpacket
) |
3408 DXEPCTL_CNAK
| DXEPCTL_EPENA
|
3410 hsotg
->regs
+ DOEPCTL0
);
3412 /* enable, but don't activate EP0in */
3413 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg
->eps_out
[0]->ep
.maxpacket
) |
3414 DXEPCTL_USBACTEP
, hsotg
->regs
+ DIEPCTL0
);
3416 dwc2_hsotg_enqueue_setup(hsotg
);
3418 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3419 dwc2_readl(hsotg
->regs
+ DIEPCTL0
),
3420 dwc2_readl(hsotg
->regs
+ DOEPCTL0
));
3422 /* clear global NAKs */
3423 val
= DCTL_CGOUTNAK
| DCTL_CGNPINNAK
;
3425 val
|= DCTL_SFTDISCON
;
3426 __orr32(hsotg
->regs
+ DCTL
, val
);
3428 /* must be at-least 3ms to allow bus to see disconnect */
3431 hsotg
->lx_state
= DWC2_L0
;
3434 static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg
*hsotg
)
3436 /* set the soft-disconnect bit */
3437 __orr32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
3440 void dwc2_hsotg_core_connect(struct dwc2_hsotg
*hsotg
)
3442 /* remove the soft-disconnect and let's go */
3443 __bic32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
3447 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3448 * @hsotg: The device state:
3450 * This interrupt indicates one of the following conditions occurred while
3451 * transmitting an ISOC transaction.
3452 * - Corrupted IN Token for ISOC EP.
3453 * - Packet not complete in FIFO.
3455 * The following actions will be taken:
3456 * - Determine the EP
3457 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3459 static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg
*hsotg
)
3461 struct dwc2_hsotg_ep
*hs_ep
;
3465 dev_dbg(hsotg
->dev
, "Incomplete isoc in interrupt received:\n");
3467 for (idx
= 1; idx
<= hsotg
->num_of_eps
; idx
++) {
3468 hs_ep
= hsotg
->eps_in
[idx
];
3469 epctrl
= dwc2_readl(hsotg
->regs
+ DIEPCTL(idx
));
3470 if ((epctrl
& DXEPCTL_EPENA
) && hs_ep
->isochronous
&&
3471 dwc2_gadget_target_frame_elapsed(hs_ep
)) {
3472 epctrl
|= DXEPCTL_SNAK
;
3473 epctrl
|= DXEPCTL_EPDIS
;
3474 dwc2_writel(epctrl
, hsotg
->regs
+ DIEPCTL(idx
));
3478 /* Clear interrupt */
3479 dwc2_writel(GINTSTS_INCOMPL_SOIN
, hsotg
->regs
+ GINTSTS
);
3483 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3484 * @hsotg: The device state:
3486 * This interrupt indicates one of the following conditions occurred while
3487 * transmitting an ISOC transaction.
3488 * - Corrupted OUT Token for ISOC EP.
3489 * - Packet not complete in FIFO.
3491 * The following actions will be taken:
3492 * - Determine the EP
3493 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3495 static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg
*hsotg
)
3500 struct dwc2_hsotg_ep
*hs_ep
;
3503 dev_dbg(hsotg
->dev
, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__
);
3505 for (idx
= 1; idx
<= hsotg
->num_of_eps
; idx
++) {
3506 hs_ep
= hsotg
->eps_out
[idx
];
3507 epctrl
= dwc2_readl(hsotg
->regs
+ DOEPCTL(idx
));
3508 if ((epctrl
& DXEPCTL_EPENA
) && hs_ep
->isochronous
&&
3509 dwc2_gadget_target_frame_elapsed(hs_ep
)) {
3510 /* Unmask GOUTNAKEFF interrupt */
3511 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
3512 gintmsk
|= GINTSTS_GOUTNAKEFF
;
3513 dwc2_writel(gintmsk
, hsotg
->regs
+ GINTMSK
);
3515 gintsts
= dwc2_readl(hsotg
->regs
+ GINTSTS
);
3516 if (!(gintsts
& GINTSTS_GOUTNAKEFF
))
3517 __orr32(hsotg
->regs
+ DCTL
, DCTL_SGOUTNAK
);
3521 /* Clear interrupt */
3522 dwc2_writel(GINTSTS_INCOMPL_SOOUT
, hsotg
->regs
+ GINTSTS
);
3526 * dwc2_hsotg_irq - handle device interrupt
3527 * @irq: The IRQ number triggered
3528 * @pw: The pw value when registered the handler.
3530 static irqreturn_t
dwc2_hsotg_irq(int irq
, void *pw
)
3532 struct dwc2_hsotg
*hsotg
= pw
;
3533 int retry_count
= 8;
3537 if (!dwc2_is_device_mode(hsotg
))
3540 spin_lock(&hsotg
->lock
);
3542 gintsts
= dwc2_readl(hsotg
->regs
+ GINTSTS
);
3543 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
3545 dev_dbg(hsotg
->dev
, "%s: %08x %08x (%08x) retry %d\n",
3546 __func__
, gintsts
, gintsts
& gintmsk
, gintmsk
, retry_count
);
3550 if (gintsts
& GINTSTS_RESETDET
) {
3551 dev_dbg(hsotg
->dev
, "%s: USBRstDet\n", __func__
);
3553 dwc2_writel(GINTSTS_RESETDET
, hsotg
->regs
+ GINTSTS
);
3555 /* This event must be used only if controller is suspended */
3556 if (hsotg
->lx_state
== DWC2_L2
) {
3557 dwc2_exit_hibernation(hsotg
, true);
3558 hsotg
->lx_state
= DWC2_L0
;
3562 if (gintsts
& (GINTSTS_USBRST
| GINTSTS_RESETDET
)) {
3563 u32 usb_status
= dwc2_readl(hsotg
->regs
+ GOTGCTL
);
3564 u32 connected
= hsotg
->connected
;
3566 dev_dbg(hsotg
->dev
, "%s: USBRst\n", __func__
);
3567 dev_dbg(hsotg
->dev
, "GNPTXSTS=%08x\n",
3568 dwc2_readl(hsotg
->regs
+ GNPTXSTS
));
3570 dwc2_writel(GINTSTS_USBRST
, hsotg
->regs
+ GINTSTS
);
3572 /* Report disconnection if it is not already done. */
3573 dwc2_hsotg_disconnect(hsotg
);
3575 /* Reset device address to zero */
3576 __bic32(hsotg
->regs
+ DCFG
, DCFG_DEVADDR_MASK
);
3578 if (usb_status
& GOTGCTL_BSESVLD
&& connected
)
3579 dwc2_hsotg_core_init_disconnected(hsotg
, true);
3582 if (gintsts
& GINTSTS_ENUMDONE
) {
3583 dwc2_writel(GINTSTS_ENUMDONE
, hsotg
->regs
+ GINTSTS
);
3585 dwc2_hsotg_irq_enumdone(hsotg
);
3588 if (gintsts
& (GINTSTS_OEPINT
| GINTSTS_IEPINT
)) {
3589 u32 daint
= dwc2_readl(hsotg
->regs
+ DAINT
);
3590 u32 daintmsk
= dwc2_readl(hsotg
->regs
+ DAINTMSK
);
3591 u32 daint_out
, daint_in
;
3595 daint_out
= daint
>> DAINT_OUTEP_SHIFT
;
3596 daint_in
= daint
& ~(daint_out
<< DAINT_OUTEP_SHIFT
);
3598 dev_dbg(hsotg
->dev
, "%s: daint=%08x\n", __func__
, daint
);
3600 for (ep
= 0; ep
< hsotg
->num_of_eps
&& daint_out
;
3601 ep
++, daint_out
>>= 1) {
3603 dwc2_hsotg_epint(hsotg
, ep
, 0);
3606 for (ep
= 0; ep
< hsotg
->num_of_eps
&& daint_in
;
3607 ep
++, daint_in
>>= 1) {
3609 dwc2_hsotg_epint(hsotg
, ep
, 1);
3613 /* check both FIFOs */
3615 if (gintsts
& GINTSTS_NPTXFEMP
) {
3616 dev_dbg(hsotg
->dev
, "NPTxFEmp\n");
3619 * Disable the interrupt to stop it happening again
3620 * unless one of these endpoint routines decides that
3621 * it needs re-enabling
3624 dwc2_hsotg_disable_gsint(hsotg
, GINTSTS_NPTXFEMP
);
3625 dwc2_hsotg_irq_fifoempty(hsotg
, false);
3628 if (gintsts
& GINTSTS_PTXFEMP
) {
3629 dev_dbg(hsotg
->dev
, "PTxFEmp\n");
3631 /* See note in GINTSTS_NPTxFEmp */
3633 dwc2_hsotg_disable_gsint(hsotg
, GINTSTS_PTXFEMP
);
3634 dwc2_hsotg_irq_fifoempty(hsotg
, true);
3637 if (gintsts
& GINTSTS_RXFLVL
) {
3639 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3640 * we need to retry dwc2_hsotg_handle_rx if this is still
3644 dwc2_hsotg_handle_rx(hsotg
);
3647 if (gintsts
& GINTSTS_ERLYSUSP
) {
3648 dev_dbg(hsotg
->dev
, "GINTSTS_ErlySusp\n");
3649 dwc2_writel(GINTSTS_ERLYSUSP
, hsotg
->regs
+ GINTSTS
);
3653 * these next two seem to crop-up occasionally causing the core
3654 * to shutdown the USB transfer, so try clearing them and logging
3658 if (gintsts
& GINTSTS_GOUTNAKEFF
) {
3662 struct dwc2_hsotg_ep
*hs_ep
;
3664 /* Mask this interrupt */
3665 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
3666 gintmsk
&= ~GINTSTS_GOUTNAKEFF
;
3667 dwc2_writel(gintmsk
, hsotg
->regs
+ GINTMSK
);
3669 dev_dbg(hsotg
->dev
, "GOUTNakEff triggered\n");
3670 for (idx
= 1; idx
<= hsotg
->num_of_eps
; idx
++) {
3671 hs_ep
= hsotg
->eps_out
[idx
];
3672 epctrl
= dwc2_readl(hsotg
->regs
+ DOEPCTL(idx
));
3674 if ((epctrl
& DXEPCTL_EPENA
) && hs_ep
->isochronous
) {
3675 epctrl
|= DXEPCTL_SNAK
;
3676 epctrl
|= DXEPCTL_EPDIS
;
3677 dwc2_writel(epctrl
, hsotg
->regs
+ DOEPCTL(idx
));
3681 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3684 if (gintsts
& GINTSTS_GINNAKEFF
) {
3685 dev_info(hsotg
->dev
, "GINNakEff triggered\n");
3687 __orr32(hsotg
->regs
+ DCTL
, DCTL_CGNPINNAK
);
3689 dwc2_hsotg_dump(hsotg
);
3692 if (gintsts
& GINTSTS_INCOMPL_SOIN
)
3693 dwc2_gadget_handle_incomplete_isoc_in(hsotg
);
3695 if (gintsts
& GINTSTS_INCOMPL_SOOUT
)
3696 dwc2_gadget_handle_incomplete_isoc_out(hsotg
);
3699 * if we've had fifo events, we should try and go around the
3700 * loop again to see if there's any point in returning yet.
3703 if (gintsts
& IRQ_RETRY_MASK
&& --retry_count
> 0)
3706 spin_unlock(&hsotg
->lock
);
3711 static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg
*hs_otg
, u32 reg
,
3712 u32 bit
, u32 timeout
)
3716 for (i
= 0; i
< timeout
; i
++) {
3717 if (dwc2_readl(hs_otg
->regs
+ reg
) & bit
)
3725 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg
*hsotg
,
3726 struct dwc2_hsotg_ep
*hs_ep
)
3731 epctrl_reg
= hs_ep
->dir_in
? DIEPCTL(hs_ep
->index
) :
3732 DOEPCTL(hs_ep
->index
);
3733 epint_reg
= hs_ep
->dir_in
? DIEPINT(hs_ep
->index
) :
3734 DOEPINT(hs_ep
->index
);
3736 dev_dbg(hsotg
->dev
, "%s: stopping transfer on %s\n", __func__
,
3739 if (hs_ep
->dir_in
) {
3740 if (hsotg
->dedicated_fifos
|| hs_ep
->periodic
) {
3741 __orr32(hsotg
->regs
+ epctrl_reg
, DXEPCTL_SNAK
);
3742 /* Wait for Nak effect */
3743 if (dwc2_hsotg_wait_bit_set(hsotg
, epint_reg
,
3744 DXEPINT_INEPNAKEFF
, 100))
3745 dev_warn(hsotg
->dev
,
3746 "%s: timeout DIEPINT.NAKEFF\n",
3749 __orr32(hsotg
->regs
+ DCTL
, DCTL_SGNPINNAK
);
3750 /* Wait for Nak effect */
3751 if (dwc2_hsotg_wait_bit_set(hsotg
, GINTSTS
,
3752 GINTSTS_GINNAKEFF
, 100))
3753 dev_warn(hsotg
->dev
,
3754 "%s: timeout GINTSTS.GINNAKEFF\n",
3758 if (!(dwc2_readl(hsotg
->regs
+ GINTSTS
) & GINTSTS_GOUTNAKEFF
))
3759 __orr32(hsotg
->regs
+ DCTL
, DCTL_SGOUTNAK
);
3761 /* Wait for global nak to take effect */
3762 if (dwc2_hsotg_wait_bit_set(hsotg
, GINTSTS
,
3763 GINTSTS_GOUTNAKEFF
, 100))
3764 dev_warn(hsotg
->dev
, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3769 __orr32(hsotg
->regs
+ epctrl_reg
, DXEPCTL_EPDIS
| DXEPCTL_SNAK
);
3771 /* Wait for ep to be disabled */
3772 if (dwc2_hsotg_wait_bit_set(hsotg
, epint_reg
, DXEPINT_EPDISBLD
, 100))
3773 dev_warn(hsotg
->dev
,
3774 "%s: timeout DOEPCTL.EPDisable\n", __func__
);
3776 /* Clear EPDISBLD interrupt */
3777 __orr32(hsotg
->regs
+ epint_reg
, DXEPINT_EPDISBLD
);
3779 if (hs_ep
->dir_in
) {
3780 unsigned short fifo_index
;
3782 if (hsotg
->dedicated_fifos
|| hs_ep
->periodic
)
3783 fifo_index
= hs_ep
->fifo_index
;
3788 dwc2_flush_tx_fifo(hsotg
, fifo_index
);
3790 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3791 if (!hsotg
->dedicated_fifos
&& !hs_ep
->periodic
)
3792 __orr32(hsotg
->regs
+ DCTL
, DCTL_CGNPINNAK
);
3795 /* Remove global NAKs */
3796 __orr32(hsotg
->regs
+ DCTL
, DCTL_CGOUTNAK
);
3801 * dwc2_hsotg_ep_enable - enable the given endpoint
3802 * @ep: The USB endpint to configure
3803 * @desc: The USB endpoint descriptor to configure with.
3805 * This is called from the USB gadget code's usb_ep_enable().
3807 static int dwc2_hsotg_ep_enable(struct usb_ep
*ep
,
3808 const struct usb_endpoint_descriptor
*desc
)
3810 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
3811 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
3812 unsigned long flags
;
3813 unsigned int index
= hs_ep
->index
;
3819 unsigned int dir_in
;
3820 unsigned int i
, val
, size
;
3824 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
3825 __func__
, ep
->name
, desc
->bEndpointAddress
, desc
->bmAttributes
,
3826 desc
->wMaxPacketSize
, desc
->bInterval
);
3828 /* not to be called for EP0 */
3830 dev_err(hsotg
->dev
, "%s: called for EP 0\n", __func__
);
3834 dir_in
= (desc
->bEndpointAddress
& USB_ENDPOINT_DIR_MASK
) ? 1 : 0;
3835 if (dir_in
!= hs_ep
->dir_in
) {
3836 dev_err(hsotg
->dev
, "%s: direction mismatch!\n", __func__
);
3840 mps
= usb_endpoint_maxp(desc
);
3841 mc
= usb_endpoint_maxp_mult(desc
);
3843 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
3845 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
3846 epctrl
= dwc2_readl(hsotg
->regs
+ epctrl_reg
);
3848 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
3849 __func__
, epctrl
, epctrl_reg
);
3851 /* Allocate DMA descriptor chain for non-ctrl endpoints */
3852 if (using_desc_dma(hsotg
) && !hs_ep
->desc_list
) {
3853 hs_ep
->desc_list
= dmam_alloc_coherent(hsotg
->dev
,
3854 MAX_DMA_DESC_NUM_GENERIC
*
3855 sizeof(struct dwc2_dma_desc
),
3856 &hs_ep
->desc_list_dma
, GFP_ATOMIC
);
3857 if (!hs_ep
->desc_list
) {
3863 spin_lock_irqsave(&hsotg
->lock
, flags
);
3865 epctrl
&= ~(DXEPCTL_EPTYPE_MASK
| DXEPCTL_MPS_MASK
);
3866 epctrl
|= DXEPCTL_MPS(mps
);
3869 * mark the endpoint as active, otherwise the core may ignore
3870 * transactions entirely for this endpoint
3872 epctrl
|= DXEPCTL_USBACTEP
;
3874 /* update the endpoint state */
3875 dwc2_hsotg_set_ep_maxpacket(hsotg
, hs_ep
->index
, mps
, mc
, dir_in
);
3877 /* default, set to non-periodic */
3878 hs_ep
->isochronous
= 0;
3879 hs_ep
->periodic
= 0;
3881 hs_ep
->interval
= desc
->bInterval
;
3883 switch (desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
) {
3884 case USB_ENDPOINT_XFER_ISOC
:
3885 epctrl
|= DXEPCTL_EPTYPE_ISO
;
3886 epctrl
|= DXEPCTL_SETEVENFR
;
3887 hs_ep
->isochronous
= 1;
3888 hs_ep
->interval
= 1 << (desc
->bInterval
- 1);
3889 hs_ep
->target_frame
= TARGET_FRAME_INITIAL
;
3890 hs_ep
->isoc_chain_num
= 0;
3891 hs_ep
->next_desc
= 0;
3893 hs_ep
->periodic
= 1;
3894 mask
= dwc2_readl(hsotg
->regs
+ DIEPMSK
);
3895 mask
|= DIEPMSK_NAKMSK
;
3896 dwc2_writel(mask
, hsotg
->regs
+ DIEPMSK
);
3898 mask
= dwc2_readl(hsotg
->regs
+ DOEPMSK
);
3899 mask
|= DOEPMSK_OUTTKNEPDISMSK
;
3900 dwc2_writel(mask
, hsotg
->regs
+ DOEPMSK
);
3904 case USB_ENDPOINT_XFER_BULK
:
3905 epctrl
|= DXEPCTL_EPTYPE_BULK
;
3908 case USB_ENDPOINT_XFER_INT
:
3910 hs_ep
->periodic
= 1;
3912 if (hsotg
->gadget
.speed
== USB_SPEED_HIGH
)
3913 hs_ep
->interval
= 1 << (desc
->bInterval
- 1);
3915 epctrl
|= DXEPCTL_EPTYPE_INTERRUPT
;
3918 case USB_ENDPOINT_XFER_CONTROL
:
3919 epctrl
|= DXEPCTL_EPTYPE_CONTROL
;
3924 * if the hardware has dedicated fifos, we must give each IN EP
3925 * a unique tx-fifo even if it is non-periodic.
3927 if (dir_in
&& hsotg
->dedicated_fifos
) {
3929 u32 fifo_size
= UINT_MAX
;
3931 size
= hs_ep
->ep
.maxpacket
* hs_ep
->mc
;
3932 for (i
= 1; i
< hsotg
->num_of_eps
; ++i
) {
3933 if (hsotg
->fifo_map
& (1 << i
))
3935 val
= dwc2_readl(hsotg
->regs
+ DPTXFSIZN(i
));
3936 val
= (val
>> FIFOSIZE_DEPTH_SHIFT
) * 4;
3939 /* Search for smallest acceptable fifo */
3940 if (val
< fifo_size
) {
3947 "%s: No suitable fifo found\n", __func__
);
3951 hsotg
->fifo_map
|= 1 << fifo_index
;
3952 epctrl
|= DXEPCTL_TXFNUM(fifo_index
);
3953 hs_ep
->fifo_index
= fifo_index
;
3954 hs_ep
->fifo_size
= fifo_size
;
3957 /* for non control endpoints, set PID to D0 */
3958 if (index
&& !hs_ep
->isochronous
)
3959 epctrl
|= DXEPCTL_SETD0PID
;
3961 dev_dbg(hsotg
->dev
, "%s: write DxEPCTL=0x%08x\n",
3964 dwc2_writel(epctrl
, hsotg
->regs
+ epctrl_reg
);
3965 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x\n",
3966 __func__
, dwc2_readl(hsotg
->regs
+ epctrl_reg
));
3968 /* enable the endpoint interrupt */
3969 dwc2_hsotg_ctrl_epint(hsotg
, index
, dir_in
, 1);
3972 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3975 if (ret
&& using_desc_dma(hsotg
) && hs_ep
->desc_list
) {
3976 dmam_free_coherent(hsotg
->dev
, MAX_DMA_DESC_NUM_GENERIC
*
3977 sizeof(struct dwc2_dma_desc
),
3978 hs_ep
->desc_list
, hs_ep
->desc_list_dma
);
3979 hs_ep
->desc_list
= NULL
;
3986 * dwc2_hsotg_ep_disable - disable given endpoint
3987 * @ep: The endpoint to disable.
3989 static int dwc2_hsotg_ep_disable(struct usb_ep
*ep
)
3991 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
3992 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
3993 int dir_in
= hs_ep
->dir_in
;
3994 int index
= hs_ep
->index
;
3995 unsigned long flags
;
3999 dev_dbg(hsotg
->dev
, "%s(ep %p)\n", __func__
, ep
);
4001 if (ep
== &hsotg
->eps_out
[0]->ep
) {
4002 dev_err(hsotg
->dev
, "%s: called for ep0\n", __func__
);
4006 if (hsotg
->op_state
!= OTG_STATE_B_PERIPHERAL
) {
4007 dev_err(hsotg
->dev
, "%s: called in host mode?\n", __func__
);
4011 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
4013 spin_lock_irqsave(&hsotg
->lock
, flags
);
4015 ctrl
= dwc2_readl(hsotg
->regs
+ epctrl_reg
);
4017 if (ctrl
& DXEPCTL_EPENA
)
4018 dwc2_hsotg_ep_stop_xfr(hsotg
, hs_ep
);
4020 ctrl
&= ~DXEPCTL_EPENA
;
4021 ctrl
&= ~DXEPCTL_USBACTEP
;
4022 ctrl
|= DXEPCTL_SNAK
;
4024 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
4025 dwc2_writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
4027 /* disable endpoint interrupts */
4028 dwc2_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 0);
4030 /* terminate all requests with shutdown */
4031 kill_all_requests(hsotg
, hs_ep
, -ESHUTDOWN
);
4033 hsotg
->fifo_map
&= ~(1 << hs_ep
->fifo_index
);
4034 hs_ep
->fifo_index
= 0;
4035 hs_ep
->fifo_size
= 0;
4037 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4042 * on_list - check request is on the given endpoint
4043 * @ep: The endpoint to check.
4044 * @test: The request to test if it is on the endpoint.
4046 static bool on_list(struct dwc2_hsotg_ep
*ep
, struct dwc2_hsotg_req
*test
)
4048 struct dwc2_hsotg_req
*req
, *treq
;
4050 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
4059 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4060 * @ep: The endpoint to dequeue.
4061 * @req: The request to be removed from a queue.
4063 static int dwc2_hsotg_ep_dequeue(struct usb_ep
*ep
, struct usb_request
*req
)
4065 struct dwc2_hsotg_req
*hs_req
= our_req(req
);
4066 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
4067 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
4068 unsigned long flags
;
4070 dev_dbg(hs
->dev
, "ep_dequeue(%p,%p)\n", ep
, req
);
4072 spin_lock_irqsave(&hs
->lock
, flags
);
4074 if (!on_list(hs_ep
, hs_req
)) {
4075 spin_unlock_irqrestore(&hs
->lock
, flags
);
4079 /* Dequeue already started request */
4080 if (req
== &hs_ep
->req
->req
)
4081 dwc2_hsotg_ep_stop_xfr(hs
, hs_ep
);
4083 dwc2_hsotg_complete_request(hs
, hs_ep
, hs_req
, -ECONNRESET
);
4084 spin_unlock_irqrestore(&hs
->lock
, flags
);
4090 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4091 * @ep: The endpoint to set halt.
4092 * @value: Set or unset the halt.
4093 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4094 * the endpoint is busy processing requests.
4096 * We need to stall the endpoint immediately if request comes from set_feature
4097 * protocol command handler.
4099 static int dwc2_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
, bool now
)
4101 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
4102 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
4103 int index
= hs_ep
->index
;
4108 dev_info(hs
->dev
, "%s(ep %p %s, %d)\n", __func__
, ep
, ep
->name
, value
);
4112 dwc2_hsotg_stall_ep0(hs
);
4115 "%s: can't clear halt on ep0\n", __func__
);
4119 if (hs_ep
->isochronous
) {
4120 dev_err(hs
->dev
, "%s is Isochronous Endpoint\n", ep
->name
);
4124 if (!now
&& value
&& !list_empty(&hs_ep
->queue
)) {
4125 dev_dbg(hs
->dev
, "%s request is pending, cannot halt\n",
4130 if (hs_ep
->dir_in
) {
4131 epreg
= DIEPCTL(index
);
4132 epctl
= dwc2_readl(hs
->regs
+ epreg
);
4135 epctl
|= DXEPCTL_STALL
| DXEPCTL_SNAK
;
4136 if (epctl
& DXEPCTL_EPENA
)
4137 epctl
|= DXEPCTL_EPDIS
;
4139 epctl
&= ~DXEPCTL_STALL
;
4140 xfertype
= epctl
& DXEPCTL_EPTYPE_MASK
;
4141 if (xfertype
== DXEPCTL_EPTYPE_BULK
||
4142 xfertype
== DXEPCTL_EPTYPE_INTERRUPT
)
4143 epctl
|= DXEPCTL_SETD0PID
;
4145 dwc2_writel(epctl
, hs
->regs
+ epreg
);
4147 epreg
= DOEPCTL(index
);
4148 epctl
= dwc2_readl(hs
->regs
+ epreg
);
4151 epctl
|= DXEPCTL_STALL
;
4153 epctl
&= ~DXEPCTL_STALL
;
4154 xfertype
= epctl
& DXEPCTL_EPTYPE_MASK
;
4155 if (xfertype
== DXEPCTL_EPTYPE_BULK
||
4156 xfertype
== DXEPCTL_EPTYPE_INTERRUPT
)
4157 epctl
|= DXEPCTL_SETD0PID
;
4159 dwc2_writel(epctl
, hs
->regs
+ epreg
);
4162 hs_ep
->halted
= value
;
4168 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4169 * @ep: The endpoint to set halt.
4170 * @value: Set or unset the halt.
4172 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep
*ep
, int value
)
4174 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
4175 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
4176 unsigned long flags
= 0;
4179 spin_lock_irqsave(&hs
->lock
, flags
);
4180 ret
= dwc2_hsotg_ep_sethalt(ep
, value
, false);
4181 spin_unlock_irqrestore(&hs
->lock
, flags
);
4186 static const struct usb_ep_ops dwc2_hsotg_ep_ops
= {
4187 .enable
= dwc2_hsotg_ep_enable
,
4188 .disable
= dwc2_hsotg_ep_disable
,
4189 .alloc_request
= dwc2_hsotg_ep_alloc_request
,
4190 .free_request
= dwc2_hsotg_ep_free_request
,
4191 .queue
= dwc2_hsotg_ep_queue_lock
,
4192 .dequeue
= dwc2_hsotg_ep_dequeue
,
4193 .set_halt
= dwc2_hsotg_ep_sethalt_lock
,
4194 /* note, don't believe we have any call for the fifo routines */
4198 * dwc2_hsotg_init - initialize the usb core
4199 * @hsotg: The driver state
4201 static void dwc2_hsotg_init(struct dwc2_hsotg
*hsotg
)
4205 /* unmask subset of endpoint interrupts */
4207 dwc2_writel(DIEPMSK_TIMEOUTMSK
| DIEPMSK_AHBERRMSK
|
4208 DIEPMSK_EPDISBLDMSK
| DIEPMSK_XFERCOMPLMSK
,
4209 hsotg
->regs
+ DIEPMSK
);
4211 dwc2_writel(DOEPMSK_SETUPMSK
| DOEPMSK_AHBERRMSK
|
4212 DOEPMSK_EPDISBLDMSK
| DOEPMSK_XFERCOMPLMSK
,
4213 hsotg
->regs
+ DOEPMSK
);
4215 dwc2_writel(0, hsotg
->regs
+ DAINTMSK
);
4217 /* Be in disconnected state until gadget is registered */
4218 __orr32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
4222 dev_dbg(hsotg
->dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4223 dwc2_readl(hsotg
->regs
+ GRXFSIZ
),
4224 dwc2_readl(hsotg
->regs
+ GNPTXFSIZ
));
4226 dwc2_hsotg_init_fifo(hsotg
);
4228 /* keep other bits untouched (so e.g. forced modes are not lost) */
4229 usbcfg
= dwc2_readl(hsotg
->regs
+ GUSBCFG
);
4230 usbcfg
&= ~(GUSBCFG_TOUTCAL_MASK
| GUSBCFG_PHYIF16
| GUSBCFG_SRPCAP
|
4231 GUSBCFG_HNPCAP
| GUSBCFG_USBTRDTIM_MASK
);
4233 /* set the PLL on, remove the HNP/SRP and set the PHY */
4234 trdtim
= (hsotg
->phyif
== GUSBCFG_PHYIF8
) ? 9 : 5;
4235 usbcfg
|= hsotg
->phyif
| GUSBCFG_TOUTCAL(7) |
4236 (trdtim
<< GUSBCFG_USBTRDTIM_SHIFT
);
4237 dwc2_writel(usbcfg
, hsotg
->regs
+ GUSBCFG
);
4239 if (using_dma(hsotg
))
4240 __orr32(hsotg
->regs
+ GAHBCFG
, GAHBCFG_DMA_EN
);
4244 * dwc2_hsotg_udc_start - prepare the udc for work
4245 * @gadget: The usb gadget state
4246 * @driver: The usb gadget driver
4248 * Perform initialization to prepare udc device and driver
4251 static int dwc2_hsotg_udc_start(struct usb_gadget
*gadget
,
4252 struct usb_gadget_driver
*driver
)
4254 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
4255 unsigned long flags
;
4259 pr_err("%s: called with no device\n", __func__
);
4264 dev_err(hsotg
->dev
, "%s: no driver\n", __func__
);
4268 if (driver
->max_speed
< USB_SPEED_FULL
)
4269 dev_err(hsotg
->dev
, "%s: bad speed\n", __func__
);
4271 if (!driver
->setup
) {
4272 dev_err(hsotg
->dev
, "%s: missing entry points\n", __func__
);
4276 WARN_ON(hsotg
->driver
);
4278 driver
->driver
.bus
= NULL
;
4279 hsotg
->driver
= driver
;
4280 hsotg
->gadget
.dev
.of_node
= hsotg
->dev
->of_node
;
4281 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
4283 if (hsotg
->dr_mode
== USB_DR_MODE_PERIPHERAL
) {
4284 ret
= dwc2_lowlevel_hw_enable(hsotg
);
4289 if (!IS_ERR_OR_NULL(hsotg
->uphy
))
4290 otg_set_peripheral(hsotg
->uphy
->otg
, &hsotg
->gadget
);
4292 spin_lock_irqsave(&hsotg
->lock
, flags
);
4293 if (dwc2_hw_is_device(hsotg
)) {
4294 dwc2_hsotg_init(hsotg
);
4295 dwc2_hsotg_core_init_disconnected(hsotg
, false);
4299 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4301 dev_info(hsotg
->dev
, "bound driver %s\n", driver
->driver
.name
);
4306 hsotg
->driver
= NULL
;
4311 * dwc2_hsotg_udc_stop - stop the udc
4312 * @gadget: The usb gadget state
4313 * @driver: The usb gadget driver
4315 * Stop udc hw block and stay tunned for future transmissions
4317 static int dwc2_hsotg_udc_stop(struct usb_gadget
*gadget
)
4319 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
4320 unsigned long flags
= 0;
4326 /* all endpoints should be shutdown */
4327 for (ep
= 1; ep
< hsotg
->num_of_eps
; ep
++) {
4328 if (hsotg
->eps_in
[ep
])
4329 dwc2_hsotg_ep_disable(&hsotg
->eps_in
[ep
]->ep
);
4330 if (hsotg
->eps_out
[ep
])
4331 dwc2_hsotg_ep_disable(&hsotg
->eps_out
[ep
]->ep
);
4334 spin_lock_irqsave(&hsotg
->lock
, flags
);
4336 hsotg
->driver
= NULL
;
4337 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
4340 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4342 if (!IS_ERR_OR_NULL(hsotg
->uphy
))
4343 otg_set_peripheral(hsotg
->uphy
->otg
, NULL
);
4345 if (hsotg
->dr_mode
== USB_DR_MODE_PERIPHERAL
)
4346 dwc2_lowlevel_hw_disable(hsotg
);
4352 * dwc2_hsotg_gadget_getframe - read the frame number
4353 * @gadget: The usb gadget state
4355 * Read the {micro} frame number
4357 static int dwc2_hsotg_gadget_getframe(struct usb_gadget
*gadget
)
4359 return dwc2_hsotg_read_frameno(to_hsotg(gadget
));
4363 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4364 * @gadget: The usb gadget state
4365 * @is_on: Current state of the USB PHY
4367 * Connect/Disconnect the USB PHY pullup
4369 static int dwc2_hsotg_pullup(struct usb_gadget
*gadget
, int is_on
)
4371 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
4372 unsigned long flags
= 0;
4374 dev_dbg(hsotg
->dev
, "%s: is_on: %d op_state: %d\n", __func__
, is_on
,
4377 /* Don't modify pullup state while in host mode */
4378 if (hsotg
->op_state
!= OTG_STATE_B_PERIPHERAL
) {
4379 hsotg
->enabled
= is_on
;
4383 spin_lock_irqsave(&hsotg
->lock
, flags
);
4386 dwc2_hsotg_core_init_disconnected(hsotg
, false);
4387 dwc2_hsotg_core_connect(hsotg
);
4389 dwc2_hsotg_core_disconnect(hsotg
);
4390 dwc2_hsotg_disconnect(hsotg
);
4394 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
4395 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4400 static int dwc2_hsotg_vbus_session(struct usb_gadget
*gadget
, int is_active
)
4402 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
4403 unsigned long flags
;
4405 dev_dbg(hsotg
->dev
, "%s: is_active: %d\n", __func__
, is_active
);
4406 spin_lock_irqsave(&hsotg
->lock
, flags
);
4409 * If controller is hibernated, it must exit from hibernation
4410 * before being initialized / de-initialized
4412 if (hsotg
->lx_state
== DWC2_L2
)
4413 dwc2_exit_hibernation(hsotg
, false);
4416 hsotg
->op_state
= OTG_STATE_B_PERIPHERAL
;
4418 dwc2_hsotg_core_init_disconnected(hsotg
, false);
4420 dwc2_hsotg_core_connect(hsotg
);
4422 dwc2_hsotg_core_disconnect(hsotg
);
4423 dwc2_hsotg_disconnect(hsotg
);
4426 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4431 * dwc2_hsotg_vbus_draw - report bMaxPower field
4432 * @gadget: The usb gadget state
4433 * @mA: Amount of current
4435 * Report how much power the device may consume to the phy.
4437 static int dwc2_hsotg_vbus_draw(struct usb_gadget
*gadget
, unsigned int mA
)
4439 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
4441 if (IS_ERR_OR_NULL(hsotg
->uphy
))
4443 return usb_phy_set_power(hsotg
->uphy
, mA
);
4446 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops
= {
4447 .get_frame
= dwc2_hsotg_gadget_getframe
,
4448 .udc_start
= dwc2_hsotg_udc_start
,
4449 .udc_stop
= dwc2_hsotg_udc_stop
,
4450 .pullup
= dwc2_hsotg_pullup
,
4451 .vbus_session
= dwc2_hsotg_vbus_session
,
4452 .vbus_draw
= dwc2_hsotg_vbus_draw
,
4456 * dwc2_hsotg_initep - initialise a single endpoint
4457 * @hsotg: The device state.
4458 * @hs_ep: The endpoint to be initialised.
4459 * @epnum: The endpoint number
4461 * Initialise the given endpoint (as part of the probe and device state
4462 * creation) to give to the gadget driver. Setup the endpoint name, any
4463 * direction information and other state that may be required.
4465 static void dwc2_hsotg_initep(struct dwc2_hsotg
*hsotg
,
4466 struct dwc2_hsotg_ep
*hs_ep
,
4479 hs_ep
->dir_in
= dir_in
;
4480 hs_ep
->index
= epnum
;
4482 snprintf(hs_ep
->name
, sizeof(hs_ep
->name
), "ep%d%s", epnum
, dir
);
4484 INIT_LIST_HEAD(&hs_ep
->queue
);
4485 INIT_LIST_HEAD(&hs_ep
->ep
.ep_list
);
4487 /* add to the list of endpoints known by the gadget driver */
4489 list_add_tail(&hs_ep
->ep
.ep_list
, &hsotg
->gadget
.ep_list
);
4491 hs_ep
->parent
= hsotg
;
4492 hs_ep
->ep
.name
= hs_ep
->name
;
4494 if (hsotg
->params
.speed
== DWC2_SPEED_PARAM_LOW
)
4495 usb_ep_set_maxpacket_limit(&hs_ep
->ep
, 8);
4497 usb_ep_set_maxpacket_limit(&hs_ep
->ep
,
4498 epnum
? 1024 : EP0_MPS_LIMIT
);
4499 hs_ep
->ep
.ops
= &dwc2_hsotg_ep_ops
;
4502 hs_ep
->ep
.caps
.type_control
= true;
4504 if (hsotg
->params
.speed
!= DWC2_SPEED_PARAM_LOW
) {
4505 hs_ep
->ep
.caps
.type_iso
= true;
4506 hs_ep
->ep
.caps
.type_bulk
= true;
4508 hs_ep
->ep
.caps
.type_int
= true;
4512 hs_ep
->ep
.caps
.dir_in
= true;
4514 hs_ep
->ep
.caps
.dir_out
= true;
4517 * if we're using dma, we need to set the next-endpoint pointer
4518 * to be something valid.
4521 if (using_dma(hsotg
)) {
4522 u32 next
= DXEPCTL_NEXTEP((epnum
+ 1) % 15);
4525 dwc2_writel(next
, hsotg
->regs
+ DIEPCTL(epnum
));
4527 dwc2_writel(next
, hsotg
->regs
+ DOEPCTL(epnum
));
4532 * dwc2_hsotg_hw_cfg - read HW configuration registers
4533 * @param: The device state
4535 * Read the USB core HW configuration registers
4537 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg
*hsotg
)
4543 /* check hardware configuration */
4545 hsotg
->num_of_eps
= hsotg
->hw_params
.num_dev_ep
;
4548 hsotg
->num_of_eps
++;
4550 hsotg
->eps_in
[0] = devm_kzalloc(hsotg
->dev
,
4551 sizeof(struct dwc2_hsotg_ep
),
4553 if (!hsotg
->eps_in
[0])
4555 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4556 hsotg
->eps_out
[0] = hsotg
->eps_in
[0];
4558 cfg
= hsotg
->hw_params
.dev_ep_dirs
;
4559 for (i
= 1, cfg
>>= 2; i
< hsotg
->num_of_eps
; i
++, cfg
>>= 2) {
4561 /* Direction in or both */
4562 if (!(ep_type
& 2)) {
4563 hsotg
->eps_in
[i
] = devm_kzalloc(hsotg
->dev
,
4564 sizeof(struct dwc2_hsotg_ep
), GFP_KERNEL
);
4565 if (!hsotg
->eps_in
[i
])
4568 /* Direction out or both */
4569 if (!(ep_type
& 1)) {
4570 hsotg
->eps_out
[i
] = devm_kzalloc(hsotg
->dev
,
4571 sizeof(struct dwc2_hsotg_ep
), GFP_KERNEL
);
4572 if (!hsotg
->eps_out
[i
])
4577 hsotg
->fifo_mem
= hsotg
->hw_params
.total_fifo_size
;
4578 hsotg
->dedicated_fifos
= hsotg
->hw_params
.en_multiple_tx_fifo
;
4580 dev_info(hsotg
->dev
, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4582 hsotg
->dedicated_fifos
? "dedicated" : "shared",
4588 * dwc2_hsotg_dump - dump state of the udc
4589 * @param: The device state
4591 static void dwc2_hsotg_dump(struct dwc2_hsotg
*hsotg
)
4594 struct device
*dev
= hsotg
->dev
;
4595 void __iomem
*regs
= hsotg
->regs
;
4599 dev_info(dev
, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4600 dwc2_readl(regs
+ DCFG
), dwc2_readl(regs
+ DCTL
),
4601 dwc2_readl(regs
+ DIEPMSK
));
4603 dev_info(dev
, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4604 dwc2_readl(regs
+ GAHBCFG
), dwc2_readl(regs
+ GHWCFG1
));
4606 dev_info(dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4607 dwc2_readl(regs
+ GRXFSIZ
), dwc2_readl(regs
+ GNPTXFSIZ
));
4609 /* show periodic fifo settings */
4611 for (idx
= 1; idx
< hsotg
->num_of_eps
; idx
++) {
4612 val
= dwc2_readl(regs
+ DPTXFSIZN(idx
));
4613 dev_info(dev
, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx
,
4614 val
>> FIFOSIZE_DEPTH_SHIFT
,
4615 val
& FIFOSIZE_STARTADDR_MASK
);
4618 for (idx
= 0; idx
< hsotg
->num_of_eps
; idx
++) {
4620 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx
,
4621 dwc2_readl(regs
+ DIEPCTL(idx
)),
4622 dwc2_readl(regs
+ DIEPTSIZ(idx
)),
4623 dwc2_readl(regs
+ DIEPDMA(idx
)));
4625 val
= dwc2_readl(regs
+ DOEPCTL(idx
));
4627 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4628 idx
, dwc2_readl(regs
+ DOEPCTL(idx
)),
4629 dwc2_readl(regs
+ DOEPTSIZ(idx
)),
4630 dwc2_readl(regs
+ DOEPDMA(idx
)));
4633 dev_info(dev
, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4634 dwc2_readl(regs
+ DVBUSDIS
), dwc2_readl(regs
+ DVBUSPULSE
));
4639 * dwc2_gadget_init - init function for gadget
4640 * @dwc2: The data structure for the DWC2 driver.
4641 * @irq: The IRQ number for the controller.
4643 int dwc2_gadget_init(struct dwc2_hsotg
*hsotg
, int irq
)
4645 struct device
*dev
= hsotg
->dev
;
4649 /* Dump fifo information */
4650 dev_dbg(dev
, "NonPeriodic TXFIFO size: %d\n",
4651 hsotg
->params
.g_np_tx_fifo_size
);
4652 dev_dbg(dev
, "RXFIFO size: %d\n", hsotg
->params
.g_rx_fifo_size
);
4654 hsotg
->gadget
.max_speed
= USB_SPEED_HIGH
;
4655 hsotg
->gadget
.ops
= &dwc2_hsotg_gadget_ops
;
4656 hsotg
->gadget
.name
= dev_name(dev
);
4657 if (hsotg
->dr_mode
== USB_DR_MODE_OTG
)
4658 hsotg
->gadget
.is_otg
= 1;
4659 else if (hsotg
->dr_mode
== USB_DR_MODE_PERIPHERAL
)
4660 hsotg
->op_state
= OTG_STATE_B_PERIPHERAL
;
4662 ret
= dwc2_hsotg_hw_cfg(hsotg
);
4664 dev_err(hsotg
->dev
, "Hardware configuration failed: %d\n", ret
);
4668 hsotg
->ctrl_buff
= devm_kzalloc(hsotg
->dev
,
4669 DWC2_CTRL_BUFF_SIZE
, GFP_KERNEL
);
4670 if (!hsotg
->ctrl_buff
)
4673 hsotg
->ep0_buff
= devm_kzalloc(hsotg
->dev
,
4674 DWC2_CTRL_BUFF_SIZE
, GFP_KERNEL
);
4675 if (!hsotg
->ep0_buff
)
4678 if (using_desc_dma(hsotg
)) {
4679 ret
= dwc2_gadget_alloc_ctrl_desc_chains(hsotg
);
4684 ret
= devm_request_irq(hsotg
->dev
, irq
, dwc2_hsotg_irq
, IRQF_SHARED
,
4685 dev_name(hsotg
->dev
), hsotg
);
4687 dev_err(dev
, "cannot claim IRQ for gadget\n");
4691 /* hsotg->num_of_eps holds number of EPs other than ep0 */
4693 if (hsotg
->num_of_eps
== 0) {
4694 dev_err(dev
, "wrong number of EPs (zero)\n");
4698 /* setup endpoint information */
4700 INIT_LIST_HEAD(&hsotg
->gadget
.ep_list
);
4701 hsotg
->gadget
.ep0
= &hsotg
->eps_out
[0]->ep
;
4703 /* allocate EP0 request */
4705 hsotg
->ctrl_req
= dwc2_hsotg_ep_alloc_request(&hsotg
->eps_out
[0]->ep
,
4707 if (!hsotg
->ctrl_req
) {
4708 dev_err(dev
, "failed to allocate ctrl req\n");
4712 /* initialise the endpoints now the core has been initialised */
4713 for (epnum
= 0; epnum
< hsotg
->num_of_eps
; epnum
++) {
4714 if (hsotg
->eps_in
[epnum
])
4715 dwc2_hsotg_initep(hsotg
, hsotg
->eps_in
[epnum
],
4717 if (hsotg
->eps_out
[epnum
])
4718 dwc2_hsotg_initep(hsotg
, hsotg
->eps_out
[epnum
],
4722 ret
= usb_add_gadget_udc(dev
, &hsotg
->gadget
);
4726 dwc2_hsotg_dump(hsotg
);
4732 * dwc2_hsotg_remove - remove function for hsotg driver
4733 * @pdev: The platform information for the driver
4735 int dwc2_hsotg_remove(struct dwc2_hsotg
*hsotg
)
4737 usb_del_gadget_udc(&hsotg
->gadget
);
4742 int dwc2_hsotg_suspend(struct dwc2_hsotg
*hsotg
)
4744 unsigned long flags
;
4746 if (hsotg
->lx_state
!= DWC2_L0
)
4749 if (hsotg
->driver
) {
4752 dev_info(hsotg
->dev
, "suspending usb gadget %s\n",
4753 hsotg
->driver
->driver
.name
);
4755 spin_lock_irqsave(&hsotg
->lock
, flags
);
4757 dwc2_hsotg_core_disconnect(hsotg
);
4758 dwc2_hsotg_disconnect(hsotg
);
4759 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
4760 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4762 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++) {
4763 if (hsotg
->eps_in
[ep
])
4764 dwc2_hsotg_ep_disable(&hsotg
->eps_in
[ep
]->ep
);
4765 if (hsotg
->eps_out
[ep
])
4766 dwc2_hsotg_ep_disable(&hsotg
->eps_out
[ep
]->ep
);
4773 int dwc2_hsotg_resume(struct dwc2_hsotg
*hsotg
)
4775 unsigned long flags
;
4777 if (hsotg
->lx_state
== DWC2_L2
)
4780 if (hsotg
->driver
) {
4781 dev_info(hsotg
->dev
, "resuming usb gadget %s\n",
4782 hsotg
->driver
->driver
.name
);
4784 spin_lock_irqsave(&hsotg
->lock
, flags
);
4785 dwc2_hsotg_core_init_disconnected(hsotg
, false);
4787 dwc2_hsotg_core_connect(hsotg
);
4788 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4795 * dwc2_backup_device_registers() - Backup controller device registers.
4796 * When suspending usb bus, registers needs to be backuped
4797 * if controller power is disabled once suspended.
4799 * @hsotg: Programming view of the DWC_otg controller
4801 int dwc2_backup_device_registers(struct dwc2_hsotg
*hsotg
)
4803 struct dwc2_dregs_backup
*dr
;
4806 dev_dbg(hsotg
->dev
, "%s\n", __func__
);
4808 /* Backup dev regs */
4809 dr
= &hsotg
->dr_backup
;
4811 dr
->dcfg
= dwc2_readl(hsotg
->regs
+ DCFG
);
4812 dr
->dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
4813 dr
->daintmsk
= dwc2_readl(hsotg
->regs
+ DAINTMSK
);
4814 dr
->diepmsk
= dwc2_readl(hsotg
->regs
+ DIEPMSK
);
4815 dr
->doepmsk
= dwc2_readl(hsotg
->regs
+ DOEPMSK
);
4817 for (i
= 0; i
< hsotg
->num_of_eps
; i
++) {
4819 dr
->diepctl
[i
] = dwc2_readl(hsotg
->regs
+ DIEPCTL(i
));
4821 /* Ensure DATA PID is correctly configured */
4822 if (dr
->diepctl
[i
] & DXEPCTL_DPID
)
4823 dr
->diepctl
[i
] |= DXEPCTL_SETD1PID
;
4825 dr
->diepctl
[i
] |= DXEPCTL_SETD0PID
;
4827 dr
->dieptsiz
[i
] = dwc2_readl(hsotg
->regs
+ DIEPTSIZ(i
));
4828 dr
->diepdma
[i
] = dwc2_readl(hsotg
->regs
+ DIEPDMA(i
));
4830 /* Backup OUT EPs */
4831 dr
->doepctl
[i
] = dwc2_readl(hsotg
->regs
+ DOEPCTL(i
));
4833 /* Ensure DATA PID is correctly configured */
4834 if (dr
->doepctl
[i
] & DXEPCTL_DPID
)
4835 dr
->doepctl
[i
] |= DXEPCTL_SETD1PID
;
4837 dr
->doepctl
[i
] |= DXEPCTL_SETD0PID
;
4839 dr
->doeptsiz
[i
] = dwc2_readl(hsotg
->regs
+ DOEPTSIZ(i
));
4840 dr
->doepdma
[i
] = dwc2_readl(hsotg
->regs
+ DOEPDMA(i
));
4847 * dwc2_restore_device_registers() - Restore controller device registers.
4848 * When resuming usb bus, device registers needs to be restored
4849 * if controller power were disabled.
4851 * @hsotg: Programming view of the DWC_otg controller
4853 int dwc2_restore_device_registers(struct dwc2_hsotg
*hsotg
)
4855 struct dwc2_dregs_backup
*dr
;
4859 dev_dbg(hsotg
->dev
, "%s\n", __func__
);
4861 /* Restore dev regs */
4862 dr
= &hsotg
->dr_backup
;
4864 dev_err(hsotg
->dev
, "%s: no device registers to restore\n",
4870 dwc2_writel(dr
->dcfg
, hsotg
->regs
+ DCFG
);
4871 dwc2_writel(dr
->dctl
, hsotg
->regs
+ DCTL
);
4872 dwc2_writel(dr
->daintmsk
, hsotg
->regs
+ DAINTMSK
);
4873 dwc2_writel(dr
->diepmsk
, hsotg
->regs
+ DIEPMSK
);
4874 dwc2_writel(dr
->doepmsk
, hsotg
->regs
+ DOEPMSK
);
4876 for (i
= 0; i
< hsotg
->num_of_eps
; i
++) {
4877 /* Restore IN EPs */
4878 dwc2_writel(dr
->diepctl
[i
], hsotg
->regs
+ DIEPCTL(i
));
4879 dwc2_writel(dr
->dieptsiz
[i
], hsotg
->regs
+ DIEPTSIZ(i
));
4880 dwc2_writel(dr
->diepdma
[i
], hsotg
->regs
+ DIEPDMA(i
));
4882 /* Restore OUT EPs */
4883 dwc2_writel(dr
->doepctl
[i
], hsotg
->regs
+ DOEPCTL(i
));
4884 dwc2_writel(dr
->doeptsiz
[i
], hsotg
->regs
+ DOEPTSIZ(i
));
4885 dwc2_writel(dr
->doepdma
[i
], hsotg
->regs
+ DOEPDMA(i
));
4888 /* Set the Power-On Programming done bit */
4889 dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
4890 dctl
|= DCTL_PWRONPRGDONE
;
4891 dwc2_writel(dctl
, hsotg
->regs
+ DCTL
);