1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
11 * S3C USB2.0 High-speed / OtG driver
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/interrupt.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/mutex.h>
21 #include <linux/seq_file.h>
22 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/of_platform.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
29 #include <linux/usb/phy.h>
34 /* conversion functions */
35 static inline struct dwc2_hsotg_req
*our_req(struct usb_request
*req
)
37 return container_of(req
, struct dwc2_hsotg_req
, req
);
40 static inline struct dwc2_hsotg_ep
*our_ep(struct usb_ep
*ep
)
42 return container_of(ep
, struct dwc2_hsotg_ep
, ep
);
45 static inline struct dwc2_hsotg
*to_hsotg(struct usb_gadget
*gadget
)
47 return container_of(gadget
, struct dwc2_hsotg
, gadget
);
50 static inline void __orr32(void __iomem
*ptr
, u32 val
)
52 dwc2_writel(dwc2_readl(ptr
) | val
, ptr
);
55 static inline void __bic32(void __iomem
*ptr
, u32 val
)
57 dwc2_writel(dwc2_readl(ptr
) & ~val
, ptr
);
60 static inline struct dwc2_hsotg_ep
*index_to_ep(struct dwc2_hsotg
*hsotg
,
61 u32 ep_index
, u32 dir_in
)
64 return hsotg
->eps_in
[ep_index
];
66 return hsotg
->eps_out
[ep_index
];
69 /* forward declaration of functions */
70 static void dwc2_hsotg_dump(struct dwc2_hsotg
*hsotg
);
73 * using_dma - return the DMA status of the driver.
74 * @hsotg: The driver state.
76 * Return true if we're using DMA.
78 * Currently, we have the DMA support code worked into everywhere
79 * that needs it, but the AMBA DMA implementation in the hardware can
80 * only DMA from 32bit aligned addresses. This means that gadgets such
81 * as the CDC Ethernet cannot work as they often pass packets which are
84 * Unfortunately the choice to use DMA or not is global to the controller
85 * and seems to be only settable when the controller is being put through
86 * a core reset. This means we either need to fix the gadgets to take
87 * account of DMA alignment, or add bounce buffers (yuerk).
89 * g_using_dma is set depending on dts flag.
91 static inline bool using_dma(struct dwc2_hsotg
*hsotg
)
93 return hsotg
->params
.g_dma
;
97 * using_desc_dma - return the descriptor DMA status of the driver.
98 * @hsotg: The driver state.
100 * Return true if we're using descriptor DMA.
102 static inline bool using_desc_dma(struct dwc2_hsotg
*hsotg
)
104 return hsotg
->params
.g_dma_desc
;
108 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
109 * @hs_ep: The endpoint
110 * @increment: The value to increment by
112 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
113 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
115 static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep
*hs_ep
)
117 hs_ep
->target_frame
+= hs_ep
->interval
;
118 if (hs_ep
->target_frame
> DSTS_SOFFN_LIMIT
) {
119 hs_ep
->frame_overrun
= 1;
120 hs_ep
->target_frame
&= DSTS_SOFFN_LIMIT
;
122 hs_ep
->frame_overrun
= 0;
127 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
128 * @hsotg: The device state
129 * @ints: A bitmask of the interrupts to enable
131 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg
*hsotg
, u32 ints
)
133 u32 gsintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
136 new_gsintmsk
= gsintmsk
| ints
;
138 if (new_gsintmsk
!= gsintmsk
) {
139 dev_dbg(hsotg
->dev
, "gsintmsk now 0x%08x\n", new_gsintmsk
);
140 dwc2_writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
145 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
146 * @hsotg: The device state
147 * @ints: A bitmask of the interrupts to enable
149 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg
*hsotg
, u32 ints
)
151 u32 gsintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
154 new_gsintmsk
= gsintmsk
& ~ints
;
156 if (new_gsintmsk
!= gsintmsk
)
157 dwc2_writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
161 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
162 * @hsotg: The device state
163 * @ep: The endpoint index
164 * @dir_in: True if direction is in.
165 * @en: The enable value, true to enable
167 * Set or clear the mask for an individual endpoint's interrupt
170 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg
*hsotg
,
171 unsigned int ep
, unsigned int dir_in
,
181 local_irq_save(flags
);
182 daint
= dwc2_readl(hsotg
->regs
+ DAINTMSK
);
187 dwc2_writel(daint
, hsotg
->regs
+ DAINTMSK
);
188 local_irq_restore(flags
);
192 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
194 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg
*hsotg
)
196 if (hsotg
->hw_params
.en_multiple_tx_fifo
)
197 /* In dedicated FIFO mode we need count of IN EPs */
198 return hsotg
->hw_params
.num_dev_in_eps
;
200 /* In shared FIFO mode we need count of Periodic IN EPs */
201 return hsotg
->hw_params
.num_dev_perio_in_ep
;
205 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
206 * device mode TX FIFOs
208 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg
*hsotg
)
214 np_tx_fifo_size
= min_t(u32
, hsotg
->hw_params
.dev_nperio_tx_fifo_size
,
215 hsotg
->params
.g_np_tx_fifo_size
);
217 /* Get Endpoint Info Control block size in DWORDs. */
218 tx_addr_max
= hsotg
->hw_params
.total_fifo_size
;
220 addr
= hsotg
->params
.g_rx_fifo_size
+ np_tx_fifo_size
;
221 if (tx_addr_max
<= addr
)
224 return tx_addr_max
- addr
;
228 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
231 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg
*hsotg
)
236 tx_fifo_depth
= dwc2_hsotg_tx_fifo_total_depth(hsotg
);
238 tx_fifo_count
= dwc2_hsotg_tx_fifo_count(hsotg
);
241 return tx_fifo_depth
;
243 return tx_fifo_depth
/ tx_fifo_count
;
247 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
248 * @hsotg: The device instance.
250 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg
*hsotg
)
256 u32
*txfsz
= hsotg
->params
.g_tx_fifo_size
;
258 /* Reset fifo map if not correctly cleared during previous session */
259 WARN_ON(hsotg
->fifo_map
);
262 /* set RX/NPTX FIFO sizes */
263 dwc2_writel(hsotg
->params
.g_rx_fifo_size
, hsotg
->regs
+ GRXFSIZ
);
264 dwc2_writel((hsotg
->params
.g_rx_fifo_size
<< FIFOSIZE_STARTADDR_SHIFT
) |
265 (hsotg
->params
.g_np_tx_fifo_size
<< FIFOSIZE_DEPTH_SHIFT
),
266 hsotg
->regs
+ GNPTXFSIZ
);
269 * arange all the rest of the TX FIFOs, as some versions of this
270 * block have overlapping default addresses. This also ensures
271 * that if the settings have been changed, then they are set to
275 /* start at the end of the GNPTXFSIZ, rounded up */
276 addr
= hsotg
->params
.g_rx_fifo_size
+ hsotg
->params
.g_np_tx_fifo_size
;
279 * Configure fifos sizes from provided configuration and assign
280 * them to endpoints dynamically according to maxpacket size value of
283 for (ep
= 1; ep
< MAX_EPS_CHANNELS
; ep
++) {
287 val
|= txfsz
[ep
] << FIFOSIZE_DEPTH_SHIFT
;
288 WARN_ONCE(addr
+ txfsz
[ep
] > hsotg
->fifo_mem
,
289 "insufficient fifo memory");
292 dwc2_writel(val
, hsotg
->regs
+ DPTXFSIZN(ep
));
293 val
= dwc2_readl(hsotg
->regs
+ DPTXFSIZN(ep
));
296 dwc2_writel(hsotg
->hw_params
.total_fifo_size
|
297 addr
<< GDFIFOCFG_EPINFOBASE_SHIFT
,
298 hsotg
->regs
+ GDFIFOCFG
);
300 * according to p428 of the design guide, we need to ensure that
301 * all fifos are flushed before continuing
304 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH
|
305 GRSTCTL_RXFFLSH
, hsotg
->regs
+ GRSTCTL
);
307 /* wait until the fifos are both flushed */
310 val
= dwc2_readl(hsotg
->regs
+ GRSTCTL
);
312 if ((val
& (GRSTCTL_TXFFLSH
| GRSTCTL_RXFFLSH
)) == 0)
315 if (--timeout
== 0) {
317 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
325 dev_dbg(hsotg
->dev
, "FIFOs reset, timeout at %d\n", timeout
);
329 * @ep: USB endpoint to allocate request for.
330 * @flags: Allocation flags
332 * Allocate a new USB request structure appropriate for the specified endpoint
334 static struct usb_request
*dwc2_hsotg_ep_alloc_request(struct usb_ep
*ep
,
337 struct dwc2_hsotg_req
*req
;
339 req
= kzalloc(sizeof(*req
), flags
);
343 INIT_LIST_HEAD(&req
->queue
);
349 * is_ep_periodic - return true if the endpoint is in periodic mode.
350 * @hs_ep: The endpoint to query.
352 * Returns true if the endpoint is in periodic mode, meaning it is being
353 * used for an Interrupt or ISO transfer.
355 static inline int is_ep_periodic(struct dwc2_hsotg_ep
*hs_ep
)
357 return hs_ep
->periodic
;
361 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
362 * @hsotg: The device state.
363 * @hs_ep: The endpoint for the request
364 * @hs_req: The request being processed.
366 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
367 * of a request to ensure the buffer is ready for access by the caller.
369 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg
*hsotg
,
370 struct dwc2_hsotg_ep
*hs_ep
,
371 struct dwc2_hsotg_req
*hs_req
)
373 struct usb_request
*req
= &hs_req
->req
;
375 usb_gadget_unmap_request(&hsotg
->gadget
, req
, hs_ep
->dir_in
);
379 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
380 * for Control endpoint
381 * @hsotg: The device state.
383 * This function will allocate 4 descriptor chains for EP 0: 2 for
384 * Setup stage, per one for IN and OUT data/status transactions.
386 static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg
*hsotg
)
388 hsotg
->setup_desc
[0] =
389 dmam_alloc_coherent(hsotg
->dev
,
390 sizeof(struct dwc2_dma_desc
),
391 &hsotg
->setup_desc_dma
[0],
393 if (!hsotg
->setup_desc
[0])
396 hsotg
->setup_desc
[1] =
397 dmam_alloc_coherent(hsotg
->dev
,
398 sizeof(struct dwc2_dma_desc
),
399 &hsotg
->setup_desc_dma
[1],
401 if (!hsotg
->setup_desc
[1])
404 hsotg
->ctrl_in_desc
=
405 dmam_alloc_coherent(hsotg
->dev
,
406 sizeof(struct dwc2_dma_desc
),
407 &hsotg
->ctrl_in_desc_dma
,
409 if (!hsotg
->ctrl_in_desc
)
412 hsotg
->ctrl_out_desc
=
413 dmam_alloc_coherent(hsotg
->dev
,
414 sizeof(struct dwc2_dma_desc
),
415 &hsotg
->ctrl_out_desc_dma
,
417 if (!hsotg
->ctrl_out_desc
)
427 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
428 * @hsotg: The controller state.
429 * @hs_ep: The endpoint we're going to write for.
430 * @hs_req: The request to write data for.
432 * This is called when the TxFIFO has some space in it to hold a new
433 * transmission and we have something to give it. The actual setup of
434 * the data size is done elsewhere, so all we have to do is to actually
437 * The return value is zero if there is more space (or nothing was done)
438 * otherwise -ENOSPC is returned if the FIFO space was used up.
440 * This routine is only needed for PIO
442 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg
*hsotg
,
443 struct dwc2_hsotg_ep
*hs_ep
,
444 struct dwc2_hsotg_req
*hs_req
)
446 bool periodic
= is_ep_periodic(hs_ep
);
447 u32 gnptxsts
= dwc2_readl(hsotg
->regs
+ GNPTXSTS
);
448 int buf_pos
= hs_req
->req
.actual
;
449 int to_write
= hs_ep
->size_loaded
;
455 to_write
-= (buf_pos
- hs_ep
->last_load
);
457 /* if there's nothing to write, get out early */
461 if (periodic
&& !hsotg
->dedicated_fifos
) {
462 u32 epsize
= dwc2_readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
467 * work out how much data was loaded so we can calculate
468 * how much data is left in the fifo.
471 size_left
= DXEPTSIZ_XFERSIZE_GET(epsize
);
474 * if shared fifo, we cannot write anything until the
475 * previous data has been completely sent.
477 if (hs_ep
->fifo_load
!= 0) {
478 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_PTXFEMP
);
482 dev_dbg(hsotg
->dev
, "%s: left=%d, load=%d, fifo=%d, size %d\n",
484 hs_ep
->size_loaded
, hs_ep
->fifo_load
, hs_ep
->fifo_size
);
486 /* how much of the data has moved */
487 size_done
= hs_ep
->size_loaded
- size_left
;
489 /* how much data is left in the fifo */
490 can_write
= hs_ep
->fifo_load
- size_done
;
491 dev_dbg(hsotg
->dev
, "%s: => can_write1=%d\n",
492 __func__
, can_write
);
494 can_write
= hs_ep
->fifo_size
- can_write
;
495 dev_dbg(hsotg
->dev
, "%s: => can_write2=%d\n",
496 __func__
, can_write
);
498 if (can_write
<= 0) {
499 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_PTXFEMP
);
502 } else if (hsotg
->dedicated_fifos
&& hs_ep
->index
!= 0) {
503 can_write
= dwc2_readl(hsotg
->regs
+
504 DTXFSTS(hs_ep
->fifo_index
));
509 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts
) == 0) {
511 "%s: no queue slots available (0x%08x)\n",
514 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_NPTXFEMP
);
518 can_write
= GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts
);
519 can_write
*= 4; /* fifo size is in 32bit quantities. */
522 max_transfer
= hs_ep
->ep
.maxpacket
* hs_ep
->mc
;
524 dev_dbg(hsotg
->dev
, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
525 __func__
, gnptxsts
, can_write
, to_write
, max_transfer
);
528 * limit to 512 bytes of data, it seems at least on the non-periodic
529 * FIFO, requests of >512 cause the endpoint to get stuck with a
530 * fragment of the end of the transfer in it.
532 if (can_write
> 512 && !periodic
)
536 * limit the write to one max-packet size worth of data, but allow
537 * the transfer to return that it did not run out of fifo space
540 if (to_write
> max_transfer
) {
541 to_write
= max_transfer
;
543 /* it's needed only when we do not use dedicated fifos */
544 if (!hsotg
->dedicated_fifos
)
545 dwc2_hsotg_en_gsint(hsotg
,
546 periodic
? GINTSTS_PTXFEMP
:
550 /* see if we can write data */
552 if (to_write
> can_write
) {
553 to_write
= can_write
;
554 pkt_round
= to_write
% max_transfer
;
557 * Round the write down to an
558 * exact number of packets.
560 * Note, we do not currently check to see if we can ever
561 * write a full packet or not to the FIFO.
565 to_write
-= pkt_round
;
568 * enable correct FIFO interrupt to alert us when there
572 /* it's needed only when we do not use dedicated fifos */
573 if (!hsotg
->dedicated_fifos
)
574 dwc2_hsotg_en_gsint(hsotg
,
575 periodic
? GINTSTS_PTXFEMP
:
579 dev_dbg(hsotg
->dev
, "write %d/%d, can_write %d, done %d\n",
580 to_write
, hs_req
->req
.length
, can_write
, buf_pos
);
585 hs_req
->req
.actual
= buf_pos
+ to_write
;
586 hs_ep
->total_data
+= to_write
;
589 hs_ep
->fifo_load
+= to_write
;
591 to_write
= DIV_ROUND_UP(to_write
, 4);
592 data
= hs_req
->req
.buf
+ buf_pos
;
594 iowrite32_rep(hsotg
->regs
+ EPFIFO(hs_ep
->index
), data
, to_write
);
596 return (to_write
>= can_write
) ? -ENOSPC
: 0;
600 * get_ep_limit - get the maximum data legnth for this endpoint
601 * @hs_ep: The endpoint
603 * Return the maximum data that can be queued in one go on a given endpoint
604 * so that transfers that are too long can be split.
606 static unsigned int get_ep_limit(struct dwc2_hsotg_ep
*hs_ep
)
608 int index
= hs_ep
->index
;
609 unsigned int maxsize
;
613 maxsize
= DXEPTSIZ_XFERSIZE_LIMIT
+ 1;
614 maxpkt
= DXEPTSIZ_PKTCNT_LIMIT
+ 1;
618 maxpkt
= DIEPTSIZ0_PKTCNT_LIMIT
+ 1;
623 /* we made the constant loading easier above by using +1 */
628 * constrain by packet count if maxpkts*pktsize is greater
629 * than the length register size.
632 if ((maxpkt
* hs_ep
->ep
.maxpacket
) < maxsize
)
633 maxsize
= maxpkt
* hs_ep
->ep
.maxpacket
;
639 * dwc2_hsotg_read_frameno - read current frame number
640 * @hsotg: The device instance
642 * Return the current frame number
644 static u32
dwc2_hsotg_read_frameno(struct dwc2_hsotg
*hsotg
)
648 dsts
= dwc2_readl(hsotg
->regs
+ DSTS
);
649 dsts
&= DSTS_SOFFN_MASK
;
650 dsts
>>= DSTS_SOFFN_SHIFT
;
656 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
657 * DMA descriptor chain prepared for specific endpoint
658 * @hs_ep: The endpoint
660 * Return the maximum data that can be queued in one go on a given endpoint
661 * depending on its descriptor chain capacity so that transfers that
662 * are too long can be split.
664 static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep
*hs_ep
)
666 int is_isoc
= hs_ep
->isochronous
;
667 unsigned int maxsize
;
670 maxsize
= hs_ep
->dir_in
? DEV_DMA_ISOC_TX_NBYTES_LIMIT
:
671 DEV_DMA_ISOC_RX_NBYTES_LIMIT
;
673 maxsize
= DEV_DMA_NBYTES_LIMIT
;
675 /* Above size of one descriptor was chosen, multiple it */
676 maxsize
*= MAX_DMA_DESC_NUM_GENERIC
;
682 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
683 * @hs_ep: The endpoint
684 * @mask: RX/TX bytes mask to be defined
686 * Returns maximum data payload for one descriptor after analyzing endpoint
688 * DMA descriptor transfer bytes limit depends on EP type:
690 * Isochronous - descriptor rx/tx bytes bitfield limit,
691 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
692 * have concatenations from various descriptors within one packet.
694 * Selects corresponding mask for RX/TX bytes as well.
696 static u32
dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep
*hs_ep
, u32
*mask
)
698 u32 mps
= hs_ep
->ep
.maxpacket
;
699 int dir_in
= hs_ep
->dir_in
;
702 if (!hs_ep
->index
&& !dir_in
) {
704 *mask
= DEV_DMA_NBYTES_MASK
;
705 } else if (hs_ep
->isochronous
) {
707 desc_size
= DEV_DMA_ISOC_TX_NBYTES_LIMIT
;
708 *mask
= DEV_DMA_ISOC_TX_NBYTES_MASK
;
710 desc_size
= DEV_DMA_ISOC_RX_NBYTES_LIMIT
;
711 *mask
= DEV_DMA_ISOC_RX_NBYTES_MASK
;
714 desc_size
= DEV_DMA_NBYTES_LIMIT
;
715 *mask
= DEV_DMA_NBYTES_MASK
;
717 /* Round down desc_size to be mps multiple */
718 desc_size
-= desc_size
% mps
;
725 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
726 * @hs_ep: The endpoint
727 * @dma_buff: DMA address to use
728 * @len: Length of the transfer
730 * This function will iterate over descriptor chain and fill its entries
731 * with corresponding information based on transfer data.
733 static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep
*hs_ep
,
737 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
738 int dir_in
= hs_ep
->dir_in
;
739 struct dwc2_dma_desc
*desc
= hs_ep
->desc_list
;
740 u32 mps
= hs_ep
->ep
.maxpacket
;
746 maxsize
= dwc2_gadget_get_desc_params(hs_ep
, &mask
);
748 hs_ep
->desc_count
= (len
/ maxsize
) +
749 ((len
% maxsize
) ? 1 : 0);
751 hs_ep
->desc_count
= 1;
753 for (i
= 0; i
< hs_ep
->desc_count
; ++i
) {
755 desc
->status
|= (DEV_DMA_BUFF_STS_HBUSY
756 << DEV_DMA_BUFF_STS_SHIFT
);
759 if (!hs_ep
->index
&& !dir_in
)
760 desc
->status
|= (DEV_DMA_L
| DEV_DMA_IOC
);
762 desc
->status
|= (maxsize
<<
763 DEV_DMA_NBYTES_SHIFT
& mask
);
764 desc
->buf
= dma_buff
+ offset
;
769 desc
->status
|= (DEV_DMA_L
| DEV_DMA_IOC
);
772 desc
->status
|= (len
% mps
) ? DEV_DMA_SHORT
:
773 ((hs_ep
->send_zlp
) ? DEV_DMA_SHORT
: 0);
775 dev_err(hsotg
->dev
, "wrong len %d\n", len
);
778 len
<< DEV_DMA_NBYTES_SHIFT
& mask
;
779 desc
->buf
= dma_buff
+ offset
;
782 desc
->status
&= ~DEV_DMA_BUFF_STS_MASK
;
783 desc
->status
|= (DEV_DMA_BUFF_STS_HREADY
784 << DEV_DMA_BUFF_STS_SHIFT
);
790 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
791 * @hs_ep: The isochronous endpoint.
792 * @dma_buff: usb requests dma buffer.
793 * @len: usb request transfer length.
795 * Finds out index of first free entry either in the bottom or up half of
796 * descriptor chain depend on which is under SW control and not processed
797 * by HW. Then fills that descriptor with the data of the arrived usb request,
798 * frame info, sets Last and IOC bits increments next_desc. If filled
799 * descriptor is not the first one, removes L bit from the previous descriptor
802 static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep
*hs_ep
,
803 dma_addr_t dma_buff
, unsigned int len
)
805 struct dwc2_dma_desc
*desc
;
806 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
811 maxsize
= dwc2_gadget_get_desc_params(hs_ep
, &mask
);
813 dev_err(hsotg
->dev
, "wrong len %d\n", len
);
818 * If SW has already filled half of chain, then return and wait for
819 * the other chain to be processed by HW.
821 if (hs_ep
->next_desc
== MAX_DMA_DESC_NUM_GENERIC
/ 2)
824 /* Increment frame number by interval for IN */
826 dwc2_gadget_incr_frame_num(hs_ep
);
828 index
= (MAX_DMA_DESC_NUM_GENERIC
/ 2) * hs_ep
->isoc_chain_num
+
831 /* Sanity check of calculated index */
832 if ((hs_ep
->isoc_chain_num
&& index
> MAX_DMA_DESC_NUM_GENERIC
) ||
833 (!hs_ep
->isoc_chain_num
&& index
> MAX_DMA_DESC_NUM_GENERIC
/ 2)) {
834 dev_err(hsotg
->dev
, "wrong index %d for iso chain\n", index
);
838 desc
= &hs_ep
->desc_list
[index
];
840 /* Clear L bit of previous desc if more than one entries in the chain */
841 if (hs_ep
->next_desc
)
842 hs_ep
->desc_list
[index
- 1].status
&= ~DEV_DMA_L
;
844 dev_dbg(hsotg
->dev
, "%s: Filling ep %d, dir %s isoc desc # %d\n",
845 __func__
, hs_ep
->index
, hs_ep
->dir_in
? "in" : "out", index
);
848 desc
->status
|= (DEV_DMA_BUFF_STS_HBUSY
<< DEV_DMA_BUFF_STS_SHIFT
);
850 desc
->buf
= dma_buff
;
851 desc
->status
|= (DEV_DMA_L
| DEV_DMA_IOC
|
852 ((len
<< DEV_DMA_NBYTES_SHIFT
) & mask
));
855 desc
->status
|= ((hs_ep
->mc
<< DEV_DMA_ISOC_PID_SHIFT
) &
856 DEV_DMA_ISOC_PID_MASK
) |
857 ((len
% hs_ep
->ep
.maxpacket
) ?
859 ((hs_ep
->target_frame
<<
860 DEV_DMA_ISOC_FRNUM_SHIFT
) &
861 DEV_DMA_ISOC_FRNUM_MASK
);
864 desc
->status
&= ~DEV_DMA_BUFF_STS_MASK
;
865 desc
->status
|= (DEV_DMA_BUFF_STS_HREADY
<< DEV_DMA_BUFF_STS_SHIFT
);
867 /* Update index of last configured entry in the chain */
874 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
875 * @hs_ep: The isochronous endpoint.
877 * Prepare first descriptor chain for isochronous endpoints. Afterwards
878 * write DMA address to HW and enable the endpoint.
880 * Switch between descriptor chains via isoc_chain_num to give SW opportunity
881 * to prepare second descriptor chain while first one is being processed by HW.
883 static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep
*hs_ep
)
885 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
886 struct dwc2_hsotg_req
*hs_req
, *treq
;
887 int index
= hs_ep
->index
;
893 if (list_empty(&hs_ep
->queue
)) {
894 dev_dbg(hsotg
->dev
, "%s: No requests in queue\n", __func__
);
898 list_for_each_entry_safe(hs_req
, treq
, &hs_ep
->queue
, queue
) {
899 ret
= dwc2_gadget_fill_isoc_desc(hs_ep
, hs_req
->req
.dma
,
902 dev_dbg(hsotg
->dev
, "%s: desc chain full\n", __func__
);
907 depctl
= hs_ep
->dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
908 dma_reg
= hs_ep
->dir_in
? DIEPDMA(index
) : DOEPDMA(index
);
910 /* write descriptor chain address to control register */
911 dwc2_writel(hs_ep
->desc_list_dma
, hsotg
->regs
+ dma_reg
);
913 ctrl
= dwc2_readl(hsotg
->regs
+ depctl
);
914 ctrl
|= DXEPCTL_EPENA
| DXEPCTL_CNAK
;
915 dwc2_writel(ctrl
, hsotg
->regs
+ depctl
);
917 /* Switch ISOC descriptor chain number being processed by SW*/
918 hs_ep
->isoc_chain_num
= (hs_ep
->isoc_chain_num
^ 1) & 0x1;
919 hs_ep
->next_desc
= 0;
923 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
924 * @hsotg: The controller state.
925 * @hs_ep: The endpoint to process a request for
926 * @hs_req: The request to start.
927 * @continuing: True if we are doing more for the current request.
929 * Start the given request running by setting the endpoint registers
930 * appropriately, and writing any data to the FIFOs.
932 static void dwc2_hsotg_start_req(struct dwc2_hsotg
*hsotg
,
933 struct dwc2_hsotg_ep
*hs_ep
,
934 struct dwc2_hsotg_req
*hs_req
,
937 struct usb_request
*ureq
= &hs_req
->req
;
938 int index
= hs_ep
->index
;
939 int dir_in
= hs_ep
->dir_in
;
945 unsigned int packets
;
947 unsigned int dma_reg
;
950 if (hs_ep
->req
&& !continuing
) {
951 dev_err(hsotg
->dev
, "%s: active request\n", __func__
);
954 } else if (hs_ep
->req
!= hs_req
&& continuing
) {
956 "%s: continue different req\n", __func__
);
962 dma_reg
= dir_in
? DIEPDMA(index
) : DOEPDMA(index
);
963 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
964 epsize_reg
= dir_in
? DIEPTSIZ(index
) : DOEPTSIZ(index
);
966 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
967 __func__
, dwc2_readl(hsotg
->regs
+ epctrl_reg
), index
,
968 hs_ep
->dir_in
? "in" : "out");
970 /* If endpoint is stalled, we will restart request later */
971 ctrl
= dwc2_readl(hsotg
->regs
+ epctrl_reg
);
973 if (index
&& ctrl
& DXEPCTL_STALL
) {
974 dev_warn(hsotg
->dev
, "%s: ep%d is stalled\n", __func__
, index
);
978 length
= ureq
->length
- ureq
->actual
;
979 dev_dbg(hsotg
->dev
, "ureq->length:%d ureq->actual:%d\n",
980 ureq
->length
, ureq
->actual
);
982 if (!using_desc_dma(hsotg
))
983 maxreq
= get_ep_limit(hs_ep
);
985 maxreq
= dwc2_gadget_get_chain_limit(hs_ep
);
987 if (length
> maxreq
) {
988 int round
= maxreq
% hs_ep
->ep
.maxpacket
;
990 dev_dbg(hsotg
->dev
, "%s: length %d, max-req %d, r %d\n",
991 __func__
, length
, maxreq
, round
);
993 /* round down to multiple of packets */
1001 packets
= DIV_ROUND_UP(length
, hs_ep
->ep
.maxpacket
);
1003 packets
= 1; /* send one packet if length is zero. */
1005 if (hs_ep
->isochronous
&& length
> (hs_ep
->mc
* hs_ep
->ep
.maxpacket
)) {
1006 dev_err(hsotg
->dev
, "req length > maxpacket*mc\n");
1010 if (dir_in
&& index
!= 0)
1011 if (hs_ep
->isochronous
)
1012 epsize
= DXEPTSIZ_MC(packets
);
1014 epsize
= DXEPTSIZ_MC(1);
1019 * zero length packet should be programmed on its own and should not
1020 * be counted in DIEPTSIZ.PktCnt with other packets.
1022 if (dir_in
&& ureq
->zero
&& !continuing
) {
1023 /* Test if zlp is actually required. */
1024 if ((ureq
->length
>= hs_ep
->ep
.maxpacket
) &&
1025 !(ureq
->length
% hs_ep
->ep
.maxpacket
))
1026 hs_ep
->send_zlp
= 1;
1029 epsize
|= DXEPTSIZ_PKTCNT(packets
);
1030 epsize
|= DXEPTSIZ_XFERSIZE(length
);
1032 dev_dbg(hsotg
->dev
, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1033 __func__
, packets
, length
, ureq
->length
, epsize
, epsize_reg
);
1035 /* store the request as the current one we're doing */
1036 hs_ep
->req
= hs_req
;
1038 if (using_desc_dma(hsotg
)) {
1040 u32 mps
= hs_ep
->ep
.maxpacket
;
1042 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1046 else if (length
% mps
)
1047 length
+= (mps
- (length
% mps
));
1051 * If more data to send, adjust DMA for EP0 out data stage.
1052 * ureq->dma stays unchanged, hence increment it by already
1053 * passed passed data count before starting new transaction.
1055 if (!index
&& hsotg
->ep0_state
== DWC2_EP0_DATA_OUT
&&
1057 offset
= ureq
->actual
;
1059 /* Fill DDMA chain entries */
1060 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep
, ureq
->dma
+ offset
,
1063 /* write descriptor chain address to control register */
1064 dwc2_writel(hs_ep
->desc_list_dma
, hsotg
->regs
+ dma_reg
);
1066 dev_dbg(hsotg
->dev
, "%s: %08x pad => 0x%08x\n",
1067 __func__
, (u32
)hs_ep
->desc_list_dma
, dma_reg
);
1069 /* write size / packets */
1070 dwc2_writel(epsize
, hsotg
->regs
+ epsize_reg
);
1072 if (using_dma(hsotg
) && !continuing
&& (length
!= 0)) {
1074 * write DMA address to control register, buffer
1075 * already synced by dwc2_hsotg_ep_queue().
1078 dwc2_writel(ureq
->dma
, hsotg
->regs
+ dma_reg
);
1080 dev_dbg(hsotg
->dev
, "%s: %pad => 0x%08x\n",
1081 __func__
, &ureq
->dma
, dma_reg
);
1085 if (hs_ep
->isochronous
&& hs_ep
->interval
== 1) {
1086 hs_ep
->target_frame
= dwc2_hsotg_read_frameno(hsotg
);
1087 dwc2_gadget_incr_frame_num(hs_ep
);
1089 if (hs_ep
->target_frame
& 0x1)
1090 ctrl
|= DXEPCTL_SETODDFR
;
1092 ctrl
|= DXEPCTL_SETEVENFR
;
1095 ctrl
|= DXEPCTL_EPENA
; /* ensure ep enabled */
1097 dev_dbg(hsotg
->dev
, "ep0 state:%d\n", hsotg
->ep0_state
);
1099 /* For Setup request do not clear NAK */
1100 if (!(index
== 0 && hsotg
->ep0_state
== DWC2_EP0_SETUP
))
1101 ctrl
|= DXEPCTL_CNAK
; /* clear NAK set by core */
1103 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
1104 dwc2_writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
1107 * set these, it seems that DMA support increments past the end
1108 * of the packet buffer so we need to calculate the length from
1111 hs_ep
->size_loaded
= length
;
1112 hs_ep
->last_load
= ureq
->actual
;
1114 if (dir_in
&& !using_dma(hsotg
)) {
1115 /* set these anyway, we may need them for non-periodic in */
1116 hs_ep
->fifo_load
= 0;
1118 dwc2_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
1122 * Note, trying to clear the NAK here causes problems with transmit
1123 * on the S3C6400 ending up with the TXFIFO becoming full.
1126 /* check ep is enabled */
1127 if (!(dwc2_readl(hsotg
->regs
+ epctrl_reg
) & DXEPCTL_EPENA
))
1129 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1130 index
, dwc2_readl(hsotg
->regs
+ epctrl_reg
));
1132 dev_dbg(hsotg
->dev
, "%s: DXEPCTL=0x%08x\n",
1133 __func__
, dwc2_readl(hsotg
->regs
+ epctrl_reg
));
1135 /* enable ep interrupts */
1136 dwc2_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 1);
1140 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1141 * @hsotg: The device state.
1142 * @hs_ep: The endpoint the request is on.
1143 * @req: The request being processed.
1145 * We've been asked to queue a request, so ensure that the memory buffer
1146 * is correctly setup for DMA. If we've been passed an extant DMA address
1147 * then ensure the buffer has been synced to memory. If our buffer has no
1148 * DMA memory, then we map the memory and mark our request to allow us to
1149 * cleanup on completion.
1151 static int dwc2_hsotg_map_dma(struct dwc2_hsotg
*hsotg
,
1152 struct dwc2_hsotg_ep
*hs_ep
,
1153 struct usb_request
*req
)
1157 ret
= usb_gadget_map_request(&hsotg
->gadget
, req
, hs_ep
->dir_in
);
1164 dev_err(hsotg
->dev
, "%s: failed to map buffer %p, %d bytes\n",
1165 __func__
, req
->buf
, req
->length
);
1170 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg
*hsotg
,
1171 struct dwc2_hsotg_ep
*hs_ep
,
1172 struct dwc2_hsotg_req
*hs_req
)
1174 void *req_buf
= hs_req
->req
.buf
;
1176 /* If dma is not being used or buffer is aligned */
1177 if (!using_dma(hsotg
) || !((long)req_buf
& 3))
1180 WARN_ON(hs_req
->saved_req_buf
);
1182 dev_dbg(hsotg
->dev
, "%s: %s: buf=%p length=%d\n", __func__
,
1183 hs_ep
->ep
.name
, req_buf
, hs_req
->req
.length
);
1185 hs_req
->req
.buf
= kmalloc(hs_req
->req
.length
, GFP_ATOMIC
);
1186 if (!hs_req
->req
.buf
) {
1187 hs_req
->req
.buf
= req_buf
;
1189 "%s: unable to allocate memory for bounce buffer\n",
1194 /* Save actual buffer */
1195 hs_req
->saved_req_buf
= req_buf
;
1198 memcpy(hs_req
->req
.buf
, req_buf
, hs_req
->req
.length
);
1203 dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg
*hsotg
,
1204 struct dwc2_hsotg_ep
*hs_ep
,
1205 struct dwc2_hsotg_req
*hs_req
)
1207 /* If dma is not being used or buffer was aligned */
1208 if (!using_dma(hsotg
) || !hs_req
->saved_req_buf
)
1211 dev_dbg(hsotg
->dev
, "%s: %s: status=%d actual-length=%d\n", __func__
,
1212 hs_ep
->ep
.name
, hs_req
->req
.status
, hs_req
->req
.actual
);
1214 /* Copy data from bounce buffer on successful out transfer */
1215 if (!hs_ep
->dir_in
&& !hs_req
->req
.status
)
1216 memcpy(hs_req
->saved_req_buf
, hs_req
->req
.buf
,
1217 hs_req
->req
.actual
);
1219 /* Free bounce buffer */
1220 kfree(hs_req
->req
.buf
);
1222 hs_req
->req
.buf
= hs_req
->saved_req_buf
;
1223 hs_req
->saved_req_buf
= NULL
;
1227 * dwc2_gadget_target_frame_elapsed - Checks target frame
1228 * @hs_ep: The driver endpoint to check
1230 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1231 * corresponding transfer.
1233 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep
*hs_ep
)
1235 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
1236 u32 target_frame
= hs_ep
->target_frame
;
1237 u32 current_frame
= dwc2_hsotg_read_frameno(hsotg
);
1238 bool frame_overrun
= hs_ep
->frame_overrun
;
1240 if (!frame_overrun
&& current_frame
>= target_frame
)
1243 if (frame_overrun
&& current_frame
>= target_frame
&&
1244 ((current_frame
- target_frame
) < DSTS_SOFFN_LIMIT
/ 2))
1251 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1252 * @hsotg: The driver state
1253 * @hs_ep: the ep descriptor chain is for
1255 * Called to update EP0 structure's pointers depend on stage of
1258 static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg
*hsotg
,
1259 struct dwc2_hsotg_ep
*hs_ep
)
1261 switch (hsotg
->ep0_state
) {
1262 case DWC2_EP0_SETUP
:
1263 case DWC2_EP0_STATUS_OUT
:
1264 hs_ep
->desc_list
= hsotg
->setup_desc
[0];
1265 hs_ep
->desc_list_dma
= hsotg
->setup_desc_dma
[0];
1267 case DWC2_EP0_DATA_IN
:
1268 case DWC2_EP0_STATUS_IN
:
1269 hs_ep
->desc_list
= hsotg
->ctrl_in_desc
;
1270 hs_ep
->desc_list_dma
= hsotg
->ctrl_in_desc_dma
;
1272 case DWC2_EP0_DATA_OUT
:
1273 hs_ep
->desc_list
= hsotg
->ctrl_out_desc
;
1274 hs_ep
->desc_list_dma
= hsotg
->ctrl_out_desc_dma
;
1277 dev_err(hsotg
->dev
, "invalid EP 0 state in queue %d\n",
1285 static int dwc2_hsotg_ep_queue(struct usb_ep
*ep
, struct usb_request
*req
,
1288 struct dwc2_hsotg_req
*hs_req
= our_req(req
);
1289 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
1290 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
1294 dev_dbg(hs
->dev
, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1295 ep
->name
, req
, req
->length
, req
->buf
, req
->no_interrupt
,
1296 req
->zero
, req
->short_not_ok
);
1298 /* Prevent new request submission when controller is suspended */
1299 if (hs
->lx_state
== DWC2_L2
) {
1300 dev_dbg(hs
->dev
, "%s: don't submit request while suspended\n",
1305 /* initialise status of the request */
1306 INIT_LIST_HEAD(&hs_req
->queue
);
1308 req
->status
= -EINPROGRESS
;
1310 ret
= dwc2_hsotg_handle_unaligned_buf_start(hs
, hs_ep
, hs_req
);
1314 /* if we're using DMA, sync the buffers as necessary */
1315 if (using_dma(hs
)) {
1316 ret
= dwc2_hsotg_map_dma(hs
, hs_ep
, req
);
1320 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1321 if (using_desc_dma(hs
) && !hs_ep
->index
) {
1322 ret
= dwc2_gadget_set_ep0_desc_chain(hs
, hs_ep
);
1327 first
= list_empty(&hs_ep
->queue
);
1328 list_add_tail(&hs_req
->queue
, &hs_ep
->queue
);
1331 * Handle DDMA isochronous transfers separately - just add new entry
1332 * to the half of descriptor chain that is not processed by HW.
1333 * Transfer will be started once SW gets either one of NAK or
1334 * OutTknEpDis interrupts.
1336 if (using_desc_dma(hs
) && hs_ep
->isochronous
&&
1337 hs_ep
->target_frame
!= TARGET_FRAME_INITIAL
) {
1338 ret
= dwc2_gadget_fill_isoc_desc(hs_ep
, hs_req
->req
.dma
,
1339 hs_req
->req
.length
);
1341 dev_dbg(hs
->dev
, "%s: ISO desc chain full\n", __func__
);
1347 if (!hs_ep
->isochronous
) {
1348 dwc2_hsotg_start_req(hs
, hs_ep
, hs_req
, false);
1352 while (dwc2_gadget_target_frame_elapsed(hs_ep
))
1353 dwc2_gadget_incr_frame_num(hs_ep
);
1355 if (hs_ep
->target_frame
!= TARGET_FRAME_INITIAL
)
1356 dwc2_hsotg_start_req(hs
, hs_ep
, hs_req
, false);
1361 static int dwc2_hsotg_ep_queue_lock(struct usb_ep
*ep
, struct usb_request
*req
,
1364 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
1365 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
1366 unsigned long flags
= 0;
1369 spin_lock_irqsave(&hs
->lock
, flags
);
1370 ret
= dwc2_hsotg_ep_queue(ep
, req
, gfp_flags
);
1371 spin_unlock_irqrestore(&hs
->lock
, flags
);
1376 static void dwc2_hsotg_ep_free_request(struct usb_ep
*ep
,
1377 struct usb_request
*req
)
1379 struct dwc2_hsotg_req
*hs_req
= our_req(req
);
1385 * dwc2_hsotg_complete_oursetup - setup completion callback
1386 * @ep: The endpoint the request was on.
1387 * @req: The request completed.
1389 * Called on completion of any requests the driver itself
1390 * submitted that need cleaning up.
1392 static void dwc2_hsotg_complete_oursetup(struct usb_ep
*ep
,
1393 struct usb_request
*req
)
1395 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
1396 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
1398 dev_dbg(hsotg
->dev
, "%s: ep %p, req %p\n", __func__
, ep
, req
);
1400 dwc2_hsotg_ep_free_request(ep
, req
);
1404 * ep_from_windex - convert control wIndex value to endpoint
1405 * @hsotg: The driver state.
1406 * @windex: The control request wIndex field (in host order).
1408 * Convert the given wIndex into a pointer to an driver endpoint
1409 * structure, or return NULL if it is not a valid endpoint.
1411 static struct dwc2_hsotg_ep
*ep_from_windex(struct dwc2_hsotg
*hsotg
,
1414 struct dwc2_hsotg_ep
*ep
;
1415 int dir
= (windex
& USB_DIR_IN
) ? 1 : 0;
1416 int idx
= windex
& 0x7F;
1418 if (windex
>= 0x100)
1421 if (idx
> hsotg
->num_of_eps
)
1424 ep
= index_to_ep(hsotg
, idx
, dir
);
1426 if (idx
&& ep
->dir_in
!= dir
)
1433 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1434 * @hsotg: The driver state.
1435 * @testmode: requested usb test mode
1436 * Enable usb Test Mode requested by the Host.
1438 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg
*hsotg
, int testmode
)
1440 int dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
1442 dctl
&= ~DCTL_TSTCTL_MASK
;
1449 dctl
|= testmode
<< DCTL_TSTCTL_SHIFT
;
1454 dwc2_writel(dctl
, hsotg
->regs
+ DCTL
);
1459 * dwc2_hsotg_send_reply - send reply to control request
1460 * @hsotg: The device state
1462 * @buff: Buffer for request
1463 * @length: Length of reply.
1465 * Create a request and queue it on the given endpoint. This is useful as
1466 * an internal method of sending replies to certain control requests, etc.
1468 static int dwc2_hsotg_send_reply(struct dwc2_hsotg
*hsotg
,
1469 struct dwc2_hsotg_ep
*ep
,
1473 struct usb_request
*req
;
1476 dev_dbg(hsotg
->dev
, "%s: buff %p, len %d\n", __func__
, buff
, length
);
1478 req
= dwc2_hsotg_ep_alloc_request(&ep
->ep
, GFP_ATOMIC
);
1479 hsotg
->ep0_reply
= req
;
1481 dev_warn(hsotg
->dev
, "%s: cannot alloc req\n", __func__
);
1485 req
->buf
= hsotg
->ep0_buff
;
1486 req
->length
= length
;
1488 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1492 req
->complete
= dwc2_hsotg_complete_oursetup
;
1495 memcpy(req
->buf
, buff
, length
);
1497 ret
= dwc2_hsotg_ep_queue(&ep
->ep
, req
, GFP_ATOMIC
);
1499 dev_warn(hsotg
->dev
, "%s: cannot queue req\n", __func__
);
1507 * dwc2_hsotg_process_req_status - process request GET_STATUS
1508 * @hsotg: The device state
1509 * @ctrl: USB control request
1511 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg
*hsotg
,
1512 struct usb_ctrlrequest
*ctrl
)
1514 struct dwc2_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
1515 struct dwc2_hsotg_ep
*ep
;
1519 dev_dbg(hsotg
->dev
, "%s: USB_REQ_GET_STATUS\n", __func__
);
1522 dev_warn(hsotg
->dev
, "%s: direction out?\n", __func__
);
1526 switch (ctrl
->bRequestType
& USB_RECIP_MASK
) {
1527 case USB_RECIP_DEVICE
:
1529 * bit 0 => self powered
1530 * bit 1 => remote wakeup
1532 reply
= cpu_to_le16(0);
1535 case USB_RECIP_INTERFACE
:
1536 /* currently, the data result should be zero */
1537 reply
= cpu_to_le16(0);
1540 case USB_RECIP_ENDPOINT
:
1541 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
1545 reply
= cpu_to_le16(ep
->halted
? 1 : 0);
1552 if (le16_to_cpu(ctrl
->wLength
) != 2)
1555 ret
= dwc2_hsotg_send_reply(hsotg
, ep0
, &reply
, 2);
1557 dev_err(hsotg
->dev
, "%s: failed to send reply\n", __func__
);
1564 static int dwc2_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
, bool now
);
1567 * get_ep_head - return the first request on the endpoint
1568 * @hs_ep: The controller endpoint to get
1570 * Get the first request on the endpoint.
1572 static struct dwc2_hsotg_req
*get_ep_head(struct dwc2_hsotg_ep
*hs_ep
)
1574 return list_first_entry_or_null(&hs_ep
->queue
, struct dwc2_hsotg_req
,
1579 * dwc2_gadget_start_next_request - Starts next request from ep queue
1580 * @hs_ep: Endpoint structure
1582 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1583 * in its handler. Hence we need to unmask it here to be able to do
1584 * resynchronization.
1586 static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep
*hs_ep
)
1589 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
1590 int dir_in
= hs_ep
->dir_in
;
1591 struct dwc2_hsotg_req
*hs_req
;
1592 u32 epmsk_reg
= dir_in
? DIEPMSK
: DOEPMSK
;
1594 if (!list_empty(&hs_ep
->queue
)) {
1595 hs_req
= get_ep_head(hs_ep
);
1596 dwc2_hsotg_start_req(hsotg
, hs_ep
, hs_req
, false);
1599 if (!hs_ep
->isochronous
)
1603 dev_dbg(hsotg
->dev
, "%s: No more ISOC-IN requests\n",
1606 dev_dbg(hsotg
->dev
, "%s: No more ISOC-OUT requests\n",
1608 mask
= dwc2_readl(hsotg
->regs
+ epmsk_reg
);
1609 mask
|= DOEPMSK_OUTTKNEPDISMSK
;
1610 dwc2_writel(mask
, hsotg
->regs
+ epmsk_reg
);
1615 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1616 * @hsotg: The device state
1617 * @ctrl: USB control request
1619 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg
*hsotg
,
1620 struct usb_ctrlrequest
*ctrl
)
1622 struct dwc2_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
1623 struct dwc2_hsotg_req
*hs_req
;
1624 bool set
= (ctrl
->bRequest
== USB_REQ_SET_FEATURE
);
1625 struct dwc2_hsotg_ep
*ep
;
1632 dev_dbg(hsotg
->dev
, "%s: %s_FEATURE\n",
1633 __func__
, set
? "SET" : "CLEAR");
1635 wValue
= le16_to_cpu(ctrl
->wValue
);
1636 wIndex
= le16_to_cpu(ctrl
->wIndex
);
1637 recip
= ctrl
->bRequestType
& USB_RECIP_MASK
;
1640 case USB_RECIP_DEVICE
:
1642 case USB_DEVICE_TEST_MODE
:
1643 if ((wIndex
& 0xff) != 0)
1648 hsotg
->test_mode
= wIndex
>> 8;
1649 ret
= dwc2_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1652 "%s: failed to send reply\n", __func__
);
1661 case USB_RECIP_ENDPOINT
:
1662 ep
= ep_from_windex(hsotg
, wIndex
);
1664 dev_dbg(hsotg
->dev
, "%s: no endpoint for 0x%04x\n",
1670 case USB_ENDPOINT_HALT
:
1671 halted
= ep
->halted
;
1673 dwc2_hsotg_ep_sethalt(&ep
->ep
, set
, true);
1675 ret
= dwc2_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1678 "%s: failed to send reply\n", __func__
);
1683 * we have to complete all requests for ep if it was
1684 * halted, and the halt was cleared by CLEAR_FEATURE
1687 if (!set
&& halted
) {
1689 * If we have request in progress,
1695 list_del_init(&hs_req
->queue
);
1696 if (hs_req
->req
.complete
) {
1697 spin_unlock(&hsotg
->lock
);
1698 usb_gadget_giveback_request(
1699 &ep
->ep
, &hs_req
->req
);
1700 spin_lock(&hsotg
->lock
);
1704 /* If we have pending request, then start it */
1706 dwc2_gadget_start_next_request(ep
);
1721 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg
*hsotg
);
1724 * dwc2_hsotg_stall_ep0 - stall ep0
1725 * @hsotg: The device state
1727 * Set stall for ep0 as response for setup request.
1729 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg
*hsotg
)
1731 struct dwc2_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
1735 dev_dbg(hsotg
->dev
, "ep0 stall (dir=%d)\n", ep0
->dir_in
);
1736 reg
= (ep0
->dir_in
) ? DIEPCTL0
: DOEPCTL0
;
1739 * DxEPCTL_Stall will be cleared by EP once it has
1740 * taken effect, so no need to clear later.
1743 ctrl
= dwc2_readl(hsotg
->regs
+ reg
);
1744 ctrl
|= DXEPCTL_STALL
;
1745 ctrl
|= DXEPCTL_CNAK
;
1746 dwc2_writel(ctrl
, hsotg
->regs
+ reg
);
1749 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1750 ctrl
, reg
, dwc2_readl(hsotg
->regs
+ reg
));
1753 * complete won't be called, so we enqueue
1754 * setup request here
1756 dwc2_hsotg_enqueue_setup(hsotg
);
1760 * dwc2_hsotg_process_control - process a control request
1761 * @hsotg: The device state
1762 * @ctrl: The control request received
1764 * The controller has received the SETUP phase of a control request, and
1765 * needs to work out what to do next (and whether to pass it on to the
1768 static void dwc2_hsotg_process_control(struct dwc2_hsotg
*hsotg
,
1769 struct usb_ctrlrequest
*ctrl
)
1771 struct dwc2_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
1776 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1777 ctrl
->bRequestType
, ctrl
->bRequest
, ctrl
->wValue
,
1778 ctrl
->wIndex
, ctrl
->wLength
);
1780 if (ctrl
->wLength
== 0) {
1782 hsotg
->ep0_state
= DWC2_EP0_STATUS_IN
;
1783 } else if (ctrl
->bRequestType
& USB_DIR_IN
) {
1785 hsotg
->ep0_state
= DWC2_EP0_DATA_IN
;
1788 hsotg
->ep0_state
= DWC2_EP0_DATA_OUT
;
1791 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
) {
1792 switch (ctrl
->bRequest
) {
1793 case USB_REQ_SET_ADDRESS
:
1794 hsotg
->connected
= 1;
1795 dcfg
= dwc2_readl(hsotg
->regs
+ DCFG
);
1796 dcfg
&= ~DCFG_DEVADDR_MASK
;
1797 dcfg
|= (le16_to_cpu(ctrl
->wValue
) <<
1798 DCFG_DEVADDR_SHIFT
) & DCFG_DEVADDR_MASK
;
1799 dwc2_writel(dcfg
, hsotg
->regs
+ DCFG
);
1801 dev_info(hsotg
->dev
, "new address %d\n", ctrl
->wValue
);
1803 ret
= dwc2_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1806 case USB_REQ_GET_STATUS
:
1807 ret
= dwc2_hsotg_process_req_status(hsotg
, ctrl
);
1810 case USB_REQ_CLEAR_FEATURE
:
1811 case USB_REQ_SET_FEATURE
:
1812 ret
= dwc2_hsotg_process_req_feature(hsotg
, ctrl
);
1817 /* as a fallback, try delivering it to the driver to deal with */
1819 if (ret
== 0 && hsotg
->driver
) {
1820 spin_unlock(&hsotg
->lock
);
1821 ret
= hsotg
->driver
->setup(&hsotg
->gadget
, ctrl
);
1822 spin_lock(&hsotg
->lock
);
1824 dev_dbg(hsotg
->dev
, "driver->setup() ret %d\n", ret
);
1828 * the request is either unhandlable, or is not formatted correctly
1829 * so respond with a STALL for the status stage to indicate failure.
1833 dwc2_hsotg_stall_ep0(hsotg
);
1837 * dwc2_hsotg_complete_setup - completion of a setup transfer
1838 * @ep: The endpoint the request was on.
1839 * @req: The request completed.
1841 * Called on completion of any requests the driver itself submitted for
1844 static void dwc2_hsotg_complete_setup(struct usb_ep
*ep
,
1845 struct usb_request
*req
)
1847 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
1848 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
1850 if (req
->status
< 0) {
1851 dev_dbg(hsotg
->dev
, "%s: failed %d\n", __func__
, req
->status
);
1855 spin_lock(&hsotg
->lock
);
1856 if (req
->actual
== 0)
1857 dwc2_hsotg_enqueue_setup(hsotg
);
1859 dwc2_hsotg_process_control(hsotg
, req
->buf
);
1860 spin_unlock(&hsotg
->lock
);
1864 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1865 * @hsotg: The device state.
1867 * Enqueue a request on EP0 if necessary to received any SETUP packets
1868 * received from the host.
1870 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg
*hsotg
)
1872 struct usb_request
*req
= hsotg
->ctrl_req
;
1873 struct dwc2_hsotg_req
*hs_req
= our_req(req
);
1876 dev_dbg(hsotg
->dev
, "%s: queueing setup request\n", __func__
);
1880 req
->buf
= hsotg
->ctrl_buff
;
1881 req
->complete
= dwc2_hsotg_complete_setup
;
1883 if (!list_empty(&hs_req
->queue
)) {
1884 dev_dbg(hsotg
->dev
, "%s already queued???\n", __func__
);
1888 hsotg
->eps_out
[0]->dir_in
= 0;
1889 hsotg
->eps_out
[0]->send_zlp
= 0;
1890 hsotg
->ep0_state
= DWC2_EP0_SETUP
;
1892 ret
= dwc2_hsotg_ep_queue(&hsotg
->eps_out
[0]->ep
, req
, GFP_ATOMIC
);
1894 dev_err(hsotg
->dev
, "%s: failed queue (%d)\n", __func__
, ret
);
1896 * Don't think there's much we can do other than watch the
1902 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg
*hsotg
,
1903 struct dwc2_hsotg_ep
*hs_ep
)
1906 u8 index
= hs_ep
->index
;
1907 u32 epctl_reg
= hs_ep
->dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
1908 u32 epsiz_reg
= hs_ep
->dir_in
? DIEPTSIZ(index
) : DOEPTSIZ(index
);
1911 dev_dbg(hsotg
->dev
, "Sending zero-length packet on ep%d\n",
1914 dev_dbg(hsotg
->dev
, "Receiving zero-length packet on ep%d\n",
1916 if (using_desc_dma(hsotg
)) {
1917 /* Not specific buffer needed for ep0 ZLP */
1918 dma_addr_t dma
= hs_ep
->desc_list_dma
;
1920 dwc2_gadget_set_ep0_desc_chain(hsotg
, hs_ep
);
1921 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep
, dma
, 0);
1923 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1924 DXEPTSIZ_XFERSIZE(0), hsotg
->regs
+
1928 ctrl
= dwc2_readl(hsotg
->regs
+ epctl_reg
);
1929 ctrl
|= DXEPCTL_CNAK
; /* clear NAK set by core */
1930 ctrl
|= DXEPCTL_EPENA
; /* ensure ep enabled */
1931 ctrl
|= DXEPCTL_USBACTEP
;
1932 dwc2_writel(ctrl
, hsotg
->regs
+ epctl_reg
);
1936 * dwc2_hsotg_complete_request - complete a request given to us
1937 * @hsotg: The device state.
1938 * @hs_ep: The endpoint the request was on.
1939 * @hs_req: The request to complete.
1940 * @result: The result code (0 => Ok, otherwise errno)
1942 * The given request has finished, so call the necessary completion
1943 * if it has one and then look to see if we can start a new request
1946 * Note, expects the ep to already be locked as appropriate.
1948 static void dwc2_hsotg_complete_request(struct dwc2_hsotg
*hsotg
,
1949 struct dwc2_hsotg_ep
*hs_ep
,
1950 struct dwc2_hsotg_req
*hs_req
,
1954 dev_dbg(hsotg
->dev
, "%s: nothing to complete?\n", __func__
);
1958 dev_dbg(hsotg
->dev
, "complete: ep %p %s, req %p, %d => %p\n",
1959 hs_ep
, hs_ep
->ep
.name
, hs_req
, result
, hs_req
->req
.complete
);
1962 * only replace the status if we've not already set an error
1963 * from a previous transaction
1966 if (hs_req
->req
.status
== -EINPROGRESS
)
1967 hs_req
->req
.status
= result
;
1969 if (using_dma(hsotg
))
1970 dwc2_hsotg_unmap_dma(hsotg
, hs_ep
, hs_req
);
1972 dwc2_hsotg_handle_unaligned_buf_complete(hsotg
, hs_ep
, hs_req
);
1975 list_del_init(&hs_req
->queue
);
1978 * call the complete request with the locks off, just in case the
1979 * request tries to queue more work for this endpoint.
1982 if (hs_req
->req
.complete
) {
1983 spin_unlock(&hsotg
->lock
);
1984 usb_gadget_giveback_request(&hs_ep
->ep
, &hs_req
->req
);
1985 spin_lock(&hsotg
->lock
);
1988 /* In DDMA don't need to proceed to starting of next ISOC request */
1989 if (using_desc_dma(hsotg
) && hs_ep
->isochronous
)
1993 * Look to see if there is anything else to do. Note, the completion
1994 * of the previous request may have caused a new request to be started
1995 * so be careful when doing this.
1998 if (!hs_ep
->req
&& result
>= 0)
1999 dwc2_gadget_start_next_request(hs_ep
);
2003 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2004 * @hs_ep: The endpoint the request was on.
2006 * Get first request from the ep queue, determine descriptor on which complete
2007 * happened. SW based on isoc_chain_num discovers which half of the descriptor
2008 * chain is currently in use by HW, adjusts dma_address and calculates index
2009 * of completed descriptor based on the value of DEPDMA register. Update actual
2010 * length of request, giveback to gadget.
2012 static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep
*hs_ep
)
2014 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
2015 struct dwc2_hsotg_req
*hs_req
;
2016 struct usb_request
*ureq
;
2018 dma_addr_t dma_addr
;
2024 hs_req
= get_ep_head(hs_ep
);
2026 dev_warn(hsotg
->dev
, "%s: ISOC EP queue empty\n", __func__
);
2029 ureq
= &hs_req
->req
;
2031 dma_addr
= hs_ep
->desc_list_dma
;
2034 * If lower half of descriptor chain is currently use by SW,
2035 * that means higher half is being processed by HW, so shift
2036 * DMA address to higher half of descriptor chain.
2038 if (!hs_ep
->isoc_chain_num
)
2039 dma_addr
+= sizeof(struct dwc2_dma_desc
) *
2040 (MAX_DMA_DESC_NUM_GENERIC
/ 2);
2042 dma_reg
= hs_ep
->dir_in
? DIEPDMA(hs_ep
->index
) : DOEPDMA(hs_ep
->index
);
2043 depdma
= dwc2_readl(hsotg
->regs
+ dma_reg
);
2045 index
= (depdma
- dma_addr
) / sizeof(struct dwc2_dma_desc
) - 1;
2046 desc_sts
= hs_ep
->desc_list
[index
].status
;
2048 mask
= hs_ep
->dir_in
? DEV_DMA_ISOC_TX_NBYTES_MASK
:
2049 DEV_DMA_ISOC_RX_NBYTES_MASK
;
2050 ureq
->actual
= ureq
->length
-
2051 ((desc_sts
& mask
) >> DEV_DMA_ISOC_NBYTES_SHIFT
);
2053 /* Adjust actual length for ISOC Out if length is not align of 4 */
2054 if (!hs_ep
->dir_in
&& ureq
->length
& 0x3)
2055 ureq
->actual
+= 4 - (ureq
->length
& 0x3);
2057 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
2061 * dwc2_gadget_start_next_isoc_ddma - start next isoc request, if any.
2062 * @hs_ep: The isochronous endpoint to be re-enabled.
2064 * If ep has been disabled due to last descriptor servicing (IN endpoint) or
2065 * BNA (OUT endpoint) check the status of other half of descriptor chain that
2066 * was under SW control till HW was busy and restart the endpoint if needed.
2068 static void dwc2_gadget_start_next_isoc_ddma(struct dwc2_hsotg_ep
*hs_ep
)
2070 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
2074 u32 dma_addr
= hs_ep
->desc_list_dma
;
2075 unsigned char index
= hs_ep
->index
;
2077 dma_reg
= hs_ep
->dir_in
? DIEPDMA(index
) : DOEPDMA(index
);
2078 depctl
= hs_ep
->dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2080 ctrl
= dwc2_readl(hsotg
->regs
+ depctl
);
2083 * EP was disabled if HW has processed last descriptor or BNA was set.
2084 * So restart ep if SW has prepared new descriptor chain in ep_queue
2085 * routine while HW was busy.
2087 if (!(ctrl
& DXEPCTL_EPENA
)) {
2088 if (!hs_ep
->next_desc
) {
2089 dev_dbg(hsotg
->dev
, "%s: No more ISOC requests\n",
2094 dma_addr
+= sizeof(struct dwc2_dma_desc
) *
2095 (MAX_DMA_DESC_NUM_GENERIC
/ 2) *
2096 hs_ep
->isoc_chain_num
;
2097 dwc2_writel(dma_addr
, hsotg
->regs
+ dma_reg
);
2099 ctrl
|= DXEPCTL_EPENA
| DXEPCTL_CNAK
;
2100 dwc2_writel(ctrl
, hsotg
->regs
+ depctl
);
2102 /* Switch ISOC descriptor chain number being processed by SW*/
2103 hs_ep
->isoc_chain_num
= (hs_ep
->isoc_chain_num
^ 1) & 0x1;
2104 hs_ep
->next_desc
= 0;
2106 dev_dbg(hsotg
->dev
, "%s: Restarted isochronous endpoint\n",
2112 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2113 * @hsotg: The device state.
2114 * @ep_idx: The endpoint index for the data
2115 * @size: The size of data in the fifo, in bytes
2117 * The FIFO status shows there is data to read from the FIFO for a given
2118 * endpoint, so sort out whether we need to read the data into a request
2119 * that has been made for that endpoint.
2121 static void dwc2_hsotg_rx_data(struct dwc2_hsotg
*hsotg
, int ep_idx
, int size
)
2123 struct dwc2_hsotg_ep
*hs_ep
= hsotg
->eps_out
[ep_idx
];
2124 struct dwc2_hsotg_req
*hs_req
= hs_ep
->req
;
2125 void __iomem
*fifo
= hsotg
->regs
+ EPFIFO(ep_idx
);
2131 u32 epctl
= dwc2_readl(hsotg
->regs
+ DOEPCTL(ep_idx
));
2135 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2136 __func__
, size
, ep_idx
, epctl
);
2138 /* dump the data from the FIFO, we've nothing we can do */
2139 for (ptr
= 0; ptr
< size
; ptr
+= 4)
2140 (void)dwc2_readl(fifo
);
2146 read_ptr
= hs_req
->req
.actual
;
2147 max_req
= hs_req
->req
.length
- read_ptr
;
2149 dev_dbg(hsotg
->dev
, "%s: read %d/%d, done %d/%d\n",
2150 __func__
, to_read
, max_req
, read_ptr
, hs_req
->req
.length
);
2152 if (to_read
> max_req
) {
2154 * more data appeared than we where willing
2155 * to deal with in this request.
2158 /* currently we don't deal this */
2162 hs_ep
->total_data
+= to_read
;
2163 hs_req
->req
.actual
+= to_read
;
2164 to_read
= DIV_ROUND_UP(to_read
, 4);
2167 * note, we might over-write the buffer end by 3 bytes depending on
2168 * alignment of the data.
2170 ioread32_rep(fifo
, hs_req
->req
.buf
+ read_ptr
, to_read
);
2174 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2175 * @hsotg: The device instance
2176 * @dir_in: If IN zlp
2178 * Generate a zero-length IN packet request for terminating a SETUP
2181 * Note, since we don't write any data to the TxFIFO, then it is
2182 * currently believed that we do not need to wait for any space in
2185 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg
*hsotg
, bool dir_in
)
2187 /* eps_out[0] is used in both directions */
2188 hsotg
->eps_out
[0]->dir_in
= dir_in
;
2189 hsotg
->ep0_state
= dir_in
? DWC2_EP0_STATUS_IN
: DWC2_EP0_STATUS_OUT
;
2191 dwc2_hsotg_program_zlp(hsotg
, hsotg
->eps_out
[0]);
2194 static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg
*hsotg
,
2199 ctrl
= dwc2_readl(hsotg
->regs
+ epctl_reg
);
2200 if (ctrl
& DXEPCTL_EOFRNUM
)
2201 ctrl
|= DXEPCTL_SETEVENFR
;
2203 ctrl
|= DXEPCTL_SETODDFR
;
2204 dwc2_writel(ctrl
, hsotg
->regs
+ epctl_reg
);
2208 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2209 * @hs_ep - The endpoint on which transfer went
2211 * Iterate over endpoints descriptor chain and get info on bytes remained
2212 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2214 static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep
*hs_ep
)
2216 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
2217 unsigned int bytes_rem
= 0;
2218 struct dwc2_dma_desc
*desc
= hs_ep
->desc_list
;
2225 for (i
= 0; i
< hs_ep
->desc_count
; ++i
) {
2226 status
= desc
->status
;
2227 bytes_rem
+= status
& DEV_DMA_NBYTES_MASK
;
2229 if (status
& DEV_DMA_STS_MASK
)
2230 dev_err(hsotg
->dev
, "descriptor %d closed with %x\n",
2231 i
, status
& DEV_DMA_STS_MASK
);
2238 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2239 * @hsotg: The device instance
2240 * @epnum: The endpoint received from
2242 * The RXFIFO has delivered an OutDone event, which means that the data
2243 * transfer for an OUT endpoint has been completed, either by a short
2244 * packet or by the finish of a transfer.
2246 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg
*hsotg
, int epnum
)
2248 u32 epsize
= dwc2_readl(hsotg
->regs
+ DOEPTSIZ(epnum
));
2249 struct dwc2_hsotg_ep
*hs_ep
= hsotg
->eps_out
[epnum
];
2250 struct dwc2_hsotg_req
*hs_req
= hs_ep
->req
;
2251 struct usb_request
*req
= &hs_req
->req
;
2252 unsigned int size_left
= DXEPTSIZ_XFERSIZE_GET(epsize
);
2256 dev_dbg(hsotg
->dev
, "%s: no request active\n", __func__
);
2260 if (epnum
== 0 && hsotg
->ep0_state
== DWC2_EP0_STATUS_OUT
) {
2261 dev_dbg(hsotg
->dev
, "zlp packet received\n");
2262 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
2263 dwc2_hsotg_enqueue_setup(hsotg
);
2267 if (using_desc_dma(hsotg
))
2268 size_left
= dwc2_gadget_get_xfersize_ddma(hs_ep
);
2270 if (using_dma(hsotg
)) {
2271 unsigned int size_done
;
2274 * Calculate the size of the transfer by checking how much
2275 * is left in the endpoint size register and then working it
2276 * out from the amount we loaded for the transfer.
2278 * We need to do this as DMA pointers are always 32bit aligned
2279 * so may overshoot/undershoot the transfer.
2282 size_done
= hs_ep
->size_loaded
- size_left
;
2283 size_done
+= hs_ep
->last_load
;
2285 req
->actual
= size_done
;
2288 /* if there is more request to do, schedule new transfer */
2289 if (req
->actual
< req
->length
&& size_left
== 0) {
2290 dwc2_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
2294 if (req
->actual
< req
->length
&& req
->short_not_ok
) {
2295 dev_dbg(hsotg
->dev
, "%s: got %d/%d (short not ok) => error\n",
2296 __func__
, req
->actual
, req
->length
);
2299 * todo - what should we return here? there's no one else
2300 * even bothering to check the status.
2304 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2305 if (!using_desc_dma(hsotg
) && epnum
== 0 &&
2306 hsotg
->ep0_state
== DWC2_EP0_DATA_OUT
) {
2307 /* Move to STATUS IN */
2308 dwc2_hsotg_ep0_zlp(hsotg
, true);
2313 * Slave mode OUT transfers do not go through XferComplete so
2314 * adjust the ISOC parity here.
2316 if (!using_dma(hsotg
)) {
2317 if (hs_ep
->isochronous
&& hs_ep
->interval
== 1)
2318 dwc2_hsotg_change_ep_iso_parity(hsotg
, DOEPCTL(epnum
));
2319 else if (hs_ep
->isochronous
&& hs_ep
->interval
> 1)
2320 dwc2_gadget_incr_frame_num(hs_ep
);
2323 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, result
);
2327 * dwc2_hsotg_handle_rx - RX FIFO has data
2328 * @hsotg: The device instance
2330 * The IRQ handler has detected that the RX FIFO has some data in it
2331 * that requires processing, so find out what is in there and do the
2334 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2335 * chunks, so if you have x packets received on an endpoint you'll get x
2336 * FIFO events delivered, each with a packet's worth of data in it.
2338 * When using DMA, we should not be processing events from the RXFIFO
2339 * as the actual data should be sent to the memory directly and we turn
2340 * on the completion interrupts to get notifications of transfer completion.
2342 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg
*hsotg
)
2344 u32 grxstsr
= dwc2_readl(hsotg
->regs
+ GRXSTSP
);
2345 u32 epnum
, status
, size
;
2347 WARN_ON(using_dma(hsotg
));
2349 epnum
= grxstsr
& GRXSTS_EPNUM_MASK
;
2350 status
= grxstsr
& GRXSTS_PKTSTS_MASK
;
2352 size
= grxstsr
& GRXSTS_BYTECNT_MASK
;
2353 size
>>= GRXSTS_BYTECNT_SHIFT
;
2355 dev_dbg(hsotg
->dev
, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2356 __func__
, grxstsr
, size
, epnum
);
2358 switch ((status
& GRXSTS_PKTSTS_MASK
) >> GRXSTS_PKTSTS_SHIFT
) {
2359 case GRXSTS_PKTSTS_GLOBALOUTNAK
:
2360 dev_dbg(hsotg
->dev
, "GLOBALOUTNAK\n");
2363 case GRXSTS_PKTSTS_OUTDONE
:
2364 dev_dbg(hsotg
->dev
, "OutDone (Frame=0x%08x)\n",
2365 dwc2_hsotg_read_frameno(hsotg
));
2367 if (!using_dma(hsotg
))
2368 dwc2_hsotg_handle_outdone(hsotg
, epnum
);
2371 case GRXSTS_PKTSTS_SETUPDONE
:
2373 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2374 dwc2_hsotg_read_frameno(hsotg
),
2375 dwc2_readl(hsotg
->regs
+ DOEPCTL(0)));
2377 * Call dwc2_hsotg_handle_outdone here if it was not called from
2378 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2379 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2381 if (hsotg
->ep0_state
== DWC2_EP0_SETUP
)
2382 dwc2_hsotg_handle_outdone(hsotg
, epnum
);
2385 case GRXSTS_PKTSTS_OUTRX
:
2386 dwc2_hsotg_rx_data(hsotg
, epnum
, size
);
2389 case GRXSTS_PKTSTS_SETUPRX
:
2391 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2392 dwc2_hsotg_read_frameno(hsotg
),
2393 dwc2_readl(hsotg
->regs
+ DOEPCTL(0)));
2395 WARN_ON(hsotg
->ep0_state
!= DWC2_EP0_SETUP
);
2397 dwc2_hsotg_rx_data(hsotg
, epnum
, size
);
2401 dev_warn(hsotg
->dev
, "%s: unknown status %08x\n",
2404 dwc2_hsotg_dump(hsotg
);
2410 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2411 * @mps: The maximum packet size in bytes.
2413 static u32
dwc2_hsotg_ep0_mps(unsigned int mps
)
2417 return D0EPCTL_MPS_64
;
2419 return D0EPCTL_MPS_32
;
2421 return D0EPCTL_MPS_16
;
2423 return D0EPCTL_MPS_8
;
2426 /* bad max packet size, warn and return invalid result */
2432 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2433 * @hsotg: The driver state.
2434 * @ep: The index number of the endpoint
2435 * @mps: The maximum packet size in bytes
2436 * @mc: The multicount value
2438 * Configure the maximum packet size for the given endpoint, updating
2439 * the hardware control registers to reflect this.
2441 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg
*hsotg
,
2442 unsigned int ep
, unsigned int mps
,
2443 unsigned int mc
, unsigned int dir_in
)
2445 struct dwc2_hsotg_ep
*hs_ep
;
2446 void __iomem
*regs
= hsotg
->regs
;
2449 hs_ep
= index_to_ep(hsotg
, ep
, dir_in
);
2454 u32 mps_bytes
= mps
;
2456 /* EP0 is a special case */
2457 mps
= dwc2_hsotg_ep0_mps(mps_bytes
);
2460 hs_ep
->ep
.maxpacket
= mps_bytes
;
2468 hs_ep
->ep
.maxpacket
= mps
;
2472 reg
= dwc2_readl(regs
+ DIEPCTL(ep
));
2473 reg
&= ~DXEPCTL_MPS_MASK
;
2475 dwc2_writel(reg
, regs
+ DIEPCTL(ep
));
2477 reg
= dwc2_readl(regs
+ DOEPCTL(ep
));
2478 reg
&= ~DXEPCTL_MPS_MASK
;
2480 dwc2_writel(reg
, regs
+ DOEPCTL(ep
));
2486 dev_err(hsotg
->dev
, "ep%d: bad mps of %d\n", ep
, mps
);
2490 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2491 * @hsotg: The driver state
2492 * @idx: The index for the endpoint (0..15)
2494 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg
*hsotg
, unsigned int idx
)
2499 dwc2_writel(GRSTCTL_TXFNUM(idx
) | GRSTCTL_TXFFLSH
,
2500 hsotg
->regs
+ GRSTCTL
);
2502 /* wait until the fifo is flushed */
2506 val
= dwc2_readl(hsotg
->regs
+ GRSTCTL
);
2508 if ((val
& (GRSTCTL_TXFFLSH
)) == 0)
2511 if (--timeout
== 0) {
2513 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
2523 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2524 * @hsotg: The driver state
2525 * @hs_ep: The driver endpoint to check.
2527 * Check to see if there is a request that has data to send, and if so
2528 * make an attempt to write data into the FIFO.
2530 static int dwc2_hsotg_trytx(struct dwc2_hsotg
*hsotg
,
2531 struct dwc2_hsotg_ep
*hs_ep
)
2533 struct dwc2_hsotg_req
*hs_req
= hs_ep
->req
;
2535 if (!hs_ep
->dir_in
|| !hs_req
) {
2537 * if request is not enqueued, we disable interrupts
2538 * for endpoints, excepting ep0
2540 if (hs_ep
->index
!= 0)
2541 dwc2_hsotg_ctrl_epint(hsotg
, hs_ep
->index
,
2546 if (hs_req
->req
.actual
< hs_req
->req
.length
) {
2547 dev_dbg(hsotg
->dev
, "trying to write more for ep%d\n",
2549 return dwc2_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
2556 * dwc2_hsotg_complete_in - complete IN transfer
2557 * @hsotg: The device state.
2558 * @hs_ep: The endpoint that has just completed.
2560 * An IN transfer has been completed, update the transfer's state and then
2561 * call the relevant completion routines.
2563 static void dwc2_hsotg_complete_in(struct dwc2_hsotg
*hsotg
,
2564 struct dwc2_hsotg_ep
*hs_ep
)
2566 struct dwc2_hsotg_req
*hs_req
= hs_ep
->req
;
2567 u32 epsize
= dwc2_readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
2568 int size_left
, size_done
;
2571 dev_dbg(hsotg
->dev
, "XferCompl but no req\n");
2575 /* Finish ZLP handling for IN EP0 transactions */
2576 if (hs_ep
->index
== 0 && hsotg
->ep0_state
== DWC2_EP0_STATUS_IN
) {
2577 dev_dbg(hsotg
->dev
, "zlp packet sent\n");
2580 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2581 * changed to IN. Change back to complete OUT transfer request
2585 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
2586 if (hsotg
->test_mode
) {
2589 ret
= dwc2_hsotg_set_test_mode(hsotg
, hsotg
->test_mode
);
2591 dev_dbg(hsotg
->dev
, "Invalid Test #%d\n",
2593 dwc2_hsotg_stall_ep0(hsotg
);
2597 dwc2_hsotg_enqueue_setup(hsotg
);
2602 * Calculate the size of the transfer by checking how much is left
2603 * in the endpoint size register and then working it out from
2604 * the amount we loaded for the transfer.
2606 * We do this even for DMA, as the transfer may have incremented
2607 * past the end of the buffer (DMA transfers are always 32bit
2610 if (using_desc_dma(hsotg
)) {
2611 size_left
= dwc2_gadget_get_xfersize_ddma(hs_ep
);
2613 dev_err(hsotg
->dev
, "error parsing DDMA results %d\n",
2616 size_left
= DXEPTSIZ_XFERSIZE_GET(epsize
);
2619 size_done
= hs_ep
->size_loaded
- size_left
;
2620 size_done
+= hs_ep
->last_load
;
2622 if (hs_req
->req
.actual
!= size_done
)
2623 dev_dbg(hsotg
->dev
, "%s: adjusting size done %d => %d\n",
2624 __func__
, hs_req
->req
.actual
, size_done
);
2626 hs_req
->req
.actual
= size_done
;
2627 dev_dbg(hsotg
->dev
, "req->length:%d req->actual:%d req->zero:%d\n",
2628 hs_req
->req
.length
, hs_req
->req
.actual
, hs_req
->req
.zero
);
2630 if (!size_left
&& hs_req
->req
.actual
< hs_req
->req
.length
) {
2631 dev_dbg(hsotg
->dev
, "%s trying more for req...\n", __func__
);
2632 dwc2_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
2636 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
2637 if (hs_ep
->send_zlp
) {
2638 dwc2_hsotg_program_zlp(hsotg
, hs_ep
);
2639 hs_ep
->send_zlp
= 0;
2640 /* transfer will be completed on next complete interrupt */
2644 if (hs_ep
->index
== 0 && hsotg
->ep0_state
== DWC2_EP0_DATA_IN
) {
2645 /* Move to STATUS OUT */
2646 dwc2_hsotg_ep0_zlp(hsotg
, false);
2650 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
2654 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2655 * @hsotg: The device state.
2656 * @idx: Index of ep.
2657 * @dir_in: Endpoint direction 1-in 0-out.
2659 * Reads for endpoint with given index and direction, by masking
2660 * epint_reg with coresponding mask.
2662 static u32
dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg
*hsotg
,
2663 unsigned int idx
, int dir_in
)
2665 u32 epmsk_reg
= dir_in
? DIEPMSK
: DOEPMSK
;
2666 u32 epint_reg
= dir_in
? DIEPINT(idx
) : DOEPINT(idx
);
2671 mask
= dwc2_readl(hsotg
->regs
+ epmsk_reg
);
2672 diepempmsk
= dwc2_readl(hsotg
->regs
+ DIEPEMPMSK
);
2673 mask
|= ((diepempmsk
>> idx
) & 0x1) ? DIEPMSK_TXFIFOEMPTY
: 0;
2674 mask
|= DXEPINT_SETUP_RCVD
;
2676 ints
= dwc2_readl(hsotg
->regs
+ epint_reg
);
2682 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2683 * @hs_ep: The endpoint on which interrupt is asserted.
2685 * This interrupt indicates that the endpoint has been disabled per the
2686 * application's request.
2688 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2689 * in case of ISOC completes current request.
2691 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2692 * request starts it.
2694 static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep
*hs_ep
)
2696 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
2697 struct dwc2_hsotg_req
*hs_req
;
2698 unsigned char idx
= hs_ep
->index
;
2699 int dir_in
= hs_ep
->dir_in
;
2700 u32 epctl_reg
= dir_in
? DIEPCTL(idx
) : DOEPCTL(idx
);
2701 int dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
2703 dev_dbg(hsotg
->dev
, "%s: EPDisbld\n", __func__
);
2706 int epctl
= dwc2_readl(hsotg
->regs
+ epctl_reg
);
2708 dwc2_hsotg_txfifo_flush(hsotg
, hs_ep
->fifo_index
);
2710 if (hs_ep
->isochronous
) {
2711 dwc2_hsotg_complete_in(hsotg
, hs_ep
);
2715 if ((epctl
& DXEPCTL_STALL
) && (epctl
& DXEPCTL_EPTYPE_BULK
)) {
2716 int dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
2718 dctl
|= DCTL_CGNPINNAK
;
2719 dwc2_writel(dctl
, hsotg
->regs
+ DCTL
);
2724 if (dctl
& DCTL_GOUTNAKSTS
) {
2725 dctl
|= DCTL_CGOUTNAK
;
2726 dwc2_writel(dctl
, hsotg
->regs
+ DCTL
);
2729 if (!hs_ep
->isochronous
)
2732 if (list_empty(&hs_ep
->queue
)) {
2733 dev_dbg(hsotg
->dev
, "%s: complete_ep 0x%p, ep->queue empty!\n",
2739 hs_req
= get_ep_head(hs_ep
);
2741 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
,
2743 dwc2_gadget_incr_frame_num(hs_ep
);
2744 } while (dwc2_gadget_target_frame_elapsed(hs_ep
));
2746 dwc2_gadget_start_next_request(hs_ep
);
2750 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2751 * @hs_ep: The endpoint on which interrupt is asserted.
2753 * This is starting point for ISOC-OUT transfer, synchronization done with
2754 * first out token received from host while corresponding EP is disabled.
2756 * Device does not know initial frame in which out token will come. For this
2757 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2758 * getting this interrupt SW starts calculation for next transfer frame.
2760 static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep
*ep
)
2762 struct dwc2_hsotg
*hsotg
= ep
->parent
;
2763 int dir_in
= ep
->dir_in
;
2767 if (dir_in
|| !ep
->isochronous
)
2771 * Store frame in which irq was asserted here, as
2772 * it can change while completing request below.
2774 tmp
= dwc2_hsotg_read_frameno(hsotg
);
2776 dwc2_hsotg_complete_request(hsotg
, ep
, get_ep_head(ep
), -ENODATA
);
2778 if (using_desc_dma(hsotg
)) {
2779 if (ep
->target_frame
== TARGET_FRAME_INITIAL
) {
2780 /* Start first ISO Out */
2781 ep
->target_frame
= tmp
;
2782 dwc2_gadget_start_isoc_ddma(ep
);
2787 if (ep
->interval
> 1 &&
2788 ep
->target_frame
== TARGET_FRAME_INITIAL
) {
2792 dsts
= dwc2_readl(hsotg
->regs
+ DSTS
);
2793 ep
->target_frame
= dwc2_hsotg_read_frameno(hsotg
);
2794 dwc2_gadget_incr_frame_num(ep
);
2796 ctrl
= dwc2_readl(hsotg
->regs
+ DOEPCTL(ep
->index
));
2797 if (ep
->target_frame
& 0x1)
2798 ctrl
|= DXEPCTL_SETODDFR
;
2800 ctrl
|= DXEPCTL_SETEVENFR
;
2802 dwc2_writel(ctrl
, hsotg
->regs
+ DOEPCTL(ep
->index
));
2805 dwc2_gadget_start_next_request(ep
);
2806 doepmsk
= dwc2_readl(hsotg
->regs
+ DOEPMSK
);
2807 doepmsk
&= ~DOEPMSK_OUTTKNEPDISMSK
;
2808 dwc2_writel(doepmsk
, hsotg
->regs
+ DOEPMSK
);
2812 * dwc2_gadget_handle_nak - handle NAK interrupt
2813 * @hs_ep: The endpoint on which interrupt is asserted.
2815 * This is starting point for ISOC-IN transfer, synchronization done with
2816 * first IN token received from host while corresponding EP is disabled.
2818 * Device does not know when first one token will arrive from host. On first
2819 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2820 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2821 * sent in response to that as there was no data in FIFO. SW is basing on this
2822 * interrupt to obtain frame in which token has come and then based on the
2823 * interval calculates next frame for transfer.
2825 static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep
*hs_ep
)
2827 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
2828 int dir_in
= hs_ep
->dir_in
;
2830 if (!dir_in
|| !hs_ep
->isochronous
)
2833 if (hs_ep
->target_frame
== TARGET_FRAME_INITIAL
) {
2834 hs_ep
->target_frame
= dwc2_hsotg_read_frameno(hsotg
);
2836 if (using_desc_dma(hsotg
)) {
2837 dwc2_gadget_start_isoc_ddma(hs_ep
);
2841 if (hs_ep
->interval
> 1) {
2842 u32 ctrl
= dwc2_readl(hsotg
->regs
+
2843 DIEPCTL(hs_ep
->index
));
2844 if (hs_ep
->target_frame
& 0x1)
2845 ctrl
|= DXEPCTL_SETODDFR
;
2847 ctrl
|= DXEPCTL_SETEVENFR
;
2849 dwc2_writel(ctrl
, hsotg
->regs
+ DIEPCTL(hs_ep
->index
));
2852 dwc2_hsotg_complete_request(hsotg
, hs_ep
,
2853 get_ep_head(hs_ep
), 0);
2856 dwc2_gadget_incr_frame_num(hs_ep
);
2860 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
2861 * @hsotg: The driver state
2862 * @idx: The index for the endpoint (0..15)
2863 * @dir_in: Set if this is an IN endpoint
2865 * Process and clear any interrupt pending for an individual endpoint
2867 static void dwc2_hsotg_epint(struct dwc2_hsotg
*hsotg
, unsigned int idx
,
2870 struct dwc2_hsotg_ep
*hs_ep
= index_to_ep(hsotg
, idx
, dir_in
);
2871 u32 epint_reg
= dir_in
? DIEPINT(idx
) : DOEPINT(idx
);
2872 u32 epctl_reg
= dir_in
? DIEPCTL(idx
) : DOEPCTL(idx
);
2873 u32 epsiz_reg
= dir_in
? DIEPTSIZ(idx
) : DOEPTSIZ(idx
);
2877 ints
= dwc2_gadget_read_ep_interrupts(hsotg
, idx
, dir_in
);
2878 ctrl
= dwc2_readl(hsotg
->regs
+ epctl_reg
);
2880 /* Clear endpoint interrupts */
2881 dwc2_writel(ints
, hsotg
->regs
+ epint_reg
);
2884 dev_err(hsotg
->dev
, "%s:Interrupt for unconfigured ep%d(%s)\n",
2885 __func__
, idx
, dir_in
? "in" : "out");
2889 dev_dbg(hsotg
->dev
, "%s: ep%d(%s) DxEPINT=0x%08x\n",
2890 __func__
, idx
, dir_in
? "in" : "out", ints
);
2892 /* Don't process XferCompl interrupt if it is a setup packet */
2893 if (idx
== 0 && (ints
& (DXEPINT_SETUP
| DXEPINT_SETUP_RCVD
)))
2894 ints
&= ~DXEPINT_XFERCOMPL
;
2897 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
2898 * stage and xfercomplete was generated without SETUP phase done
2899 * interrupt. SW should parse received setup packet only after host's
2900 * exit from setup phase of control transfer.
2902 if (using_desc_dma(hsotg
) && idx
== 0 && !hs_ep
->dir_in
&&
2903 hsotg
->ep0_state
== DWC2_EP0_SETUP
&& !(ints
& DXEPINT_SETUP
))
2904 ints
&= ~DXEPINT_XFERCOMPL
;
2906 if (ints
& DXEPINT_XFERCOMPL
) {
2908 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
2909 __func__
, dwc2_readl(hsotg
->regs
+ epctl_reg
),
2910 dwc2_readl(hsotg
->regs
+ epsiz_reg
));
2912 /* In DDMA handle isochronous requests separately */
2913 if (using_desc_dma(hsotg
) && hs_ep
->isochronous
) {
2914 dwc2_gadget_complete_isoc_request_ddma(hs_ep
);
2915 /* Try to start next isoc request */
2916 dwc2_gadget_start_next_isoc_ddma(hs_ep
);
2917 } else if (dir_in
) {
2919 * We get OutDone from the FIFO, so we only
2920 * need to look at completing IN requests here
2921 * if operating slave mode
2923 if (hs_ep
->isochronous
&& hs_ep
->interval
> 1)
2924 dwc2_gadget_incr_frame_num(hs_ep
);
2926 dwc2_hsotg_complete_in(hsotg
, hs_ep
);
2927 if (ints
& DXEPINT_NAKINTRPT
)
2928 ints
&= ~DXEPINT_NAKINTRPT
;
2930 if (idx
== 0 && !hs_ep
->req
)
2931 dwc2_hsotg_enqueue_setup(hsotg
);
2932 } else if (using_dma(hsotg
)) {
2934 * We're using DMA, we need to fire an OutDone here
2935 * as we ignore the RXFIFO.
2937 if (hs_ep
->isochronous
&& hs_ep
->interval
> 1)
2938 dwc2_gadget_incr_frame_num(hs_ep
);
2940 dwc2_hsotg_handle_outdone(hsotg
, idx
);
2944 if (ints
& DXEPINT_EPDISBLD
)
2945 dwc2_gadget_handle_ep_disabled(hs_ep
);
2947 if (ints
& DXEPINT_OUTTKNEPDIS
)
2948 dwc2_gadget_handle_out_token_ep_disabled(hs_ep
);
2950 if (ints
& DXEPINT_NAKINTRPT
)
2951 dwc2_gadget_handle_nak(hs_ep
);
2953 if (ints
& DXEPINT_AHBERR
)
2954 dev_dbg(hsotg
->dev
, "%s: AHBErr\n", __func__
);
2956 if (ints
& DXEPINT_SETUP
) { /* Setup or Timeout */
2957 dev_dbg(hsotg
->dev
, "%s: Setup/Timeout\n", __func__
);
2959 if (using_dma(hsotg
) && idx
== 0) {
2961 * this is the notification we've received a
2962 * setup packet. In non-DMA mode we'd get this
2963 * from the RXFIFO, instead we need to process
2970 dwc2_hsotg_handle_outdone(hsotg
, 0);
2974 if (ints
& DXEPINT_STSPHSERCVD
) {
2975 dev_dbg(hsotg
->dev
, "%s: StsPhseRcvd\n", __func__
);
2977 /* Move to STATUS IN for DDMA */
2978 if (using_desc_dma(hsotg
))
2979 dwc2_hsotg_ep0_zlp(hsotg
, true);
2982 if (ints
& DXEPINT_BACK2BACKSETUP
)
2983 dev_dbg(hsotg
->dev
, "%s: B2BSetup/INEPNakEff\n", __func__
);
2985 if (ints
& DXEPINT_BNAINTR
) {
2986 dev_dbg(hsotg
->dev
, "%s: BNA interrupt\n", __func__
);
2989 * Try to start next isoc request, if any.
2990 * Sometimes the endpoint remains enabled after BNA interrupt
2991 * assertion, which is not expected, hence we can enter here
2994 if (hs_ep
->isochronous
)
2995 dwc2_gadget_start_next_isoc_ddma(hs_ep
);
2998 if (dir_in
&& !hs_ep
->isochronous
) {
2999 /* not sure if this is important, but we'll clear it anyway */
3000 if (ints
& DXEPINT_INTKNTXFEMP
) {
3001 dev_dbg(hsotg
->dev
, "%s: ep%d: INTknTXFEmpMsk\n",
3005 /* this probably means something bad is happening */
3006 if (ints
& DXEPINT_INTKNEPMIS
) {
3007 dev_warn(hsotg
->dev
, "%s: ep%d: INTknEP\n",
3011 /* FIFO has space or is empty (see GAHBCFG) */
3012 if (hsotg
->dedicated_fifos
&&
3013 ints
& DXEPINT_TXFEMP
) {
3014 dev_dbg(hsotg
->dev
, "%s: ep%d: TxFIFOEmpty\n",
3016 if (!using_dma(hsotg
))
3017 dwc2_hsotg_trytx(hsotg
, hs_ep
);
3023 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3024 * @hsotg: The device state.
3026 * Handle updating the device settings after the enumeration phase has
3029 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg
*hsotg
)
3031 u32 dsts
= dwc2_readl(hsotg
->regs
+ DSTS
);
3032 int ep0_mps
= 0, ep_mps
= 8;
3035 * This should signal the finish of the enumeration phase
3036 * of the USB handshaking, so we should now know what rate
3040 dev_dbg(hsotg
->dev
, "EnumDone (DSTS=0x%08x)\n", dsts
);
3043 * note, since we're limited by the size of transfer on EP0, and
3044 * it seems IN transfers must be a even number of packets we do
3045 * not advertise a 64byte MPS on EP0.
3048 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3049 switch ((dsts
& DSTS_ENUMSPD_MASK
) >> DSTS_ENUMSPD_SHIFT
) {
3050 case DSTS_ENUMSPD_FS
:
3051 case DSTS_ENUMSPD_FS48
:
3052 hsotg
->gadget
.speed
= USB_SPEED_FULL
;
3053 ep0_mps
= EP0_MPS_LIMIT
;
3057 case DSTS_ENUMSPD_HS
:
3058 hsotg
->gadget
.speed
= USB_SPEED_HIGH
;
3059 ep0_mps
= EP0_MPS_LIMIT
;
3063 case DSTS_ENUMSPD_LS
:
3064 hsotg
->gadget
.speed
= USB_SPEED_LOW
;
3068 * note, we don't actually support LS in this driver at the
3069 * moment, and the documentation seems to imply that it isn't
3070 * supported by the PHYs on some of the devices.
3074 dev_info(hsotg
->dev
, "new device is %s\n",
3075 usb_speed_string(hsotg
->gadget
.speed
));
3078 * we should now know the maximum packet size for an
3079 * endpoint, so set the endpoints to a default value.
3084 /* Initialize ep0 for both in and out directions */
3085 dwc2_hsotg_set_ep_maxpacket(hsotg
, 0, ep0_mps
, 0, 1);
3086 dwc2_hsotg_set_ep_maxpacket(hsotg
, 0, ep0_mps
, 0, 0);
3087 for (i
= 1; i
< hsotg
->num_of_eps
; i
++) {
3088 if (hsotg
->eps_in
[i
])
3089 dwc2_hsotg_set_ep_maxpacket(hsotg
, i
, ep_mps
,
3091 if (hsotg
->eps_out
[i
])
3092 dwc2_hsotg_set_ep_maxpacket(hsotg
, i
, ep_mps
,
3097 /* ensure after enumeration our EP0 is active */
3099 dwc2_hsotg_enqueue_setup(hsotg
);
3101 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3102 dwc2_readl(hsotg
->regs
+ DIEPCTL0
),
3103 dwc2_readl(hsotg
->regs
+ DOEPCTL0
));
3107 * kill_all_requests - remove all requests from the endpoint's queue
3108 * @hsotg: The device state.
3109 * @ep: The endpoint the requests may be on.
3110 * @result: The result code to use.
3112 * Go through the requests on the given endpoint and mark them
3113 * completed with the given result code.
3115 static void kill_all_requests(struct dwc2_hsotg
*hsotg
,
3116 struct dwc2_hsotg_ep
*ep
,
3119 struct dwc2_hsotg_req
*req
, *treq
;
3124 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
)
3125 dwc2_hsotg_complete_request(hsotg
, ep
, req
,
3128 if (!hsotg
->dedicated_fifos
)
3130 size
= (dwc2_readl(hsotg
->regs
+ DTXFSTS(ep
->fifo_index
)) & 0xffff) * 4;
3131 if (size
< ep
->fifo_size
)
3132 dwc2_hsotg_txfifo_flush(hsotg
, ep
->fifo_index
);
3136 * dwc2_hsotg_disconnect - disconnect service
3137 * @hsotg: The device state.
3139 * The device has been disconnected. Remove all current
3140 * transactions and signal the gadget driver that this
3143 void dwc2_hsotg_disconnect(struct dwc2_hsotg
*hsotg
)
3147 if (!hsotg
->connected
)
3150 hsotg
->connected
= 0;
3151 hsotg
->test_mode
= 0;
3153 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++) {
3154 if (hsotg
->eps_in
[ep
])
3155 kill_all_requests(hsotg
, hsotg
->eps_in
[ep
],
3157 if (hsotg
->eps_out
[ep
])
3158 kill_all_requests(hsotg
, hsotg
->eps_out
[ep
],
3162 call_gadget(hsotg
, disconnect
);
3163 hsotg
->lx_state
= DWC2_L3
;
3165 usb_gadget_set_state(&hsotg
->gadget
, USB_STATE_NOTATTACHED
);
3169 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3170 * @hsotg: The device state:
3171 * @periodic: True if this is a periodic FIFO interrupt
3173 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg
*hsotg
, bool periodic
)
3175 struct dwc2_hsotg_ep
*ep
;
3178 /* look through for any more data to transmit */
3179 for (epno
= 0; epno
< hsotg
->num_of_eps
; epno
++) {
3180 ep
= index_to_ep(hsotg
, epno
, 1);
3188 if ((periodic
&& !ep
->periodic
) ||
3189 (!periodic
&& ep
->periodic
))
3192 ret
= dwc2_hsotg_trytx(hsotg
, ep
);
3198 /* IRQ flags which will trigger a retry around the IRQ loop */
3199 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3204 * dwc2_hsotg_core_init - issue softreset to the core
3205 * @hsotg: The device state
3207 * Issue a soft reset to the core, and await the core finishing it.
3209 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg
*hsotg
,
3217 /* Kill any ep0 requests as controller will be reinitialized */
3218 kill_all_requests(hsotg
, hsotg
->eps_out
[0], -ECONNRESET
);
3221 if (dwc2_core_reset(hsotg
, true))
3225 * we must now enable ep0 ready for host detection and then
3226 * set configuration.
3229 /* keep other bits untouched (so e.g. forced modes are not lost) */
3230 usbcfg
= dwc2_readl(hsotg
->regs
+ GUSBCFG
);
3231 usbcfg
&= ~(GUSBCFG_TOUTCAL_MASK
| GUSBCFG_PHYIF16
| GUSBCFG_SRPCAP
|
3232 GUSBCFG_HNPCAP
| GUSBCFG_USBTRDTIM_MASK
);
3234 if (hsotg
->params
.phy_type
== DWC2_PHY_TYPE_PARAM_FS
&&
3235 (hsotg
->params
.speed
== DWC2_SPEED_PARAM_FULL
||
3236 hsotg
->params
.speed
== DWC2_SPEED_PARAM_LOW
)) {
3237 /* FS/LS Dedicated Transceiver Interface */
3238 usbcfg
|= GUSBCFG_PHYSEL
;
3240 /* set the PLL on, remove the HNP/SRP and set the PHY */
3241 val
= (hsotg
->phyif
== GUSBCFG_PHYIF8
) ? 9 : 5;
3242 usbcfg
|= hsotg
->phyif
| GUSBCFG_TOUTCAL(7) |
3243 (val
<< GUSBCFG_USBTRDTIM_SHIFT
);
3245 dwc2_writel(usbcfg
, hsotg
->regs
+ GUSBCFG
);
3247 dwc2_hsotg_init_fifo(hsotg
);
3250 __orr32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
3252 dcfg
|= DCFG_EPMISCNT(1);
3254 switch (hsotg
->params
.speed
) {
3255 case DWC2_SPEED_PARAM_LOW
:
3256 dcfg
|= DCFG_DEVSPD_LS
;
3258 case DWC2_SPEED_PARAM_FULL
:
3259 if (hsotg
->params
.phy_type
== DWC2_PHY_TYPE_PARAM_FS
)
3260 dcfg
|= DCFG_DEVSPD_FS48
;
3262 dcfg
|= DCFG_DEVSPD_FS
;
3265 dcfg
|= DCFG_DEVSPD_HS
;
3268 dwc2_writel(dcfg
, hsotg
->regs
+ DCFG
);
3270 /* Clear any pending OTG interrupts */
3271 dwc2_writel(0xffffffff, hsotg
->regs
+ GOTGINT
);
3273 /* Clear any pending interrupts */
3274 dwc2_writel(0xffffffff, hsotg
->regs
+ GINTSTS
);
3275 intmsk
= GINTSTS_ERLYSUSP
| GINTSTS_SESSREQINT
|
3276 GINTSTS_GOUTNAKEFF
| GINTSTS_GINNAKEFF
|
3277 GINTSTS_USBRST
| GINTSTS_RESETDET
|
3278 GINTSTS_ENUMDONE
| GINTSTS_OTGINT
|
3279 GINTSTS_USBSUSP
| GINTSTS_WKUPINT
;
3281 if (!using_desc_dma(hsotg
))
3282 intmsk
|= GINTSTS_INCOMPL_SOIN
| GINTSTS_INCOMPL_SOOUT
;
3284 if (!hsotg
->params
.external_id_pin_ctl
)
3285 intmsk
|= GINTSTS_CONIDSTSCHNG
;
3287 dwc2_writel(intmsk
, hsotg
->regs
+ GINTMSK
);
3289 if (using_dma(hsotg
)) {
3290 dwc2_writel(GAHBCFG_GLBL_INTR_EN
| GAHBCFG_DMA_EN
|
3291 (GAHBCFG_HBSTLEN_INCR4
<< GAHBCFG_HBSTLEN_SHIFT
),
3292 hsotg
->regs
+ GAHBCFG
);
3294 /* Set DDMA mode support in the core if needed */
3295 if (using_desc_dma(hsotg
))
3296 __orr32(hsotg
->regs
+ DCFG
, DCFG_DESCDMA_EN
);
3299 dwc2_writel(((hsotg
->dedicated_fifos
) ?
3300 (GAHBCFG_NP_TXF_EMP_LVL
|
3301 GAHBCFG_P_TXF_EMP_LVL
) : 0) |
3302 GAHBCFG_GLBL_INTR_EN
, hsotg
->regs
+ GAHBCFG
);
3306 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3307 * when we have no data to transfer. Otherwise we get being flooded by
3311 dwc2_writel(((hsotg
->dedicated_fifos
&& !using_dma(hsotg
)) ?
3312 DIEPMSK_TXFIFOEMPTY
| DIEPMSK_INTKNTXFEMPMSK
: 0) |
3313 DIEPMSK_EPDISBLDMSK
| DIEPMSK_XFERCOMPLMSK
|
3314 DIEPMSK_TIMEOUTMSK
| DIEPMSK_AHBERRMSK
,
3315 hsotg
->regs
+ DIEPMSK
);
3318 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3319 * DMA mode we may need this and StsPhseRcvd.
3321 dwc2_writel((using_dma(hsotg
) ? (DIEPMSK_XFERCOMPLMSK
|
3322 DOEPMSK_STSPHSERCVDMSK
) : 0) |
3323 DOEPMSK_EPDISBLDMSK
| DOEPMSK_AHBERRMSK
|
3325 hsotg
->regs
+ DOEPMSK
);
3327 /* Enable BNA interrupt for DDMA */
3328 if (using_desc_dma(hsotg
))
3329 __orr32(hsotg
->regs
+ DOEPMSK
, DOEPMSK_BNAMSK
);
3331 dwc2_writel(0, hsotg
->regs
+ DAINTMSK
);
3333 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3334 dwc2_readl(hsotg
->regs
+ DIEPCTL0
),
3335 dwc2_readl(hsotg
->regs
+ DOEPCTL0
));
3337 /* enable in and out endpoint interrupts */
3338 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_OEPINT
| GINTSTS_IEPINT
);
3341 * Enable the RXFIFO when in slave mode, as this is how we collect
3342 * the data. In DMA mode, we get events from the FIFO but also
3343 * things we cannot process, so do not use it.
3345 if (!using_dma(hsotg
))
3346 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_RXFLVL
);
3348 /* Enable interrupts for EP0 in and out */
3349 dwc2_hsotg_ctrl_epint(hsotg
, 0, 0, 1);
3350 dwc2_hsotg_ctrl_epint(hsotg
, 0, 1, 1);
3352 if (!is_usb_reset
) {
3353 __orr32(hsotg
->regs
+ DCTL
, DCTL_PWRONPRGDONE
);
3354 udelay(10); /* see openiboot */
3355 __bic32(hsotg
->regs
+ DCTL
, DCTL_PWRONPRGDONE
);
3358 dev_dbg(hsotg
->dev
, "DCTL=0x%08x\n", dwc2_readl(hsotg
->regs
+ DCTL
));
3361 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3362 * writing to the EPCTL register..
3365 /* set to read 1 8byte packet */
3366 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3367 DXEPTSIZ_XFERSIZE(8), hsotg
->regs
+ DOEPTSIZ0
);
3369 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg
->eps_out
[0]->ep
.maxpacket
) |
3370 DXEPCTL_CNAK
| DXEPCTL_EPENA
|
3372 hsotg
->regs
+ DOEPCTL0
);
3374 /* enable, but don't activate EP0in */
3375 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg
->eps_out
[0]->ep
.maxpacket
) |
3376 DXEPCTL_USBACTEP
, hsotg
->regs
+ DIEPCTL0
);
3378 dwc2_hsotg_enqueue_setup(hsotg
);
3380 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3381 dwc2_readl(hsotg
->regs
+ DIEPCTL0
),
3382 dwc2_readl(hsotg
->regs
+ DOEPCTL0
));
3384 /* clear global NAKs */
3385 val
= DCTL_CGOUTNAK
| DCTL_CGNPINNAK
;
3387 val
|= DCTL_SFTDISCON
;
3388 __orr32(hsotg
->regs
+ DCTL
, val
);
3390 /* must be at-least 3ms to allow bus to see disconnect */
3393 hsotg
->lx_state
= DWC2_L0
;
3396 static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg
*hsotg
)
3398 /* set the soft-disconnect bit */
3399 __orr32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
3402 void dwc2_hsotg_core_connect(struct dwc2_hsotg
*hsotg
)
3404 /* remove the soft-disconnect and let's go */
3405 __bic32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
3409 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3410 * @hsotg: The device state:
3412 * This interrupt indicates one of the following conditions occurred while
3413 * transmitting an ISOC transaction.
3414 * - Corrupted IN Token for ISOC EP.
3415 * - Packet not complete in FIFO.
3417 * The following actions will be taken:
3418 * - Determine the EP
3419 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3421 static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg
*hsotg
)
3423 struct dwc2_hsotg_ep
*hs_ep
;
3427 dev_dbg(hsotg
->dev
, "Incomplete isoc in interrupt received:\n");
3429 for (idx
= 1; idx
<= hsotg
->num_of_eps
; idx
++) {
3430 hs_ep
= hsotg
->eps_in
[idx
];
3431 epctrl
= dwc2_readl(hsotg
->regs
+ DIEPCTL(idx
));
3432 if ((epctrl
& DXEPCTL_EPENA
) && hs_ep
->isochronous
&&
3433 dwc2_gadget_target_frame_elapsed(hs_ep
)) {
3434 epctrl
|= DXEPCTL_SNAK
;
3435 epctrl
|= DXEPCTL_EPDIS
;
3436 dwc2_writel(epctrl
, hsotg
->regs
+ DIEPCTL(idx
));
3440 /* Clear interrupt */
3441 dwc2_writel(GINTSTS_INCOMPL_SOIN
, hsotg
->regs
+ GINTSTS
);
3445 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3446 * @hsotg: The device state:
3448 * This interrupt indicates one of the following conditions occurred while
3449 * transmitting an ISOC transaction.
3450 * - Corrupted OUT Token for ISOC EP.
3451 * - Packet not complete in FIFO.
3453 * The following actions will be taken:
3454 * - Determine the EP
3455 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3457 static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg
*hsotg
)
3462 struct dwc2_hsotg_ep
*hs_ep
;
3465 dev_dbg(hsotg
->dev
, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__
);
3467 for (idx
= 1; idx
<= hsotg
->num_of_eps
; idx
++) {
3468 hs_ep
= hsotg
->eps_out
[idx
];
3469 epctrl
= dwc2_readl(hsotg
->regs
+ DOEPCTL(idx
));
3470 if ((epctrl
& DXEPCTL_EPENA
) && hs_ep
->isochronous
&&
3471 dwc2_gadget_target_frame_elapsed(hs_ep
)) {
3472 /* Unmask GOUTNAKEFF interrupt */
3473 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
3474 gintmsk
|= GINTSTS_GOUTNAKEFF
;
3475 dwc2_writel(gintmsk
, hsotg
->regs
+ GINTMSK
);
3477 gintsts
= dwc2_readl(hsotg
->regs
+ GINTSTS
);
3478 if (!(gintsts
& GINTSTS_GOUTNAKEFF
))
3479 __orr32(hsotg
->regs
+ DCTL
, DCTL_SGOUTNAK
);
3483 /* Clear interrupt */
3484 dwc2_writel(GINTSTS_INCOMPL_SOOUT
, hsotg
->regs
+ GINTSTS
);
3488 * dwc2_hsotg_irq - handle device interrupt
3489 * @irq: The IRQ number triggered
3490 * @pw: The pw value when registered the handler.
3492 static irqreturn_t
dwc2_hsotg_irq(int irq
, void *pw
)
3494 struct dwc2_hsotg
*hsotg
= pw
;
3495 int retry_count
= 8;
3499 if (!dwc2_is_device_mode(hsotg
))
3502 spin_lock(&hsotg
->lock
);
3504 gintsts
= dwc2_readl(hsotg
->regs
+ GINTSTS
);
3505 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
3507 dev_dbg(hsotg
->dev
, "%s: %08x %08x (%08x) retry %d\n",
3508 __func__
, gintsts
, gintsts
& gintmsk
, gintmsk
, retry_count
);
3512 if (gintsts
& GINTSTS_RESETDET
) {
3513 dev_dbg(hsotg
->dev
, "%s: USBRstDet\n", __func__
);
3515 dwc2_writel(GINTSTS_RESETDET
, hsotg
->regs
+ GINTSTS
);
3517 /* This event must be used only if controller is suspended */
3518 if (hsotg
->lx_state
== DWC2_L2
) {
3519 dwc2_exit_hibernation(hsotg
, true);
3520 hsotg
->lx_state
= DWC2_L0
;
3524 if (gintsts
& (GINTSTS_USBRST
| GINTSTS_RESETDET
)) {
3525 u32 usb_status
= dwc2_readl(hsotg
->regs
+ GOTGCTL
);
3526 u32 connected
= hsotg
->connected
;
3528 dev_dbg(hsotg
->dev
, "%s: USBRst\n", __func__
);
3529 dev_dbg(hsotg
->dev
, "GNPTXSTS=%08x\n",
3530 dwc2_readl(hsotg
->regs
+ GNPTXSTS
));
3532 dwc2_writel(GINTSTS_USBRST
, hsotg
->regs
+ GINTSTS
);
3534 /* Report disconnection if it is not already done. */
3535 dwc2_hsotg_disconnect(hsotg
);
3537 /* Reset device address to zero */
3538 __bic32(hsotg
->regs
+ DCFG
, DCFG_DEVADDR_MASK
);
3540 if (usb_status
& GOTGCTL_BSESVLD
&& connected
)
3541 dwc2_hsotg_core_init_disconnected(hsotg
, true);
3544 if (gintsts
& GINTSTS_ENUMDONE
) {
3545 dwc2_writel(GINTSTS_ENUMDONE
, hsotg
->regs
+ GINTSTS
);
3547 dwc2_hsotg_irq_enumdone(hsotg
);
3550 if (gintsts
& (GINTSTS_OEPINT
| GINTSTS_IEPINT
)) {
3551 u32 daint
= dwc2_readl(hsotg
->regs
+ DAINT
);
3552 u32 daintmsk
= dwc2_readl(hsotg
->regs
+ DAINTMSK
);
3553 u32 daint_out
, daint_in
;
3557 daint_out
= daint
>> DAINT_OUTEP_SHIFT
;
3558 daint_in
= daint
& ~(daint_out
<< DAINT_OUTEP_SHIFT
);
3560 dev_dbg(hsotg
->dev
, "%s: daint=%08x\n", __func__
, daint
);
3562 for (ep
= 0; ep
< hsotg
->num_of_eps
&& daint_out
;
3563 ep
++, daint_out
>>= 1) {
3565 dwc2_hsotg_epint(hsotg
, ep
, 0);
3568 for (ep
= 0; ep
< hsotg
->num_of_eps
&& daint_in
;
3569 ep
++, daint_in
>>= 1) {
3571 dwc2_hsotg_epint(hsotg
, ep
, 1);
3575 /* check both FIFOs */
3577 if (gintsts
& GINTSTS_NPTXFEMP
) {
3578 dev_dbg(hsotg
->dev
, "NPTxFEmp\n");
3581 * Disable the interrupt to stop it happening again
3582 * unless one of these endpoint routines decides that
3583 * it needs re-enabling
3586 dwc2_hsotg_disable_gsint(hsotg
, GINTSTS_NPTXFEMP
);
3587 dwc2_hsotg_irq_fifoempty(hsotg
, false);
3590 if (gintsts
& GINTSTS_PTXFEMP
) {
3591 dev_dbg(hsotg
->dev
, "PTxFEmp\n");
3593 /* See note in GINTSTS_NPTxFEmp */
3595 dwc2_hsotg_disable_gsint(hsotg
, GINTSTS_PTXFEMP
);
3596 dwc2_hsotg_irq_fifoempty(hsotg
, true);
3599 if (gintsts
& GINTSTS_RXFLVL
) {
3601 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3602 * we need to retry dwc2_hsotg_handle_rx if this is still
3606 dwc2_hsotg_handle_rx(hsotg
);
3609 if (gintsts
& GINTSTS_ERLYSUSP
) {
3610 dev_dbg(hsotg
->dev
, "GINTSTS_ErlySusp\n");
3611 dwc2_writel(GINTSTS_ERLYSUSP
, hsotg
->regs
+ GINTSTS
);
3615 * these next two seem to crop-up occasionally causing the core
3616 * to shutdown the USB transfer, so try clearing them and logging
3620 if (gintsts
& GINTSTS_GOUTNAKEFF
) {
3624 struct dwc2_hsotg_ep
*hs_ep
;
3626 /* Mask this interrupt */
3627 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
3628 gintmsk
&= ~GINTSTS_GOUTNAKEFF
;
3629 dwc2_writel(gintmsk
, hsotg
->regs
+ GINTMSK
);
3631 dev_dbg(hsotg
->dev
, "GOUTNakEff triggered\n");
3632 for (idx
= 1; idx
<= hsotg
->num_of_eps
; idx
++) {
3633 hs_ep
= hsotg
->eps_out
[idx
];
3634 epctrl
= dwc2_readl(hsotg
->regs
+ DOEPCTL(idx
));
3636 if ((epctrl
& DXEPCTL_EPENA
) && hs_ep
->isochronous
) {
3637 epctrl
|= DXEPCTL_SNAK
;
3638 epctrl
|= DXEPCTL_EPDIS
;
3639 dwc2_writel(epctrl
, hsotg
->regs
+ DOEPCTL(idx
));
3643 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3646 if (gintsts
& GINTSTS_GINNAKEFF
) {
3647 dev_info(hsotg
->dev
, "GINNakEff triggered\n");
3649 __orr32(hsotg
->regs
+ DCTL
, DCTL_CGNPINNAK
);
3651 dwc2_hsotg_dump(hsotg
);
3654 if (gintsts
& GINTSTS_INCOMPL_SOIN
)
3655 dwc2_gadget_handle_incomplete_isoc_in(hsotg
);
3657 if (gintsts
& GINTSTS_INCOMPL_SOOUT
)
3658 dwc2_gadget_handle_incomplete_isoc_out(hsotg
);
3661 * if we've had fifo events, we should try and go around the
3662 * loop again to see if there's any point in returning yet.
3665 if (gintsts
& IRQ_RETRY_MASK
&& --retry_count
> 0)
3668 spin_unlock(&hsotg
->lock
);
3673 static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg
*hs_otg
, u32 reg
,
3674 u32 bit
, u32 timeout
)
3678 for (i
= 0; i
< timeout
; i
++) {
3679 if (dwc2_readl(hs_otg
->regs
+ reg
) & bit
)
3687 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg
*hsotg
,
3688 struct dwc2_hsotg_ep
*hs_ep
)
3693 epctrl_reg
= hs_ep
->dir_in
? DIEPCTL(hs_ep
->index
) :
3694 DOEPCTL(hs_ep
->index
);
3695 epint_reg
= hs_ep
->dir_in
? DIEPINT(hs_ep
->index
) :
3696 DOEPINT(hs_ep
->index
);
3698 dev_dbg(hsotg
->dev
, "%s: stopping transfer on %s\n", __func__
,
3701 if (hs_ep
->dir_in
) {
3702 if (hsotg
->dedicated_fifos
|| hs_ep
->periodic
) {
3703 __orr32(hsotg
->regs
+ epctrl_reg
, DXEPCTL_SNAK
);
3704 /* Wait for Nak effect */
3705 if (dwc2_hsotg_wait_bit_set(hsotg
, epint_reg
,
3706 DXEPINT_INEPNAKEFF
, 100))
3707 dev_warn(hsotg
->dev
,
3708 "%s: timeout DIEPINT.NAKEFF\n",
3711 __orr32(hsotg
->regs
+ DCTL
, DCTL_SGNPINNAK
);
3712 /* Wait for Nak effect */
3713 if (dwc2_hsotg_wait_bit_set(hsotg
, GINTSTS
,
3714 GINTSTS_GINNAKEFF
, 100))
3715 dev_warn(hsotg
->dev
,
3716 "%s: timeout GINTSTS.GINNAKEFF\n",
3720 if (!(dwc2_readl(hsotg
->regs
+ GINTSTS
) & GINTSTS_GOUTNAKEFF
))
3721 __orr32(hsotg
->regs
+ DCTL
, DCTL_SGOUTNAK
);
3723 /* Wait for global nak to take effect */
3724 if (dwc2_hsotg_wait_bit_set(hsotg
, GINTSTS
,
3725 GINTSTS_GOUTNAKEFF
, 100))
3726 dev_warn(hsotg
->dev
, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3731 __orr32(hsotg
->regs
+ epctrl_reg
, DXEPCTL_EPDIS
| DXEPCTL_SNAK
);
3733 /* Wait for ep to be disabled */
3734 if (dwc2_hsotg_wait_bit_set(hsotg
, epint_reg
, DXEPINT_EPDISBLD
, 100))
3735 dev_warn(hsotg
->dev
,
3736 "%s: timeout DOEPCTL.EPDisable\n", __func__
);
3738 /* Clear EPDISBLD interrupt */
3739 __orr32(hsotg
->regs
+ epint_reg
, DXEPINT_EPDISBLD
);
3741 if (hs_ep
->dir_in
) {
3742 unsigned short fifo_index
;
3744 if (hsotg
->dedicated_fifos
|| hs_ep
->periodic
)
3745 fifo_index
= hs_ep
->fifo_index
;
3750 dwc2_flush_tx_fifo(hsotg
, fifo_index
);
3752 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3753 if (!hsotg
->dedicated_fifos
&& !hs_ep
->periodic
)
3754 __orr32(hsotg
->regs
+ DCTL
, DCTL_CGNPINNAK
);
3757 /* Remove global NAKs */
3758 __orr32(hsotg
->regs
+ DCTL
, DCTL_CGOUTNAK
);
3763 * dwc2_hsotg_ep_enable - enable the given endpoint
3764 * @ep: The USB endpint to configure
3765 * @desc: The USB endpoint descriptor to configure with.
3767 * This is called from the USB gadget code's usb_ep_enable().
3769 static int dwc2_hsotg_ep_enable(struct usb_ep
*ep
,
3770 const struct usb_endpoint_descriptor
*desc
)
3772 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
3773 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
3774 unsigned long flags
;
3775 unsigned int index
= hs_ep
->index
;
3781 unsigned int dir_in
;
3782 unsigned int i
, val
, size
;
3786 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
3787 __func__
, ep
->name
, desc
->bEndpointAddress
, desc
->bmAttributes
,
3788 desc
->wMaxPacketSize
, desc
->bInterval
);
3790 /* not to be called for EP0 */
3792 dev_err(hsotg
->dev
, "%s: called for EP 0\n", __func__
);
3796 dir_in
= (desc
->bEndpointAddress
& USB_ENDPOINT_DIR_MASK
) ? 1 : 0;
3797 if (dir_in
!= hs_ep
->dir_in
) {
3798 dev_err(hsotg
->dev
, "%s: direction mismatch!\n", __func__
);
3802 mps
= usb_endpoint_maxp(desc
);
3803 mc
= usb_endpoint_maxp_mult(desc
);
3805 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
3807 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
3808 epctrl
= dwc2_readl(hsotg
->regs
+ epctrl_reg
);
3810 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
3811 __func__
, epctrl
, epctrl_reg
);
3813 /* Allocate DMA descriptor chain for non-ctrl endpoints */
3814 if (using_desc_dma(hsotg
) && !hs_ep
->desc_list
) {
3815 hs_ep
->desc_list
= dmam_alloc_coherent(hsotg
->dev
,
3816 MAX_DMA_DESC_NUM_GENERIC
*
3817 sizeof(struct dwc2_dma_desc
),
3818 &hs_ep
->desc_list_dma
, GFP_ATOMIC
);
3819 if (!hs_ep
->desc_list
) {
3825 spin_lock_irqsave(&hsotg
->lock
, flags
);
3827 epctrl
&= ~(DXEPCTL_EPTYPE_MASK
| DXEPCTL_MPS_MASK
);
3828 epctrl
|= DXEPCTL_MPS(mps
);
3831 * mark the endpoint as active, otherwise the core may ignore
3832 * transactions entirely for this endpoint
3834 epctrl
|= DXEPCTL_USBACTEP
;
3836 /* update the endpoint state */
3837 dwc2_hsotg_set_ep_maxpacket(hsotg
, hs_ep
->index
, mps
, mc
, dir_in
);
3839 /* default, set to non-periodic */
3840 hs_ep
->isochronous
= 0;
3841 hs_ep
->periodic
= 0;
3843 hs_ep
->interval
= desc
->bInterval
;
3845 switch (desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
) {
3846 case USB_ENDPOINT_XFER_ISOC
:
3847 epctrl
|= DXEPCTL_EPTYPE_ISO
;
3848 epctrl
|= DXEPCTL_SETEVENFR
;
3849 hs_ep
->isochronous
= 1;
3850 hs_ep
->interval
= 1 << (desc
->bInterval
- 1);
3851 hs_ep
->target_frame
= TARGET_FRAME_INITIAL
;
3852 hs_ep
->isoc_chain_num
= 0;
3853 hs_ep
->next_desc
= 0;
3855 hs_ep
->periodic
= 1;
3856 mask
= dwc2_readl(hsotg
->regs
+ DIEPMSK
);
3857 mask
|= DIEPMSK_NAKMSK
;
3858 dwc2_writel(mask
, hsotg
->regs
+ DIEPMSK
);
3860 mask
= dwc2_readl(hsotg
->regs
+ DOEPMSK
);
3861 mask
|= DOEPMSK_OUTTKNEPDISMSK
;
3862 dwc2_writel(mask
, hsotg
->regs
+ DOEPMSK
);
3866 case USB_ENDPOINT_XFER_BULK
:
3867 epctrl
|= DXEPCTL_EPTYPE_BULK
;
3870 case USB_ENDPOINT_XFER_INT
:
3872 hs_ep
->periodic
= 1;
3874 if (hsotg
->gadget
.speed
== USB_SPEED_HIGH
)
3875 hs_ep
->interval
= 1 << (desc
->bInterval
- 1);
3877 epctrl
|= DXEPCTL_EPTYPE_INTERRUPT
;
3880 case USB_ENDPOINT_XFER_CONTROL
:
3881 epctrl
|= DXEPCTL_EPTYPE_CONTROL
;
3886 * if the hardware has dedicated fifos, we must give each IN EP
3887 * a unique tx-fifo even if it is non-periodic.
3889 if (dir_in
&& hsotg
->dedicated_fifos
) {
3891 u32 fifo_size
= UINT_MAX
;
3893 size
= hs_ep
->ep
.maxpacket
* hs_ep
->mc
;
3894 for (i
= 1; i
< hsotg
->num_of_eps
; ++i
) {
3895 if (hsotg
->fifo_map
& (1 << i
))
3897 val
= dwc2_readl(hsotg
->regs
+ DPTXFSIZN(i
));
3898 val
= (val
>> FIFOSIZE_DEPTH_SHIFT
) * 4;
3901 /* Search for smallest acceptable fifo */
3902 if (val
< fifo_size
) {
3909 "%s: No suitable fifo found\n", __func__
);
3913 hsotg
->fifo_map
|= 1 << fifo_index
;
3914 epctrl
|= DXEPCTL_TXFNUM(fifo_index
);
3915 hs_ep
->fifo_index
= fifo_index
;
3916 hs_ep
->fifo_size
= fifo_size
;
3919 /* for non control endpoints, set PID to D0 */
3920 if (index
&& !hs_ep
->isochronous
)
3921 epctrl
|= DXEPCTL_SETD0PID
;
3923 dev_dbg(hsotg
->dev
, "%s: write DxEPCTL=0x%08x\n",
3926 dwc2_writel(epctrl
, hsotg
->regs
+ epctrl_reg
);
3927 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x\n",
3928 __func__
, dwc2_readl(hsotg
->regs
+ epctrl_reg
));
3930 /* enable the endpoint interrupt */
3931 dwc2_hsotg_ctrl_epint(hsotg
, index
, dir_in
, 1);
3934 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3937 if (ret
&& using_desc_dma(hsotg
) && hs_ep
->desc_list
) {
3938 dmam_free_coherent(hsotg
->dev
, MAX_DMA_DESC_NUM_GENERIC
*
3939 sizeof(struct dwc2_dma_desc
),
3940 hs_ep
->desc_list
, hs_ep
->desc_list_dma
);
3941 hs_ep
->desc_list
= NULL
;
3948 * dwc2_hsotg_ep_disable - disable given endpoint
3949 * @ep: The endpoint to disable.
3951 static int dwc2_hsotg_ep_disable(struct usb_ep
*ep
)
3953 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
3954 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
3955 int dir_in
= hs_ep
->dir_in
;
3956 int index
= hs_ep
->index
;
3957 unsigned long flags
;
3961 dev_dbg(hsotg
->dev
, "%s(ep %p)\n", __func__
, ep
);
3963 if (ep
== &hsotg
->eps_out
[0]->ep
) {
3964 dev_err(hsotg
->dev
, "%s: called for ep0\n", __func__
);
3968 if (hsotg
->op_state
!= OTG_STATE_B_PERIPHERAL
) {
3969 dev_err(hsotg
->dev
, "%s: called in host mode?\n", __func__
);
3973 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
3975 spin_lock_irqsave(&hsotg
->lock
, flags
);
3977 ctrl
= dwc2_readl(hsotg
->regs
+ epctrl_reg
);
3979 if (ctrl
& DXEPCTL_EPENA
)
3980 dwc2_hsotg_ep_stop_xfr(hsotg
, hs_ep
);
3982 ctrl
&= ~DXEPCTL_EPENA
;
3983 ctrl
&= ~DXEPCTL_USBACTEP
;
3984 ctrl
|= DXEPCTL_SNAK
;
3986 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
3987 dwc2_writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
3989 /* disable endpoint interrupts */
3990 dwc2_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 0);
3992 /* terminate all requests with shutdown */
3993 kill_all_requests(hsotg
, hs_ep
, -ESHUTDOWN
);
3995 hsotg
->fifo_map
&= ~(1 << hs_ep
->fifo_index
);
3996 hs_ep
->fifo_index
= 0;
3997 hs_ep
->fifo_size
= 0;
3999 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4004 * on_list - check request is on the given endpoint
4005 * @ep: The endpoint to check.
4006 * @test: The request to test if it is on the endpoint.
4008 static bool on_list(struct dwc2_hsotg_ep
*ep
, struct dwc2_hsotg_req
*test
)
4010 struct dwc2_hsotg_req
*req
, *treq
;
4012 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
4021 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4022 * @ep: The endpoint to dequeue.
4023 * @req: The request to be removed from a queue.
4025 static int dwc2_hsotg_ep_dequeue(struct usb_ep
*ep
, struct usb_request
*req
)
4027 struct dwc2_hsotg_req
*hs_req
= our_req(req
);
4028 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
4029 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
4030 unsigned long flags
;
4032 dev_dbg(hs
->dev
, "ep_dequeue(%p,%p)\n", ep
, req
);
4034 spin_lock_irqsave(&hs
->lock
, flags
);
4036 if (!on_list(hs_ep
, hs_req
)) {
4037 spin_unlock_irqrestore(&hs
->lock
, flags
);
4041 /* Dequeue already started request */
4042 if (req
== &hs_ep
->req
->req
)
4043 dwc2_hsotg_ep_stop_xfr(hs
, hs_ep
);
4045 dwc2_hsotg_complete_request(hs
, hs_ep
, hs_req
, -ECONNRESET
);
4046 spin_unlock_irqrestore(&hs
->lock
, flags
);
4052 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4053 * @ep: The endpoint to set halt.
4054 * @value: Set or unset the halt.
4055 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4056 * the endpoint is busy processing requests.
4058 * We need to stall the endpoint immediately if request comes from set_feature
4059 * protocol command handler.
4061 static int dwc2_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
, bool now
)
4063 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
4064 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
4065 int index
= hs_ep
->index
;
4070 dev_info(hs
->dev
, "%s(ep %p %s, %d)\n", __func__
, ep
, ep
->name
, value
);
4074 dwc2_hsotg_stall_ep0(hs
);
4077 "%s: can't clear halt on ep0\n", __func__
);
4081 if (hs_ep
->isochronous
) {
4082 dev_err(hs
->dev
, "%s is Isochronous Endpoint\n", ep
->name
);
4086 if (!now
&& value
&& !list_empty(&hs_ep
->queue
)) {
4087 dev_dbg(hs
->dev
, "%s request is pending, cannot halt\n",
4092 if (hs_ep
->dir_in
) {
4093 epreg
= DIEPCTL(index
);
4094 epctl
= dwc2_readl(hs
->regs
+ epreg
);
4097 epctl
|= DXEPCTL_STALL
| DXEPCTL_SNAK
;
4098 if (epctl
& DXEPCTL_EPENA
)
4099 epctl
|= DXEPCTL_EPDIS
;
4101 epctl
&= ~DXEPCTL_STALL
;
4102 xfertype
= epctl
& DXEPCTL_EPTYPE_MASK
;
4103 if (xfertype
== DXEPCTL_EPTYPE_BULK
||
4104 xfertype
== DXEPCTL_EPTYPE_INTERRUPT
)
4105 epctl
|= DXEPCTL_SETD0PID
;
4107 dwc2_writel(epctl
, hs
->regs
+ epreg
);
4109 epreg
= DOEPCTL(index
);
4110 epctl
= dwc2_readl(hs
->regs
+ epreg
);
4113 epctl
|= DXEPCTL_STALL
;
4115 epctl
&= ~DXEPCTL_STALL
;
4116 xfertype
= epctl
& DXEPCTL_EPTYPE_MASK
;
4117 if (xfertype
== DXEPCTL_EPTYPE_BULK
||
4118 xfertype
== DXEPCTL_EPTYPE_INTERRUPT
)
4119 epctl
|= DXEPCTL_SETD0PID
;
4121 dwc2_writel(epctl
, hs
->regs
+ epreg
);
4124 hs_ep
->halted
= value
;
4130 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4131 * @ep: The endpoint to set halt.
4132 * @value: Set or unset the halt.
4134 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep
*ep
, int value
)
4136 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
4137 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
4138 unsigned long flags
= 0;
4141 spin_lock_irqsave(&hs
->lock
, flags
);
4142 ret
= dwc2_hsotg_ep_sethalt(ep
, value
, false);
4143 spin_unlock_irqrestore(&hs
->lock
, flags
);
4148 static const struct usb_ep_ops dwc2_hsotg_ep_ops
= {
4149 .enable
= dwc2_hsotg_ep_enable
,
4150 .disable
= dwc2_hsotg_ep_disable
,
4151 .alloc_request
= dwc2_hsotg_ep_alloc_request
,
4152 .free_request
= dwc2_hsotg_ep_free_request
,
4153 .queue
= dwc2_hsotg_ep_queue_lock
,
4154 .dequeue
= dwc2_hsotg_ep_dequeue
,
4155 .set_halt
= dwc2_hsotg_ep_sethalt_lock
,
4156 /* note, don't believe we have any call for the fifo routines */
4160 * dwc2_hsotg_init - initialize the usb core
4161 * @hsotg: The driver state
4163 static void dwc2_hsotg_init(struct dwc2_hsotg
*hsotg
)
4167 /* unmask subset of endpoint interrupts */
4169 dwc2_writel(DIEPMSK_TIMEOUTMSK
| DIEPMSK_AHBERRMSK
|
4170 DIEPMSK_EPDISBLDMSK
| DIEPMSK_XFERCOMPLMSK
,
4171 hsotg
->regs
+ DIEPMSK
);
4173 dwc2_writel(DOEPMSK_SETUPMSK
| DOEPMSK_AHBERRMSK
|
4174 DOEPMSK_EPDISBLDMSK
| DOEPMSK_XFERCOMPLMSK
,
4175 hsotg
->regs
+ DOEPMSK
);
4177 dwc2_writel(0, hsotg
->regs
+ DAINTMSK
);
4179 /* Be in disconnected state until gadget is registered */
4180 __orr32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
4184 dev_dbg(hsotg
->dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4185 dwc2_readl(hsotg
->regs
+ GRXFSIZ
),
4186 dwc2_readl(hsotg
->regs
+ GNPTXFSIZ
));
4188 dwc2_hsotg_init_fifo(hsotg
);
4190 /* keep other bits untouched (so e.g. forced modes are not lost) */
4191 usbcfg
= dwc2_readl(hsotg
->regs
+ GUSBCFG
);
4192 usbcfg
&= ~(GUSBCFG_TOUTCAL_MASK
| GUSBCFG_PHYIF16
| GUSBCFG_SRPCAP
|
4193 GUSBCFG_HNPCAP
| GUSBCFG_USBTRDTIM_MASK
);
4195 /* set the PLL on, remove the HNP/SRP and set the PHY */
4196 trdtim
= (hsotg
->phyif
== GUSBCFG_PHYIF8
) ? 9 : 5;
4197 usbcfg
|= hsotg
->phyif
| GUSBCFG_TOUTCAL(7) |
4198 (trdtim
<< GUSBCFG_USBTRDTIM_SHIFT
);
4199 dwc2_writel(usbcfg
, hsotg
->regs
+ GUSBCFG
);
4201 if (using_dma(hsotg
))
4202 __orr32(hsotg
->regs
+ GAHBCFG
, GAHBCFG_DMA_EN
);
4206 * dwc2_hsotg_udc_start - prepare the udc for work
4207 * @gadget: The usb gadget state
4208 * @driver: The usb gadget driver
4210 * Perform initialization to prepare udc device and driver
4213 static int dwc2_hsotg_udc_start(struct usb_gadget
*gadget
,
4214 struct usb_gadget_driver
*driver
)
4216 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
4217 unsigned long flags
;
4221 pr_err("%s: called with no device\n", __func__
);
4226 dev_err(hsotg
->dev
, "%s: no driver\n", __func__
);
4230 if (driver
->max_speed
< USB_SPEED_FULL
)
4231 dev_err(hsotg
->dev
, "%s: bad speed\n", __func__
);
4233 if (!driver
->setup
) {
4234 dev_err(hsotg
->dev
, "%s: missing entry points\n", __func__
);
4238 WARN_ON(hsotg
->driver
);
4240 driver
->driver
.bus
= NULL
;
4241 hsotg
->driver
= driver
;
4242 hsotg
->gadget
.dev
.of_node
= hsotg
->dev
->of_node
;
4243 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
4245 if (hsotg
->dr_mode
== USB_DR_MODE_PERIPHERAL
) {
4246 ret
= dwc2_lowlevel_hw_enable(hsotg
);
4251 if (!IS_ERR_OR_NULL(hsotg
->uphy
))
4252 otg_set_peripheral(hsotg
->uphy
->otg
, &hsotg
->gadget
);
4254 spin_lock_irqsave(&hsotg
->lock
, flags
);
4255 if (dwc2_hw_is_device(hsotg
)) {
4256 dwc2_hsotg_init(hsotg
);
4257 dwc2_hsotg_core_init_disconnected(hsotg
, false);
4261 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4263 dev_info(hsotg
->dev
, "bound driver %s\n", driver
->driver
.name
);
4268 hsotg
->driver
= NULL
;
4273 * dwc2_hsotg_udc_stop - stop the udc
4274 * @gadget: The usb gadget state
4275 * @driver: The usb gadget driver
4277 * Stop udc hw block and stay tunned for future transmissions
4279 static int dwc2_hsotg_udc_stop(struct usb_gadget
*gadget
)
4281 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
4282 unsigned long flags
= 0;
4288 /* all endpoints should be shutdown */
4289 for (ep
= 1; ep
< hsotg
->num_of_eps
; ep
++) {
4290 if (hsotg
->eps_in
[ep
])
4291 dwc2_hsotg_ep_disable(&hsotg
->eps_in
[ep
]->ep
);
4292 if (hsotg
->eps_out
[ep
])
4293 dwc2_hsotg_ep_disable(&hsotg
->eps_out
[ep
]->ep
);
4296 spin_lock_irqsave(&hsotg
->lock
, flags
);
4298 hsotg
->driver
= NULL
;
4299 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
4302 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4304 if (!IS_ERR_OR_NULL(hsotg
->uphy
))
4305 otg_set_peripheral(hsotg
->uphy
->otg
, NULL
);
4307 if (hsotg
->dr_mode
== USB_DR_MODE_PERIPHERAL
)
4308 dwc2_lowlevel_hw_disable(hsotg
);
4314 * dwc2_hsotg_gadget_getframe - read the frame number
4315 * @gadget: The usb gadget state
4317 * Read the {micro} frame number
4319 static int dwc2_hsotg_gadget_getframe(struct usb_gadget
*gadget
)
4321 return dwc2_hsotg_read_frameno(to_hsotg(gadget
));
4325 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4326 * @gadget: The usb gadget state
4327 * @is_on: Current state of the USB PHY
4329 * Connect/Disconnect the USB PHY pullup
4331 static int dwc2_hsotg_pullup(struct usb_gadget
*gadget
, int is_on
)
4333 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
4334 unsigned long flags
= 0;
4336 dev_dbg(hsotg
->dev
, "%s: is_on: %d op_state: %d\n", __func__
, is_on
,
4339 /* Don't modify pullup state while in host mode */
4340 if (hsotg
->op_state
!= OTG_STATE_B_PERIPHERAL
) {
4341 hsotg
->enabled
= is_on
;
4345 spin_lock_irqsave(&hsotg
->lock
, flags
);
4348 dwc2_hsotg_core_init_disconnected(hsotg
, false);
4349 dwc2_hsotg_core_connect(hsotg
);
4351 dwc2_hsotg_core_disconnect(hsotg
);
4352 dwc2_hsotg_disconnect(hsotg
);
4356 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
4357 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4362 static int dwc2_hsotg_vbus_session(struct usb_gadget
*gadget
, int is_active
)
4364 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
4365 unsigned long flags
;
4367 dev_dbg(hsotg
->dev
, "%s: is_active: %d\n", __func__
, is_active
);
4368 spin_lock_irqsave(&hsotg
->lock
, flags
);
4371 * If controller is hibernated, it must exit from hibernation
4372 * before being initialized / de-initialized
4374 if (hsotg
->lx_state
== DWC2_L2
)
4375 dwc2_exit_hibernation(hsotg
, false);
4378 hsotg
->op_state
= OTG_STATE_B_PERIPHERAL
;
4380 dwc2_hsotg_core_init_disconnected(hsotg
, false);
4382 dwc2_hsotg_core_connect(hsotg
);
4384 dwc2_hsotg_core_disconnect(hsotg
);
4385 dwc2_hsotg_disconnect(hsotg
);
4388 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4393 * dwc2_hsotg_vbus_draw - report bMaxPower field
4394 * @gadget: The usb gadget state
4395 * @mA: Amount of current
4397 * Report how much power the device may consume to the phy.
4399 static int dwc2_hsotg_vbus_draw(struct usb_gadget
*gadget
, unsigned int mA
)
4401 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
4403 if (IS_ERR_OR_NULL(hsotg
->uphy
))
4405 return usb_phy_set_power(hsotg
->uphy
, mA
);
4408 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops
= {
4409 .get_frame
= dwc2_hsotg_gadget_getframe
,
4410 .udc_start
= dwc2_hsotg_udc_start
,
4411 .udc_stop
= dwc2_hsotg_udc_stop
,
4412 .pullup
= dwc2_hsotg_pullup
,
4413 .vbus_session
= dwc2_hsotg_vbus_session
,
4414 .vbus_draw
= dwc2_hsotg_vbus_draw
,
4418 * dwc2_hsotg_initep - initialise a single endpoint
4419 * @hsotg: The device state.
4420 * @hs_ep: The endpoint to be initialised.
4421 * @epnum: The endpoint number
4423 * Initialise the given endpoint (as part of the probe and device state
4424 * creation) to give to the gadget driver. Setup the endpoint name, any
4425 * direction information and other state that may be required.
4427 static void dwc2_hsotg_initep(struct dwc2_hsotg
*hsotg
,
4428 struct dwc2_hsotg_ep
*hs_ep
,
4441 hs_ep
->dir_in
= dir_in
;
4442 hs_ep
->index
= epnum
;
4444 snprintf(hs_ep
->name
, sizeof(hs_ep
->name
), "ep%d%s", epnum
, dir
);
4446 INIT_LIST_HEAD(&hs_ep
->queue
);
4447 INIT_LIST_HEAD(&hs_ep
->ep
.ep_list
);
4449 /* add to the list of endpoints known by the gadget driver */
4451 list_add_tail(&hs_ep
->ep
.ep_list
, &hsotg
->gadget
.ep_list
);
4453 hs_ep
->parent
= hsotg
;
4454 hs_ep
->ep
.name
= hs_ep
->name
;
4456 if (hsotg
->params
.speed
== DWC2_SPEED_PARAM_LOW
)
4457 usb_ep_set_maxpacket_limit(&hs_ep
->ep
, 8);
4459 usb_ep_set_maxpacket_limit(&hs_ep
->ep
,
4460 epnum
? 1024 : EP0_MPS_LIMIT
);
4461 hs_ep
->ep
.ops
= &dwc2_hsotg_ep_ops
;
4464 hs_ep
->ep
.caps
.type_control
= true;
4466 if (hsotg
->params
.speed
!= DWC2_SPEED_PARAM_LOW
) {
4467 hs_ep
->ep
.caps
.type_iso
= true;
4468 hs_ep
->ep
.caps
.type_bulk
= true;
4470 hs_ep
->ep
.caps
.type_int
= true;
4474 hs_ep
->ep
.caps
.dir_in
= true;
4476 hs_ep
->ep
.caps
.dir_out
= true;
4479 * if we're using dma, we need to set the next-endpoint pointer
4480 * to be something valid.
4483 if (using_dma(hsotg
)) {
4484 u32 next
= DXEPCTL_NEXTEP((epnum
+ 1) % 15);
4487 dwc2_writel(next
, hsotg
->regs
+ DIEPCTL(epnum
));
4489 dwc2_writel(next
, hsotg
->regs
+ DOEPCTL(epnum
));
4494 * dwc2_hsotg_hw_cfg - read HW configuration registers
4495 * @param: The device state
4497 * Read the USB core HW configuration registers
4499 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg
*hsotg
)
4505 /* check hardware configuration */
4507 hsotg
->num_of_eps
= hsotg
->hw_params
.num_dev_ep
;
4510 hsotg
->num_of_eps
++;
4512 hsotg
->eps_in
[0] = devm_kzalloc(hsotg
->dev
,
4513 sizeof(struct dwc2_hsotg_ep
),
4515 if (!hsotg
->eps_in
[0])
4517 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4518 hsotg
->eps_out
[0] = hsotg
->eps_in
[0];
4520 cfg
= hsotg
->hw_params
.dev_ep_dirs
;
4521 for (i
= 1, cfg
>>= 2; i
< hsotg
->num_of_eps
; i
++, cfg
>>= 2) {
4523 /* Direction in or both */
4524 if (!(ep_type
& 2)) {
4525 hsotg
->eps_in
[i
] = devm_kzalloc(hsotg
->dev
,
4526 sizeof(struct dwc2_hsotg_ep
), GFP_KERNEL
);
4527 if (!hsotg
->eps_in
[i
])
4530 /* Direction out or both */
4531 if (!(ep_type
& 1)) {
4532 hsotg
->eps_out
[i
] = devm_kzalloc(hsotg
->dev
,
4533 sizeof(struct dwc2_hsotg_ep
), GFP_KERNEL
);
4534 if (!hsotg
->eps_out
[i
])
4539 hsotg
->fifo_mem
= hsotg
->hw_params
.total_fifo_size
;
4540 hsotg
->dedicated_fifos
= hsotg
->hw_params
.en_multiple_tx_fifo
;
4542 dev_info(hsotg
->dev
, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4544 hsotg
->dedicated_fifos
? "dedicated" : "shared",
4550 * dwc2_hsotg_dump - dump state of the udc
4551 * @param: The device state
4553 static void dwc2_hsotg_dump(struct dwc2_hsotg
*hsotg
)
4556 struct device
*dev
= hsotg
->dev
;
4557 void __iomem
*regs
= hsotg
->regs
;
4561 dev_info(dev
, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4562 dwc2_readl(regs
+ DCFG
), dwc2_readl(regs
+ DCTL
),
4563 dwc2_readl(regs
+ DIEPMSK
));
4565 dev_info(dev
, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4566 dwc2_readl(regs
+ GAHBCFG
), dwc2_readl(regs
+ GHWCFG1
));
4568 dev_info(dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4569 dwc2_readl(regs
+ GRXFSIZ
), dwc2_readl(regs
+ GNPTXFSIZ
));
4571 /* show periodic fifo settings */
4573 for (idx
= 1; idx
< hsotg
->num_of_eps
; idx
++) {
4574 val
= dwc2_readl(regs
+ DPTXFSIZN(idx
));
4575 dev_info(dev
, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx
,
4576 val
>> FIFOSIZE_DEPTH_SHIFT
,
4577 val
& FIFOSIZE_STARTADDR_MASK
);
4580 for (idx
= 0; idx
< hsotg
->num_of_eps
; idx
++) {
4582 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx
,
4583 dwc2_readl(regs
+ DIEPCTL(idx
)),
4584 dwc2_readl(regs
+ DIEPTSIZ(idx
)),
4585 dwc2_readl(regs
+ DIEPDMA(idx
)));
4587 val
= dwc2_readl(regs
+ DOEPCTL(idx
));
4589 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4590 idx
, dwc2_readl(regs
+ DOEPCTL(idx
)),
4591 dwc2_readl(regs
+ DOEPTSIZ(idx
)),
4592 dwc2_readl(regs
+ DOEPDMA(idx
)));
4595 dev_info(dev
, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4596 dwc2_readl(regs
+ DVBUSDIS
), dwc2_readl(regs
+ DVBUSPULSE
));
4601 * dwc2_gadget_init - init function for gadget
4602 * @dwc2: The data structure for the DWC2 driver.
4603 * @irq: The IRQ number for the controller.
4605 int dwc2_gadget_init(struct dwc2_hsotg
*hsotg
, int irq
)
4607 struct device
*dev
= hsotg
->dev
;
4611 /* Dump fifo information */
4612 dev_dbg(dev
, "NonPeriodic TXFIFO size: %d\n",
4613 hsotg
->params
.g_np_tx_fifo_size
);
4614 dev_dbg(dev
, "RXFIFO size: %d\n", hsotg
->params
.g_rx_fifo_size
);
4616 hsotg
->gadget
.max_speed
= USB_SPEED_HIGH
;
4617 hsotg
->gadget
.ops
= &dwc2_hsotg_gadget_ops
;
4618 hsotg
->gadget
.name
= dev_name(dev
);
4619 if (hsotg
->dr_mode
== USB_DR_MODE_OTG
)
4620 hsotg
->gadget
.is_otg
= 1;
4621 else if (hsotg
->dr_mode
== USB_DR_MODE_PERIPHERAL
)
4622 hsotg
->op_state
= OTG_STATE_B_PERIPHERAL
;
4624 ret
= dwc2_hsotg_hw_cfg(hsotg
);
4626 dev_err(hsotg
->dev
, "Hardware configuration failed: %d\n", ret
);
4630 hsotg
->ctrl_buff
= devm_kzalloc(hsotg
->dev
,
4631 DWC2_CTRL_BUFF_SIZE
, GFP_KERNEL
);
4632 if (!hsotg
->ctrl_buff
)
4635 hsotg
->ep0_buff
= devm_kzalloc(hsotg
->dev
,
4636 DWC2_CTRL_BUFF_SIZE
, GFP_KERNEL
);
4637 if (!hsotg
->ep0_buff
)
4640 if (using_desc_dma(hsotg
)) {
4641 ret
= dwc2_gadget_alloc_ctrl_desc_chains(hsotg
);
4646 ret
= devm_request_irq(hsotg
->dev
, irq
, dwc2_hsotg_irq
, IRQF_SHARED
,
4647 dev_name(hsotg
->dev
), hsotg
);
4649 dev_err(dev
, "cannot claim IRQ for gadget\n");
4653 /* hsotg->num_of_eps holds number of EPs other than ep0 */
4655 if (hsotg
->num_of_eps
== 0) {
4656 dev_err(dev
, "wrong number of EPs (zero)\n");
4660 /* setup endpoint information */
4662 INIT_LIST_HEAD(&hsotg
->gadget
.ep_list
);
4663 hsotg
->gadget
.ep0
= &hsotg
->eps_out
[0]->ep
;
4665 /* allocate EP0 request */
4667 hsotg
->ctrl_req
= dwc2_hsotg_ep_alloc_request(&hsotg
->eps_out
[0]->ep
,
4669 if (!hsotg
->ctrl_req
) {
4670 dev_err(dev
, "failed to allocate ctrl req\n");
4674 /* initialise the endpoints now the core has been initialised */
4675 for (epnum
= 0; epnum
< hsotg
->num_of_eps
; epnum
++) {
4676 if (hsotg
->eps_in
[epnum
])
4677 dwc2_hsotg_initep(hsotg
, hsotg
->eps_in
[epnum
],
4679 if (hsotg
->eps_out
[epnum
])
4680 dwc2_hsotg_initep(hsotg
, hsotg
->eps_out
[epnum
],
4684 ret
= usb_add_gadget_udc(dev
, &hsotg
->gadget
);
4688 dwc2_hsotg_dump(hsotg
);
4694 * dwc2_hsotg_remove - remove function for hsotg driver
4695 * @pdev: The platform information for the driver
4697 int dwc2_hsotg_remove(struct dwc2_hsotg
*hsotg
)
4699 usb_del_gadget_udc(&hsotg
->gadget
);
4704 int dwc2_hsotg_suspend(struct dwc2_hsotg
*hsotg
)
4706 unsigned long flags
;
4708 if (hsotg
->lx_state
!= DWC2_L0
)
4711 if (hsotg
->driver
) {
4714 dev_info(hsotg
->dev
, "suspending usb gadget %s\n",
4715 hsotg
->driver
->driver
.name
);
4717 spin_lock_irqsave(&hsotg
->lock
, flags
);
4719 dwc2_hsotg_core_disconnect(hsotg
);
4720 dwc2_hsotg_disconnect(hsotg
);
4721 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
4722 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4724 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++) {
4725 if (hsotg
->eps_in
[ep
])
4726 dwc2_hsotg_ep_disable(&hsotg
->eps_in
[ep
]->ep
);
4727 if (hsotg
->eps_out
[ep
])
4728 dwc2_hsotg_ep_disable(&hsotg
->eps_out
[ep
]->ep
);
4735 int dwc2_hsotg_resume(struct dwc2_hsotg
*hsotg
)
4737 unsigned long flags
;
4739 if (hsotg
->lx_state
== DWC2_L2
)
4742 if (hsotg
->driver
) {
4743 dev_info(hsotg
->dev
, "resuming usb gadget %s\n",
4744 hsotg
->driver
->driver
.name
);
4746 spin_lock_irqsave(&hsotg
->lock
, flags
);
4747 dwc2_hsotg_core_init_disconnected(hsotg
, false);
4749 dwc2_hsotg_core_connect(hsotg
);
4750 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4757 * dwc2_backup_device_registers() - Backup controller device registers.
4758 * When suspending usb bus, registers needs to be backuped
4759 * if controller power is disabled once suspended.
4761 * @hsotg: Programming view of the DWC_otg controller
4763 int dwc2_backup_device_registers(struct dwc2_hsotg
*hsotg
)
4765 struct dwc2_dregs_backup
*dr
;
4768 dev_dbg(hsotg
->dev
, "%s\n", __func__
);
4770 /* Backup dev regs */
4771 dr
= &hsotg
->dr_backup
;
4773 dr
->dcfg
= dwc2_readl(hsotg
->regs
+ DCFG
);
4774 dr
->dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
4775 dr
->daintmsk
= dwc2_readl(hsotg
->regs
+ DAINTMSK
);
4776 dr
->diepmsk
= dwc2_readl(hsotg
->regs
+ DIEPMSK
);
4777 dr
->doepmsk
= dwc2_readl(hsotg
->regs
+ DOEPMSK
);
4779 for (i
= 0; i
< hsotg
->num_of_eps
; i
++) {
4781 dr
->diepctl
[i
] = dwc2_readl(hsotg
->regs
+ DIEPCTL(i
));
4783 /* Ensure DATA PID is correctly configured */
4784 if (dr
->diepctl
[i
] & DXEPCTL_DPID
)
4785 dr
->diepctl
[i
] |= DXEPCTL_SETD1PID
;
4787 dr
->diepctl
[i
] |= DXEPCTL_SETD0PID
;
4789 dr
->dieptsiz
[i
] = dwc2_readl(hsotg
->regs
+ DIEPTSIZ(i
));
4790 dr
->diepdma
[i
] = dwc2_readl(hsotg
->regs
+ DIEPDMA(i
));
4792 /* Backup OUT EPs */
4793 dr
->doepctl
[i
] = dwc2_readl(hsotg
->regs
+ DOEPCTL(i
));
4795 /* Ensure DATA PID is correctly configured */
4796 if (dr
->doepctl
[i
] & DXEPCTL_DPID
)
4797 dr
->doepctl
[i
] |= DXEPCTL_SETD1PID
;
4799 dr
->doepctl
[i
] |= DXEPCTL_SETD0PID
;
4801 dr
->doeptsiz
[i
] = dwc2_readl(hsotg
->regs
+ DOEPTSIZ(i
));
4802 dr
->doepdma
[i
] = dwc2_readl(hsotg
->regs
+ DOEPDMA(i
));
4809 * dwc2_restore_device_registers() - Restore controller device registers.
4810 * When resuming usb bus, device registers needs to be restored
4811 * if controller power were disabled.
4813 * @hsotg: Programming view of the DWC_otg controller
4815 int dwc2_restore_device_registers(struct dwc2_hsotg
*hsotg
)
4817 struct dwc2_dregs_backup
*dr
;
4821 dev_dbg(hsotg
->dev
, "%s\n", __func__
);
4823 /* Restore dev regs */
4824 dr
= &hsotg
->dr_backup
;
4826 dev_err(hsotg
->dev
, "%s: no device registers to restore\n",
4832 dwc2_writel(dr
->dcfg
, hsotg
->regs
+ DCFG
);
4833 dwc2_writel(dr
->dctl
, hsotg
->regs
+ DCTL
);
4834 dwc2_writel(dr
->daintmsk
, hsotg
->regs
+ DAINTMSK
);
4835 dwc2_writel(dr
->diepmsk
, hsotg
->regs
+ DIEPMSK
);
4836 dwc2_writel(dr
->doepmsk
, hsotg
->regs
+ DOEPMSK
);
4838 for (i
= 0; i
< hsotg
->num_of_eps
; i
++) {
4839 /* Restore IN EPs */
4840 dwc2_writel(dr
->diepctl
[i
], hsotg
->regs
+ DIEPCTL(i
));
4841 dwc2_writel(dr
->dieptsiz
[i
], hsotg
->regs
+ DIEPTSIZ(i
));
4842 dwc2_writel(dr
->diepdma
[i
], hsotg
->regs
+ DIEPDMA(i
));
4844 /* Restore OUT EPs */
4845 dwc2_writel(dr
->doepctl
[i
], hsotg
->regs
+ DOEPCTL(i
));
4846 dwc2_writel(dr
->doeptsiz
[i
], hsotg
->regs
+ DOEPTSIZ(i
));
4847 dwc2_writel(dr
->doepdma
[i
], hsotg
->regs
+ DOEPDMA(i
));
4850 /* Set the Power-On Programming done bit */
4851 dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
4852 dctl
|= DCTL_PWRONPRGDONE
;
4853 dwc2_writel(dctl
, hsotg
->regs
+ DCTL
);