2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * S3C USB2.0 High-speed / OtG driver
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/debugfs.h>
24 #include <linux/mutex.h>
25 #include <linux/seq_file.h>
26 #include <linux/delay.h>
28 #include <linux/slab.h>
29 #include <linux/clk.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/of_platform.h>
32 #include <linux/phy/phy.h>
34 #include <linux/usb/ch9.h>
35 #include <linux/usb/gadget.h>
36 #include <linux/usb/phy.h>
37 #include <linux/platform_data/s3c-hsotg.h>
42 /* conversion functions */
43 static inline struct s3c_hsotg_req
*our_req(struct usb_request
*req
)
45 return container_of(req
, struct s3c_hsotg_req
, req
);
48 static inline struct s3c_hsotg_ep
*our_ep(struct usb_ep
*ep
)
50 return container_of(ep
, struct s3c_hsotg_ep
, ep
);
53 static inline struct dwc2_hsotg
*to_hsotg(struct usb_gadget
*gadget
)
55 return container_of(gadget
, struct dwc2_hsotg
, gadget
);
58 static inline void __orr32(void __iomem
*ptr
, u32 val
)
60 writel(readl(ptr
) | val
, ptr
);
63 static inline void __bic32(void __iomem
*ptr
, u32 val
)
65 writel(readl(ptr
) & ~val
, ptr
);
68 static inline struct s3c_hsotg_ep
*index_to_ep(struct dwc2_hsotg
*hsotg
,
69 u32 ep_index
, u32 dir_in
)
72 return hsotg
->eps_in
[ep_index
];
74 return hsotg
->eps_out
[ep_index
];
77 /* forward declaration of functions */
78 static void s3c_hsotg_dump(struct dwc2_hsotg
*hsotg
);
81 * using_dma - return the DMA status of the driver.
82 * @hsotg: The driver state.
84 * Return true if we're using DMA.
86 * Currently, we have the DMA support code worked into everywhere
87 * that needs it, but the AMBA DMA implementation in the hardware can
88 * only DMA from 32bit aligned addresses. This means that gadgets such
89 * as the CDC Ethernet cannot work as they often pass packets which are
92 * Unfortunately the choice to use DMA or not is global to the controller
93 * and seems to be only settable when the controller is being put through
94 * a core reset. This means we either need to fix the gadgets to take
95 * account of DMA alignment, or add bounce buffers (yuerk).
97 * g_using_dma is set depending on dts flag.
99 static inline bool using_dma(struct dwc2_hsotg
*hsotg
)
101 return hsotg
->g_using_dma
;
105 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
106 * @hsotg: The device state
107 * @ints: A bitmask of the interrupts to enable
109 static void s3c_hsotg_en_gsint(struct dwc2_hsotg
*hsotg
, u32 ints
)
111 u32 gsintmsk
= readl(hsotg
->regs
+ GINTMSK
);
114 new_gsintmsk
= gsintmsk
| ints
;
116 if (new_gsintmsk
!= gsintmsk
) {
117 dev_dbg(hsotg
->dev
, "gsintmsk now 0x%08x\n", new_gsintmsk
);
118 writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
123 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
124 * @hsotg: The device state
125 * @ints: A bitmask of the interrupts to enable
127 static void s3c_hsotg_disable_gsint(struct dwc2_hsotg
*hsotg
, u32 ints
)
129 u32 gsintmsk
= readl(hsotg
->regs
+ GINTMSK
);
132 new_gsintmsk
= gsintmsk
& ~ints
;
134 if (new_gsintmsk
!= gsintmsk
)
135 writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
139 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
140 * @hsotg: The device state
141 * @ep: The endpoint index
142 * @dir_in: True if direction is in.
143 * @en: The enable value, true to enable
145 * Set or clear the mask for an individual endpoint's interrupt
148 static void s3c_hsotg_ctrl_epint(struct dwc2_hsotg
*hsotg
,
149 unsigned int ep
, unsigned int dir_in
,
159 local_irq_save(flags
);
160 daint
= readl(hsotg
->regs
+ DAINTMSK
);
165 writel(daint
, hsotg
->regs
+ DAINTMSK
);
166 local_irq_restore(flags
);
170 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
171 * @hsotg: The device instance.
173 static void s3c_hsotg_init_fifo(struct dwc2_hsotg
*hsotg
)
181 /* set FIFO sizes to 2048/1024 */
183 writel(2048, hsotg
->regs
+ GRXFSIZ
);
184 writel((2048 << FIFOSIZE_STARTADDR_SHIFT
) |
185 (1024 << FIFOSIZE_DEPTH_SHIFT
), hsotg
->regs
+ GNPTXFSIZ
);
188 * arange all the rest of the TX FIFOs, as some versions of this
189 * block have overlapping default addresses. This also ensures
190 * that if the settings have been changed, then they are set to
194 /* start at the end of the GNPTXFSIZ, rounded up */
198 * Because we have not enough memory to have each TX FIFO of size at
199 * least 3072 bytes (the maximum single packet size), we create four
200 * FIFOs of lenght 1024, and four of length 3072 bytes, and assing
201 * them to endpoints dynamically according to maxpacket size value of
205 /* 256*4=1024 bytes FIFO length */
207 for (ep
= 1; ep
<= 4; ep
++) {
209 val
|= size
<< FIFOSIZE_DEPTH_SHIFT
;
210 WARN_ONCE(addr
+ size
> hsotg
->fifo_mem
,
211 "insufficient fifo memory");
214 writel(val
, hsotg
->regs
+ DPTXFSIZN(ep
));
216 /* 768*4=3072 bytes FIFO length */
218 for (ep
= 5; ep
<= 8; ep
++) {
220 val
|= size
<< FIFOSIZE_DEPTH_SHIFT
;
221 WARN_ONCE(addr
+ size
> hsotg
->fifo_mem
,
222 "insufficient fifo memory");
225 writel(val
, hsotg
->regs
+ DPTXFSIZN(ep
));
229 * according to p428 of the design guide, we need to ensure that
230 * all fifos are flushed before continuing
233 writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH
|
234 GRSTCTL_RXFFLSH
, hsotg
->regs
+ GRSTCTL
);
236 /* wait until the fifos are both flushed */
239 val
= readl(hsotg
->regs
+ GRSTCTL
);
241 if ((val
& (GRSTCTL_TXFFLSH
| GRSTCTL_RXFFLSH
)) == 0)
244 if (--timeout
== 0) {
246 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
253 dev_dbg(hsotg
->dev
, "FIFOs reset, timeout at %d\n", timeout
);
257 * @ep: USB endpoint to allocate request for.
258 * @flags: Allocation flags
260 * Allocate a new USB request structure appropriate for the specified endpoint
262 static struct usb_request
*s3c_hsotg_ep_alloc_request(struct usb_ep
*ep
,
265 struct s3c_hsotg_req
*req
;
267 req
= kzalloc(sizeof(struct s3c_hsotg_req
), flags
);
271 INIT_LIST_HEAD(&req
->queue
);
277 * is_ep_periodic - return true if the endpoint is in periodic mode.
278 * @hs_ep: The endpoint to query.
280 * Returns true if the endpoint is in periodic mode, meaning it is being
281 * used for an Interrupt or ISO transfer.
283 static inline int is_ep_periodic(struct s3c_hsotg_ep
*hs_ep
)
285 return hs_ep
->periodic
;
289 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
290 * @hsotg: The device state.
291 * @hs_ep: The endpoint for the request
292 * @hs_req: The request being processed.
294 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
295 * of a request to ensure the buffer is ready for access by the caller.
297 static void s3c_hsotg_unmap_dma(struct dwc2_hsotg
*hsotg
,
298 struct s3c_hsotg_ep
*hs_ep
,
299 struct s3c_hsotg_req
*hs_req
)
301 struct usb_request
*req
= &hs_req
->req
;
303 /* ignore this if we're not moving any data */
304 if (hs_req
->req
.length
== 0)
307 usb_gadget_unmap_request(&hsotg
->gadget
, req
, hs_ep
->dir_in
);
311 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
312 * @hsotg: The controller state.
313 * @hs_ep: The endpoint we're going to write for.
314 * @hs_req: The request to write data for.
316 * This is called when the TxFIFO has some space in it to hold a new
317 * transmission and we have something to give it. The actual setup of
318 * the data size is done elsewhere, so all we have to do is to actually
321 * The return value is zero if there is more space (or nothing was done)
322 * otherwise -ENOSPC is returned if the FIFO space was used up.
324 * This routine is only needed for PIO
326 static int s3c_hsotg_write_fifo(struct dwc2_hsotg
*hsotg
,
327 struct s3c_hsotg_ep
*hs_ep
,
328 struct s3c_hsotg_req
*hs_req
)
330 bool periodic
= is_ep_periodic(hs_ep
);
331 u32 gnptxsts
= readl(hsotg
->regs
+ GNPTXSTS
);
332 int buf_pos
= hs_req
->req
.actual
;
333 int to_write
= hs_ep
->size_loaded
;
339 to_write
-= (buf_pos
- hs_ep
->last_load
);
341 /* if there's nothing to write, get out early */
345 if (periodic
&& !hsotg
->dedicated_fifos
) {
346 u32 epsize
= readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
351 * work out how much data was loaded so we can calculate
352 * how much data is left in the fifo.
355 size_left
= DXEPTSIZ_XFERSIZE_GET(epsize
);
358 * if shared fifo, we cannot write anything until the
359 * previous data has been completely sent.
361 if (hs_ep
->fifo_load
!= 0) {
362 s3c_hsotg_en_gsint(hsotg
, GINTSTS_PTXFEMP
);
366 dev_dbg(hsotg
->dev
, "%s: left=%d, load=%d, fifo=%d, size %d\n",
368 hs_ep
->size_loaded
, hs_ep
->fifo_load
, hs_ep
->fifo_size
);
370 /* how much of the data has moved */
371 size_done
= hs_ep
->size_loaded
- size_left
;
373 /* how much data is left in the fifo */
374 can_write
= hs_ep
->fifo_load
- size_done
;
375 dev_dbg(hsotg
->dev
, "%s: => can_write1=%d\n",
376 __func__
, can_write
);
378 can_write
= hs_ep
->fifo_size
- can_write
;
379 dev_dbg(hsotg
->dev
, "%s: => can_write2=%d\n",
380 __func__
, can_write
);
382 if (can_write
<= 0) {
383 s3c_hsotg_en_gsint(hsotg
, GINTSTS_PTXFEMP
);
386 } else if (hsotg
->dedicated_fifos
&& hs_ep
->index
!= 0) {
387 can_write
= readl(hsotg
->regs
+ DTXFSTS(hs_ep
->index
));
392 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts
) == 0) {
394 "%s: no queue slots available (0x%08x)\n",
397 s3c_hsotg_en_gsint(hsotg
, GINTSTS_NPTXFEMP
);
401 can_write
= GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts
);
402 can_write
*= 4; /* fifo size is in 32bit quantities. */
405 max_transfer
= hs_ep
->ep
.maxpacket
* hs_ep
->mc
;
407 dev_dbg(hsotg
->dev
, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
408 __func__
, gnptxsts
, can_write
, to_write
, max_transfer
);
411 * limit to 512 bytes of data, it seems at least on the non-periodic
412 * FIFO, requests of >512 cause the endpoint to get stuck with a
413 * fragment of the end of the transfer in it.
415 if (can_write
> 512 && !periodic
)
419 * limit the write to one max-packet size worth of data, but allow
420 * the transfer to return that it did not run out of fifo space
423 if (to_write
> max_transfer
) {
424 to_write
= max_transfer
;
426 /* it's needed only when we do not use dedicated fifos */
427 if (!hsotg
->dedicated_fifos
)
428 s3c_hsotg_en_gsint(hsotg
,
429 periodic
? GINTSTS_PTXFEMP
:
433 /* see if we can write data */
435 if (to_write
> can_write
) {
436 to_write
= can_write
;
437 pkt_round
= to_write
% max_transfer
;
440 * Round the write down to an
441 * exact number of packets.
443 * Note, we do not currently check to see if we can ever
444 * write a full packet or not to the FIFO.
448 to_write
-= pkt_round
;
451 * enable correct FIFO interrupt to alert us when there
455 /* it's needed only when we do not use dedicated fifos */
456 if (!hsotg
->dedicated_fifos
)
457 s3c_hsotg_en_gsint(hsotg
,
458 periodic
? GINTSTS_PTXFEMP
:
462 dev_dbg(hsotg
->dev
, "write %d/%d, can_write %d, done %d\n",
463 to_write
, hs_req
->req
.length
, can_write
, buf_pos
);
468 hs_req
->req
.actual
= buf_pos
+ to_write
;
469 hs_ep
->total_data
+= to_write
;
472 hs_ep
->fifo_load
+= to_write
;
474 to_write
= DIV_ROUND_UP(to_write
, 4);
475 data
= hs_req
->req
.buf
+ buf_pos
;
477 iowrite32_rep(hsotg
->regs
+ EPFIFO(hs_ep
->index
), data
, to_write
);
479 return (to_write
>= can_write
) ? -ENOSPC
: 0;
483 * get_ep_limit - get the maximum data legnth for this endpoint
484 * @hs_ep: The endpoint
486 * Return the maximum data that can be queued in one go on a given endpoint
487 * so that transfers that are too long can be split.
489 static unsigned get_ep_limit(struct s3c_hsotg_ep
*hs_ep
)
491 int index
= hs_ep
->index
;
496 maxsize
= DXEPTSIZ_XFERSIZE_LIMIT
+ 1;
497 maxpkt
= DXEPTSIZ_PKTCNT_LIMIT
+ 1;
501 maxpkt
= DIEPTSIZ0_PKTCNT_LIMIT
+ 1;
506 /* we made the constant loading easier above by using +1 */
511 * constrain by packet count if maxpkts*pktsize is greater
512 * than the length register size.
515 if ((maxpkt
* hs_ep
->ep
.maxpacket
) < maxsize
)
516 maxsize
= maxpkt
* hs_ep
->ep
.maxpacket
;
522 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
523 * @hsotg: The controller state.
524 * @hs_ep: The endpoint to process a request for
525 * @hs_req: The request to start.
526 * @continuing: True if we are doing more for the current request.
528 * Start the given request running by setting the endpoint registers
529 * appropriately, and writing any data to the FIFOs.
531 static void s3c_hsotg_start_req(struct dwc2_hsotg
*hsotg
,
532 struct s3c_hsotg_ep
*hs_ep
,
533 struct s3c_hsotg_req
*hs_req
,
536 struct usb_request
*ureq
= &hs_req
->req
;
537 int index
= hs_ep
->index
;
538 int dir_in
= hs_ep
->dir_in
;
548 if (hs_ep
->req
&& !continuing
) {
549 dev_err(hsotg
->dev
, "%s: active request\n", __func__
);
552 } else if (hs_ep
->req
!= hs_req
&& continuing
) {
554 "%s: continue different req\n", __func__
);
560 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
561 epsize_reg
= dir_in
? DIEPTSIZ(index
) : DOEPTSIZ(index
);
563 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
564 __func__
, readl(hsotg
->regs
+ epctrl_reg
), index
,
565 hs_ep
->dir_in
? "in" : "out");
567 /* If endpoint is stalled, we will restart request later */
568 ctrl
= readl(hsotg
->regs
+ epctrl_reg
);
570 if (ctrl
& DXEPCTL_STALL
) {
571 dev_warn(hsotg
->dev
, "%s: ep%d is stalled\n", __func__
, index
);
575 length
= ureq
->length
- ureq
->actual
;
576 dev_dbg(hsotg
->dev
, "ureq->length:%d ureq->actual:%d\n",
577 ureq
->length
, ureq
->actual
);
580 "REQ buf %p len %d dma %pad noi=%d zp=%d snok=%d\n",
581 ureq
->buf
, length
, &ureq
->dma
,
582 ureq
->no_interrupt
, ureq
->zero
, ureq
->short_not_ok
);
584 maxreq
= get_ep_limit(hs_ep
);
585 if (length
> maxreq
) {
586 int round
= maxreq
% hs_ep
->ep
.maxpacket
;
588 dev_dbg(hsotg
->dev
, "%s: length %d, max-req %d, r %d\n",
589 __func__
, length
, maxreq
, round
);
591 /* round down to multiple of packets */
599 packets
= DIV_ROUND_UP(length
, hs_ep
->ep
.maxpacket
);
601 packets
= 1; /* send one packet if length is zero. */
603 if (hs_ep
->isochronous
&& length
> (hs_ep
->mc
* hs_ep
->ep
.maxpacket
)) {
604 dev_err(hsotg
->dev
, "req length > maxpacket*mc\n");
608 if (dir_in
&& index
!= 0)
609 if (hs_ep
->isochronous
)
610 epsize
= DXEPTSIZ_MC(packets
);
612 epsize
= DXEPTSIZ_MC(1);
616 if (index
!= 0 && ureq
->zero
) {
618 * test for the packets being exactly right for the
622 if (length
== (packets
* hs_ep
->ep
.maxpacket
))
626 epsize
|= DXEPTSIZ_PKTCNT(packets
);
627 epsize
|= DXEPTSIZ_XFERSIZE(length
);
629 dev_dbg(hsotg
->dev
, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
630 __func__
, packets
, length
, ureq
->length
, epsize
, epsize_reg
);
632 /* store the request as the current one we're doing */
635 /* write size / packets */
636 writel(epsize
, hsotg
->regs
+ epsize_reg
);
638 if (using_dma(hsotg
) && !continuing
) {
639 unsigned int dma_reg
;
642 * write DMA address to control register, buffer already
643 * synced by s3c_hsotg_ep_queue().
646 dma_reg
= dir_in
? DIEPDMA(index
) : DOEPDMA(index
);
647 writel(ureq
->dma
, hsotg
->regs
+ dma_reg
);
649 dev_dbg(hsotg
->dev
, "%s: %pad => 0x%08x\n",
650 __func__
, &ureq
->dma
, dma_reg
);
653 ctrl
|= DXEPCTL_EPENA
; /* ensure ep enabled */
654 ctrl
|= DXEPCTL_USBACTEP
;
656 dev_dbg(hsotg
->dev
, "setup req:%d\n", hsotg
->setup
);
658 /* For Setup request do not clear NAK */
659 if (hsotg
->setup
&& index
== 0)
662 ctrl
|= DXEPCTL_CNAK
; /* clear NAK set by core */
665 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
666 writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
669 * set these, it seems that DMA support increments past the end
670 * of the packet buffer so we need to calculate the length from
673 hs_ep
->size_loaded
= length
;
674 hs_ep
->last_load
= ureq
->actual
;
676 if (dir_in
&& !using_dma(hsotg
)) {
677 /* set these anyway, we may need them for non-periodic in */
678 hs_ep
->fifo_load
= 0;
680 s3c_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
684 * clear the INTknTXFEmpMsk when we start request, more as a aide
685 * to debugging to see what is going on.
688 writel(DIEPMSK_INTKNTXFEMPMSK
,
689 hsotg
->regs
+ DIEPINT(index
));
692 * Note, trying to clear the NAK here causes problems with transmit
693 * on the S3C6400 ending up with the TXFIFO becoming full.
696 /* check ep is enabled */
697 if (!(readl(hsotg
->regs
+ epctrl_reg
) & DXEPCTL_EPENA
))
699 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
700 index
, readl(hsotg
->regs
+ epctrl_reg
));
702 dev_dbg(hsotg
->dev
, "%s: DXEPCTL=0x%08x\n",
703 __func__
, readl(hsotg
->regs
+ epctrl_reg
));
705 /* enable ep interrupts */
706 s3c_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 1);
710 * s3c_hsotg_map_dma - map the DMA memory being used for the request
711 * @hsotg: The device state.
712 * @hs_ep: The endpoint the request is on.
713 * @req: The request being processed.
715 * We've been asked to queue a request, so ensure that the memory buffer
716 * is correctly setup for DMA. If we've been passed an extant DMA address
717 * then ensure the buffer has been synced to memory. If our buffer has no
718 * DMA memory, then we map the memory and mark our request to allow us to
719 * cleanup on completion.
721 static int s3c_hsotg_map_dma(struct dwc2_hsotg
*hsotg
,
722 struct s3c_hsotg_ep
*hs_ep
,
723 struct usb_request
*req
)
725 struct s3c_hsotg_req
*hs_req
= our_req(req
);
728 /* if the length is zero, ignore the DMA data */
729 if (hs_req
->req
.length
== 0)
732 ret
= usb_gadget_map_request(&hsotg
->gadget
, req
, hs_ep
->dir_in
);
739 dev_err(hsotg
->dev
, "%s: failed to map buffer %p, %d bytes\n",
740 __func__
, req
->buf
, req
->length
);
745 static int s3c_hsotg_ep_queue(struct usb_ep
*ep
, struct usb_request
*req
,
748 struct s3c_hsotg_req
*hs_req
= our_req(req
);
749 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
750 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
753 dev_dbg(hs
->dev
, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
754 ep
->name
, req
, req
->length
, req
->buf
, req
->no_interrupt
,
755 req
->zero
, req
->short_not_ok
);
757 /* initialise status of the request */
758 INIT_LIST_HEAD(&hs_req
->queue
);
760 req
->status
= -EINPROGRESS
;
762 /* if we're using DMA, sync the buffers as necessary */
764 int ret
= s3c_hsotg_map_dma(hs
, hs_ep
, req
);
769 first
= list_empty(&hs_ep
->queue
);
770 list_add_tail(&hs_req
->queue
, &hs_ep
->queue
);
773 s3c_hsotg_start_req(hs
, hs_ep
, hs_req
, false);
778 static int s3c_hsotg_ep_queue_lock(struct usb_ep
*ep
, struct usb_request
*req
,
781 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
782 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
783 unsigned long flags
= 0;
786 spin_lock_irqsave(&hs
->lock
, flags
);
787 ret
= s3c_hsotg_ep_queue(ep
, req
, gfp_flags
);
788 spin_unlock_irqrestore(&hs
->lock
, flags
);
793 static void s3c_hsotg_ep_free_request(struct usb_ep
*ep
,
794 struct usb_request
*req
)
796 struct s3c_hsotg_req
*hs_req
= our_req(req
);
802 * s3c_hsotg_complete_oursetup - setup completion callback
803 * @ep: The endpoint the request was on.
804 * @req: The request completed.
806 * Called on completion of any requests the driver itself
807 * submitted that need cleaning up.
809 static void s3c_hsotg_complete_oursetup(struct usb_ep
*ep
,
810 struct usb_request
*req
)
812 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
813 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
815 dev_dbg(hsotg
->dev
, "%s: ep %p, req %p\n", __func__
, ep
, req
);
817 s3c_hsotg_ep_free_request(ep
, req
);
821 * ep_from_windex - convert control wIndex value to endpoint
822 * @hsotg: The driver state.
823 * @windex: The control request wIndex field (in host order).
825 * Convert the given wIndex into a pointer to an driver endpoint
826 * structure, or return NULL if it is not a valid endpoint.
828 static struct s3c_hsotg_ep
*ep_from_windex(struct dwc2_hsotg
*hsotg
,
831 struct s3c_hsotg_ep
*ep
;
832 int dir
= (windex
& USB_DIR_IN
) ? 1 : 0;
833 int idx
= windex
& 0x7F;
838 if (idx
> hsotg
->num_of_eps
)
841 ep
= index_to_ep(hsotg
, idx
, dir
);
843 if (idx
&& ep
->dir_in
!= dir
)
850 * s3c_hsotg_send_reply - send reply to control request
851 * @hsotg: The device state
853 * @buff: Buffer for request
854 * @length: Length of reply.
856 * Create a request and queue it on the given endpoint. This is useful as
857 * an internal method of sending replies to certain control requests, etc.
859 static int s3c_hsotg_send_reply(struct dwc2_hsotg
*hsotg
,
860 struct s3c_hsotg_ep
*ep
,
864 struct usb_request
*req
;
867 dev_dbg(hsotg
->dev
, "%s: buff %p, len %d\n", __func__
, buff
, length
);
869 req
= s3c_hsotg_ep_alloc_request(&ep
->ep
, GFP_ATOMIC
);
870 hsotg
->ep0_reply
= req
;
872 dev_warn(hsotg
->dev
, "%s: cannot alloc req\n", __func__
);
876 req
->buf
= hsotg
->ep0_buff
;
877 req
->length
= length
;
878 req
->zero
= 1; /* always do zero-length final transfer */
879 req
->complete
= s3c_hsotg_complete_oursetup
;
882 memcpy(req
->buf
, buff
, length
);
886 ret
= s3c_hsotg_ep_queue(&ep
->ep
, req
, GFP_ATOMIC
);
888 dev_warn(hsotg
->dev
, "%s: cannot queue req\n", __func__
);
896 * s3c_hsotg_process_req_status - process request GET_STATUS
897 * @hsotg: The device state
898 * @ctrl: USB control request
900 static int s3c_hsotg_process_req_status(struct dwc2_hsotg
*hsotg
,
901 struct usb_ctrlrequest
*ctrl
)
903 struct s3c_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
904 struct s3c_hsotg_ep
*ep
;
908 dev_dbg(hsotg
->dev
, "%s: USB_REQ_GET_STATUS\n", __func__
);
911 dev_warn(hsotg
->dev
, "%s: direction out?\n", __func__
);
915 switch (ctrl
->bRequestType
& USB_RECIP_MASK
) {
916 case USB_RECIP_DEVICE
:
917 reply
= cpu_to_le16(0); /* bit 0 => self powered,
918 * bit 1 => remote wakeup */
921 case USB_RECIP_INTERFACE
:
922 /* currently, the data result should be zero */
923 reply
= cpu_to_le16(0);
926 case USB_RECIP_ENDPOINT
:
927 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
931 reply
= cpu_to_le16(ep
->halted
? 1 : 0);
938 if (le16_to_cpu(ctrl
->wLength
) != 2)
941 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, &reply
, 2);
943 dev_err(hsotg
->dev
, "%s: failed to send reply\n", __func__
);
950 static int s3c_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
);
953 * get_ep_head - return the first request on the endpoint
954 * @hs_ep: The controller endpoint to get
956 * Get the first request on the endpoint.
958 static struct s3c_hsotg_req
*get_ep_head(struct s3c_hsotg_ep
*hs_ep
)
960 if (list_empty(&hs_ep
->queue
))
963 return list_first_entry(&hs_ep
->queue
, struct s3c_hsotg_req
, queue
);
967 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
968 * @hsotg: The device state
969 * @ctrl: USB control request
971 static int s3c_hsotg_process_req_feature(struct dwc2_hsotg
*hsotg
,
972 struct usb_ctrlrequest
*ctrl
)
974 struct s3c_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
975 struct s3c_hsotg_req
*hs_req
;
977 bool set
= (ctrl
->bRequest
== USB_REQ_SET_FEATURE
);
978 struct s3c_hsotg_ep
*ep
;
982 dev_dbg(hsotg
->dev
, "%s: %s_FEATURE\n",
983 __func__
, set
? "SET" : "CLEAR");
985 if (ctrl
->bRequestType
== USB_RECIP_ENDPOINT
) {
986 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
988 dev_dbg(hsotg
->dev
, "%s: no endpoint for 0x%04x\n",
989 __func__
, le16_to_cpu(ctrl
->wIndex
));
993 switch (le16_to_cpu(ctrl
->wValue
)) {
994 case USB_ENDPOINT_HALT
:
997 s3c_hsotg_ep_sethalt(&ep
->ep
, set
);
999 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1002 "%s: failed to send reply\n", __func__
);
1007 * we have to complete all requests for ep if it was
1008 * halted, and the halt was cleared by CLEAR_FEATURE
1011 if (!set
&& halted
) {
1013 * If we have request in progress,
1019 list_del_init(&hs_req
->queue
);
1020 usb_gadget_giveback_request(&ep
->ep
,
1024 /* If we have pending request, then start it */
1025 restart
= !list_empty(&ep
->queue
);
1027 hs_req
= get_ep_head(ep
);
1028 s3c_hsotg_start_req(hsotg
, ep
,
1039 return -ENOENT
; /* currently only deal with endpoint */
1044 static void s3c_hsotg_enqueue_setup(struct dwc2_hsotg
*hsotg
);
1047 * s3c_hsotg_stall_ep0 - stall ep0
1048 * @hsotg: The device state
1050 * Set stall for ep0 as response for setup request.
1052 static void s3c_hsotg_stall_ep0(struct dwc2_hsotg
*hsotg
)
1054 struct s3c_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
1058 dev_dbg(hsotg
->dev
, "ep0 stall (dir=%d)\n", ep0
->dir_in
);
1059 reg
= (ep0
->dir_in
) ? DIEPCTL0
: DOEPCTL0
;
1062 * DxEPCTL_Stall will be cleared by EP once it has
1063 * taken effect, so no need to clear later.
1066 ctrl
= readl(hsotg
->regs
+ reg
);
1067 ctrl
|= DXEPCTL_STALL
;
1068 ctrl
|= DXEPCTL_CNAK
;
1069 writel(ctrl
, hsotg
->regs
+ reg
);
1072 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1073 ctrl
, reg
, readl(hsotg
->regs
+ reg
));
1076 * complete won't be called, so we enqueue
1077 * setup request here
1079 s3c_hsotg_enqueue_setup(hsotg
);
1083 * s3c_hsotg_process_control - process a control request
1084 * @hsotg: The device state
1085 * @ctrl: The control request received
1087 * The controller has received the SETUP phase of a control request, and
1088 * needs to work out what to do next (and whether to pass it on to the
1091 static void s3c_hsotg_process_control(struct dwc2_hsotg
*hsotg
,
1092 struct usb_ctrlrequest
*ctrl
)
1094 struct s3c_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
1100 dev_dbg(hsotg
->dev
, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1101 ctrl
->bRequest
, ctrl
->bRequestType
,
1102 ctrl
->wValue
, ctrl
->wLength
);
1105 * record the direction of the request, for later use when enquing
1109 ep0
->dir_in
= (ctrl
->bRequestType
& USB_DIR_IN
) ? 1 : 0;
1110 dev_dbg(hsotg
->dev
, "ctrl: dir_in=%d\n", ep0
->dir_in
);
1113 * if we've no data with this request, then the last part of the
1114 * transaction is going to implicitly be IN.
1116 if (ctrl
->wLength
== 0)
1119 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
) {
1120 switch (ctrl
->bRequest
) {
1121 case USB_REQ_SET_ADDRESS
:
1122 dcfg
= readl(hsotg
->regs
+ DCFG
);
1123 dcfg
&= ~DCFG_DEVADDR_MASK
;
1124 dcfg
|= (le16_to_cpu(ctrl
->wValue
) <<
1125 DCFG_DEVADDR_SHIFT
) & DCFG_DEVADDR_MASK
;
1126 writel(dcfg
, hsotg
->regs
+ DCFG
);
1128 dev_info(hsotg
->dev
, "new address %d\n", ctrl
->wValue
);
1130 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1133 case USB_REQ_GET_STATUS
:
1134 ret
= s3c_hsotg_process_req_status(hsotg
, ctrl
);
1137 case USB_REQ_CLEAR_FEATURE
:
1138 case USB_REQ_SET_FEATURE
:
1139 ret
= s3c_hsotg_process_req_feature(hsotg
, ctrl
);
1144 /* as a fallback, try delivering it to the driver to deal with */
1146 if (ret
== 0 && hsotg
->driver
) {
1147 spin_unlock(&hsotg
->lock
);
1148 ret
= hsotg
->driver
->setup(&hsotg
->gadget
, ctrl
);
1149 spin_lock(&hsotg
->lock
);
1151 dev_dbg(hsotg
->dev
, "driver->setup() ret %d\n", ret
);
1155 * the request is either unhandlable, or is not formatted correctly
1156 * so respond with a STALL for the status stage to indicate failure.
1160 s3c_hsotg_stall_ep0(hsotg
);
1164 * s3c_hsotg_complete_setup - completion of a setup transfer
1165 * @ep: The endpoint the request was on.
1166 * @req: The request completed.
1168 * Called on completion of any requests the driver itself submitted for
1171 static void s3c_hsotg_complete_setup(struct usb_ep
*ep
,
1172 struct usb_request
*req
)
1174 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
1175 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
1177 if (req
->status
< 0) {
1178 dev_dbg(hsotg
->dev
, "%s: failed %d\n", __func__
, req
->status
);
1182 spin_lock(&hsotg
->lock
);
1183 if (req
->actual
== 0)
1184 s3c_hsotg_enqueue_setup(hsotg
);
1186 s3c_hsotg_process_control(hsotg
, req
->buf
);
1187 spin_unlock(&hsotg
->lock
);
1191 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1192 * @hsotg: The device state.
1194 * Enqueue a request on EP0 if necessary to received any SETUP packets
1195 * received from the host.
1197 static void s3c_hsotg_enqueue_setup(struct dwc2_hsotg
*hsotg
)
1199 struct usb_request
*req
= hsotg
->ctrl_req
;
1200 struct s3c_hsotg_req
*hs_req
= our_req(req
);
1203 dev_dbg(hsotg
->dev
, "%s: queueing setup request\n", __func__
);
1207 req
->buf
= hsotg
->ctrl_buff
;
1208 req
->complete
= s3c_hsotg_complete_setup
;
1210 if (!list_empty(&hs_req
->queue
)) {
1211 dev_dbg(hsotg
->dev
, "%s already queued???\n", __func__
);
1215 hsotg
->eps_out
[0]->dir_in
= 0;
1217 ret
= s3c_hsotg_ep_queue(&hsotg
->eps_out
[0]->ep
, req
, GFP_ATOMIC
);
1219 dev_err(hsotg
->dev
, "%s: failed queue (%d)\n", __func__
, ret
);
1221 * Don't think there's much we can do other than watch the
1228 * s3c_hsotg_complete_request - complete a request given to us
1229 * @hsotg: The device state.
1230 * @hs_ep: The endpoint the request was on.
1231 * @hs_req: The request to complete.
1232 * @result: The result code (0 => Ok, otherwise errno)
1234 * The given request has finished, so call the necessary completion
1235 * if it has one and then look to see if we can start a new request
1238 * Note, expects the ep to already be locked as appropriate.
1240 static void s3c_hsotg_complete_request(struct dwc2_hsotg
*hsotg
,
1241 struct s3c_hsotg_ep
*hs_ep
,
1242 struct s3c_hsotg_req
*hs_req
,
1248 dev_dbg(hsotg
->dev
, "%s: nothing to complete?\n", __func__
);
1252 dev_dbg(hsotg
->dev
, "complete: ep %p %s, req %p, %d => %p\n",
1253 hs_ep
, hs_ep
->ep
.name
, hs_req
, result
, hs_req
->req
.complete
);
1256 * only replace the status if we've not already set an error
1257 * from a previous transaction
1260 if (hs_req
->req
.status
== -EINPROGRESS
)
1261 hs_req
->req
.status
= result
;
1264 list_del_init(&hs_req
->queue
);
1266 if (using_dma(hsotg
))
1267 s3c_hsotg_unmap_dma(hsotg
, hs_ep
, hs_req
);
1270 * call the complete request with the locks off, just in case the
1271 * request tries to queue more work for this endpoint.
1274 if (hs_req
->req
.complete
) {
1275 spin_unlock(&hsotg
->lock
);
1276 usb_gadget_giveback_request(&hs_ep
->ep
, &hs_req
->req
);
1277 spin_lock(&hsotg
->lock
);
1281 * Look to see if there is anything else to do. Note, the completion
1282 * of the previous request may have caused a new request to be started
1283 * so be careful when doing this.
1286 if (!hs_ep
->req
&& result
>= 0) {
1287 restart
= !list_empty(&hs_ep
->queue
);
1289 hs_req
= get_ep_head(hs_ep
);
1290 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, false);
1296 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1297 * @hsotg: The device state.
1298 * @ep_idx: The endpoint index for the data
1299 * @size: The size of data in the fifo, in bytes
1301 * The FIFO status shows there is data to read from the FIFO for a given
1302 * endpoint, so sort out whether we need to read the data into a request
1303 * that has been made for that endpoint.
1305 static void s3c_hsotg_rx_data(struct dwc2_hsotg
*hsotg
, int ep_idx
, int size
)
1307 struct s3c_hsotg_ep
*hs_ep
= hsotg
->eps_out
[ep_idx
];
1308 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1309 void __iomem
*fifo
= hsotg
->regs
+ EPFIFO(ep_idx
);
1316 u32 epctl
= readl(hsotg
->regs
+ DOEPCTL(ep_idx
));
1320 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
1321 __func__
, size
, ep_idx
, epctl
);
1323 /* dump the data from the FIFO, we've nothing we can do */
1324 for (ptr
= 0; ptr
< size
; ptr
+= 4)
1331 read_ptr
= hs_req
->req
.actual
;
1332 max_req
= hs_req
->req
.length
- read_ptr
;
1334 dev_dbg(hsotg
->dev
, "%s: read %d/%d, done %d/%d\n",
1335 __func__
, to_read
, max_req
, read_ptr
, hs_req
->req
.length
);
1337 if (to_read
> max_req
) {
1339 * more data appeared than we where willing
1340 * to deal with in this request.
1343 /* currently we don't deal this */
1347 hs_ep
->total_data
+= to_read
;
1348 hs_req
->req
.actual
+= to_read
;
1349 to_read
= DIV_ROUND_UP(to_read
, 4);
1352 * note, we might over-write the buffer end by 3 bytes depending on
1353 * alignment of the data.
1355 ioread32_rep(fifo
, hs_req
->req
.buf
+ read_ptr
, to_read
);
1359 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1360 * @hsotg: The device instance
1361 * @req: The request currently on this endpoint
1363 * Generate a zero-length IN packet request for terminating a SETUP
1366 * Note, since we don't write any data to the TxFIFO, then it is
1367 * currently believed that we do not need to wait for any space in
1370 static void s3c_hsotg_send_zlp(struct dwc2_hsotg
*hsotg
,
1371 struct s3c_hsotg_req
*req
)
1376 dev_warn(hsotg
->dev
, "%s: no request?\n", __func__
);
1380 if (req
->req
.length
== 0) {
1381 hsotg
->eps_out
[0]->sent_zlp
= 1;
1382 s3c_hsotg_enqueue_setup(hsotg
);
1386 /* eps_out[0] is used in both directions */
1387 hsotg
->eps_out
[0]->dir_in
= 1;
1388 hsotg
->eps_out
[0]->sent_zlp
= 1;
1390 dev_dbg(hsotg
->dev
, "sending zero-length packet\n");
1392 /* issue a zero-sized packet to terminate this */
1393 writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1394 DXEPTSIZ_XFERSIZE(0), hsotg
->regs
+ DIEPTSIZ(0));
1396 ctrl
= readl(hsotg
->regs
+ DIEPCTL0
);
1397 ctrl
|= DXEPCTL_CNAK
; /* clear NAK set by core */
1398 ctrl
|= DXEPCTL_EPENA
; /* ensure ep enabled */
1399 ctrl
|= DXEPCTL_USBACTEP
;
1400 writel(ctrl
, hsotg
->regs
+ DIEPCTL0
);
1404 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1405 * @hsotg: The device instance
1406 * @epnum: The endpoint received from
1407 * @was_setup: Set if processing a SetupDone event.
1409 * The RXFIFO has delivered an OutDone event, which means that the data
1410 * transfer for an OUT endpoint has been completed, either by a short
1411 * packet or by the finish of a transfer.
1413 static void s3c_hsotg_handle_outdone(struct dwc2_hsotg
*hsotg
,
1414 int epnum
, bool was_setup
)
1416 u32 epsize
= readl(hsotg
->regs
+ DOEPTSIZ(epnum
));
1417 struct s3c_hsotg_ep
*hs_ep
= hsotg
->eps_out
[epnum
];
1418 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1419 struct usb_request
*req
= &hs_req
->req
;
1420 unsigned size_left
= DXEPTSIZ_XFERSIZE_GET(epsize
);
1424 dev_dbg(hsotg
->dev
, "%s: no request active\n", __func__
);
1428 if (using_dma(hsotg
)) {
1432 * Calculate the size of the transfer by checking how much
1433 * is left in the endpoint size register and then working it
1434 * out from the amount we loaded for the transfer.
1436 * We need to do this as DMA pointers are always 32bit aligned
1437 * so may overshoot/undershoot the transfer.
1440 size_done
= hs_ep
->size_loaded
- size_left
;
1441 size_done
+= hs_ep
->last_load
;
1443 req
->actual
= size_done
;
1446 /* if there is more request to do, schedule new transfer */
1447 if (req
->actual
< req
->length
&& size_left
== 0) {
1448 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1450 } else if (epnum
== 0) {
1452 * After was_setup = 1 =>
1453 * set CNAK for non Setup requests
1455 hsotg
->setup
= was_setup
? 0 : 1;
1458 if (req
->actual
< req
->length
&& req
->short_not_ok
) {
1459 dev_dbg(hsotg
->dev
, "%s: got %d/%d (short not ok) => error\n",
1460 __func__
, req
->actual
, req
->length
);
1463 * todo - what should we return here? there's no one else
1464 * even bothering to check the status.
1470 * Condition req->complete != s3c_hsotg_complete_setup says:
1471 * send ZLP when we have an asynchronous request from gadget
1473 if (!was_setup
&& req
->complete
!= s3c_hsotg_complete_setup
)
1474 s3c_hsotg_send_zlp(hsotg
, hs_req
);
1477 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, result
);
1481 * s3c_hsotg_read_frameno - read current frame number
1482 * @hsotg: The device instance
1484 * Return the current frame number
1486 static u32
s3c_hsotg_read_frameno(struct dwc2_hsotg
*hsotg
)
1490 dsts
= readl(hsotg
->regs
+ DSTS
);
1491 dsts
&= DSTS_SOFFN_MASK
;
1492 dsts
>>= DSTS_SOFFN_SHIFT
;
1498 * s3c_hsotg_handle_rx - RX FIFO has data
1499 * @hsotg: The device instance
1501 * The IRQ handler has detected that the RX FIFO has some data in it
1502 * that requires processing, so find out what is in there and do the
1505 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1506 * chunks, so if you have x packets received on an endpoint you'll get x
1507 * FIFO events delivered, each with a packet's worth of data in it.
1509 * When using DMA, we should not be processing events from the RXFIFO
1510 * as the actual data should be sent to the memory directly and we turn
1511 * on the completion interrupts to get notifications of transfer completion.
1513 static void s3c_hsotg_handle_rx(struct dwc2_hsotg
*hsotg
)
1515 u32 grxstsr
= readl(hsotg
->regs
+ GRXSTSP
);
1516 u32 epnum
, status
, size
;
1518 WARN_ON(using_dma(hsotg
));
1520 epnum
= grxstsr
& GRXSTS_EPNUM_MASK
;
1521 status
= grxstsr
& GRXSTS_PKTSTS_MASK
;
1523 size
= grxstsr
& GRXSTS_BYTECNT_MASK
;
1524 size
>>= GRXSTS_BYTECNT_SHIFT
;
1527 dev_dbg(hsotg
->dev
, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1528 __func__
, grxstsr
, size
, epnum
);
1530 switch ((status
& GRXSTS_PKTSTS_MASK
) >> GRXSTS_PKTSTS_SHIFT
) {
1531 case GRXSTS_PKTSTS_GLOBALOUTNAK
:
1532 dev_dbg(hsotg
->dev
, "GLOBALOUTNAK\n");
1535 case GRXSTS_PKTSTS_OUTDONE
:
1536 dev_dbg(hsotg
->dev
, "OutDone (Frame=0x%08x)\n",
1537 s3c_hsotg_read_frameno(hsotg
));
1539 if (!using_dma(hsotg
))
1540 s3c_hsotg_handle_outdone(hsotg
, epnum
, false);
1543 case GRXSTS_PKTSTS_SETUPDONE
:
1545 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1546 s3c_hsotg_read_frameno(hsotg
),
1547 readl(hsotg
->regs
+ DOEPCTL(0)));
1549 s3c_hsotg_handle_outdone(hsotg
, epnum
, true);
1552 case GRXSTS_PKTSTS_OUTRX
:
1553 s3c_hsotg_rx_data(hsotg
, epnum
, size
);
1556 case GRXSTS_PKTSTS_SETUPRX
:
1558 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1559 s3c_hsotg_read_frameno(hsotg
),
1560 readl(hsotg
->regs
+ DOEPCTL(0)));
1562 s3c_hsotg_rx_data(hsotg
, epnum
, size
);
1566 dev_warn(hsotg
->dev
, "%s: unknown status %08x\n",
1569 s3c_hsotg_dump(hsotg
);
1575 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1576 * @mps: The maximum packet size in bytes.
1578 static u32
s3c_hsotg_ep0_mps(unsigned int mps
)
1582 return D0EPCTL_MPS_64
;
1584 return D0EPCTL_MPS_32
;
1586 return D0EPCTL_MPS_16
;
1588 return D0EPCTL_MPS_8
;
1591 /* bad max packet size, warn and return invalid result */
1597 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1598 * @hsotg: The driver state.
1599 * @ep: The index number of the endpoint
1600 * @mps: The maximum packet size in bytes
1602 * Configure the maximum packet size for the given endpoint, updating
1603 * the hardware control registers to reflect this.
1605 static void s3c_hsotg_set_ep_maxpacket(struct dwc2_hsotg
*hsotg
,
1606 unsigned int ep
, unsigned int mps
, unsigned int dir_in
)
1608 struct s3c_hsotg_ep
*hs_ep
;
1609 void __iomem
*regs
= hsotg
->regs
;
1614 hs_ep
= index_to_ep(hsotg
, ep
, dir_in
);
1619 /* EP0 is a special case */
1620 mpsval
= s3c_hsotg_ep0_mps(mps
);
1623 hs_ep
->ep
.maxpacket
= mps
;
1626 mpsval
= mps
& DXEPCTL_MPS_MASK
;
1629 mcval
= ((mps
>> 11) & 0x3) + 1;
1633 hs_ep
->ep
.maxpacket
= mpsval
;
1637 reg
= readl(regs
+ DIEPCTL(ep
));
1638 reg
&= ~DXEPCTL_MPS_MASK
;
1640 writel(reg
, regs
+ DIEPCTL(ep
));
1642 reg
= readl(regs
+ DOEPCTL(ep
));
1643 reg
&= ~DXEPCTL_MPS_MASK
;
1645 writel(reg
, regs
+ DOEPCTL(ep
));
1651 dev_err(hsotg
->dev
, "ep%d: bad mps of %d\n", ep
, mps
);
1655 * s3c_hsotg_txfifo_flush - flush Tx FIFO
1656 * @hsotg: The driver state
1657 * @idx: The index for the endpoint (0..15)
1659 static void s3c_hsotg_txfifo_flush(struct dwc2_hsotg
*hsotg
, unsigned int idx
)
1664 writel(GRSTCTL_TXFNUM(idx
) | GRSTCTL_TXFFLSH
,
1665 hsotg
->regs
+ GRSTCTL
);
1667 /* wait until the fifo is flushed */
1671 val
= readl(hsotg
->regs
+ GRSTCTL
);
1673 if ((val
& (GRSTCTL_TXFFLSH
)) == 0)
1676 if (--timeout
== 0) {
1678 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1688 * s3c_hsotg_trytx - check to see if anything needs transmitting
1689 * @hsotg: The driver state
1690 * @hs_ep: The driver endpoint to check.
1692 * Check to see if there is a request that has data to send, and if so
1693 * make an attempt to write data into the FIFO.
1695 static int s3c_hsotg_trytx(struct dwc2_hsotg
*hsotg
,
1696 struct s3c_hsotg_ep
*hs_ep
)
1698 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1700 if (!hs_ep
->dir_in
|| !hs_req
) {
1702 * if request is not enqueued, we disable interrupts
1703 * for endpoints, excepting ep0
1705 if (hs_ep
->index
!= 0)
1706 s3c_hsotg_ctrl_epint(hsotg
, hs_ep
->index
,
1711 if (hs_req
->req
.actual
< hs_req
->req
.length
) {
1712 dev_dbg(hsotg
->dev
, "trying to write more for ep%d\n",
1714 return s3c_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
1721 * s3c_hsotg_complete_in - complete IN transfer
1722 * @hsotg: The device state.
1723 * @hs_ep: The endpoint that has just completed.
1725 * An IN transfer has been completed, update the transfer's state and then
1726 * call the relevant completion routines.
1728 static void s3c_hsotg_complete_in(struct dwc2_hsotg
*hsotg
,
1729 struct s3c_hsotg_ep
*hs_ep
)
1731 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1732 u32 epsize
= readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
1733 int size_left
, size_done
;
1736 dev_dbg(hsotg
->dev
, "XferCompl but no req\n");
1740 /* Finish ZLP handling for IN EP0 transactions */
1741 if (hsotg
->eps_out
[0]->sent_zlp
) {
1742 dev_dbg(hsotg
->dev
, "zlp packet received\n");
1743 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
1748 * Calculate the size of the transfer by checking how much is left
1749 * in the endpoint size register and then working it out from
1750 * the amount we loaded for the transfer.
1752 * We do this even for DMA, as the transfer may have incremented
1753 * past the end of the buffer (DMA transfers are always 32bit
1757 size_left
= DXEPTSIZ_XFERSIZE_GET(epsize
);
1759 size_done
= hs_ep
->size_loaded
- size_left
;
1760 size_done
+= hs_ep
->last_load
;
1762 if (hs_req
->req
.actual
!= size_done
)
1763 dev_dbg(hsotg
->dev
, "%s: adjusting size done %d => %d\n",
1764 __func__
, hs_req
->req
.actual
, size_done
);
1766 hs_req
->req
.actual
= size_done
;
1767 dev_dbg(hsotg
->dev
, "req->length:%d req->actual:%d req->zero:%d\n",
1768 hs_req
->req
.length
, hs_req
->req
.actual
, hs_req
->req
.zero
);
1771 * Check if dealing with Maximum Packet Size(MPS) IN transfer at EP0
1772 * When sent data is a multiple MPS size (e.g. 64B ,128B ,192B
1773 * ,256B ... ), after last MPS sized packet send IN ZLP packet to
1774 * inform the host that no more data is available.
1775 * The state of req.zero member is checked to be sure that the value to
1776 * send is smaller than wValue expected from host.
1777 * Check req.length to NOT send another ZLP when the current one is
1778 * under completion (the one for which this completion has been called).
1780 if (hs_req
->req
.length
&& hs_ep
->index
== 0 && hs_req
->req
.zero
&&
1781 hs_req
->req
.length
== hs_req
->req
.actual
&&
1782 !(hs_req
->req
.length
% hs_ep
->ep
.maxpacket
)) {
1784 dev_dbg(hsotg
->dev
, "ep0 zlp IN packet sent\n");
1785 s3c_hsotg_send_zlp(hsotg
, hs_req
);
1790 if (!size_left
&& hs_req
->req
.actual
< hs_req
->req
.length
) {
1791 dev_dbg(hsotg
->dev
, "%s trying more for req...\n", __func__
);
1792 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1794 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
1798 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1799 * @hsotg: The driver state
1800 * @idx: The index for the endpoint (0..15)
1801 * @dir_in: Set if this is an IN endpoint
1803 * Process and clear any interrupt pending for an individual endpoint
1805 static void s3c_hsotg_epint(struct dwc2_hsotg
*hsotg
, unsigned int idx
,
1808 struct s3c_hsotg_ep
*hs_ep
= index_to_ep(hsotg
, idx
, dir_in
);
1809 u32 epint_reg
= dir_in
? DIEPINT(idx
) : DOEPINT(idx
);
1810 u32 epctl_reg
= dir_in
? DIEPCTL(idx
) : DOEPCTL(idx
);
1811 u32 epsiz_reg
= dir_in
? DIEPTSIZ(idx
) : DOEPTSIZ(idx
);
1815 ints
= readl(hsotg
->regs
+ epint_reg
);
1816 ctrl
= readl(hsotg
->regs
+ epctl_reg
);
1818 /* Clear endpoint interrupts */
1819 writel(ints
, hsotg
->regs
+ epint_reg
);
1822 dev_err(hsotg
->dev
, "%s:Interrupt for unconfigured ep%d(%s)\n",
1823 __func__
, idx
, dir_in
? "in" : "out");
1827 dev_dbg(hsotg
->dev
, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1828 __func__
, idx
, dir_in
? "in" : "out", ints
);
1830 /* Don't process XferCompl interrupt if it is a setup packet */
1831 if (idx
== 0 && (ints
& (DXEPINT_SETUP
| DXEPINT_SETUP_RCVD
)))
1832 ints
&= ~DXEPINT_XFERCOMPL
;
1834 if (ints
& DXEPINT_XFERCOMPL
) {
1835 if (hs_ep
->isochronous
&& hs_ep
->interval
== 1) {
1836 if (ctrl
& DXEPCTL_EOFRNUM
)
1837 ctrl
|= DXEPCTL_SETEVENFR
;
1839 ctrl
|= DXEPCTL_SETODDFR
;
1840 writel(ctrl
, hsotg
->regs
+ epctl_reg
);
1844 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
1845 __func__
, readl(hsotg
->regs
+ epctl_reg
),
1846 readl(hsotg
->regs
+ epsiz_reg
));
1849 * we get OutDone from the FIFO, so we only need to look
1850 * at completing IN requests here
1853 s3c_hsotg_complete_in(hsotg
, hs_ep
);
1855 if (idx
== 0 && !hs_ep
->req
)
1856 s3c_hsotg_enqueue_setup(hsotg
);
1857 } else if (using_dma(hsotg
)) {
1859 * We're using DMA, we need to fire an OutDone here
1860 * as we ignore the RXFIFO.
1863 s3c_hsotg_handle_outdone(hsotg
, idx
, false);
1867 if (ints
& DXEPINT_EPDISBLD
) {
1868 dev_dbg(hsotg
->dev
, "%s: EPDisbld\n", __func__
);
1871 int epctl
= readl(hsotg
->regs
+ epctl_reg
);
1873 s3c_hsotg_txfifo_flush(hsotg
, hs_ep
->fifo_index
);
1875 if ((epctl
& DXEPCTL_STALL
) &&
1876 (epctl
& DXEPCTL_EPTYPE_BULK
)) {
1877 int dctl
= readl(hsotg
->regs
+ DCTL
);
1879 dctl
|= DCTL_CGNPINNAK
;
1880 writel(dctl
, hsotg
->regs
+ DCTL
);
1885 if (ints
& DXEPINT_AHBERR
)
1886 dev_dbg(hsotg
->dev
, "%s: AHBErr\n", __func__
);
1888 if (ints
& DXEPINT_SETUP
) { /* Setup or Timeout */
1889 dev_dbg(hsotg
->dev
, "%s: Setup/Timeout\n", __func__
);
1891 if (using_dma(hsotg
) && idx
== 0) {
1893 * this is the notification we've received a
1894 * setup packet. In non-DMA mode we'd get this
1895 * from the RXFIFO, instead we need to process
1902 s3c_hsotg_handle_outdone(hsotg
, 0, true);
1906 if (ints
& DXEPINT_BACK2BACKSETUP
)
1907 dev_dbg(hsotg
->dev
, "%s: B2BSetup/INEPNakEff\n", __func__
);
1909 if (dir_in
&& !hs_ep
->isochronous
) {
1910 /* not sure if this is important, but we'll clear it anyway */
1911 if (ints
& DIEPMSK_INTKNTXFEMPMSK
) {
1912 dev_dbg(hsotg
->dev
, "%s: ep%d: INTknTXFEmpMsk\n",
1916 /* this probably means something bad is happening */
1917 if (ints
& DIEPMSK_INTKNEPMISMSK
) {
1918 dev_warn(hsotg
->dev
, "%s: ep%d: INTknEP\n",
1922 /* FIFO has space or is empty (see GAHBCFG) */
1923 if (hsotg
->dedicated_fifos
&&
1924 ints
& DIEPMSK_TXFIFOEMPTY
) {
1925 dev_dbg(hsotg
->dev
, "%s: ep%d: TxFIFOEmpty\n",
1927 if (!using_dma(hsotg
))
1928 s3c_hsotg_trytx(hsotg
, hs_ep
);
1934 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
1935 * @hsotg: The device state.
1937 * Handle updating the device settings after the enumeration phase has
1940 static void s3c_hsotg_irq_enumdone(struct dwc2_hsotg
*hsotg
)
1942 u32 dsts
= readl(hsotg
->regs
+ DSTS
);
1943 int ep0_mps
= 0, ep_mps
= 8;
1946 * This should signal the finish of the enumeration phase
1947 * of the USB handshaking, so we should now know what rate
1951 dev_dbg(hsotg
->dev
, "EnumDone (DSTS=0x%08x)\n", dsts
);
1954 * note, since we're limited by the size of transfer on EP0, and
1955 * it seems IN transfers must be a even number of packets we do
1956 * not advertise a 64byte MPS on EP0.
1959 /* catch both EnumSpd_FS and EnumSpd_FS48 */
1960 switch (dsts
& DSTS_ENUMSPD_MASK
) {
1961 case DSTS_ENUMSPD_FS
:
1962 case DSTS_ENUMSPD_FS48
:
1963 hsotg
->gadget
.speed
= USB_SPEED_FULL
;
1964 ep0_mps
= EP0_MPS_LIMIT
;
1968 case DSTS_ENUMSPD_HS
:
1969 hsotg
->gadget
.speed
= USB_SPEED_HIGH
;
1970 ep0_mps
= EP0_MPS_LIMIT
;
1974 case DSTS_ENUMSPD_LS
:
1975 hsotg
->gadget
.speed
= USB_SPEED_LOW
;
1977 * note, we don't actually support LS in this driver at the
1978 * moment, and the documentation seems to imply that it isn't
1979 * supported by the PHYs on some of the devices.
1983 dev_info(hsotg
->dev
, "new device is %s\n",
1984 usb_speed_string(hsotg
->gadget
.speed
));
1987 * we should now know the maximum packet size for an
1988 * endpoint, so set the endpoints to a default value.
1993 /* Initialize ep0 for both in and out directions */
1994 s3c_hsotg_set_ep_maxpacket(hsotg
, 0, ep0_mps
, 1);
1995 s3c_hsotg_set_ep_maxpacket(hsotg
, 0, ep0_mps
, 0);
1996 for (i
= 1; i
< hsotg
->num_of_eps
; i
++) {
1997 if (hsotg
->eps_in
[i
])
1998 s3c_hsotg_set_ep_maxpacket(hsotg
, i
, ep_mps
, 1);
1999 if (hsotg
->eps_out
[i
])
2000 s3c_hsotg_set_ep_maxpacket(hsotg
, i
, ep_mps
, 0);
2004 /* ensure after enumeration our EP0 is active */
2006 s3c_hsotg_enqueue_setup(hsotg
);
2008 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2009 readl(hsotg
->regs
+ DIEPCTL0
),
2010 readl(hsotg
->regs
+ DOEPCTL0
));
2014 * kill_all_requests - remove all requests from the endpoint's queue
2015 * @hsotg: The device state.
2016 * @ep: The endpoint the requests may be on.
2017 * @result: The result code to use.
2019 * Go through the requests on the given endpoint and mark them
2020 * completed with the given result code.
2022 static void kill_all_requests(struct dwc2_hsotg
*hsotg
,
2023 struct s3c_hsotg_ep
*ep
,
2026 struct s3c_hsotg_req
*req
, *treq
;
2031 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
)
2032 s3c_hsotg_complete_request(hsotg
, ep
, req
,
2035 if (!hsotg
->dedicated_fifos
)
2037 size
= (readl(hsotg
->regs
+ DTXFSTS(ep
->index
)) & 0xffff) * 4;
2038 if (size
< ep
->fifo_size
)
2039 s3c_hsotg_txfifo_flush(hsotg
, ep
->fifo_index
);
2043 * s3c_hsotg_disconnect - disconnect service
2044 * @hsotg: The device state.
2046 * The device has been disconnected. Remove all current
2047 * transactions and signal the gadget driver that this
2050 void s3c_hsotg_disconnect(struct dwc2_hsotg
*hsotg
)
2054 if (!hsotg
->connected
)
2057 hsotg
->connected
= 0;
2059 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++) {
2060 if (hsotg
->eps_in
[ep
])
2061 kill_all_requests(hsotg
, hsotg
->eps_in
[ep
],
2063 if (hsotg
->eps_out
[ep
])
2064 kill_all_requests(hsotg
, hsotg
->eps_out
[ep
],
2068 call_gadget(hsotg
, disconnect
);
2070 EXPORT_SYMBOL_GPL(s3c_hsotg_disconnect
);
2073 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2074 * @hsotg: The device state:
2075 * @periodic: True if this is a periodic FIFO interrupt
2077 static void s3c_hsotg_irq_fifoempty(struct dwc2_hsotg
*hsotg
, bool periodic
)
2079 struct s3c_hsotg_ep
*ep
;
2082 /* look through for any more data to transmit */
2083 for (epno
= 0; epno
< hsotg
->num_of_eps
; epno
++) {
2084 ep
= index_to_ep(hsotg
, epno
, 1);
2092 if ((periodic
&& !ep
->periodic
) ||
2093 (!periodic
&& ep
->periodic
))
2096 ret
= s3c_hsotg_trytx(hsotg
, ep
);
2102 /* IRQ flags which will trigger a retry around the IRQ loop */
2103 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
2108 * s3c_hsotg_corereset - issue softreset to the core
2109 * @hsotg: The device state
2111 * Issue a soft reset to the core, and await the core finishing it.
2113 static int s3c_hsotg_corereset(struct dwc2_hsotg
*hsotg
)
2118 dev_dbg(hsotg
->dev
, "resetting core\n");
2120 /* issue soft reset */
2121 writel(GRSTCTL_CSFTRST
, hsotg
->regs
+ GRSTCTL
);
2125 grstctl
= readl(hsotg
->regs
+ GRSTCTL
);
2126 } while ((grstctl
& GRSTCTL_CSFTRST
) && timeout
-- > 0);
2128 if (grstctl
& GRSTCTL_CSFTRST
) {
2129 dev_err(hsotg
->dev
, "Failed to get CSftRst asserted\n");
2136 u32 grstctl
= readl(hsotg
->regs
+ GRSTCTL
);
2138 if (timeout
-- < 0) {
2139 dev_info(hsotg
->dev
,
2140 "%s: reset failed, GRSTCTL=%08x\n",
2145 if (!(grstctl
& GRSTCTL_AHBIDLE
))
2148 break; /* reset done */
2151 dev_dbg(hsotg
->dev
, "reset successful\n");
2156 * s3c_hsotg_core_init - issue softreset to the core
2157 * @hsotg: The device state
2159 * Issue a soft reset to the core, and await the core finishing it.
2161 void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg
*hsotg
)
2163 s3c_hsotg_corereset(hsotg
);
2166 * we must now enable ep0 ready for host detection and then
2167 * set configuration.
2170 /* set the PLL on, remove the HNP/SRP and set the PHY */
2171 writel(hsotg
->phyif
| GUSBCFG_TOUTCAL(7) |
2172 (0x5 << 10), hsotg
->regs
+ GUSBCFG
);
2174 s3c_hsotg_init_fifo(hsotg
);
2176 __orr32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
2178 writel(1 << 18 | DCFG_DEVSPD_HS
, hsotg
->regs
+ DCFG
);
2180 /* Clear any pending OTG interrupts */
2181 writel(0xffffffff, hsotg
->regs
+ GOTGINT
);
2183 /* Clear any pending interrupts */
2184 writel(0xffffffff, hsotg
->regs
+ GINTSTS
);
2186 writel(GINTSTS_ERLYSUSP
| GINTSTS_SESSREQINT
|
2187 GINTSTS_GOUTNAKEFF
| GINTSTS_GINNAKEFF
|
2188 GINTSTS_CONIDSTSCHNG
| GINTSTS_USBRST
|
2189 GINTSTS_ENUMDONE
| GINTSTS_OTGINT
|
2190 GINTSTS_USBSUSP
| GINTSTS_WKUPINT
,
2191 hsotg
->regs
+ GINTMSK
);
2193 if (using_dma(hsotg
))
2194 writel(GAHBCFG_GLBL_INTR_EN
| GAHBCFG_DMA_EN
|
2195 (GAHBCFG_HBSTLEN_INCR4
<< GAHBCFG_HBSTLEN_SHIFT
),
2196 hsotg
->regs
+ GAHBCFG
);
2198 writel(((hsotg
->dedicated_fifos
) ? (GAHBCFG_NP_TXF_EMP_LVL
|
2199 GAHBCFG_P_TXF_EMP_LVL
) : 0) |
2200 GAHBCFG_GLBL_INTR_EN
,
2201 hsotg
->regs
+ GAHBCFG
);
2204 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2205 * when we have no data to transfer. Otherwise we get being flooded by
2209 writel(((hsotg
->dedicated_fifos
&& !using_dma(hsotg
)) ?
2210 DIEPMSK_TXFIFOEMPTY
| DIEPMSK_INTKNTXFEMPMSK
: 0) |
2211 DIEPMSK_EPDISBLDMSK
| DIEPMSK_XFERCOMPLMSK
|
2212 DIEPMSK_TIMEOUTMSK
| DIEPMSK_AHBERRMSK
|
2213 DIEPMSK_INTKNEPMISMSK
,
2214 hsotg
->regs
+ DIEPMSK
);
2217 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2218 * DMA mode we may need this.
2220 writel((using_dma(hsotg
) ? (DIEPMSK_XFERCOMPLMSK
|
2221 DIEPMSK_TIMEOUTMSK
) : 0) |
2222 DOEPMSK_EPDISBLDMSK
| DOEPMSK_AHBERRMSK
|
2224 hsotg
->regs
+ DOEPMSK
);
2226 writel(0, hsotg
->regs
+ DAINTMSK
);
2228 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2229 readl(hsotg
->regs
+ DIEPCTL0
),
2230 readl(hsotg
->regs
+ DOEPCTL0
));
2232 /* enable in and out endpoint interrupts */
2233 s3c_hsotg_en_gsint(hsotg
, GINTSTS_OEPINT
| GINTSTS_IEPINT
);
2236 * Enable the RXFIFO when in slave mode, as this is how we collect
2237 * the data. In DMA mode, we get events from the FIFO but also
2238 * things we cannot process, so do not use it.
2240 if (!using_dma(hsotg
))
2241 s3c_hsotg_en_gsint(hsotg
, GINTSTS_RXFLVL
);
2243 /* Enable interrupts for EP0 in and out */
2244 s3c_hsotg_ctrl_epint(hsotg
, 0, 0, 1);
2245 s3c_hsotg_ctrl_epint(hsotg
, 0, 1, 1);
2247 __orr32(hsotg
->regs
+ DCTL
, DCTL_PWRONPRGDONE
);
2248 udelay(10); /* see openiboot */
2249 __bic32(hsotg
->regs
+ DCTL
, DCTL_PWRONPRGDONE
);
2251 dev_dbg(hsotg
->dev
, "DCTL=0x%08x\n", readl(hsotg
->regs
+ DCTL
));
2254 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2255 * writing to the EPCTL register..
2258 /* set to read 1 8byte packet */
2259 writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2260 DXEPTSIZ_XFERSIZE(8), hsotg
->regs
+ DOEPTSIZ0
);
2262 writel(s3c_hsotg_ep0_mps(hsotg
->eps_out
[0]->ep
.maxpacket
) |
2263 DXEPCTL_CNAK
| DXEPCTL_EPENA
|
2265 hsotg
->regs
+ DOEPCTL0
);
2267 /* enable, but don't activate EP0in */
2268 writel(s3c_hsotg_ep0_mps(hsotg
->eps_out
[0]->ep
.maxpacket
) |
2269 DXEPCTL_USBACTEP
, hsotg
->regs
+ DIEPCTL0
);
2271 s3c_hsotg_enqueue_setup(hsotg
);
2273 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2274 readl(hsotg
->regs
+ DIEPCTL0
),
2275 readl(hsotg
->regs
+ DOEPCTL0
));
2277 /* clear global NAKs */
2278 writel(DCTL_CGOUTNAK
| DCTL_CGNPINNAK
| DCTL_SFTDISCON
,
2279 hsotg
->regs
+ DCTL
);
2281 /* must be at-least 3ms to allow bus to see disconnect */
2284 hsotg
->last_rst
= jiffies
;
2287 static void s3c_hsotg_core_disconnect(struct dwc2_hsotg
*hsotg
)
2289 /* set the soft-disconnect bit */
2290 __orr32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
2293 void s3c_hsotg_core_connect(struct dwc2_hsotg
*hsotg
)
2295 /* remove the soft-disconnect and let's go */
2296 __bic32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
2300 * s3c_hsotg_irq - handle device interrupt
2301 * @irq: The IRQ number triggered
2302 * @pw: The pw value when registered the handler.
2304 static irqreturn_t
s3c_hsotg_irq(int irq
, void *pw
)
2306 struct dwc2_hsotg
*hsotg
= pw
;
2307 int retry_count
= 8;
2311 spin_lock(&hsotg
->lock
);
2313 gintsts
= readl(hsotg
->regs
+ GINTSTS
);
2314 gintmsk
= readl(hsotg
->regs
+ GINTMSK
);
2316 dev_dbg(hsotg
->dev
, "%s: %08x %08x (%08x) retry %d\n",
2317 __func__
, gintsts
, gintsts
& gintmsk
, gintmsk
, retry_count
);
2321 if (gintsts
& GINTSTS_ENUMDONE
) {
2322 writel(GINTSTS_ENUMDONE
, hsotg
->regs
+ GINTSTS
);
2324 s3c_hsotg_irq_enumdone(hsotg
);
2325 hsotg
->connected
= 1;
2328 if (gintsts
& (GINTSTS_OEPINT
| GINTSTS_IEPINT
)) {
2329 u32 daint
= readl(hsotg
->regs
+ DAINT
);
2330 u32 daintmsk
= readl(hsotg
->regs
+ DAINTMSK
);
2331 u32 daint_out
, daint_in
;
2335 daint_out
= daint
>> DAINT_OUTEP_SHIFT
;
2336 daint_in
= daint
& ~(daint_out
<< DAINT_OUTEP_SHIFT
);
2338 dev_dbg(hsotg
->dev
, "%s: daint=%08x\n", __func__
, daint
);
2340 for (ep
= 0; ep
< 15 && daint_out
; ep
++, daint_out
>>= 1) {
2342 s3c_hsotg_epint(hsotg
, ep
, 0);
2345 for (ep
= 0; ep
< 15 && daint_in
; ep
++, daint_in
>>= 1) {
2347 s3c_hsotg_epint(hsotg
, ep
, 1);
2351 if (gintsts
& GINTSTS_USBRST
) {
2353 u32 usb_status
= readl(hsotg
->regs
+ GOTGCTL
);
2355 dev_dbg(hsotg
->dev
, "%s: USBRst\n", __func__
);
2356 dev_dbg(hsotg
->dev
, "GNPTXSTS=%08x\n",
2357 readl(hsotg
->regs
+ GNPTXSTS
));
2359 writel(GINTSTS_USBRST
, hsotg
->regs
+ GINTSTS
);
2361 if (usb_status
& GOTGCTL_BSESVLD
) {
2362 if (time_after(jiffies
, hsotg
->last_rst
+
2363 msecs_to_jiffies(200))) {
2365 kill_all_requests(hsotg
, hsotg
->eps_out
[0],
2368 s3c_hsotg_core_init_disconnected(hsotg
);
2369 s3c_hsotg_core_connect(hsotg
);
2374 /* check both FIFOs */
2376 if (gintsts
& GINTSTS_NPTXFEMP
) {
2377 dev_dbg(hsotg
->dev
, "NPTxFEmp\n");
2380 * Disable the interrupt to stop it happening again
2381 * unless one of these endpoint routines decides that
2382 * it needs re-enabling
2385 s3c_hsotg_disable_gsint(hsotg
, GINTSTS_NPTXFEMP
);
2386 s3c_hsotg_irq_fifoempty(hsotg
, false);
2389 if (gintsts
& GINTSTS_PTXFEMP
) {
2390 dev_dbg(hsotg
->dev
, "PTxFEmp\n");
2392 /* See note in GINTSTS_NPTxFEmp */
2394 s3c_hsotg_disable_gsint(hsotg
, GINTSTS_PTXFEMP
);
2395 s3c_hsotg_irq_fifoempty(hsotg
, true);
2398 if (gintsts
& GINTSTS_RXFLVL
) {
2400 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2401 * we need to retry s3c_hsotg_handle_rx if this is still
2405 s3c_hsotg_handle_rx(hsotg
);
2408 if (gintsts
& GINTSTS_ERLYSUSP
) {
2409 dev_dbg(hsotg
->dev
, "GINTSTS_ErlySusp\n");
2410 writel(GINTSTS_ERLYSUSP
, hsotg
->regs
+ GINTSTS
);
2414 * these next two seem to crop-up occasionally causing the core
2415 * to shutdown the USB transfer, so try clearing them and logging
2419 if (gintsts
& GINTSTS_GOUTNAKEFF
) {
2420 dev_info(hsotg
->dev
, "GOUTNakEff triggered\n");
2422 writel(DCTL_CGOUTNAK
, hsotg
->regs
+ DCTL
);
2424 s3c_hsotg_dump(hsotg
);
2427 if (gintsts
& GINTSTS_GINNAKEFF
) {
2428 dev_info(hsotg
->dev
, "GINNakEff triggered\n");
2430 writel(DCTL_CGNPINNAK
, hsotg
->regs
+ DCTL
);
2432 s3c_hsotg_dump(hsotg
);
2436 * if we've had fifo events, we should try and go around the
2437 * loop again to see if there's any point in returning yet.
2440 if (gintsts
& IRQ_RETRY_MASK
&& --retry_count
> 0)
2443 spin_unlock(&hsotg
->lock
);
2449 * s3c_hsotg_ep_enable - enable the given endpoint
2450 * @ep: The USB endpint to configure
2451 * @desc: The USB endpoint descriptor to configure with.
2453 * This is called from the USB gadget code's usb_ep_enable().
2455 static int s3c_hsotg_ep_enable(struct usb_ep
*ep
,
2456 const struct usb_endpoint_descriptor
*desc
)
2458 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2459 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
2460 unsigned long flags
;
2461 int index
= hs_ep
->index
;
2470 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2471 __func__
, ep
->name
, desc
->bEndpointAddress
, desc
->bmAttributes
,
2472 desc
->wMaxPacketSize
, desc
->bInterval
);
2474 /* not to be called for EP0 */
2475 WARN_ON(index
== 0);
2477 dir_in
= (desc
->bEndpointAddress
& USB_ENDPOINT_DIR_MASK
) ? 1 : 0;
2478 if (dir_in
!= hs_ep
->dir_in
) {
2479 dev_err(hsotg
->dev
, "%s: direction mismatch!\n", __func__
);
2483 mps
= usb_endpoint_maxp(desc
);
2485 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2487 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2488 epctrl
= readl(hsotg
->regs
+ epctrl_reg
);
2490 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2491 __func__
, epctrl
, epctrl_reg
);
2493 spin_lock_irqsave(&hsotg
->lock
, flags
);
2495 epctrl
&= ~(DXEPCTL_EPTYPE_MASK
| DXEPCTL_MPS_MASK
);
2496 epctrl
|= DXEPCTL_MPS(mps
);
2499 * mark the endpoint as active, otherwise the core may ignore
2500 * transactions entirely for this endpoint
2502 epctrl
|= DXEPCTL_USBACTEP
;
2505 * set the NAK status on the endpoint, otherwise we might try and
2506 * do something with data that we've yet got a request to process
2507 * since the RXFIFO will take data for an endpoint even if the
2508 * size register hasn't been set.
2511 epctrl
|= DXEPCTL_SNAK
;
2513 /* update the endpoint state */
2514 s3c_hsotg_set_ep_maxpacket(hsotg
, hs_ep
->index
, mps
, dir_in
);
2516 /* default, set to non-periodic */
2517 hs_ep
->isochronous
= 0;
2518 hs_ep
->periodic
= 0;
2520 hs_ep
->interval
= desc
->bInterval
;
2522 if (hs_ep
->interval
> 1 && hs_ep
->mc
> 1)
2523 dev_err(hsotg
->dev
, "MC > 1 when interval is not 1\n");
2525 switch (desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
) {
2526 case USB_ENDPOINT_XFER_ISOC
:
2527 epctrl
|= DXEPCTL_EPTYPE_ISO
;
2528 epctrl
|= DXEPCTL_SETEVENFR
;
2529 hs_ep
->isochronous
= 1;
2531 hs_ep
->periodic
= 1;
2534 case USB_ENDPOINT_XFER_BULK
:
2535 epctrl
|= DXEPCTL_EPTYPE_BULK
;
2538 case USB_ENDPOINT_XFER_INT
:
2540 hs_ep
->periodic
= 1;
2542 epctrl
|= DXEPCTL_EPTYPE_INTERRUPT
;
2545 case USB_ENDPOINT_XFER_CONTROL
:
2546 epctrl
|= DXEPCTL_EPTYPE_CONTROL
;
2551 * if the hardware has dedicated fifos, we must give each IN EP
2552 * a unique tx-fifo even if it is non-periodic.
2554 if (dir_in
&& hsotg
->dedicated_fifos
) {
2555 size
= hs_ep
->ep
.maxpacket
*hs_ep
->mc
;
2556 for (i
= 1; i
<= 8; ++i
) {
2557 if (hsotg
->fifo_map
& (1<<i
))
2559 val
= readl(hsotg
->regs
+ DPTXFSIZN(i
));
2560 val
= (val
>> FIFOSIZE_DEPTH_SHIFT
)*4;
2563 hsotg
->fifo_map
|= 1<<i
;
2565 epctrl
|= DXEPCTL_TXFNUM(i
);
2566 hs_ep
->fifo_index
= i
;
2567 hs_ep
->fifo_size
= val
;
2576 /* for non control endpoints, set PID to D0 */
2578 epctrl
|= DXEPCTL_SETD0PID
;
2580 dev_dbg(hsotg
->dev
, "%s: write DxEPCTL=0x%08x\n",
2583 writel(epctrl
, hsotg
->regs
+ epctrl_reg
);
2584 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x\n",
2585 __func__
, readl(hsotg
->regs
+ epctrl_reg
));
2587 /* enable the endpoint interrupt */
2588 s3c_hsotg_ctrl_epint(hsotg
, index
, dir_in
, 1);
2591 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2596 * s3c_hsotg_ep_disable - disable given endpoint
2597 * @ep: The endpoint to disable.
2599 static int s3c_hsotg_ep_disable(struct usb_ep
*ep
)
2601 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2602 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
2603 int dir_in
= hs_ep
->dir_in
;
2604 int index
= hs_ep
->index
;
2605 unsigned long flags
;
2609 dev_dbg(hsotg
->dev
, "%s(ep %p)\n", __func__
, ep
);
2611 if (ep
== &hsotg
->eps_out
[0]->ep
) {
2612 dev_err(hsotg
->dev
, "%s: called for ep0\n", __func__
);
2616 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2618 spin_lock_irqsave(&hsotg
->lock
, flags
);
2619 /* terminate all requests with shutdown */
2620 kill_all_requests(hsotg
, hs_ep
, -ESHUTDOWN
);
2622 hsotg
->fifo_map
&= ~(1<<hs_ep
->fifo_index
);
2623 hs_ep
->fifo_index
= 0;
2624 hs_ep
->fifo_size
= 0;
2626 ctrl
= readl(hsotg
->regs
+ epctrl_reg
);
2627 ctrl
&= ~DXEPCTL_EPENA
;
2628 ctrl
&= ~DXEPCTL_USBACTEP
;
2629 ctrl
|= DXEPCTL_SNAK
;
2631 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
2632 writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
2634 /* disable endpoint interrupts */
2635 s3c_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 0);
2637 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2642 * on_list - check request is on the given endpoint
2643 * @ep: The endpoint to check.
2644 * @test: The request to test if it is on the endpoint.
2646 static bool on_list(struct s3c_hsotg_ep
*ep
, struct s3c_hsotg_req
*test
)
2648 struct s3c_hsotg_req
*req
, *treq
;
2650 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
2659 * s3c_hsotg_ep_dequeue - dequeue given endpoint
2660 * @ep: The endpoint to dequeue.
2661 * @req: The request to be removed from a queue.
2663 static int s3c_hsotg_ep_dequeue(struct usb_ep
*ep
, struct usb_request
*req
)
2665 struct s3c_hsotg_req
*hs_req
= our_req(req
);
2666 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2667 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
2668 unsigned long flags
;
2670 dev_dbg(hs
->dev
, "ep_dequeue(%p,%p)\n", ep
, req
);
2672 spin_lock_irqsave(&hs
->lock
, flags
);
2674 if (!on_list(hs_ep
, hs_req
)) {
2675 spin_unlock_irqrestore(&hs
->lock
, flags
);
2679 s3c_hsotg_complete_request(hs
, hs_ep
, hs_req
, -ECONNRESET
);
2680 spin_unlock_irqrestore(&hs
->lock
, flags
);
2686 * s3c_hsotg_ep_sethalt - set halt on a given endpoint
2687 * @ep: The endpoint to set halt.
2688 * @value: Set or unset the halt.
2690 static int s3c_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
)
2692 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2693 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
2694 int index
= hs_ep
->index
;
2699 dev_info(hs
->dev
, "%s(ep %p %s, %d)\n", __func__
, ep
, ep
->name
, value
);
2703 s3c_hsotg_stall_ep0(hs
);
2706 "%s: can't clear halt on ep0\n", __func__
);
2710 if (hs_ep
->dir_in
) {
2711 epreg
= DIEPCTL(index
);
2712 epctl
= readl(hs
->regs
+ epreg
);
2715 epctl
|= DXEPCTL_STALL
+ DXEPCTL_SNAK
;
2716 if (epctl
& DXEPCTL_EPENA
)
2717 epctl
|= DXEPCTL_EPDIS
;
2719 epctl
&= ~DXEPCTL_STALL
;
2720 xfertype
= epctl
& DXEPCTL_EPTYPE_MASK
;
2721 if (xfertype
== DXEPCTL_EPTYPE_BULK
||
2722 xfertype
== DXEPCTL_EPTYPE_INTERRUPT
)
2723 epctl
|= DXEPCTL_SETD0PID
;
2725 writel(epctl
, hs
->regs
+ epreg
);
2728 epreg
= DOEPCTL(index
);
2729 epctl
= readl(hs
->regs
+ epreg
);
2732 epctl
|= DXEPCTL_STALL
;
2734 epctl
&= ~DXEPCTL_STALL
;
2735 xfertype
= epctl
& DXEPCTL_EPTYPE_MASK
;
2736 if (xfertype
== DXEPCTL_EPTYPE_BULK
||
2737 xfertype
== DXEPCTL_EPTYPE_INTERRUPT
)
2738 epctl
|= DXEPCTL_SETD0PID
;
2740 writel(epctl
, hs
->regs
+ epreg
);
2743 hs_ep
->halted
= value
;
2749 * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
2750 * @ep: The endpoint to set halt.
2751 * @value: Set or unset the halt.
2753 static int s3c_hsotg_ep_sethalt_lock(struct usb_ep
*ep
, int value
)
2755 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2756 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
2757 unsigned long flags
= 0;
2760 spin_lock_irqsave(&hs
->lock
, flags
);
2761 ret
= s3c_hsotg_ep_sethalt(ep
, value
);
2762 spin_unlock_irqrestore(&hs
->lock
, flags
);
2767 static struct usb_ep_ops s3c_hsotg_ep_ops
= {
2768 .enable
= s3c_hsotg_ep_enable
,
2769 .disable
= s3c_hsotg_ep_disable
,
2770 .alloc_request
= s3c_hsotg_ep_alloc_request
,
2771 .free_request
= s3c_hsotg_ep_free_request
,
2772 .queue
= s3c_hsotg_ep_queue_lock
,
2773 .dequeue
= s3c_hsotg_ep_dequeue
,
2774 .set_halt
= s3c_hsotg_ep_sethalt_lock
,
2775 /* note, don't believe we have any call for the fifo routines */
2779 * s3c_hsotg_phy_enable - enable platform phy dev
2780 * @hsotg: The driver state
2782 * A wrapper for platform code responsible for controlling
2783 * low-level USB code
2785 static void s3c_hsotg_phy_enable(struct dwc2_hsotg
*hsotg
)
2787 struct platform_device
*pdev
= to_platform_device(hsotg
->dev
);
2789 dev_dbg(hsotg
->dev
, "pdev 0x%p\n", pdev
);
2792 usb_phy_init(hsotg
->uphy
);
2793 else if (hsotg
->plat
&& hsotg
->plat
->phy_init
)
2794 hsotg
->plat
->phy_init(pdev
, hsotg
->plat
->phy_type
);
2796 phy_init(hsotg
->phy
);
2797 phy_power_on(hsotg
->phy
);
2802 * s3c_hsotg_phy_disable - disable platform phy dev
2803 * @hsotg: The driver state
2805 * A wrapper for platform code responsible for controlling
2806 * low-level USB code
2808 static void s3c_hsotg_phy_disable(struct dwc2_hsotg
*hsotg
)
2810 struct platform_device
*pdev
= to_platform_device(hsotg
->dev
);
2813 usb_phy_shutdown(hsotg
->uphy
);
2814 else if (hsotg
->plat
&& hsotg
->plat
->phy_exit
)
2815 hsotg
->plat
->phy_exit(pdev
, hsotg
->plat
->phy_type
);
2817 phy_power_off(hsotg
->phy
);
2818 phy_exit(hsotg
->phy
);
2823 * s3c_hsotg_init - initalize the usb core
2824 * @hsotg: The driver state
2826 static void s3c_hsotg_init(struct dwc2_hsotg
*hsotg
)
2828 /* unmask subset of endpoint interrupts */
2830 writel(DIEPMSK_TIMEOUTMSK
| DIEPMSK_AHBERRMSK
|
2831 DIEPMSK_EPDISBLDMSK
| DIEPMSK_XFERCOMPLMSK
,
2832 hsotg
->regs
+ DIEPMSK
);
2834 writel(DOEPMSK_SETUPMSK
| DOEPMSK_AHBERRMSK
|
2835 DOEPMSK_EPDISBLDMSK
| DOEPMSK_XFERCOMPLMSK
,
2836 hsotg
->regs
+ DOEPMSK
);
2838 writel(0, hsotg
->regs
+ DAINTMSK
);
2840 /* Be in disconnected state until gadget is registered */
2841 __orr32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
2844 /* post global nak until we're ready */
2845 writel(DCTL_SGNPINNAK
| DCTL_SGOUTNAK
,
2846 hsotg
->regs
+ DCTL
);
2851 dev_dbg(hsotg
->dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2852 readl(hsotg
->regs
+ GRXFSIZ
),
2853 readl(hsotg
->regs
+ GNPTXFSIZ
));
2855 s3c_hsotg_init_fifo(hsotg
);
2857 /* set the PLL on, remove the HNP/SRP and set the PHY */
2858 writel(GUSBCFG_PHYIF16
| GUSBCFG_TOUTCAL(7) | (0x5 << 10),
2859 hsotg
->regs
+ GUSBCFG
);
2861 if (using_dma(hsotg
))
2862 __orr32(hsotg
->regs
+ GAHBCFG
, GAHBCFG_DMA_EN
);
2866 * s3c_hsotg_udc_start - prepare the udc for work
2867 * @gadget: The usb gadget state
2868 * @driver: The usb gadget driver
2870 * Perform initialization to prepare udc device and driver
2873 static int s3c_hsotg_udc_start(struct usb_gadget
*gadget
,
2874 struct usb_gadget_driver
*driver
)
2876 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
2877 unsigned long flags
;
2881 pr_err("%s: called with no device\n", __func__
);
2886 dev_err(hsotg
->dev
, "%s: no driver\n", __func__
);
2890 if (driver
->max_speed
< USB_SPEED_FULL
)
2891 dev_err(hsotg
->dev
, "%s: bad speed\n", __func__
);
2893 if (!driver
->setup
) {
2894 dev_err(hsotg
->dev
, "%s: missing entry points\n", __func__
);
2898 mutex_lock(&hsotg
->init_mutex
);
2899 WARN_ON(hsotg
->driver
);
2901 driver
->driver
.bus
= NULL
;
2902 hsotg
->driver
= driver
;
2903 hsotg
->gadget
.dev
.of_node
= hsotg
->dev
->of_node
;
2904 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2906 clk_enable(hsotg
->clk
);
2908 ret
= regulator_bulk_enable(ARRAY_SIZE(hsotg
->supplies
),
2911 dev_err(hsotg
->dev
, "failed to enable supplies: %d\n", ret
);
2915 s3c_hsotg_phy_enable(hsotg
);
2916 if (!IS_ERR_OR_NULL(hsotg
->uphy
))
2917 otg_set_peripheral(hsotg
->uphy
->otg
, &hsotg
->gadget
);
2919 spin_lock_irqsave(&hsotg
->lock
, flags
);
2920 s3c_hsotg_init(hsotg
);
2921 s3c_hsotg_core_init_disconnected(hsotg
);
2923 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2925 dev_info(hsotg
->dev
, "bound driver %s\n", driver
->driver
.name
);
2927 mutex_unlock(&hsotg
->init_mutex
);
2932 mutex_unlock(&hsotg
->init_mutex
);
2933 hsotg
->driver
= NULL
;
2938 * s3c_hsotg_udc_stop - stop the udc
2939 * @gadget: The usb gadget state
2940 * @driver: The usb gadget driver
2942 * Stop udc hw block and stay tunned for future transmissions
2944 static int s3c_hsotg_udc_stop(struct usb_gadget
*gadget
)
2946 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
2947 unsigned long flags
= 0;
2953 mutex_lock(&hsotg
->init_mutex
);
2955 /* all endpoints should be shutdown */
2956 for (ep
= 1; ep
< hsotg
->num_of_eps
; ep
++) {
2957 if (hsotg
->eps_in
[ep
])
2958 s3c_hsotg_ep_disable(&hsotg
->eps_in
[ep
]->ep
);
2959 if (hsotg
->eps_out
[ep
])
2960 s3c_hsotg_ep_disable(&hsotg
->eps_out
[ep
]->ep
);
2963 spin_lock_irqsave(&hsotg
->lock
, flags
);
2965 hsotg
->driver
= NULL
;
2966 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2969 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2971 if (!IS_ERR_OR_NULL(hsotg
->uphy
))
2972 otg_set_peripheral(hsotg
->uphy
->otg
, NULL
);
2973 s3c_hsotg_phy_disable(hsotg
);
2975 regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
), hsotg
->supplies
);
2977 clk_disable(hsotg
->clk
);
2979 mutex_unlock(&hsotg
->init_mutex
);
2985 * s3c_hsotg_gadget_getframe - read the frame number
2986 * @gadget: The usb gadget state
2988 * Read the {micro} frame number
2990 static int s3c_hsotg_gadget_getframe(struct usb_gadget
*gadget
)
2992 return s3c_hsotg_read_frameno(to_hsotg(gadget
));
2996 * s3c_hsotg_pullup - connect/disconnect the USB PHY
2997 * @gadget: The usb gadget state
2998 * @is_on: Current state of the USB PHY
3000 * Connect/Disconnect the USB PHY pullup
3002 static int s3c_hsotg_pullup(struct usb_gadget
*gadget
, int is_on
)
3004 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
3005 unsigned long flags
= 0;
3007 dev_dbg(hsotg
->dev
, "%s: is_on: %d\n", __func__
, is_on
);
3009 mutex_lock(&hsotg
->init_mutex
);
3010 spin_lock_irqsave(&hsotg
->lock
, flags
);
3012 clk_enable(hsotg
->clk
);
3014 s3c_hsotg_core_connect(hsotg
);
3016 s3c_hsotg_core_disconnect(hsotg
);
3018 clk_disable(hsotg
->clk
);
3021 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3022 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3023 mutex_unlock(&hsotg
->init_mutex
);
3028 static const struct usb_gadget_ops s3c_hsotg_gadget_ops
= {
3029 .get_frame
= s3c_hsotg_gadget_getframe
,
3030 .udc_start
= s3c_hsotg_udc_start
,
3031 .udc_stop
= s3c_hsotg_udc_stop
,
3032 .pullup
= s3c_hsotg_pullup
,
3036 * s3c_hsotg_initep - initialise a single endpoint
3037 * @hsotg: The device state.
3038 * @hs_ep: The endpoint to be initialised.
3039 * @epnum: The endpoint number
3041 * Initialise the given endpoint (as part of the probe and device state
3042 * creation) to give to the gadget driver. Setup the endpoint name, any
3043 * direction information and other state that may be required.
3045 static void s3c_hsotg_initep(struct dwc2_hsotg
*hsotg
,
3046 struct s3c_hsotg_ep
*hs_ep
,
3059 hs_ep
->dir_in
= dir_in
;
3060 hs_ep
->index
= epnum
;
3062 snprintf(hs_ep
->name
, sizeof(hs_ep
->name
), "ep%d%s", epnum
, dir
);
3064 INIT_LIST_HEAD(&hs_ep
->queue
);
3065 INIT_LIST_HEAD(&hs_ep
->ep
.ep_list
);
3067 /* add to the list of endpoints known by the gadget driver */
3069 list_add_tail(&hs_ep
->ep
.ep_list
, &hsotg
->gadget
.ep_list
);
3071 hs_ep
->parent
= hsotg
;
3072 hs_ep
->ep
.name
= hs_ep
->name
;
3073 usb_ep_set_maxpacket_limit(&hs_ep
->ep
, epnum
? 1024 : EP0_MPS_LIMIT
);
3074 hs_ep
->ep
.ops
= &s3c_hsotg_ep_ops
;
3077 * if we're using dma, we need to set the next-endpoint pointer
3078 * to be something valid.
3081 if (using_dma(hsotg
)) {
3082 u32 next
= DXEPCTL_NEXTEP((epnum
+ 1) % 15);
3084 writel(next
, hsotg
->regs
+ DIEPCTL(epnum
));
3086 writel(next
, hsotg
->regs
+ DOEPCTL(epnum
));
3091 * s3c_hsotg_hw_cfg - read HW configuration registers
3092 * @param: The device state
3094 * Read the USB core HW configuration registers
3096 static int s3c_hsotg_hw_cfg(struct dwc2_hsotg
*hsotg
)
3102 /* check hardware configuration */
3104 cfg
= readl(hsotg
->regs
+ GHWCFG2
);
3105 hsotg
->num_of_eps
= (cfg
>> 10) & 0xF;
3107 hsotg
->num_of_eps
++;
3109 hsotg
->eps_in
[0] = devm_kzalloc(hsotg
->dev
, sizeof(struct s3c_hsotg_ep
),
3111 if (!hsotg
->eps_in
[0])
3113 /* Same s3c_hsotg_ep is used in both directions for ep0 */
3114 hsotg
->eps_out
[0] = hsotg
->eps_in
[0];
3116 cfg
= readl(hsotg
->regs
+ GHWCFG1
);
3117 for (i
= 1; i
< hsotg
->num_of_eps
; i
++, cfg
>>= 2) {
3119 /* Direction in or both */
3120 if (!(ep_type
& 2)) {
3121 hsotg
->eps_in
[i
] = devm_kzalloc(hsotg
->dev
,
3122 sizeof(struct s3c_hsotg_ep
), GFP_KERNEL
);
3123 if (!hsotg
->eps_in
[i
])
3126 /* Direction out or both */
3127 if (!(ep_type
& 1)) {
3128 hsotg
->eps_out
[i
] = devm_kzalloc(hsotg
->dev
,
3129 sizeof(struct s3c_hsotg_ep
), GFP_KERNEL
);
3130 if (!hsotg
->eps_out
[i
])
3135 cfg
= readl(hsotg
->regs
+ GHWCFG3
);
3136 hsotg
->fifo_mem
= (cfg
>> 16);
3138 cfg
= readl(hsotg
->regs
+ GHWCFG4
);
3139 hsotg
->dedicated_fifos
= (cfg
>> 25) & 1;
3141 dev_info(hsotg
->dev
, "EPs: %d, %s fifos, %d entries in SPRAM\n",
3143 hsotg
->dedicated_fifos
? "dedicated" : "shared",
3149 * s3c_hsotg_dump - dump state of the udc
3150 * @param: The device state
3152 static void s3c_hsotg_dump(struct dwc2_hsotg
*hsotg
)
3155 struct device
*dev
= hsotg
->dev
;
3156 void __iomem
*regs
= hsotg
->regs
;
3160 dev_info(dev
, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3161 readl(regs
+ DCFG
), readl(regs
+ DCTL
),
3162 readl(regs
+ DIEPMSK
));
3164 dev_info(dev
, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
3165 readl(regs
+ GAHBCFG
), readl(regs
+ 0x44));
3167 dev_info(dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3168 readl(regs
+ GRXFSIZ
), readl(regs
+ GNPTXFSIZ
));
3170 /* show periodic fifo settings */
3172 for (idx
= 1; idx
<= 15; idx
++) {
3173 val
= readl(regs
+ DPTXFSIZN(idx
));
3174 dev_info(dev
, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx
,
3175 val
>> FIFOSIZE_DEPTH_SHIFT
,
3176 val
& FIFOSIZE_STARTADDR_MASK
);
3179 for (idx
= 0; idx
< 15; idx
++) {
3181 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx
,
3182 readl(regs
+ DIEPCTL(idx
)),
3183 readl(regs
+ DIEPTSIZ(idx
)),
3184 readl(regs
+ DIEPDMA(idx
)));
3186 val
= readl(regs
+ DOEPCTL(idx
));
3188 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3189 idx
, readl(regs
+ DOEPCTL(idx
)),
3190 readl(regs
+ DOEPTSIZ(idx
)),
3191 readl(regs
+ DOEPDMA(idx
)));
3195 dev_info(dev
, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3196 readl(regs
+ DVBUSDIS
), readl(regs
+ DVBUSPULSE
));
3201 * state_show - debugfs: show overall driver and device state.
3202 * @seq: The seq file to write to.
3203 * @v: Unused parameter.
3205 * This debugfs entry shows the overall state of the hardware and
3206 * some general information about each of the endpoints available
3209 static int state_show(struct seq_file
*seq
, void *v
)
3211 struct dwc2_hsotg
*hsotg
= seq
->private;
3212 void __iomem
*regs
= hsotg
->regs
;
3215 seq_printf(seq
, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
3218 readl(regs
+ DSTS
));
3220 seq_printf(seq
, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
3221 readl(regs
+ DIEPMSK
), readl(regs
+ DOEPMSK
));
3223 seq_printf(seq
, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
3224 readl(regs
+ GINTMSK
),
3225 readl(regs
+ GINTSTS
));
3227 seq_printf(seq
, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
3228 readl(regs
+ DAINTMSK
),
3229 readl(regs
+ DAINT
));
3231 seq_printf(seq
, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3232 readl(regs
+ GNPTXSTS
),
3233 readl(regs
+ GRXSTSR
));
3235 seq_puts(seq
, "\nEndpoint status:\n");
3237 for (idx
= 0; idx
< 15; idx
++) {
3240 in
= readl(regs
+ DIEPCTL(idx
));
3241 out
= readl(regs
+ DOEPCTL(idx
));
3243 seq_printf(seq
, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3246 in
= readl(regs
+ DIEPTSIZ(idx
));
3247 out
= readl(regs
+ DOEPTSIZ(idx
));
3249 seq_printf(seq
, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3252 seq_puts(seq
, "\n");
3258 static int state_open(struct inode
*inode
, struct file
*file
)
3260 return single_open(file
, state_show
, inode
->i_private
);
3263 static const struct file_operations state_fops
= {
3264 .owner
= THIS_MODULE
,
3267 .llseek
= seq_lseek
,
3268 .release
= single_release
,
3272 * fifo_show - debugfs: show the fifo information
3273 * @seq: The seq_file to write data to.
3274 * @v: Unused parameter.
3276 * Show the FIFO information for the overall fifo and all the
3277 * periodic transmission FIFOs.
3279 static int fifo_show(struct seq_file
*seq
, void *v
)
3281 struct dwc2_hsotg
*hsotg
= seq
->private;
3282 void __iomem
*regs
= hsotg
->regs
;
3286 seq_puts(seq
, "Non-periodic FIFOs:\n");
3287 seq_printf(seq
, "RXFIFO: Size %d\n", readl(regs
+ GRXFSIZ
));
3289 val
= readl(regs
+ GNPTXFSIZ
);
3290 seq_printf(seq
, "NPTXFIFO: Size %d, Start 0x%08x\n",
3291 val
>> FIFOSIZE_DEPTH_SHIFT
,
3292 val
& FIFOSIZE_DEPTH_MASK
);
3294 seq_puts(seq
, "\nPeriodic TXFIFOs:\n");
3296 for (idx
= 1; idx
<= 15; idx
++) {
3297 val
= readl(regs
+ DPTXFSIZN(idx
));
3299 seq_printf(seq
, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx
,
3300 val
>> FIFOSIZE_DEPTH_SHIFT
,
3301 val
& FIFOSIZE_STARTADDR_MASK
);
3307 static int fifo_open(struct inode
*inode
, struct file
*file
)
3309 return single_open(file
, fifo_show
, inode
->i_private
);
3312 static const struct file_operations fifo_fops
= {
3313 .owner
= THIS_MODULE
,
3316 .llseek
= seq_lseek
,
3317 .release
= single_release
,
3321 static const char *decode_direction(int is_in
)
3323 return is_in
? "in" : "out";
3327 * ep_show - debugfs: show the state of an endpoint.
3328 * @seq: The seq_file to write data to.
3329 * @v: Unused parameter.
3331 * This debugfs entry shows the state of the given endpoint (one is
3332 * registered for each available).
3334 static int ep_show(struct seq_file
*seq
, void *v
)
3336 struct s3c_hsotg_ep
*ep
= seq
->private;
3337 struct dwc2_hsotg
*hsotg
= ep
->parent
;
3338 struct s3c_hsotg_req
*req
;
3339 void __iomem
*regs
= hsotg
->regs
;
3340 int index
= ep
->index
;
3341 int show_limit
= 15;
3342 unsigned long flags
;
3344 seq_printf(seq
, "Endpoint index %d, named %s, dir %s:\n",
3345 ep
->index
, ep
->ep
.name
, decode_direction(ep
->dir_in
));
3347 /* first show the register state */
3349 seq_printf(seq
, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3350 readl(regs
+ DIEPCTL(index
)),
3351 readl(regs
+ DOEPCTL(index
)));
3353 seq_printf(seq
, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3354 readl(regs
+ DIEPDMA(index
)),
3355 readl(regs
+ DOEPDMA(index
)));
3357 seq_printf(seq
, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3358 readl(regs
+ DIEPINT(index
)),
3359 readl(regs
+ DOEPINT(index
)));
3361 seq_printf(seq
, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3362 readl(regs
+ DIEPTSIZ(index
)),
3363 readl(regs
+ DOEPTSIZ(index
)));
3365 seq_puts(seq
, "\n");
3366 seq_printf(seq
, "mps %d\n", ep
->ep
.maxpacket
);
3367 seq_printf(seq
, "total_data=%ld\n", ep
->total_data
);
3369 seq_printf(seq
, "request list (%p,%p):\n",
3370 ep
->queue
.next
, ep
->queue
.prev
);
3372 spin_lock_irqsave(&hsotg
->lock
, flags
);
3374 list_for_each_entry(req
, &ep
->queue
, queue
) {
3375 if (--show_limit
< 0) {
3376 seq_puts(seq
, "not showing more requests...\n");
3380 seq_printf(seq
, "%c req %p: %d bytes @%p, ",
3381 req
== ep
->req
? '*' : ' ',
3382 req
, req
->req
.length
, req
->req
.buf
);
3383 seq_printf(seq
, "%d done, res %d\n",
3384 req
->req
.actual
, req
->req
.status
);
3387 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3392 static int ep_open(struct inode
*inode
, struct file
*file
)
3394 return single_open(file
, ep_show
, inode
->i_private
);
3397 static const struct file_operations ep_fops
= {
3398 .owner
= THIS_MODULE
,
3401 .llseek
= seq_lseek
,
3402 .release
= single_release
,
3406 * s3c_hsotg_create_debug - create debugfs directory and files
3407 * @hsotg: The driver state
3409 * Create the debugfs files to allow the user to get information
3410 * about the state of the system. The directory name is created
3411 * with the same name as the device itself, in case we end up
3412 * with multiple blocks in future systems.
3414 static void s3c_hsotg_create_debug(struct dwc2_hsotg
*hsotg
)
3416 struct dentry
*root
;
3419 root
= debugfs_create_dir(dev_name(hsotg
->dev
), NULL
);
3420 hsotg
->debug_root
= root
;
3422 dev_err(hsotg
->dev
, "cannot create debug root\n");
3426 /* create general state file */
3428 hsotg
->debug_file
= debugfs_create_file("state", 0444, root
,
3429 hsotg
, &state_fops
);
3431 if (IS_ERR(hsotg
->debug_file
))
3432 dev_err(hsotg
->dev
, "%s: failed to create state\n", __func__
);
3434 hsotg
->debug_fifo
= debugfs_create_file("fifo", 0444, root
,
3437 if (IS_ERR(hsotg
->debug_fifo
))
3438 dev_err(hsotg
->dev
, "%s: failed to create fifo\n", __func__
);
3440 /* Create one file for each out endpoint */
3441 for (epidx
= 0; epidx
< hsotg
->num_of_eps
; epidx
++) {
3442 struct s3c_hsotg_ep
*ep
;
3444 ep
= hsotg
->eps_out
[epidx
];
3446 ep
->debugfs
= debugfs_create_file(ep
->name
, 0444,
3447 root
, ep
, &ep_fops
);
3449 if (IS_ERR(ep
->debugfs
))
3450 dev_err(hsotg
->dev
, "failed to create %s debug file\n",
3454 /* Create one file for each in endpoint. EP0 is handled with out eps */
3455 for (epidx
= 1; epidx
< hsotg
->num_of_eps
; epidx
++) {
3456 struct s3c_hsotg_ep
*ep
;
3458 ep
= hsotg
->eps_in
[epidx
];
3460 ep
->debugfs
= debugfs_create_file(ep
->name
, 0444,
3461 root
, ep
, &ep_fops
);
3463 if (IS_ERR(ep
->debugfs
))
3464 dev_err(hsotg
->dev
, "failed to create %s debug file\n",
3471 * s3c_hsotg_delete_debug - cleanup debugfs entries
3472 * @hsotg: The driver state
3474 * Cleanup (remove) the debugfs files for use on module exit.
3476 static void s3c_hsotg_delete_debug(struct dwc2_hsotg
*hsotg
)
3480 for (epidx
= 0; epidx
< hsotg
->num_of_eps
; epidx
++) {
3481 if (hsotg
->eps_in
[epidx
])
3482 debugfs_remove(hsotg
->eps_in
[epidx
]->debugfs
);
3483 if (hsotg
->eps_out
[epidx
])
3484 debugfs_remove(hsotg
->eps_out
[epidx
]->debugfs
);
3487 debugfs_remove(hsotg
->debug_file
);
3488 debugfs_remove(hsotg
->debug_fifo
);
3489 debugfs_remove(hsotg
->debug_root
);
3493 static void s3c_hsotg_of_probe(struct dwc2_hsotg
*hsotg
)
3495 struct device_node
*np
= hsotg
->dev
->of_node
;
3497 /* Enable dma if requested in device tree */
3498 hsotg
->g_using_dma
= of_property_read_bool(np
, "g-use-dma");
3501 static inline void s3c_hsotg_of_probe(struct dwc2_hsotg
*hsotg
) { }
3505 * dwc2_gadget_init - init function for gadget
3506 * @dwc2: The data structure for the DWC2 driver.
3507 * @irq: The IRQ number for the controller.
3509 int dwc2_gadget_init(struct dwc2_hsotg
*hsotg
, int irq
)
3511 struct device
*dev
= hsotg
->dev
;
3512 struct s3c_hsotg_plat
*plat
= dev
->platform_data
;
3517 /* Set default UTMI width */
3518 hsotg
->phyif
= GUSBCFG_PHYIF16
;
3520 s3c_hsotg_of_probe(hsotg
);
3523 * If platform probe couldn't find a generic PHY or an old style
3524 * USB PHY, fall back to pdata
3526 if (IS_ERR_OR_NULL(hsotg
->phy
) && IS_ERR_OR_NULL(hsotg
->uphy
)) {
3527 plat
= dev_get_platdata(dev
);
3530 "no platform data or transceiver defined\n");
3531 return -EPROBE_DEFER
;
3534 } else if (hsotg
->phy
) {
3536 * If using the generic PHY framework, check if the PHY bus
3537 * width is 8-bit and set the phyif appropriately.
3539 if (phy_get_bus_width(hsotg
->phy
) == 8)
3540 hsotg
->phyif
= GUSBCFG_PHYIF8
;
3543 hsotg
->clk
= devm_clk_get(dev
, "otg");
3544 if (IS_ERR(hsotg
->clk
)) {
3546 dev_dbg(dev
, "cannot get otg clock\n");
3549 hsotg
->gadget
.max_speed
= USB_SPEED_HIGH
;
3550 hsotg
->gadget
.ops
= &s3c_hsotg_gadget_ops
;
3551 hsotg
->gadget
.name
= dev_name(dev
);
3553 /* reset the system */
3555 ret
= clk_prepare_enable(hsotg
->clk
);
3557 dev_err(dev
, "failed to enable otg clk\n");
3564 for (i
= 0; i
< ARRAY_SIZE(hsotg
->supplies
); i
++)
3565 hsotg
->supplies
[i
].supply
= s3c_hsotg_supply_names
[i
];
3567 ret
= devm_regulator_bulk_get(dev
, ARRAY_SIZE(hsotg
->supplies
),
3570 dev_err(dev
, "failed to request supplies: %d\n", ret
);
3574 ret
= regulator_bulk_enable(ARRAY_SIZE(hsotg
->supplies
),
3578 dev_err(dev
, "failed to enable supplies: %d\n", ret
);
3582 /* usb phy enable */
3583 s3c_hsotg_phy_enable(hsotg
);
3585 s3c_hsotg_corereset(hsotg
);
3586 ret
= s3c_hsotg_hw_cfg(hsotg
);
3588 dev_err(hsotg
->dev
, "Hardware configuration failed: %d\n", ret
);
3592 s3c_hsotg_init(hsotg
);
3594 hsotg
->ctrl_buff
= devm_kzalloc(hsotg
->dev
,
3595 DWC2_CTRL_BUFF_SIZE
, GFP_KERNEL
);
3596 if (!hsotg
->ctrl_buff
) {
3597 dev_err(dev
, "failed to allocate ctrl request buff\n");
3602 hsotg
->ep0_buff
= devm_kzalloc(hsotg
->dev
,
3603 DWC2_CTRL_BUFF_SIZE
, GFP_KERNEL
);
3604 if (!hsotg
->ep0_buff
) {
3605 dev_err(dev
, "failed to allocate ctrl reply buff\n");
3610 ret
= devm_request_irq(hsotg
->dev
, irq
, s3c_hsotg_irq
, IRQF_SHARED
,
3611 dev_name(hsotg
->dev
), hsotg
);
3613 s3c_hsotg_phy_disable(hsotg
);
3614 clk_disable_unprepare(hsotg
->clk
);
3615 regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
),
3617 dev_err(dev
, "cannot claim IRQ for gadget\n");
3621 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3623 if (hsotg
->num_of_eps
== 0) {
3624 dev_err(dev
, "wrong number of EPs (zero)\n");
3629 /* setup endpoint information */
3631 INIT_LIST_HEAD(&hsotg
->gadget
.ep_list
);
3632 hsotg
->gadget
.ep0
= &hsotg
->eps_out
[0]->ep
;
3634 /* allocate EP0 request */
3636 hsotg
->ctrl_req
= s3c_hsotg_ep_alloc_request(&hsotg
->eps_out
[0]->ep
,
3638 if (!hsotg
->ctrl_req
) {
3639 dev_err(dev
, "failed to allocate ctrl req\n");
3644 /* initialise the endpoints now the core has been initialised */
3645 for (epnum
= 0; epnum
< hsotg
->num_of_eps
; epnum
++) {
3646 if (hsotg
->eps_in
[epnum
])
3647 s3c_hsotg_initep(hsotg
, hsotg
->eps_in
[epnum
],
3649 if (hsotg
->eps_out
[epnum
])
3650 s3c_hsotg_initep(hsotg
, hsotg
->eps_out
[epnum
],
3654 /* disable power and clock */
3655 s3c_hsotg_phy_disable(hsotg
);
3657 ret
= regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
),
3660 dev_err(dev
, "failed to disable supplies: %d\n", ret
);
3664 ret
= usb_add_gadget_udc(dev
, &hsotg
->gadget
);
3668 s3c_hsotg_create_debug(hsotg
);
3670 s3c_hsotg_dump(hsotg
);
3675 s3c_hsotg_phy_disable(hsotg
);
3677 clk_disable_unprepare(hsotg
->clk
);
3681 EXPORT_SYMBOL_GPL(dwc2_gadget_init
);
3684 * s3c_hsotg_remove - remove function for hsotg driver
3685 * @pdev: The platform information for the driver
3687 int s3c_hsotg_remove(struct dwc2_hsotg
*hsotg
)
3689 usb_del_gadget_udc(&hsotg
->gadget
);
3690 s3c_hsotg_delete_debug(hsotg
);
3691 clk_disable_unprepare(hsotg
->clk
);
3695 EXPORT_SYMBOL_GPL(s3c_hsotg_remove
);
3697 int s3c_hsotg_suspend(struct dwc2_hsotg
*hsotg
)
3699 unsigned long flags
;
3702 mutex_lock(&hsotg
->init_mutex
);
3704 if (hsotg
->driver
) {
3707 dev_info(hsotg
->dev
, "suspending usb gadget %s\n",
3708 hsotg
->driver
->driver
.name
);
3710 spin_lock_irqsave(&hsotg
->lock
, flags
);
3712 s3c_hsotg_core_disconnect(hsotg
);
3713 s3c_hsotg_disconnect(hsotg
);
3714 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3715 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3717 s3c_hsotg_phy_disable(hsotg
);
3719 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++) {
3720 if (hsotg
->eps_in
[ep
])
3721 s3c_hsotg_ep_disable(&hsotg
->eps_in
[ep
]->ep
);
3722 if (hsotg
->eps_out
[ep
])
3723 s3c_hsotg_ep_disable(&hsotg
->eps_out
[ep
]->ep
);
3726 ret
= regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
),
3728 clk_disable(hsotg
->clk
);
3731 mutex_unlock(&hsotg
->init_mutex
);
3735 EXPORT_SYMBOL_GPL(s3c_hsotg_suspend
);
3737 int s3c_hsotg_resume(struct dwc2_hsotg
*hsotg
)
3739 unsigned long flags
;
3742 mutex_lock(&hsotg
->init_mutex
);
3744 if (hsotg
->driver
) {
3745 dev_info(hsotg
->dev
, "resuming usb gadget %s\n",
3746 hsotg
->driver
->driver
.name
);
3748 clk_enable(hsotg
->clk
);
3749 ret
= regulator_bulk_enable(ARRAY_SIZE(hsotg
->supplies
),
3752 s3c_hsotg_phy_enable(hsotg
);
3754 spin_lock_irqsave(&hsotg
->lock
, flags
);
3755 s3c_hsotg_core_init_disconnected(hsotg
);
3757 s3c_hsotg_core_connect(hsotg
);
3758 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3760 mutex_unlock(&hsotg
->init_mutex
);
3764 EXPORT_SYMBOL_GPL(s3c_hsotg_resume
);