2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * S3C USB2.0 High-speed / OtG driver
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/debugfs.h>
24 #include <linux/mutex.h>
25 #include <linux/seq_file.h>
26 #include <linux/delay.h>
28 #include <linux/slab.h>
29 #include <linux/clk.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/of_platform.h>
32 #include <linux/phy/phy.h>
34 #include <linux/usb/ch9.h>
35 #include <linux/usb/gadget.h>
36 #include <linux/usb/phy.h>
37 #include <linux/platform_data/s3c-hsotg.h>
42 /* conversion functions */
43 static inline struct s3c_hsotg_req
*our_req(struct usb_request
*req
)
45 return container_of(req
, struct s3c_hsotg_req
, req
);
48 static inline struct s3c_hsotg_ep
*our_ep(struct usb_ep
*ep
)
50 return container_of(ep
, struct s3c_hsotg_ep
, ep
);
53 static inline struct dwc2_hsotg
*to_hsotg(struct usb_gadget
*gadget
)
55 return container_of(gadget
, struct dwc2_hsotg
, gadget
);
58 static inline void __orr32(void __iomem
*ptr
, u32 val
)
60 writel(readl(ptr
) | val
, ptr
);
63 static inline void __bic32(void __iomem
*ptr
, u32 val
)
65 writel(readl(ptr
) & ~val
, ptr
);
68 /* forward declaration of functions */
69 static void s3c_hsotg_dump(struct dwc2_hsotg
*hsotg
);
72 * using_dma - return the DMA status of the driver.
73 * @hsotg: The driver state.
75 * Return true if we're using DMA.
77 * Currently, we have the DMA support code worked into everywhere
78 * that needs it, but the AMBA DMA implementation in the hardware can
79 * only DMA from 32bit aligned addresses. This means that gadgets such
80 * as the CDC Ethernet cannot work as they often pass packets which are
83 * Unfortunately the choice to use DMA or not is global to the controller
84 * and seems to be only settable when the controller is being put through
85 * a core reset. This means we either need to fix the gadgets to take
86 * account of DMA alignment, or add bounce buffers (yuerk).
88 * Until this issue is sorted out, we always return 'false'.
90 static inline bool using_dma(struct dwc2_hsotg
*hsotg
)
92 return false; /* support is not complete */
96 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
97 * @hsotg: The device state
98 * @ints: A bitmask of the interrupts to enable
100 static void s3c_hsotg_en_gsint(struct dwc2_hsotg
*hsotg
, u32 ints
)
102 u32 gsintmsk
= readl(hsotg
->regs
+ GINTMSK
);
105 new_gsintmsk
= gsintmsk
| ints
;
107 if (new_gsintmsk
!= gsintmsk
) {
108 dev_dbg(hsotg
->dev
, "gsintmsk now 0x%08x\n", new_gsintmsk
);
109 writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
114 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
115 * @hsotg: The device state
116 * @ints: A bitmask of the interrupts to enable
118 static void s3c_hsotg_disable_gsint(struct dwc2_hsotg
*hsotg
, u32 ints
)
120 u32 gsintmsk
= readl(hsotg
->regs
+ GINTMSK
);
123 new_gsintmsk
= gsintmsk
& ~ints
;
125 if (new_gsintmsk
!= gsintmsk
)
126 writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
130 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
131 * @hsotg: The device state
132 * @ep: The endpoint index
133 * @dir_in: True if direction is in.
134 * @en: The enable value, true to enable
136 * Set or clear the mask for an individual endpoint's interrupt
139 static void s3c_hsotg_ctrl_epint(struct dwc2_hsotg
*hsotg
,
140 unsigned int ep
, unsigned int dir_in
,
150 local_irq_save(flags
);
151 daint
= readl(hsotg
->regs
+ DAINTMSK
);
156 writel(daint
, hsotg
->regs
+ DAINTMSK
);
157 local_irq_restore(flags
);
161 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
162 * @hsotg: The device instance.
164 static void s3c_hsotg_init_fifo(struct dwc2_hsotg
*hsotg
)
172 /* set FIFO sizes to 2048/1024 */
174 writel(2048, hsotg
->regs
+ GRXFSIZ
);
175 writel((2048 << FIFOSIZE_STARTADDR_SHIFT
) |
176 (1024 << FIFOSIZE_DEPTH_SHIFT
), hsotg
->regs
+ GNPTXFSIZ
);
179 * arange all the rest of the TX FIFOs, as some versions of this
180 * block have overlapping default addresses. This also ensures
181 * that if the settings have been changed, then they are set to
185 /* start at the end of the GNPTXFSIZ, rounded up */
189 * Because we have not enough memory to have each TX FIFO of size at
190 * least 3072 bytes (the maximum single packet size), we create four
191 * FIFOs of lenght 1024, and four of length 3072 bytes, and assing
192 * them to endpoints dynamically according to maxpacket size value of
196 /* 256*4=1024 bytes FIFO length */
198 for (ep
= 1; ep
<= 4; ep
++) {
200 val
|= size
<< FIFOSIZE_DEPTH_SHIFT
;
201 WARN_ONCE(addr
+ size
> hsotg
->fifo_mem
,
202 "insufficient fifo memory");
205 writel(val
, hsotg
->regs
+ DPTXFSIZN(ep
));
207 /* 768*4=3072 bytes FIFO length */
209 for (ep
= 5; ep
<= 8; ep
++) {
211 val
|= size
<< FIFOSIZE_DEPTH_SHIFT
;
212 WARN_ONCE(addr
+ size
> hsotg
->fifo_mem
,
213 "insufficient fifo memory");
216 writel(val
, hsotg
->regs
+ DPTXFSIZN(ep
));
220 * according to p428 of the design guide, we need to ensure that
221 * all fifos are flushed before continuing
224 writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH
|
225 GRSTCTL_RXFFLSH
, hsotg
->regs
+ GRSTCTL
);
227 /* wait until the fifos are both flushed */
230 val
= readl(hsotg
->regs
+ GRSTCTL
);
232 if ((val
& (GRSTCTL_TXFFLSH
| GRSTCTL_RXFFLSH
)) == 0)
235 if (--timeout
== 0) {
237 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
244 dev_dbg(hsotg
->dev
, "FIFOs reset, timeout at %d\n", timeout
);
248 * @ep: USB endpoint to allocate request for.
249 * @flags: Allocation flags
251 * Allocate a new USB request structure appropriate for the specified endpoint
253 static struct usb_request
*s3c_hsotg_ep_alloc_request(struct usb_ep
*ep
,
256 struct s3c_hsotg_req
*req
;
258 req
= kzalloc(sizeof(struct s3c_hsotg_req
), flags
);
262 INIT_LIST_HEAD(&req
->queue
);
268 * is_ep_periodic - return true if the endpoint is in periodic mode.
269 * @hs_ep: The endpoint to query.
271 * Returns true if the endpoint is in periodic mode, meaning it is being
272 * used for an Interrupt or ISO transfer.
274 static inline int is_ep_periodic(struct s3c_hsotg_ep
*hs_ep
)
276 return hs_ep
->periodic
;
280 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
281 * @hsotg: The device state.
282 * @hs_ep: The endpoint for the request
283 * @hs_req: The request being processed.
285 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
286 * of a request to ensure the buffer is ready for access by the caller.
288 static void s3c_hsotg_unmap_dma(struct dwc2_hsotg
*hsotg
,
289 struct s3c_hsotg_ep
*hs_ep
,
290 struct s3c_hsotg_req
*hs_req
)
292 struct usb_request
*req
= &hs_req
->req
;
294 /* ignore this if we're not moving any data */
295 if (hs_req
->req
.length
== 0)
298 usb_gadget_unmap_request(&hsotg
->gadget
, req
, hs_ep
->dir_in
);
302 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
303 * @hsotg: The controller state.
304 * @hs_ep: The endpoint we're going to write for.
305 * @hs_req: The request to write data for.
307 * This is called when the TxFIFO has some space in it to hold a new
308 * transmission and we have something to give it. The actual setup of
309 * the data size is done elsewhere, so all we have to do is to actually
312 * The return value is zero if there is more space (or nothing was done)
313 * otherwise -ENOSPC is returned if the FIFO space was used up.
315 * This routine is only needed for PIO
317 static int s3c_hsotg_write_fifo(struct dwc2_hsotg
*hsotg
,
318 struct s3c_hsotg_ep
*hs_ep
,
319 struct s3c_hsotg_req
*hs_req
)
321 bool periodic
= is_ep_periodic(hs_ep
);
322 u32 gnptxsts
= readl(hsotg
->regs
+ GNPTXSTS
);
323 int buf_pos
= hs_req
->req
.actual
;
324 int to_write
= hs_ep
->size_loaded
;
330 to_write
-= (buf_pos
- hs_ep
->last_load
);
332 /* if there's nothing to write, get out early */
336 if (periodic
&& !hsotg
->dedicated_fifos
) {
337 u32 epsize
= readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
342 * work out how much data was loaded so we can calculate
343 * how much data is left in the fifo.
346 size_left
= DXEPTSIZ_XFERSIZE_GET(epsize
);
349 * if shared fifo, we cannot write anything until the
350 * previous data has been completely sent.
352 if (hs_ep
->fifo_load
!= 0) {
353 s3c_hsotg_en_gsint(hsotg
, GINTSTS_PTXFEMP
);
357 dev_dbg(hsotg
->dev
, "%s: left=%d, load=%d, fifo=%d, size %d\n",
359 hs_ep
->size_loaded
, hs_ep
->fifo_load
, hs_ep
->fifo_size
);
361 /* how much of the data has moved */
362 size_done
= hs_ep
->size_loaded
- size_left
;
364 /* how much data is left in the fifo */
365 can_write
= hs_ep
->fifo_load
- size_done
;
366 dev_dbg(hsotg
->dev
, "%s: => can_write1=%d\n",
367 __func__
, can_write
);
369 can_write
= hs_ep
->fifo_size
- can_write
;
370 dev_dbg(hsotg
->dev
, "%s: => can_write2=%d\n",
371 __func__
, can_write
);
373 if (can_write
<= 0) {
374 s3c_hsotg_en_gsint(hsotg
, GINTSTS_PTXFEMP
);
377 } else if (hsotg
->dedicated_fifos
&& hs_ep
->index
!= 0) {
378 can_write
= readl(hsotg
->regs
+ DTXFSTS(hs_ep
->index
));
383 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts
) == 0) {
385 "%s: no queue slots available (0x%08x)\n",
388 s3c_hsotg_en_gsint(hsotg
, GINTSTS_NPTXFEMP
);
392 can_write
= GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts
);
393 can_write
*= 4; /* fifo size is in 32bit quantities. */
396 max_transfer
= hs_ep
->ep
.maxpacket
* hs_ep
->mc
;
398 dev_dbg(hsotg
->dev
, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
399 __func__
, gnptxsts
, can_write
, to_write
, max_transfer
);
402 * limit to 512 bytes of data, it seems at least on the non-periodic
403 * FIFO, requests of >512 cause the endpoint to get stuck with a
404 * fragment of the end of the transfer in it.
406 if (can_write
> 512 && !periodic
)
410 * limit the write to one max-packet size worth of data, but allow
411 * the transfer to return that it did not run out of fifo space
414 if (to_write
> max_transfer
) {
415 to_write
= max_transfer
;
417 /* it's needed only when we do not use dedicated fifos */
418 if (!hsotg
->dedicated_fifos
)
419 s3c_hsotg_en_gsint(hsotg
,
420 periodic
? GINTSTS_PTXFEMP
:
424 /* see if we can write data */
426 if (to_write
> can_write
) {
427 to_write
= can_write
;
428 pkt_round
= to_write
% max_transfer
;
431 * Round the write down to an
432 * exact number of packets.
434 * Note, we do not currently check to see if we can ever
435 * write a full packet or not to the FIFO.
439 to_write
-= pkt_round
;
442 * enable correct FIFO interrupt to alert us when there
446 /* it's needed only when we do not use dedicated fifos */
447 if (!hsotg
->dedicated_fifos
)
448 s3c_hsotg_en_gsint(hsotg
,
449 periodic
? GINTSTS_PTXFEMP
:
453 dev_dbg(hsotg
->dev
, "write %d/%d, can_write %d, done %d\n",
454 to_write
, hs_req
->req
.length
, can_write
, buf_pos
);
459 hs_req
->req
.actual
= buf_pos
+ to_write
;
460 hs_ep
->total_data
+= to_write
;
463 hs_ep
->fifo_load
+= to_write
;
465 to_write
= DIV_ROUND_UP(to_write
, 4);
466 data
= hs_req
->req
.buf
+ buf_pos
;
468 iowrite32_rep(hsotg
->regs
+ EPFIFO(hs_ep
->index
), data
, to_write
);
470 return (to_write
>= can_write
) ? -ENOSPC
: 0;
474 * get_ep_limit - get the maximum data legnth for this endpoint
475 * @hs_ep: The endpoint
477 * Return the maximum data that can be queued in one go on a given endpoint
478 * so that transfers that are too long can be split.
480 static unsigned get_ep_limit(struct s3c_hsotg_ep
*hs_ep
)
482 int index
= hs_ep
->index
;
487 maxsize
= DXEPTSIZ_XFERSIZE_LIMIT
+ 1;
488 maxpkt
= DXEPTSIZ_PKTCNT_LIMIT
+ 1;
492 maxpkt
= DIEPTSIZ0_PKTCNT_LIMIT
+ 1;
497 /* we made the constant loading easier above by using +1 */
502 * constrain by packet count if maxpkts*pktsize is greater
503 * than the length register size.
506 if ((maxpkt
* hs_ep
->ep
.maxpacket
) < maxsize
)
507 maxsize
= maxpkt
* hs_ep
->ep
.maxpacket
;
513 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
514 * @hsotg: The controller state.
515 * @hs_ep: The endpoint to process a request for
516 * @hs_req: The request to start.
517 * @continuing: True if we are doing more for the current request.
519 * Start the given request running by setting the endpoint registers
520 * appropriately, and writing any data to the FIFOs.
522 static void s3c_hsotg_start_req(struct dwc2_hsotg
*hsotg
,
523 struct s3c_hsotg_ep
*hs_ep
,
524 struct s3c_hsotg_req
*hs_req
,
527 struct usb_request
*ureq
= &hs_req
->req
;
528 int index
= hs_ep
->index
;
529 int dir_in
= hs_ep
->dir_in
;
539 if (hs_ep
->req
&& !continuing
) {
540 dev_err(hsotg
->dev
, "%s: active request\n", __func__
);
543 } else if (hs_ep
->req
!= hs_req
&& continuing
) {
545 "%s: continue different req\n", __func__
);
551 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
552 epsize_reg
= dir_in
? DIEPTSIZ(index
) : DOEPTSIZ(index
);
554 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
555 __func__
, readl(hsotg
->regs
+ epctrl_reg
), index
,
556 hs_ep
->dir_in
? "in" : "out");
558 /* If endpoint is stalled, we will restart request later */
559 ctrl
= readl(hsotg
->regs
+ epctrl_reg
);
561 if (ctrl
& DXEPCTL_STALL
) {
562 dev_warn(hsotg
->dev
, "%s: ep%d is stalled\n", __func__
, index
);
566 length
= ureq
->length
- ureq
->actual
;
567 dev_dbg(hsotg
->dev
, "ureq->length:%d ureq->actual:%d\n",
568 ureq
->length
, ureq
->actual
);
571 "REQ buf %p len %d dma %pad noi=%d zp=%d snok=%d\n",
572 ureq
->buf
, length
, &ureq
->dma
,
573 ureq
->no_interrupt
, ureq
->zero
, ureq
->short_not_ok
);
575 maxreq
= get_ep_limit(hs_ep
);
576 if (length
> maxreq
) {
577 int round
= maxreq
% hs_ep
->ep
.maxpacket
;
579 dev_dbg(hsotg
->dev
, "%s: length %d, max-req %d, r %d\n",
580 __func__
, length
, maxreq
, round
);
582 /* round down to multiple of packets */
590 packets
= DIV_ROUND_UP(length
, hs_ep
->ep
.maxpacket
);
592 packets
= 1; /* send one packet if length is zero. */
594 if (hs_ep
->isochronous
&& length
> (hs_ep
->mc
* hs_ep
->ep
.maxpacket
)) {
595 dev_err(hsotg
->dev
, "req length > maxpacket*mc\n");
599 if (dir_in
&& index
!= 0)
600 if (hs_ep
->isochronous
)
601 epsize
= DXEPTSIZ_MC(packets
);
603 epsize
= DXEPTSIZ_MC(1);
607 if (index
!= 0 && ureq
->zero
) {
609 * test for the packets being exactly right for the
613 if (length
== (packets
* hs_ep
->ep
.maxpacket
))
617 epsize
|= DXEPTSIZ_PKTCNT(packets
);
618 epsize
|= DXEPTSIZ_XFERSIZE(length
);
620 dev_dbg(hsotg
->dev
, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
621 __func__
, packets
, length
, ureq
->length
, epsize
, epsize_reg
);
623 /* store the request as the current one we're doing */
626 /* write size / packets */
627 writel(epsize
, hsotg
->regs
+ epsize_reg
);
629 if (using_dma(hsotg
) && !continuing
) {
630 unsigned int dma_reg
;
633 * write DMA address to control register, buffer already
634 * synced by s3c_hsotg_ep_queue().
637 dma_reg
= dir_in
? DIEPDMA(index
) : DOEPDMA(index
);
638 writel(ureq
->dma
, hsotg
->regs
+ dma_reg
);
640 dev_dbg(hsotg
->dev
, "%s: %pad => 0x%08x\n",
641 __func__
, &ureq
->dma
, dma_reg
);
644 ctrl
|= DXEPCTL_EPENA
; /* ensure ep enabled */
645 ctrl
|= DXEPCTL_USBACTEP
;
647 dev_dbg(hsotg
->dev
, "setup req:%d\n", hsotg
->setup
);
649 /* For Setup request do not clear NAK */
650 if (hsotg
->setup
&& index
== 0)
653 ctrl
|= DXEPCTL_CNAK
; /* clear NAK set by core */
656 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
657 writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
660 * set these, it seems that DMA support increments past the end
661 * of the packet buffer so we need to calculate the length from
664 hs_ep
->size_loaded
= length
;
665 hs_ep
->last_load
= ureq
->actual
;
667 if (dir_in
&& !using_dma(hsotg
)) {
668 /* set these anyway, we may need them for non-periodic in */
669 hs_ep
->fifo_load
= 0;
671 s3c_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
675 * clear the INTknTXFEmpMsk when we start request, more as a aide
676 * to debugging to see what is going on.
679 writel(DIEPMSK_INTKNTXFEMPMSK
,
680 hsotg
->regs
+ DIEPINT(index
));
683 * Note, trying to clear the NAK here causes problems with transmit
684 * on the S3C6400 ending up with the TXFIFO becoming full.
687 /* check ep is enabled */
688 if (!(readl(hsotg
->regs
+ epctrl_reg
) & DXEPCTL_EPENA
))
690 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
691 index
, readl(hsotg
->regs
+ epctrl_reg
));
693 dev_dbg(hsotg
->dev
, "%s: DXEPCTL=0x%08x\n",
694 __func__
, readl(hsotg
->regs
+ epctrl_reg
));
696 /* enable ep interrupts */
697 s3c_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 1);
701 * s3c_hsotg_map_dma - map the DMA memory being used for the request
702 * @hsotg: The device state.
703 * @hs_ep: The endpoint the request is on.
704 * @req: The request being processed.
706 * We've been asked to queue a request, so ensure that the memory buffer
707 * is correctly setup for DMA. If we've been passed an extant DMA address
708 * then ensure the buffer has been synced to memory. If our buffer has no
709 * DMA memory, then we map the memory and mark our request to allow us to
710 * cleanup on completion.
712 static int s3c_hsotg_map_dma(struct dwc2_hsotg
*hsotg
,
713 struct s3c_hsotg_ep
*hs_ep
,
714 struct usb_request
*req
)
716 struct s3c_hsotg_req
*hs_req
= our_req(req
);
719 /* if the length is zero, ignore the DMA data */
720 if (hs_req
->req
.length
== 0)
723 ret
= usb_gadget_map_request(&hsotg
->gadget
, req
, hs_ep
->dir_in
);
730 dev_err(hsotg
->dev
, "%s: failed to map buffer %p, %d bytes\n",
731 __func__
, req
->buf
, req
->length
);
736 static int s3c_hsotg_ep_queue(struct usb_ep
*ep
, struct usb_request
*req
,
739 struct s3c_hsotg_req
*hs_req
= our_req(req
);
740 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
741 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
744 dev_dbg(hs
->dev
, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
745 ep
->name
, req
, req
->length
, req
->buf
, req
->no_interrupt
,
746 req
->zero
, req
->short_not_ok
);
748 /* initialise status of the request */
749 INIT_LIST_HEAD(&hs_req
->queue
);
751 req
->status
= -EINPROGRESS
;
753 /* if we're using DMA, sync the buffers as necessary */
755 int ret
= s3c_hsotg_map_dma(hs
, hs_ep
, req
);
760 first
= list_empty(&hs_ep
->queue
);
761 list_add_tail(&hs_req
->queue
, &hs_ep
->queue
);
764 s3c_hsotg_start_req(hs
, hs_ep
, hs_req
, false);
769 static int s3c_hsotg_ep_queue_lock(struct usb_ep
*ep
, struct usb_request
*req
,
772 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
773 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
774 unsigned long flags
= 0;
777 spin_lock_irqsave(&hs
->lock
, flags
);
778 ret
= s3c_hsotg_ep_queue(ep
, req
, gfp_flags
);
779 spin_unlock_irqrestore(&hs
->lock
, flags
);
784 static void s3c_hsotg_ep_free_request(struct usb_ep
*ep
,
785 struct usb_request
*req
)
787 struct s3c_hsotg_req
*hs_req
= our_req(req
);
793 * s3c_hsotg_complete_oursetup - setup completion callback
794 * @ep: The endpoint the request was on.
795 * @req: The request completed.
797 * Called on completion of any requests the driver itself
798 * submitted that need cleaning up.
800 static void s3c_hsotg_complete_oursetup(struct usb_ep
*ep
,
801 struct usb_request
*req
)
803 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
804 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
806 dev_dbg(hsotg
->dev
, "%s: ep %p, req %p\n", __func__
, ep
, req
);
808 s3c_hsotg_ep_free_request(ep
, req
);
812 * ep_from_windex - convert control wIndex value to endpoint
813 * @hsotg: The driver state.
814 * @windex: The control request wIndex field (in host order).
816 * Convert the given wIndex into a pointer to an driver endpoint
817 * structure, or return NULL if it is not a valid endpoint.
819 static struct s3c_hsotg_ep
*ep_from_windex(struct dwc2_hsotg
*hsotg
,
822 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[windex
& 0x7F];
823 int dir
= (windex
& USB_DIR_IN
) ? 1 : 0;
824 int idx
= windex
& 0x7F;
829 if (idx
> hsotg
->num_of_eps
)
832 if (idx
&& ep
->dir_in
!= dir
)
839 * s3c_hsotg_send_reply - send reply to control request
840 * @hsotg: The device state
842 * @buff: Buffer for request
843 * @length: Length of reply.
845 * Create a request and queue it on the given endpoint. This is useful as
846 * an internal method of sending replies to certain control requests, etc.
848 static int s3c_hsotg_send_reply(struct dwc2_hsotg
*hsotg
,
849 struct s3c_hsotg_ep
*ep
,
853 struct usb_request
*req
;
856 dev_dbg(hsotg
->dev
, "%s: buff %p, len %d\n", __func__
, buff
, length
);
858 req
= s3c_hsotg_ep_alloc_request(&ep
->ep
, GFP_ATOMIC
);
859 hsotg
->ep0_reply
= req
;
861 dev_warn(hsotg
->dev
, "%s: cannot alloc req\n", __func__
);
865 req
->buf
= hsotg
->ep0_buff
;
866 req
->length
= length
;
867 req
->zero
= 1; /* always do zero-length final transfer */
868 req
->complete
= s3c_hsotg_complete_oursetup
;
871 memcpy(req
->buf
, buff
, length
);
875 ret
= s3c_hsotg_ep_queue(&ep
->ep
, req
, GFP_ATOMIC
);
877 dev_warn(hsotg
->dev
, "%s: cannot queue req\n", __func__
);
885 * s3c_hsotg_process_req_status - process request GET_STATUS
886 * @hsotg: The device state
887 * @ctrl: USB control request
889 static int s3c_hsotg_process_req_status(struct dwc2_hsotg
*hsotg
,
890 struct usb_ctrlrequest
*ctrl
)
892 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
893 struct s3c_hsotg_ep
*ep
;
897 dev_dbg(hsotg
->dev
, "%s: USB_REQ_GET_STATUS\n", __func__
);
900 dev_warn(hsotg
->dev
, "%s: direction out?\n", __func__
);
904 switch (ctrl
->bRequestType
& USB_RECIP_MASK
) {
905 case USB_RECIP_DEVICE
:
906 reply
= cpu_to_le16(0); /* bit 0 => self powered,
907 * bit 1 => remote wakeup */
910 case USB_RECIP_INTERFACE
:
911 /* currently, the data result should be zero */
912 reply
= cpu_to_le16(0);
915 case USB_RECIP_ENDPOINT
:
916 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
920 reply
= cpu_to_le16(ep
->halted
? 1 : 0);
927 if (le16_to_cpu(ctrl
->wLength
) != 2)
930 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, &reply
, 2);
932 dev_err(hsotg
->dev
, "%s: failed to send reply\n", __func__
);
939 static int s3c_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
);
942 * get_ep_head - return the first request on the endpoint
943 * @hs_ep: The controller endpoint to get
945 * Get the first request on the endpoint.
947 static struct s3c_hsotg_req
*get_ep_head(struct s3c_hsotg_ep
*hs_ep
)
949 if (list_empty(&hs_ep
->queue
))
952 return list_first_entry(&hs_ep
->queue
, struct s3c_hsotg_req
, queue
);
956 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
957 * @hsotg: The device state
958 * @ctrl: USB control request
960 static int s3c_hsotg_process_req_feature(struct dwc2_hsotg
*hsotg
,
961 struct usb_ctrlrequest
*ctrl
)
963 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
964 struct s3c_hsotg_req
*hs_req
;
966 bool set
= (ctrl
->bRequest
== USB_REQ_SET_FEATURE
);
967 struct s3c_hsotg_ep
*ep
;
971 dev_dbg(hsotg
->dev
, "%s: %s_FEATURE\n",
972 __func__
, set
? "SET" : "CLEAR");
974 if (ctrl
->bRequestType
== USB_RECIP_ENDPOINT
) {
975 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
977 dev_dbg(hsotg
->dev
, "%s: no endpoint for 0x%04x\n",
978 __func__
, le16_to_cpu(ctrl
->wIndex
));
982 switch (le16_to_cpu(ctrl
->wValue
)) {
983 case USB_ENDPOINT_HALT
:
986 s3c_hsotg_ep_sethalt(&ep
->ep
, set
);
988 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
991 "%s: failed to send reply\n", __func__
);
996 * we have to complete all requests for ep if it was
997 * halted, and the halt was cleared by CLEAR_FEATURE
1000 if (!set
&& halted
) {
1002 * If we have request in progress,
1008 list_del_init(&hs_req
->queue
);
1009 usb_gadget_giveback_request(&ep
->ep
,
1013 /* If we have pending request, then start it */
1014 restart
= !list_empty(&ep
->queue
);
1016 hs_req
= get_ep_head(ep
);
1017 s3c_hsotg_start_req(hsotg
, ep
,
1028 return -ENOENT
; /* currently only deal with endpoint */
1033 static void s3c_hsotg_enqueue_setup(struct dwc2_hsotg
*hsotg
);
1036 * s3c_hsotg_stall_ep0 - stall ep0
1037 * @hsotg: The device state
1039 * Set stall for ep0 as response for setup request.
1041 static void s3c_hsotg_stall_ep0(struct dwc2_hsotg
*hsotg
)
1043 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1047 dev_dbg(hsotg
->dev
, "ep0 stall (dir=%d)\n", ep0
->dir_in
);
1048 reg
= (ep0
->dir_in
) ? DIEPCTL0
: DOEPCTL0
;
1051 * DxEPCTL_Stall will be cleared by EP once it has
1052 * taken effect, so no need to clear later.
1055 ctrl
= readl(hsotg
->regs
+ reg
);
1056 ctrl
|= DXEPCTL_STALL
;
1057 ctrl
|= DXEPCTL_CNAK
;
1058 writel(ctrl
, hsotg
->regs
+ reg
);
1061 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1062 ctrl
, reg
, readl(hsotg
->regs
+ reg
));
1065 * complete won't be called, so we enqueue
1066 * setup request here
1068 s3c_hsotg_enqueue_setup(hsotg
);
1072 * s3c_hsotg_process_control - process a control request
1073 * @hsotg: The device state
1074 * @ctrl: The control request received
1076 * The controller has received the SETUP phase of a control request, and
1077 * needs to work out what to do next (and whether to pass it on to the
1080 static void s3c_hsotg_process_control(struct dwc2_hsotg
*hsotg
,
1081 struct usb_ctrlrequest
*ctrl
)
1083 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1089 dev_dbg(hsotg
->dev
, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1090 ctrl
->bRequest
, ctrl
->bRequestType
,
1091 ctrl
->wValue
, ctrl
->wLength
);
1094 * record the direction of the request, for later use when enquing
1098 ep0
->dir_in
= (ctrl
->bRequestType
& USB_DIR_IN
) ? 1 : 0;
1099 dev_dbg(hsotg
->dev
, "ctrl: dir_in=%d\n", ep0
->dir_in
);
1102 * if we've no data with this request, then the last part of the
1103 * transaction is going to implicitly be IN.
1105 if (ctrl
->wLength
== 0)
1108 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
) {
1109 switch (ctrl
->bRequest
) {
1110 case USB_REQ_SET_ADDRESS
:
1111 dcfg
= readl(hsotg
->regs
+ DCFG
);
1112 dcfg
&= ~DCFG_DEVADDR_MASK
;
1113 dcfg
|= (le16_to_cpu(ctrl
->wValue
) <<
1114 DCFG_DEVADDR_SHIFT
) & DCFG_DEVADDR_MASK
;
1115 writel(dcfg
, hsotg
->regs
+ DCFG
);
1117 dev_info(hsotg
->dev
, "new address %d\n", ctrl
->wValue
);
1119 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1122 case USB_REQ_GET_STATUS
:
1123 ret
= s3c_hsotg_process_req_status(hsotg
, ctrl
);
1126 case USB_REQ_CLEAR_FEATURE
:
1127 case USB_REQ_SET_FEATURE
:
1128 ret
= s3c_hsotg_process_req_feature(hsotg
, ctrl
);
1133 /* as a fallback, try delivering it to the driver to deal with */
1135 if (ret
== 0 && hsotg
->driver
) {
1136 spin_unlock(&hsotg
->lock
);
1137 ret
= hsotg
->driver
->setup(&hsotg
->gadget
, ctrl
);
1138 spin_lock(&hsotg
->lock
);
1140 dev_dbg(hsotg
->dev
, "driver->setup() ret %d\n", ret
);
1144 * the request is either unhandlable, or is not formatted correctly
1145 * so respond with a STALL for the status stage to indicate failure.
1149 s3c_hsotg_stall_ep0(hsotg
);
1153 * s3c_hsotg_complete_setup - completion of a setup transfer
1154 * @ep: The endpoint the request was on.
1155 * @req: The request completed.
1157 * Called on completion of any requests the driver itself submitted for
1160 static void s3c_hsotg_complete_setup(struct usb_ep
*ep
,
1161 struct usb_request
*req
)
1163 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
1164 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
1166 if (req
->status
< 0) {
1167 dev_dbg(hsotg
->dev
, "%s: failed %d\n", __func__
, req
->status
);
1171 spin_lock(&hsotg
->lock
);
1172 if (req
->actual
== 0)
1173 s3c_hsotg_enqueue_setup(hsotg
);
1175 s3c_hsotg_process_control(hsotg
, req
->buf
);
1176 spin_unlock(&hsotg
->lock
);
1180 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1181 * @hsotg: The device state.
1183 * Enqueue a request on EP0 if necessary to received any SETUP packets
1184 * received from the host.
1186 static void s3c_hsotg_enqueue_setup(struct dwc2_hsotg
*hsotg
)
1188 struct usb_request
*req
= hsotg
->ctrl_req
;
1189 struct s3c_hsotg_req
*hs_req
= our_req(req
);
1192 dev_dbg(hsotg
->dev
, "%s: queueing setup request\n", __func__
);
1196 req
->buf
= hsotg
->ctrl_buff
;
1197 req
->complete
= s3c_hsotg_complete_setup
;
1199 if (!list_empty(&hs_req
->queue
)) {
1200 dev_dbg(hsotg
->dev
, "%s already queued???\n", __func__
);
1204 hsotg
->eps
[0].dir_in
= 0;
1206 ret
= s3c_hsotg_ep_queue(&hsotg
->eps
[0].ep
, req
, GFP_ATOMIC
);
1208 dev_err(hsotg
->dev
, "%s: failed queue (%d)\n", __func__
, ret
);
1210 * Don't think there's much we can do other than watch the
1217 * s3c_hsotg_complete_request - complete a request given to us
1218 * @hsotg: The device state.
1219 * @hs_ep: The endpoint the request was on.
1220 * @hs_req: The request to complete.
1221 * @result: The result code (0 => Ok, otherwise errno)
1223 * The given request has finished, so call the necessary completion
1224 * if it has one and then look to see if we can start a new request
1227 * Note, expects the ep to already be locked as appropriate.
1229 static void s3c_hsotg_complete_request(struct dwc2_hsotg
*hsotg
,
1230 struct s3c_hsotg_ep
*hs_ep
,
1231 struct s3c_hsotg_req
*hs_req
,
1237 dev_dbg(hsotg
->dev
, "%s: nothing to complete?\n", __func__
);
1241 dev_dbg(hsotg
->dev
, "complete: ep %p %s, req %p, %d => %p\n",
1242 hs_ep
, hs_ep
->ep
.name
, hs_req
, result
, hs_req
->req
.complete
);
1245 * only replace the status if we've not already set an error
1246 * from a previous transaction
1249 if (hs_req
->req
.status
== -EINPROGRESS
)
1250 hs_req
->req
.status
= result
;
1253 list_del_init(&hs_req
->queue
);
1255 if (using_dma(hsotg
))
1256 s3c_hsotg_unmap_dma(hsotg
, hs_ep
, hs_req
);
1259 * call the complete request with the locks off, just in case the
1260 * request tries to queue more work for this endpoint.
1263 if (hs_req
->req
.complete
) {
1264 spin_unlock(&hsotg
->lock
);
1265 usb_gadget_giveback_request(&hs_ep
->ep
, &hs_req
->req
);
1266 spin_lock(&hsotg
->lock
);
1270 * Look to see if there is anything else to do. Note, the completion
1271 * of the previous request may have caused a new request to be started
1272 * so be careful when doing this.
1275 if (!hs_ep
->req
&& result
>= 0) {
1276 restart
= !list_empty(&hs_ep
->queue
);
1278 hs_req
= get_ep_head(hs_ep
);
1279 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, false);
1285 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1286 * @hsotg: The device state.
1287 * @ep_idx: The endpoint index for the data
1288 * @size: The size of data in the fifo, in bytes
1290 * The FIFO status shows there is data to read from the FIFO for a given
1291 * endpoint, so sort out whether we need to read the data into a request
1292 * that has been made for that endpoint.
1294 static void s3c_hsotg_rx_data(struct dwc2_hsotg
*hsotg
, int ep_idx
, int size
)
1296 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[ep_idx
];
1297 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1298 void __iomem
*fifo
= hsotg
->regs
+ EPFIFO(ep_idx
);
1305 u32 epctl
= readl(hsotg
->regs
+ DOEPCTL(ep_idx
));
1309 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
1310 __func__
, size
, ep_idx
, epctl
);
1312 /* dump the data from the FIFO, we've nothing we can do */
1313 for (ptr
= 0; ptr
< size
; ptr
+= 4)
1320 read_ptr
= hs_req
->req
.actual
;
1321 max_req
= hs_req
->req
.length
- read_ptr
;
1323 dev_dbg(hsotg
->dev
, "%s: read %d/%d, done %d/%d\n",
1324 __func__
, to_read
, max_req
, read_ptr
, hs_req
->req
.length
);
1326 if (to_read
> max_req
) {
1328 * more data appeared than we where willing
1329 * to deal with in this request.
1332 /* currently we don't deal this */
1336 hs_ep
->total_data
+= to_read
;
1337 hs_req
->req
.actual
+= to_read
;
1338 to_read
= DIV_ROUND_UP(to_read
, 4);
1341 * note, we might over-write the buffer end by 3 bytes depending on
1342 * alignment of the data.
1344 ioread32_rep(fifo
, hs_req
->req
.buf
+ read_ptr
, to_read
);
1348 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1349 * @hsotg: The device instance
1350 * @req: The request currently on this endpoint
1352 * Generate a zero-length IN packet request for terminating a SETUP
1355 * Note, since we don't write any data to the TxFIFO, then it is
1356 * currently believed that we do not need to wait for any space in
1359 static void s3c_hsotg_send_zlp(struct dwc2_hsotg
*hsotg
,
1360 struct s3c_hsotg_req
*req
)
1365 dev_warn(hsotg
->dev
, "%s: no request?\n", __func__
);
1369 if (req
->req
.length
== 0) {
1370 hsotg
->eps
[0].sent_zlp
= 1;
1371 s3c_hsotg_enqueue_setup(hsotg
);
1375 hsotg
->eps
[0].dir_in
= 1;
1376 hsotg
->eps
[0].sent_zlp
= 1;
1378 dev_dbg(hsotg
->dev
, "sending zero-length packet\n");
1380 /* issue a zero-sized packet to terminate this */
1381 writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1382 DXEPTSIZ_XFERSIZE(0), hsotg
->regs
+ DIEPTSIZ(0));
1384 ctrl
= readl(hsotg
->regs
+ DIEPCTL0
);
1385 ctrl
|= DXEPCTL_CNAK
; /* clear NAK set by core */
1386 ctrl
|= DXEPCTL_EPENA
; /* ensure ep enabled */
1387 ctrl
|= DXEPCTL_USBACTEP
;
1388 writel(ctrl
, hsotg
->regs
+ DIEPCTL0
);
1392 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1393 * @hsotg: The device instance
1394 * @epnum: The endpoint received from
1395 * @was_setup: Set if processing a SetupDone event.
1397 * The RXFIFO has delivered an OutDone event, which means that the data
1398 * transfer for an OUT endpoint has been completed, either by a short
1399 * packet or by the finish of a transfer.
1401 static void s3c_hsotg_handle_outdone(struct dwc2_hsotg
*hsotg
,
1402 int epnum
, bool was_setup
)
1404 u32 epsize
= readl(hsotg
->regs
+ DOEPTSIZ(epnum
));
1405 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[epnum
];
1406 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1407 struct usb_request
*req
= &hs_req
->req
;
1408 unsigned size_left
= DXEPTSIZ_XFERSIZE_GET(epsize
);
1412 dev_dbg(hsotg
->dev
, "%s: no request active\n", __func__
);
1416 if (using_dma(hsotg
)) {
1420 * Calculate the size of the transfer by checking how much
1421 * is left in the endpoint size register and then working it
1422 * out from the amount we loaded for the transfer.
1424 * We need to do this as DMA pointers are always 32bit aligned
1425 * so may overshoot/undershoot the transfer.
1428 size_done
= hs_ep
->size_loaded
- size_left
;
1429 size_done
+= hs_ep
->last_load
;
1431 req
->actual
= size_done
;
1434 /* if there is more request to do, schedule new transfer */
1435 if (req
->actual
< req
->length
&& size_left
== 0) {
1436 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1438 } else if (epnum
== 0) {
1440 * After was_setup = 1 =>
1441 * set CNAK for non Setup requests
1443 hsotg
->setup
= was_setup
? 0 : 1;
1446 if (req
->actual
< req
->length
&& req
->short_not_ok
) {
1447 dev_dbg(hsotg
->dev
, "%s: got %d/%d (short not ok) => error\n",
1448 __func__
, req
->actual
, req
->length
);
1451 * todo - what should we return here? there's no one else
1452 * even bothering to check the status.
1458 * Condition req->complete != s3c_hsotg_complete_setup says:
1459 * send ZLP when we have an asynchronous request from gadget
1461 if (!was_setup
&& req
->complete
!= s3c_hsotg_complete_setup
)
1462 s3c_hsotg_send_zlp(hsotg
, hs_req
);
1465 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, result
);
1469 * s3c_hsotg_read_frameno - read current frame number
1470 * @hsotg: The device instance
1472 * Return the current frame number
1474 static u32
s3c_hsotg_read_frameno(struct dwc2_hsotg
*hsotg
)
1478 dsts
= readl(hsotg
->regs
+ DSTS
);
1479 dsts
&= DSTS_SOFFN_MASK
;
1480 dsts
>>= DSTS_SOFFN_SHIFT
;
1486 * s3c_hsotg_handle_rx - RX FIFO has data
1487 * @hsotg: The device instance
1489 * The IRQ handler has detected that the RX FIFO has some data in it
1490 * that requires processing, so find out what is in there and do the
1493 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1494 * chunks, so if you have x packets received on an endpoint you'll get x
1495 * FIFO events delivered, each with a packet's worth of data in it.
1497 * When using DMA, we should not be processing events from the RXFIFO
1498 * as the actual data should be sent to the memory directly and we turn
1499 * on the completion interrupts to get notifications of transfer completion.
1501 static void s3c_hsotg_handle_rx(struct dwc2_hsotg
*hsotg
)
1503 u32 grxstsr
= readl(hsotg
->regs
+ GRXSTSP
);
1504 u32 epnum
, status
, size
;
1506 WARN_ON(using_dma(hsotg
));
1508 epnum
= grxstsr
& GRXSTS_EPNUM_MASK
;
1509 status
= grxstsr
& GRXSTS_PKTSTS_MASK
;
1511 size
= grxstsr
& GRXSTS_BYTECNT_MASK
;
1512 size
>>= GRXSTS_BYTECNT_SHIFT
;
1515 dev_dbg(hsotg
->dev
, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1516 __func__
, grxstsr
, size
, epnum
);
1518 switch ((status
& GRXSTS_PKTSTS_MASK
) >> GRXSTS_PKTSTS_SHIFT
) {
1519 case GRXSTS_PKTSTS_GLOBALOUTNAK
:
1520 dev_dbg(hsotg
->dev
, "GLOBALOUTNAK\n");
1523 case GRXSTS_PKTSTS_OUTDONE
:
1524 dev_dbg(hsotg
->dev
, "OutDone (Frame=0x%08x)\n",
1525 s3c_hsotg_read_frameno(hsotg
));
1527 if (!using_dma(hsotg
))
1528 s3c_hsotg_handle_outdone(hsotg
, epnum
, false);
1531 case GRXSTS_PKTSTS_SETUPDONE
:
1533 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1534 s3c_hsotg_read_frameno(hsotg
),
1535 readl(hsotg
->regs
+ DOEPCTL(0)));
1537 s3c_hsotg_handle_outdone(hsotg
, epnum
, true);
1540 case GRXSTS_PKTSTS_OUTRX
:
1541 s3c_hsotg_rx_data(hsotg
, epnum
, size
);
1544 case GRXSTS_PKTSTS_SETUPRX
:
1546 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1547 s3c_hsotg_read_frameno(hsotg
),
1548 readl(hsotg
->regs
+ DOEPCTL(0)));
1550 s3c_hsotg_rx_data(hsotg
, epnum
, size
);
1554 dev_warn(hsotg
->dev
, "%s: unknown status %08x\n",
1557 s3c_hsotg_dump(hsotg
);
1563 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1564 * @mps: The maximum packet size in bytes.
1566 static u32
s3c_hsotg_ep0_mps(unsigned int mps
)
1570 return D0EPCTL_MPS_64
;
1572 return D0EPCTL_MPS_32
;
1574 return D0EPCTL_MPS_16
;
1576 return D0EPCTL_MPS_8
;
1579 /* bad max packet size, warn and return invalid result */
1585 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1586 * @hsotg: The driver state.
1587 * @ep: The index number of the endpoint
1588 * @mps: The maximum packet size in bytes
1590 * Configure the maximum packet size for the given endpoint, updating
1591 * the hardware control registers to reflect this.
1593 static void s3c_hsotg_set_ep_maxpacket(struct dwc2_hsotg
*hsotg
,
1594 unsigned int ep
, unsigned int mps
)
1596 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[ep
];
1597 void __iomem
*regs
= hsotg
->regs
;
1603 /* EP0 is a special case */
1604 mpsval
= s3c_hsotg_ep0_mps(mps
);
1607 hs_ep
->ep
.maxpacket
= mps
;
1610 mpsval
= mps
& DXEPCTL_MPS_MASK
;
1613 mcval
= ((mps
>> 11) & 0x3) + 1;
1617 hs_ep
->ep
.maxpacket
= mpsval
;
1621 * update both the in and out endpoint controldir_ registers, even
1622 * if one of the directions may not be in use.
1625 reg
= readl(regs
+ DIEPCTL(ep
));
1626 reg
&= ~DXEPCTL_MPS_MASK
;
1628 writel(reg
, regs
+ DIEPCTL(ep
));
1631 reg
= readl(regs
+ DOEPCTL(ep
));
1632 reg
&= ~DXEPCTL_MPS_MASK
;
1634 writel(reg
, regs
+ DOEPCTL(ep
));
1640 dev_err(hsotg
->dev
, "ep%d: bad mps of %d\n", ep
, mps
);
1644 * s3c_hsotg_txfifo_flush - flush Tx FIFO
1645 * @hsotg: The driver state
1646 * @idx: The index for the endpoint (0..15)
1648 static void s3c_hsotg_txfifo_flush(struct dwc2_hsotg
*hsotg
, unsigned int idx
)
1653 writel(GRSTCTL_TXFNUM(idx
) | GRSTCTL_TXFFLSH
,
1654 hsotg
->regs
+ GRSTCTL
);
1656 /* wait until the fifo is flushed */
1660 val
= readl(hsotg
->regs
+ GRSTCTL
);
1662 if ((val
& (GRSTCTL_TXFFLSH
)) == 0)
1665 if (--timeout
== 0) {
1667 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1677 * s3c_hsotg_trytx - check to see if anything needs transmitting
1678 * @hsotg: The driver state
1679 * @hs_ep: The driver endpoint to check.
1681 * Check to see if there is a request that has data to send, and if so
1682 * make an attempt to write data into the FIFO.
1684 static int s3c_hsotg_trytx(struct dwc2_hsotg
*hsotg
,
1685 struct s3c_hsotg_ep
*hs_ep
)
1687 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1689 if (!hs_ep
->dir_in
|| !hs_req
) {
1691 * if request is not enqueued, we disable interrupts
1692 * for endpoints, excepting ep0
1694 if (hs_ep
->index
!= 0)
1695 s3c_hsotg_ctrl_epint(hsotg
, hs_ep
->index
,
1700 if (hs_req
->req
.actual
< hs_req
->req
.length
) {
1701 dev_dbg(hsotg
->dev
, "trying to write more for ep%d\n",
1703 return s3c_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
1710 * s3c_hsotg_complete_in - complete IN transfer
1711 * @hsotg: The device state.
1712 * @hs_ep: The endpoint that has just completed.
1714 * An IN transfer has been completed, update the transfer's state and then
1715 * call the relevant completion routines.
1717 static void s3c_hsotg_complete_in(struct dwc2_hsotg
*hsotg
,
1718 struct s3c_hsotg_ep
*hs_ep
)
1720 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1721 u32 epsize
= readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
1722 int size_left
, size_done
;
1725 dev_dbg(hsotg
->dev
, "XferCompl but no req\n");
1729 /* Finish ZLP handling for IN EP0 transactions */
1730 if (hsotg
->eps
[0].sent_zlp
) {
1731 dev_dbg(hsotg
->dev
, "zlp packet received\n");
1732 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
1737 * Calculate the size of the transfer by checking how much is left
1738 * in the endpoint size register and then working it out from
1739 * the amount we loaded for the transfer.
1741 * We do this even for DMA, as the transfer may have incremented
1742 * past the end of the buffer (DMA transfers are always 32bit
1746 size_left
= DXEPTSIZ_XFERSIZE_GET(epsize
);
1748 size_done
= hs_ep
->size_loaded
- size_left
;
1749 size_done
+= hs_ep
->last_load
;
1751 if (hs_req
->req
.actual
!= size_done
)
1752 dev_dbg(hsotg
->dev
, "%s: adjusting size done %d => %d\n",
1753 __func__
, hs_req
->req
.actual
, size_done
);
1755 hs_req
->req
.actual
= size_done
;
1756 dev_dbg(hsotg
->dev
, "req->length:%d req->actual:%d req->zero:%d\n",
1757 hs_req
->req
.length
, hs_req
->req
.actual
, hs_req
->req
.zero
);
1760 * Check if dealing with Maximum Packet Size(MPS) IN transfer at EP0
1761 * When sent data is a multiple MPS size (e.g. 64B ,128B ,192B
1762 * ,256B ... ), after last MPS sized packet send IN ZLP packet to
1763 * inform the host that no more data is available.
1764 * The state of req.zero member is checked to be sure that the value to
1765 * send is smaller than wValue expected from host.
1766 * Check req.length to NOT send another ZLP when the current one is
1767 * under completion (the one for which this completion has been called).
1769 if (hs_req
->req
.length
&& hs_ep
->index
== 0 && hs_req
->req
.zero
&&
1770 hs_req
->req
.length
== hs_req
->req
.actual
&&
1771 !(hs_req
->req
.length
% hs_ep
->ep
.maxpacket
)) {
1773 dev_dbg(hsotg
->dev
, "ep0 zlp IN packet sent\n");
1774 s3c_hsotg_send_zlp(hsotg
, hs_req
);
1779 if (!size_left
&& hs_req
->req
.actual
< hs_req
->req
.length
) {
1780 dev_dbg(hsotg
->dev
, "%s trying more for req...\n", __func__
);
1781 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1783 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
1787 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1788 * @hsotg: The driver state
1789 * @idx: The index for the endpoint (0..15)
1790 * @dir_in: Set if this is an IN endpoint
1792 * Process and clear any interrupt pending for an individual endpoint
1794 static void s3c_hsotg_epint(struct dwc2_hsotg
*hsotg
, unsigned int idx
,
1797 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[idx
];
1798 u32 epint_reg
= dir_in
? DIEPINT(idx
) : DOEPINT(idx
);
1799 u32 epctl_reg
= dir_in
? DIEPCTL(idx
) : DOEPCTL(idx
);
1800 u32 epsiz_reg
= dir_in
? DIEPTSIZ(idx
) : DOEPTSIZ(idx
);
1804 ints
= readl(hsotg
->regs
+ epint_reg
);
1805 ctrl
= readl(hsotg
->regs
+ epctl_reg
);
1807 /* Clear endpoint interrupts */
1808 writel(ints
, hsotg
->regs
+ epint_reg
);
1810 dev_dbg(hsotg
->dev
, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1811 __func__
, idx
, dir_in
? "in" : "out", ints
);
1813 /* Don't process XferCompl interrupt if it is a setup packet */
1814 if (idx
== 0 && (ints
& (DXEPINT_SETUP
| DXEPINT_SETUP_RCVD
)))
1815 ints
&= ~DXEPINT_XFERCOMPL
;
1817 if (ints
& DXEPINT_XFERCOMPL
) {
1818 if (hs_ep
->isochronous
&& hs_ep
->interval
== 1) {
1819 if (ctrl
& DXEPCTL_EOFRNUM
)
1820 ctrl
|= DXEPCTL_SETEVENFR
;
1822 ctrl
|= DXEPCTL_SETODDFR
;
1823 writel(ctrl
, hsotg
->regs
+ epctl_reg
);
1827 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
1828 __func__
, readl(hsotg
->regs
+ epctl_reg
),
1829 readl(hsotg
->regs
+ epsiz_reg
));
1832 * we get OutDone from the FIFO, so we only need to look
1833 * at completing IN requests here
1836 s3c_hsotg_complete_in(hsotg
, hs_ep
);
1838 if (idx
== 0 && !hs_ep
->req
)
1839 s3c_hsotg_enqueue_setup(hsotg
);
1840 } else if (using_dma(hsotg
)) {
1842 * We're using DMA, we need to fire an OutDone here
1843 * as we ignore the RXFIFO.
1846 s3c_hsotg_handle_outdone(hsotg
, idx
, false);
1850 if (ints
& DXEPINT_EPDISBLD
) {
1851 dev_dbg(hsotg
->dev
, "%s: EPDisbld\n", __func__
);
1854 int epctl
= readl(hsotg
->regs
+ epctl_reg
);
1856 s3c_hsotg_txfifo_flush(hsotg
, hs_ep
->fifo_index
);
1858 if ((epctl
& DXEPCTL_STALL
) &&
1859 (epctl
& DXEPCTL_EPTYPE_BULK
)) {
1860 int dctl
= readl(hsotg
->regs
+ DCTL
);
1862 dctl
|= DCTL_CGNPINNAK
;
1863 writel(dctl
, hsotg
->regs
+ DCTL
);
1868 if (ints
& DXEPINT_AHBERR
)
1869 dev_dbg(hsotg
->dev
, "%s: AHBErr\n", __func__
);
1871 if (ints
& DXEPINT_SETUP
) { /* Setup or Timeout */
1872 dev_dbg(hsotg
->dev
, "%s: Setup/Timeout\n", __func__
);
1874 if (using_dma(hsotg
) && idx
== 0) {
1876 * this is the notification we've received a
1877 * setup packet. In non-DMA mode we'd get this
1878 * from the RXFIFO, instead we need to process
1885 s3c_hsotg_handle_outdone(hsotg
, 0, true);
1889 if (ints
& DXEPINT_BACK2BACKSETUP
)
1890 dev_dbg(hsotg
->dev
, "%s: B2BSetup/INEPNakEff\n", __func__
);
1892 if (dir_in
&& !hs_ep
->isochronous
) {
1893 /* not sure if this is important, but we'll clear it anyway */
1894 if (ints
& DIEPMSK_INTKNTXFEMPMSK
) {
1895 dev_dbg(hsotg
->dev
, "%s: ep%d: INTknTXFEmpMsk\n",
1899 /* this probably means something bad is happening */
1900 if (ints
& DIEPMSK_INTKNEPMISMSK
) {
1901 dev_warn(hsotg
->dev
, "%s: ep%d: INTknEP\n",
1905 /* FIFO has space or is empty (see GAHBCFG) */
1906 if (hsotg
->dedicated_fifos
&&
1907 ints
& DIEPMSK_TXFIFOEMPTY
) {
1908 dev_dbg(hsotg
->dev
, "%s: ep%d: TxFIFOEmpty\n",
1910 if (!using_dma(hsotg
))
1911 s3c_hsotg_trytx(hsotg
, hs_ep
);
1917 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
1918 * @hsotg: The device state.
1920 * Handle updating the device settings after the enumeration phase has
1923 static void s3c_hsotg_irq_enumdone(struct dwc2_hsotg
*hsotg
)
1925 u32 dsts
= readl(hsotg
->regs
+ DSTS
);
1926 int ep0_mps
= 0, ep_mps
= 8;
1929 * This should signal the finish of the enumeration phase
1930 * of the USB handshaking, so we should now know what rate
1934 dev_dbg(hsotg
->dev
, "EnumDone (DSTS=0x%08x)\n", dsts
);
1937 * note, since we're limited by the size of transfer on EP0, and
1938 * it seems IN transfers must be a even number of packets we do
1939 * not advertise a 64byte MPS on EP0.
1942 /* catch both EnumSpd_FS and EnumSpd_FS48 */
1943 switch (dsts
& DSTS_ENUMSPD_MASK
) {
1944 case DSTS_ENUMSPD_FS
:
1945 case DSTS_ENUMSPD_FS48
:
1946 hsotg
->gadget
.speed
= USB_SPEED_FULL
;
1947 ep0_mps
= EP0_MPS_LIMIT
;
1951 case DSTS_ENUMSPD_HS
:
1952 hsotg
->gadget
.speed
= USB_SPEED_HIGH
;
1953 ep0_mps
= EP0_MPS_LIMIT
;
1957 case DSTS_ENUMSPD_LS
:
1958 hsotg
->gadget
.speed
= USB_SPEED_LOW
;
1960 * note, we don't actually support LS in this driver at the
1961 * moment, and the documentation seems to imply that it isn't
1962 * supported by the PHYs on some of the devices.
1966 dev_info(hsotg
->dev
, "new device is %s\n",
1967 usb_speed_string(hsotg
->gadget
.speed
));
1970 * we should now know the maximum packet size for an
1971 * endpoint, so set the endpoints to a default value.
1976 s3c_hsotg_set_ep_maxpacket(hsotg
, 0, ep0_mps
);
1977 for (i
= 1; i
< hsotg
->num_of_eps
; i
++)
1978 s3c_hsotg_set_ep_maxpacket(hsotg
, i
, ep_mps
);
1981 /* ensure after enumeration our EP0 is active */
1983 s3c_hsotg_enqueue_setup(hsotg
);
1985 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1986 readl(hsotg
->regs
+ DIEPCTL0
),
1987 readl(hsotg
->regs
+ DOEPCTL0
));
1991 * kill_all_requests - remove all requests from the endpoint's queue
1992 * @hsotg: The device state.
1993 * @ep: The endpoint the requests may be on.
1994 * @result: The result code to use.
1996 * Go through the requests on the given endpoint and mark them
1997 * completed with the given result code.
1999 static void kill_all_requests(struct dwc2_hsotg
*hsotg
,
2000 struct s3c_hsotg_ep
*ep
,
2003 struct s3c_hsotg_req
*req
, *treq
;
2008 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
)
2009 s3c_hsotg_complete_request(hsotg
, ep
, req
,
2012 if (!hsotg
->dedicated_fifos
)
2014 size
= (readl(hsotg
->regs
+ DTXFSTS(ep
->index
)) & 0xffff) * 4;
2015 if (size
< ep
->fifo_size
)
2016 s3c_hsotg_txfifo_flush(hsotg
, ep
->fifo_index
);
2020 * s3c_hsotg_disconnect - disconnect service
2021 * @hsotg: The device state.
2023 * The device has been disconnected. Remove all current
2024 * transactions and signal the gadget driver that this
2027 void s3c_hsotg_disconnect(struct dwc2_hsotg
*hsotg
)
2031 if (!hsotg
->connected
)
2034 hsotg
->connected
= 0;
2035 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++)
2036 kill_all_requests(hsotg
, &hsotg
->eps
[ep
], -ESHUTDOWN
);
2038 call_gadget(hsotg
, disconnect
);
2040 EXPORT_SYMBOL_GPL(s3c_hsotg_disconnect
);
2043 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2044 * @hsotg: The device state:
2045 * @periodic: True if this is a periodic FIFO interrupt
2047 static void s3c_hsotg_irq_fifoempty(struct dwc2_hsotg
*hsotg
, bool periodic
)
2049 struct s3c_hsotg_ep
*ep
;
2052 /* look through for any more data to transmit */
2054 for (epno
= 0; epno
< hsotg
->num_of_eps
; epno
++) {
2055 ep
= &hsotg
->eps
[epno
];
2060 if ((periodic
&& !ep
->periodic
) ||
2061 (!periodic
&& ep
->periodic
))
2064 ret
= s3c_hsotg_trytx(hsotg
, ep
);
2070 /* IRQ flags which will trigger a retry around the IRQ loop */
2071 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
2076 * s3c_hsotg_corereset - issue softreset to the core
2077 * @hsotg: The device state
2079 * Issue a soft reset to the core, and await the core finishing it.
2081 static int s3c_hsotg_corereset(struct dwc2_hsotg
*hsotg
)
2086 dev_dbg(hsotg
->dev
, "resetting core\n");
2088 /* issue soft reset */
2089 writel(GRSTCTL_CSFTRST
, hsotg
->regs
+ GRSTCTL
);
2093 grstctl
= readl(hsotg
->regs
+ GRSTCTL
);
2094 } while ((grstctl
& GRSTCTL_CSFTRST
) && timeout
-- > 0);
2096 if (grstctl
& GRSTCTL_CSFTRST
) {
2097 dev_err(hsotg
->dev
, "Failed to get CSftRst asserted\n");
2104 u32 grstctl
= readl(hsotg
->regs
+ GRSTCTL
);
2106 if (timeout
-- < 0) {
2107 dev_info(hsotg
->dev
,
2108 "%s: reset failed, GRSTCTL=%08x\n",
2113 if (!(grstctl
& GRSTCTL_AHBIDLE
))
2116 break; /* reset done */
2119 dev_dbg(hsotg
->dev
, "reset successful\n");
2124 * s3c_hsotg_core_init - issue softreset to the core
2125 * @hsotg: The device state
2127 * Issue a soft reset to the core, and await the core finishing it.
2129 void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg
*hsotg
)
2131 s3c_hsotg_corereset(hsotg
);
2134 * we must now enable ep0 ready for host detection and then
2135 * set configuration.
2138 /* set the PLL on, remove the HNP/SRP and set the PHY */
2139 writel(hsotg
->phyif
| GUSBCFG_TOUTCAL(7) |
2140 (0x5 << 10), hsotg
->regs
+ GUSBCFG
);
2142 s3c_hsotg_init_fifo(hsotg
);
2144 __orr32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
2146 writel(1 << 18 | DCFG_DEVSPD_HS
, hsotg
->regs
+ DCFG
);
2148 /* Clear any pending OTG interrupts */
2149 writel(0xffffffff, hsotg
->regs
+ GOTGINT
);
2151 /* Clear any pending interrupts */
2152 writel(0xffffffff, hsotg
->regs
+ GINTSTS
);
2154 writel(GINTSTS_ERLYSUSP
| GINTSTS_SESSREQINT
|
2155 GINTSTS_GOUTNAKEFF
| GINTSTS_GINNAKEFF
|
2156 GINTSTS_CONIDSTSCHNG
| GINTSTS_USBRST
|
2157 GINTSTS_ENUMDONE
| GINTSTS_OTGINT
|
2158 GINTSTS_USBSUSP
| GINTSTS_WKUPINT
,
2159 hsotg
->regs
+ GINTMSK
);
2161 if (using_dma(hsotg
))
2162 writel(GAHBCFG_GLBL_INTR_EN
| GAHBCFG_DMA_EN
|
2163 (GAHBCFG_HBSTLEN_INCR4
<< GAHBCFG_HBSTLEN_SHIFT
),
2164 hsotg
->regs
+ GAHBCFG
);
2166 writel(((hsotg
->dedicated_fifos
) ? (GAHBCFG_NP_TXF_EMP_LVL
|
2167 GAHBCFG_P_TXF_EMP_LVL
) : 0) |
2168 GAHBCFG_GLBL_INTR_EN
,
2169 hsotg
->regs
+ GAHBCFG
);
2172 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2173 * when we have no data to transfer. Otherwise we get being flooded by
2177 writel(((hsotg
->dedicated_fifos
&& !using_dma(hsotg
)) ?
2178 DIEPMSK_TXFIFOEMPTY
| DIEPMSK_INTKNTXFEMPMSK
: 0) |
2179 DIEPMSK_EPDISBLDMSK
| DIEPMSK_XFERCOMPLMSK
|
2180 DIEPMSK_TIMEOUTMSK
| DIEPMSK_AHBERRMSK
|
2181 DIEPMSK_INTKNEPMISMSK
,
2182 hsotg
->regs
+ DIEPMSK
);
2185 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2186 * DMA mode we may need this.
2188 writel((using_dma(hsotg
) ? (DIEPMSK_XFERCOMPLMSK
|
2189 DIEPMSK_TIMEOUTMSK
) : 0) |
2190 DOEPMSK_EPDISBLDMSK
| DOEPMSK_AHBERRMSK
|
2192 hsotg
->regs
+ DOEPMSK
);
2194 writel(0, hsotg
->regs
+ DAINTMSK
);
2196 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2197 readl(hsotg
->regs
+ DIEPCTL0
),
2198 readl(hsotg
->regs
+ DOEPCTL0
));
2200 /* enable in and out endpoint interrupts */
2201 s3c_hsotg_en_gsint(hsotg
, GINTSTS_OEPINT
| GINTSTS_IEPINT
);
2204 * Enable the RXFIFO when in slave mode, as this is how we collect
2205 * the data. In DMA mode, we get events from the FIFO but also
2206 * things we cannot process, so do not use it.
2208 if (!using_dma(hsotg
))
2209 s3c_hsotg_en_gsint(hsotg
, GINTSTS_RXFLVL
);
2211 /* Enable interrupts for EP0 in and out */
2212 s3c_hsotg_ctrl_epint(hsotg
, 0, 0, 1);
2213 s3c_hsotg_ctrl_epint(hsotg
, 0, 1, 1);
2215 __orr32(hsotg
->regs
+ DCTL
, DCTL_PWRONPRGDONE
);
2216 udelay(10); /* see openiboot */
2217 __bic32(hsotg
->regs
+ DCTL
, DCTL_PWRONPRGDONE
);
2219 dev_dbg(hsotg
->dev
, "DCTL=0x%08x\n", readl(hsotg
->regs
+ DCTL
));
2222 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2223 * writing to the EPCTL register..
2226 /* set to read 1 8byte packet */
2227 writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2228 DXEPTSIZ_XFERSIZE(8), hsotg
->regs
+ DOEPTSIZ0
);
2230 writel(s3c_hsotg_ep0_mps(hsotg
->eps
[0].ep
.maxpacket
) |
2231 DXEPCTL_CNAK
| DXEPCTL_EPENA
|
2233 hsotg
->regs
+ DOEPCTL0
);
2235 /* enable, but don't activate EP0in */
2236 writel(s3c_hsotg_ep0_mps(hsotg
->eps
[0].ep
.maxpacket
) |
2237 DXEPCTL_USBACTEP
, hsotg
->regs
+ DIEPCTL0
);
2239 s3c_hsotg_enqueue_setup(hsotg
);
2241 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2242 readl(hsotg
->regs
+ DIEPCTL0
),
2243 readl(hsotg
->regs
+ DOEPCTL0
));
2245 /* clear global NAKs */
2246 writel(DCTL_CGOUTNAK
| DCTL_CGNPINNAK
| DCTL_SFTDISCON
,
2247 hsotg
->regs
+ DCTL
);
2249 /* must be at-least 3ms to allow bus to see disconnect */
2252 hsotg
->last_rst
= jiffies
;
2255 static void s3c_hsotg_core_disconnect(struct dwc2_hsotg
*hsotg
)
2257 /* set the soft-disconnect bit */
2258 __orr32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
2261 void s3c_hsotg_core_connect(struct dwc2_hsotg
*hsotg
)
2263 /* remove the soft-disconnect and let's go */
2264 __bic32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
2268 * s3c_hsotg_irq - handle device interrupt
2269 * @irq: The IRQ number triggered
2270 * @pw: The pw value when registered the handler.
2272 static irqreturn_t
s3c_hsotg_irq(int irq
, void *pw
)
2274 struct dwc2_hsotg
*hsotg
= pw
;
2275 int retry_count
= 8;
2279 spin_lock(&hsotg
->lock
);
2281 gintsts
= readl(hsotg
->regs
+ GINTSTS
);
2282 gintmsk
= readl(hsotg
->regs
+ GINTMSK
);
2284 dev_dbg(hsotg
->dev
, "%s: %08x %08x (%08x) retry %d\n",
2285 __func__
, gintsts
, gintsts
& gintmsk
, gintmsk
, retry_count
);
2289 if (gintsts
& GINTSTS_ENUMDONE
) {
2290 writel(GINTSTS_ENUMDONE
, hsotg
->regs
+ GINTSTS
);
2292 s3c_hsotg_irq_enumdone(hsotg
);
2293 hsotg
->connected
= 1;
2296 if (gintsts
& (GINTSTS_OEPINT
| GINTSTS_IEPINT
)) {
2297 u32 daint
= readl(hsotg
->regs
+ DAINT
);
2298 u32 daintmsk
= readl(hsotg
->regs
+ DAINTMSK
);
2299 u32 daint_out
, daint_in
;
2303 daint_out
= daint
>> DAINT_OUTEP_SHIFT
;
2304 daint_in
= daint
& ~(daint_out
<< DAINT_OUTEP_SHIFT
);
2306 dev_dbg(hsotg
->dev
, "%s: daint=%08x\n", __func__
, daint
);
2308 for (ep
= 0; ep
< 15 && daint_out
; ep
++, daint_out
>>= 1) {
2310 s3c_hsotg_epint(hsotg
, ep
, 0);
2313 for (ep
= 0; ep
< 15 && daint_in
; ep
++, daint_in
>>= 1) {
2315 s3c_hsotg_epint(hsotg
, ep
, 1);
2319 if (gintsts
& GINTSTS_USBRST
) {
2321 u32 usb_status
= readl(hsotg
->regs
+ GOTGCTL
);
2323 dev_dbg(hsotg
->dev
, "%s: USBRst\n", __func__
);
2324 dev_dbg(hsotg
->dev
, "GNPTXSTS=%08x\n",
2325 readl(hsotg
->regs
+ GNPTXSTS
));
2327 writel(GINTSTS_USBRST
, hsotg
->regs
+ GINTSTS
);
2329 if (usb_status
& GOTGCTL_BSESVLD
) {
2330 if (time_after(jiffies
, hsotg
->last_rst
+
2331 msecs_to_jiffies(200))) {
2333 kill_all_requests(hsotg
, &hsotg
->eps
[0],
2336 s3c_hsotg_core_init_disconnected(hsotg
);
2337 s3c_hsotg_core_connect(hsotg
);
2342 /* check both FIFOs */
2344 if (gintsts
& GINTSTS_NPTXFEMP
) {
2345 dev_dbg(hsotg
->dev
, "NPTxFEmp\n");
2348 * Disable the interrupt to stop it happening again
2349 * unless one of these endpoint routines decides that
2350 * it needs re-enabling
2353 s3c_hsotg_disable_gsint(hsotg
, GINTSTS_NPTXFEMP
);
2354 s3c_hsotg_irq_fifoempty(hsotg
, false);
2357 if (gintsts
& GINTSTS_PTXFEMP
) {
2358 dev_dbg(hsotg
->dev
, "PTxFEmp\n");
2360 /* See note in GINTSTS_NPTxFEmp */
2362 s3c_hsotg_disable_gsint(hsotg
, GINTSTS_PTXFEMP
);
2363 s3c_hsotg_irq_fifoempty(hsotg
, true);
2366 if (gintsts
& GINTSTS_RXFLVL
) {
2368 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2369 * we need to retry s3c_hsotg_handle_rx if this is still
2373 s3c_hsotg_handle_rx(hsotg
);
2376 if (gintsts
& GINTSTS_ERLYSUSP
) {
2377 dev_dbg(hsotg
->dev
, "GINTSTS_ErlySusp\n");
2378 writel(GINTSTS_ERLYSUSP
, hsotg
->regs
+ GINTSTS
);
2382 * these next two seem to crop-up occasionally causing the core
2383 * to shutdown the USB transfer, so try clearing them and logging
2387 if (gintsts
& GINTSTS_GOUTNAKEFF
) {
2388 dev_info(hsotg
->dev
, "GOUTNakEff triggered\n");
2390 writel(DCTL_CGOUTNAK
, hsotg
->regs
+ DCTL
);
2392 s3c_hsotg_dump(hsotg
);
2395 if (gintsts
& GINTSTS_GINNAKEFF
) {
2396 dev_info(hsotg
->dev
, "GINNakEff triggered\n");
2398 writel(DCTL_CGNPINNAK
, hsotg
->regs
+ DCTL
);
2400 s3c_hsotg_dump(hsotg
);
2404 * if we've had fifo events, we should try and go around the
2405 * loop again to see if there's any point in returning yet.
2408 if (gintsts
& IRQ_RETRY_MASK
&& --retry_count
> 0)
2411 spin_unlock(&hsotg
->lock
);
2417 * s3c_hsotg_ep_enable - enable the given endpoint
2418 * @ep: The USB endpint to configure
2419 * @desc: The USB endpoint descriptor to configure with.
2421 * This is called from the USB gadget code's usb_ep_enable().
2423 static int s3c_hsotg_ep_enable(struct usb_ep
*ep
,
2424 const struct usb_endpoint_descriptor
*desc
)
2426 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2427 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
2428 unsigned long flags
;
2429 int index
= hs_ep
->index
;
2438 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2439 __func__
, ep
->name
, desc
->bEndpointAddress
, desc
->bmAttributes
,
2440 desc
->wMaxPacketSize
, desc
->bInterval
);
2442 /* not to be called for EP0 */
2443 WARN_ON(index
== 0);
2445 dir_in
= (desc
->bEndpointAddress
& USB_ENDPOINT_DIR_MASK
) ? 1 : 0;
2446 if (dir_in
!= hs_ep
->dir_in
) {
2447 dev_err(hsotg
->dev
, "%s: direction mismatch!\n", __func__
);
2451 mps
= usb_endpoint_maxp(desc
);
2453 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2455 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2456 epctrl
= readl(hsotg
->regs
+ epctrl_reg
);
2458 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2459 __func__
, epctrl
, epctrl_reg
);
2461 spin_lock_irqsave(&hsotg
->lock
, flags
);
2463 epctrl
&= ~(DXEPCTL_EPTYPE_MASK
| DXEPCTL_MPS_MASK
);
2464 epctrl
|= DXEPCTL_MPS(mps
);
2467 * mark the endpoint as active, otherwise the core may ignore
2468 * transactions entirely for this endpoint
2470 epctrl
|= DXEPCTL_USBACTEP
;
2473 * set the NAK status on the endpoint, otherwise we might try and
2474 * do something with data that we've yet got a request to process
2475 * since the RXFIFO will take data for an endpoint even if the
2476 * size register hasn't been set.
2479 epctrl
|= DXEPCTL_SNAK
;
2481 /* update the endpoint state */
2482 s3c_hsotg_set_ep_maxpacket(hsotg
, hs_ep
->index
, mps
);
2484 /* default, set to non-periodic */
2485 hs_ep
->isochronous
= 0;
2486 hs_ep
->periodic
= 0;
2488 hs_ep
->interval
= desc
->bInterval
;
2490 if (hs_ep
->interval
> 1 && hs_ep
->mc
> 1)
2491 dev_err(hsotg
->dev
, "MC > 1 when interval is not 1\n");
2493 switch (desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
) {
2494 case USB_ENDPOINT_XFER_ISOC
:
2495 epctrl
|= DXEPCTL_EPTYPE_ISO
;
2496 epctrl
|= DXEPCTL_SETEVENFR
;
2497 hs_ep
->isochronous
= 1;
2499 hs_ep
->periodic
= 1;
2502 case USB_ENDPOINT_XFER_BULK
:
2503 epctrl
|= DXEPCTL_EPTYPE_BULK
;
2506 case USB_ENDPOINT_XFER_INT
:
2508 hs_ep
->periodic
= 1;
2510 epctrl
|= DXEPCTL_EPTYPE_INTERRUPT
;
2513 case USB_ENDPOINT_XFER_CONTROL
:
2514 epctrl
|= DXEPCTL_EPTYPE_CONTROL
;
2519 * if the hardware has dedicated fifos, we must give each IN EP
2520 * a unique tx-fifo even if it is non-periodic.
2522 if (dir_in
&& hsotg
->dedicated_fifos
) {
2523 size
= hs_ep
->ep
.maxpacket
*hs_ep
->mc
;
2524 for (i
= 1; i
<= 8; ++i
) {
2525 if (hsotg
->fifo_map
& (1<<i
))
2527 val
= readl(hsotg
->regs
+ DPTXFSIZN(i
));
2528 val
= (val
>> FIFOSIZE_DEPTH_SHIFT
)*4;
2531 hsotg
->fifo_map
|= 1<<i
;
2533 epctrl
|= DXEPCTL_TXFNUM(i
);
2534 hs_ep
->fifo_index
= i
;
2535 hs_ep
->fifo_size
= val
;
2544 /* for non control endpoints, set PID to D0 */
2546 epctrl
|= DXEPCTL_SETD0PID
;
2548 dev_dbg(hsotg
->dev
, "%s: write DxEPCTL=0x%08x\n",
2551 writel(epctrl
, hsotg
->regs
+ epctrl_reg
);
2552 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x\n",
2553 __func__
, readl(hsotg
->regs
+ epctrl_reg
));
2555 /* enable the endpoint interrupt */
2556 s3c_hsotg_ctrl_epint(hsotg
, index
, dir_in
, 1);
2559 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2564 * s3c_hsotg_ep_disable - disable given endpoint
2565 * @ep: The endpoint to disable.
2567 static int s3c_hsotg_ep_disable(struct usb_ep
*ep
)
2569 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2570 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
2571 int dir_in
= hs_ep
->dir_in
;
2572 int index
= hs_ep
->index
;
2573 unsigned long flags
;
2577 dev_dbg(hsotg
->dev
, "%s(ep %p)\n", __func__
, ep
);
2579 if (ep
== &hsotg
->eps
[0].ep
) {
2580 dev_err(hsotg
->dev
, "%s: called for ep0\n", __func__
);
2584 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2586 spin_lock_irqsave(&hsotg
->lock
, flags
);
2587 /* terminate all requests with shutdown */
2588 kill_all_requests(hsotg
, hs_ep
, -ESHUTDOWN
);
2590 hsotg
->fifo_map
&= ~(1<<hs_ep
->fifo_index
);
2591 hs_ep
->fifo_index
= 0;
2592 hs_ep
->fifo_size
= 0;
2594 ctrl
= readl(hsotg
->regs
+ epctrl_reg
);
2595 ctrl
&= ~DXEPCTL_EPENA
;
2596 ctrl
&= ~DXEPCTL_USBACTEP
;
2597 ctrl
|= DXEPCTL_SNAK
;
2599 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
2600 writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
2602 /* disable endpoint interrupts */
2603 s3c_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 0);
2605 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2610 * on_list - check request is on the given endpoint
2611 * @ep: The endpoint to check.
2612 * @test: The request to test if it is on the endpoint.
2614 static bool on_list(struct s3c_hsotg_ep
*ep
, struct s3c_hsotg_req
*test
)
2616 struct s3c_hsotg_req
*req
, *treq
;
2618 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
2627 * s3c_hsotg_ep_dequeue - dequeue given endpoint
2628 * @ep: The endpoint to dequeue.
2629 * @req: The request to be removed from a queue.
2631 static int s3c_hsotg_ep_dequeue(struct usb_ep
*ep
, struct usb_request
*req
)
2633 struct s3c_hsotg_req
*hs_req
= our_req(req
);
2634 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2635 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
2636 unsigned long flags
;
2638 dev_dbg(hs
->dev
, "ep_dequeue(%p,%p)\n", ep
, req
);
2640 spin_lock_irqsave(&hs
->lock
, flags
);
2642 if (!on_list(hs_ep
, hs_req
)) {
2643 spin_unlock_irqrestore(&hs
->lock
, flags
);
2647 s3c_hsotg_complete_request(hs
, hs_ep
, hs_req
, -ECONNRESET
);
2648 spin_unlock_irqrestore(&hs
->lock
, flags
);
2654 * s3c_hsotg_ep_sethalt - set halt on a given endpoint
2655 * @ep: The endpoint to set halt.
2656 * @value: Set or unset the halt.
2658 static int s3c_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
)
2660 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2661 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
2662 int index
= hs_ep
->index
;
2667 dev_info(hs
->dev
, "%s(ep %p %s, %d)\n", __func__
, ep
, ep
->name
, value
);
2671 s3c_hsotg_stall_ep0(hs
);
2674 "%s: can't clear halt on ep0\n", __func__
);
2678 /* write both IN and OUT control registers */
2680 epreg
= DIEPCTL(index
);
2681 epctl
= readl(hs
->regs
+ epreg
);
2684 epctl
|= DXEPCTL_STALL
+ DXEPCTL_SNAK
;
2685 if (epctl
& DXEPCTL_EPENA
)
2686 epctl
|= DXEPCTL_EPDIS
;
2688 epctl
&= ~DXEPCTL_STALL
;
2689 xfertype
= epctl
& DXEPCTL_EPTYPE_MASK
;
2690 if (xfertype
== DXEPCTL_EPTYPE_BULK
||
2691 xfertype
== DXEPCTL_EPTYPE_INTERRUPT
)
2692 epctl
|= DXEPCTL_SETD0PID
;
2695 writel(epctl
, hs
->regs
+ epreg
);
2697 epreg
= DOEPCTL(index
);
2698 epctl
= readl(hs
->regs
+ epreg
);
2701 epctl
|= DXEPCTL_STALL
;
2703 epctl
&= ~DXEPCTL_STALL
;
2704 xfertype
= epctl
& DXEPCTL_EPTYPE_MASK
;
2705 if (xfertype
== DXEPCTL_EPTYPE_BULK
||
2706 xfertype
== DXEPCTL_EPTYPE_INTERRUPT
)
2707 epctl
|= DXEPCTL_SETD0PID
;
2710 writel(epctl
, hs
->regs
+ epreg
);
2712 hs_ep
->halted
= value
;
2718 * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
2719 * @ep: The endpoint to set halt.
2720 * @value: Set or unset the halt.
2722 static int s3c_hsotg_ep_sethalt_lock(struct usb_ep
*ep
, int value
)
2724 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2725 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
2726 unsigned long flags
= 0;
2729 spin_lock_irqsave(&hs
->lock
, flags
);
2730 ret
= s3c_hsotg_ep_sethalt(ep
, value
);
2731 spin_unlock_irqrestore(&hs
->lock
, flags
);
2736 static struct usb_ep_ops s3c_hsotg_ep_ops
= {
2737 .enable
= s3c_hsotg_ep_enable
,
2738 .disable
= s3c_hsotg_ep_disable
,
2739 .alloc_request
= s3c_hsotg_ep_alloc_request
,
2740 .free_request
= s3c_hsotg_ep_free_request
,
2741 .queue
= s3c_hsotg_ep_queue_lock
,
2742 .dequeue
= s3c_hsotg_ep_dequeue
,
2743 .set_halt
= s3c_hsotg_ep_sethalt_lock
,
2744 /* note, don't believe we have any call for the fifo routines */
2748 * s3c_hsotg_phy_enable - enable platform phy dev
2749 * @hsotg: The driver state
2751 * A wrapper for platform code responsible for controlling
2752 * low-level USB code
2754 static void s3c_hsotg_phy_enable(struct dwc2_hsotg
*hsotg
)
2756 struct platform_device
*pdev
= to_platform_device(hsotg
->dev
);
2758 dev_dbg(hsotg
->dev
, "pdev 0x%p\n", pdev
);
2761 usb_phy_init(hsotg
->uphy
);
2762 else if (hsotg
->plat
&& hsotg
->plat
->phy_init
)
2763 hsotg
->plat
->phy_init(pdev
, hsotg
->plat
->phy_type
);
2765 phy_init(hsotg
->phy
);
2766 phy_power_on(hsotg
->phy
);
2771 * s3c_hsotg_phy_disable - disable platform phy dev
2772 * @hsotg: The driver state
2774 * A wrapper for platform code responsible for controlling
2775 * low-level USB code
2777 static void s3c_hsotg_phy_disable(struct dwc2_hsotg
*hsotg
)
2779 struct platform_device
*pdev
= to_platform_device(hsotg
->dev
);
2782 usb_phy_shutdown(hsotg
->uphy
);
2783 else if (hsotg
->plat
&& hsotg
->plat
->phy_exit
)
2784 hsotg
->plat
->phy_exit(pdev
, hsotg
->plat
->phy_type
);
2786 phy_power_off(hsotg
->phy
);
2787 phy_exit(hsotg
->phy
);
2792 * s3c_hsotg_init - initalize the usb core
2793 * @hsotg: The driver state
2795 static void s3c_hsotg_init(struct dwc2_hsotg
*hsotg
)
2797 /* unmask subset of endpoint interrupts */
2799 writel(DIEPMSK_TIMEOUTMSK
| DIEPMSK_AHBERRMSK
|
2800 DIEPMSK_EPDISBLDMSK
| DIEPMSK_XFERCOMPLMSK
,
2801 hsotg
->regs
+ DIEPMSK
);
2803 writel(DOEPMSK_SETUPMSK
| DOEPMSK_AHBERRMSK
|
2804 DOEPMSK_EPDISBLDMSK
| DOEPMSK_XFERCOMPLMSK
,
2805 hsotg
->regs
+ DOEPMSK
);
2807 writel(0, hsotg
->regs
+ DAINTMSK
);
2809 /* Be in disconnected state until gadget is registered */
2810 __orr32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
2813 /* post global nak until we're ready */
2814 writel(DCTL_SGNPINNAK
| DCTL_SGOUTNAK
,
2815 hsotg
->regs
+ DCTL
);
2820 dev_dbg(hsotg
->dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2821 readl(hsotg
->regs
+ GRXFSIZ
),
2822 readl(hsotg
->regs
+ GNPTXFSIZ
));
2824 s3c_hsotg_init_fifo(hsotg
);
2826 /* set the PLL on, remove the HNP/SRP and set the PHY */
2827 writel(GUSBCFG_PHYIF16
| GUSBCFG_TOUTCAL(7) | (0x5 << 10),
2828 hsotg
->regs
+ GUSBCFG
);
2830 if (using_dma(hsotg
))
2831 __orr32(hsotg
->regs
+ GAHBCFG
, GAHBCFG_DMA_EN
);
2835 * s3c_hsotg_udc_start - prepare the udc for work
2836 * @gadget: The usb gadget state
2837 * @driver: The usb gadget driver
2839 * Perform initialization to prepare udc device and driver
2842 static int s3c_hsotg_udc_start(struct usb_gadget
*gadget
,
2843 struct usb_gadget_driver
*driver
)
2845 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
2846 unsigned long flags
;
2850 pr_err("%s: called with no device\n", __func__
);
2855 dev_err(hsotg
->dev
, "%s: no driver\n", __func__
);
2859 if (driver
->max_speed
< USB_SPEED_FULL
)
2860 dev_err(hsotg
->dev
, "%s: bad speed\n", __func__
);
2862 if (!driver
->setup
) {
2863 dev_err(hsotg
->dev
, "%s: missing entry points\n", __func__
);
2867 mutex_lock(&hsotg
->init_mutex
);
2868 WARN_ON(hsotg
->driver
);
2870 driver
->driver
.bus
= NULL
;
2871 hsotg
->driver
= driver
;
2872 hsotg
->gadget
.dev
.of_node
= hsotg
->dev
->of_node
;
2873 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2875 clk_enable(hsotg
->clk
);
2877 ret
= regulator_bulk_enable(ARRAY_SIZE(hsotg
->supplies
),
2880 dev_err(hsotg
->dev
, "failed to enable supplies: %d\n", ret
);
2884 s3c_hsotg_phy_enable(hsotg
);
2885 if (!IS_ERR_OR_NULL(hsotg
->uphy
))
2886 otg_set_peripheral(hsotg
->uphy
->otg
, &hsotg
->gadget
);
2888 spin_lock_irqsave(&hsotg
->lock
, flags
);
2889 s3c_hsotg_init(hsotg
);
2890 s3c_hsotg_core_init_disconnected(hsotg
);
2892 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2894 dev_info(hsotg
->dev
, "bound driver %s\n", driver
->driver
.name
);
2896 mutex_unlock(&hsotg
->init_mutex
);
2901 mutex_unlock(&hsotg
->init_mutex
);
2902 hsotg
->driver
= NULL
;
2907 * s3c_hsotg_udc_stop - stop the udc
2908 * @gadget: The usb gadget state
2909 * @driver: The usb gadget driver
2911 * Stop udc hw block and stay tunned for future transmissions
2913 static int s3c_hsotg_udc_stop(struct usb_gadget
*gadget
)
2915 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
2916 unsigned long flags
= 0;
2922 mutex_lock(&hsotg
->init_mutex
);
2924 /* all endpoints should be shutdown */
2925 for (ep
= 1; ep
< hsotg
->num_of_eps
; ep
++)
2926 s3c_hsotg_ep_disable(&hsotg
->eps
[ep
].ep
);
2928 spin_lock_irqsave(&hsotg
->lock
, flags
);
2930 hsotg
->driver
= NULL
;
2931 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2934 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2936 if (!IS_ERR_OR_NULL(hsotg
->uphy
))
2937 otg_set_peripheral(hsotg
->uphy
->otg
, NULL
);
2938 s3c_hsotg_phy_disable(hsotg
);
2940 regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
), hsotg
->supplies
);
2942 clk_disable(hsotg
->clk
);
2944 mutex_unlock(&hsotg
->init_mutex
);
2950 * s3c_hsotg_gadget_getframe - read the frame number
2951 * @gadget: The usb gadget state
2953 * Read the {micro} frame number
2955 static int s3c_hsotg_gadget_getframe(struct usb_gadget
*gadget
)
2957 return s3c_hsotg_read_frameno(to_hsotg(gadget
));
2961 * s3c_hsotg_pullup - connect/disconnect the USB PHY
2962 * @gadget: The usb gadget state
2963 * @is_on: Current state of the USB PHY
2965 * Connect/Disconnect the USB PHY pullup
2967 static int s3c_hsotg_pullup(struct usb_gadget
*gadget
, int is_on
)
2969 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
2970 unsigned long flags
= 0;
2972 dev_dbg(hsotg
->dev
, "%s: is_on: %d\n", __func__
, is_on
);
2974 mutex_lock(&hsotg
->init_mutex
);
2975 spin_lock_irqsave(&hsotg
->lock
, flags
);
2977 clk_enable(hsotg
->clk
);
2979 s3c_hsotg_core_connect(hsotg
);
2981 s3c_hsotg_core_disconnect(hsotg
);
2983 clk_disable(hsotg
->clk
);
2986 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2987 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2988 mutex_unlock(&hsotg
->init_mutex
);
2993 static const struct usb_gadget_ops s3c_hsotg_gadget_ops
= {
2994 .get_frame
= s3c_hsotg_gadget_getframe
,
2995 .udc_start
= s3c_hsotg_udc_start
,
2996 .udc_stop
= s3c_hsotg_udc_stop
,
2997 .pullup
= s3c_hsotg_pullup
,
3001 * s3c_hsotg_initep - initialise a single endpoint
3002 * @hsotg: The device state.
3003 * @hs_ep: The endpoint to be initialised.
3004 * @epnum: The endpoint number
3006 * Initialise the given endpoint (as part of the probe and device state
3007 * creation) to give to the gadget driver. Setup the endpoint name, any
3008 * direction information and other state that may be required.
3010 static void s3c_hsotg_initep(struct dwc2_hsotg
*hsotg
,
3011 struct s3c_hsotg_ep
*hs_ep
,
3018 else if ((epnum
% 2) == 0) {
3025 hs_ep
->index
= epnum
;
3027 snprintf(hs_ep
->name
, sizeof(hs_ep
->name
), "ep%d%s", epnum
, dir
);
3029 INIT_LIST_HEAD(&hs_ep
->queue
);
3030 INIT_LIST_HEAD(&hs_ep
->ep
.ep_list
);
3032 /* add to the list of endpoints known by the gadget driver */
3034 list_add_tail(&hs_ep
->ep
.ep_list
, &hsotg
->gadget
.ep_list
);
3036 hs_ep
->parent
= hsotg
;
3037 hs_ep
->ep
.name
= hs_ep
->name
;
3038 usb_ep_set_maxpacket_limit(&hs_ep
->ep
, epnum
? 1024 : EP0_MPS_LIMIT
);
3039 hs_ep
->ep
.ops
= &s3c_hsotg_ep_ops
;
3042 * if we're using dma, we need to set the next-endpoint pointer
3043 * to be something valid.
3046 if (using_dma(hsotg
)) {
3047 u32 next
= DXEPCTL_NEXTEP((epnum
+ 1) % 15);
3048 writel(next
, hsotg
->regs
+ DIEPCTL(epnum
));
3049 writel(next
, hsotg
->regs
+ DOEPCTL(epnum
));
3054 * s3c_hsotg_hw_cfg - read HW configuration registers
3055 * @param: The device state
3057 * Read the USB core HW configuration registers
3059 static void s3c_hsotg_hw_cfg(struct dwc2_hsotg
*hsotg
)
3061 u32 cfg2
, cfg3
, cfg4
;
3062 /* check hardware configuration */
3064 cfg2
= readl(hsotg
->regs
+ 0x48);
3065 hsotg
->num_of_eps
= (cfg2
>> 10) & 0xF;
3067 cfg3
= readl(hsotg
->regs
+ 0x4C);
3068 hsotg
->fifo_mem
= (cfg3
>> 16);
3070 cfg4
= readl(hsotg
->regs
+ 0x50);
3071 hsotg
->dedicated_fifos
= (cfg4
>> 25) & 1;
3073 dev_info(hsotg
->dev
, "EPs: %d, %s fifos, %d entries in SPRAM\n",
3075 hsotg
->dedicated_fifos
? "dedicated" : "shared",
3080 * s3c_hsotg_dump - dump state of the udc
3081 * @param: The device state
3083 static void s3c_hsotg_dump(struct dwc2_hsotg
*hsotg
)
3086 struct device
*dev
= hsotg
->dev
;
3087 void __iomem
*regs
= hsotg
->regs
;
3091 dev_info(dev
, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3092 readl(regs
+ DCFG
), readl(regs
+ DCTL
),
3093 readl(regs
+ DIEPMSK
));
3095 dev_info(dev
, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
3096 readl(regs
+ GAHBCFG
), readl(regs
+ 0x44));
3098 dev_info(dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3099 readl(regs
+ GRXFSIZ
), readl(regs
+ GNPTXFSIZ
));
3101 /* show periodic fifo settings */
3103 for (idx
= 1; idx
<= 15; idx
++) {
3104 val
= readl(regs
+ DPTXFSIZN(idx
));
3105 dev_info(dev
, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx
,
3106 val
>> FIFOSIZE_DEPTH_SHIFT
,
3107 val
& FIFOSIZE_STARTADDR_MASK
);
3110 for (idx
= 0; idx
< 15; idx
++) {
3112 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx
,
3113 readl(regs
+ DIEPCTL(idx
)),
3114 readl(regs
+ DIEPTSIZ(idx
)),
3115 readl(regs
+ DIEPDMA(idx
)));
3117 val
= readl(regs
+ DOEPCTL(idx
));
3119 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3120 idx
, readl(regs
+ DOEPCTL(idx
)),
3121 readl(regs
+ DOEPTSIZ(idx
)),
3122 readl(regs
+ DOEPDMA(idx
)));
3126 dev_info(dev
, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3127 readl(regs
+ DVBUSDIS
), readl(regs
+ DVBUSPULSE
));
3132 * state_show - debugfs: show overall driver and device state.
3133 * @seq: The seq file to write to.
3134 * @v: Unused parameter.
3136 * This debugfs entry shows the overall state of the hardware and
3137 * some general information about each of the endpoints available
3140 static int state_show(struct seq_file
*seq
, void *v
)
3142 struct dwc2_hsotg
*hsotg
= seq
->private;
3143 void __iomem
*regs
= hsotg
->regs
;
3146 seq_printf(seq
, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
3149 readl(regs
+ DSTS
));
3151 seq_printf(seq
, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
3152 readl(regs
+ DIEPMSK
), readl(regs
+ DOEPMSK
));
3154 seq_printf(seq
, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
3155 readl(regs
+ GINTMSK
),
3156 readl(regs
+ GINTSTS
));
3158 seq_printf(seq
, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
3159 readl(regs
+ DAINTMSK
),
3160 readl(regs
+ DAINT
));
3162 seq_printf(seq
, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3163 readl(regs
+ GNPTXSTS
),
3164 readl(regs
+ GRXSTSR
));
3166 seq_puts(seq
, "\nEndpoint status:\n");
3168 for (idx
= 0; idx
< 15; idx
++) {
3171 in
= readl(regs
+ DIEPCTL(idx
));
3172 out
= readl(regs
+ DOEPCTL(idx
));
3174 seq_printf(seq
, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3177 in
= readl(regs
+ DIEPTSIZ(idx
));
3178 out
= readl(regs
+ DOEPTSIZ(idx
));
3180 seq_printf(seq
, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3183 seq_puts(seq
, "\n");
3189 static int state_open(struct inode
*inode
, struct file
*file
)
3191 return single_open(file
, state_show
, inode
->i_private
);
3194 static const struct file_operations state_fops
= {
3195 .owner
= THIS_MODULE
,
3198 .llseek
= seq_lseek
,
3199 .release
= single_release
,
3203 * fifo_show - debugfs: show the fifo information
3204 * @seq: The seq_file to write data to.
3205 * @v: Unused parameter.
3207 * Show the FIFO information for the overall fifo and all the
3208 * periodic transmission FIFOs.
3210 static int fifo_show(struct seq_file
*seq
, void *v
)
3212 struct dwc2_hsotg
*hsotg
= seq
->private;
3213 void __iomem
*regs
= hsotg
->regs
;
3217 seq_puts(seq
, "Non-periodic FIFOs:\n");
3218 seq_printf(seq
, "RXFIFO: Size %d\n", readl(regs
+ GRXFSIZ
));
3220 val
= readl(regs
+ GNPTXFSIZ
);
3221 seq_printf(seq
, "NPTXFIFO: Size %d, Start 0x%08x\n",
3222 val
>> FIFOSIZE_DEPTH_SHIFT
,
3223 val
& FIFOSIZE_DEPTH_MASK
);
3225 seq_puts(seq
, "\nPeriodic TXFIFOs:\n");
3227 for (idx
= 1; idx
<= 15; idx
++) {
3228 val
= readl(regs
+ DPTXFSIZN(idx
));
3230 seq_printf(seq
, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx
,
3231 val
>> FIFOSIZE_DEPTH_SHIFT
,
3232 val
& FIFOSIZE_STARTADDR_MASK
);
3238 static int fifo_open(struct inode
*inode
, struct file
*file
)
3240 return single_open(file
, fifo_show
, inode
->i_private
);
3243 static const struct file_operations fifo_fops
= {
3244 .owner
= THIS_MODULE
,
3247 .llseek
= seq_lseek
,
3248 .release
= single_release
,
3252 static const char *decode_direction(int is_in
)
3254 return is_in
? "in" : "out";
3258 * ep_show - debugfs: show the state of an endpoint.
3259 * @seq: The seq_file to write data to.
3260 * @v: Unused parameter.
3262 * This debugfs entry shows the state of the given endpoint (one is
3263 * registered for each available).
3265 static int ep_show(struct seq_file
*seq
, void *v
)
3267 struct s3c_hsotg_ep
*ep
= seq
->private;
3268 struct dwc2_hsotg
*hsotg
= ep
->parent
;
3269 struct s3c_hsotg_req
*req
;
3270 void __iomem
*regs
= hsotg
->regs
;
3271 int index
= ep
->index
;
3272 int show_limit
= 15;
3273 unsigned long flags
;
3275 seq_printf(seq
, "Endpoint index %d, named %s, dir %s:\n",
3276 ep
->index
, ep
->ep
.name
, decode_direction(ep
->dir_in
));
3278 /* first show the register state */
3280 seq_printf(seq
, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3281 readl(regs
+ DIEPCTL(index
)),
3282 readl(regs
+ DOEPCTL(index
)));
3284 seq_printf(seq
, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3285 readl(regs
+ DIEPDMA(index
)),
3286 readl(regs
+ DOEPDMA(index
)));
3288 seq_printf(seq
, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3289 readl(regs
+ DIEPINT(index
)),
3290 readl(regs
+ DOEPINT(index
)));
3292 seq_printf(seq
, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3293 readl(regs
+ DIEPTSIZ(index
)),
3294 readl(regs
+ DOEPTSIZ(index
)));
3296 seq_puts(seq
, "\n");
3297 seq_printf(seq
, "mps %d\n", ep
->ep
.maxpacket
);
3298 seq_printf(seq
, "total_data=%ld\n", ep
->total_data
);
3300 seq_printf(seq
, "request list (%p,%p):\n",
3301 ep
->queue
.next
, ep
->queue
.prev
);
3303 spin_lock_irqsave(&hsotg
->lock
, flags
);
3305 list_for_each_entry(req
, &ep
->queue
, queue
) {
3306 if (--show_limit
< 0) {
3307 seq_puts(seq
, "not showing more requests...\n");
3311 seq_printf(seq
, "%c req %p: %d bytes @%p, ",
3312 req
== ep
->req
? '*' : ' ',
3313 req
, req
->req
.length
, req
->req
.buf
);
3314 seq_printf(seq
, "%d done, res %d\n",
3315 req
->req
.actual
, req
->req
.status
);
3318 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3323 static int ep_open(struct inode
*inode
, struct file
*file
)
3325 return single_open(file
, ep_show
, inode
->i_private
);
3328 static const struct file_operations ep_fops
= {
3329 .owner
= THIS_MODULE
,
3332 .llseek
= seq_lseek
,
3333 .release
= single_release
,
3337 * s3c_hsotg_create_debug - create debugfs directory and files
3338 * @hsotg: The driver state
3340 * Create the debugfs files to allow the user to get information
3341 * about the state of the system. The directory name is created
3342 * with the same name as the device itself, in case we end up
3343 * with multiple blocks in future systems.
3345 static void s3c_hsotg_create_debug(struct dwc2_hsotg
*hsotg
)
3347 struct dentry
*root
;
3350 root
= debugfs_create_dir(dev_name(hsotg
->dev
), NULL
);
3351 hsotg
->debug_root
= root
;
3353 dev_err(hsotg
->dev
, "cannot create debug root\n");
3357 /* create general state file */
3359 hsotg
->debug_file
= debugfs_create_file("state", 0444, root
,
3360 hsotg
, &state_fops
);
3362 if (IS_ERR(hsotg
->debug_file
))
3363 dev_err(hsotg
->dev
, "%s: failed to create state\n", __func__
);
3365 hsotg
->debug_fifo
= debugfs_create_file("fifo", 0444, root
,
3368 if (IS_ERR(hsotg
->debug_fifo
))
3369 dev_err(hsotg
->dev
, "%s: failed to create fifo\n", __func__
);
3371 /* create one file for each endpoint */
3373 for (epidx
= 0; epidx
< hsotg
->num_of_eps
; epidx
++) {
3374 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[epidx
];
3376 ep
->debugfs
= debugfs_create_file(ep
->name
, 0444,
3377 root
, ep
, &ep_fops
);
3379 if (IS_ERR(ep
->debugfs
))
3380 dev_err(hsotg
->dev
, "failed to create %s debug file\n",
3386 * s3c_hsotg_delete_debug - cleanup debugfs entries
3387 * @hsotg: The driver state
3389 * Cleanup (remove) the debugfs files for use on module exit.
3391 static void s3c_hsotg_delete_debug(struct dwc2_hsotg
*hsotg
)
3395 for (epidx
= 0; epidx
< hsotg
->num_of_eps
; epidx
++) {
3396 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[epidx
];
3397 debugfs_remove(ep
->debugfs
);
3400 debugfs_remove(hsotg
->debug_file
);
3401 debugfs_remove(hsotg
->debug_fifo
);
3402 debugfs_remove(hsotg
->debug_root
);
3406 * dwc2_gadget_init - init function for gadget
3407 * @dwc2: The data structure for the DWC2 driver.
3408 * @irq: The IRQ number for the controller.
3410 int dwc2_gadget_init(struct dwc2_hsotg
*hsotg
, int irq
)
3412 struct device
*dev
= hsotg
->dev
;
3413 struct s3c_hsotg_plat
*plat
= dev
->platform_data
;
3414 struct s3c_hsotg_ep
*eps
;
3419 /* Set default UTMI width */
3420 hsotg
->phyif
= GUSBCFG_PHYIF16
;
3423 * If platform probe couldn't find a generic PHY or an old style
3424 * USB PHY, fall back to pdata
3426 if (IS_ERR_OR_NULL(hsotg
->phy
) && IS_ERR_OR_NULL(hsotg
->uphy
)) {
3427 plat
= dev_get_platdata(dev
);
3430 "no platform data or transceiver defined\n");
3431 return -EPROBE_DEFER
;
3434 } else if (hsotg
->phy
) {
3436 * If using the generic PHY framework, check if the PHY bus
3437 * width is 8-bit and set the phyif appropriately.
3439 if (phy_get_bus_width(hsotg
->phy
) == 8)
3440 hsotg
->phyif
= GUSBCFG_PHYIF8
;
3443 hsotg
->clk
= devm_clk_get(dev
, "otg");
3444 if (IS_ERR(hsotg
->clk
)) {
3446 dev_dbg(dev
, "cannot get otg clock\n");
3449 hsotg
->gadget
.max_speed
= USB_SPEED_HIGH
;
3450 hsotg
->gadget
.ops
= &s3c_hsotg_gadget_ops
;
3451 hsotg
->gadget
.name
= dev_name(dev
);
3453 /* reset the system */
3455 ret
= clk_prepare_enable(hsotg
->clk
);
3457 dev_err(dev
, "failed to enable otg clk\n");
3464 for (i
= 0; i
< ARRAY_SIZE(hsotg
->supplies
); i
++)
3465 hsotg
->supplies
[i
].supply
= s3c_hsotg_supply_names
[i
];
3467 ret
= devm_regulator_bulk_get(dev
, ARRAY_SIZE(hsotg
->supplies
),
3470 dev_err(dev
, "failed to request supplies: %d\n", ret
);
3474 ret
= regulator_bulk_enable(ARRAY_SIZE(hsotg
->supplies
),
3478 dev_err(dev
, "failed to enable supplies: %d\n", ret
);
3482 /* usb phy enable */
3483 s3c_hsotg_phy_enable(hsotg
);
3485 s3c_hsotg_corereset(hsotg
);
3486 s3c_hsotg_hw_cfg(hsotg
);
3487 s3c_hsotg_init(hsotg
);
3489 hsotg
->ctrl_buff
= devm_kzalloc(hsotg
->dev
,
3490 DWC2_CTRL_BUFF_SIZE
, GFP_KERNEL
);
3491 if (!hsotg
->ctrl_buff
) {
3492 dev_err(dev
, "failed to allocate ctrl request buff\n");
3497 hsotg
->ep0_buff
= devm_kzalloc(hsotg
->dev
,
3498 DWC2_CTRL_BUFF_SIZE
, GFP_KERNEL
);
3499 if (!hsotg
->ep0_buff
) {
3500 dev_err(dev
, "failed to allocate ctrl reply buff\n");
3505 ret
= devm_request_irq(hsotg
->dev
, irq
, s3c_hsotg_irq
, IRQF_SHARED
,
3506 dev_name(hsotg
->dev
), hsotg
);
3508 s3c_hsotg_phy_disable(hsotg
);
3509 clk_disable_unprepare(hsotg
->clk
);
3510 regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
),
3512 dev_err(dev
, "cannot claim IRQ for gadget\n");
3516 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3518 if (hsotg
->num_of_eps
== 0) {
3519 dev_err(dev
, "wrong number of EPs (zero)\n");
3524 eps
= kcalloc(hsotg
->num_of_eps
+ 1, sizeof(struct s3c_hsotg_ep
),
3533 /* setup endpoint information */
3535 INIT_LIST_HEAD(&hsotg
->gadget
.ep_list
);
3536 hsotg
->gadget
.ep0
= &hsotg
->eps
[0].ep
;
3538 /* allocate EP0 request */
3540 hsotg
->ctrl_req
= s3c_hsotg_ep_alloc_request(&hsotg
->eps
[0].ep
,
3542 if (!hsotg
->ctrl_req
) {
3543 dev_err(dev
, "failed to allocate ctrl req\n");
3548 /* initialise the endpoints now the core has been initialised */
3549 for (epnum
= 0; epnum
< hsotg
->num_of_eps
; epnum
++)
3550 s3c_hsotg_initep(hsotg
, &hsotg
->eps
[epnum
], epnum
);
3552 /* disable power and clock */
3553 s3c_hsotg_phy_disable(hsotg
);
3555 ret
= regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
),
3558 dev_err(dev
, "failed to disable supplies: %d\n", ret
);
3562 ret
= usb_add_gadget_udc(dev
, &hsotg
->gadget
);
3566 s3c_hsotg_create_debug(hsotg
);
3568 s3c_hsotg_dump(hsotg
);
3575 s3c_hsotg_phy_disable(hsotg
);
3577 clk_disable_unprepare(hsotg
->clk
);
3581 EXPORT_SYMBOL_GPL(dwc2_gadget_init
);
3584 * s3c_hsotg_remove - remove function for hsotg driver
3585 * @pdev: The platform information for the driver
3587 int s3c_hsotg_remove(struct dwc2_hsotg
*hsotg
)
3589 usb_del_gadget_udc(&hsotg
->gadget
);
3590 s3c_hsotg_delete_debug(hsotg
);
3591 clk_disable_unprepare(hsotg
->clk
);
3595 EXPORT_SYMBOL_GPL(s3c_hsotg_remove
);
3597 int s3c_hsotg_suspend(struct dwc2_hsotg
*hsotg
)
3599 unsigned long flags
;
3602 mutex_lock(&hsotg
->init_mutex
);
3604 if (hsotg
->driver
) {
3607 dev_info(hsotg
->dev
, "suspending usb gadget %s\n",
3608 hsotg
->driver
->driver
.name
);
3610 spin_lock_irqsave(&hsotg
->lock
, flags
);
3612 s3c_hsotg_core_disconnect(hsotg
);
3613 s3c_hsotg_disconnect(hsotg
);
3614 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3615 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3617 s3c_hsotg_phy_disable(hsotg
);
3619 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++)
3620 s3c_hsotg_ep_disable(&hsotg
->eps
[ep
].ep
);
3622 ret
= regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
),
3624 clk_disable(hsotg
->clk
);
3627 mutex_unlock(&hsotg
->init_mutex
);
3631 EXPORT_SYMBOL_GPL(s3c_hsotg_suspend
);
3633 int s3c_hsotg_resume(struct dwc2_hsotg
*hsotg
)
3635 unsigned long flags
;
3638 mutex_lock(&hsotg
->init_mutex
);
3640 if (hsotg
->driver
) {
3641 dev_info(hsotg
->dev
, "resuming usb gadget %s\n",
3642 hsotg
->driver
->driver
.name
);
3644 clk_enable(hsotg
->clk
);
3645 ret
= regulator_bulk_enable(ARRAY_SIZE(hsotg
->supplies
),
3648 s3c_hsotg_phy_enable(hsotg
);
3650 spin_lock_irqsave(&hsotg
->lock
, flags
);
3651 s3c_hsotg_core_init_disconnected(hsotg
);
3653 s3c_hsotg_core_connect(hsotg
);
3654 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3656 mutex_unlock(&hsotg
->init_mutex
);
3660 EXPORT_SYMBOL_GPL(s3c_hsotg_resume
);