1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * hcd_queue.c - DesignWare HS OTG Controller host queuing routines
5 * Copyright (C) 2004-2013 Synopsys, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 * This file contains the functions to manage Queue Heads and Queue
40 * Transfer Descriptors for Host mode
42 #include <linux/gcd.h>
43 #include <linux/kernel.h>
44 #include <linux/module.h>
45 #include <linux/spinlock.h>
46 #include <linux/interrupt.h>
47 #include <linux/dma-mapping.h>
49 #include <linux/slab.h>
50 #include <linux/usb.h>
52 #include <linux/usb/hcd.h>
53 #include <linux/usb/ch11.h>
58 /* Wait this long before releasing periodic reservation */
59 #define DWC2_UNRESERVE_DELAY (msecs_to_jiffies(5))
62 * dwc2_periodic_channel_available() - Checks that a channel is available for a
65 * @hsotg: The HCD state structure for the DWC OTG controller
67 * Return: 0 if successful, negative error code otherwise
69 static int dwc2_periodic_channel_available(struct dwc2_hsotg
*hsotg
)
72 * Currently assuming that there is a dedicated host channel for
73 * each periodic transaction plus at least one host channel for
74 * non-periodic transactions
79 num_channels
= hsotg
->params
.host_channels
;
80 if ((hsotg
->periodic_channels
+ hsotg
->non_periodic_channels
<
81 num_channels
) && (hsotg
->periodic_channels
< num_channels
- 1)) {
85 "%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
86 __func__
, num_channels
,
87 hsotg
->periodic_channels
, hsotg
->non_periodic_channels
);
95 * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth
96 * for the specified QH in the periodic schedule
98 * @hsotg: The HCD state structure for the DWC OTG controller
99 * @qh: QH containing periodic bandwidth required
101 * Return: 0 if successful, negative error code otherwise
103 * For simplicity, this calculation assumes that all the transfers in the
104 * periodic schedule may occur in the same (micro)frame
106 static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg
*hsotg
,
110 s16 max_claimed_usecs
;
114 if (qh
->dev_speed
== USB_SPEED_HIGH
|| qh
->do_split
) {
117 * Max periodic usecs is 80% x 125 usec = 100 usec
119 max_claimed_usecs
= 100 - qh
->host_us
;
123 * Max periodic usecs is 90% x 1000 usec = 900 usec
125 max_claimed_usecs
= 900 - qh
->host_us
;
128 if (hsotg
->periodic_usecs
> max_claimed_usecs
) {
130 "%s: already claimed usecs %d, required usecs %d\n",
131 __func__
, hsotg
->periodic_usecs
, qh
->host_us
);
139 * pmap_schedule() - Schedule time in a periodic bitmap (pmap).
141 * @map: The bitmap representing the schedule; will be updated
143 * @bits_per_period: The schedule represents several periods. This is how many
144 * bits are in each period. It's assumed that the beginning
145 * of the schedule will repeat after its end.
146 * @periods_in_map: The number of periods in the schedule.
147 * @num_bits: The number of bits we need per period we want to reserve
148 * in this function call.
149 * @interval: How often we need to be scheduled for the reservation this
150 * time. 1 means every period. 2 means every other period.
151 * ...you get the picture?
152 * @start: The bit number to start at. Normally 0. Must be within
153 * the interval or we return failure right away.
154 * @only_one_period: Normally we'll allow picking a start anywhere within the
155 * first interval, since we can still make all repetition
156 * requirements by doing that. However, if you pass true
157 * here then we'll return failure if we can't fit within
158 * the period that "start" is in.
160 * The idea here is that we want to schedule time for repeating events that all
161 * want the same resource. The resource is divided into fixed-sized periods
162 * and the events want to repeat every "interval" periods. The schedule
163 * granularity is one bit.
165 * To keep things "simple", we'll represent our schedule with a bitmap that
166 * contains a fixed number of periods. This gets rid of a lot of complexity
167 * but does mean that we need to handle things specially (and non-ideally) if
168 * the number of the periods in the schedule doesn't match well with the
169 * intervals that we're trying to schedule.
171 * Here's an explanation of the scheme we'll implement, assuming 8 periods.
172 * - If interval is 1, we need to take up space in each of the 8
173 * periods we're scheduling. Easy.
174 * - If interval is 2, we need to take up space in half of the
175 * periods. Again, easy.
176 * - If interval is 3, we actually need to fall back to interval 1.
177 * Why? Because we might need time in any period. AKA for the
178 * first 8 periods, we'll be in slot 0, 3, 6. Then we'll be
179 * in slot 1, 4, 7. Then we'll be in 2, 5. Then we'll be back to
180 * 0, 3, and 6. Since we could be in any frame we need to reserve
181 * for all of them. Sucks, but that's what you gotta do. Note that
182 * if we were instead scheduling 8 * 3 = 24 we'd do much better, but
183 * then we need more memory and time to do scheduling.
184 * - If interval is 4, easy.
185 * - If interval is 5, we again need interval 1. The schedule will be
186 * 0, 5, 2, 7, 4, 1, 6, 3, 0
187 * - If interval is 6, we need interval 2. 0, 6, 4, 2.
188 * - If interval is 7, we need interval 1.
189 * - If interval is 8, we need interval 8.
191 * If you do the math, you'll see that we need to pretend that interval is
192 * equal to the greatest_common_divisor(interval, periods_in_map).
194 * Note that at the moment this function tends to front-pack the schedule.
195 * In some cases that's really non-ideal (it's hard to schedule things that
196 * need to repeat every period). In other cases it's perfect (you can easily
197 * schedule bigger, less often repeating things).
199 * Here's the algorithm in action (8 periods, 5 bits per period):
200 * |** | |** | |** | |** | | OK 2 bits, intv 2 at 0
201 * |*****| ***|*****| ***|*****| ***|*****| ***| OK 3 bits, intv 3 at 2
202 * |*****|* ***|*****| ***|*****|* ***|*****| ***| OK 1 bits, intv 4 at 5
203 * |** |* |** | |** |* |** | | Remv 3 bits, intv 3 at 2
204 * |*** |* |*** | |*** |* |*** | | OK 1 bits, intv 6 at 2
205 * |**** |* * |**** | * |**** |* * |**** | * | OK 1 bits, intv 1 at 3
206 * |**** |**** |**** | *** |**** |**** |**** | *** | OK 2 bits, intv 2 at 6
207 * |*****|*****|*****| ****|*****|*****|*****| ****| OK 1 bits, intv 1 at 4
208 * |*****|*****|*****| ****|*****|*****|*****| ****| FAIL 1 bits, intv 1
209 * | ***|*****| ***| ****| ***|*****| ***| ****| Remv 2 bits, intv 2 at 0
210 * | ***| ****| ***| ****| ***| ****| ***| ****| Remv 1 bits, intv 4 at 5
211 * | **| ****| **| ****| **| ****| **| ****| Remv 1 bits, intv 6 at 2
212 * | *| ** *| *| ** *| *| ** *| *| ** *| Remv 1 bits, intv 1 at 3
213 * | *| *| *| *| *| *| *| *| Remv 2 bits, intv 2 at 6
214 * | | | | | | | | | Remv 1 bits, intv 1 at 4
215 * |** | |** | |** | |** | | OK 2 bits, intv 2 at 0
216 * |*** | |** | |*** | |** | | OK 1 bits, intv 4 at 2
217 * |*****| |** **| |*****| |** **| | OK 2 bits, intv 2 at 3
218 * |*****|* |** **| |*****|* |** **| | OK 1 bits, intv 4 at 5
219 * |*****|*** |** **| ** |*****|*** |** **| ** | OK 2 bits, intv 2 at 6
220 * |*****|*****|** **| ****|*****|*****|** **| ****| OK 2 bits, intv 2 at 8
221 * |*****|*****|*****| ****|*****|*****|*****| ****| OK 1 bits, intv 4 at 12
223 * This function is pretty generic and could be easily abstracted if anything
224 * needed similar scheduling.
226 * Returns either -ENOSPC or a >= 0 start bit which should be passed to the
227 * unschedule routine. The map bitmap will be updated on a non-error result.
229 static int pmap_schedule(unsigned long *map
, int bits_per_period
,
230 int periods_in_map
, int num_bits
,
231 int interval
, int start
, bool only_one_period
)
238 if (num_bits
> bits_per_period
)
241 /* Adjust interval as per description */
242 interval
= gcd(interval
, periods_in_map
);
244 interval_bits
= bits_per_period
* interval
;
245 to_reserve
= periods_in_map
/ interval
;
247 /* If start has gotten us past interval then we can't schedule */
248 if (start
>= interval_bits
)
252 /* Must fit within same period as start; end at begin of next */
253 first_end
= (start
/ bits_per_period
+ 1) * bits_per_period
;
255 /* Can fit anywhere in the first interval */
256 first_end
= interval_bits
;
259 * We'll try to pick the first repetition, then see if that time
260 * is free for each of the subsequent repetitions. If it's not
261 * we'll adjust the start time for the next search of the first
264 while (start
+ num_bits
<= first_end
) {
267 /* Need to stay within this period */
268 end
= (start
/ bits_per_period
+ 1) * bits_per_period
;
270 /* Look for num_bits us in this microframe starting at start */
271 start
= bitmap_find_next_zero_area(map
, end
, start
, num_bits
,
275 * We should get start >= end if we fail. We might be
276 * able to check the next microframe depending on the
277 * interval, so continue on (start already updated).
284 /* At this point we have a valid point for first one */
285 for (i
= 1; i
< to_reserve
; i
++) {
286 int ith_start
= start
+ interval_bits
* i
;
287 int ith_end
= end
+ interval_bits
* i
;
290 /* Use this as a dumb "check if bits are 0" */
291 ret
= bitmap_find_next_zero_area(
292 map
, ith_start
+ num_bits
, ith_start
, num_bits
,
295 /* We got the right place, continue checking */
296 if (ret
== ith_start
)
299 /* Move start up for next time and exit for loop */
300 ith_start
= bitmap_find_next_zero_area(
301 map
, ith_end
, ith_start
, num_bits
, 0);
302 if (ith_start
>= ith_end
)
303 /* Need a while new period next time */
306 start
= ith_start
- interval_bits
* i
;
310 /* If didn't exit the for loop with a break, we have success */
315 if (start
+ num_bits
> first_end
)
318 for (i
= 0; i
< to_reserve
; i
++) {
319 int ith_start
= start
+ interval_bits
* i
;
321 bitmap_set(map
, ith_start
, num_bits
);
328 * pmap_unschedule() - Undo work done by pmap_schedule()
330 * @map: See pmap_schedule().
331 * @bits_per_period: See pmap_schedule().
332 * @periods_in_map: See pmap_schedule().
333 * @num_bits: The number of bits that was passed to schedule.
334 * @interval: The interval that was passed to schedule.
335 * @start: The return value from pmap_schedule().
337 static void pmap_unschedule(unsigned long *map
, int bits_per_period
,
338 int periods_in_map
, int num_bits
,
339 int interval
, int start
)
345 /* Adjust interval as per description in pmap_schedule() */
346 interval
= gcd(interval
, periods_in_map
);
348 interval_bits
= bits_per_period
* interval
;
349 to_release
= periods_in_map
/ interval
;
351 for (i
= 0; i
< to_release
; i
++) {
352 int ith_start
= start
+ interval_bits
* i
;
354 bitmap_clear(map
, ith_start
, num_bits
);
359 * dwc2_get_ls_map() - Get the map used for the given qh
361 * @hsotg: The HCD state structure for the DWC OTG controller.
362 * @qh: QH for the periodic transfer.
364 * We'll always get the periodic map out of our TT. Note that even if we're
365 * running the host straight in low speed / full speed mode it appears as if
366 * a TT is allocated for us, so we'll use it. If that ever changes we can
367 * add logic here to get a map out of "hsotg" if !qh->do_split.
369 * Returns: the map or NULL if a map couldn't be found.
371 static unsigned long *dwc2_get_ls_map(struct dwc2_hsotg
*hsotg
,
376 /* Don't expect to be missing a TT and be doing low speed scheduling */
377 if (WARN_ON(!qh
->dwc_tt
))
380 /* Get the map and adjust if this is a multi_tt hub */
381 map
= qh
->dwc_tt
->periodic_bitmaps
;
382 if (qh
->dwc_tt
->usb_tt
->multi
)
383 map
+= DWC2_ELEMENTS_PER_LS_BITMAP
* qh
->ttport
;
388 #ifdef DWC2_PRINT_SCHEDULE
390 * cat_printf() - A printf() + strcat() helper
392 * This is useful for concatenating a bunch of strings where each string is
393 * constructed using printf.
395 * @buf: The destination buffer; will be updated to point after the printed
397 * @size: The number of bytes in the buffer (includes space for '\0').
398 * @fmt: The format for printf.
399 * @...: The args for printf.
401 static __printf(3, 4)
402 void cat_printf(char **buf
, size_t *size
, const char *fmt
, ...)
411 i
= vsnprintf(*buf
, *size
, fmt
, args
);
415 (*buf
)[*size
- 1] = '\0';
425 * pmap_print() - Print the given periodic map
427 * Will attempt to print out the periodic schedule.
429 * @map: See pmap_schedule().
430 * @bits_per_period: See pmap_schedule().
431 * @periods_in_map: See pmap_schedule().
432 * @period_name: The name of 1 period, like "uFrame"
433 * @units: The name of the units, like "us".
434 * @print_fn: The function to call for printing.
435 * @print_data: Opaque data to pass to the print function.
437 static void pmap_print(unsigned long *map
, int bits_per_period
,
438 int periods_in_map
, const char *period_name
,
440 void (*print_fn
)(const char *str
, void *data
),
445 for (period
= 0; period
< periods_in_map
; period
++) {
448 size_t buf_size
= sizeof(tmp
);
449 int period_start
= period
* bits_per_period
;
450 int period_end
= period_start
+ bits_per_period
;
453 bool printed
= false;
456 for (i
= period_start
; i
< period_end
+ 1; i
++) {
457 /* Handle case when ith bit is set */
458 if (i
< period_end
&&
459 bitmap_find_next_zero_area(map
, i
+ 1,
462 start
= i
- period_start
;
467 /* ith bit isn't set; don't care if count == 0 */
472 cat_printf(&buf
, &buf_size
, "%s %d: ",
473 period_name
, period
);
475 cat_printf(&buf
, &buf_size
, ", ");
478 cat_printf(&buf
, &buf_size
, "%d %s -%3d %s", start
,
479 units
, start
+ count
- 1, units
);
484 print_fn(tmp
, print_data
);
488 struct dwc2_qh_print_data
{
489 struct dwc2_hsotg
*hsotg
;
494 * dwc2_qh_print() - Helper function for dwc2_qh_schedule_print()
496 * @str: The string to print
497 * @data: A pointer to a struct dwc2_qh_print_data
499 static void dwc2_qh_print(const char *str
, void *data
)
501 struct dwc2_qh_print_data
*print_data
= data
;
503 dwc2_sch_dbg(print_data
->hsotg
, "QH=%p ...%s\n", print_data
->qh
, str
);
507 * dwc2_qh_schedule_print() - Print the periodic schedule
509 * @hsotg: The HCD state structure for the DWC OTG controller.
512 static void dwc2_qh_schedule_print(struct dwc2_hsotg
*hsotg
,
515 struct dwc2_qh_print_data print_data
= { hsotg
, qh
};
519 * The printing functions are quite slow and inefficient.
520 * If we don't have tracing turned on, don't run unless the special
521 * define is turned on.
524 if (qh
->schedule_low_speed
) {
525 unsigned long *map
= dwc2_get_ls_map(hsotg
, qh
);
527 dwc2_sch_dbg(hsotg
, "QH=%p LS/FS trans: %d=>%d us @ %d us",
529 DWC2_ROUND_US_TO_SLICE(qh
->device_us
),
530 DWC2_US_PER_SLICE
* qh
->ls_start_schedule_slice
);
534 "QH=%p Whole low/full speed map %p now:\n",
536 pmap_print(map
, DWC2_LS_PERIODIC_SLICES_PER_FRAME
,
537 DWC2_LS_SCHEDULE_FRAMES
, "Frame ", "slices",
538 dwc2_qh_print
, &print_data
);
542 for (i
= 0; i
< qh
->num_hs_transfers
; i
++) {
543 struct dwc2_hs_transfer_time
*trans_time
= qh
->hs_transfers
+ i
;
544 int uframe
= trans_time
->start_schedule_us
/
545 DWC2_HS_PERIODIC_US_PER_UFRAME
;
546 int rel_us
= trans_time
->start_schedule_us
%
547 DWC2_HS_PERIODIC_US_PER_UFRAME
;
550 "QH=%p HS trans #%d: %d us @ uFrame %d + %d us\n",
551 qh
, i
, trans_time
->duration_us
, uframe
, rel_us
);
553 if (qh
->num_hs_transfers
) {
554 dwc2_sch_dbg(hsotg
, "QH=%p Whole high speed map now:\n", qh
);
555 pmap_print(hsotg
->hs_periodic_bitmap
,
556 DWC2_HS_PERIODIC_US_PER_UFRAME
,
557 DWC2_HS_SCHEDULE_UFRAMES
, "uFrame", "us",
558 dwc2_qh_print
, &print_data
);
562 static inline void dwc2_qh_schedule_print(struct dwc2_hsotg
*hsotg
,
563 struct dwc2_qh
*qh
) {};
567 * dwc2_ls_pmap_schedule() - Schedule a low speed QH
569 * @hsotg: The HCD state structure for the DWC OTG controller.
570 * @qh: QH for the periodic transfer.
571 * @search_slice: We'll start trying to schedule at the passed slice.
572 * Remember that slices are the units of the low speed
573 * schedule (think 25us or so).
575 * Wraps pmap_schedule() with the right parameters for low speed scheduling.
577 * Normally we schedule low speed devices on the map associated with the TT.
579 * Returns: 0 for success or an error code.
581 static int dwc2_ls_pmap_schedule(struct dwc2_hsotg
*hsotg
, struct dwc2_qh
*qh
,
584 int slices
= DIV_ROUND_UP(qh
->device_us
, DWC2_US_PER_SLICE
);
585 unsigned long *map
= dwc2_get_ls_map(hsotg
, qh
);
592 * Schedule on the proper low speed map with our low speed scheduling
593 * parameters. Note that we use the "device_interval" here since
594 * we want the low speed interval and the only way we'd be in this
595 * function is if the device is low speed.
597 * If we happen to be doing low speed and high speed scheduling for the
598 * same transaction (AKA we have a split) we always do low speed first.
599 * That means we can always pass "false" for only_one_period (that
600 * parameters is only useful when we're trying to get one schedule to
601 * match what we already planned in the other schedule).
603 slice
= pmap_schedule(map
, DWC2_LS_PERIODIC_SLICES_PER_FRAME
,
604 DWC2_LS_SCHEDULE_FRAMES
, slices
,
605 qh
->device_interval
, search_slice
, false);
610 qh
->ls_start_schedule_slice
= slice
;
615 * dwc2_ls_pmap_unschedule() - Undo work done by dwc2_ls_pmap_schedule()
617 * @hsotg: The HCD state structure for the DWC OTG controller.
618 * @qh: QH for the periodic transfer.
620 static void dwc2_ls_pmap_unschedule(struct dwc2_hsotg
*hsotg
,
623 int slices
= DIV_ROUND_UP(qh
->device_us
, DWC2_US_PER_SLICE
);
624 unsigned long *map
= dwc2_get_ls_map(hsotg
, qh
);
626 /* Schedule should have failed, so no worries about no error code */
630 pmap_unschedule(map
, DWC2_LS_PERIODIC_SLICES_PER_FRAME
,
631 DWC2_LS_SCHEDULE_FRAMES
, slices
, qh
->device_interval
,
632 qh
->ls_start_schedule_slice
);
636 * dwc2_hs_pmap_schedule - Schedule in the main high speed schedule
638 * This will schedule something on the main dwc2 schedule.
640 * We'll start looking in qh->hs_transfers[index].start_schedule_us. We'll
641 * update this with the result upon success. We also use the duration from
642 * the same structure.
644 * @hsotg: The HCD state structure for the DWC OTG controller.
645 * @qh: QH for the periodic transfer.
646 * @only_one_period: If true we will limit ourselves to just looking at
647 * one period (aka one 100us chunk). This is used if we have
648 * already scheduled something on the low speed schedule and
649 * need to find something that matches on the high speed one.
650 * @index: The index into qh->hs_transfers that we're working with.
652 * Returns: 0 for success or an error code. Upon success the
653 * dwc2_hs_transfer_time specified by "index" will be updated.
655 static int dwc2_hs_pmap_schedule(struct dwc2_hsotg
*hsotg
, struct dwc2_qh
*qh
,
656 bool only_one_period
, int index
)
658 struct dwc2_hs_transfer_time
*trans_time
= qh
->hs_transfers
+ index
;
661 us
= pmap_schedule(hsotg
->hs_periodic_bitmap
,
662 DWC2_HS_PERIODIC_US_PER_UFRAME
,
663 DWC2_HS_SCHEDULE_UFRAMES
, trans_time
->duration_us
,
664 qh
->host_interval
, trans_time
->start_schedule_us
,
670 trans_time
->start_schedule_us
= us
;
675 * dwc2_ls_pmap_unschedule() - Undo work done by dwc2_hs_pmap_schedule()
677 * @hsotg: The HCD state structure for the DWC OTG controller.
678 * @qh: QH for the periodic transfer.
680 static void dwc2_hs_pmap_unschedule(struct dwc2_hsotg
*hsotg
,
681 struct dwc2_qh
*qh
, int index
)
683 struct dwc2_hs_transfer_time
*trans_time
= qh
->hs_transfers
+ index
;
685 pmap_unschedule(hsotg
->hs_periodic_bitmap
,
686 DWC2_HS_PERIODIC_US_PER_UFRAME
,
687 DWC2_HS_SCHEDULE_UFRAMES
, trans_time
->duration_us
,
688 qh
->host_interval
, trans_time
->start_schedule_us
);
692 * dwc2_uframe_schedule_split - Schedule a QH for a periodic split xfer.
694 * This is the most complicated thing in USB. We have to find matching time
695 * in both the global high speed schedule for the port and the low speed
696 * schedule for the TT associated with the given device.
698 * Being here means that the host must be running in high speed mode and the
699 * device is in low or full speed mode (and behind a hub).
701 * @hsotg: The HCD state structure for the DWC OTG controller.
702 * @qh: QH for the periodic transfer.
704 static int dwc2_uframe_schedule_split(struct dwc2_hsotg
*hsotg
,
707 int bytecount
= dwc2_hb_mult(qh
->maxp
) * dwc2_max_packet(qh
->maxp
);
710 int host_interval_in_sched
;
713 * The interval (how often to repeat) in the actual host schedule.
714 * See pmap_schedule() for gcd() explanation.
716 host_interval_in_sched
= gcd(qh
->host_interval
,
717 DWC2_HS_SCHEDULE_UFRAMES
);
720 * We always try to find space in the low speed schedule first, then
721 * try to find high speed time that matches. If we don't, we'll bump
722 * up the place we start searching in the low speed schedule and try
723 * again. To start we'll look right at the beginning of the low speed
726 * Note that this will tend to front-load the high speed schedule.
727 * We may eventually want to try to avoid this by either considering
728 * both schedules together or doing some sort of round robin.
732 while (ls_search_slice
< DWC2_LS_SCHEDULE_SLICES
) {
740 int first_data_bytes
;
741 int other_data_bytes
;
744 if (qh
->schedule_low_speed
) {
745 err
= dwc2_ls_pmap_schedule(hsotg
, qh
, ls_search_slice
);
748 * If we got an error here there's no other magic we
749 * can do, so bail. All the looping above is only
750 * helpful to redo things if we got a low speed slot
751 * and then couldn't find a matching high speed slot.
756 /* Must be missing the tt structure? Why? */
761 * This will give us a number 0 - 7 if
762 * DWC2_LS_SCHEDULE_FRAMES == 1, or 0 - 15 if == 2, or ...
764 start_s_uframe
= qh
->ls_start_schedule_slice
/
765 DWC2_SLICES_PER_UFRAME
;
767 /* Get a number that's always 0 - 7 */
768 rel_uframe
= (start_s_uframe
% 8);
771 * If we were going to start in uframe 7 then we would need to
772 * issue a start split in uframe 6, which spec says is not OK.
773 * Move on to the next full frame (assuming there is one).
775 * See 11.18.4 Host Split Transaction Scheduling Requirements
778 if (rel_uframe
== 7) {
779 if (qh
->schedule_low_speed
)
780 dwc2_ls_pmap_unschedule(hsotg
, qh
);
782 (qh
->ls_start_schedule_slice
/
783 DWC2_LS_PERIODIC_SLICES_PER_FRAME
+ 1) *
784 DWC2_LS_PERIODIC_SLICES_PER_FRAME
;
790 * - start split (frame -1)
791 * - complete split w/ data (frame +1)
792 * - complete split w/ data (frame +2)
794 * - complete split w/ data (frame +num_data_packets)
795 * - complete split w/ data (frame +num_data_packets+1)
796 * - complete split w/ data (frame +num_data_packets+2, max 8)
797 * ...though if frame was "0" then max is 7...
799 * For ISOC out we might need to do:
800 * - start split w/ data (frame -1)
801 * - start split w/ data (frame +0)
803 * - start split w/ data (frame +num_data_packets-2)
805 * For INTERRUPT in we might need to do:
806 * - start split (frame -1)
807 * - complete split w/ data (frame +1)
808 * - complete split w/ data (frame +2)
809 * - complete split w/ data (frame +3, max 8)
811 * For INTERRUPT out we might need to do:
812 * - start split w/ data (frame -1)
813 * - complete split (frame +1)
814 * - complete split (frame +2)
815 * - complete split (frame +3, max 8)
819 ssplit_s_uframe
= (start_s_uframe
+
820 host_interval_in_sched
- 1) %
821 host_interval_in_sched
;
822 if (qh
->ep_type
== USB_ENDPOINT_XFER_ISOC
&& !qh
->ep_is_in
)
823 second_s_uframe
= start_s_uframe
;
825 second_s_uframe
= start_s_uframe
+ 1;
827 /* First data transfer might not be all 188 bytes. */
828 first_data_bytes
= 188 -
829 DIV_ROUND_UP(188 * (qh
->ls_start_schedule_slice
%
830 DWC2_SLICES_PER_UFRAME
),
831 DWC2_SLICES_PER_UFRAME
);
832 if (first_data_bytes
> bytecount
)
833 first_data_bytes
= bytecount
;
834 other_data_bytes
= bytecount
- first_data_bytes
;
837 * For now, skip OUT xfers where first xfer is partial
839 * Main dwc2 code assumes:
840 * - INT transfers never get split in two.
841 * - ISOC transfers can always transfer 188 bytes the first
844 * Until that code is fixed, try again if the first transfer
845 * couldn't transfer everything.
847 * This code can be removed if/when the rest of dwc2 handles
848 * the above cases. Until it's fixed we just won't be able
849 * to schedule quite as tightly.
852 (first_data_bytes
!= min_t(int, 188, bytecount
))) {
854 "QH=%p avoiding broken 1st xfer (%d, %d)\n",
855 qh
, first_data_bytes
, bytecount
);
856 if (qh
->schedule_low_speed
)
857 dwc2_ls_pmap_unschedule(hsotg
, qh
);
858 ls_search_slice
= (start_s_uframe
+ 1) *
859 DWC2_SLICES_PER_UFRAME
;
863 /* Start by assuming transfers for the bytes */
864 qh
->num_hs_transfers
= 1 + DIV_ROUND_UP(other_data_bytes
, 188);
867 * Everything except ISOC OUT has extra transfers. Rules are
868 * complicated. See 11.18.4 Host Split Transaction Scheduling
869 * Requirements bullet 3.
871 if (qh
->ep_type
== USB_ENDPOINT_XFER_INT
) {
873 qh
->num_hs_transfers
+= 2;
875 qh
->num_hs_transfers
+= 3;
879 * First is start split, middle/end is data.
880 * Allocate full data bytes for all data.
883 middle_count
= bytecount
;
884 end_count
= bytecount
;
887 * First is data, middle/end is complete.
888 * First transfer and second can have data.
889 * Rest should just have complete split.
891 first_count
= first_data_bytes
;
892 middle_count
= max_t(int, 4, other_data_bytes
);
899 /* Account for the start split */
900 qh
->num_hs_transfers
++;
902 /* Calculate "L" value from spec */
903 last
= rel_uframe
+ qh
->num_hs_transfers
+ 1;
905 /* Start with basic case */
907 qh
->num_hs_transfers
+= 2;
909 qh
->num_hs_transfers
+= 1;
911 /* Adjust downwards */
912 if (last
>= 6 && rel_uframe
== 0)
913 qh
->num_hs_transfers
--;
915 /* 1st = start; rest can contain data */
917 middle_count
= min_t(int, 188, bytecount
);
918 end_count
= middle_count
;
920 /* All contain data, last might be smaller */
921 first_count
= first_data_bytes
;
922 middle_count
= min_t(int, 188,
924 end_count
= other_data_bytes
% 188;
928 /* Assign durations per uFrame */
929 qh
->hs_transfers
[0].duration_us
= HS_USECS_ISO(first_count
);
930 for (i
= 1; i
< qh
->num_hs_transfers
- 1; i
++)
931 qh
->hs_transfers
[i
].duration_us
=
932 HS_USECS_ISO(middle_count
);
933 if (qh
->num_hs_transfers
> 1)
934 qh
->hs_transfers
[qh
->num_hs_transfers
- 1].duration_us
=
935 HS_USECS_ISO(end_count
);
938 * Assign start us. The call below to dwc2_hs_pmap_schedule()
939 * will start with these numbers but may adjust within the same
942 qh
->hs_transfers
[0].start_schedule_us
=
943 ssplit_s_uframe
* DWC2_HS_PERIODIC_US_PER_UFRAME
;
944 for (i
= 1; i
< qh
->num_hs_transfers
; i
++)
945 qh
->hs_transfers
[i
].start_schedule_us
=
946 ((second_s_uframe
+ i
- 1) %
947 DWC2_HS_SCHEDULE_UFRAMES
) *
948 DWC2_HS_PERIODIC_US_PER_UFRAME
;
950 /* Try to schedule with filled in hs_transfers above */
951 for (i
= 0; i
< qh
->num_hs_transfers
; i
++) {
952 err
= dwc2_hs_pmap_schedule(hsotg
, qh
, true, i
);
957 /* If we scheduled all w/out breaking out then we're all good */
958 if (i
== qh
->num_hs_transfers
)
962 dwc2_hs_pmap_unschedule(hsotg
, qh
, i
);
964 if (qh
->schedule_low_speed
)
965 dwc2_ls_pmap_unschedule(hsotg
, qh
);
967 /* Try again starting in the next microframe */
968 ls_search_slice
= (start_s_uframe
+ 1) * DWC2_SLICES_PER_UFRAME
;
971 if (ls_search_slice
>= DWC2_LS_SCHEDULE_SLICES
)
978 * dwc2_uframe_schedule_hs - Schedule a QH for a periodic high speed xfer.
980 * Basically this just wraps dwc2_hs_pmap_schedule() to provide a clean
983 * @hsotg: The HCD state structure for the DWC OTG controller.
984 * @qh: QH for the periodic transfer.
986 static int dwc2_uframe_schedule_hs(struct dwc2_hsotg
*hsotg
, struct dwc2_qh
*qh
)
988 /* In non-split host and device time are the same */
989 WARN_ON(qh
->host_us
!= qh
->device_us
);
990 WARN_ON(qh
->host_interval
!= qh
->device_interval
);
991 WARN_ON(qh
->num_hs_transfers
!= 1);
993 /* We'll have one transfer; init start to 0 before calling scheduler */
994 qh
->hs_transfers
[0].start_schedule_us
= 0;
995 qh
->hs_transfers
[0].duration_us
= qh
->host_us
;
997 return dwc2_hs_pmap_schedule(hsotg
, qh
, false, 0);
1001 * dwc2_uframe_schedule_ls - Schedule a QH for a periodic low/full speed xfer.
1003 * Basically this just wraps dwc2_ls_pmap_schedule() to provide a clean
1006 * @hsotg: The HCD state structure for the DWC OTG controller.
1007 * @qh: QH for the periodic transfer.
1009 static int dwc2_uframe_schedule_ls(struct dwc2_hsotg
*hsotg
, struct dwc2_qh
*qh
)
1011 /* In non-split host and device time are the same */
1012 WARN_ON(qh
->host_us
!= qh
->device_us
);
1013 WARN_ON(qh
->host_interval
!= qh
->device_interval
);
1014 WARN_ON(!qh
->schedule_low_speed
);
1016 /* Run on the main low speed schedule (no split = no hub = no TT) */
1017 return dwc2_ls_pmap_schedule(hsotg
, qh
, 0);
1021 * dwc2_uframe_schedule - Schedule a QH for a periodic xfer.
1023 * Calls one of the 3 sub-function depending on what type of transfer this QH
1024 * is for. Also adds some printing.
1026 * @hsotg: The HCD state structure for the DWC OTG controller.
1027 * @qh: QH for the periodic transfer.
1029 static int dwc2_uframe_schedule(struct dwc2_hsotg
*hsotg
, struct dwc2_qh
*qh
)
1033 if (qh
->dev_speed
== USB_SPEED_HIGH
)
1034 ret
= dwc2_uframe_schedule_hs(hsotg
, qh
);
1035 else if (!qh
->do_split
)
1036 ret
= dwc2_uframe_schedule_ls(hsotg
, qh
);
1038 ret
= dwc2_uframe_schedule_split(hsotg
, qh
);
1041 dwc2_sch_dbg(hsotg
, "QH=%p Failed to schedule %d\n", qh
, ret
);
1043 dwc2_qh_schedule_print(hsotg
, qh
);
1049 * dwc2_uframe_unschedule - Undoes dwc2_uframe_schedule().
1051 * @hsotg: The HCD state structure for the DWC OTG controller.
1052 * @qh: QH for the periodic transfer.
1054 static void dwc2_uframe_unschedule(struct dwc2_hsotg
*hsotg
, struct dwc2_qh
*qh
)
1058 for (i
= 0; i
< qh
->num_hs_transfers
; i
++)
1059 dwc2_hs_pmap_unschedule(hsotg
, qh
, i
);
1061 if (qh
->schedule_low_speed
)
1062 dwc2_ls_pmap_unschedule(hsotg
, qh
);
1064 dwc2_sch_dbg(hsotg
, "QH=%p Unscheduled\n", qh
);
1068 * dwc2_pick_first_frame() - Choose 1st frame for qh that's already scheduled
1070 * Takes a qh that has already been scheduled (which means we know we have the
1071 * bandwdith reserved for us) and set the next_active_frame and the
1072 * start_active_frame.
1074 * This is expected to be called on qh's that weren't previously actively
1075 * running. It just picks the next frame that we can fit into without any
1076 * thought about the past.
1078 * @hsotg: The HCD state structure for the DWC OTG controller
1079 * @qh: QH for a periodic endpoint
1082 static void dwc2_pick_first_frame(struct dwc2_hsotg
*hsotg
, struct dwc2_qh
*qh
)
1086 u16 next_active_frame
;
1091 * Use the real frame number rather than the cached value as of the
1092 * last SOF to give us a little extra slop.
1094 frame_number
= dwc2_hcd_get_frame_number(hsotg
);
1097 * We wouldn't want to start any earlier than the next frame just in
1098 * case the frame number ticks as we're doing this calculation.
1100 * NOTE: if we could quantify how long till we actually get scheduled
1101 * we might be able to avoid the "+ 1" by looking at the upper part of
1102 * HFNUM (the FRREM field). For now we'll just use the + 1 though.
1104 earliest_frame
= dwc2_frame_num_inc(frame_number
, 1);
1105 next_active_frame
= earliest_frame
;
1107 /* Get the "no microframe schduler" out of the way... */
1108 if (!hsotg
->params
.uframe_sched
) {
1110 /* Splits are active at microframe 0 minus 1 */
1111 next_active_frame
|= 0x7;
1115 if (qh
->dev_speed
== USB_SPEED_HIGH
|| qh
->do_split
) {
1117 * We're either at high speed or we're doing a split (which
1118 * means we're talking high speed to a hub). In any case
1119 * the first frame should be based on when the first scheduled
1122 WARN_ON(qh
->num_hs_transfers
< 1);
1124 relative_frame
= qh
->hs_transfers
[0].start_schedule_us
/
1125 DWC2_HS_PERIODIC_US_PER_UFRAME
;
1127 /* Adjust interval as per high speed schedule */
1128 interval
= gcd(qh
->host_interval
, DWC2_HS_SCHEDULE_UFRAMES
);
1132 * Low or full speed directly on dwc2. Just about the same
1133 * as high speed but on a different schedule and with slightly
1134 * different adjustments. Note that this works because when
1135 * the host and device are both low speed then frames in the
1136 * controller tick at low speed.
1138 relative_frame
= qh
->ls_start_schedule_slice
/
1139 DWC2_LS_PERIODIC_SLICES_PER_FRAME
;
1140 interval
= gcd(qh
->host_interval
, DWC2_LS_SCHEDULE_FRAMES
);
1143 /* Scheduler messed up if frame is past interval */
1144 WARN_ON(relative_frame
>= interval
);
1147 * We know interval must divide (HFNUM_MAX_FRNUM + 1) now that we've
1148 * done the gcd(), so it's safe to move to the beginning of the current
1149 * interval like this.
1151 * After this we might be before earliest_frame, but don't worry,
1154 next_active_frame
= (next_active_frame
/ interval
) * interval
;
1157 * Actually choose to start at the frame number we've been
1160 next_active_frame
= dwc2_frame_num_inc(next_active_frame
,
1164 * We actually need 1 frame before since the next_active_frame is
1165 * the frame number we'll be put on the ready list and we won't be on
1166 * the bus until 1 frame later.
1168 next_active_frame
= dwc2_frame_num_dec(next_active_frame
, 1);
1171 * By now we might actually be before the earliest_frame. Let's move
1172 * up intervals until we're not.
1174 while (dwc2_frame_num_gt(earliest_frame
, next_active_frame
))
1175 next_active_frame
= dwc2_frame_num_inc(next_active_frame
,
1179 qh
->next_active_frame
= next_active_frame
;
1180 qh
->start_active_frame
= next_active_frame
;
1182 dwc2_sch_vdbg(hsotg
, "QH=%p First fn=%04x nxt=%04x\n",
1183 qh
, frame_number
, qh
->next_active_frame
);
1187 * dwc2_do_reserve() - Make a periodic reservation
1189 * Try to allocate space in the periodic schedule. Depending on parameters
1190 * this might use the microframe scheduler or the dumb scheduler.
1192 * @hsotg: The HCD state structure for the DWC OTG controller
1193 * @qh: QH for the periodic transfer.
1195 * Returns: 0 upon success; error upon failure.
1197 static int dwc2_do_reserve(struct dwc2_hsotg
*hsotg
, struct dwc2_qh
*qh
)
1201 if (hsotg
->params
.uframe_sched
) {
1202 status
= dwc2_uframe_schedule(hsotg
, qh
);
1204 status
= dwc2_periodic_channel_available(hsotg
);
1206 dev_info(hsotg
->dev
,
1207 "%s: No host channel available for periodic transfer\n",
1212 status
= dwc2_check_periodic_bandwidth(hsotg
, qh
);
1217 "%s: Insufficient periodic bandwidth for periodic transfer\n",
1222 if (!hsotg
->params
.uframe_sched
)
1223 /* Reserve periodic channel */
1224 hsotg
->periodic_channels
++;
1226 /* Update claimed usecs per (micro)frame */
1227 hsotg
->periodic_usecs
+= qh
->host_us
;
1229 dwc2_pick_first_frame(hsotg
, qh
);
1235 * dwc2_do_unreserve() - Actually release the periodic reservation
1237 * This function actually releases the periodic bandwidth that was reserved
1240 * @hsotg: The HCD state structure for the DWC OTG controller
1241 * @qh: QH for the periodic transfer.
1243 static void dwc2_do_unreserve(struct dwc2_hsotg
*hsotg
, struct dwc2_qh
*qh
)
1245 assert_spin_locked(&hsotg
->lock
);
1247 WARN_ON(!qh
->unreserve_pending
);
1249 /* No more unreserve pending--we're doing it */
1250 qh
->unreserve_pending
= false;
1252 if (WARN_ON(!list_empty(&qh
->qh_list_entry
)))
1253 list_del_init(&qh
->qh_list_entry
);
1255 /* Update claimed usecs per (micro)frame */
1256 hsotg
->periodic_usecs
-= qh
->host_us
;
1258 if (hsotg
->params
.uframe_sched
) {
1259 dwc2_uframe_unschedule(hsotg
, qh
);
1261 /* Release periodic channel reservation */
1262 hsotg
->periodic_channels
--;
1267 * dwc2_unreserve_timer_fn() - Timer function to release periodic reservation
1269 * According to the kernel doc for usb_submit_urb() (specifically the part about
1270 * "Reserved Bandwidth Transfers"), we need to keep a reservation active as
1271 * long as a device driver keeps submitting. Since we're using HCD_BH to give
1272 * back the URB we need to give the driver a little bit of time before we
1273 * release the reservation. This worker is called after the appropriate
1276 * @work: Pointer to a qh unreserve_work.
1278 static void dwc2_unreserve_timer_fn(unsigned long data
)
1280 struct dwc2_qh
*qh
= (struct dwc2_qh
*)data
;
1281 struct dwc2_hsotg
*hsotg
= qh
->hsotg
;
1282 unsigned long flags
;
1285 * Wait for the lock, or for us to be scheduled again. We
1286 * could be scheduled again if:
1287 * - We started executing but didn't get the lock yet.
1288 * - A new reservation came in, but cancel didn't take effect
1289 * because we already started executing.
1290 * - The timer has been kicked again.
1291 * In that case cancel and wait for the next call.
1293 while (!spin_trylock_irqsave(&hsotg
->lock
, flags
)) {
1294 if (timer_pending(&qh
->unreserve_timer
))
1299 * Might be no more unreserve pending if:
1300 * - We started executing but didn't get the lock yet.
1301 * - A new reservation came in, but cancel didn't take effect
1302 * because we already started executing.
1304 * We can't put this in the loop above because unreserve_pending needs
1305 * to be accessed under lock, so we can only check it once we got the
1308 if (qh
->unreserve_pending
)
1309 dwc2_do_unreserve(hsotg
, qh
);
1311 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
1315 * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a
1316 * host channel is large enough to handle the maximum data transfer in a single
1317 * (micro)frame for a periodic transfer
1319 * @hsotg: The HCD state structure for the DWC OTG controller
1320 * @qh: QH for a periodic endpoint
1322 * Return: 0 if successful, negative error code otherwise
1324 static int dwc2_check_max_xfer_size(struct dwc2_hsotg
*hsotg
,
1328 u32 max_channel_xfer_size
;
1331 max_xfer_size
= dwc2_max_packet(qh
->maxp
) * dwc2_hb_mult(qh
->maxp
);
1332 max_channel_xfer_size
= hsotg
->params
.max_transfer_size
;
1334 if (max_xfer_size
> max_channel_xfer_size
) {
1336 "%s: Periodic xfer length %d > max xfer length for channel %d\n",
1337 __func__
, max_xfer_size
, max_channel_xfer_size
);
1345 * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in
1346 * the periodic schedule
1348 * @hsotg: The HCD state structure for the DWC OTG controller
1349 * @qh: QH for the periodic transfer. The QH should already contain the
1350 * scheduling information.
1352 * Return: 0 if successful, negative error code otherwise
1354 static int dwc2_schedule_periodic(struct dwc2_hsotg
*hsotg
, struct dwc2_qh
*qh
)
1358 status
= dwc2_check_max_xfer_size(hsotg
, qh
);
1361 "%s: Channel max transfer size too small for periodic transfer\n",
1366 /* Cancel pending unreserve; if canceled OK, unreserve was pending */
1367 if (del_timer(&qh
->unreserve_timer
))
1368 WARN_ON(!qh
->unreserve_pending
);
1371 * Only need to reserve if there's not an unreserve pending, since if an
1372 * unreserve is pending then by definition our old reservation is still
1373 * valid. Unreserve might still be pending even if we didn't cancel if
1374 * dwc2_unreserve_timer_fn() already started. Code in the timer handles
1377 if (!qh
->unreserve_pending
) {
1378 status
= dwc2_do_reserve(hsotg
, qh
);
1383 * It might have been a while, so make sure that frame_number
1384 * is still good. Note: we could also try to use the similar
1385 * dwc2_next_periodic_start() but that schedules much more
1386 * tightly and we might need to hurry and queue things up.
1388 if (dwc2_frame_num_le(qh
->next_active_frame
,
1389 hsotg
->frame_number
))
1390 dwc2_pick_first_frame(hsotg
, qh
);
1393 qh
->unreserve_pending
= 0;
1395 if (hsotg
->params
.dma_desc_enable
)
1396 /* Don't rely on SOF and start in ready schedule */
1397 list_add_tail(&qh
->qh_list_entry
, &hsotg
->periodic_sched_ready
);
1399 /* Always start in inactive schedule */
1400 list_add_tail(&qh
->qh_list_entry
,
1401 &hsotg
->periodic_sched_inactive
);
1407 * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer
1408 * from the periodic schedule
1410 * @hsotg: The HCD state structure for the DWC OTG controller
1411 * @qh: QH for the periodic transfer
1413 static void dwc2_deschedule_periodic(struct dwc2_hsotg
*hsotg
,
1418 assert_spin_locked(&hsotg
->lock
);
1421 * Schedule the unreserve to happen in a little bit. Cases here:
1422 * - Unreserve worker might be sitting there waiting to grab the lock.
1423 * In this case it will notice it's been schedule again and will
1425 * - Unreserve worker might not be scheduled.
1427 * We should never already be scheduled since dwc2_schedule_periodic()
1428 * should have canceled the scheduled unreserve timer (hence the
1429 * warning on did_modify).
1431 * We add + 1 to the timer to guarantee that at least 1 jiffy has
1432 * passed (otherwise if the jiffy counter might tick right after we
1433 * read it and we'll get no delay).
1435 did_modify
= mod_timer(&qh
->unreserve_timer
,
1436 jiffies
+ DWC2_UNRESERVE_DELAY
+ 1);
1437 WARN_ON(did_modify
);
1438 qh
->unreserve_pending
= 1;
1440 list_del_init(&qh
->qh_list_entry
);
1444 * dwc2_qh_init() - Initializes a QH structure
1446 * @hsotg: The HCD state structure for the DWC OTG controller
1447 * @qh: The QH to init
1448 * @urb: Holds the information about the device/endpoint needed to initialize
1450 * @mem_flags: Flags for allocating memory.
1452 static void dwc2_qh_init(struct dwc2_hsotg
*hsotg
, struct dwc2_qh
*qh
,
1453 struct dwc2_hcd_urb
*urb
, gfp_t mem_flags
)
1455 int dev_speed
= dwc2_host_get_speed(hsotg
, urb
->priv
);
1456 u8 ep_type
= dwc2_hcd_get_pipe_type(&urb
->pipe_info
);
1457 bool ep_is_in
= !!dwc2_hcd_is_pipe_in(&urb
->pipe_info
);
1458 bool ep_is_isoc
= (ep_type
== USB_ENDPOINT_XFER_ISOC
);
1459 bool ep_is_int
= (ep_type
== USB_ENDPOINT_XFER_INT
);
1460 u32 hprt
= dwc2_readl(hsotg
->regs
+ HPRT0
);
1461 u32 prtspd
= (hprt
& HPRT0_SPD_MASK
) >> HPRT0_SPD_SHIFT
;
1462 bool do_split
= (prtspd
== HPRT0_SPD_HIGH_SPEED
&&
1463 dev_speed
!= USB_SPEED_HIGH
);
1464 int maxp
= dwc2_hcd_get_mps(&urb
->pipe_info
);
1465 int bytecount
= dwc2_hb_mult(maxp
) * dwc2_max_packet(maxp
);
1470 setup_timer(&qh
->unreserve_timer
, dwc2_unreserve_timer_fn
,
1472 qh
->ep_type
= ep_type
;
1473 qh
->ep_is_in
= ep_is_in
;
1475 qh
->data_toggle
= DWC2_HC_PID_DATA0
;
1477 INIT_LIST_HEAD(&qh
->qtd_list
);
1478 INIT_LIST_HEAD(&qh
->qh_list_entry
);
1480 qh
->do_split
= do_split
;
1481 qh
->dev_speed
= dev_speed
;
1483 if (ep_is_int
|| ep_is_isoc
) {
1484 /* Compute scheduling parameters once and save them */
1485 int host_speed
= do_split
? USB_SPEED_HIGH
: dev_speed
;
1486 struct dwc2_tt
*dwc_tt
= dwc2_host_get_tt_info(hsotg
, urb
->priv
,
1491 qh
->dwc_tt
= dwc_tt
;
1493 qh
->host_us
= NS_TO_US(usb_calc_bus_time(host_speed
, ep_is_in
,
1494 ep_is_isoc
, bytecount
));
1495 device_ns
= usb_calc_bus_time(dev_speed
, ep_is_in
,
1496 ep_is_isoc
, bytecount
);
1498 if (do_split
&& dwc_tt
)
1499 device_ns
+= dwc_tt
->usb_tt
->think_time
;
1500 qh
->device_us
= NS_TO_US(device_ns
);
1502 qh
->device_interval
= urb
->interval
;
1503 qh
->host_interval
= urb
->interval
* (do_split
? 8 : 1);
1506 * Schedule low speed if we're running the host in low or
1507 * full speed OR if we've got a "TT" to deal with to access this
1510 qh
->schedule_low_speed
= prtspd
!= HPRT0_SPD_HIGH_SPEED
||
1514 /* We won't know num transfers until we schedule */
1515 qh
->num_hs_transfers
= -1;
1516 } else if (dev_speed
== USB_SPEED_HIGH
) {
1517 qh
->num_hs_transfers
= 1;
1519 qh
->num_hs_transfers
= 0;
1522 /* We'll schedule later when we have something to do */
1525 switch (dev_speed
) {
1529 case USB_SPEED_FULL
:
1532 case USB_SPEED_HIGH
:
1540 switch (qh
->ep_type
) {
1541 case USB_ENDPOINT_XFER_ISOC
:
1542 type
= "isochronous";
1544 case USB_ENDPOINT_XFER_INT
:
1547 case USB_ENDPOINT_XFER_CONTROL
:
1550 case USB_ENDPOINT_XFER_BULK
:
1558 dwc2_sch_dbg(hsotg
, "QH=%p Init %s, %s speed, %d bytes:\n", qh
, type
,
1560 dwc2_sch_dbg(hsotg
, "QH=%p ...addr=%d, ep=%d, %s\n", qh
,
1561 dwc2_hcd_get_dev_addr(&urb
->pipe_info
),
1562 dwc2_hcd_get_ep_num(&urb
->pipe_info
),
1563 ep_is_in
? "IN" : "OUT");
1564 if (ep_is_int
|| ep_is_isoc
) {
1566 "QH=%p ...duration: host=%d us, device=%d us\n",
1567 qh
, qh
->host_us
, qh
->device_us
);
1568 dwc2_sch_dbg(hsotg
, "QH=%p ...interval: host=%d, device=%d\n",
1569 qh
, qh
->host_interval
, qh
->device_interval
);
1570 if (qh
->schedule_low_speed
)
1571 dwc2_sch_dbg(hsotg
, "QH=%p ...low speed schedule=%p\n",
1572 qh
, dwc2_get_ls_map(hsotg
, qh
));
1577 * dwc2_hcd_qh_create() - Allocates and initializes a QH
1579 * @hsotg: The HCD state structure for the DWC OTG controller
1580 * @urb: Holds the information about the device/endpoint needed
1581 * to initialize the QH
1582 * @atomic_alloc: Flag to do atomic allocation if needed
1584 * Return: Pointer to the newly allocated QH, or NULL on error
1586 struct dwc2_qh
*dwc2_hcd_qh_create(struct dwc2_hsotg
*hsotg
,
1587 struct dwc2_hcd_urb
*urb
,
1595 /* Allocate memory */
1596 qh
= kzalloc(sizeof(*qh
), mem_flags
);
1600 dwc2_qh_init(hsotg
, qh
, urb
, mem_flags
);
1602 if (hsotg
->params
.dma_desc_enable
&&
1603 dwc2_hcd_qh_init_ddma(hsotg
, qh
, mem_flags
) < 0) {
1604 dwc2_hcd_qh_free(hsotg
, qh
);
1612 * dwc2_hcd_qh_free() - Frees the QH
1614 * @hsotg: HCD instance
1615 * @qh: The QH to free
1617 * QH should already be removed from the list. QTD list should already be empty
1618 * if called from URB Dequeue.
1620 * Must NOT be called with interrupt disabled or spinlock held
1622 void dwc2_hcd_qh_free(struct dwc2_hsotg
*hsotg
, struct dwc2_qh
*qh
)
1624 /* Make sure any unreserve work is finished. */
1625 if (del_timer_sync(&qh
->unreserve_timer
)) {
1626 unsigned long flags
;
1628 spin_lock_irqsave(&hsotg
->lock
, flags
);
1629 dwc2_do_unreserve(hsotg
, qh
);
1630 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
1632 dwc2_host_put_tt_info(hsotg
, qh
->dwc_tt
);
1635 dwc2_hcd_qh_free_ddma(hsotg
, qh
);
1640 * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic
1641 * schedule if it is not already in the schedule. If the QH is already in
1642 * the schedule, no action is taken.
1644 * @hsotg: The HCD state structure for the DWC OTG controller
1645 * @qh: The QH to add
1647 * Return: 0 if successful, negative error code otherwise
1649 int dwc2_hcd_qh_add(struct dwc2_hsotg
*hsotg
, struct dwc2_qh
*qh
)
1655 dev_vdbg(hsotg
->dev
, "%s()\n", __func__
);
1657 if (!list_empty(&qh
->qh_list_entry
))
1658 /* QH already in a schedule */
1661 /* Add the new QH to the appropriate schedule */
1662 if (dwc2_qh_is_non_per(qh
)) {
1663 /* Schedule right away */
1664 qh
->start_active_frame
= hsotg
->frame_number
;
1665 qh
->next_active_frame
= qh
->start_active_frame
;
1667 /* Always start in inactive schedule */
1668 list_add_tail(&qh
->qh_list_entry
,
1669 &hsotg
->non_periodic_sched_inactive
);
1673 status
= dwc2_schedule_periodic(hsotg
, qh
);
1676 if (!hsotg
->periodic_qh_count
) {
1677 intr_mask
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
1678 intr_mask
|= GINTSTS_SOF
;
1679 dwc2_writel(intr_mask
, hsotg
->regs
+ GINTMSK
);
1681 hsotg
->periodic_qh_count
++;
1687 * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic
1688 * schedule. Memory is not freed.
1690 * @hsotg: The HCD state structure
1691 * @qh: QH to remove from schedule
1693 void dwc2_hcd_qh_unlink(struct dwc2_hsotg
*hsotg
, struct dwc2_qh
*qh
)
1697 dev_vdbg(hsotg
->dev
, "%s()\n", __func__
);
1699 if (list_empty(&qh
->qh_list_entry
))
1700 /* QH is not in a schedule */
1703 if (dwc2_qh_is_non_per(qh
)) {
1704 if (hsotg
->non_periodic_qh_ptr
== &qh
->qh_list_entry
)
1705 hsotg
->non_periodic_qh_ptr
=
1706 hsotg
->non_periodic_qh_ptr
->next
;
1707 list_del_init(&qh
->qh_list_entry
);
1711 dwc2_deschedule_periodic(hsotg
, qh
);
1712 hsotg
->periodic_qh_count
--;
1713 if (!hsotg
->periodic_qh_count
&&
1714 !hsotg
->params
.dma_desc_enable
) {
1715 intr_mask
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
1716 intr_mask
&= ~GINTSTS_SOF
;
1717 dwc2_writel(intr_mask
, hsotg
->regs
+ GINTMSK
);
1722 * dwc2_next_for_periodic_split() - Set next_active_frame midway thru a split.
1724 * This is called for setting next_active_frame for periodic splits for all but
1725 * the first packet of the split. Confusing? I thought so...
1727 * Periodic splits are single low/full speed transfers that we end up splitting
1728 * up into several high speed transfers. They always fit into one full (1 ms)
1729 * frame but might be split over several microframes (125 us each). We to put
1730 * each of the parts on a very specific high speed frame.
1732 * This function figures out where the next active uFrame needs to be.
1734 * @hsotg: The HCD state structure
1735 * @qh: QH for the periodic transfer.
1736 * @frame_number: The current frame number.
1738 * Return: number missed by (or 0 if we didn't miss).
1740 static int dwc2_next_for_periodic_split(struct dwc2_hsotg
*hsotg
,
1741 struct dwc2_qh
*qh
, u16 frame_number
)
1743 u16 old_frame
= qh
->next_active_frame
;
1744 u16 prev_frame_number
= dwc2_frame_num_dec(frame_number
, 1);
1749 * See dwc2_uframe_schedule_split() for split scheduling.
1751 * Basically: increment 1 normally, but 2 right after the start split
1752 * (except for ISOC out).
1754 if (old_frame
== qh
->start_active_frame
&&
1755 !(qh
->ep_type
== USB_ENDPOINT_XFER_ISOC
&& !qh
->ep_is_in
))
1760 qh
->next_active_frame
= dwc2_frame_num_inc(old_frame
, incr
);
1763 * Note that it's OK for frame_number to be 1 frame past
1764 * next_active_frame. Remember that next_active_frame is supposed to
1765 * be 1 frame _before_ when we want to be scheduled. If we're 1 frame
1766 * past it just means schedule ASAP.
1768 * It's _not_ OK, however, if we're more than one frame past.
1770 if (dwc2_frame_num_gt(prev_frame_number
, qh
->next_active_frame
)) {
1772 * OOPS, we missed. That's actually pretty bad since
1773 * the hub will be unhappy; try ASAP I guess.
1775 missed
= dwc2_frame_num_dec(prev_frame_number
,
1776 qh
->next_active_frame
);
1777 qh
->next_active_frame
= frame_number
;
1784 * dwc2_next_periodic_start() - Set next_active_frame for next transfer start
1786 * This is called for setting next_active_frame for a periodic transfer for
1787 * all cases other than midway through a periodic split. This will also update
1788 * start_active_frame.
1790 * Since we _always_ keep start_active_frame as the start of the previous
1791 * transfer this is normally pretty easy: we just add our interval to
1792 * start_active_frame and we've got our answer.
1794 * The tricks come into play if we miss. In that case we'll look for the next
1795 * slot we can fit into.
1797 * @hsotg: The HCD state structure
1798 * @qh: QH for the periodic transfer.
1799 * @frame_number: The current frame number.
1801 * Return: number missed by (or 0 if we didn't miss).
1803 static int dwc2_next_periodic_start(struct dwc2_hsotg
*hsotg
,
1804 struct dwc2_qh
*qh
, u16 frame_number
)
1807 u16 interval
= qh
->host_interval
;
1808 u16 prev_frame_number
= dwc2_frame_num_dec(frame_number
, 1);
1810 qh
->start_active_frame
= dwc2_frame_num_inc(qh
->start_active_frame
,
1814 * The dwc2_frame_num_gt() function used below won't work terribly well
1815 * with if we just incremented by a really large intervals since the
1816 * frame counter only goes to 0x3fff. It's terribly unlikely that we
1817 * will have missed in this case anyway. Just go to exit. If we want
1818 * to try to do better we'll need to keep track of a bigger counter
1819 * somewhere in the driver and handle overflows.
1821 if (interval
>= 0x1000)
1825 * Test for misses, which is when it's too late to schedule.
1827 * A few things to note:
1828 * - We compare against prev_frame_number since start_active_frame
1829 * and next_active_frame are always 1 frame before we want things
1830 * to be active and we assume we can still get scheduled in the
1831 * current frame number.
1832 * - It's possible for start_active_frame (now incremented) to be
1833 * next_active_frame if we got an EO MISS (even_odd miss) which
1834 * basically means that we detected there wasn't enough time for
1835 * the last packet and dwc2_hc_set_even_odd_frame() rescheduled us
1836 * at the last second. We want to make sure we don't schedule
1837 * another transfer for the same frame. My test webcam doesn't seem
1838 * terribly upset by missing a transfer but really doesn't like when
1839 * we do two transfers in the same frame.
1840 * - Some misses are expected. Specifically, in order to work
1841 * perfectly dwc2 really needs quite spectacular interrupt latency
1842 * requirements. It needs to be able to handle its interrupts
1843 * completely within 125 us of them being asserted. That not only
1844 * means that the dwc2 interrupt handler needs to be fast but it
1845 * means that nothing else in the system has to block dwc2 for a long
1846 * time. We can help with the dwc2 parts of this, but it's hard to
1847 * guarantee that a system will have interrupt latency < 125 us, so
1848 * we have to be robust to some misses.
1850 if (qh
->start_active_frame
== qh
->next_active_frame
||
1851 dwc2_frame_num_gt(prev_frame_number
, qh
->start_active_frame
)) {
1852 u16 ideal_start
= qh
->start_active_frame
;
1856 * Adjust interval as per gcd with map size.
1857 * See pmap_schedule() for more details here.
1859 if (qh
->do_split
|| qh
->dev_speed
== USB_SPEED_HIGH
)
1860 periods_in_map
= DWC2_HS_SCHEDULE_UFRAMES
;
1862 periods_in_map
= DWC2_LS_SCHEDULE_FRAMES
;
1863 interval
= gcd(interval
, periods_in_map
);
1866 qh
->start_active_frame
= dwc2_frame_num_inc(
1867 qh
->start_active_frame
, interval
);
1868 } while (dwc2_frame_num_gt(prev_frame_number
,
1869 qh
->start_active_frame
));
1871 missed
= dwc2_frame_num_dec(qh
->start_active_frame
,
1876 qh
->next_active_frame
= qh
->start_active_frame
;
1882 * Deactivates a QH. For non-periodic QHs, removes the QH from the active
1883 * non-periodic schedule. The QH is added to the inactive non-periodic
1884 * schedule if any QTDs are still attached to the QH.
1886 * For periodic QHs, the QH is removed from the periodic queued schedule. If
1887 * there are any QTDs still attached to the QH, the QH is added to either the
1888 * periodic inactive schedule or the periodic ready schedule and its next
1889 * scheduled frame is calculated. The QH is placed in the ready schedule if
1890 * the scheduled frame has been reached already. Otherwise it's placed in the
1891 * inactive schedule. If there are no QTDs attached to the QH, the QH is
1892 * completely removed from the periodic schedule.
1894 void dwc2_hcd_qh_deactivate(struct dwc2_hsotg
*hsotg
, struct dwc2_qh
*qh
,
1895 int sched_next_periodic_split
)
1897 u16 old_frame
= qh
->next_active_frame
;
1902 dev_vdbg(hsotg
->dev
, "%s()\n", __func__
);
1904 if (dwc2_qh_is_non_per(qh
)) {
1905 dwc2_hcd_qh_unlink(hsotg
, qh
);
1906 if (!list_empty(&qh
->qtd_list
))
1907 /* Add back to inactive non-periodic schedule */
1908 dwc2_hcd_qh_add(hsotg
, qh
);
1913 * Use the real frame number rather than the cached value as of the
1914 * last SOF just to get us a little closer to reality. Note that
1915 * means we don't actually know if we've already handled the SOF
1916 * interrupt for this frame.
1918 frame_number
= dwc2_hcd_get_frame_number(hsotg
);
1920 if (sched_next_periodic_split
)
1921 missed
= dwc2_next_for_periodic_split(hsotg
, qh
, frame_number
);
1923 missed
= dwc2_next_periodic_start(hsotg
, qh
, frame_number
);
1925 dwc2_sch_vdbg(hsotg
,
1926 "QH=%p next(%d) fn=%04x, sch=%04x=>%04x (%+d) miss=%d %s\n",
1927 qh
, sched_next_periodic_split
, frame_number
, old_frame
,
1928 qh
->next_active_frame
,
1929 dwc2_frame_num_dec(qh
->next_active_frame
, old_frame
),
1930 missed
, missed
? "MISS" : "");
1932 if (list_empty(&qh
->qtd_list
)) {
1933 dwc2_hcd_qh_unlink(hsotg
, qh
);
1938 * Remove from periodic_sched_queued and move to
1941 * Note: we purposely use the frame_number from the "hsotg" structure
1942 * since we know SOF interrupt will handle future frames.
1944 if (dwc2_frame_num_le(qh
->next_active_frame
, hsotg
->frame_number
))
1945 list_move_tail(&qh
->qh_list_entry
,
1946 &hsotg
->periodic_sched_ready
);
1948 list_move_tail(&qh
->qh_list_entry
,
1949 &hsotg
->periodic_sched_inactive
);
1953 * dwc2_hcd_qtd_init() - Initializes a QTD structure
1955 * @qtd: The QTD to initialize
1956 * @urb: The associated URB
1958 void dwc2_hcd_qtd_init(struct dwc2_qtd
*qtd
, struct dwc2_hcd_urb
*urb
)
1961 if (dwc2_hcd_get_pipe_type(&urb
->pipe_info
) ==
1962 USB_ENDPOINT_XFER_CONTROL
) {
1964 * The only time the QTD data toggle is used is on the data
1965 * phase of control transfers. This phase always starts with
1968 qtd
->data_toggle
= DWC2_HC_PID_DATA1
;
1969 qtd
->control_phase
= DWC2_CONTROL_SETUP
;
1973 qtd
->complete_split
= 0;
1974 qtd
->isoc_split_pos
= DWC2_HCSPLT_XACTPOS_ALL
;
1975 qtd
->isoc_split_offset
= 0;
1976 qtd
->in_process
= 0;
1978 /* Store the qtd ptr in the urb to reference the QTD */
1983 * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH
1984 * Caller must hold driver lock.
1986 * @hsotg: The DWC HCD structure
1987 * @qtd: The QTD to add
1988 * @qh: Queue head to add qtd to
1990 * Return: 0 if successful, negative error code otherwise
1992 * If the QH to which the QTD is added is not currently scheduled, it is placed
1993 * into the proper schedule based on its EP type.
1995 int dwc2_hcd_qtd_add(struct dwc2_hsotg
*hsotg
, struct dwc2_qtd
*qtd
,
2000 if (unlikely(!qh
)) {
2001 dev_err(hsotg
->dev
, "%s: Invalid QH\n", __func__
);
2006 retval
= dwc2_hcd_qh_add(hsotg
, qh
);
2011 list_add_tail(&qtd
->qtd_list_entry
, &qh
->qtd_list
);