2 * core.c - DesignWare USB3 DRD Controller Core file
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <linux/version.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
36 #include <linux/acpi.h>
38 #include <linux/usb/ch9.h>
39 #include <linux/usb/gadget.h>
40 #include <linux/usb/of.h>
41 #include <linux/usb/otg.h>
43 #include "platform_data.h"
50 /* -------------------------------------------------------------------------- */
52 void dwc3_set_mode(struct dwc3
*dwc
, u32 mode
)
56 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
57 reg
&= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG
));
58 reg
|= DWC3_GCTL_PRTCAPDIR(mode
);
59 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
63 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
64 * @dwc: pointer to our context structure
66 static int dwc3_core_soft_reset(struct dwc3
*dwc
)
71 /* Before Resetting PHY, put Core in Reset */
72 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
73 reg
|= DWC3_GCTL_CORESOFTRESET
;
74 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
76 /* Assert USB3 PHY reset */
77 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB3PIPECTL(0));
78 reg
|= DWC3_GUSB3PIPECTL_PHYSOFTRST
;
79 dwc3_writel(dwc
->regs
, DWC3_GUSB3PIPECTL(0), reg
);
81 /* Assert USB2 PHY reset */
82 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
83 reg
|= DWC3_GUSB2PHYCFG_PHYSOFTRST
;
84 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
86 usb_phy_init(dwc
->usb2_phy
);
87 usb_phy_init(dwc
->usb3_phy
);
88 ret
= phy_init(dwc
->usb2_generic_phy
);
92 ret
= phy_init(dwc
->usb3_generic_phy
);
94 phy_exit(dwc
->usb2_generic_phy
);
99 /* Clear USB3 PHY reset */
100 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB3PIPECTL(0));
101 reg
&= ~DWC3_GUSB3PIPECTL_PHYSOFTRST
;
102 dwc3_writel(dwc
->regs
, DWC3_GUSB3PIPECTL(0), reg
);
104 /* Clear USB2 PHY reset */
105 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
106 reg
&= ~DWC3_GUSB2PHYCFG_PHYSOFTRST
;
107 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
111 /* After PHYs are stable we can take Core out of reset state */
112 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
113 reg
&= ~DWC3_GCTL_CORESOFTRESET
;
114 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
120 * dwc3_free_one_event_buffer - Frees one event buffer
121 * @dwc: Pointer to our controller context structure
122 * @evt: Pointer to event buffer to be freed
124 static void dwc3_free_one_event_buffer(struct dwc3
*dwc
,
125 struct dwc3_event_buffer
*evt
)
127 dma_free_coherent(dwc
->dev
, evt
->length
, evt
->buf
, evt
->dma
);
131 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
132 * @dwc: Pointer to our controller context structure
133 * @length: size of the event buffer
135 * Returns a pointer to the allocated event buffer structure on success
136 * otherwise ERR_PTR(errno).
138 static struct dwc3_event_buffer
*dwc3_alloc_one_event_buffer(struct dwc3
*dwc
,
141 struct dwc3_event_buffer
*evt
;
143 evt
= devm_kzalloc(dwc
->dev
, sizeof(*evt
), GFP_KERNEL
);
145 return ERR_PTR(-ENOMEM
);
148 evt
->length
= length
;
149 evt
->buf
= dma_alloc_coherent(dwc
->dev
, length
,
150 &evt
->dma
, GFP_KERNEL
);
152 return ERR_PTR(-ENOMEM
);
158 * dwc3_free_event_buffers - frees all allocated event buffers
159 * @dwc: Pointer to our controller context structure
161 static void dwc3_free_event_buffers(struct dwc3
*dwc
)
163 struct dwc3_event_buffer
*evt
;
166 for (i
= 0; i
< dwc
->num_event_buffers
; i
++) {
167 evt
= dwc
->ev_buffs
[i
];
169 dwc3_free_one_event_buffer(dwc
, evt
);
174 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
175 * @dwc: pointer to our controller context structure
176 * @length: size of event buffer
178 * Returns 0 on success otherwise negative errno. In the error case, dwc
179 * may contain some buffers allocated but not all which were requested.
181 static int dwc3_alloc_event_buffers(struct dwc3
*dwc
, unsigned length
)
186 num
= DWC3_NUM_INT(dwc
->hwparams
.hwparams1
);
187 dwc
->num_event_buffers
= num
;
189 dwc
->ev_buffs
= devm_kzalloc(dwc
->dev
, sizeof(*dwc
->ev_buffs
) * num
,
194 for (i
= 0; i
< num
; i
++) {
195 struct dwc3_event_buffer
*evt
;
197 evt
= dwc3_alloc_one_event_buffer(dwc
, length
);
199 dev_err(dwc
->dev
, "can't allocate event buffer\n");
202 dwc
->ev_buffs
[i
] = evt
;
209 * dwc3_event_buffers_setup - setup our allocated event buffers
210 * @dwc: pointer to our controller context structure
212 * Returns 0 on success otherwise negative errno.
214 static int dwc3_event_buffers_setup(struct dwc3
*dwc
)
216 struct dwc3_event_buffer
*evt
;
219 for (n
= 0; n
< dwc
->num_event_buffers
; n
++) {
220 evt
= dwc
->ev_buffs
[n
];
221 dev_dbg(dwc
->dev
, "Event buf %p dma %08llx length %d\n",
222 evt
->buf
, (unsigned long long) evt
->dma
,
227 dwc3_writel(dwc
->regs
, DWC3_GEVNTADRLO(n
),
228 lower_32_bits(evt
->dma
));
229 dwc3_writel(dwc
->regs
, DWC3_GEVNTADRHI(n
),
230 upper_32_bits(evt
->dma
));
231 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(n
),
232 DWC3_GEVNTSIZ_SIZE(evt
->length
));
233 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(n
), 0);
239 static void dwc3_event_buffers_cleanup(struct dwc3
*dwc
)
241 struct dwc3_event_buffer
*evt
;
244 for (n
= 0; n
< dwc
->num_event_buffers
; n
++) {
245 evt
= dwc
->ev_buffs
[n
];
249 dwc3_writel(dwc
->regs
, DWC3_GEVNTADRLO(n
), 0);
250 dwc3_writel(dwc
->regs
, DWC3_GEVNTADRHI(n
), 0);
251 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(n
), DWC3_GEVNTSIZ_INTMASK
252 | DWC3_GEVNTSIZ_SIZE(0));
253 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(n
), 0);
257 static int dwc3_alloc_scratch_buffers(struct dwc3
*dwc
)
259 if (!dwc
->has_hibernation
)
262 if (!dwc
->nr_scratch
)
265 dwc
->scratchbuf
= kmalloc_array(dwc
->nr_scratch
,
266 DWC3_SCRATCHBUF_SIZE
, GFP_KERNEL
);
267 if (!dwc
->scratchbuf
)
273 static int dwc3_setup_scratch_buffers(struct dwc3
*dwc
)
275 dma_addr_t scratch_addr
;
279 if (!dwc
->has_hibernation
)
282 if (!dwc
->nr_scratch
)
285 /* should never fall here */
286 if (!WARN_ON(dwc
->scratchbuf
))
289 scratch_addr
= dma_map_single(dwc
->dev
, dwc
->scratchbuf
,
290 dwc
->nr_scratch
* DWC3_SCRATCHBUF_SIZE
,
292 if (dma_mapping_error(dwc
->dev
, scratch_addr
)) {
293 dev_err(dwc
->dev
, "failed to map scratch buffer\n");
298 dwc
->scratch_addr
= scratch_addr
;
300 param
= lower_32_bits(scratch_addr
);
302 ret
= dwc3_send_gadget_generic_command(dwc
,
303 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO
, param
);
307 param
= upper_32_bits(scratch_addr
);
309 ret
= dwc3_send_gadget_generic_command(dwc
,
310 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI
, param
);
317 dma_unmap_single(dwc
->dev
, dwc
->scratch_addr
, dwc
->nr_scratch
*
318 DWC3_SCRATCHBUF_SIZE
, DMA_BIDIRECTIONAL
);
324 static void dwc3_free_scratch_buffers(struct dwc3
*dwc
)
326 if (!dwc
->has_hibernation
)
329 if (!dwc
->nr_scratch
)
332 /* should never fall here */
333 if (!WARN_ON(dwc
->scratchbuf
))
336 dma_unmap_single(dwc
->dev
, dwc
->scratch_addr
, dwc
->nr_scratch
*
337 DWC3_SCRATCHBUF_SIZE
, DMA_BIDIRECTIONAL
);
338 kfree(dwc
->scratchbuf
);
341 static void dwc3_core_num_eps(struct dwc3
*dwc
)
343 struct dwc3_hwparams
*parms
= &dwc
->hwparams
;
345 dwc
->num_in_eps
= DWC3_NUM_IN_EPS(parms
);
346 dwc
->num_out_eps
= DWC3_NUM_EPS(parms
) - dwc
->num_in_eps
;
348 dev_vdbg(dwc
->dev
, "found %d IN and %d OUT endpoints\n",
349 dwc
->num_in_eps
, dwc
->num_out_eps
);
352 static void dwc3_cache_hwparams(struct dwc3
*dwc
)
354 struct dwc3_hwparams
*parms
= &dwc
->hwparams
;
356 parms
->hwparams0
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS0
);
357 parms
->hwparams1
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS1
);
358 parms
->hwparams2
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS2
);
359 parms
->hwparams3
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS3
);
360 parms
->hwparams4
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS4
);
361 parms
->hwparams5
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS5
);
362 parms
->hwparams6
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS6
);
363 parms
->hwparams7
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS7
);
364 parms
->hwparams8
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS8
);
368 * dwc3_core_init - Low-level initialization of DWC3 Core
369 * @dwc: Pointer to our controller context structure
371 * Returns 0 on success otherwise negative errno.
373 static int dwc3_core_init(struct dwc3
*dwc
)
375 unsigned long timeout
;
376 u32 hwparams4
= dwc
->hwparams
.hwparams4
;
380 reg
= dwc3_readl(dwc
->regs
, DWC3_GSNPSID
);
381 /* This should read as U3 followed by revision number */
382 if ((reg
& DWC3_GSNPSID_MASK
) != 0x55330000) {
383 dev_err(dwc
->dev
, "this is not a DesignWare USB3 DRD Core\n");
390 * Write Linux Version Code to our GUID register so it's easy to figure
391 * out which kernel version a bug was found.
393 dwc3_writel(dwc
->regs
, DWC3_GUID
, LINUX_VERSION_CODE
);
395 /* Handle USB2.0-only core configuration */
396 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc
->hwparams
.hwparams3
) ==
397 DWC3_GHWPARAMS3_SSPHY_IFC_DIS
) {
398 if (dwc
->maximum_speed
== USB_SPEED_SUPER
)
399 dwc
->maximum_speed
= USB_SPEED_HIGH
;
402 /* issue device SoftReset too */
403 timeout
= jiffies
+ msecs_to_jiffies(500);
404 dwc3_writel(dwc
->regs
, DWC3_DCTL
, DWC3_DCTL_CSFTRST
);
406 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
407 if (!(reg
& DWC3_DCTL_CSFTRST
))
410 if (time_after(jiffies
, timeout
)) {
411 dev_err(dwc
->dev
, "Reset Timed Out\n");
419 ret
= dwc3_core_soft_reset(dwc
);
423 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
424 reg
&= ~DWC3_GCTL_SCALEDOWN_MASK
;
425 reg
&= ~DWC3_GCTL_DISSCRAMBLE
;
427 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc
->hwparams
.hwparams1
)) {
428 case DWC3_GHWPARAMS1_EN_PWROPT_CLK
:
430 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
431 * issue which would cause xHCI compliance tests to fail.
433 * Because of that we cannot enable clock gating on such
438 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
441 if ((dwc
->dr_mode
== USB_DR_MODE_HOST
||
442 dwc
->dr_mode
== USB_DR_MODE_OTG
) &&
443 (dwc
->revision
>= DWC3_REVISION_210A
&&
444 dwc
->revision
<= DWC3_REVISION_250A
))
445 reg
|= DWC3_GCTL_DSBLCLKGTNG
| DWC3_GCTL_SOFITPSYNC
;
447 reg
&= ~DWC3_GCTL_DSBLCLKGTNG
;
449 case DWC3_GHWPARAMS1_EN_PWROPT_HIB
:
450 /* enable hibernation here */
451 dwc
->nr_scratch
= DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4
);
454 * REVISIT Enabling this bit so that host-mode hibernation
455 * will work. Device-mode hibernation is not yet implemented.
457 reg
|= DWC3_GCTL_GBLHIBERNATIONEN
;
460 dev_dbg(dwc
->dev
, "No power optimization available\n");
464 * WORKAROUND: DWC3 revisions <1.90a have a bug
465 * where the device can fail to connect at SuperSpeed
466 * and falls back to high-speed mode which causes
467 * the device to enter a Connect/Disconnect loop
469 if (dwc
->revision
< DWC3_REVISION_190A
)
470 reg
|= DWC3_GCTL_U2RSTECN
;
472 dwc3_core_num_eps(dwc
);
474 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
476 ret
= dwc3_alloc_scratch_buffers(dwc
);
480 ret
= dwc3_setup_scratch_buffers(dwc
);
487 dwc3_free_scratch_buffers(dwc
);
490 usb_phy_shutdown(dwc
->usb2_phy
);
491 usb_phy_shutdown(dwc
->usb3_phy
);
492 phy_exit(dwc
->usb2_generic_phy
);
493 phy_exit(dwc
->usb3_generic_phy
);
499 static void dwc3_core_exit(struct dwc3
*dwc
)
501 dwc3_free_scratch_buffers(dwc
);
502 usb_phy_shutdown(dwc
->usb2_phy
);
503 usb_phy_shutdown(dwc
->usb3_phy
);
504 phy_exit(dwc
->usb2_generic_phy
);
505 phy_exit(dwc
->usb3_generic_phy
);
508 static int dwc3_core_get_phy(struct dwc3
*dwc
)
510 struct device
*dev
= dwc
->dev
;
511 struct device_node
*node
= dev
->of_node
;
515 dwc
->usb2_phy
= devm_usb_get_phy_by_phandle(dev
, "usb-phy", 0);
516 dwc
->usb3_phy
= devm_usb_get_phy_by_phandle(dev
, "usb-phy", 1);
518 dwc
->usb2_phy
= devm_usb_get_phy(dev
, USB_PHY_TYPE_USB2
);
519 dwc
->usb3_phy
= devm_usb_get_phy(dev
, USB_PHY_TYPE_USB3
);
522 if (IS_ERR(dwc
->usb2_phy
)) {
523 ret
= PTR_ERR(dwc
->usb2_phy
);
524 if (ret
== -ENXIO
|| ret
== -ENODEV
) {
525 dwc
->usb2_phy
= NULL
;
526 } else if (ret
== -EPROBE_DEFER
) {
529 dev_err(dev
, "no usb2 phy configured\n");
534 if (IS_ERR(dwc
->usb3_phy
)) {
535 ret
= PTR_ERR(dwc
->usb3_phy
);
536 if (ret
== -ENXIO
|| ret
== -ENODEV
) {
537 dwc
->usb3_phy
= NULL
;
538 } else if (ret
== -EPROBE_DEFER
) {
541 dev_err(dev
, "no usb3 phy configured\n");
546 dwc
->usb2_generic_phy
= devm_phy_get(dev
, "usb2-phy");
547 if (IS_ERR(dwc
->usb2_generic_phy
)) {
548 ret
= PTR_ERR(dwc
->usb2_generic_phy
);
549 if (ret
== -ENOSYS
|| ret
== -ENODEV
) {
550 dwc
->usb2_generic_phy
= NULL
;
551 } else if (ret
== -EPROBE_DEFER
) {
554 dev_err(dev
, "no usb2 phy configured\n");
559 dwc
->usb3_generic_phy
= devm_phy_get(dev
, "usb3-phy");
560 if (IS_ERR(dwc
->usb3_generic_phy
)) {
561 ret
= PTR_ERR(dwc
->usb3_generic_phy
);
562 if (ret
== -ENOSYS
|| ret
== -ENODEV
) {
563 dwc
->usb3_generic_phy
= NULL
;
564 } else if (ret
== -EPROBE_DEFER
) {
567 dev_err(dev
, "no usb3 phy configured\n");
575 static int dwc3_core_init_mode(struct dwc3
*dwc
)
577 struct device
*dev
= dwc
->dev
;
580 switch (dwc
->dr_mode
) {
581 case USB_DR_MODE_PERIPHERAL
:
582 dwc3_set_mode(dwc
, DWC3_GCTL_PRTCAP_DEVICE
);
583 ret
= dwc3_gadget_init(dwc
);
585 dev_err(dev
, "failed to initialize gadget\n");
589 case USB_DR_MODE_HOST
:
590 dwc3_set_mode(dwc
, DWC3_GCTL_PRTCAP_HOST
);
591 ret
= dwc3_host_init(dwc
);
593 dev_err(dev
, "failed to initialize host\n");
597 case USB_DR_MODE_OTG
:
598 dwc3_set_mode(dwc
, DWC3_GCTL_PRTCAP_OTG
);
599 ret
= dwc3_host_init(dwc
);
601 dev_err(dev
, "failed to initialize host\n");
605 ret
= dwc3_gadget_init(dwc
);
607 dev_err(dev
, "failed to initialize gadget\n");
612 dev_err(dev
, "Unsupported mode of operation %d\n", dwc
->dr_mode
);
619 static void dwc3_core_exit_mode(struct dwc3
*dwc
)
621 switch (dwc
->dr_mode
) {
622 case USB_DR_MODE_PERIPHERAL
:
623 dwc3_gadget_exit(dwc
);
625 case USB_DR_MODE_HOST
:
628 case USB_DR_MODE_OTG
:
630 dwc3_gadget_exit(dwc
);
638 #define DWC3_ALIGN_MASK (16 - 1)
640 static int dwc3_probe(struct platform_device
*pdev
)
642 struct device
*dev
= &pdev
->dev
;
643 struct dwc3_platform_data
*pdata
= dev_get_platdata(dev
);
644 struct device_node
*node
= dev
->of_node
;
645 struct resource
*res
;
653 mem
= devm_kzalloc(dev
, sizeof(*dwc
) + DWC3_ALIGN_MASK
, GFP_KERNEL
);
657 dwc
= PTR_ALIGN(mem
, DWC3_ALIGN_MASK
+ 1);
661 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
663 dev_err(dev
, "missing IRQ\n");
666 dwc
->xhci_resources
[1].start
= res
->start
;
667 dwc
->xhci_resources
[1].end
= res
->end
;
668 dwc
->xhci_resources
[1].flags
= res
->flags
;
669 dwc
->xhci_resources
[1].name
= res
->name
;
671 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
673 dev_err(dev
, "missing memory resource\n");
677 dwc
->xhci_resources
[0].start
= res
->start
;
678 dwc
->xhci_resources
[0].end
= dwc
->xhci_resources
[0].start
+
680 dwc
->xhci_resources
[0].flags
= res
->flags
;
681 dwc
->xhci_resources
[0].name
= res
->name
;
683 res
->start
+= DWC3_GLOBALS_REGS_START
;
686 * Request memory region but exclude xHCI regs,
687 * since it will be requested by the xhci-plat driver.
689 regs
= devm_ioremap_resource(dev
, res
);
691 return PTR_ERR(regs
);
694 dwc
->regs_size
= resource_size(res
);
696 * restore res->start back to its original value so that,
697 * in case the probe is deferred, we don't end up getting error in
698 * request the memory region the next time probe is called.
700 res
->start
-= DWC3_GLOBALS_REGS_START
;
703 dwc
->maximum_speed
= of_usb_get_maximum_speed(node
);
705 dwc
->needs_fifo_resize
= of_property_read_bool(node
, "tx-fifo-resize");
706 dwc
->dr_mode
= of_usb_get_dr_mode(node
);
708 dwc
->maximum_speed
= pdata
->maximum_speed
;
710 dwc
->needs_fifo_resize
= pdata
->tx_fifo_resize
;
711 dwc
->dr_mode
= pdata
->dr_mode
;
714 /* default to superspeed if no maximum_speed passed */
715 if (dwc
->maximum_speed
== USB_SPEED_UNKNOWN
)
716 dwc
->maximum_speed
= USB_SPEED_SUPER
;
718 ret
= dwc3_core_get_phy(dwc
);
722 spin_lock_init(&dwc
->lock
);
723 platform_set_drvdata(pdev
, dwc
);
725 if (!dev
->dma_mask
) {
726 dev
->dma_mask
= dev
->parent
->dma_mask
;
727 dev
->dma_parms
= dev
->parent
->dma_parms
;
728 dma_set_coherent_mask(dev
, dev
->parent
->coherent_dma_mask
);
731 pm_runtime_enable(dev
);
732 pm_runtime_get_sync(dev
);
733 pm_runtime_forbid(dev
);
735 dwc3_cache_hwparams(dwc
);
737 ret
= dwc3_alloc_event_buffers(dwc
, DWC3_EVENT_BUFFERS_SIZE
);
739 dev_err(dwc
->dev
, "failed to allocate event buffers\n");
744 if (IS_ENABLED(CONFIG_USB_DWC3_HOST
))
745 dwc
->dr_mode
= USB_DR_MODE_HOST
;
746 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET
))
747 dwc
->dr_mode
= USB_DR_MODE_PERIPHERAL
;
749 if (dwc
->dr_mode
== USB_DR_MODE_UNKNOWN
)
750 dwc
->dr_mode
= USB_DR_MODE_OTG
;
752 ret
= dwc3_core_init(dwc
);
754 dev_err(dev
, "failed to initialize core\n");
758 usb_phy_set_suspend(dwc
->usb2_phy
, 0);
759 usb_phy_set_suspend(dwc
->usb3_phy
, 0);
760 ret
= phy_power_on(dwc
->usb2_generic_phy
);
764 ret
= phy_power_on(dwc
->usb3_generic_phy
);
766 goto err_usb2phy_power
;
768 ret
= dwc3_event_buffers_setup(dwc
);
770 dev_err(dwc
->dev
, "failed to setup event buffers\n");
771 goto err_usb3phy_power
;
774 ret
= dwc3_core_init_mode(dwc
);
778 ret
= dwc3_debugfs_init(dwc
);
780 dev_err(dev
, "failed to initialize debugfs\n");
784 pm_runtime_allow(dev
);
789 dwc3_core_exit_mode(dwc
);
792 dwc3_event_buffers_cleanup(dwc
);
795 phy_power_off(dwc
->usb3_generic_phy
);
798 phy_power_off(dwc
->usb2_generic_phy
);
801 usb_phy_set_suspend(dwc
->usb2_phy
, 1);
802 usb_phy_set_suspend(dwc
->usb3_phy
, 1);
806 dwc3_free_event_buffers(dwc
);
811 static int dwc3_remove(struct platform_device
*pdev
)
813 struct dwc3
*dwc
= platform_get_drvdata(pdev
);
815 dwc3_debugfs_exit(dwc
);
816 dwc3_core_exit_mode(dwc
);
817 dwc3_event_buffers_cleanup(dwc
);
818 dwc3_free_event_buffers(dwc
);
820 usb_phy_set_suspend(dwc
->usb2_phy
, 1);
821 usb_phy_set_suspend(dwc
->usb3_phy
, 1);
822 phy_power_off(dwc
->usb2_generic_phy
);
823 phy_power_off(dwc
->usb3_generic_phy
);
827 pm_runtime_put_sync(&pdev
->dev
);
828 pm_runtime_disable(&pdev
->dev
);
833 #ifdef CONFIG_PM_SLEEP
834 static int dwc3_suspend(struct device
*dev
)
836 struct dwc3
*dwc
= dev_get_drvdata(dev
);
839 spin_lock_irqsave(&dwc
->lock
, flags
);
841 switch (dwc
->dr_mode
) {
842 case USB_DR_MODE_PERIPHERAL
:
843 case USB_DR_MODE_OTG
:
844 dwc3_gadget_suspend(dwc
);
846 case USB_DR_MODE_HOST
:
848 dwc3_event_buffers_cleanup(dwc
);
852 dwc
->gctl
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
853 spin_unlock_irqrestore(&dwc
->lock
, flags
);
855 usb_phy_shutdown(dwc
->usb3_phy
);
856 usb_phy_shutdown(dwc
->usb2_phy
);
857 phy_exit(dwc
->usb2_generic_phy
);
858 phy_exit(dwc
->usb3_generic_phy
);
863 static int dwc3_resume(struct device
*dev
)
865 struct dwc3
*dwc
= dev_get_drvdata(dev
);
869 usb_phy_init(dwc
->usb3_phy
);
870 usb_phy_init(dwc
->usb2_phy
);
871 ret
= phy_init(dwc
->usb2_generic_phy
);
875 ret
= phy_init(dwc
->usb3_generic_phy
);
877 goto err_usb2phy_init
;
879 spin_lock_irqsave(&dwc
->lock
, flags
);
881 dwc3_event_buffers_setup(dwc
);
882 dwc3_writel(dwc
->regs
, DWC3_GCTL
, dwc
->gctl
);
884 switch (dwc
->dr_mode
) {
885 case USB_DR_MODE_PERIPHERAL
:
886 case USB_DR_MODE_OTG
:
887 dwc3_gadget_resume(dwc
);
889 case USB_DR_MODE_HOST
:
895 spin_unlock_irqrestore(&dwc
->lock
, flags
);
897 pm_runtime_disable(dev
);
898 pm_runtime_set_active(dev
);
899 pm_runtime_enable(dev
);
904 phy_exit(dwc
->usb2_generic_phy
);
909 static const struct dev_pm_ops dwc3_dev_pm_ops
= {
910 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend
, dwc3_resume
)
913 #define DWC3_PM_OPS &(dwc3_dev_pm_ops)
915 #define DWC3_PM_OPS NULL
919 static const struct of_device_id of_dwc3_match
[] = {
921 .compatible
= "snps,dwc3"
924 .compatible
= "synopsys,dwc3"
928 MODULE_DEVICE_TABLE(of
, of_dwc3_match
);
933 #define ACPI_ID_INTEL_BSW "808622B7"
935 static const struct acpi_device_id dwc3_acpi_match
[] = {
936 { ACPI_ID_INTEL_BSW
, 0 },
939 MODULE_DEVICE_TABLE(acpi
, dwc3_acpi_match
);
942 static struct platform_driver dwc3_driver
= {
944 .remove
= dwc3_remove
,
947 .of_match_table
= of_match_ptr(of_dwc3_match
),
948 .acpi_match_table
= ACPI_PTR(dwc3_acpi_match
),
953 module_platform_driver(dwc3_driver
);
955 MODULE_ALIAS("platform:dwc3");
956 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
957 MODULE_LICENSE("GPL v2");
958 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");