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usb: dwc3: Undo PHY init if soft reset fails
[mirror_ubuntu-bionic-kernel.git] / drivers / usb / dwc3 / core.c
1 // SPDX-License-Identifier: GPL-2.0
2 /**
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/version.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/spinlock.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/interrupt.h>
19 #include <linux/ioport.h>
20 #include <linux/io.h>
21 #include <linux/list.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/of.h>
25 #include <linux/acpi.h>
26 #include <linux/pinctrl/consumer.h>
27
28 #include <linux/usb/ch9.h>
29 #include <linux/usb/gadget.h>
30 #include <linux/usb/of.h>
31 #include <linux/usb/otg.h>
32
33 #include "core.h"
34 #include "gadget.h"
35 #include "io.h"
36
37 #include "debug.h"
38
39 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
40
41 /**
42 * dwc3_get_dr_mode - Validates and sets dr_mode
43 * @dwc: pointer to our context structure
44 */
45 static int dwc3_get_dr_mode(struct dwc3 *dwc)
46 {
47 enum usb_dr_mode mode;
48 struct device *dev = dwc->dev;
49 unsigned int hw_mode;
50
51 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
52 dwc->dr_mode = USB_DR_MODE_OTG;
53
54 mode = dwc->dr_mode;
55 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
56
57 switch (hw_mode) {
58 case DWC3_GHWPARAMS0_MODE_GADGET:
59 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
60 dev_err(dev,
61 "Controller does not support host mode.\n");
62 return -EINVAL;
63 }
64 mode = USB_DR_MODE_PERIPHERAL;
65 break;
66 case DWC3_GHWPARAMS0_MODE_HOST:
67 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
68 dev_err(dev,
69 "Controller does not support device mode.\n");
70 return -EINVAL;
71 }
72 mode = USB_DR_MODE_HOST;
73 break;
74 default:
75 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
76 mode = USB_DR_MODE_HOST;
77 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
78 mode = USB_DR_MODE_PERIPHERAL;
79 }
80
81 if (mode != dwc->dr_mode) {
82 dev_warn(dev,
83 "Configuration mismatch. dr_mode forced to %s\n",
84 mode == USB_DR_MODE_HOST ? "host" : "gadget");
85
86 dwc->dr_mode = mode;
87 }
88
89 return 0;
90 }
91
92 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
93 static int dwc3_event_buffers_setup(struct dwc3 *dwc);
94
95 static void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
96 {
97 u32 reg;
98
99 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
100 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
101 reg |= DWC3_GCTL_PRTCAPDIR(mode);
102 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
103
104 dwc->current_dr_role = mode;
105 }
106
107 static void __dwc3_set_mode(struct work_struct *work)
108 {
109 struct dwc3 *dwc = work_to_dwc(work);
110 unsigned long flags;
111 int ret;
112
113 if (!dwc->desired_dr_role)
114 return;
115
116 if (dwc->desired_dr_role == dwc->current_dr_role)
117 return;
118
119 if (dwc->dr_mode != USB_DR_MODE_OTG)
120 return;
121
122 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG)
123 return;
124
125 switch (dwc->current_dr_role) {
126 case DWC3_GCTL_PRTCAP_HOST:
127 dwc3_host_exit(dwc);
128 break;
129 case DWC3_GCTL_PRTCAP_DEVICE:
130 dwc3_gadget_exit(dwc);
131 dwc3_event_buffers_cleanup(dwc);
132 break;
133 default:
134 break;
135 }
136
137 spin_lock_irqsave(&dwc->lock, flags);
138
139 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
140
141 spin_unlock_irqrestore(&dwc->lock, flags);
142
143 switch (dwc->desired_dr_role) {
144 case DWC3_GCTL_PRTCAP_HOST:
145 ret = dwc3_host_init(dwc);
146 if (ret) {
147 dev_err(dwc->dev, "failed to initialize host\n");
148 } else {
149 if (dwc->usb2_phy)
150 otg_set_vbus(dwc->usb2_phy->otg, true);
151 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
152 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
153 }
154 break;
155 case DWC3_GCTL_PRTCAP_DEVICE:
156 dwc3_event_buffers_setup(dwc);
157
158 if (dwc->usb2_phy)
159 otg_set_vbus(dwc->usb2_phy->otg, false);
160 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
161 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
162
163 ret = dwc3_gadget_init(dwc);
164 if (ret)
165 dev_err(dwc->dev, "failed to initialize peripheral\n");
166 break;
167 default:
168 break;
169 }
170 }
171
172 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
173 {
174 unsigned long flags;
175
176 spin_lock_irqsave(&dwc->lock, flags);
177 dwc->desired_dr_role = mode;
178 spin_unlock_irqrestore(&dwc->lock, flags);
179
180 queue_work(system_freezable_wq, &dwc->drd_work);
181 }
182
183 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
184 {
185 struct dwc3 *dwc = dep->dwc;
186 u32 reg;
187
188 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
189 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
190 DWC3_GDBGFIFOSPACE_TYPE(type));
191
192 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
193
194 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
195 }
196
197 /**
198 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
199 * @dwc: pointer to our context structure
200 */
201 static int dwc3_core_soft_reset(struct dwc3 *dwc)
202 {
203 u32 reg;
204 int retries = 1000;
205 int ret;
206
207 usb_phy_init(dwc->usb2_phy);
208 usb_phy_init(dwc->usb3_phy);
209 ret = phy_init(dwc->usb2_generic_phy);
210 if (ret < 0)
211 return ret;
212
213 ret = phy_init(dwc->usb3_generic_phy);
214 if (ret < 0) {
215 phy_exit(dwc->usb2_generic_phy);
216 return ret;
217 }
218
219 /*
220 * We're resetting only the device side because, if we're in host mode,
221 * XHCI driver will reset the host block. If dwc3 was configured for
222 * host-only mode, then we can return early.
223 */
224 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
225 return 0;
226
227 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
228 reg |= DWC3_DCTL_CSFTRST;
229 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
230
231 do {
232 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
233 if (!(reg & DWC3_DCTL_CSFTRST))
234 return 0;
235
236 udelay(1);
237 } while (--retries);
238
239 phy_exit(dwc->usb3_generic_phy);
240 phy_exit(dwc->usb2_generic_phy);
241
242 return -ETIMEDOUT;
243 }
244
245 /*
246 * dwc3_frame_length_adjustment - Adjusts frame length if required
247 * @dwc3: Pointer to our controller context structure
248 */
249 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
250 {
251 u32 reg;
252 u32 dft;
253
254 if (dwc->revision < DWC3_REVISION_250A)
255 return;
256
257 if (dwc->fladj == 0)
258 return;
259
260 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
261 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
262 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
263 "request value same as default, ignoring\n")) {
264 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
265 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
266 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
267 }
268 }
269
270 /**
271 * dwc3_free_one_event_buffer - Frees one event buffer
272 * @dwc: Pointer to our controller context structure
273 * @evt: Pointer to event buffer to be freed
274 */
275 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
276 struct dwc3_event_buffer *evt)
277 {
278 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
279 }
280
281 /**
282 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
283 * @dwc: Pointer to our controller context structure
284 * @length: size of the event buffer
285 *
286 * Returns a pointer to the allocated event buffer structure on success
287 * otherwise ERR_PTR(errno).
288 */
289 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
290 unsigned length)
291 {
292 struct dwc3_event_buffer *evt;
293
294 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
295 if (!evt)
296 return ERR_PTR(-ENOMEM);
297
298 evt->dwc = dwc;
299 evt->length = length;
300 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
301 if (!evt->cache)
302 return ERR_PTR(-ENOMEM);
303
304 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
305 &evt->dma, GFP_KERNEL);
306 if (!evt->buf)
307 return ERR_PTR(-ENOMEM);
308
309 return evt;
310 }
311
312 /**
313 * dwc3_free_event_buffers - frees all allocated event buffers
314 * @dwc: Pointer to our controller context structure
315 */
316 static void dwc3_free_event_buffers(struct dwc3 *dwc)
317 {
318 struct dwc3_event_buffer *evt;
319
320 evt = dwc->ev_buf;
321 if (evt)
322 dwc3_free_one_event_buffer(dwc, evt);
323 }
324
325 /**
326 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
327 * @dwc: pointer to our controller context structure
328 * @length: size of event buffer
329 *
330 * Returns 0 on success otherwise negative errno. In the error case, dwc
331 * may contain some buffers allocated but not all which were requested.
332 */
333 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
334 {
335 struct dwc3_event_buffer *evt;
336
337 evt = dwc3_alloc_one_event_buffer(dwc, length);
338 if (IS_ERR(evt)) {
339 dev_err(dwc->dev, "can't allocate event buffer\n");
340 return PTR_ERR(evt);
341 }
342 dwc->ev_buf = evt;
343
344 return 0;
345 }
346
347 /**
348 * dwc3_event_buffers_setup - setup our allocated event buffers
349 * @dwc: pointer to our controller context structure
350 *
351 * Returns 0 on success otherwise negative errno.
352 */
353 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
354 {
355 struct dwc3_event_buffer *evt;
356
357 evt = dwc->ev_buf;
358 evt->lpos = 0;
359 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
360 lower_32_bits(evt->dma));
361 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
362 upper_32_bits(evt->dma));
363 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
364 DWC3_GEVNTSIZ_SIZE(evt->length));
365 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
366
367 return 0;
368 }
369
370 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
371 {
372 struct dwc3_event_buffer *evt;
373
374 evt = dwc->ev_buf;
375
376 evt->lpos = 0;
377
378 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
379 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
380 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
381 | DWC3_GEVNTSIZ_SIZE(0));
382 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
383 }
384
385 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
386 {
387 if (!dwc->has_hibernation)
388 return 0;
389
390 if (!dwc->nr_scratch)
391 return 0;
392
393 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
394 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
395 if (!dwc->scratchbuf)
396 return -ENOMEM;
397
398 return 0;
399 }
400
401 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
402 {
403 dma_addr_t scratch_addr;
404 u32 param;
405 int ret;
406
407 if (!dwc->has_hibernation)
408 return 0;
409
410 if (!dwc->nr_scratch)
411 return 0;
412
413 /* should never fall here */
414 if (!WARN_ON(dwc->scratchbuf))
415 return 0;
416
417 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
418 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
419 DMA_BIDIRECTIONAL);
420 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
421 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
422 ret = -EFAULT;
423 goto err0;
424 }
425
426 dwc->scratch_addr = scratch_addr;
427
428 param = lower_32_bits(scratch_addr);
429
430 ret = dwc3_send_gadget_generic_command(dwc,
431 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
432 if (ret < 0)
433 goto err1;
434
435 param = upper_32_bits(scratch_addr);
436
437 ret = dwc3_send_gadget_generic_command(dwc,
438 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
439 if (ret < 0)
440 goto err1;
441
442 return 0;
443
444 err1:
445 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
446 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
447
448 err0:
449 return ret;
450 }
451
452 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
453 {
454 if (!dwc->has_hibernation)
455 return;
456
457 if (!dwc->nr_scratch)
458 return;
459
460 /* should never fall here */
461 if (!WARN_ON(dwc->scratchbuf))
462 return;
463
464 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
465 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
466 kfree(dwc->scratchbuf);
467 }
468
469 static void dwc3_core_num_eps(struct dwc3 *dwc)
470 {
471 struct dwc3_hwparams *parms = &dwc->hwparams;
472
473 dwc->num_eps = DWC3_NUM_EPS(parms);
474 }
475
476 static void dwc3_cache_hwparams(struct dwc3 *dwc)
477 {
478 struct dwc3_hwparams *parms = &dwc->hwparams;
479
480 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
481 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
482 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
483 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
484 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
485 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
486 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
487 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
488 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
489 }
490
491 /**
492 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
493 * @dwc: Pointer to our controller context structure
494 *
495 * Returns 0 on success. The USB PHY interfaces are configured but not
496 * initialized. The PHY interfaces and the PHYs get initialized together with
497 * the core in dwc3_core_init.
498 */
499 static int dwc3_phy_setup(struct dwc3 *dwc)
500 {
501 u32 reg;
502 int ret;
503
504 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
505
506 /*
507 * Make sure UX_EXIT_PX is cleared as that causes issues with some
508 * PHYs. Also, this bit is not supposed to be used in normal operation.
509 */
510 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
511
512 /*
513 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
514 * to '0' during coreConsultant configuration. So default value
515 * will be '0' when the core is reset. Application needs to set it
516 * to '1' after the core initialization is completed.
517 */
518 if (dwc->revision > DWC3_REVISION_194A)
519 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
520
521 if (dwc->u2ss_inp3_quirk)
522 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
523
524 if (dwc->dis_rxdet_inp3_quirk)
525 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
526
527 if (dwc->req_p1p2p3_quirk)
528 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
529
530 if (dwc->del_p1p2p3_quirk)
531 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
532
533 if (dwc->del_phy_power_chg_quirk)
534 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
535
536 if (dwc->lfps_filter_quirk)
537 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
538
539 if (dwc->rx_detect_poll_quirk)
540 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
541
542 if (dwc->tx_de_emphasis_quirk)
543 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
544
545 if (dwc->dis_u3_susphy_quirk)
546 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
547
548 if (dwc->dis_del_phy_power_chg_quirk)
549 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
550
551 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
552
553 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
554
555 /* Select the HS PHY interface */
556 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
557 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
558 if (dwc->hsphy_interface &&
559 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
560 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
561 break;
562 } else if (dwc->hsphy_interface &&
563 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
564 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
565 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
566 } else {
567 /* Relying on default value. */
568 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
569 break;
570 }
571 /* FALLTHROUGH */
572 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
573 ret = dwc3_ulpi_init(dwc);
574 if (ret)
575 return ret;
576 /* FALLTHROUGH */
577 default:
578 break;
579 }
580
581 switch (dwc->hsphy_mode) {
582 case USBPHY_INTERFACE_MODE_UTMI:
583 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
584 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
585 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
586 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
587 break;
588 case USBPHY_INTERFACE_MODE_UTMIW:
589 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
590 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
591 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
592 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
593 break;
594 default:
595 break;
596 }
597
598 /*
599 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
600 * '0' during coreConsultant configuration. So default value will
601 * be '0' when the core is reset. Application needs to set it to
602 * '1' after the core initialization is completed.
603 */
604 if (dwc->revision > DWC3_REVISION_194A)
605 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
606
607 if (dwc->dis_u2_susphy_quirk)
608 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
609
610 if (dwc->dis_enblslpm_quirk)
611 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
612
613 if (dwc->dis_u2_freeclk_exists_quirk)
614 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
615
616 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
617
618 return 0;
619 }
620
621 static void dwc3_core_exit(struct dwc3 *dwc)
622 {
623 dwc3_event_buffers_cleanup(dwc);
624
625 usb_phy_shutdown(dwc->usb2_phy);
626 usb_phy_shutdown(dwc->usb3_phy);
627 phy_exit(dwc->usb2_generic_phy);
628 phy_exit(dwc->usb3_generic_phy);
629
630 usb_phy_set_suspend(dwc->usb2_phy, 1);
631 usb_phy_set_suspend(dwc->usb3_phy, 1);
632 phy_power_off(dwc->usb2_generic_phy);
633 phy_power_off(dwc->usb3_generic_phy);
634 }
635
636 static bool dwc3_core_is_valid(struct dwc3 *dwc)
637 {
638 u32 reg;
639
640 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
641
642 /* This should read as U3 followed by revision number */
643 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
644 /* Detected DWC_usb3 IP */
645 dwc->revision = reg;
646 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
647 /* Detected DWC_usb31 IP */
648 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
649 dwc->revision |= DWC3_REVISION_IS_DWC31;
650 } else {
651 return false;
652 }
653
654 return true;
655 }
656
657 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
658 {
659 u32 hwparams4 = dwc->hwparams.hwparams4;
660 u32 reg;
661
662 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
663 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
664
665 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
666 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
667 /**
668 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
669 * issue which would cause xHCI compliance tests to fail.
670 *
671 * Because of that we cannot enable clock gating on such
672 * configurations.
673 *
674 * Refers to:
675 *
676 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
677 * SOF/ITP Mode Used
678 */
679 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
680 dwc->dr_mode == USB_DR_MODE_OTG) &&
681 (dwc->revision >= DWC3_REVISION_210A &&
682 dwc->revision <= DWC3_REVISION_250A))
683 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
684 else
685 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
686 break;
687 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
688 /* enable hibernation here */
689 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
690
691 /*
692 * REVISIT Enabling this bit so that host-mode hibernation
693 * will work. Device-mode hibernation is not yet implemented.
694 */
695 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
696 break;
697 default:
698 /* nothing */
699 break;
700 }
701
702 /* check if current dwc3 is on simulation board */
703 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
704 dev_info(dwc->dev, "Running with FPGA optmizations\n");
705 dwc->is_fpga = true;
706 }
707
708 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
709 "disable_scramble cannot be used on non-FPGA builds\n");
710
711 if (dwc->disable_scramble_quirk && dwc->is_fpga)
712 reg |= DWC3_GCTL_DISSCRAMBLE;
713 else
714 reg &= ~DWC3_GCTL_DISSCRAMBLE;
715
716 if (dwc->u2exit_lfps_quirk)
717 reg |= DWC3_GCTL_U2EXIT_LFPS;
718
719 /*
720 * WORKAROUND: DWC3 revisions <1.90a have a bug
721 * where the device can fail to connect at SuperSpeed
722 * and falls back to high-speed mode which causes
723 * the device to enter a Connect/Disconnect loop
724 */
725 if (dwc->revision < DWC3_REVISION_190A)
726 reg |= DWC3_GCTL_U2RSTECN;
727
728 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
729 }
730
731 static int dwc3_core_get_phy(struct dwc3 *dwc);
732
733 /**
734 * dwc3_core_init - Low-level initialization of DWC3 Core
735 * @dwc: Pointer to our controller context structure
736 *
737 * Returns 0 on success otherwise negative errno.
738 */
739 static int dwc3_core_init(struct dwc3 *dwc)
740 {
741 u32 reg;
742 int ret;
743
744 if (!dwc3_core_is_valid(dwc)) {
745 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
746 ret = -ENODEV;
747 goto err0;
748 }
749
750 /*
751 * Write Linux Version Code to our GUID register so it's easy to figure
752 * out which kernel version a bug was found.
753 */
754 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
755
756 /* Handle USB2.0-only core configuration */
757 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
758 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
759 if (dwc->maximum_speed == USB_SPEED_SUPER)
760 dwc->maximum_speed = USB_SPEED_HIGH;
761 }
762
763 ret = dwc3_core_get_phy(dwc);
764 if (ret)
765 goto err0;
766
767 ret = dwc3_core_soft_reset(dwc);
768 if (ret)
769 goto err0;
770
771 ret = dwc3_phy_setup(dwc);
772 if (ret)
773 goto err0;
774
775 dwc3_core_setup_global_control(dwc);
776 dwc3_core_num_eps(dwc);
777
778 ret = dwc3_setup_scratch_buffers(dwc);
779 if (ret)
780 goto err1;
781
782 /* Adjust Frame Length */
783 dwc3_frame_length_adjustment(dwc);
784
785 usb_phy_set_suspend(dwc->usb2_phy, 0);
786 usb_phy_set_suspend(dwc->usb3_phy, 0);
787 ret = phy_power_on(dwc->usb2_generic_phy);
788 if (ret < 0)
789 goto err2;
790
791 ret = phy_power_on(dwc->usb3_generic_phy);
792 if (ret < 0)
793 goto err3;
794
795 ret = dwc3_event_buffers_setup(dwc);
796 if (ret) {
797 dev_err(dwc->dev, "failed to setup event buffers\n");
798 goto err4;
799 }
800
801 /*
802 * ENDXFER polling is available on version 3.10a and later of
803 * the DWC_usb3 controller. It is NOT available in the
804 * DWC_usb31 controller.
805 */
806 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
807 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
808 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
809 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
810 }
811
812 if (dwc->revision >= DWC3_REVISION_250A) {
813 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
814
815 /*
816 * Enable hardware control of sending remote wakeup
817 * in HS when the device is in the L1 state.
818 */
819 if (dwc->revision >= DWC3_REVISION_290A)
820 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
821
822 if (dwc->dis_tx_ipgap_linecheck_quirk)
823 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
824
825 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
826 }
827
828 return 0;
829
830 err4:
831 phy_power_off(dwc->usb3_generic_phy);
832
833 err3:
834 phy_power_off(dwc->usb2_generic_phy);
835
836 err2:
837 usb_phy_set_suspend(dwc->usb2_phy, 1);
838 usb_phy_set_suspend(dwc->usb3_phy, 1);
839
840 err1:
841 usb_phy_shutdown(dwc->usb2_phy);
842 usb_phy_shutdown(dwc->usb3_phy);
843 phy_exit(dwc->usb2_generic_phy);
844 phy_exit(dwc->usb3_generic_phy);
845
846 err0:
847 return ret;
848 }
849
850 static int dwc3_core_get_phy(struct dwc3 *dwc)
851 {
852 struct device *dev = dwc->dev;
853 struct device_node *node = dev->of_node;
854 int ret;
855
856 if (node) {
857 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
858 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
859 } else {
860 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
861 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
862 }
863
864 if (IS_ERR(dwc->usb2_phy)) {
865 ret = PTR_ERR(dwc->usb2_phy);
866 if (ret == -ENXIO || ret == -ENODEV) {
867 dwc->usb2_phy = NULL;
868 } else if (ret == -EPROBE_DEFER) {
869 return ret;
870 } else {
871 dev_err(dev, "no usb2 phy configured\n");
872 return ret;
873 }
874 }
875
876 if (IS_ERR(dwc->usb3_phy)) {
877 ret = PTR_ERR(dwc->usb3_phy);
878 if (ret == -ENXIO || ret == -ENODEV) {
879 dwc->usb3_phy = NULL;
880 } else if (ret == -EPROBE_DEFER) {
881 return ret;
882 } else {
883 dev_err(dev, "no usb3 phy configured\n");
884 return ret;
885 }
886 }
887
888 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
889 if (IS_ERR(dwc->usb2_generic_phy)) {
890 ret = PTR_ERR(dwc->usb2_generic_phy);
891 if (ret == -ENOSYS || ret == -ENODEV) {
892 dwc->usb2_generic_phy = NULL;
893 } else if (ret == -EPROBE_DEFER) {
894 return ret;
895 } else {
896 dev_err(dev, "no usb2 phy configured\n");
897 return ret;
898 }
899 }
900
901 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
902 if (IS_ERR(dwc->usb3_generic_phy)) {
903 ret = PTR_ERR(dwc->usb3_generic_phy);
904 if (ret == -ENOSYS || ret == -ENODEV) {
905 dwc->usb3_generic_phy = NULL;
906 } else if (ret == -EPROBE_DEFER) {
907 return ret;
908 } else {
909 dev_err(dev, "no usb3 phy configured\n");
910 return ret;
911 }
912 }
913
914 return 0;
915 }
916
917 static int dwc3_core_init_mode(struct dwc3 *dwc)
918 {
919 struct device *dev = dwc->dev;
920 int ret;
921
922 switch (dwc->dr_mode) {
923 case USB_DR_MODE_PERIPHERAL:
924 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
925
926 if (dwc->usb2_phy)
927 otg_set_vbus(dwc->usb2_phy->otg, false);
928 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
929 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
930
931 ret = dwc3_gadget_init(dwc);
932 if (ret) {
933 if (ret != -EPROBE_DEFER)
934 dev_err(dev, "failed to initialize gadget\n");
935 return ret;
936 }
937 break;
938 case USB_DR_MODE_HOST:
939 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
940
941 if (dwc->usb2_phy)
942 otg_set_vbus(dwc->usb2_phy->otg, true);
943 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
944 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
945
946 ret = dwc3_host_init(dwc);
947 if (ret) {
948 if (ret != -EPROBE_DEFER)
949 dev_err(dev, "failed to initialize host\n");
950 return ret;
951 }
952 break;
953 case USB_DR_MODE_OTG:
954 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
955 ret = dwc3_drd_init(dwc);
956 if (ret) {
957 if (ret != -EPROBE_DEFER)
958 dev_err(dev, "failed to initialize dual-role\n");
959 return ret;
960 }
961 break;
962 default:
963 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
964 return -EINVAL;
965 }
966
967 return 0;
968 }
969
970 static void dwc3_core_exit_mode(struct dwc3 *dwc)
971 {
972 switch (dwc->dr_mode) {
973 case USB_DR_MODE_PERIPHERAL:
974 dwc3_gadget_exit(dwc);
975 break;
976 case USB_DR_MODE_HOST:
977 dwc3_host_exit(dwc);
978 break;
979 case USB_DR_MODE_OTG:
980 dwc3_drd_exit(dwc);
981 break;
982 default:
983 /* do nothing */
984 break;
985 }
986 }
987
988 static void dwc3_get_properties(struct dwc3 *dwc)
989 {
990 struct device *dev = dwc->dev;
991 u8 lpm_nyet_threshold;
992 u8 tx_de_emphasis;
993 u8 hird_threshold;
994
995 /* default to highest possible threshold */
996 lpm_nyet_threshold = 0xff;
997
998 /* default to -3.5dB de-emphasis */
999 tx_de_emphasis = 1;
1000
1001 /*
1002 * default to assert utmi_sleep_n and use maximum allowed HIRD
1003 * threshold value of 0b1100
1004 */
1005 hird_threshold = 12;
1006
1007 dwc->maximum_speed = usb_get_maximum_speed(dev);
1008 dwc->dr_mode = usb_get_dr_mode(dev);
1009 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1010
1011 dwc->sysdev_is_parent = device_property_read_bool(dev,
1012 "linux,sysdev_is_parent");
1013 if (dwc->sysdev_is_parent)
1014 dwc->sysdev = dwc->dev->parent;
1015 else
1016 dwc->sysdev = dwc->dev;
1017
1018 dwc->has_lpm_erratum = device_property_read_bool(dev,
1019 "snps,has-lpm-erratum");
1020 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1021 &lpm_nyet_threshold);
1022 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1023 "snps,is-utmi-l1-suspend");
1024 device_property_read_u8(dev, "snps,hird-threshold",
1025 &hird_threshold);
1026 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1027 "snps,usb3_lpm_capable");
1028
1029 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1030 "snps,disable_scramble_quirk");
1031 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1032 "snps,u2exit_lfps_quirk");
1033 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1034 "snps,u2ss_inp3_quirk");
1035 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1036 "snps,req_p1p2p3_quirk");
1037 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1038 "snps,del_p1p2p3_quirk");
1039 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1040 "snps,del_phy_power_chg_quirk");
1041 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1042 "snps,lfps_filter_quirk");
1043 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1044 "snps,rx_detect_poll_quirk");
1045 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1046 "snps,dis_u3_susphy_quirk");
1047 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1048 "snps,dis_u2_susphy_quirk");
1049 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1050 "snps,dis_enblslpm_quirk");
1051 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1052 "snps,dis_rxdet_inp3_quirk");
1053 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1054 "snps,dis-u2-freeclk-exists-quirk");
1055 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1056 "snps,dis-del-phy-power-chg-quirk");
1057 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1058 "snps,dis-tx-ipgap-linecheck-quirk");
1059
1060 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1061 "snps,tx_de_emphasis_quirk");
1062 device_property_read_u8(dev, "snps,tx_de_emphasis",
1063 &tx_de_emphasis);
1064 device_property_read_string(dev, "snps,hsphy_interface",
1065 &dwc->hsphy_interface);
1066 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1067 &dwc->fladj);
1068
1069 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1070 dwc->tx_de_emphasis = tx_de_emphasis;
1071
1072 dwc->hird_threshold = hird_threshold
1073 | (dwc->is_utmi_l1_suspend << 4);
1074
1075 dwc->imod_interval = 0;
1076 }
1077
1078 /* check whether the core supports IMOD */
1079 bool dwc3_has_imod(struct dwc3 *dwc)
1080 {
1081 return ((dwc3_is_usb3(dwc) &&
1082 dwc->revision >= DWC3_REVISION_300A) ||
1083 (dwc3_is_usb31(dwc) &&
1084 dwc->revision >= DWC3_USB31_REVISION_120A));
1085 }
1086
1087 static void dwc3_check_params(struct dwc3 *dwc)
1088 {
1089 struct device *dev = dwc->dev;
1090
1091 /* Check for proper value of imod_interval */
1092 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1093 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1094 dwc->imod_interval = 0;
1095 }
1096
1097 /*
1098 * Workaround for STAR 9000961433 which affects only version
1099 * 3.00a of the DWC_usb3 core. This prevents the controller
1100 * interrupt from being masked while handling events. IMOD
1101 * allows us to work around this issue. Enable it for the
1102 * affected version.
1103 */
1104 if (!dwc->imod_interval &&
1105 (dwc->revision == DWC3_REVISION_300A))
1106 dwc->imod_interval = 1;
1107
1108 /* Check the maximum_speed parameter */
1109 switch (dwc->maximum_speed) {
1110 case USB_SPEED_LOW:
1111 case USB_SPEED_FULL:
1112 case USB_SPEED_HIGH:
1113 case USB_SPEED_SUPER:
1114 case USB_SPEED_SUPER_PLUS:
1115 break;
1116 default:
1117 dev_err(dev, "invalid maximum_speed parameter %d\n",
1118 dwc->maximum_speed);
1119 /* fall through */
1120 case USB_SPEED_UNKNOWN:
1121 /* default to superspeed */
1122 dwc->maximum_speed = USB_SPEED_SUPER;
1123
1124 /*
1125 * default to superspeed plus if we are capable.
1126 */
1127 if (dwc3_is_usb31(dwc) &&
1128 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1129 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1130 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1131
1132 break;
1133 }
1134 }
1135
1136 static int dwc3_probe(struct platform_device *pdev)
1137 {
1138 struct device *dev = &pdev->dev;
1139 struct resource *res;
1140 struct dwc3 *dwc;
1141
1142 int ret;
1143
1144 void __iomem *regs;
1145
1146 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1147 if (!dwc)
1148 return -ENOMEM;
1149
1150 dwc->dev = dev;
1151
1152 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1153 if (!res) {
1154 dev_err(dev, "missing memory resource\n");
1155 return -ENODEV;
1156 }
1157
1158 dwc->xhci_resources[0].start = res->start;
1159 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1160 DWC3_XHCI_REGS_END;
1161 dwc->xhci_resources[0].flags = res->flags;
1162 dwc->xhci_resources[0].name = res->name;
1163
1164 res->start += DWC3_GLOBALS_REGS_START;
1165
1166 /*
1167 * Request memory region but exclude xHCI regs,
1168 * since it will be requested by the xhci-plat driver.
1169 */
1170 regs = devm_ioremap_resource(dev, res);
1171 if (IS_ERR(regs)) {
1172 ret = PTR_ERR(regs);
1173 goto err0;
1174 }
1175
1176 dwc->regs = regs;
1177 dwc->regs_size = resource_size(res);
1178
1179 dwc3_get_properties(dwc);
1180
1181 platform_set_drvdata(pdev, dwc);
1182 dwc3_cache_hwparams(dwc);
1183
1184 spin_lock_init(&dwc->lock);
1185
1186 pm_runtime_set_active(dev);
1187 pm_runtime_use_autosuspend(dev);
1188 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1189 pm_runtime_enable(dev);
1190 ret = pm_runtime_get_sync(dev);
1191 if (ret < 0)
1192 goto err1;
1193
1194 pm_runtime_forbid(dev);
1195
1196 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1197 if (ret) {
1198 dev_err(dwc->dev, "failed to allocate event buffers\n");
1199 ret = -ENOMEM;
1200 goto err2;
1201 }
1202
1203 ret = dwc3_get_dr_mode(dwc);
1204 if (ret)
1205 goto err3;
1206
1207 ret = dwc3_alloc_scratch_buffers(dwc);
1208 if (ret)
1209 goto err3;
1210
1211 ret = dwc3_core_init(dwc);
1212 if (ret) {
1213 dev_err(dev, "failed to initialize core\n");
1214 goto err4;
1215 }
1216
1217 dwc3_check_params(dwc);
1218
1219 ret = dwc3_core_init_mode(dwc);
1220 if (ret)
1221 goto err5;
1222
1223 dwc3_debugfs_init(dwc);
1224 pm_runtime_put(dev);
1225
1226 return 0;
1227
1228 err5:
1229 dwc3_event_buffers_cleanup(dwc);
1230
1231 err4:
1232 dwc3_free_scratch_buffers(dwc);
1233
1234 err3:
1235 dwc3_free_event_buffers(dwc);
1236 dwc3_ulpi_exit(dwc);
1237
1238 err2:
1239 pm_runtime_allow(&pdev->dev);
1240
1241 err1:
1242 pm_runtime_put_sync(&pdev->dev);
1243 pm_runtime_disable(&pdev->dev);
1244
1245 err0:
1246 /*
1247 * restore res->start back to its original value so that, in case the
1248 * probe is deferred, we don't end up getting error in request the
1249 * memory region the next time probe is called.
1250 */
1251 res->start -= DWC3_GLOBALS_REGS_START;
1252
1253 return ret;
1254 }
1255
1256 static int dwc3_remove(struct platform_device *pdev)
1257 {
1258 struct dwc3 *dwc = platform_get_drvdata(pdev);
1259 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1260
1261 pm_runtime_get_sync(&pdev->dev);
1262 /*
1263 * restore res->start back to its original value so that, in case the
1264 * probe is deferred, we don't end up getting error in request the
1265 * memory region the next time probe is called.
1266 */
1267 res->start -= DWC3_GLOBALS_REGS_START;
1268
1269 dwc3_debugfs_exit(dwc);
1270 dwc3_core_exit_mode(dwc);
1271
1272 dwc3_core_exit(dwc);
1273 dwc3_ulpi_exit(dwc);
1274
1275 pm_runtime_put_sync(&pdev->dev);
1276 pm_runtime_allow(&pdev->dev);
1277 pm_runtime_disable(&pdev->dev);
1278
1279 dwc3_free_event_buffers(dwc);
1280 dwc3_free_scratch_buffers(dwc);
1281
1282 return 0;
1283 }
1284
1285 #ifdef CONFIG_PM
1286 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1287 {
1288 unsigned long flags;
1289
1290 switch (dwc->current_dr_role) {
1291 case DWC3_GCTL_PRTCAP_DEVICE:
1292 spin_lock_irqsave(&dwc->lock, flags);
1293 dwc3_gadget_suspend(dwc);
1294 spin_unlock_irqrestore(&dwc->lock, flags);
1295 dwc3_core_exit(dwc);
1296 break;
1297 case DWC3_GCTL_PRTCAP_HOST:
1298 /* do nothing during host runtime_suspend */
1299 if (!PMSG_IS_AUTO(msg))
1300 dwc3_core_exit(dwc);
1301 break;
1302 default:
1303 /* do nothing */
1304 break;
1305 }
1306
1307 return 0;
1308 }
1309
1310 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1311 {
1312 unsigned long flags;
1313 int ret;
1314
1315 switch (dwc->current_dr_role) {
1316 case DWC3_GCTL_PRTCAP_DEVICE:
1317 ret = dwc3_core_init(dwc);
1318 if (ret)
1319 return ret;
1320
1321 spin_lock_irqsave(&dwc->lock, flags);
1322 dwc3_gadget_resume(dwc);
1323 spin_unlock_irqrestore(&dwc->lock, flags);
1324 break;
1325 case DWC3_GCTL_PRTCAP_HOST:
1326 /* nothing to do on host runtime_resume */
1327 if (!PMSG_IS_AUTO(msg)) {
1328 ret = dwc3_core_init(dwc);
1329 if (ret)
1330 return ret;
1331 }
1332 break;
1333 default:
1334 /* do nothing */
1335 break;
1336 }
1337
1338 return 0;
1339 }
1340
1341 static int dwc3_runtime_checks(struct dwc3 *dwc)
1342 {
1343 switch (dwc->current_dr_role) {
1344 case DWC3_GCTL_PRTCAP_DEVICE:
1345 if (dwc->connected)
1346 return -EBUSY;
1347 break;
1348 case DWC3_GCTL_PRTCAP_HOST:
1349 default:
1350 /* do nothing */
1351 break;
1352 }
1353
1354 return 0;
1355 }
1356
1357 static int dwc3_runtime_suspend(struct device *dev)
1358 {
1359 struct dwc3 *dwc = dev_get_drvdata(dev);
1360 int ret;
1361
1362 if (dwc3_runtime_checks(dwc))
1363 return -EBUSY;
1364
1365 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1366 if (ret)
1367 return ret;
1368
1369 device_init_wakeup(dev, true);
1370
1371 return 0;
1372 }
1373
1374 static int dwc3_runtime_resume(struct device *dev)
1375 {
1376 struct dwc3 *dwc = dev_get_drvdata(dev);
1377 int ret;
1378
1379 device_init_wakeup(dev, false);
1380
1381 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1382 if (ret)
1383 return ret;
1384
1385 switch (dwc->current_dr_role) {
1386 case DWC3_GCTL_PRTCAP_DEVICE:
1387 dwc3_gadget_process_pending_events(dwc);
1388 break;
1389 case DWC3_GCTL_PRTCAP_HOST:
1390 default:
1391 /* do nothing */
1392 break;
1393 }
1394
1395 pm_runtime_mark_last_busy(dev);
1396
1397 return 0;
1398 }
1399
1400 static int dwc3_runtime_idle(struct device *dev)
1401 {
1402 struct dwc3 *dwc = dev_get_drvdata(dev);
1403
1404 switch (dwc->current_dr_role) {
1405 case DWC3_GCTL_PRTCAP_DEVICE:
1406 if (dwc3_runtime_checks(dwc))
1407 return -EBUSY;
1408 break;
1409 case DWC3_GCTL_PRTCAP_HOST:
1410 default:
1411 /* do nothing */
1412 break;
1413 }
1414
1415 pm_runtime_mark_last_busy(dev);
1416 pm_runtime_autosuspend(dev);
1417
1418 return 0;
1419 }
1420 #endif /* CONFIG_PM */
1421
1422 #ifdef CONFIG_PM_SLEEP
1423 static int dwc3_suspend(struct device *dev)
1424 {
1425 struct dwc3 *dwc = dev_get_drvdata(dev);
1426 int ret;
1427
1428 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1429 if (ret)
1430 return ret;
1431
1432 pinctrl_pm_select_sleep_state(dev);
1433
1434 return 0;
1435 }
1436
1437 static int dwc3_resume(struct device *dev)
1438 {
1439 struct dwc3 *dwc = dev_get_drvdata(dev);
1440 int ret;
1441
1442 pinctrl_pm_select_default_state(dev);
1443
1444 ret = dwc3_resume_common(dwc, PMSG_RESUME);
1445 if (ret)
1446 return ret;
1447
1448 pm_runtime_disable(dev);
1449 pm_runtime_set_active(dev);
1450 pm_runtime_enable(dev);
1451
1452 return 0;
1453 }
1454 #endif /* CONFIG_PM_SLEEP */
1455
1456 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1457 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1458 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1459 dwc3_runtime_idle)
1460 };
1461
1462 #ifdef CONFIG_OF
1463 static const struct of_device_id of_dwc3_match[] = {
1464 {
1465 .compatible = "snps,dwc3"
1466 },
1467 {
1468 .compatible = "synopsys,dwc3"
1469 },
1470 { },
1471 };
1472 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1473 #endif
1474
1475 #ifdef CONFIG_ACPI
1476
1477 #define ACPI_ID_INTEL_BSW "808622B7"
1478
1479 static const struct acpi_device_id dwc3_acpi_match[] = {
1480 { ACPI_ID_INTEL_BSW, 0 },
1481 { },
1482 };
1483 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1484 #endif
1485
1486 static struct platform_driver dwc3_driver = {
1487 .probe = dwc3_probe,
1488 .remove = dwc3_remove,
1489 .driver = {
1490 .name = "dwc3",
1491 .of_match_table = of_match_ptr(of_dwc3_match),
1492 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1493 .pm = &dwc3_dev_pm_ops,
1494 },
1495 };
1496
1497 module_platform_driver(dwc3_driver);
1498
1499 MODULE_ALIAS("platform:dwc3");
1500 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1501 MODULE_LICENSE("GPL v2");
1502 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
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