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[mirror_ubuntu-bionic-kernel.git] / drivers / usb / dwc3 / core.c
1 // SPDX-License-Identifier: GPL-2.0
2 /**
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/version.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/spinlock.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/interrupt.h>
19 #include <linux/ioport.h>
20 #include <linux/io.h>
21 #include <linux/list.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/of.h>
25 #include <linux/acpi.h>
26 #include <linux/pinctrl/consumer.h>
27
28 #include <linux/usb/ch9.h>
29 #include <linux/usb/gadget.h>
30 #include <linux/usb/of.h>
31 #include <linux/usb/otg.h>
32
33 #include "core.h"
34 #include "gadget.h"
35 #include "io.h"
36
37 #include "debug.h"
38
39 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
40
41 /**
42 * dwc3_get_dr_mode - Validates and sets dr_mode
43 * @dwc: pointer to our context structure
44 */
45 static int dwc3_get_dr_mode(struct dwc3 *dwc)
46 {
47 enum usb_dr_mode mode;
48 struct device *dev = dwc->dev;
49 unsigned int hw_mode;
50
51 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
52 dwc->dr_mode = USB_DR_MODE_OTG;
53
54 mode = dwc->dr_mode;
55 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
56
57 switch (hw_mode) {
58 case DWC3_GHWPARAMS0_MODE_GADGET:
59 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
60 dev_err(dev,
61 "Controller does not support host mode.\n");
62 return -EINVAL;
63 }
64 mode = USB_DR_MODE_PERIPHERAL;
65 break;
66 case DWC3_GHWPARAMS0_MODE_HOST:
67 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
68 dev_err(dev,
69 "Controller does not support device mode.\n");
70 return -EINVAL;
71 }
72 mode = USB_DR_MODE_HOST;
73 break;
74 default:
75 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
76 mode = USB_DR_MODE_HOST;
77 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
78 mode = USB_DR_MODE_PERIPHERAL;
79 }
80
81 if (mode != dwc->dr_mode) {
82 dev_warn(dev,
83 "Configuration mismatch. dr_mode forced to %s\n",
84 mode == USB_DR_MODE_HOST ? "host" : "gadget");
85
86 dwc->dr_mode = mode;
87 }
88
89 return 0;
90 }
91
92 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
93 static int dwc3_event_buffers_setup(struct dwc3 *dwc);
94
95 static void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
96 {
97 u32 reg;
98
99 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
100 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
101 reg |= DWC3_GCTL_PRTCAPDIR(mode);
102 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
103
104 dwc->current_dr_role = mode;
105 }
106
107 static void __dwc3_set_mode(struct work_struct *work)
108 {
109 struct dwc3 *dwc = work_to_dwc(work);
110 unsigned long flags;
111 int ret;
112
113 if (!dwc->desired_dr_role)
114 return;
115
116 if (dwc->desired_dr_role == dwc->current_dr_role)
117 return;
118
119 if (dwc->dr_mode != USB_DR_MODE_OTG)
120 return;
121
122 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG)
123 return;
124
125 switch (dwc->current_dr_role) {
126 case DWC3_GCTL_PRTCAP_HOST:
127 dwc3_host_exit(dwc);
128 break;
129 case DWC3_GCTL_PRTCAP_DEVICE:
130 dwc3_gadget_exit(dwc);
131 dwc3_event_buffers_cleanup(dwc);
132 break;
133 default:
134 break;
135 }
136
137 spin_lock_irqsave(&dwc->lock, flags);
138
139 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
140
141 spin_unlock_irqrestore(&dwc->lock, flags);
142
143 switch (dwc->desired_dr_role) {
144 case DWC3_GCTL_PRTCAP_HOST:
145 ret = dwc3_host_init(dwc);
146 if (ret) {
147 dev_err(dwc->dev, "failed to initialize host\n");
148 } else {
149 if (dwc->usb2_phy)
150 otg_set_vbus(dwc->usb2_phy->otg, true);
151 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
152 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
153 }
154 break;
155 case DWC3_GCTL_PRTCAP_DEVICE:
156 dwc3_event_buffers_setup(dwc);
157
158 if (dwc->usb2_phy)
159 otg_set_vbus(dwc->usb2_phy->otg, false);
160 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
161 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
162
163 ret = dwc3_gadget_init(dwc);
164 if (ret)
165 dev_err(dwc->dev, "failed to initialize peripheral\n");
166 break;
167 default:
168 break;
169 }
170 }
171
172 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
173 {
174 unsigned long flags;
175
176 spin_lock_irqsave(&dwc->lock, flags);
177 dwc->desired_dr_role = mode;
178 spin_unlock_irqrestore(&dwc->lock, flags);
179
180 queue_work(system_freezable_wq, &dwc->drd_work);
181 }
182
183 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
184 {
185 struct dwc3 *dwc = dep->dwc;
186 u32 reg;
187
188 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
189 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
190 DWC3_GDBGFIFOSPACE_TYPE(type));
191
192 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
193
194 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
195 }
196
197 /**
198 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
199 * @dwc: pointer to our context structure
200 */
201 static int dwc3_core_soft_reset(struct dwc3 *dwc)
202 {
203 u32 reg;
204 int retries = 1000;
205 int ret;
206
207 usb_phy_init(dwc->usb2_phy);
208 usb_phy_init(dwc->usb3_phy);
209 ret = phy_init(dwc->usb2_generic_phy);
210 if (ret < 0)
211 return ret;
212
213 ret = phy_init(dwc->usb3_generic_phy);
214 if (ret < 0) {
215 phy_exit(dwc->usb2_generic_phy);
216 return ret;
217 }
218
219 /*
220 * We're resetting only the device side because, if we're in host mode,
221 * XHCI driver will reset the host block. If dwc3 was configured for
222 * host-only mode, then we can return early.
223 */
224 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
225 return 0;
226
227 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
228 reg |= DWC3_DCTL_CSFTRST;
229 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
230
231 do {
232 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
233 if (!(reg & DWC3_DCTL_CSFTRST))
234 goto done;
235
236 udelay(1);
237 } while (--retries);
238
239 phy_exit(dwc->usb3_generic_phy);
240 phy_exit(dwc->usb2_generic_phy);
241
242 return -ETIMEDOUT;
243
244 done:
245 /*
246 * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
247 * we must wait at least 50ms before accessing the PHY domain
248 * (synchronization delay). DWC_usb31 programming guide section 1.3.2.
249 */
250 if (dwc3_is_usb31(dwc))
251 msleep(50);
252
253 return 0;
254 }
255
256 /*
257 * dwc3_frame_length_adjustment - Adjusts frame length if required
258 * @dwc3: Pointer to our controller context structure
259 */
260 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
261 {
262 u32 reg;
263 u32 dft;
264
265 if (dwc->revision < DWC3_REVISION_250A)
266 return;
267
268 if (dwc->fladj == 0)
269 return;
270
271 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
272 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
273 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
274 "request value same as default, ignoring\n")) {
275 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
276 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
277 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
278 }
279 }
280
281 /**
282 * dwc3_free_one_event_buffer - Frees one event buffer
283 * @dwc: Pointer to our controller context structure
284 * @evt: Pointer to event buffer to be freed
285 */
286 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
287 struct dwc3_event_buffer *evt)
288 {
289 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
290 }
291
292 /**
293 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
294 * @dwc: Pointer to our controller context structure
295 * @length: size of the event buffer
296 *
297 * Returns a pointer to the allocated event buffer structure on success
298 * otherwise ERR_PTR(errno).
299 */
300 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
301 unsigned length)
302 {
303 struct dwc3_event_buffer *evt;
304
305 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
306 if (!evt)
307 return ERR_PTR(-ENOMEM);
308
309 evt->dwc = dwc;
310 evt->length = length;
311 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
312 if (!evt->cache)
313 return ERR_PTR(-ENOMEM);
314
315 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
316 &evt->dma, GFP_KERNEL);
317 if (!evt->buf)
318 return ERR_PTR(-ENOMEM);
319
320 return evt;
321 }
322
323 /**
324 * dwc3_free_event_buffers - frees all allocated event buffers
325 * @dwc: Pointer to our controller context structure
326 */
327 static void dwc3_free_event_buffers(struct dwc3 *dwc)
328 {
329 struct dwc3_event_buffer *evt;
330
331 evt = dwc->ev_buf;
332 if (evt)
333 dwc3_free_one_event_buffer(dwc, evt);
334 }
335
336 /**
337 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
338 * @dwc: pointer to our controller context structure
339 * @length: size of event buffer
340 *
341 * Returns 0 on success otherwise negative errno. In the error case, dwc
342 * may contain some buffers allocated but not all which were requested.
343 */
344 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
345 {
346 struct dwc3_event_buffer *evt;
347
348 evt = dwc3_alloc_one_event_buffer(dwc, length);
349 if (IS_ERR(evt)) {
350 dev_err(dwc->dev, "can't allocate event buffer\n");
351 return PTR_ERR(evt);
352 }
353 dwc->ev_buf = evt;
354
355 return 0;
356 }
357
358 /**
359 * dwc3_event_buffers_setup - setup our allocated event buffers
360 * @dwc: pointer to our controller context structure
361 *
362 * Returns 0 on success otherwise negative errno.
363 */
364 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
365 {
366 struct dwc3_event_buffer *evt;
367
368 evt = dwc->ev_buf;
369 evt->lpos = 0;
370 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
371 lower_32_bits(evt->dma));
372 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
373 upper_32_bits(evt->dma));
374 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
375 DWC3_GEVNTSIZ_SIZE(evt->length));
376 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
377
378 return 0;
379 }
380
381 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
382 {
383 struct dwc3_event_buffer *evt;
384
385 evt = dwc->ev_buf;
386
387 evt->lpos = 0;
388
389 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
390 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
391 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
392 | DWC3_GEVNTSIZ_SIZE(0));
393 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
394 }
395
396 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
397 {
398 if (!dwc->has_hibernation)
399 return 0;
400
401 if (!dwc->nr_scratch)
402 return 0;
403
404 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
405 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
406 if (!dwc->scratchbuf)
407 return -ENOMEM;
408
409 return 0;
410 }
411
412 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
413 {
414 dma_addr_t scratch_addr;
415 u32 param;
416 int ret;
417
418 if (!dwc->has_hibernation)
419 return 0;
420
421 if (!dwc->nr_scratch)
422 return 0;
423
424 /* should never fall here */
425 if (!WARN_ON(dwc->scratchbuf))
426 return 0;
427
428 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
429 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
430 DMA_BIDIRECTIONAL);
431 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
432 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
433 ret = -EFAULT;
434 goto err0;
435 }
436
437 dwc->scratch_addr = scratch_addr;
438
439 param = lower_32_bits(scratch_addr);
440
441 ret = dwc3_send_gadget_generic_command(dwc,
442 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
443 if (ret < 0)
444 goto err1;
445
446 param = upper_32_bits(scratch_addr);
447
448 ret = dwc3_send_gadget_generic_command(dwc,
449 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
450 if (ret < 0)
451 goto err1;
452
453 return 0;
454
455 err1:
456 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
457 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
458
459 err0:
460 return ret;
461 }
462
463 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
464 {
465 if (!dwc->has_hibernation)
466 return;
467
468 if (!dwc->nr_scratch)
469 return;
470
471 /* should never fall here */
472 if (!WARN_ON(dwc->scratchbuf))
473 return;
474
475 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
476 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
477 kfree(dwc->scratchbuf);
478 }
479
480 static void dwc3_core_num_eps(struct dwc3 *dwc)
481 {
482 struct dwc3_hwparams *parms = &dwc->hwparams;
483
484 dwc->num_eps = DWC3_NUM_EPS(parms);
485 }
486
487 static void dwc3_cache_hwparams(struct dwc3 *dwc)
488 {
489 struct dwc3_hwparams *parms = &dwc->hwparams;
490
491 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
492 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
493 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
494 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
495 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
496 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
497 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
498 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
499 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
500 }
501
502 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
503 {
504 int intf;
505 int ret = 0;
506
507 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
508
509 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
510 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
511 dwc->hsphy_interface &&
512 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
513 ret = dwc3_ulpi_init(dwc);
514
515 return ret;
516 }
517
518 /**
519 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
520 * @dwc: Pointer to our controller context structure
521 *
522 * Returns 0 on success. The USB PHY interfaces are configured but not
523 * initialized. The PHY interfaces and the PHYs get initialized together with
524 * the core in dwc3_core_init.
525 */
526 static int dwc3_phy_setup(struct dwc3 *dwc)
527 {
528 u32 reg;
529
530 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
531
532 /*
533 * Make sure UX_EXIT_PX is cleared as that causes issues with some
534 * PHYs. Also, this bit is not supposed to be used in normal operation.
535 */
536 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
537
538 /*
539 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
540 * to '0' during coreConsultant configuration. So default value
541 * will be '0' when the core is reset. Application needs to set it
542 * to '1' after the core initialization is completed.
543 */
544 if (dwc->revision > DWC3_REVISION_194A)
545 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
546
547 if (dwc->u2ss_inp3_quirk)
548 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
549
550 if (dwc->dis_rxdet_inp3_quirk)
551 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
552
553 if (dwc->req_p1p2p3_quirk)
554 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
555
556 if (dwc->del_p1p2p3_quirk)
557 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
558
559 if (dwc->del_phy_power_chg_quirk)
560 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
561
562 if (dwc->lfps_filter_quirk)
563 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
564
565 if (dwc->rx_detect_poll_quirk)
566 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
567
568 if (dwc->tx_de_emphasis_quirk)
569 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
570
571 if (dwc->dis_u3_susphy_quirk)
572 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
573
574 if (dwc->dis_del_phy_power_chg_quirk)
575 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
576
577 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
578
579 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
580
581 /* Select the HS PHY interface */
582 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
583 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
584 if (dwc->hsphy_interface &&
585 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
586 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
587 break;
588 } else if (dwc->hsphy_interface &&
589 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
590 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
591 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
592 } else {
593 /* Relying on default value. */
594 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
595 break;
596 }
597 /* FALLTHROUGH */
598 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
599 /* FALLTHROUGH */
600 default:
601 break;
602 }
603
604 switch (dwc->hsphy_mode) {
605 case USBPHY_INTERFACE_MODE_UTMI:
606 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
607 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
608 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
609 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
610 break;
611 case USBPHY_INTERFACE_MODE_UTMIW:
612 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
613 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
614 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
615 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
616 break;
617 default:
618 break;
619 }
620
621 /*
622 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
623 * '0' during coreConsultant configuration. So default value will
624 * be '0' when the core is reset. Application needs to set it to
625 * '1' after the core initialization is completed.
626 */
627 if (dwc->revision > DWC3_REVISION_194A)
628 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
629
630 if (dwc->dis_u2_susphy_quirk)
631 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
632
633 if (dwc->dis_enblslpm_quirk)
634 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
635
636 if (dwc->dis_u2_freeclk_exists_quirk)
637 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
638
639 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
640
641 return 0;
642 }
643
644 static void dwc3_core_exit(struct dwc3 *dwc)
645 {
646 dwc3_event_buffers_cleanup(dwc);
647
648 usb_phy_shutdown(dwc->usb2_phy);
649 usb_phy_shutdown(dwc->usb3_phy);
650 phy_exit(dwc->usb2_generic_phy);
651 phy_exit(dwc->usb3_generic_phy);
652
653 usb_phy_set_suspend(dwc->usb2_phy, 1);
654 usb_phy_set_suspend(dwc->usb3_phy, 1);
655 phy_power_off(dwc->usb2_generic_phy);
656 phy_power_off(dwc->usb3_generic_phy);
657 }
658
659 static bool dwc3_core_is_valid(struct dwc3 *dwc)
660 {
661 u32 reg;
662
663 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
664
665 /* This should read as U3 followed by revision number */
666 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
667 /* Detected DWC_usb3 IP */
668 dwc->revision = reg;
669 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
670 /* Detected DWC_usb31 IP */
671 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
672 dwc->revision |= DWC3_REVISION_IS_DWC31;
673 } else {
674 return false;
675 }
676
677 return true;
678 }
679
680 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
681 {
682 u32 hwparams4 = dwc->hwparams.hwparams4;
683 u32 reg;
684
685 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
686 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
687
688 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
689 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
690 /**
691 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
692 * issue which would cause xHCI compliance tests to fail.
693 *
694 * Because of that we cannot enable clock gating on such
695 * configurations.
696 *
697 * Refers to:
698 *
699 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
700 * SOF/ITP Mode Used
701 */
702 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
703 dwc->dr_mode == USB_DR_MODE_OTG) &&
704 (dwc->revision >= DWC3_REVISION_210A &&
705 dwc->revision <= DWC3_REVISION_250A))
706 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
707 else
708 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
709 break;
710 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
711 /* enable hibernation here */
712 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
713
714 /*
715 * REVISIT Enabling this bit so that host-mode hibernation
716 * will work. Device-mode hibernation is not yet implemented.
717 */
718 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
719 break;
720 default:
721 /* nothing */
722 break;
723 }
724
725 /* check if current dwc3 is on simulation board */
726 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
727 dev_info(dwc->dev, "Running with FPGA optmizations\n");
728 dwc->is_fpga = true;
729 }
730
731 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
732 "disable_scramble cannot be used on non-FPGA builds\n");
733
734 if (dwc->disable_scramble_quirk && dwc->is_fpga)
735 reg |= DWC3_GCTL_DISSCRAMBLE;
736 else
737 reg &= ~DWC3_GCTL_DISSCRAMBLE;
738
739 if (dwc->u2exit_lfps_quirk)
740 reg |= DWC3_GCTL_U2EXIT_LFPS;
741
742 /*
743 * WORKAROUND: DWC3 revisions <1.90a have a bug
744 * where the device can fail to connect at SuperSpeed
745 * and falls back to high-speed mode which causes
746 * the device to enter a Connect/Disconnect loop
747 */
748 if (dwc->revision < DWC3_REVISION_190A)
749 reg |= DWC3_GCTL_U2RSTECN;
750
751 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
752 }
753
754 static int dwc3_core_get_phy(struct dwc3 *dwc);
755 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
756
757 /**
758 * dwc3_core_init - Low-level initialization of DWC3 Core
759 * @dwc: Pointer to our controller context structure
760 *
761 * Returns 0 on success otherwise negative errno.
762 */
763 static int dwc3_core_init(struct dwc3 *dwc)
764 {
765 u32 reg;
766 int ret;
767
768 if (!dwc3_core_is_valid(dwc)) {
769 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
770 ret = -ENODEV;
771 goto err0;
772 }
773
774 /*
775 * Write Linux Version Code to our GUID register so it's easy to figure
776 * out which kernel version a bug was found.
777 */
778 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
779
780 /* Handle USB2.0-only core configuration */
781 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
782 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
783 if (dwc->maximum_speed == USB_SPEED_SUPER)
784 dwc->maximum_speed = USB_SPEED_HIGH;
785 }
786
787 ret = dwc3_phy_setup(dwc);
788 if (ret)
789 goto err0;
790
791 if (!dwc->ulpi_ready) {
792 ret = dwc3_core_ulpi_init(dwc);
793 if (ret)
794 goto err0;
795 dwc->ulpi_ready = true;
796 }
797
798 if (!dwc->phys_ready) {
799 ret = dwc3_core_get_phy(dwc);
800 if (ret)
801 goto err0a;
802 dwc->phys_ready = true;
803 }
804
805 ret = dwc3_core_soft_reset(dwc);
806 if (ret)
807 goto err0a;
808
809 dwc3_core_setup_global_control(dwc);
810 dwc3_core_num_eps(dwc);
811
812 ret = dwc3_setup_scratch_buffers(dwc);
813 if (ret)
814 goto err1;
815
816 /* Adjust Frame Length */
817 dwc3_frame_length_adjustment(dwc);
818
819 usb_phy_set_suspend(dwc->usb2_phy, 0);
820 usb_phy_set_suspend(dwc->usb3_phy, 0);
821 ret = phy_power_on(dwc->usb2_generic_phy);
822 if (ret < 0)
823 goto err2;
824
825 ret = phy_power_on(dwc->usb3_generic_phy);
826 if (ret < 0)
827 goto err3;
828
829 ret = dwc3_event_buffers_setup(dwc);
830 if (ret) {
831 dev_err(dwc->dev, "failed to setup event buffers\n");
832 goto err4;
833 }
834
835 /*
836 * ENDXFER polling is available on version 3.10a and later of
837 * the DWC_usb3 controller. It is NOT available in the
838 * DWC_usb31 controller.
839 */
840 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
841 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
842 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
843 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
844 }
845
846 if (dwc->revision >= DWC3_REVISION_250A) {
847 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
848
849 /*
850 * Enable hardware control of sending remote wakeup
851 * in HS when the device is in the L1 state.
852 */
853 if (dwc->revision >= DWC3_REVISION_290A)
854 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
855
856 if (dwc->dis_tx_ipgap_linecheck_quirk)
857 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
858
859 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
860 }
861
862 return 0;
863
864 err4:
865 phy_power_off(dwc->usb3_generic_phy);
866
867 err3:
868 phy_power_off(dwc->usb2_generic_phy);
869
870 err2:
871 usb_phy_set_suspend(dwc->usb2_phy, 1);
872 usb_phy_set_suspend(dwc->usb3_phy, 1);
873
874 err1:
875 usb_phy_shutdown(dwc->usb2_phy);
876 usb_phy_shutdown(dwc->usb3_phy);
877 phy_exit(dwc->usb2_generic_phy);
878 phy_exit(dwc->usb3_generic_phy);
879
880 err0a:
881 dwc3_ulpi_exit(dwc);
882
883 err0:
884 return ret;
885 }
886
887 static int dwc3_core_get_phy(struct dwc3 *dwc)
888 {
889 struct device *dev = dwc->dev;
890 struct device_node *node = dev->of_node;
891 int ret;
892
893 if (node) {
894 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
895 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
896 } else {
897 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
898 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
899 }
900
901 if (IS_ERR(dwc->usb2_phy)) {
902 ret = PTR_ERR(dwc->usb2_phy);
903 if (ret == -ENXIO || ret == -ENODEV) {
904 dwc->usb2_phy = NULL;
905 } else if (ret == -EPROBE_DEFER) {
906 return ret;
907 } else {
908 dev_err(dev, "no usb2 phy configured\n");
909 return ret;
910 }
911 }
912
913 if (IS_ERR(dwc->usb3_phy)) {
914 ret = PTR_ERR(dwc->usb3_phy);
915 if (ret == -ENXIO || ret == -ENODEV) {
916 dwc->usb3_phy = NULL;
917 } else if (ret == -EPROBE_DEFER) {
918 return ret;
919 } else {
920 dev_err(dev, "no usb3 phy configured\n");
921 return ret;
922 }
923 }
924
925 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
926 if (IS_ERR(dwc->usb2_generic_phy)) {
927 ret = PTR_ERR(dwc->usb2_generic_phy);
928 if (ret == -ENOSYS || ret == -ENODEV) {
929 dwc->usb2_generic_phy = NULL;
930 } else if (ret == -EPROBE_DEFER) {
931 return ret;
932 } else {
933 dev_err(dev, "no usb2 phy configured\n");
934 return ret;
935 }
936 }
937
938 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
939 if (IS_ERR(dwc->usb3_generic_phy)) {
940 ret = PTR_ERR(dwc->usb3_generic_phy);
941 if (ret == -ENOSYS || ret == -ENODEV) {
942 dwc->usb3_generic_phy = NULL;
943 } else if (ret == -EPROBE_DEFER) {
944 return ret;
945 } else {
946 dev_err(dev, "no usb3 phy configured\n");
947 return ret;
948 }
949 }
950
951 return 0;
952 }
953
954 static int dwc3_core_init_mode(struct dwc3 *dwc)
955 {
956 struct device *dev = dwc->dev;
957 int ret;
958
959 switch (dwc->dr_mode) {
960 case USB_DR_MODE_PERIPHERAL:
961 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
962
963 if (dwc->usb2_phy)
964 otg_set_vbus(dwc->usb2_phy->otg, false);
965 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
966 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
967
968 ret = dwc3_gadget_init(dwc);
969 if (ret) {
970 if (ret != -EPROBE_DEFER)
971 dev_err(dev, "failed to initialize gadget\n");
972 return ret;
973 }
974 break;
975 case USB_DR_MODE_HOST:
976 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
977
978 if (dwc->usb2_phy)
979 otg_set_vbus(dwc->usb2_phy->otg, true);
980 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
981 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
982
983 ret = dwc3_host_init(dwc);
984 if (ret) {
985 if (ret != -EPROBE_DEFER)
986 dev_err(dev, "failed to initialize host\n");
987 return ret;
988 }
989 break;
990 case USB_DR_MODE_OTG:
991 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
992 ret = dwc3_drd_init(dwc);
993 if (ret) {
994 if (ret != -EPROBE_DEFER)
995 dev_err(dev, "failed to initialize dual-role\n");
996 return ret;
997 }
998 break;
999 default:
1000 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1001 return -EINVAL;
1002 }
1003
1004 return 0;
1005 }
1006
1007 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1008 {
1009 switch (dwc->dr_mode) {
1010 case USB_DR_MODE_PERIPHERAL:
1011 dwc3_gadget_exit(dwc);
1012 break;
1013 case USB_DR_MODE_HOST:
1014 dwc3_host_exit(dwc);
1015 break;
1016 case USB_DR_MODE_OTG:
1017 dwc3_drd_exit(dwc);
1018 break;
1019 default:
1020 /* do nothing */
1021 break;
1022 }
1023 }
1024
1025 static void dwc3_get_properties(struct dwc3 *dwc)
1026 {
1027 struct device *dev = dwc->dev;
1028 u8 lpm_nyet_threshold;
1029 u8 tx_de_emphasis;
1030 u8 hird_threshold;
1031
1032 /* default to highest possible threshold */
1033 lpm_nyet_threshold = 0xff;
1034
1035 /* default to -3.5dB de-emphasis */
1036 tx_de_emphasis = 1;
1037
1038 /*
1039 * default to assert utmi_sleep_n and use maximum allowed HIRD
1040 * threshold value of 0b1100
1041 */
1042 hird_threshold = 12;
1043
1044 dwc->maximum_speed = usb_get_maximum_speed(dev);
1045 dwc->dr_mode = usb_get_dr_mode(dev);
1046 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1047
1048 dwc->sysdev_is_parent = device_property_read_bool(dev,
1049 "linux,sysdev_is_parent");
1050 if (dwc->sysdev_is_parent)
1051 dwc->sysdev = dwc->dev->parent;
1052 else
1053 dwc->sysdev = dwc->dev;
1054
1055 dwc->has_lpm_erratum = device_property_read_bool(dev,
1056 "snps,has-lpm-erratum");
1057 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1058 &lpm_nyet_threshold);
1059 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1060 "snps,is-utmi-l1-suspend");
1061 device_property_read_u8(dev, "snps,hird-threshold",
1062 &hird_threshold);
1063 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1064 "snps,usb3_lpm_capable");
1065
1066 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1067 "snps,disable_scramble_quirk");
1068 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1069 "snps,u2exit_lfps_quirk");
1070 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1071 "snps,u2ss_inp3_quirk");
1072 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1073 "snps,req_p1p2p3_quirk");
1074 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1075 "snps,del_p1p2p3_quirk");
1076 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1077 "snps,del_phy_power_chg_quirk");
1078 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1079 "snps,lfps_filter_quirk");
1080 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1081 "snps,rx_detect_poll_quirk");
1082 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1083 "snps,dis_u3_susphy_quirk");
1084 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1085 "snps,dis_u2_susphy_quirk");
1086 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1087 "snps,dis_enblslpm_quirk");
1088 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1089 "snps,dis_rxdet_inp3_quirk");
1090 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1091 "snps,dis-u2-freeclk-exists-quirk");
1092 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1093 "snps,dis-del-phy-power-chg-quirk");
1094 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1095 "snps,dis-tx-ipgap-linecheck-quirk");
1096
1097 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1098 "snps,tx_de_emphasis_quirk");
1099 device_property_read_u8(dev, "snps,tx_de_emphasis",
1100 &tx_de_emphasis);
1101 device_property_read_string(dev, "snps,hsphy_interface",
1102 &dwc->hsphy_interface);
1103 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1104 &dwc->fladj);
1105
1106 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1107 dwc->tx_de_emphasis = tx_de_emphasis;
1108
1109 dwc->hird_threshold = hird_threshold
1110 | (dwc->is_utmi_l1_suspend << 4);
1111
1112 dwc->imod_interval = 0;
1113 }
1114
1115 /* check whether the core supports IMOD */
1116 bool dwc3_has_imod(struct dwc3 *dwc)
1117 {
1118 return ((dwc3_is_usb3(dwc) &&
1119 dwc->revision >= DWC3_REVISION_300A) ||
1120 (dwc3_is_usb31(dwc) &&
1121 dwc->revision >= DWC3_USB31_REVISION_120A));
1122 }
1123
1124 static void dwc3_check_params(struct dwc3 *dwc)
1125 {
1126 struct device *dev = dwc->dev;
1127
1128 /* Check for proper value of imod_interval */
1129 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1130 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1131 dwc->imod_interval = 0;
1132 }
1133
1134 /*
1135 * Workaround for STAR 9000961433 which affects only version
1136 * 3.00a of the DWC_usb3 core. This prevents the controller
1137 * interrupt from being masked while handling events. IMOD
1138 * allows us to work around this issue. Enable it for the
1139 * affected version.
1140 */
1141 if (!dwc->imod_interval &&
1142 (dwc->revision == DWC3_REVISION_300A))
1143 dwc->imod_interval = 1;
1144
1145 /* Check the maximum_speed parameter */
1146 switch (dwc->maximum_speed) {
1147 case USB_SPEED_LOW:
1148 case USB_SPEED_FULL:
1149 case USB_SPEED_HIGH:
1150 case USB_SPEED_SUPER:
1151 case USB_SPEED_SUPER_PLUS:
1152 break;
1153 default:
1154 dev_err(dev, "invalid maximum_speed parameter %d\n",
1155 dwc->maximum_speed);
1156 /* fall through */
1157 case USB_SPEED_UNKNOWN:
1158 /* default to superspeed */
1159 dwc->maximum_speed = USB_SPEED_SUPER;
1160
1161 /*
1162 * default to superspeed plus if we are capable.
1163 */
1164 if (dwc3_is_usb31(dwc) &&
1165 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1166 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1167 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1168
1169 break;
1170 }
1171 }
1172
1173 static int dwc3_probe(struct platform_device *pdev)
1174 {
1175 struct device *dev = &pdev->dev;
1176 struct resource *res;
1177 struct dwc3 *dwc;
1178
1179 int ret;
1180
1181 void __iomem *regs;
1182
1183 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1184 if (!dwc)
1185 return -ENOMEM;
1186
1187 dwc->dev = dev;
1188
1189 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1190 if (!res) {
1191 dev_err(dev, "missing memory resource\n");
1192 return -ENODEV;
1193 }
1194
1195 dwc->xhci_resources[0].start = res->start;
1196 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1197 DWC3_XHCI_REGS_END;
1198 dwc->xhci_resources[0].flags = res->flags;
1199 dwc->xhci_resources[0].name = res->name;
1200
1201 res->start += DWC3_GLOBALS_REGS_START;
1202
1203 /*
1204 * Request memory region but exclude xHCI regs,
1205 * since it will be requested by the xhci-plat driver.
1206 */
1207 regs = devm_ioremap_resource(dev, res);
1208 if (IS_ERR(regs)) {
1209 ret = PTR_ERR(regs);
1210 goto err0;
1211 }
1212
1213 dwc->regs = regs;
1214 dwc->regs_size = resource_size(res);
1215
1216 dwc3_get_properties(dwc);
1217
1218 platform_set_drvdata(pdev, dwc);
1219 dwc3_cache_hwparams(dwc);
1220
1221 spin_lock_init(&dwc->lock);
1222
1223 pm_runtime_set_active(dev);
1224 pm_runtime_use_autosuspend(dev);
1225 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1226 pm_runtime_enable(dev);
1227 ret = pm_runtime_get_sync(dev);
1228 if (ret < 0)
1229 goto err1;
1230
1231 pm_runtime_forbid(dev);
1232
1233 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1234 if (ret) {
1235 dev_err(dwc->dev, "failed to allocate event buffers\n");
1236 ret = -ENOMEM;
1237 goto err2;
1238 }
1239
1240 ret = dwc3_get_dr_mode(dwc);
1241 if (ret)
1242 goto err3;
1243
1244 ret = dwc3_alloc_scratch_buffers(dwc);
1245 if (ret)
1246 goto err3;
1247
1248 ret = dwc3_core_init(dwc);
1249 if (ret) {
1250 dev_err(dev, "failed to initialize core\n");
1251 goto err4;
1252 }
1253
1254 dwc3_check_params(dwc);
1255
1256 ret = dwc3_core_init_mode(dwc);
1257 if (ret)
1258 goto err5;
1259
1260 dwc3_debugfs_init(dwc);
1261 pm_runtime_put(dev);
1262
1263 return 0;
1264
1265 err5:
1266 dwc3_event_buffers_cleanup(dwc);
1267
1268 err4:
1269 dwc3_free_scratch_buffers(dwc);
1270
1271 err3:
1272 dwc3_free_event_buffers(dwc);
1273
1274 err2:
1275 pm_runtime_allow(&pdev->dev);
1276
1277 err1:
1278 pm_runtime_put_sync(&pdev->dev);
1279 pm_runtime_disable(&pdev->dev);
1280
1281 err0:
1282 /*
1283 * restore res->start back to its original value so that, in case the
1284 * probe is deferred, we don't end up getting error in request the
1285 * memory region the next time probe is called.
1286 */
1287 res->start -= DWC3_GLOBALS_REGS_START;
1288
1289 return ret;
1290 }
1291
1292 static int dwc3_remove(struct platform_device *pdev)
1293 {
1294 struct dwc3 *dwc = platform_get_drvdata(pdev);
1295 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1296
1297 pm_runtime_get_sync(&pdev->dev);
1298 /*
1299 * restore res->start back to its original value so that, in case the
1300 * probe is deferred, we don't end up getting error in request the
1301 * memory region the next time probe is called.
1302 */
1303 res->start -= DWC3_GLOBALS_REGS_START;
1304
1305 dwc3_debugfs_exit(dwc);
1306 dwc3_core_exit_mode(dwc);
1307
1308 dwc3_core_exit(dwc);
1309 dwc3_ulpi_exit(dwc);
1310
1311 pm_runtime_put_sync(&pdev->dev);
1312 pm_runtime_allow(&pdev->dev);
1313 pm_runtime_disable(&pdev->dev);
1314
1315 dwc3_free_event_buffers(dwc);
1316 dwc3_free_scratch_buffers(dwc);
1317
1318 return 0;
1319 }
1320
1321 #ifdef CONFIG_PM
1322 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1323 {
1324 unsigned long flags;
1325
1326 switch (dwc->current_dr_role) {
1327 case DWC3_GCTL_PRTCAP_DEVICE:
1328 spin_lock_irqsave(&dwc->lock, flags);
1329 dwc3_gadget_suspend(dwc);
1330 spin_unlock_irqrestore(&dwc->lock, flags);
1331 dwc3_core_exit(dwc);
1332 break;
1333 case DWC3_GCTL_PRTCAP_HOST:
1334 /* do nothing during host runtime_suspend */
1335 if (!PMSG_IS_AUTO(msg))
1336 dwc3_core_exit(dwc);
1337 break;
1338 default:
1339 /* do nothing */
1340 break;
1341 }
1342
1343 return 0;
1344 }
1345
1346 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1347 {
1348 unsigned long flags;
1349 int ret;
1350
1351 switch (dwc->current_dr_role) {
1352 case DWC3_GCTL_PRTCAP_DEVICE:
1353 ret = dwc3_core_init(dwc);
1354 if (ret)
1355 return ret;
1356
1357 spin_lock_irqsave(&dwc->lock, flags);
1358 dwc3_gadget_resume(dwc);
1359 spin_unlock_irqrestore(&dwc->lock, flags);
1360 break;
1361 case DWC3_GCTL_PRTCAP_HOST:
1362 /* nothing to do on host runtime_resume */
1363 if (!PMSG_IS_AUTO(msg)) {
1364 ret = dwc3_core_init(dwc);
1365 if (ret)
1366 return ret;
1367 }
1368 break;
1369 default:
1370 /* do nothing */
1371 break;
1372 }
1373
1374 return 0;
1375 }
1376
1377 static int dwc3_runtime_checks(struct dwc3 *dwc)
1378 {
1379 switch (dwc->current_dr_role) {
1380 case DWC3_GCTL_PRTCAP_DEVICE:
1381 if (dwc->connected)
1382 return -EBUSY;
1383 break;
1384 case DWC3_GCTL_PRTCAP_HOST:
1385 default:
1386 /* do nothing */
1387 break;
1388 }
1389
1390 return 0;
1391 }
1392
1393 static int dwc3_runtime_suspend(struct device *dev)
1394 {
1395 struct dwc3 *dwc = dev_get_drvdata(dev);
1396 int ret;
1397
1398 if (dwc3_runtime_checks(dwc))
1399 return -EBUSY;
1400
1401 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1402 if (ret)
1403 return ret;
1404
1405 device_init_wakeup(dev, true);
1406
1407 return 0;
1408 }
1409
1410 static int dwc3_runtime_resume(struct device *dev)
1411 {
1412 struct dwc3 *dwc = dev_get_drvdata(dev);
1413 int ret;
1414
1415 device_init_wakeup(dev, false);
1416
1417 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1418 if (ret)
1419 return ret;
1420
1421 switch (dwc->current_dr_role) {
1422 case DWC3_GCTL_PRTCAP_DEVICE:
1423 dwc3_gadget_process_pending_events(dwc);
1424 break;
1425 case DWC3_GCTL_PRTCAP_HOST:
1426 default:
1427 /* do nothing */
1428 break;
1429 }
1430
1431 pm_runtime_mark_last_busy(dev);
1432
1433 return 0;
1434 }
1435
1436 static int dwc3_runtime_idle(struct device *dev)
1437 {
1438 struct dwc3 *dwc = dev_get_drvdata(dev);
1439
1440 switch (dwc->current_dr_role) {
1441 case DWC3_GCTL_PRTCAP_DEVICE:
1442 if (dwc3_runtime_checks(dwc))
1443 return -EBUSY;
1444 break;
1445 case DWC3_GCTL_PRTCAP_HOST:
1446 default:
1447 /* do nothing */
1448 break;
1449 }
1450
1451 pm_runtime_mark_last_busy(dev);
1452 pm_runtime_autosuspend(dev);
1453
1454 return 0;
1455 }
1456 #endif /* CONFIG_PM */
1457
1458 #ifdef CONFIG_PM_SLEEP
1459 static int dwc3_suspend(struct device *dev)
1460 {
1461 struct dwc3 *dwc = dev_get_drvdata(dev);
1462 int ret;
1463
1464 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1465 if (ret)
1466 return ret;
1467
1468 pinctrl_pm_select_sleep_state(dev);
1469
1470 return 0;
1471 }
1472
1473 static int dwc3_resume(struct device *dev)
1474 {
1475 struct dwc3 *dwc = dev_get_drvdata(dev);
1476 int ret;
1477
1478 pinctrl_pm_select_default_state(dev);
1479
1480 ret = dwc3_resume_common(dwc, PMSG_RESUME);
1481 if (ret)
1482 return ret;
1483
1484 pm_runtime_disable(dev);
1485 pm_runtime_set_active(dev);
1486 pm_runtime_enable(dev);
1487
1488 return 0;
1489 }
1490 #endif /* CONFIG_PM_SLEEP */
1491
1492 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1493 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1494 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1495 dwc3_runtime_idle)
1496 };
1497
1498 #ifdef CONFIG_OF
1499 static const struct of_device_id of_dwc3_match[] = {
1500 {
1501 .compatible = "snps,dwc3"
1502 },
1503 {
1504 .compatible = "synopsys,dwc3"
1505 },
1506 { },
1507 };
1508 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1509 #endif
1510
1511 #ifdef CONFIG_ACPI
1512
1513 #define ACPI_ID_INTEL_BSW "808622B7"
1514
1515 static const struct acpi_device_id dwc3_acpi_match[] = {
1516 { ACPI_ID_INTEL_BSW, 0 },
1517 { },
1518 };
1519 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1520 #endif
1521
1522 static struct platform_driver dwc3_driver = {
1523 .probe = dwc3_probe,
1524 .remove = dwc3_remove,
1525 .driver = {
1526 .name = "dwc3",
1527 .of_match_table = of_match_ptr(of_dwc3_match),
1528 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1529 .pm = &dwc3_dev_pm_ops,
1530 },
1531 };
1532
1533 module_platform_driver(dwc3_driver);
1534
1535 MODULE_ALIAS("platform:dwc3");
1536 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1537 MODULE_LICENSE("GPL v2");
1538 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
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