1 // SPDX-License-Identifier: GPL-2.0
3 * core.c - DesignWare USB3 DRD Controller Core file
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/version.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/spinlock.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/interrupt.h>
19 #include <linux/ioport.h>
21 #include <linux/list.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
25 #include <linux/acpi.h>
26 #include <linux/pinctrl/consumer.h>
28 #include <linux/usb/ch9.h>
29 #include <linux/usb/gadget.h>
30 #include <linux/usb/of.h>
31 #include <linux/usb/otg.h>
39 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
42 * dwc3_get_dr_mode - Validates and sets dr_mode
43 * @dwc: pointer to our context structure
45 static int dwc3_get_dr_mode(struct dwc3
*dwc
)
47 enum usb_dr_mode mode
;
48 struct device
*dev
= dwc
->dev
;
51 if (dwc
->dr_mode
== USB_DR_MODE_UNKNOWN
)
52 dwc
->dr_mode
= USB_DR_MODE_OTG
;
55 hw_mode
= DWC3_GHWPARAMS0_MODE(dwc
->hwparams
.hwparams0
);
58 case DWC3_GHWPARAMS0_MODE_GADGET
:
59 if (IS_ENABLED(CONFIG_USB_DWC3_HOST
)) {
61 "Controller does not support host mode.\n");
64 mode
= USB_DR_MODE_PERIPHERAL
;
66 case DWC3_GHWPARAMS0_MODE_HOST
:
67 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET
)) {
69 "Controller does not support device mode.\n");
72 mode
= USB_DR_MODE_HOST
;
75 if (IS_ENABLED(CONFIG_USB_DWC3_HOST
))
76 mode
= USB_DR_MODE_HOST
;
77 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET
))
78 mode
= USB_DR_MODE_PERIPHERAL
;
81 if (mode
!= dwc
->dr_mode
) {
83 "Configuration mismatch. dr_mode forced to %s\n",
84 mode
== USB_DR_MODE_HOST
? "host" : "gadget");
92 static void dwc3_event_buffers_cleanup(struct dwc3
*dwc
);
93 static int dwc3_event_buffers_setup(struct dwc3
*dwc
);
95 static void dwc3_set_prtcap(struct dwc3
*dwc
, u32 mode
)
99 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
100 reg
&= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG
));
101 reg
|= DWC3_GCTL_PRTCAPDIR(mode
);
102 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
105 static void __dwc3_set_mode(struct work_struct
*work
)
107 struct dwc3
*dwc
= work_to_dwc(work
);
111 if (!dwc
->desired_dr_role
)
114 if (dwc
->desired_dr_role
== dwc
->current_dr_role
)
117 if (dwc
->dr_mode
!= USB_DR_MODE_OTG
)
120 switch (dwc
->current_dr_role
) {
121 case DWC3_GCTL_PRTCAP_HOST
:
124 case DWC3_GCTL_PRTCAP_DEVICE
:
125 dwc3_gadget_exit(dwc
);
126 dwc3_event_buffers_cleanup(dwc
);
132 spin_lock_irqsave(&dwc
->lock
, flags
);
134 dwc3_set_prtcap(dwc
, dwc
->desired_dr_role
);
136 dwc
->current_dr_role
= dwc
->desired_dr_role
;
138 spin_unlock_irqrestore(&dwc
->lock
, flags
);
140 switch (dwc
->desired_dr_role
) {
141 case DWC3_GCTL_PRTCAP_HOST
:
142 ret
= dwc3_host_init(dwc
);
144 dev_err(dwc
->dev
, "failed to initialize host\n");
147 otg_set_vbus(dwc
->usb2_phy
->otg
, true);
148 phy_set_mode(dwc
->usb2_generic_phy
, PHY_MODE_USB_HOST
);
149 phy_set_mode(dwc
->usb3_generic_phy
, PHY_MODE_USB_HOST
);
152 case DWC3_GCTL_PRTCAP_DEVICE
:
153 dwc3_event_buffers_setup(dwc
);
156 otg_set_vbus(dwc
->usb2_phy
->otg
, false);
157 phy_set_mode(dwc
->usb2_generic_phy
, PHY_MODE_USB_DEVICE
);
158 phy_set_mode(dwc
->usb3_generic_phy
, PHY_MODE_USB_DEVICE
);
160 ret
= dwc3_gadget_init(dwc
);
162 dev_err(dwc
->dev
, "failed to initialize peripheral\n");
169 void dwc3_set_mode(struct dwc3
*dwc
, u32 mode
)
173 spin_lock_irqsave(&dwc
->lock
, flags
);
174 dwc
->desired_dr_role
= mode
;
175 spin_unlock_irqrestore(&dwc
->lock
, flags
);
177 queue_work(system_power_efficient_wq
, &dwc
->drd_work
);
180 u32
dwc3_core_fifo_space(struct dwc3_ep
*dep
, u8 type
)
182 struct dwc3
*dwc
= dep
->dwc
;
185 dwc3_writel(dwc
->regs
, DWC3_GDBGFIFOSPACE
,
186 DWC3_GDBGFIFOSPACE_NUM(dep
->number
) |
187 DWC3_GDBGFIFOSPACE_TYPE(type
));
189 reg
= dwc3_readl(dwc
->regs
, DWC3_GDBGFIFOSPACE
);
191 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg
);
195 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
196 * @dwc: pointer to our context structure
198 static int dwc3_core_soft_reset(struct dwc3
*dwc
)
204 usb_phy_init(dwc
->usb2_phy
);
205 usb_phy_init(dwc
->usb3_phy
);
206 ret
= phy_init(dwc
->usb2_generic_phy
);
210 ret
= phy_init(dwc
->usb3_generic_phy
);
212 phy_exit(dwc
->usb2_generic_phy
);
217 * We're resetting only the device side because, if we're in host mode,
218 * XHCI driver will reset the host block. If dwc3 was configured for
219 * host-only mode, then we can return early.
221 if (dwc
->dr_mode
== USB_DR_MODE_HOST
)
224 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
225 reg
|= DWC3_DCTL_CSFTRST
;
226 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
229 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
230 if (!(reg
& DWC3_DCTL_CSFTRST
))
240 * dwc3_frame_length_adjustment - Adjusts frame length if required
241 * @dwc3: Pointer to our controller context structure
243 static void dwc3_frame_length_adjustment(struct dwc3
*dwc
)
248 if (dwc
->revision
< DWC3_REVISION_250A
)
254 reg
= dwc3_readl(dwc
->regs
, DWC3_GFLADJ
);
255 dft
= reg
& DWC3_GFLADJ_30MHZ_MASK
;
256 if (!dev_WARN_ONCE(dwc
->dev
, dft
== dwc
->fladj
,
257 "request value same as default, ignoring\n")) {
258 reg
&= ~DWC3_GFLADJ_30MHZ_MASK
;
259 reg
|= DWC3_GFLADJ_30MHZ_SDBND_SEL
| dwc
->fladj
;
260 dwc3_writel(dwc
->regs
, DWC3_GFLADJ
, reg
);
265 * dwc3_free_one_event_buffer - Frees one event buffer
266 * @dwc: Pointer to our controller context structure
267 * @evt: Pointer to event buffer to be freed
269 static void dwc3_free_one_event_buffer(struct dwc3
*dwc
,
270 struct dwc3_event_buffer
*evt
)
272 dma_free_coherent(dwc
->sysdev
, evt
->length
, evt
->buf
, evt
->dma
);
276 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
277 * @dwc: Pointer to our controller context structure
278 * @length: size of the event buffer
280 * Returns a pointer to the allocated event buffer structure on success
281 * otherwise ERR_PTR(errno).
283 static struct dwc3_event_buffer
*dwc3_alloc_one_event_buffer(struct dwc3
*dwc
,
286 struct dwc3_event_buffer
*evt
;
288 evt
= devm_kzalloc(dwc
->dev
, sizeof(*evt
), GFP_KERNEL
);
290 return ERR_PTR(-ENOMEM
);
293 evt
->length
= length
;
294 evt
->cache
= devm_kzalloc(dwc
->dev
, length
, GFP_KERNEL
);
296 return ERR_PTR(-ENOMEM
);
298 evt
->buf
= dma_alloc_coherent(dwc
->sysdev
, length
,
299 &evt
->dma
, GFP_KERNEL
);
301 return ERR_PTR(-ENOMEM
);
307 * dwc3_free_event_buffers - frees all allocated event buffers
308 * @dwc: Pointer to our controller context structure
310 static void dwc3_free_event_buffers(struct dwc3
*dwc
)
312 struct dwc3_event_buffer
*evt
;
316 dwc3_free_one_event_buffer(dwc
, evt
);
320 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
321 * @dwc: pointer to our controller context structure
322 * @length: size of event buffer
324 * Returns 0 on success otherwise negative errno. In the error case, dwc
325 * may contain some buffers allocated but not all which were requested.
327 static int dwc3_alloc_event_buffers(struct dwc3
*dwc
, unsigned length
)
329 struct dwc3_event_buffer
*evt
;
331 evt
= dwc3_alloc_one_event_buffer(dwc
, length
);
333 dev_err(dwc
->dev
, "can't allocate event buffer\n");
342 * dwc3_event_buffers_setup - setup our allocated event buffers
343 * @dwc: pointer to our controller context structure
345 * Returns 0 on success otherwise negative errno.
347 static int dwc3_event_buffers_setup(struct dwc3
*dwc
)
349 struct dwc3_event_buffer
*evt
;
353 dwc3_writel(dwc
->regs
, DWC3_GEVNTADRLO(0),
354 lower_32_bits(evt
->dma
));
355 dwc3_writel(dwc
->regs
, DWC3_GEVNTADRHI(0),
356 upper_32_bits(evt
->dma
));
357 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0),
358 DWC3_GEVNTSIZ_SIZE(evt
->length
));
359 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), 0);
364 static void dwc3_event_buffers_cleanup(struct dwc3
*dwc
)
366 struct dwc3_event_buffer
*evt
;
372 dwc3_writel(dwc
->regs
, DWC3_GEVNTADRLO(0), 0);
373 dwc3_writel(dwc
->regs
, DWC3_GEVNTADRHI(0), 0);
374 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
375 | DWC3_GEVNTSIZ_SIZE(0));
376 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), 0);
379 static int dwc3_alloc_scratch_buffers(struct dwc3
*dwc
)
381 if (!dwc
->has_hibernation
)
384 if (!dwc
->nr_scratch
)
387 dwc
->scratchbuf
= kmalloc_array(dwc
->nr_scratch
,
388 DWC3_SCRATCHBUF_SIZE
, GFP_KERNEL
);
389 if (!dwc
->scratchbuf
)
395 static int dwc3_setup_scratch_buffers(struct dwc3
*dwc
)
397 dma_addr_t scratch_addr
;
401 if (!dwc
->has_hibernation
)
404 if (!dwc
->nr_scratch
)
407 /* should never fall here */
408 if (!WARN_ON(dwc
->scratchbuf
))
411 scratch_addr
= dma_map_single(dwc
->sysdev
, dwc
->scratchbuf
,
412 dwc
->nr_scratch
* DWC3_SCRATCHBUF_SIZE
,
414 if (dma_mapping_error(dwc
->sysdev
, scratch_addr
)) {
415 dev_err(dwc
->sysdev
, "failed to map scratch buffer\n");
420 dwc
->scratch_addr
= scratch_addr
;
422 param
= lower_32_bits(scratch_addr
);
424 ret
= dwc3_send_gadget_generic_command(dwc
,
425 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO
, param
);
429 param
= upper_32_bits(scratch_addr
);
431 ret
= dwc3_send_gadget_generic_command(dwc
,
432 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI
, param
);
439 dma_unmap_single(dwc
->sysdev
, dwc
->scratch_addr
, dwc
->nr_scratch
*
440 DWC3_SCRATCHBUF_SIZE
, DMA_BIDIRECTIONAL
);
446 static void dwc3_free_scratch_buffers(struct dwc3
*dwc
)
448 if (!dwc
->has_hibernation
)
451 if (!dwc
->nr_scratch
)
454 /* should never fall here */
455 if (!WARN_ON(dwc
->scratchbuf
))
458 dma_unmap_single(dwc
->sysdev
, dwc
->scratch_addr
, dwc
->nr_scratch
*
459 DWC3_SCRATCHBUF_SIZE
, DMA_BIDIRECTIONAL
);
460 kfree(dwc
->scratchbuf
);
463 static void dwc3_core_num_eps(struct dwc3
*dwc
)
465 struct dwc3_hwparams
*parms
= &dwc
->hwparams
;
467 dwc
->num_eps
= DWC3_NUM_EPS(parms
);
470 static void dwc3_cache_hwparams(struct dwc3
*dwc
)
472 struct dwc3_hwparams
*parms
= &dwc
->hwparams
;
474 parms
->hwparams0
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS0
);
475 parms
->hwparams1
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS1
);
476 parms
->hwparams2
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS2
);
477 parms
->hwparams3
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS3
);
478 parms
->hwparams4
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS4
);
479 parms
->hwparams5
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS5
);
480 parms
->hwparams6
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS6
);
481 parms
->hwparams7
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS7
);
482 parms
->hwparams8
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS8
);
486 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
487 * @dwc: Pointer to our controller context structure
489 * Returns 0 on success. The USB PHY interfaces are configured but not
490 * initialized. The PHY interfaces and the PHYs get initialized together with
491 * the core in dwc3_core_init.
493 static int dwc3_phy_setup(struct dwc3
*dwc
)
498 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB3PIPECTL(0));
501 * Make sure UX_EXIT_PX is cleared as that causes issues with some
502 * PHYs. Also, this bit is not supposed to be used in normal operation.
504 reg
&= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX
;
507 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
508 * to '0' during coreConsultant configuration. So default value
509 * will be '0' when the core is reset. Application needs to set it
510 * to '1' after the core initialization is completed.
512 if (dwc
->revision
> DWC3_REVISION_194A
)
513 reg
|= DWC3_GUSB3PIPECTL_SUSPHY
;
515 if (dwc
->u2ss_inp3_quirk
)
516 reg
|= DWC3_GUSB3PIPECTL_U2SSINP3OK
;
518 if (dwc
->dis_rxdet_inp3_quirk
)
519 reg
|= DWC3_GUSB3PIPECTL_DISRXDETINP3
;
521 if (dwc
->req_p1p2p3_quirk
)
522 reg
|= DWC3_GUSB3PIPECTL_REQP1P2P3
;
524 if (dwc
->del_p1p2p3_quirk
)
525 reg
|= DWC3_GUSB3PIPECTL_DEP1P2P3_EN
;
527 if (dwc
->del_phy_power_chg_quirk
)
528 reg
|= DWC3_GUSB3PIPECTL_DEPOCHANGE
;
530 if (dwc
->lfps_filter_quirk
)
531 reg
|= DWC3_GUSB3PIPECTL_LFPSFILT
;
533 if (dwc
->rx_detect_poll_quirk
)
534 reg
|= DWC3_GUSB3PIPECTL_RX_DETOPOLL
;
536 if (dwc
->tx_de_emphasis_quirk
)
537 reg
|= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc
->tx_de_emphasis
);
539 if (dwc
->dis_u3_susphy_quirk
)
540 reg
&= ~DWC3_GUSB3PIPECTL_SUSPHY
;
542 if (dwc
->dis_del_phy_power_chg_quirk
)
543 reg
&= ~DWC3_GUSB3PIPECTL_DEPOCHANGE
;
545 dwc3_writel(dwc
->regs
, DWC3_GUSB3PIPECTL(0), reg
);
547 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
549 /* Select the HS PHY interface */
550 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc
->hwparams
.hwparams3
)) {
551 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI
:
552 if (dwc
->hsphy_interface
&&
553 !strncmp(dwc
->hsphy_interface
, "utmi", 4)) {
554 reg
&= ~DWC3_GUSB2PHYCFG_ULPI_UTMI
;
556 } else if (dwc
->hsphy_interface
&&
557 !strncmp(dwc
->hsphy_interface
, "ulpi", 4)) {
558 reg
|= DWC3_GUSB2PHYCFG_ULPI_UTMI
;
559 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
561 /* Relying on default value. */
562 if (!(reg
& DWC3_GUSB2PHYCFG_ULPI_UTMI
))
566 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI
:
567 ret
= dwc3_ulpi_init(dwc
);
575 switch (dwc
->hsphy_mode
) {
576 case USBPHY_INTERFACE_MODE_UTMI
:
577 reg
&= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK
|
578 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK
);
579 reg
|= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT
) |
580 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT
);
582 case USBPHY_INTERFACE_MODE_UTMIW
:
583 reg
&= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK
|
584 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK
);
585 reg
|= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT
) |
586 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT
);
593 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
594 * '0' during coreConsultant configuration. So default value will
595 * be '0' when the core is reset. Application needs to set it to
596 * '1' after the core initialization is completed.
598 if (dwc
->revision
> DWC3_REVISION_194A
)
599 reg
|= DWC3_GUSB2PHYCFG_SUSPHY
;
601 if (dwc
->dis_u2_susphy_quirk
)
602 reg
&= ~DWC3_GUSB2PHYCFG_SUSPHY
;
604 if (dwc
->dis_enblslpm_quirk
)
605 reg
&= ~DWC3_GUSB2PHYCFG_ENBLSLPM
;
607 if (dwc
->dis_u2_freeclk_exists_quirk
)
608 reg
&= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS
;
610 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
615 static void dwc3_core_exit(struct dwc3
*dwc
)
617 dwc3_event_buffers_cleanup(dwc
);
619 usb_phy_shutdown(dwc
->usb2_phy
);
620 usb_phy_shutdown(dwc
->usb3_phy
);
621 phy_exit(dwc
->usb2_generic_phy
);
622 phy_exit(dwc
->usb3_generic_phy
);
624 usb_phy_set_suspend(dwc
->usb2_phy
, 1);
625 usb_phy_set_suspend(dwc
->usb3_phy
, 1);
626 phy_power_off(dwc
->usb2_generic_phy
);
627 phy_power_off(dwc
->usb3_generic_phy
);
630 static bool dwc3_core_is_valid(struct dwc3
*dwc
)
634 reg
= dwc3_readl(dwc
->regs
, DWC3_GSNPSID
);
636 /* This should read as U3 followed by revision number */
637 if ((reg
& DWC3_GSNPSID_MASK
) == 0x55330000) {
638 /* Detected DWC_usb3 IP */
640 } else if ((reg
& DWC3_GSNPSID_MASK
) == 0x33310000) {
641 /* Detected DWC_usb31 IP */
642 dwc
->revision
= dwc3_readl(dwc
->regs
, DWC3_VER_NUMBER
);
643 dwc
->revision
|= DWC3_REVISION_IS_DWC31
;
651 static void dwc3_core_setup_global_control(struct dwc3
*dwc
)
653 u32 hwparams4
= dwc
->hwparams
.hwparams4
;
656 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
657 reg
&= ~DWC3_GCTL_SCALEDOWN_MASK
;
659 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc
->hwparams
.hwparams1
)) {
660 case DWC3_GHWPARAMS1_EN_PWROPT_CLK
:
662 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
663 * issue which would cause xHCI compliance tests to fail.
665 * Because of that we cannot enable clock gating on such
670 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
673 if ((dwc
->dr_mode
== USB_DR_MODE_HOST
||
674 dwc
->dr_mode
== USB_DR_MODE_OTG
) &&
675 (dwc
->revision
>= DWC3_REVISION_210A
&&
676 dwc
->revision
<= DWC3_REVISION_250A
))
677 reg
|= DWC3_GCTL_DSBLCLKGTNG
| DWC3_GCTL_SOFITPSYNC
;
679 reg
&= ~DWC3_GCTL_DSBLCLKGTNG
;
681 case DWC3_GHWPARAMS1_EN_PWROPT_HIB
:
682 /* enable hibernation here */
683 dwc
->nr_scratch
= DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4
);
686 * REVISIT Enabling this bit so that host-mode hibernation
687 * will work. Device-mode hibernation is not yet implemented.
689 reg
|= DWC3_GCTL_GBLHIBERNATIONEN
;
696 /* check if current dwc3 is on simulation board */
697 if (dwc
->hwparams
.hwparams6
& DWC3_GHWPARAMS6_EN_FPGA
) {
698 dev_info(dwc
->dev
, "Running with FPGA optmizations\n");
702 WARN_ONCE(dwc
->disable_scramble_quirk
&& !dwc
->is_fpga
,
703 "disable_scramble cannot be used on non-FPGA builds\n");
705 if (dwc
->disable_scramble_quirk
&& dwc
->is_fpga
)
706 reg
|= DWC3_GCTL_DISSCRAMBLE
;
708 reg
&= ~DWC3_GCTL_DISSCRAMBLE
;
710 if (dwc
->u2exit_lfps_quirk
)
711 reg
|= DWC3_GCTL_U2EXIT_LFPS
;
714 * WORKAROUND: DWC3 revisions <1.90a have a bug
715 * where the device can fail to connect at SuperSpeed
716 * and falls back to high-speed mode which causes
717 * the device to enter a Connect/Disconnect loop
719 if (dwc
->revision
< DWC3_REVISION_190A
)
720 reg
|= DWC3_GCTL_U2RSTECN
;
722 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
725 static int dwc3_core_get_phy(struct dwc3
*dwc
);
728 * dwc3_core_init - Low-level initialization of DWC3 Core
729 * @dwc: Pointer to our controller context structure
731 * Returns 0 on success otherwise negative errno.
733 static int dwc3_core_init(struct dwc3
*dwc
)
738 if (!dwc3_core_is_valid(dwc
)) {
739 dev_err(dwc
->dev
, "this is not a DesignWare USB3 DRD Core\n");
745 * Write Linux Version Code to our GUID register so it's easy to figure
746 * out which kernel version a bug was found.
748 dwc3_writel(dwc
->regs
, DWC3_GUID
, LINUX_VERSION_CODE
);
750 /* Handle USB2.0-only core configuration */
751 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc
->hwparams
.hwparams3
) ==
752 DWC3_GHWPARAMS3_SSPHY_IFC_DIS
) {
753 if (dwc
->maximum_speed
== USB_SPEED_SUPER
)
754 dwc
->maximum_speed
= USB_SPEED_HIGH
;
757 ret
= dwc3_core_get_phy(dwc
);
761 ret
= dwc3_core_soft_reset(dwc
);
765 ret
= dwc3_phy_setup(dwc
);
769 dwc3_core_setup_global_control(dwc
);
770 dwc3_core_num_eps(dwc
);
772 ret
= dwc3_setup_scratch_buffers(dwc
);
776 /* Adjust Frame Length */
777 dwc3_frame_length_adjustment(dwc
);
779 usb_phy_set_suspend(dwc
->usb2_phy
, 0);
780 usb_phy_set_suspend(dwc
->usb3_phy
, 0);
781 ret
= phy_power_on(dwc
->usb2_generic_phy
);
785 ret
= phy_power_on(dwc
->usb3_generic_phy
);
789 ret
= dwc3_event_buffers_setup(dwc
);
791 dev_err(dwc
->dev
, "failed to setup event buffers\n");
796 * ENDXFER polling is available on version 3.10a and later of
797 * the DWC_usb3 controller. It is NOT available in the
798 * DWC_usb31 controller.
800 if (!dwc3_is_usb31(dwc
) && dwc
->revision
>= DWC3_REVISION_310A
) {
801 reg
= dwc3_readl(dwc
->regs
, DWC3_GUCTL2
);
802 reg
|= DWC3_GUCTL2_RST_ACTBITLATER
;
803 dwc3_writel(dwc
->regs
, DWC3_GUCTL2
, reg
);
806 if (dwc
->revision
>= DWC3_REVISION_250A
) {
807 reg
= dwc3_readl(dwc
->regs
, DWC3_GUCTL1
);
810 * Enable hardware control of sending remote wakeup
811 * in HS when the device is in the L1 state.
813 if (dwc
->revision
>= DWC3_REVISION_290A
)
814 reg
|= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW
;
816 if (dwc
->dis_tx_ipgap_linecheck_quirk
)
817 reg
|= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS
;
819 dwc3_writel(dwc
->regs
, DWC3_GUCTL1
, reg
);
825 phy_power_off(dwc
->usb3_generic_phy
);
828 phy_power_off(dwc
->usb2_generic_phy
);
831 usb_phy_set_suspend(dwc
->usb2_phy
, 1);
832 usb_phy_set_suspend(dwc
->usb3_phy
, 1);
835 usb_phy_shutdown(dwc
->usb2_phy
);
836 usb_phy_shutdown(dwc
->usb3_phy
);
837 phy_exit(dwc
->usb2_generic_phy
);
838 phy_exit(dwc
->usb3_generic_phy
);
844 static int dwc3_core_get_phy(struct dwc3
*dwc
)
846 struct device
*dev
= dwc
->dev
;
847 struct device_node
*node
= dev
->of_node
;
851 dwc
->usb2_phy
= devm_usb_get_phy_by_phandle(dev
, "usb-phy", 0);
852 dwc
->usb3_phy
= devm_usb_get_phy_by_phandle(dev
, "usb-phy", 1);
854 dwc
->usb2_phy
= devm_usb_get_phy(dev
, USB_PHY_TYPE_USB2
);
855 dwc
->usb3_phy
= devm_usb_get_phy(dev
, USB_PHY_TYPE_USB3
);
858 if (IS_ERR(dwc
->usb2_phy
)) {
859 ret
= PTR_ERR(dwc
->usb2_phy
);
860 if (ret
== -ENXIO
|| ret
== -ENODEV
) {
861 dwc
->usb2_phy
= NULL
;
862 } else if (ret
== -EPROBE_DEFER
) {
865 dev_err(dev
, "no usb2 phy configured\n");
870 if (IS_ERR(dwc
->usb3_phy
)) {
871 ret
= PTR_ERR(dwc
->usb3_phy
);
872 if (ret
== -ENXIO
|| ret
== -ENODEV
) {
873 dwc
->usb3_phy
= NULL
;
874 } else if (ret
== -EPROBE_DEFER
) {
877 dev_err(dev
, "no usb3 phy configured\n");
882 dwc
->usb2_generic_phy
= devm_phy_get(dev
, "usb2-phy");
883 if (IS_ERR(dwc
->usb2_generic_phy
)) {
884 ret
= PTR_ERR(dwc
->usb2_generic_phy
);
885 if (ret
== -ENOSYS
|| ret
== -ENODEV
) {
886 dwc
->usb2_generic_phy
= NULL
;
887 } else if (ret
== -EPROBE_DEFER
) {
890 dev_err(dev
, "no usb2 phy configured\n");
895 dwc
->usb3_generic_phy
= devm_phy_get(dev
, "usb3-phy");
896 if (IS_ERR(dwc
->usb3_generic_phy
)) {
897 ret
= PTR_ERR(dwc
->usb3_generic_phy
);
898 if (ret
== -ENOSYS
|| ret
== -ENODEV
) {
899 dwc
->usb3_generic_phy
= NULL
;
900 } else if (ret
== -EPROBE_DEFER
) {
903 dev_err(dev
, "no usb3 phy configured\n");
911 static int dwc3_core_init_mode(struct dwc3
*dwc
)
913 struct device
*dev
= dwc
->dev
;
916 switch (dwc
->dr_mode
) {
917 case USB_DR_MODE_PERIPHERAL
:
918 dwc
->current_dr_role
= DWC3_GCTL_PRTCAP_DEVICE
;
919 dwc3_set_prtcap(dwc
, DWC3_GCTL_PRTCAP_DEVICE
);
922 otg_set_vbus(dwc
->usb2_phy
->otg
, false);
923 phy_set_mode(dwc
->usb2_generic_phy
, PHY_MODE_USB_DEVICE
);
924 phy_set_mode(dwc
->usb3_generic_phy
, PHY_MODE_USB_DEVICE
);
926 ret
= dwc3_gadget_init(dwc
);
928 if (ret
!= -EPROBE_DEFER
)
929 dev_err(dev
, "failed to initialize gadget\n");
933 case USB_DR_MODE_HOST
:
934 dwc
->current_dr_role
= DWC3_GCTL_PRTCAP_HOST
;
935 dwc3_set_prtcap(dwc
, DWC3_GCTL_PRTCAP_HOST
);
938 otg_set_vbus(dwc
->usb2_phy
->otg
, true);
939 phy_set_mode(dwc
->usb2_generic_phy
, PHY_MODE_USB_HOST
);
940 phy_set_mode(dwc
->usb3_generic_phy
, PHY_MODE_USB_HOST
);
942 ret
= dwc3_host_init(dwc
);
944 if (ret
!= -EPROBE_DEFER
)
945 dev_err(dev
, "failed to initialize host\n");
949 case USB_DR_MODE_OTG
:
950 INIT_WORK(&dwc
->drd_work
, __dwc3_set_mode
);
951 ret
= dwc3_drd_init(dwc
);
953 if (ret
!= -EPROBE_DEFER
)
954 dev_err(dev
, "failed to initialize dual-role\n");
959 dev_err(dev
, "Unsupported mode of operation %d\n", dwc
->dr_mode
);
966 static void dwc3_core_exit_mode(struct dwc3
*dwc
)
968 switch (dwc
->dr_mode
) {
969 case USB_DR_MODE_PERIPHERAL
:
970 dwc3_gadget_exit(dwc
);
972 case USB_DR_MODE_HOST
:
975 case USB_DR_MODE_OTG
:
984 static void dwc3_get_properties(struct dwc3
*dwc
)
986 struct device
*dev
= dwc
->dev
;
987 u8 lpm_nyet_threshold
;
991 /* default to highest possible threshold */
992 lpm_nyet_threshold
= 0xff;
994 /* default to -3.5dB de-emphasis */
998 * default to assert utmi_sleep_n and use maximum allowed HIRD
999 * threshold value of 0b1100
1001 hird_threshold
= 12;
1003 dwc
->maximum_speed
= usb_get_maximum_speed(dev
);
1004 dwc
->dr_mode
= usb_get_dr_mode(dev
);
1005 dwc
->hsphy_mode
= of_usb_get_phy_mode(dev
->of_node
);
1007 dwc
->sysdev_is_parent
= device_property_read_bool(dev
,
1008 "linux,sysdev_is_parent");
1009 if (dwc
->sysdev_is_parent
)
1010 dwc
->sysdev
= dwc
->dev
->parent
;
1012 dwc
->sysdev
= dwc
->dev
;
1014 dwc
->has_lpm_erratum
= device_property_read_bool(dev
,
1015 "snps,has-lpm-erratum");
1016 device_property_read_u8(dev
, "snps,lpm-nyet-threshold",
1017 &lpm_nyet_threshold
);
1018 dwc
->is_utmi_l1_suspend
= device_property_read_bool(dev
,
1019 "snps,is-utmi-l1-suspend");
1020 device_property_read_u8(dev
, "snps,hird-threshold",
1022 dwc
->usb3_lpm_capable
= device_property_read_bool(dev
,
1023 "snps,usb3_lpm_capable");
1025 dwc
->disable_scramble_quirk
= device_property_read_bool(dev
,
1026 "snps,disable_scramble_quirk");
1027 dwc
->u2exit_lfps_quirk
= device_property_read_bool(dev
,
1028 "snps,u2exit_lfps_quirk");
1029 dwc
->u2ss_inp3_quirk
= device_property_read_bool(dev
,
1030 "snps,u2ss_inp3_quirk");
1031 dwc
->req_p1p2p3_quirk
= device_property_read_bool(dev
,
1032 "snps,req_p1p2p3_quirk");
1033 dwc
->del_p1p2p3_quirk
= device_property_read_bool(dev
,
1034 "snps,del_p1p2p3_quirk");
1035 dwc
->del_phy_power_chg_quirk
= device_property_read_bool(dev
,
1036 "snps,del_phy_power_chg_quirk");
1037 dwc
->lfps_filter_quirk
= device_property_read_bool(dev
,
1038 "snps,lfps_filter_quirk");
1039 dwc
->rx_detect_poll_quirk
= device_property_read_bool(dev
,
1040 "snps,rx_detect_poll_quirk");
1041 dwc
->dis_u3_susphy_quirk
= device_property_read_bool(dev
,
1042 "snps,dis_u3_susphy_quirk");
1043 dwc
->dis_u2_susphy_quirk
= device_property_read_bool(dev
,
1044 "snps,dis_u2_susphy_quirk");
1045 dwc
->dis_enblslpm_quirk
= device_property_read_bool(dev
,
1046 "snps,dis_enblslpm_quirk");
1047 dwc
->dis_rxdet_inp3_quirk
= device_property_read_bool(dev
,
1048 "snps,dis_rxdet_inp3_quirk");
1049 dwc
->dis_u2_freeclk_exists_quirk
= device_property_read_bool(dev
,
1050 "snps,dis-u2-freeclk-exists-quirk");
1051 dwc
->dis_del_phy_power_chg_quirk
= device_property_read_bool(dev
,
1052 "snps,dis-del-phy-power-chg-quirk");
1053 dwc
->dis_tx_ipgap_linecheck_quirk
= device_property_read_bool(dev
,
1054 "snps,dis-tx-ipgap-linecheck-quirk");
1056 dwc
->tx_de_emphasis_quirk
= device_property_read_bool(dev
,
1057 "snps,tx_de_emphasis_quirk");
1058 device_property_read_u8(dev
, "snps,tx_de_emphasis",
1060 device_property_read_string(dev
, "snps,hsphy_interface",
1061 &dwc
->hsphy_interface
);
1062 device_property_read_u32(dev
, "snps,quirk-frame-length-adjustment",
1065 dwc
->lpm_nyet_threshold
= lpm_nyet_threshold
;
1066 dwc
->tx_de_emphasis
= tx_de_emphasis
;
1068 dwc
->hird_threshold
= hird_threshold
1069 | (dwc
->is_utmi_l1_suspend
<< 4);
1071 dwc
->imod_interval
= 0;
1074 /* check whether the core supports IMOD */
1075 bool dwc3_has_imod(struct dwc3
*dwc
)
1077 return ((dwc3_is_usb3(dwc
) &&
1078 dwc
->revision
>= DWC3_REVISION_300A
) ||
1079 (dwc3_is_usb31(dwc
) &&
1080 dwc
->revision
>= DWC3_USB31_REVISION_120A
));
1083 static void dwc3_check_params(struct dwc3
*dwc
)
1085 struct device
*dev
= dwc
->dev
;
1087 /* Check for proper value of imod_interval */
1088 if (dwc
->imod_interval
&& !dwc3_has_imod(dwc
)) {
1089 dev_warn(dwc
->dev
, "Interrupt moderation not supported\n");
1090 dwc
->imod_interval
= 0;
1094 * Workaround for STAR 9000961433 which affects only version
1095 * 3.00a of the DWC_usb3 core. This prevents the controller
1096 * interrupt from being masked while handling events. IMOD
1097 * allows us to work around this issue. Enable it for the
1100 if (!dwc
->imod_interval
&&
1101 (dwc
->revision
== DWC3_REVISION_300A
))
1102 dwc
->imod_interval
= 1;
1104 /* Check the maximum_speed parameter */
1105 switch (dwc
->maximum_speed
) {
1107 case USB_SPEED_FULL
:
1108 case USB_SPEED_HIGH
:
1109 case USB_SPEED_SUPER
:
1110 case USB_SPEED_SUPER_PLUS
:
1113 dev_err(dev
, "invalid maximum_speed parameter %d\n",
1114 dwc
->maximum_speed
);
1116 case USB_SPEED_UNKNOWN
:
1117 /* default to superspeed */
1118 dwc
->maximum_speed
= USB_SPEED_SUPER
;
1121 * default to superspeed plus if we are capable.
1123 if (dwc3_is_usb31(dwc
) &&
1124 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc
->hwparams
.hwparams3
) ==
1125 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2
))
1126 dwc
->maximum_speed
= USB_SPEED_SUPER_PLUS
;
1132 static int dwc3_probe(struct platform_device
*pdev
)
1134 struct device
*dev
= &pdev
->dev
;
1135 struct resource
*res
;
1142 dwc
= devm_kzalloc(dev
, sizeof(*dwc
), GFP_KERNEL
);
1148 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1150 dev_err(dev
, "missing memory resource\n");
1154 dwc
->xhci_resources
[0].start
= res
->start
;
1155 dwc
->xhci_resources
[0].end
= dwc
->xhci_resources
[0].start
+
1157 dwc
->xhci_resources
[0].flags
= res
->flags
;
1158 dwc
->xhci_resources
[0].name
= res
->name
;
1160 res
->start
+= DWC3_GLOBALS_REGS_START
;
1163 * Request memory region but exclude xHCI regs,
1164 * since it will be requested by the xhci-plat driver.
1166 regs
= devm_ioremap_resource(dev
, res
);
1168 ret
= PTR_ERR(regs
);
1173 dwc
->regs_size
= resource_size(res
);
1175 dwc3_get_properties(dwc
);
1177 platform_set_drvdata(pdev
, dwc
);
1178 dwc3_cache_hwparams(dwc
);
1180 spin_lock_init(&dwc
->lock
);
1182 pm_runtime_set_active(dev
);
1183 pm_runtime_use_autosuspend(dev
);
1184 pm_runtime_set_autosuspend_delay(dev
, DWC3_DEFAULT_AUTOSUSPEND_DELAY
);
1185 pm_runtime_enable(dev
);
1186 ret
= pm_runtime_get_sync(dev
);
1190 pm_runtime_forbid(dev
);
1192 ret
= dwc3_alloc_event_buffers(dwc
, DWC3_EVENT_BUFFERS_SIZE
);
1194 dev_err(dwc
->dev
, "failed to allocate event buffers\n");
1199 ret
= dwc3_get_dr_mode(dwc
);
1203 ret
= dwc3_alloc_scratch_buffers(dwc
);
1207 ret
= dwc3_core_init(dwc
);
1209 dev_err(dev
, "failed to initialize core\n");
1213 dwc3_check_params(dwc
);
1215 ret
= dwc3_core_init_mode(dwc
);
1219 dwc3_debugfs_init(dwc
);
1220 pm_runtime_put(dev
);
1225 dwc3_event_buffers_cleanup(dwc
);
1228 dwc3_free_scratch_buffers(dwc
);
1231 dwc3_free_event_buffers(dwc
);
1232 dwc3_ulpi_exit(dwc
);
1235 pm_runtime_allow(&pdev
->dev
);
1238 pm_runtime_put_sync(&pdev
->dev
);
1239 pm_runtime_disable(&pdev
->dev
);
1243 * restore res->start back to its original value so that, in case the
1244 * probe is deferred, we don't end up getting error in request the
1245 * memory region the next time probe is called.
1247 res
->start
-= DWC3_GLOBALS_REGS_START
;
1252 static int dwc3_remove(struct platform_device
*pdev
)
1254 struct dwc3
*dwc
= platform_get_drvdata(pdev
);
1255 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1257 pm_runtime_get_sync(&pdev
->dev
);
1259 * restore res->start back to its original value so that, in case the
1260 * probe is deferred, we don't end up getting error in request the
1261 * memory region the next time probe is called.
1263 res
->start
-= DWC3_GLOBALS_REGS_START
;
1265 dwc3_debugfs_exit(dwc
);
1266 dwc3_core_exit_mode(dwc
);
1268 dwc3_core_exit(dwc
);
1269 dwc3_ulpi_exit(dwc
);
1271 pm_runtime_put_sync(&pdev
->dev
);
1272 pm_runtime_allow(&pdev
->dev
);
1273 pm_runtime_disable(&pdev
->dev
);
1275 dwc3_free_event_buffers(dwc
);
1276 dwc3_free_scratch_buffers(dwc
);
1282 static int dwc3_suspend_common(struct dwc3
*dwc
)
1284 unsigned long flags
;
1286 switch (dwc
->current_dr_role
) {
1287 case DWC3_GCTL_PRTCAP_DEVICE
:
1288 spin_lock_irqsave(&dwc
->lock
, flags
);
1289 dwc3_gadget_suspend(dwc
);
1290 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1291 dwc3_core_exit(dwc
);
1293 case DWC3_GCTL_PRTCAP_HOST
:
1302 static int dwc3_resume_common(struct dwc3
*dwc
)
1304 unsigned long flags
;
1307 switch (dwc
->current_dr_role
) {
1308 case DWC3_GCTL_PRTCAP_DEVICE
:
1309 ret
= dwc3_core_init(dwc
);
1313 spin_lock_irqsave(&dwc
->lock
, flags
);
1314 dwc3_gadget_resume(dwc
);
1315 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1317 case DWC3_GCTL_PRTCAP_HOST
:
1326 static int dwc3_runtime_checks(struct dwc3
*dwc
)
1328 switch (dwc
->current_dr_role
) {
1329 case USB_DR_MODE_PERIPHERAL
:
1330 case USB_DR_MODE_OTG
:
1334 case USB_DR_MODE_HOST
:
1343 static int dwc3_runtime_suspend(struct device
*dev
)
1345 struct dwc3
*dwc
= dev_get_drvdata(dev
);
1348 if (dwc3_runtime_checks(dwc
))
1351 ret
= dwc3_suspend_common(dwc
);
1355 device_init_wakeup(dev
, true);
1360 static int dwc3_runtime_resume(struct device
*dev
)
1362 struct dwc3
*dwc
= dev_get_drvdata(dev
);
1365 device_init_wakeup(dev
, false);
1367 ret
= dwc3_resume_common(dwc
);
1371 switch (dwc
->current_dr_role
) {
1372 case DWC3_GCTL_PRTCAP_DEVICE
:
1373 dwc3_gadget_process_pending_events(dwc
);
1375 case DWC3_GCTL_PRTCAP_HOST
:
1381 pm_runtime_mark_last_busy(dev
);
1386 static int dwc3_runtime_idle(struct device
*dev
)
1388 struct dwc3
*dwc
= dev_get_drvdata(dev
);
1390 switch (dwc
->current_dr_role
) {
1391 case DWC3_GCTL_PRTCAP_DEVICE
:
1392 if (dwc3_runtime_checks(dwc
))
1395 case DWC3_GCTL_PRTCAP_HOST
:
1401 pm_runtime_mark_last_busy(dev
);
1402 pm_runtime_autosuspend(dev
);
1406 #endif /* CONFIG_PM */
1408 #ifdef CONFIG_PM_SLEEP
1409 static int dwc3_suspend(struct device
*dev
)
1411 struct dwc3
*dwc
= dev_get_drvdata(dev
);
1414 ret
= dwc3_suspend_common(dwc
);
1418 pinctrl_pm_select_sleep_state(dev
);
1423 static int dwc3_resume(struct device
*dev
)
1425 struct dwc3
*dwc
= dev_get_drvdata(dev
);
1428 pinctrl_pm_select_default_state(dev
);
1430 ret
= dwc3_resume_common(dwc
);
1434 pm_runtime_disable(dev
);
1435 pm_runtime_set_active(dev
);
1436 pm_runtime_enable(dev
);
1440 #endif /* CONFIG_PM_SLEEP */
1442 static const struct dev_pm_ops dwc3_dev_pm_ops
= {
1443 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend
, dwc3_resume
)
1444 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend
, dwc3_runtime_resume
,
1449 static const struct of_device_id of_dwc3_match
[] = {
1451 .compatible
= "snps,dwc3"
1454 .compatible
= "synopsys,dwc3"
1458 MODULE_DEVICE_TABLE(of
, of_dwc3_match
);
1463 #define ACPI_ID_INTEL_BSW "808622B7"
1465 static const struct acpi_device_id dwc3_acpi_match
[] = {
1466 { ACPI_ID_INTEL_BSW
, 0 },
1469 MODULE_DEVICE_TABLE(acpi
, dwc3_acpi_match
);
1472 static struct platform_driver dwc3_driver
= {
1473 .probe
= dwc3_probe
,
1474 .remove
= dwc3_remove
,
1477 .of_match_table
= of_match_ptr(of_dwc3_match
),
1478 .acpi_match_table
= ACPI_PTR(dwc3_acpi_match
),
1479 .pm
= &dwc3_dev_pm_ops
,
1483 module_platform_driver(dwc3_driver
);
1485 MODULE_ALIAS("platform:dwc3");
1486 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1487 MODULE_LICENSE("GPL v2");
1488 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");