drivers/usb/dwc3/core.h

   1 /**
   2  * core.h - DesignWare USB3 DRD Core Header
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #ifndef __DRIVERS_USB_DWC3_CORE_H
  40 #define __DRIVERS_USB_DWC3_CORE_H
  41
  42 #include <linux/device.h>
  43 #include <linux/spinlock.h>
  44 #include <linux/ioport.h>
  45 #include <linux/list.h>
  46 #include <linux/dma-mapping.h>
  47 #include <linux/mm.h>
  48 #include <linux/debugfs.h>
  49
  50 #include <linux/usb/ch9.h>
  51 #include <linux/usb/gadget.h>
  52
  53 /* Global constants */
  54 #define DWC3_ENDPOINTS_NUM      32
  55 #define DWC3_XHCI_RESOURCES_NUM 2
  56
  57 #define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE
  58 #define DWC3_EVENT_TYPE_MASK    0xfe
  59
  60 #define DWC3_EVENT_TYPE_DEV     0
  61 #define DWC3_EVENT_TYPE_CARKIT  3
  62 #define DWC3_EVENT_TYPE_I2C     4
  63
  64 #define DWC3_DEVICE_EVENT_DISCONNECT            0
  65 #define DWC3_DEVICE_EVENT_RESET                 1
  66 #define DWC3_DEVICE_EVENT_CONNECT_DONE          2
  67 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE    3
  68 #define DWC3_DEVICE_EVENT_WAKEUP                4
  69 #define DWC3_DEVICE_EVENT_EOPF                  6
  70 #define DWC3_DEVICE_EVENT_SOF                   7
  71 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR         9
  72 #define DWC3_DEVICE_EVENT_CMD_CMPL              10
  73 #define DWC3_DEVICE_EVENT_OVERFLOW              11
  74
  75 #define DWC3_GEVNTCOUNT_MASK    0xfffc
  76 #define DWC3_GSNPSID_MASK       0xffff0000
  77 #define DWC3_GSNPSREV_MASK      0xffff
  78
  79 /* DWC3 registers memory space boundries */
  80 #define DWC3_XHCI_REGS_START            0x0
  81 #define DWC3_XHCI_REGS_END              0x7fff
  82 #define DWC3_GLOBALS_REGS_START         0xc100
  83 #define DWC3_GLOBALS_REGS_END           0xc6ff
  84 #define DWC3_DEVICE_REGS_START          0xc700
  85 #define DWC3_DEVICE_REGS_END            0xcbff
  86 #define DWC3_OTG_REGS_START             0xcc00
  87 #define DWC3_OTG_REGS_END               0xccff
  88
  89 /* Global Registers */
  90 #define DWC3_GSBUSCFG0          0xc100
  91 #define DWC3_GSBUSCFG1          0xc104
  92 #define DWC3_GTXTHRCFG          0xc108
  93 #define DWC3_GRXTHRCFG          0xc10c
  94 #define DWC3_GCTL               0xc110
  95 #define DWC3_GEVTEN             0xc114
  96 #define DWC3_GSTS               0xc118
  97 #define DWC3_GSNPSID            0xc120
  98 #define DWC3_GGPIO              0xc124
  99 #define DWC3_GUID               0xc128
 100 #define DWC3_GUCTL              0xc12c
 101 #define DWC3_GBUSERRADDR0       0xc130
 102 #define DWC3_GBUSERRADDR1       0xc134
 103 #define DWC3_GPRTBIMAP0         0xc138
 104 #define DWC3_GPRTBIMAP1         0xc13c
 105 #define DWC3_GHWPARAMS0         0xc140
 106 #define DWC3_GHWPARAMS1         0xc144
 107 #define DWC3_GHWPARAMS2         0xc148
 108 #define DWC3_GHWPARAMS3         0xc14c
 109 #define DWC3_GHWPARAMS4         0xc150
 110 #define DWC3_GHWPARAMS5         0xc154
 111 #define DWC3_GHWPARAMS6         0xc158
 112 #define DWC3_GHWPARAMS7         0xc15c
 113 #define DWC3_GDBGFIFOSPACE      0xc160
 114 #define DWC3_GDBGLTSSM          0xc164
 115 #define DWC3_GPRTBIMAP_HS0      0xc180
 116 #define DWC3_GPRTBIMAP_HS1      0xc184
 117 #define DWC3_GPRTBIMAP_FS0      0xc188
 118 #define DWC3_GPRTBIMAP_FS1      0xc18c
 119
 120 #define DWC3_GUSB2PHYCFG(n)     (0xc200 + (n * 0x04))
 121 #define DWC3_GUSB2I2CCTL(n)     (0xc240 + (n * 0x04))
 122
 123 #define DWC3_GUSB2PHYACC(n)     (0xc280 + (n * 0x04))
 124
 125 #define DWC3_GUSB3PIPECTL(n)    (0xc2c0 + (n * 0x04))
 126
 127 #define DWC3_GTXFIFOSIZ(n)      (0xc300 + (n * 0x04))
 128 #define DWC3_GRXFIFOSIZ(n)      (0xc380 + (n * 0x04))
 129
 130 #define DWC3_GEVNTADRLO(n)      (0xc400 + (n * 0x10))
 131 #define DWC3_GEVNTADRHI(n)      (0xc404 + (n * 0x10))
 132 #define DWC3_GEVNTSIZ(n)        (0xc408 + (n * 0x10))
 133 #define DWC3_GEVNTCOUNT(n)      (0xc40c + (n * 0x10))
 134
 135 #define DWC3_GHWPARAMS8         0xc600
 136
 137 /* Device Registers */
 138 #define DWC3_DCFG               0xc700
 139 #define DWC3_DCTL               0xc704
 140 #define DWC3_DEVTEN             0xc708
 141 #define DWC3_DSTS               0xc70c
 142 #define DWC3_DGCMDPAR           0xc710
 143 #define DWC3_DGCMD              0xc714
 144 #define DWC3_DALEPENA           0xc720
 145 #define DWC3_DEPCMDPAR2(n)      (0xc800 + (n * 0x10))
 146 #define DWC3_DEPCMDPAR1(n)      (0xc804 + (n * 0x10))
 147 #define DWC3_DEPCMDPAR0(n)      (0xc808 + (n * 0x10))
 148 #define DWC3_DEPCMD(n)          (0xc80c + (n * 0x10))
 149
 150 /* OTG Registers */
 151 #define DWC3_OCFG               0xcc00
 152 #define DWC3_OCTL               0xcc04
 153 #define DWC3_OEVTEN             0xcc08
 154 #define DWC3_OSTS               0xcc0C
 155
 156 /* Bit fields */
 157
 158 /* Global Configuration Register */
 159 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
 160 #define DWC3_GCTL_U2RSTECN      (1 << 16)
 161 #define DWC3_GCTL_RAMCLKSEL(x)  (((x) & DWC3_GCTL_CLK_MASK) << 6)
 162 #define DWC3_GCTL_CLK_BUS       (0)
 163 #define DWC3_GCTL_CLK_PIPE      (1)
 164 #define DWC3_GCTL_CLK_PIPEHALF  (2)
 165 #define DWC3_GCTL_CLK_MASK      (3)
 166
 167 #define DWC3_GCTL_PRTCAP(n)     (((n) & (3 << 12)) >> 12)
 168 #define DWC3_GCTL_PRTCAPDIR(n)  ((n) << 12)
 169 #define DWC3_GCTL_PRTCAP_HOST   1
 170 #define DWC3_GCTL_PRTCAP_DEVICE 2
 171 #define DWC3_GCTL_PRTCAP_OTG    3
 172
 173 #define DWC3_GCTL_CORESOFTRESET (1 << 11)
 174 #define DWC3_GCTL_SCALEDOWN(n)  ((n) << 4)
 175 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
 176 #define DWC3_GCTL_DISSCRAMBLE   (1 << 3)
 177 #define DWC3_GCTL_DSBLCLKGTNG   (1 << 0)
 178
 179 /* Global USB2 PHY Configuration Register */
 180 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
 181 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
 182
 183 /* Global USB3 PIPE Control Register */
 184 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
 185 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
 186
 187 /* Global TX Fifo Size Register */
 188 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
 189 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
 190
 191 /* Global HWPARAMS1 Register */
 192 #define DWC3_GHWPARAMS1_EN_PWROPT(n)    (((n) & (3 << 24)) >> 24)
 193 #define DWC3_GHWPARAMS1_EN_PWROPT_NO    0
 194 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK   1
 195
 196 /* Device Configuration Register */
 197 #define DWC3_DCFG_LPM_CAP       (1 << 22)
 198 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
 199 #define DWC3_DCFG_DEVADDR_MASK  DWC3_DCFG_DEVADDR(0x7f)
 200
 201 #define DWC3_DCFG_SPEED_MASK    (7 << 0)
 202 #define DWC3_DCFG_SUPERSPEED    (4 << 0)
 203 #define DWC3_DCFG_HIGHSPEED     (0 << 0)
 204 #define DWC3_DCFG_FULLSPEED2    (1 << 0)
 205 #define DWC3_DCFG_LOWSPEED      (2 << 0)
 206 #define DWC3_DCFG_FULLSPEED1    (3 << 0)
 207
 208 /* Device Control Register */
 209 #define DWC3_DCTL_RUN_STOP      (1 << 31)
 210 #define DWC3_DCTL_CSFTRST       (1 << 30)
 211 #define DWC3_DCTL_LSFTRST       (1 << 29)
 212
 213 #define DWC3_DCTL_HIRD_THRES_MASK       (0x1f << 24)
 214 #define DWC3_DCTL_HIRD_THRES(n) (((n) & DWC3_DCTL_HIRD_THRES_MASK) >> 24)
 215
 216 #define DWC3_DCTL_APPL1RES      (1 << 23)
 217
 218 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
 219 #define DWC3_DCTL_TRGTULST(n)   ((n) << 17)
 220
 221 #define DWC3_DCTL_TRGTULST_U2   (DWC3_DCTL_TRGTULST(2))
 222 #define DWC3_DCTL_TRGTULST_U3   (DWC3_DCTL_TRGTULST(3))
 223 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
 224 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
 225 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
 226
 227 #define DWC3_DCTL_INITU2ENA     (1 << 12)
 228 #define DWC3_DCTL_ACCEPTU2ENA   (1 << 11)
 229 #define DWC3_DCTL_INITU1ENA     (1 << 10)
 230 #define DWC3_DCTL_ACCEPTU1ENA   (1 << 9)
 231 #define DWC3_DCTL_TSTCTRL_MASK  (0xf << 1)
 232
 233 #define DWC3_DCTL_ULSTCHNGREQ_MASK      (0x0f << 5)
 234 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
 235
 236 #define DWC3_DCTL_ULSTCHNG_NO_ACTION    (DWC3_DCTL_ULSTCHNGREQ(0))
 237 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED  (DWC3_DCTL_ULSTCHNGREQ(4))
 238 #define DWC3_DCTL_ULSTCHNG_RX_DETECT    (DWC3_DCTL_ULSTCHNGREQ(5))
 239 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE  (DWC3_DCTL_ULSTCHNGREQ(6))
 240 #define DWC3_DCTL_ULSTCHNG_RECOVERY     (DWC3_DCTL_ULSTCHNGREQ(8))
 241 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE   (DWC3_DCTL_ULSTCHNGREQ(10))
 242 #define DWC3_DCTL_ULSTCHNG_LOOPBACK     (DWC3_DCTL_ULSTCHNGREQ(11))
 243
 244 /* Device Event Enable Register */
 245 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN   (1 << 12)
 246 #define DWC3_DEVTEN_EVNTOVERFLOWEN      (1 << 11)
 247 #define DWC3_DEVTEN_CMDCMPLTEN          (1 << 10)
 248 #define DWC3_DEVTEN_ERRTICERREN         (1 << 9)
 249 #define DWC3_DEVTEN_SOFEN               (1 << 7)
 250 #define DWC3_DEVTEN_EOPFEN              (1 << 6)
 251 #define DWC3_DEVTEN_WKUPEVTEN           (1 << 4)
 252 #define DWC3_DEVTEN_ULSTCNGEN           (1 << 3)
 253 #define DWC3_DEVTEN_CONNECTDONEEN       (1 << 2)
 254 #define DWC3_DEVTEN_USBRSTEN            (1 << 1)
 255 #define DWC3_DEVTEN_DISCONNEVTEN        (1 << 0)
 256
 257 /* Device Status Register */
 258 #define DWC3_DSTS_PWRUPREQ              (1 << 24)
 259 #define DWC3_DSTS_COREIDLE              (1 << 23)
 260 #define DWC3_DSTS_DEVCTRLHLT            (1 << 22)
 261
 262 #define DWC3_DSTS_USBLNKST_MASK         (0x0f << 18)
 263 #define DWC3_DSTS_USBLNKST(n)           (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
 264
 265 #define DWC3_DSTS_RXFIFOEMPTY           (1 << 17)
 266
 267 #define DWC3_DSTS_SOFFN_MASK            (0x3ff << 3)
 268 #define DWC3_DSTS_SOFFN(n)              (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
 269
 270 #define DWC3_DSTS_CONNECTSPD            (7 << 0)
 271
 272 #define DWC3_DSTS_SUPERSPEED            (4 << 0)
 273 #define DWC3_DSTS_HIGHSPEED             (0 << 0)
 274 #define DWC3_DSTS_FULLSPEED2            (1 << 0)
 275 #define DWC3_DSTS_LOWSPEED              (2 << 0)
 276 #define DWC3_DSTS_FULLSPEED1            (3 << 0)
 277
 278 /* Device Generic Command Register */
 279 #define DWC3_DGCMD_SET_LMP              0x01
 280 #define DWC3_DGCMD_SET_PERIODIC_PAR     0x02
 281 #define DWC3_DGCMD_XMIT_FUNCTION        0x03
 282 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH  0x09
 283 #define DWC3_DGCMD_ALL_FIFO_FLUSH       0x0a
 284 #define DWC3_DGCMD_SET_ENDPOINT_NRDY    0x0c
 285 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
 286
 287 #define DWC3_DGCMD_STATUS(n)            (((n) >> 15) & 1)
 288 #define DWC3_DGCMD_CMDACT               (1 << 10)
 289
 290 /* Device Endpoint Command Register */
 291 #define DWC3_DEPCMD_PARAM_SHIFT         16
 292 #define DWC3_DEPCMD_PARAM(x)            ((x) << DWC3_DEPCMD_PARAM_SHIFT)
 293 #define DWC3_DEPCMD_GET_RSC_IDX(x)     (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
 294 #define DWC3_DEPCMD_STATUS(x)           (((x) >> 15) & 1)
 295 #define DWC3_DEPCMD_HIPRI_FORCERM       (1 << 11)
 296 #define DWC3_DEPCMD_CMDACT              (1 << 10)
 297 #define DWC3_DEPCMD_CMDIOC              (1 << 8)
 298
 299 #define DWC3_DEPCMD_DEPSTARTCFG         (0x09 << 0)
 300 #define DWC3_DEPCMD_ENDTRANSFER         (0x08 << 0)
 301 #define DWC3_DEPCMD_UPDATETRANSFER      (0x07 << 0)
 302 #define DWC3_DEPCMD_STARTTRANSFER       (0x06 << 0)
 303 #define DWC3_DEPCMD_CLEARSTALL          (0x05 << 0)
 304 #define DWC3_DEPCMD_SETSTALL            (0x04 << 0)
 305 #define DWC3_DEPCMD_GETSEQNUMBER        (0x03 << 0)
 306 #define DWC3_DEPCMD_SETTRANSFRESOURCE   (0x02 << 0)
 307 #define DWC3_DEPCMD_SETEPCONFIG         (0x01 << 0)
 308
 309 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
 310 #define DWC3_DALEPENA_EP(n)             (1 << n)
 311
 312 #define DWC3_DEPCMD_TYPE_CONTROL        0
 313 #define DWC3_DEPCMD_TYPE_ISOC           1
 314 #define DWC3_DEPCMD_TYPE_BULK           2
 315 #define DWC3_DEPCMD_TYPE_INTR           3
 316
 317 /* Structures */
 318
 319 struct dwc3_trb;
 320
 321 /**
 322  * struct dwc3_event_buffer - Software event buffer representation
 323  * @list: a list of event buffers
 324  * @buf: _THE_ buffer
 325  * @length: size of this buffer
 326  * @dma: dma_addr_t
 327  * @dwc: pointer to DWC controller
 328  */
 329 struct dwc3_event_buffer {
 330         void                    *buf;
 331         unsigned                length;
 332         unsigned int            lpos;
 333
 334         dma_addr_t              dma;
 335
 336         struct dwc3             *dwc;
 337 };
 338
 339 #define DWC3_EP_FLAG_STALLED    (1 << 0)
 340 #define DWC3_EP_FLAG_WEDGED     (1 << 1)
 341
 342 #define DWC3_EP_DIRECTION_TX    true
 343 #define DWC3_EP_DIRECTION_RX    false
 344
 345 #define DWC3_TRB_NUM            32
 346 #define DWC3_TRB_MASK           (DWC3_TRB_NUM - 1)
 347
 348 /**
 349  * struct dwc3_ep - device side endpoint representation
 350  * @endpoint: usb endpoint
 351  * @request_list: list of requests for this endpoint
 352  * @req_queued: list of requests on this ep which have TRBs setup
 353  * @trb_pool: array of transaction buffers
 354  * @trb_pool_dma: dma address of @trb_pool
 355  * @free_slot: next slot which is going to be used
 356  * @busy_slot: first slot which is owned by HW
 357  * @desc: usb_endpoint_descriptor pointer
 358  * @dwc: pointer to DWC controller
 359  * @flags: endpoint flags (wedged, stalled, ...)
 360  * @current_trb: index of current used trb
 361  * @number: endpoint number (1 - 15)
 362  * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
 363  * @res_trans_idx: Resource transfer index
 364  * @interval: the intervall on which the ISOC transfer is started
 365  * @name: a human readable name e.g. ep1out-bulk
 366  * @direction: true for TX, false for RX
 367  * @stream_capable: true when streams are enabled
 368  */
 369 struct dwc3_ep {
 370         struct usb_ep           endpoint;
 371         struct list_head        request_list;
 372         struct list_head        req_queued;
 373
 374         struct dwc3_trb         *trb_pool;
 375         dma_addr_t              trb_pool_dma;
 376         u32                     free_slot;
 377         u32                     busy_slot;
 378         const struct usb_endpoint_descriptor *desc;
 379         const struct usb_ss_ep_comp_descriptor *comp_desc;
 380         struct dwc3             *dwc;
 381
 382         unsigned                flags;
 383 #define DWC3_EP_ENABLED         (1 << 0)
 384 #define DWC3_EP_STALL           (1 << 1)
 385 #define DWC3_EP_WEDGE           (1 << 2)
 386 #define DWC3_EP_BUSY            (1 << 4)
 387 #define DWC3_EP_PENDING_REQUEST (1 << 5)
 388
 389         /* This last one is specific to EP0 */
 390 #define DWC3_EP0_DIR_IN         (1 << 31)
 391
 392         unsigned                current_trb;
 393
 394         u8                      number;
 395         u8                      type;
 396         u8                      res_trans_idx;
 397         u32                     interval;
 398
 399         char                    name[20];
 400
 401         unsigned                direction:1;
 402         unsigned                stream_capable:1;
 403 };
 404
 405 enum dwc3_phy {
 406         DWC3_PHY_UNKNOWN = 0,
 407         DWC3_PHY_USB3,
 408         DWC3_PHY_USB2,
 409 };
 410
 411 enum dwc3_ep0_next {
 412         DWC3_EP0_UNKNOWN = 0,
 413         DWC3_EP0_COMPLETE,
 414         DWC3_EP0_NRDY_SETUP,
 415         DWC3_EP0_NRDY_DATA,
 416         DWC3_EP0_NRDY_STATUS,
 417 };
 418
 419 enum dwc3_ep0_state {
 420         EP0_UNCONNECTED         = 0,
 421         EP0_SETUP_PHASE,
 422         EP0_DATA_PHASE,
 423         EP0_STATUS_PHASE,
 424 };
 425
 426 enum dwc3_link_state {
 427         /* In SuperSpeed */
 428         DWC3_LINK_STATE_U0              = 0x00, /* in HS, means ON */
 429         DWC3_LINK_STATE_U1              = 0x01,
 430         DWC3_LINK_STATE_U2              = 0x02, /* in HS, means SLEEP */
 431         DWC3_LINK_STATE_U3              = 0x03, /* in HS, means SUSPEND */
 432         DWC3_LINK_STATE_SS_DIS          = 0x04,
 433         DWC3_LINK_STATE_RX_DET          = 0x05, /* in HS, means Early Suspend */
 434         DWC3_LINK_STATE_SS_INACT        = 0x06,
 435         DWC3_LINK_STATE_POLL            = 0x07,
 436         DWC3_LINK_STATE_RECOV           = 0x08,
 437         DWC3_LINK_STATE_HRESET          = 0x09,
 438         DWC3_LINK_STATE_CMPLY           = 0x0a,
 439         DWC3_LINK_STATE_LPBK            = 0x0b,
 440         DWC3_LINK_STATE_MASK            = 0x0f,
 441 };
 442
 443 enum dwc3_device_state {
 444         DWC3_DEFAULT_STATE,
 445         DWC3_ADDRESS_STATE,
 446         DWC3_CONFIGURED_STATE,
 447 };
 448
 449 /* TRB Length, PCM and Status */
 450 #define DWC3_TRB_SIZE_MASK      (0x00ffffff)
 451 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
 452 #define DWC3_TRB_SIZE_PCM1(n)   (((n) & 0x03) << 24)
 453 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28) >> 28))
 454
 455 #define DWC3_TRBSTS_OK                  0
 456 #define DWC3_TRBSTS_MISSED_ISOC         1
 457 #define DWC3_TRBSTS_SETUP_PENDING       2
 458
 459 /* TRB Control */
 460 #define DWC3_TRB_CTRL_HWO               (1 << 0)
 461 #define DWC3_TRB_CTRL_LST               (1 << 1)
 462 #define DWC3_TRB_CTRL_CHN               (1 << 2)
 463 #define DWC3_TRB_CTRL_CSP               (1 << 3)
 464 #define DWC3_TRB_CTRL_TRBCTL(n)         (((n) & 0x3f) << 4)
 465 #define DWC3_TRB_CTRL_ISP_IMI           (1 << 10)
 466 #define DWC3_TRB_CTRL_IOC               (1 << 11)
 467 #define DWC3_TRB_CTRL_SID_SOFN(n)       (((n) & 0xffff) << 14)
 468
 469 #define DWC3_TRBCTL_NORMAL              DWC3_TRB_CTRL_TRBCTL(1)
 470 #define DWC3_TRBCTL_CONTROL_SETUP       DWC3_TRB_CTRL_TRBCTL(2)
 471 #define DWC3_TRBCTL_CONTROL_STATUS2     DWC3_TRB_CTRL_TRBCTL(3)
 472 #define DWC3_TRBCTL_CONTROL_STATUS3     DWC3_TRB_CTRL_TRBCTL(4)
 473 #define DWC3_TRBCTL_CONTROL_DATA        DWC3_TRB_CTRL_TRBCTL(5)
 474 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST   DWC3_TRB_CTRL_TRBCTL(6)
 475 #define DWC3_TRBCTL_ISOCHRONOUS         DWC3_TRB_CTRL_TRBCTL(7)
 476 #define DWC3_TRBCTL_LINK_TRB            DWC3_TRB_CTRL_TRBCTL(8)
 477
 478 /**
 479  * struct dwc3_trb - transfer request block (hw format)
 480  * @bpl: DW0-3
 481  * @bph: DW4-7
 482  * @size: DW8-B
 483  * @trl: DWC-F
 484  */
 485 struct dwc3_trb {
 486         u32             bpl;
 487         u32             bph;
 488         u32             size;
 489         u32             ctrl;
 490 } __packed;
 491
 492 /**
 493  * dwc3_hwparams - copy of HWPARAMS registers
 494  * @hwparams0 - GHWPARAMS0
 495  * @hwparams1 - GHWPARAMS1
 496  * @hwparams2 - GHWPARAMS2
 497  * @hwparams3 - GHWPARAMS3
 498  * @hwparams4 - GHWPARAMS4
 499  * @hwparams5 - GHWPARAMS5
 500  * @hwparams6 - GHWPARAMS6
 501  * @hwparams7 - GHWPARAMS7
 502  * @hwparams8 - GHWPARAMS8
 503  */
 504 struct dwc3_hwparams {
 505         u32     hwparams0;
 506         u32     hwparams1;
 507         u32     hwparams2;
 508         u32     hwparams3;
 509         u32     hwparams4;
 510         u32     hwparams5;
 511         u32     hwparams6;
 512         u32     hwparams7;
 513         u32     hwparams8;
 514 };
 515
 516 /* HWPARAMS0 */
 517 #define DWC3_MODE(n)            ((n) & 0x7)
 518
 519 #define DWC3_MODE_DEVICE        0
 520 #define DWC3_MODE_HOST          1
 521 #define DWC3_MODE_DRD           2
 522 #define DWC3_MODE_HUB           3
 523
 524 #define DWC3_MDWIDTH(n)         (((n) & 0xff00) >> 8)
 525
 526 /* HWPARAMS1 */
 527 #define DWC3_NUM_INT(n)         (((n) & (0x3f << 15)) >> 15)
 528
 529 /* HWPARAMS7 */
 530 #define DWC3_RAM1_DEPTH(n)      ((n) & 0xffff)
 531
 532 struct dwc3_request {
 533         struct usb_request      request;
 534         struct list_head        list;
 535         struct dwc3_ep          *dep;
 536
 537         u8                      epnum;
 538         struct dwc3_trb         *trb;
 539         dma_addr_t              trb_dma;
 540
 541         unsigned                direction:1;
 542         unsigned                mapped:1;
 543         unsigned                queued:1;
 544 };
 545
 546 /**
 547  * struct dwc3 - representation of our controller
 548  * @ctrl_req: usb control request which is used for ep0
 549  * @ep0_trb: trb which is used for the ctrl_req
 550  * @ep0_bounce: bounce buffer for ep0
 551  * @setup_buf: used while precessing STD USB requests
 552  * @ctrl_req_addr: dma address of ctrl_req
 553  * @ep0_trb: dma address of ep0_trb
 554  * @ep0_usb_req: dummy req used while handling STD USB requests
 555  * @ep0_bounce_addr: dma address of ep0_bounce
 556  * @lock: for synchronizing
 557  * @dev: pointer to our struct device
 558  * @xhci: pointer to our xHCI child
 559  * @event_buffer_list: a list of event buffers
 560  * @gadget: device side representation of the peripheral controller
 561  * @gadget_driver: pointer to the gadget driver
 562  * @regs: base address for our registers
 563  * @regs_size: address space size
 564  * @irq: IRQ number
 565  * @num_event_buffers: calculated number of event buffers
 566  * @u1u2: only used on revisions <1.83a for workaround
 567  * @maximum_speed: maximum speed requested (mainly for testing purposes)
 568  * @revision: revision register contents
 569  * @mode: mode of operation
 570  * @is_selfpowered: true when we are selfpowered
 571  * @three_stage_setup: set if we perform a three phase setup
 572  * @ep0_bounced: true when we used bounce buffer
 573  * @ep0_expect_in: true when we expect a DATA IN transfer
 574  * @start_config_issued: true when StartConfig command has been issued
 575  * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
 576  * @needs_fifo_resize: not all users might want fifo resizing, flag it
 577  * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes.
 578  * @ep0_next_event: hold the next expected event
 579  * @ep0state: state of endpoint zero
 580  * @link_state: link state
 581  * @speed: device speed (super, high, full, low)
 582  * @mem: points to start of memory which is used for this struct.
 583  * @hwparams: copy of hwparams registers
 584  * @root: debugfs root folder pointer
 585  */
 586 struct dwc3 {
 587         struct usb_ctrlrequest  *ctrl_req;
 588         struct dwc3_trb         *ep0_trb;
 589         void                    *ep0_bounce;
 590         u8                      *setup_buf;
 591         dma_addr_t              ctrl_req_addr;
 592         dma_addr_t              ep0_trb_addr;
 593         dma_addr_t              ep0_bounce_addr;
 594         struct dwc3_request     ep0_usb_req;
 595         /* device lock */
 596         spinlock_t              lock;
 597         struct device           *dev;
 598
 599         struct platform_device  *xhci;
 600         struct resource         xhci_resources[DWC3_XHCI_RESOURCES_NUM];
 601
 602         struct dwc3_event_buffer **ev_buffs;
 603         struct dwc3_ep          *eps[DWC3_ENDPOINTS_NUM];
 604
 605         struct usb_gadget       gadget;
 606         struct usb_gadget_driver *gadget_driver;
 607
 608         void __iomem            *regs;
 609         size_t                  regs_size;
 610
 611         u32                     num_event_buffers;
 612         u32                     u1u2;
 613         u32                     maximum_speed;
 614         u32                     revision;
 615         u32                     mode;
 616
 617 #define DWC3_REVISION_173A      0x5533173a
 618 #define DWC3_REVISION_175A      0x5533175a
 619 #define DWC3_REVISION_180A      0x5533180a
 620 #define DWC3_REVISION_183A      0x5533183a
 621 #define DWC3_REVISION_185A      0x5533185a
 622 #define DWC3_REVISION_188A      0x5533188a
 623 #define DWC3_REVISION_190A      0x5533190a
 624 #define DWC3_REVISION_200A      0x5533200a
 625 #define DWC3_REVISION_202A      0x5533202a
 626 #define DWC3_REVISION_210A      0x5533210a
 627 #define DWC3_REVISION_220A      0x5533220a
 628
 629         unsigned                is_selfpowered:1;
 630         unsigned                three_stage_setup:1;
 631         unsigned                ep0_bounced:1;
 632         unsigned                ep0_expect_in:1;
 633         unsigned                start_config_issued:1;
 634         unsigned                setup_packet_pending:1;
 635         unsigned                delayed_status:1;
 636         unsigned                needs_fifo_resize:1;
 637         unsigned                resize_fifos:1;
 638
 639         enum dwc3_ep0_next      ep0_next_event;
 640         enum dwc3_ep0_state     ep0state;
 641         enum dwc3_link_state    link_state;
 642         enum dwc3_device_state  dev_state;
 643
 644         u8                      speed;
 645         void                    *mem;
 646
 647         struct dwc3_hwparams    hwparams;
 648         struct dentry           *root;
 649
 650         u8                      test_mode;
 651         u8                      test_mode_nr;
 652 };
 653
 654 /* -------------------------------------------------------------------------- */
 655
 656 /* -------------------------------------------------------------------------- */
 657
 658 struct dwc3_event_type {
 659         u32     is_devspec:1;
 660         u32     type:6;
 661         u32     reserved8_31:25;
 662 } __packed;
 663
 664 #define DWC3_DEPEVT_XFERCOMPLETE        0x01
 665 #define DWC3_DEPEVT_XFERINPROGRESS      0x02
 666 #define DWC3_DEPEVT_XFERNOTREADY        0x03
 667 #define DWC3_DEPEVT_RXTXFIFOEVT         0x04
 668 #define DWC3_DEPEVT_STREAMEVT           0x06
 669 #define DWC3_DEPEVT_EPCMDCMPLT          0x07
 670
 671 /**
 672  * struct dwc3_event_depvt - Device Endpoint Events
 673  * @one_bit: indicates this is an endpoint event (not used)
 674  * @endpoint_number: number of the endpoint
 675  * @endpoint_event: The event we have:
 676  *      0x00    - Reserved
 677  *      0x01    - XferComplete
 678  *      0x02    - XferInProgress
 679  *      0x03    - XferNotReady
 680  *      0x04    - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
 681  *      0x05    - Reserved
 682  *      0x06    - StreamEvt
 683  *      0x07    - EPCmdCmplt
 684  * @reserved11_10: Reserved, don't use.
 685  * @status: Indicates the status of the event. Refer to databook for
 686  *      more information.
 687  * @parameters: Parameters of the current event. Refer to databook for
 688  *      more information.
 689  */
 690 struct dwc3_event_depevt {
 691         u32     one_bit:1;
 692         u32     endpoint_number:5;
 693         u32     endpoint_event:4;
 694         u32     reserved11_10:2;
 695         u32     status:4;
 696
 697 /* Within XferNotReady */
 698 #define DEPEVT_STATUS_TRANSFER_ACTIVE   (1 << 3)
 699
 700 /* Within XferComplete */
 701 #define DEPEVT_STATUS_BUSERR    (1 << 0)
 702 #define DEPEVT_STATUS_SHORT     (1 << 1)
 703 #define DEPEVT_STATUS_IOC       (1 << 2)
 704 #define DEPEVT_STATUS_LST       (1 << 3)
 705
 706 /* Stream event only */
 707 #define DEPEVT_STREAMEVT_FOUND          1
 708 #define DEPEVT_STREAMEVT_NOTFOUND       2
 709
 710 /* Control-only Status */
 711 #define DEPEVT_STATUS_CONTROL_SETUP     0
 712 #define DEPEVT_STATUS_CONTROL_DATA      1
 713 #define DEPEVT_STATUS_CONTROL_STATUS    2
 714
 715         u32     parameters:16;
 716 } __packed;
 717
 718 /**
 719  * struct dwc3_event_devt - Device Events
 720  * @one_bit: indicates this is a non-endpoint event (not used)
 721  * @device_event: indicates it's a device event. Should read as 0x00
 722  * @type: indicates the type of device event.
 723  *      0       - DisconnEvt
 724  *      1       - USBRst
 725  *      2       - ConnectDone
 726  *      3       - ULStChng
 727  *      4       - WkUpEvt
 728  *      5       - Reserved
 729  *      6       - EOPF
 730  *      7       - SOF
 731  *      8       - Reserved
 732  *      9       - ErrticErr
 733  *      10      - CmdCmplt
 734  *      11      - EvntOverflow
 735  *      12      - VndrDevTstRcved
 736  * @reserved15_12: Reserved, not used
 737  * @event_info: Information about this event
 738  * @reserved31_24: Reserved, not used
 739  */
 740 struct dwc3_event_devt {
 741         u32     one_bit:1;
 742         u32     device_event:7;
 743         u32     type:4;
 744         u32     reserved15_12:4;
 745         u32     event_info:8;
 746         u32     reserved31_24:8;
 747 } __packed;
 748
 749 /**
 750  * struct dwc3_event_gevt - Other Core Events
 751  * @one_bit: indicates this is a non-endpoint event (not used)
 752  * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
 753  * @phy_port_number: self-explanatory
 754  * @reserved31_12: Reserved, not used.
 755  */
 756 struct dwc3_event_gevt {
 757         u32     one_bit:1;
 758         u32     device_event:7;
 759         u32     phy_port_number:4;
 760         u32     reserved31_12:20;
 761 } __packed;
 762
 763 /**
 764  * union dwc3_event - representation of Event Buffer contents
 765  * @raw: raw 32-bit event
 766  * @type: the type of the event
 767  * @depevt: Device Endpoint Event
 768  * @devt: Device Event
 769  * @gevt: Global Event
 770  */
 771 union dwc3_event {
 772         u32                             raw;
 773         struct dwc3_event_type          type;
 774         struct dwc3_event_depevt        depevt;
 775         struct dwc3_event_devt          devt;
 776         struct dwc3_event_gevt          gevt;
 777 };
 778
 779 /*
 780  * DWC3 Features to be used as Driver Data
 781  */
 782
 783 #define DWC3_HAS_PERIPHERAL             BIT(0)
 784 #define DWC3_HAS_XHCI                   BIT(1)
 785 #define DWC3_HAS_OTG                    BIT(3)
 786
 787 /* prototypes */
 788 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
 789 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
 790
 791 int dwc3_host_init(struct dwc3 *dwc);
 792 void dwc3_host_exit(struct dwc3 *dwc);
 793
 794 int dwc3_gadget_init(struct dwc3 *dwc);
 795 void dwc3_gadget_exit(struct dwc3 *dwc);
 796
 797 extern int dwc3_get_device_id(void);
 798 extern void dwc3_put_device_id(int id);
 799
 800 #endif /* __DRIVERS_USB_DWC3_CORE_H */